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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include "e1000.h"
5#include <linux/ethtool.h>
6
7static s32 e1000_wait_autoneg(struct e1000_hw *hw);
8static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10static u32 e1000_get_phy_addr_for_hv_page(u32 page);
11static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
12 u16 *data, bool read);
13
14/* Cable length tables */
15static const u16 e1000_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
17};
18
19#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
20 ARRAY_SIZE(e1000_m88_cable_length_table)
21
22static const u16 e1000_igp_2_cable_length_table[] = {
23 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
24 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
25 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
26 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
27 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
28 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
29 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 124
31};
32
33#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
34 ARRAY_SIZE(e1000_igp_2_cable_length_table)
35
36/**
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
38 * @hw: pointer to the HW structure
39 *
40 * Read the PHY management control register and check whether a PHY reset
41 * is blocked. If a reset is not blocked return 0, otherwise
42 * return E1000_BLK_PHY_RESET (12).
43 **/
44s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
45{
46 u32 manc;
47
48 manc = er32(MANC);
49
50 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
51}
52
53/**
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
55 * @hw: pointer to the HW structure
56 *
57 * Reads the PHY registers and stores the PHY ID and possibly the PHY
58 * revision in the hardware structure.
59 **/
60s32 e1000e_get_phy_id(struct e1000_hw *hw)
61{
62 struct e1000_phy_info *phy = &hw->phy;
63 s32 ret_val = 0;
64 u16 phy_id;
65 u16 retry_count = 0;
66
67 if (!phy->ops.read_reg)
68 return 0;
69
70 while (retry_count < 2) {
71 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
72 if (ret_val)
73 return ret_val;
74
75 phy->id = (u32)(phy_id << 16);
76 usleep_range(20, 40);
77 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
78 if (ret_val)
79 return ret_val;
80
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
83
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
85 return 0;
86
87 retry_count++;
88 }
89
90 return 0;
91}
92
93/**
94 * e1000e_phy_reset_dsp - Reset PHY DSP
95 * @hw: pointer to the HW structure
96 *
97 * Reset the digital signal processor.
98 **/
99s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
100{
101 s32 ret_val;
102
103 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
104 if (ret_val)
105 return ret_val;
106
107 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
108}
109
110/**
111 * e1000e_read_phy_reg_mdic - Read MDI control register
112 * @hw: pointer to the HW structure
113 * @offset: register offset to be read
114 * @data: pointer to the read data
115 *
116 * Reads the MDI control register in the PHY at offset and stores the
117 * information read to data.
118 **/
119s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
120{
121 struct e1000_phy_info *phy = &hw->phy;
122 u32 i, mdic = 0;
123
124 if (offset > MAX_PHY_REG_ADDRESS) {
125 e_dbg("PHY Address %d is out of range\n", offset);
126 return -E1000_ERR_PARAM;
127 }
128
129 /* Set up Op-code, Phy Address, and register offset in the MDI
130 * Control register. The MAC will take care of interfacing with the
131 * PHY to retrieve the desired data.
132 */
133 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
134 (phy->addr << E1000_MDIC_PHY_SHIFT) |
135 (E1000_MDIC_OP_READ));
136
137 ew32(MDIC, mdic);
138
139 /* Poll the ready bit to see if the MDI read completed
140 * Increasing the time out as testing showed failures with
141 * the lower time out
142 */
143 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
144 udelay(50);
145 mdic = er32(MDIC);
146 if (mdic & E1000_MDIC_READY)
147 break;
148 }
149 if (!(mdic & E1000_MDIC_READY)) {
150 e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
151 return -E1000_ERR_PHY;
152 }
153 if (mdic & E1000_MDIC_ERROR) {
154 e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
155 return -E1000_ERR_PHY;
156 }
157 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
158 e_dbg("MDI Read offset error - requested %d, returned %d\n",
159 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
160 return -E1000_ERR_PHY;
161 }
162 *data = (u16)mdic;
163
164 /* Allow some time after each MDIC transaction to avoid
165 * reading duplicate data in the next MDIC transaction.
166 */
167 if (hw->mac.type == e1000_pch2lan)
168 udelay(100);
169 return 0;
170}
171
172/**
173 * e1000e_write_phy_reg_mdic - Write MDI control register
174 * @hw: pointer to the HW structure
175 * @offset: register offset to write to
176 * @data: data to write to register at offset
177 *
178 * Writes data to MDI control register in the PHY at offset.
179 **/
180s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
181{
182 struct e1000_phy_info *phy = &hw->phy;
183 u32 i, mdic = 0;
184
185 if (offset > MAX_PHY_REG_ADDRESS) {
186 e_dbg("PHY Address %d is out of range\n", offset);
187 return -E1000_ERR_PARAM;
188 }
189
190 /* Set up Op-code, Phy Address, and register offset in the MDI
191 * Control register. The MAC will take care of interfacing with the
192 * PHY to retrieve the desired data.
193 */
194 mdic = (((u32)data) |
195 (offset << E1000_MDIC_REG_SHIFT) |
196 (phy->addr << E1000_MDIC_PHY_SHIFT) |
197 (E1000_MDIC_OP_WRITE));
198
199 ew32(MDIC, mdic);
200
201 /* Poll the ready bit to see if the MDI read completed
202 * Increasing the time out as testing showed failures with
203 * the lower time out
204 */
205 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
206 udelay(50);
207 mdic = er32(MDIC);
208 if (mdic & E1000_MDIC_READY)
209 break;
210 }
211 if (!(mdic & E1000_MDIC_READY)) {
212 e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
213 return -E1000_ERR_PHY;
214 }
215 if (mdic & E1000_MDIC_ERROR) {
216 e_dbg("MDI Write PHY Red Address %d Error\n", offset);
217 return -E1000_ERR_PHY;
218 }
219 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
220 e_dbg("MDI Write offset error - requested %d, returned %d\n",
221 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
222 return -E1000_ERR_PHY;
223 }
224
225 /* Allow some time after each MDIC transaction to avoid
226 * reading duplicate data in the next MDIC transaction.
227 */
228 if (hw->mac.type == e1000_pch2lan)
229 udelay(100);
230
231 return 0;
232}
233
234/**
235 * e1000e_read_phy_reg_m88 - Read m88 PHY register
236 * @hw: pointer to the HW structure
237 * @offset: register offset to be read
238 * @data: pointer to the read data
239 *
240 * Acquires semaphore, if necessary, then reads the PHY register at offset
241 * and storing the retrieved information in data. Release any acquired
242 * semaphores before exiting.
243 **/
244s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
245{
246 s32 ret_val;
247
248 ret_val = hw->phy.ops.acquire(hw);
249 if (ret_val)
250 return ret_val;
251
252 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
253 data);
254
255 hw->phy.ops.release(hw);
256
257 return ret_val;
258}
259
260/**
261 * e1000e_write_phy_reg_m88 - Write m88 PHY register
262 * @hw: pointer to the HW structure
263 * @offset: register offset to write to
264 * @data: data to write at register offset
265 *
266 * Acquires semaphore, if necessary, then writes the data to PHY register
267 * at the offset. Release any acquired semaphores before exiting.
268 **/
269s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
270{
271 s32 ret_val;
272
273 ret_val = hw->phy.ops.acquire(hw);
274 if (ret_val)
275 return ret_val;
276
277 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
278 data);
279
280 hw->phy.ops.release(hw);
281
282 return ret_val;
283}
284
285/**
286 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
287 * @hw: pointer to the HW structure
288 * @page: page to set (shifted left when necessary)
289 *
290 * Sets PHY page required for PHY register access. Assumes semaphore is
291 * already acquired. Note, this function sets phy.addr to 1 so the caller
292 * must set it appropriately (if necessary) after this function returns.
293 **/
294s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
295{
296 e_dbg("Setting page 0x%x\n", page);
297
298 hw->phy.addr = 1;
299
300 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
301}
302
303/**
304 * __e1000e_read_phy_reg_igp - Read igp PHY register
305 * @hw: pointer to the HW structure
306 * @offset: register offset to be read
307 * @data: pointer to the read data
308 * @locked: semaphore has already been acquired or not
309 *
310 * Acquires semaphore, if necessary, then reads the PHY register at offset
311 * and stores the retrieved information in data. Release any acquired
312 * semaphores before exiting.
313 **/
314static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
315 bool locked)
316{
317 s32 ret_val = 0;
318
319 if (!locked) {
320 if (!hw->phy.ops.acquire)
321 return 0;
322
323 ret_val = hw->phy.ops.acquire(hw);
324 if (ret_val)
325 return ret_val;
326 }
327
328 if (offset > MAX_PHY_MULTI_PAGE_REG)
329 ret_val = e1000e_write_phy_reg_mdic(hw,
330 IGP01E1000_PHY_PAGE_SELECT,
331 (u16)offset);
332 if (!ret_val)
333 ret_val = e1000e_read_phy_reg_mdic(hw,
334 MAX_PHY_REG_ADDRESS & offset,
335 data);
336 if (!locked)
337 hw->phy.ops.release(hw);
338
339 return ret_val;
340}
341
342/**
343 * e1000e_read_phy_reg_igp - Read igp PHY register
344 * @hw: pointer to the HW structure
345 * @offset: register offset to be read
346 * @data: pointer to the read data
347 *
348 * Acquires semaphore then reads the PHY register at offset and stores the
349 * retrieved information in data.
350 * Release the acquired semaphore before exiting.
351 **/
352s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
353{
354 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
355}
356
357/**
358 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
359 * @hw: pointer to the HW structure
360 * @offset: register offset to be read
361 * @data: pointer to the read data
362 *
363 * Reads the PHY register at offset and stores the retrieved information
364 * in data. Assumes semaphore already acquired.
365 **/
366s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
367{
368 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
369}
370
371/**
372 * __e1000e_write_phy_reg_igp - Write igp PHY register
373 * @hw: pointer to the HW structure
374 * @offset: register offset to write to
375 * @data: data to write at register offset
376 * @locked: semaphore has already been acquired or not
377 *
378 * Acquires semaphore, if necessary, then writes the data to PHY register
379 * at the offset. Release any acquired semaphores before exiting.
380 **/
381static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
382 bool locked)
383{
384 s32 ret_val = 0;
385
386 if (!locked) {
387 if (!hw->phy.ops.acquire)
388 return 0;
389
390 ret_val = hw->phy.ops.acquire(hw);
391 if (ret_val)
392 return ret_val;
393 }
394
395 if (offset > MAX_PHY_MULTI_PAGE_REG)
396 ret_val = e1000e_write_phy_reg_mdic(hw,
397 IGP01E1000_PHY_PAGE_SELECT,
398 (u16)offset);
399 if (!ret_val)
400 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
401 offset, data);
402 if (!locked)
403 hw->phy.ops.release(hw);
404
405 return ret_val;
406}
407
408/**
409 * e1000e_write_phy_reg_igp - Write igp PHY register
410 * @hw: pointer to the HW structure
411 * @offset: register offset to write to
412 * @data: data to write at register offset
413 *
414 * Acquires semaphore then writes the data to PHY register
415 * at the offset. Release any acquired semaphores before exiting.
416 **/
417s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
418{
419 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
420}
421
422/**
423 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
424 * @hw: pointer to the HW structure
425 * @offset: register offset to write to
426 * @data: data to write at register offset
427 *
428 * Writes the data to PHY register at the offset.
429 * Assumes semaphore already acquired.
430 **/
431s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
432{
433 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
434}
435
436/**
437 * __e1000_read_kmrn_reg - Read kumeran register
438 * @hw: pointer to the HW structure
439 * @offset: register offset to be read
440 * @data: pointer to the read data
441 * @locked: semaphore has already been acquired or not
442 *
443 * Acquires semaphore, if necessary. Then reads the PHY register at offset
444 * using the kumeran interface. The information retrieved is stored in data.
445 * Release any acquired semaphores before exiting.
446 **/
447static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
448 bool locked)
449{
450 u32 kmrnctrlsta;
451
452 if (!locked) {
453 s32 ret_val = 0;
454
455 if (!hw->phy.ops.acquire)
456 return 0;
457
458 ret_val = hw->phy.ops.acquire(hw);
459 if (ret_val)
460 return ret_val;
461 }
462
463 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) |
464 E1000_KMRNCTRLSTA_REN;
465 ew32(KMRNCTRLSTA, kmrnctrlsta);
466 e1e_flush();
467
468 udelay(2);
469
470 kmrnctrlsta = er32(KMRNCTRLSTA);
471 *data = (u16)kmrnctrlsta;
472
473 if (!locked)
474 hw->phy.ops.release(hw);
475
476 return 0;
477}
478
479/**
480 * e1000e_read_kmrn_reg - Read kumeran register
481 * @hw: pointer to the HW structure
482 * @offset: register offset to be read
483 * @data: pointer to the read data
484 *
485 * Acquires semaphore then reads the PHY register at offset using the
486 * kumeran interface. The information retrieved is stored in data.
487 * Release the acquired semaphore before exiting.
488 **/
489s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
490{
491 return __e1000_read_kmrn_reg(hw, offset, data, false);
492}
493
494/**
495 * e1000e_read_kmrn_reg_locked - Read kumeran register
496 * @hw: pointer to the HW structure
497 * @offset: register offset to be read
498 * @data: pointer to the read data
499 *
500 * Reads the PHY register at offset using the kumeran interface. The
501 * information retrieved is stored in data.
502 * Assumes semaphore already acquired.
503 **/
504s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
505{
506 return __e1000_read_kmrn_reg(hw, offset, data, true);
507}
508
509/**
510 * __e1000_write_kmrn_reg - Write kumeran register
511 * @hw: pointer to the HW structure
512 * @offset: register offset to write to
513 * @data: data to write at register offset
514 * @locked: semaphore has already been acquired or not
515 *
516 * Acquires semaphore, if necessary. Then write the data to PHY register
517 * at the offset using the kumeran interface. Release any acquired semaphores
518 * before exiting.
519 **/
520static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
521 bool locked)
522{
523 u32 kmrnctrlsta;
524
525 if (!locked) {
526 s32 ret_val = 0;
527
528 if (!hw->phy.ops.acquire)
529 return 0;
530
531 ret_val = hw->phy.ops.acquire(hw);
532 if (ret_val)
533 return ret_val;
534 }
535
536 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data;
537 ew32(KMRNCTRLSTA, kmrnctrlsta);
538 e1e_flush();
539
540 udelay(2);
541
542 if (!locked)
543 hw->phy.ops.release(hw);
544
545 return 0;
546}
547
548/**
549 * e1000e_write_kmrn_reg - Write kumeran register
550 * @hw: pointer to the HW structure
551 * @offset: register offset to write to
552 * @data: data to write at register offset
553 *
554 * Acquires semaphore then writes the data to the PHY register at the offset
555 * using the kumeran interface. Release the acquired semaphore before exiting.
556 **/
557s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
558{
559 return __e1000_write_kmrn_reg(hw, offset, data, false);
560}
561
562/**
563 * e1000e_write_kmrn_reg_locked - Write kumeran register
564 * @hw: pointer to the HW structure
565 * @offset: register offset to write to
566 * @data: data to write at register offset
567 *
568 * Write the data to PHY register at the offset using the kumeran interface.
569 * Assumes semaphore already acquired.
570 **/
571s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
572{
573 return __e1000_write_kmrn_reg(hw, offset, data, true);
574}
575
576/**
577 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
578 * @hw: pointer to the HW structure
579 *
580 * Sets up Master/slave mode
581 **/
582static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
583{
584 s32 ret_val;
585 u16 phy_data;
586
587 /* Resolve Master/Slave mode */
588 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
589 if (ret_val)
590 return ret_val;
591
592 /* load defaults for future use */
593 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
594 ((phy_data & CTL1000_AS_MASTER) ?
595 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
596
597 switch (hw->phy.ms_type) {
598 case e1000_ms_force_master:
599 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
600 break;
601 case e1000_ms_force_slave:
602 phy_data |= CTL1000_ENABLE_MASTER;
603 phy_data &= ~(CTL1000_AS_MASTER);
604 break;
605 case e1000_ms_auto:
606 phy_data &= ~CTL1000_ENABLE_MASTER;
607 fallthrough;
608 default:
609 break;
610 }
611
612 return e1e_wphy(hw, MII_CTRL1000, phy_data);
613}
614
615/**
616 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
617 * @hw: pointer to the HW structure
618 *
619 * Sets up Carrier-sense on Transmit and downshift values.
620 **/
621s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
622{
623 s32 ret_val;
624 u16 phy_data;
625
626 /* Enable CRS on Tx. This must be set for half-duplex operation. */
627 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
628 if (ret_val)
629 return ret_val;
630
631 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
632
633 /* Enable downshift */
634 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
635
636 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
637 if (ret_val)
638 return ret_val;
639
640 /* Set MDI/MDIX mode */
641 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
642 if (ret_val)
643 return ret_val;
644 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
645 /* Options:
646 * 0 - Auto (default)
647 * 1 - MDI mode
648 * 2 - MDI-X mode
649 */
650 switch (hw->phy.mdix) {
651 case 1:
652 break;
653 case 2:
654 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
655 break;
656 case 0:
657 default:
658 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
659 break;
660 }
661 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
662 if (ret_val)
663 return ret_val;
664
665 return e1000_set_master_slave_mode(hw);
666}
667
668/**
669 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
670 * @hw: pointer to the HW structure
671 *
672 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
673 * and downshift values are set also.
674 **/
675s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
676{
677 struct e1000_phy_info *phy = &hw->phy;
678 s32 ret_val;
679 u16 phy_data;
680
681 /* Enable CRS on Tx. This must be set for half-duplex operation. */
682 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
683 if (ret_val)
684 return ret_val;
685
686 /* For BM PHY this bit is downshift enable */
687 if (phy->type != e1000_phy_bm)
688 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
689
690 /* Options:
691 * MDI/MDI-X = 0 (default)
692 * 0 - Auto for all speeds
693 * 1 - MDI mode
694 * 2 - MDI-X mode
695 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
696 */
697 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
698
699 switch (phy->mdix) {
700 case 1:
701 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
702 break;
703 case 2:
704 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
705 break;
706 case 3:
707 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
708 break;
709 case 0:
710 default:
711 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
712 break;
713 }
714
715 /* Options:
716 * disable_polarity_correction = 0 (default)
717 * Automatic Correction for Reversed Cable Polarity
718 * 0 - Disabled
719 * 1 - Enabled
720 */
721 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
722 if (phy->disable_polarity_correction)
723 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
724
725 /* Enable downshift on BM (disabled by default) */
726 if (phy->type == e1000_phy_bm) {
727 /* For 82574/82583, first disable then enable downshift */
728 if (phy->id == BME1000_E_PHY_ID_R2) {
729 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
730 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
731 phy_data);
732 if (ret_val)
733 return ret_val;
734 /* Commit the changes. */
735 ret_val = phy->ops.commit(hw);
736 if (ret_val) {
737 e_dbg("Error committing the PHY changes\n");
738 return ret_val;
739 }
740 }
741
742 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
743 }
744
745 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
746 if (ret_val)
747 return ret_val;
748
749 if ((phy->type == e1000_phy_m88) &&
750 (phy->revision < E1000_REVISION_4) &&
751 (phy->id != BME1000_E_PHY_ID_R2)) {
752 /* Force TX_CLK in the Extended PHY Specific Control Register
753 * to 25MHz clock.
754 */
755 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
756 if (ret_val)
757 return ret_val;
758
759 phy_data |= M88E1000_EPSCR_TX_CLK_25;
760
761 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
762 /* 82573L PHY - set the downshift counter to 5x. */
763 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
764 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
765 } else {
766 /* Configure Master and Slave downshift values */
767 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
768 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
769 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
770 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
771 }
772 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
773 if (ret_val)
774 return ret_val;
775 }
776
777 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
778 /* Set PHY page 0, register 29 to 0x0003 */
779 ret_val = e1e_wphy(hw, 29, 0x0003);
780 if (ret_val)
781 return ret_val;
782
783 /* Set PHY page 0, register 30 to 0x0000 */
784 ret_val = e1e_wphy(hw, 30, 0x0000);
785 if (ret_val)
786 return ret_val;
787 }
788
789 /* Commit the changes. */
790 if (phy->ops.commit) {
791 ret_val = phy->ops.commit(hw);
792 if (ret_val) {
793 e_dbg("Error committing the PHY changes\n");
794 return ret_val;
795 }
796 }
797
798 if (phy->type == e1000_phy_82578) {
799 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
800 if (ret_val)
801 return ret_val;
802
803 /* 82578 PHY - set the downshift count to 1x. */
804 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
805 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
806 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
807 if (ret_val)
808 return ret_val;
809 }
810
811 return 0;
812}
813
814/**
815 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
816 * @hw: pointer to the HW structure
817 *
818 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
819 * igp PHY's.
820 **/
821s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
822{
823 struct e1000_phy_info *phy = &hw->phy;
824 s32 ret_val;
825 u16 data;
826
827 ret_val = e1000_phy_hw_reset(hw);
828 if (ret_val) {
829 e_dbg("Error resetting the PHY.\n");
830 return ret_val;
831 }
832
833 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
834 * timeout issues when LFS is enabled.
835 */
836 msleep(100);
837
838 /* disable lplu d0 during driver init */
839 if (hw->phy.ops.set_d0_lplu_state) {
840 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
841 if (ret_val) {
842 e_dbg("Error Disabling LPLU D0\n");
843 return ret_val;
844 }
845 }
846 /* Configure mdi-mdix settings */
847 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
848 if (ret_val)
849 return ret_val;
850
851 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
852
853 switch (phy->mdix) {
854 case 1:
855 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
856 break;
857 case 2:
858 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
859 break;
860 case 0:
861 default:
862 data |= IGP01E1000_PSCR_AUTO_MDIX;
863 break;
864 }
865 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
866 if (ret_val)
867 return ret_val;
868
869 /* set auto-master slave resolution settings */
870 if (hw->mac.autoneg) {
871 /* when autonegotiation advertisement is only 1000Mbps then we
872 * should disable SmartSpeed and enable Auto MasterSlave
873 * resolution as hardware default.
874 */
875 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
876 /* Disable SmartSpeed */
877 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
878 &data);
879 if (ret_val)
880 return ret_val;
881
882 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
883 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
884 data);
885 if (ret_val)
886 return ret_val;
887
888 /* Set auto Master/Slave resolution process */
889 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
890 if (ret_val)
891 return ret_val;
892
893 data &= ~CTL1000_ENABLE_MASTER;
894 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
895 if (ret_val)
896 return ret_val;
897 }
898
899 ret_val = e1000_set_master_slave_mode(hw);
900 }
901
902 return ret_val;
903}
904
905/**
906 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
907 * @hw: pointer to the HW structure
908 *
909 * Reads the MII auto-neg advertisement register and/or the 1000T control
910 * register and if the PHY is already setup for auto-negotiation, then
911 * return successful. Otherwise, setup advertisement and flow control to
912 * the appropriate values for the wanted auto-negotiation.
913 **/
914static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
915{
916 struct e1000_phy_info *phy = &hw->phy;
917 s32 ret_val;
918 u16 mii_autoneg_adv_reg;
919 u16 mii_1000t_ctrl_reg = 0;
920
921 phy->autoneg_advertised &= phy->autoneg_mask;
922
923 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
924 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
925 if (ret_val)
926 return ret_val;
927
928 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
929 /* Read the MII 1000Base-T Control Register (Address 9). */
930 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
931 if (ret_val)
932 return ret_val;
933 }
934
935 /* Need to parse both autoneg_advertised and fc and set up
936 * the appropriate PHY registers. First we will parse for
937 * autoneg_advertised software override. Since we can advertise
938 * a plethora of combinations, we need to check each bit
939 * individually.
940 */
941
942 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
943 * Advertisement Register (Address 4) and the 1000 mb speed bits in
944 * the 1000Base-T Control Register (Address 9).
945 */
946 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
947 ADVERTISE_100HALF |
948 ADVERTISE_10FULL | ADVERTISE_10HALF);
949 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
950
951 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
952
953 /* Do we want to advertise 10 Mb Half Duplex? */
954 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
955 e_dbg("Advertise 10mb Half duplex\n");
956 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
957 }
958
959 /* Do we want to advertise 10 Mb Full Duplex? */
960 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
961 e_dbg("Advertise 10mb Full duplex\n");
962 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
963 }
964
965 /* Do we want to advertise 100 Mb Half Duplex? */
966 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
967 e_dbg("Advertise 100mb Half duplex\n");
968 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
969 }
970
971 /* Do we want to advertise 100 Mb Full Duplex? */
972 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
973 e_dbg("Advertise 100mb Full duplex\n");
974 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
975 }
976
977 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
978 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
979 e_dbg("Advertise 1000mb Half duplex request denied!\n");
980
981 /* Do we want to advertise 1000 Mb Full Duplex? */
982 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
983 e_dbg("Advertise 1000mb Full duplex\n");
984 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
985 }
986
987 /* Check for a software override of the flow control settings, and
988 * setup the PHY advertisement registers accordingly. If
989 * auto-negotiation is enabled, then software will have to set the
990 * "PAUSE" bits to the correct value in the Auto-Negotiation
991 * Advertisement Register (MII_ADVERTISE) and re-start auto-
992 * negotiation.
993 *
994 * The possible values of the "fc" parameter are:
995 * 0: Flow control is completely disabled
996 * 1: Rx flow control is enabled (we can receive pause frames
997 * but not send pause frames).
998 * 2: Tx flow control is enabled (we can send pause frames
999 * but we do not support receiving pause frames).
1000 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1001 * other: No software override. The flow control configuration
1002 * in the EEPROM is used.
1003 */
1004 switch (hw->fc.current_mode) {
1005 case e1000_fc_none:
1006 /* Flow control (Rx & Tx) is completely disabled by a
1007 * software over-ride.
1008 */
1009 mii_autoneg_adv_reg &=
1010 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1011 phy->autoneg_advertised &=
1012 ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1013 break;
1014 case e1000_fc_rx_pause:
1015 /* Rx Flow control is enabled, and Tx Flow control is
1016 * disabled, by a software over-ride.
1017 *
1018 * Since there really isn't a way to advertise that we are
1019 * capable of Rx Pause ONLY, we will advertise that we
1020 * support both symmetric and asymmetric Rx PAUSE. Later
1021 * (in e1000e_config_fc_after_link_up) we will disable the
1022 * hw's ability to send PAUSE frames.
1023 */
1024 mii_autoneg_adv_reg |=
1025 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1026 phy->autoneg_advertised |=
1027 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1028 break;
1029 case e1000_fc_tx_pause:
1030 /* Tx Flow control is enabled, and Rx Flow control is
1031 * disabled, by a software over-ride.
1032 */
1033 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1034 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1035 phy->autoneg_advertised |= ADVERTISED_Asym_Pause;
1036 phy->autoneg_advertised &= ~ADVERTISED_Pause;
1037 break;
1038 case e1000_fc_full:
1039 /* Flow control (both Rx and Tx) is enabled by a software
1040 * over-ride.
1041 */
1042 mii_autoneg_adv_reg |=
1043 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1044 phy->autoneg_advertised |=
1045 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1046 break;
1047 default:
1048 e_dbg("Flow control param set incorrectly\n");
1049 return -E1000_ERR_CONFIG;
1050 }
1051
1052 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1053 if (ret_val)
1054 return ret_val;
1055
1056 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1057
1058 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1059 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1060
1061 return ret_val;
1062}
1063
1064/**
1065 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1066 * @hw: pointer to the HW structure
1067 *
1068 * Performs initial bounds checking on autoneg advertisement parameter, then
1069 * configure to advertise the full capability. Setup the PHY to autoneg
1070 * and restart the negotiation process between the link partner. If
1071 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1072 **/
1073static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1074{
1075 struct e1000_phy_info *phy = &hw->phy;
1076 s32 ret_val;
1077 u16 phy_ctrl;
1078
1079 /* Perform some bounds checking on the autoneg advertisement
1080 * parameter.
1081 */
1082 phy->autoneg_advertised &= phy->autoneg_mask;
1083
1084 /* If autoneg_advertised is zero, we assume it was not defaulted
1085 * by the calling code so we set to advertise full capability.
1086 */
1087 if (!phy->autoneg_advertised)
1088 phy->autoneg_advertised = phy->autoneg_mask;
1089
1090 e_dbg("Reconfiguring auto-neg advertisement params\n");
1091 ret_val = e1000_phy_setup_autoneg(hw);
1092 if (ret_val) {
1093 e_dbg("Error Setting up Auto-Negotiation\n");
1094 return ret_val;
1095 }
1096 e_dbg("Restarting Auto-Neg\n");
1097
1098 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1099 * the Auto Neg Restart bit in the PHY control register.
1100 */
1101 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1102 if (ret_val)
1103 return ret_val;
1104
1105 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1106 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1107 if (ret_val)
1108 return ret_val;
1109
1110 /* Does the user want to wait for Auto-Neg to complete here, or
1111 * check at a later time (for example, callback routine).
1112 */
1113 if (phy->autoneg_wait_to_complete) {
1114 ret_val = e1000_wait_autoneg(hw);
1115 if (ret_val) {
1116 e_dbg("Error while waiting for autoneg to complete\n");
1117 return ret_val;
1118 }
1119 }
1120
1121 hw->mac.get_link_status = true;
1122
1123 return ret_val;
1124}
1125
1126/**
1127 * e1000e_setup_copper_link - Configure copper link settings
1128 * @hw: pointer to the HW structure
1129 *
1130 * Calls the appropriate function to configure the link for auto-neg or forced
1131 * speed and duplex. Then we check for link, once link is established calls
1132 * to configure collision distance and flow control are called. If link is
1133 * not established, we return -E1000_ERR_PHY (-2).
1134 **/
1135s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1136{
1137 s32 ret_val;
1138 bool link;
1139
1140 if (hw->mac.autoneg) {
1141 /* Setup autoneg and flow control advertisement and perform
1142 * autonegotiation.
1143 */
1144 ret_val = e1000_copper_link_autoneg(hw);
1145 if (ret_val)
1146 return ret_val;
1147 } else {
1148 /* PHY will be set to 10H, 10F, 100H or 100F
1149 * depending on user settings.
1150 */
1151 e_dbg("Forcing Speed and Duplex\n");
1152 ret_val = hw->phy.ops.force_speed_duplex(hw);
1153 if (ret_val) {
1154 e_dbg("Error Forcing Speed and Duplex\n");
1155 return ret_val;
1156 }
1157 }
1158
1159 /* Check link status. Wait up to 100 microseconds for link to become
1160 * valid.
1161 */
1162 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1163 &link);
1164 if (ret_val)
1165 return ret_val;
1166
1167 if (link) {
1168 e_dbg("Valid link established!!!\n");
1169 hw->mac.ops.config_collision_dist(hw);
1170 ret_val = e1000e_config_fc_after_link_up(hw);
1171 } else {
1172 e_dbg("Unable to establish link!!!\n");
1173 }
1174
1175 return ret_val;
1176}
1177
1178/**
1179 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1180 * @hw: pointer to the HW structure
1181 *
1182 * Calls the PHY setup function to force speed and duplex. Clears the
1183 * auto-crossover to force MDI manually. Waits for link and returns
1184 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1185 **/
1186s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1187{
1188 struct e1000_phy_info *phy = &hw->phy;
1189 s32 ret_val;
1190 u16 phy_data;
1191 bool link;
1192
1193 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1194 if (ret_val)
1195 return ret_val;
1196
1197 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1198
1199 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1200 if (ret_val)
1201 return ret_val;
1202
1203 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1204 * forced whenever speed and duplex are forced.
1205 */
1206 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1207 if (ret_val)
1208 return ret_val;
1209
1210 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1211 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1212
1213 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1214 if (ret_val)
1215 return ret_val;
1216
1217 e_dbg("IGP PSCR: %X\n", phy_data);
1218
1219 udelay(1);
1220
1221 if (phy->autoneg_wait_to_complete) {
1222 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1223
1224 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1225 100000, &link);
1226 if (ret_val)
1227 return ret_val;
1228
1229 if (!link)
1230 e_dbg("Link taking longer than expected.\n");
1231
1232 /* Try once more */
1233 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1234 100000, &link);
1235 }
1236
1237 return ret_val;
1238}
1239
1240/**
1241 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1242 * @hw: pointer to the HW structure
1243 *
1244 * Calls the PHY setup function to force speed and duplex. Clears the
1245 * auto-crossover to force MDI manually. Resets the PHY to commit the
1246 * changes. If time expires while waiting for link up, we reset the DSP.
1247 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1248 * successful completion, else return corresponding error code.
1249 **/
1250s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1251{
1252 struct e1000_phy_info *phy = &hw->phy;
1253 s32 ret_val;
1254 u16 phy_data;
1255 bool link;
1256
1257 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1258 * forced whenever speed and duplex are forced.
1259 */
1260 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1261 if (ret_val)
1262 return ret_val;
1263
1264 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1265 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1266 if (ret_val)
1267 return ret_val;
1268
1269 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1270
1271 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1272 if (ret_val)
1273 return ret_val;
1274
1275 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1276
1277 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1278 if (ret_val)
1279 return ret_val;
1280
1281 /* Reset the phy to commit changes. */
1282 if (hw->phy.ops.commit) {
1283 ret_val = hw->phy.ops.commit(hw);
1284 if (ret_val)
1285 return ret_val;
1286 }
1287
1288 if (phy->autoneg_wait_to_complete) {
1289 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1290
1291 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1292 100000, &link);
1293 if (ret_val)
1294 return ret_val;
1295
1296 if (!link) {
1297 if (hw->phy.type != e1000_phy_m88) {
1298 e_dbg("Link taking longer than expected.\n");
1299 } else {
1300 /* We didn't get link.
1301 * Reset the DSP and cross our fingers.
1302 */
1303 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1304 0x001d);
1305 if (ret_val)
1306 return ret_val;
1307 ret_val = e1000e_phy_reset_dsp(hw);
1308 if (ret_val)
1309 return ret_val;
1310 }
1311 }
1312
1313 /* Try once more */
1314 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1315 100000, &link);
1316 if (ret_val)
1317 return ret_val;
1318 }
1319
1320 if (hw->phy.type != e1000_phy_m88)
1321 return 0;
1322
1323 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1324 if (ret_val)
1325 return ret_val;
1326
1327 /* Resetting the phy means we need to re-force TX_CLK in the
1328 * Extended PHY Specific Control Register to 25MHz clock from
1329 * the reset value of 2.5MHz.
1330 */
1331 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1332 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1333 if (ret_val)
1334 return ret_val;
1335
1336 /* In addition, we must re-enable CRS on Tx for both half and full
1337 * duplex.
1338 */
1339 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1340 if (ret_val)
1341 return ret_val;
1342
1343 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1344 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1345
1346 return ret_val;
1347}
1348
1349/**
1350 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1351 * @hw: pointer to the HW structure
1352 *
1353 * Forces the speed and duplex settings of the PHY.
1354 * This is a function pointer entry point only called by
1355 * PHY setup routines.
1356 **/
1357s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1358{
1359 struct e1000_phy_info *phy = &hw->phy;
1360 s32 ret_val;
1361 u16 data;
1362 bool link;
1363
1364 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1365 if (ret_val)
1366 return ret_val;
1367
1368 e1000e_phy_force_speed_duplex_setup(hw, &data);
1369
1370 ret_val = e1e_wphy(hw, MII_BMCR, data);
1371 if (ret_val)
1372 return ret_val;
1373
1374 /* Disable MDI-X support for 10/100 */
1375 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1376 if (ret_val)
1377 return ret_val;
1378
1379 data &= ~IFE_PMC_AUTO_MDIX;
1380 data &= ~IFE_PMC_FORCE_MDIX;
1381
1382 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1383 if (ret_val)
1384 return ret_val;
1385
1386 e_dbg("IFE PMC: %X\n", data);
1387
1388 udelay(1);
1389
1390 if (phy->autoneg_wait_to_complete) {
1391 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1392
1393 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1394 100000, &link);
1395 if (ret_val)
1396 return ret_val;
1397
1398 if (!link)
1399 e_dbg("Link taking longer than expected.\n");
1400
1401 /* Try once more */
1402 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1403 100000, &link);
1404 if (ret_val)
1405 return ret_val;
1406 }
1407
1408 return 0;
1409}
1410
1411/**
1412 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1413 * @hw: pointer to the HW structure
1414 * @phy_ctrl: pointer to current value of MII_BMCR
1415 *
1416 * Forces speed and duplex on the PHY by doing the following: disable flow
1417 * control, force speed/duplex on the MAC, disable auto speed detection,
1418 * disable auto-negotiation, configure duplex, configure speed, configure
1419 * the collision distance, write configuration to CTRL register. The
1420 * caller must write to the MII_BMCR register for these settings to
1421 * take affect.
1422 **/
1423void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1424{
1425 struct e1000_mac_info *mac = &hw->mac;
1426 u32 ctrl;
1427
1428 /* Turn off flow control when forcing speed/duplex */
1429 hw->fc.current_mode = e1000_fc_none;
1430
1431 /* Force speed/duplex on the mac */
1432 ctrl = er32(CTRL);
1433 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1434 ctrl &= ~E1000_CTRL_SPD_SEL;
1435
1436 /* Disable Auto Speed Detection */
1437 ctrl &= ~E1000_CTRL_ASDE;
1438
1439 /* Disable autoneg on the phy */
1440 *phy_ctrl &= ~BMCR_ANENABLE;
1441
1442 /* Forcing Full or Half Duplex? */
1443 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1444 ctrl &= ~E1000_CTRL_FD;
1445 *phy_ctrl &= ~BMCR_FULLDPLX;
1446 e_dbg("Half Duplex\n");
1447 } else {
1448 ctrl |= E1000_CTRL_FD;
1449 *phy_ctrl |= BMCR_FULLDPLX;
1450 e_dbg("Full Duplex\n");
1451 }
1452
1453 /* Forcing 10mb or 100mb? */
1454 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1455 ctrl |= E1000_CTRL_SPD_100;
1456 *phy_ctrl |= BMCR_SPEED100;
1457 *phy_ctrl &= ~BMCR_SPEED1000;
1458 e_dbg("Forcing 100mb\n");
1459 } else {
1460 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1461 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1462 e_dbg("Forcing 10mb\n");
1463 }
1464
1465 hw->mac.ops.config_collision_dist(hw);
1466
1467 ew32(CTRL, ctrl);
1468}
1469
1470/**
1471 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1472 * @hw: pointer to the HW structure
1473 * @active: boolean used to enable/disable lplu
1474 *
1475 * Success returns 0, Failure returns 1
1476 *
1477 * The low power link up (lplu) state is set to the power management level D3
1478 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1479 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1480 * is used during Dx states where the power conservation is most important.
1481 * During driver activity, SmartSpeed should be enabled so performance is
1482 * maintained.
1483 **/
1484s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1485{
1486 struct e1000_phy_info *phy = &hw->phy;
1487 s32 ret_val;
1488 u16 data;
1489
1490 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1491 if (ret_val)
1492 return ret_val;
1493
1494 if (!active) {
1495 data &= ~IGP02E1000_PM_D3_LPLU;
1496 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1497 if (ret_val)
1498 return ret_val;
1499 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1500 * during Dx states where the power conservation is most
1501 * important. During driver activity we should enable
1502 * SmartSpeed, so performance is maintained.
1503 */
1504 if (phy->smart_speed == e1000_smart_speed_on) {
1505 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1506 &data);
1507 if (ret_val)
1508 return ret_val;
1509
1510 data |= IGP01E1000_PSCFR_SMART_SPEED;
1511 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1512 data);
1513 if (ret_val)
1514 return ret_val;
1515 } else if (phy->smart_speed == e1000_smart_speed_off) {
1516 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1517 &data);
1518 if (ret_val)
1519 return ret_val;
1520
1521 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1522 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1523 data);
1524 if (ret_val)
1525 return ret_val;
1526 }
1527 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1528 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1529 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1530 data |= IGP02E1000_PM_D3_LPLU;
1531 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 /* When LPLU is enabled, we should disable SmartSpeed */
1536 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1537 if (ret_val)
1538 return ret_val;
1539
1540 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1541 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1542 }
1543
1544 return ret_val;
1545}
1546
1547/**
1548 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1549 * @hw: pointer to the HW structure
1550 *
1551 * Success returns 0, Failure returns 1
1552 *
1553 * A downshift is detected by querying the PHY link health.
1554 **/
1555s32 e1000e_check_downshift(struct e1000_hw *hw)
1556{
1557 struct e1000_phy_info *phy = &hw->phy;
1558 s32 ret_val;
1559 u16 phy_data, offset, mask;
1560
1561 switch (phy->type) {
1562 case e1000_phy_m88:
1563 case e1000_phy_gg82563:
1564 case e1000_phy_bm:
1565 case e1000_phy_82578:
1566 offset = M88E1000_PHY_SPEC_STATUS;
1567 mask = M88E1000_PSSR_DOWNSHIFT;
1568 break;
1569 case e1000_phy_igp_2:
1570 case e1000_phy_igp_3:
1571 offset = IGP01E1000_PHY_LINK_HEALTH;
1572 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1573 break;
1574 default:
1575 /* speed downshift not supported */
1576 phy->speed_downgraded = false;
1577 return 0;
1578 }
1579
1580 ret_val = e1e_rphy(hw, offset, &phy_data);
1581
1582 if (!ret_val)
1583 phy->speed_downgraded = !!(phy_data & mask);
1584
1585 return ret_val;
1586}
1587
1588/**
1589 * e1000_check_polarity_m88 - Checks the polarity.
1590 * @hw: pointer to the HW structure
1591 *
1592 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1593 *
1594 * Polarity is determined based on the PHY specific status register.
1595 **/
1596s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1597{
1598 struct e1000_phy_info *phy = &hw->phy;
1599 s32 ret_val;
1600 u16 data;
1601
1602 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1603
1604 if (!ret_val)
1605 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1606 ? e1000_rev_polarity_reversed
1607 : e1000_rev_polarity_normal);
1608
1609 return ret_val;
1610}
1611
1612/**
1613 * e1000_check_polarity_igp - Checks the polarity.
1614 * @hw: pointer to the HW structure
1615 *
1616 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1617 *
1618 * Polarity is determined based on the PHY port status register, and the
1619 * current speed (since there is no polarity at 100Mbps).
1620 **/
1621s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1622{
1623 struct e1000_phy_info *phy = &hw->phy;
1624 s32 ret_val;
1625 u16 data, offset, mask;
1626
1627 /* Polarity is determined based on the speed of
1628 * our connection.
1629 */
1630 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1631 if (ret_val)
1632 return ret_val;
1633
1634 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1635 IGP01E1000_PSSR_SPEED_1000MBPS) {
1636 offset = IGP01E1000_PHY_PCS_INIT_REG;
1637 mask = IGP01E1000_PHY_POLARITY_MASK;
1638 } else {
1639 /* This really only applies to 10Mbps since
1640 * there is no polarity for 100Mbps (always 0).
1641 */
1642 offset = IGP01E1000_PHY_PORT_STATUS;
1643 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1644 }
1645
1646 ret_val = e1e_rphy(hw, offset, &data);
1647
1648 if (!ret_val)
1649 phy->cable_polarity = ((data & mask)
1650 ? e1000_rev_polarity_reversed
1651 : e1000_rev_polarity_normal);
1652
1653 return ret_val;
1654}
1655
1656/**
1657 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1658 * @hw: pointer to the HW structure
1659 *
1660 * Polarity is determined on the polarity reversal feature being enabled.
1661 **/
1662s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1663{
1664 struct e1000_phy_info *phy = &hw->phy;
1665 s32 ret_val;
1666 u16 phy_data, offset, mask;
1667
1668 /* Polarity is determined based on the reversal feature being enabled.
1669 */
1670 if (phy->polarity_correction) {
1671 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1672 mask = IFE_PESC_POLARITY_REVERSED;
1673 } else {
1674 offset = IFE_PHY_SPECIAL_CONTROL;
1675 mask = IFE_PSC_FORCE_POLARITY;
1676 }
1677
1678 ret_val = e1e_rphy(hw, offset, &phy_data);
1679
1680 if (!ret_val)
1681 phy->cable_polarity = ((phy_data & mask)
1682 ? e1000_rev_polarity_reversed
1683 : e1000_rev_polarity_normal);
1684
1685 return ret_val;
1686}
1687
1688/**
1689 * e1000_wait_autoneg - Wait for auto-neg completion
1690 * @hw: pointer to the HW structure
1691 *
1692 * Waits for auto-negotiation to complete or for the auto-negotiation time
1693 * limit to expire, which ever happens first.
1694 **/
1695static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1696{
1697 s32 ret_val = 0;
1698 u16 i, phy_status;
1699
1700 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1701 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1702 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1703 if (ret_val)
1704 break;
1705 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1706 if (ret_val)
1707 break;
1708 if (phy_status & BMSR_ANEGCOMPLETE)
1709 break;
1710 msleep(100);
1711 }
1712
1713 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1714 * has completed.
1715 */
1716 return ret_val;
1717}
1718
1719/**
1720 * e1000e_phy_has_link_generic - Polls PHY for link
1721 * @hw: pointer to the HW structure
1722 * @iterations: number of times to poll for link
1723 * @usec_interval: delay between polling attempts
1724 * @success: pointer to whether polling was successful or not
1725 *
1726 * Polls the PHY status register for link, 'iterations' number of times.
1727 **/
1728s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1729 u32 usec_interval, bool *success)
1730{
1731 s32 ret_val = 0;
1732 u16 i, phy_status;
1733
1734 *success = false;
1735 for (i = 0; i < iterations; i++) {
1736 /* Some PHYs require the MII_BMSR register to be read
1737 * twice due to the link bit being sticky. No harm doing
1738 * it across the board.
1739 */
1740 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1741 if (ret_val) {
1742 /* If the first read fails, another entity may have
1743 * ownership of the resources, wait and try again to
1744 * see if they have relinquished the resources yet.
1745 */
1746 if (usec_interval >= 1000)
1747 msleep(usec_interval / 1000);
1748 else
1749 udelay(usec_interval);
1750 }
1751 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1752 if (ret_val)
1753 break;
1754 if (phy_status & BMSR_LSTATUS) {
1755 *success = true;
1756 break;
1757 }
1758 if (usec_interval >= 1000)
1759 msleep(usec_interval / 1000);
1760 else
1761 udelay(usec_interval);
1762 }
1763
1764 return ret_val;
1765}
1766
1767/**
1768 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1769 * @hw: pointer to the HW structure
1770 *
1771 * Reads the PHY specific status register to retrieve the cable length
1772 * information. The cable length is determined by averaging the minimum and
1773 * maximum values to get the "average" cable length. The m88 PHY has four
1774 * possible cable length values, which are:
1775 * Register Value Cable Length
1776 * 0 < 50 meters
1777 * 1 50 - 80 meters
1778 * 2 80 - 110 meters
1779 * 3 110 - 140 meters
1780 * 4 > 140 meters
1781 **/
1782s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1783{
1784 struct e1000_phy_info *phy = &hw->phy;
1785 s32 ret_val;
1786 u16 phy_data, index;
1787
1788 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1789 if (ret_val)
1790 return ret_val;
1791
1792 index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);
1793
1794 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1795 return -E1000_ERR_PHY;
1796
1797 phy->min_cable_length = e1000_m88_cable_length_table[index];
1798 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1799
1800 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1801
1802 return 0;
1803}
1804
1805/**
1806 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1807 * @hw: pointer to the HW structure
1808 *
1809 * The automatic gain control (agc) normalizes the amplitude of the
1810 * received signal, adjusting for the attenuation produced by the
1811 * cable. By reading the AGC registers, which represent the
1812 * combination of coarse and fine gain value, the value can be put
1813 * into a lookup table to obtain the approximate cable length
1814 * for each channel.
1815 **/
1816s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1817{
1818 struct e1000_phy_info *phy = &hw->phy;
1819 s32 ret_val;
1820 u16 phy_data, i, agc_value = 0;
1821 u16 cur_agc_index, max_agc_index = 0;
1822 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1823 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1824 IGP02E1000_PHY_AGC_A,
1825 IGP02E1000_PHY_AGC_B,
1826 IGP02E1000_PHY_AGC_C,
1827 IGP02E1000_PHY_AGC_D
1828 };
1829
1830 /* Read the AGC registers for all channels */
1831 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1832 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1833 if (ret_val)
1834 return ret_val;
1835
1836 /* Getting bits 15:9, which represent the combination of
1837 * coarse and fine gain values. The result is a number
1838 * that can be put into the lookup table to obtain the
1839 * approximate cable length.
1840 */
1841 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1842 IGP02E1000_AGC_LENGTH_MASK);
1843
1844 /* Array index bound check. */
1845 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1846 (cur_agc_index == 0))
1847 return -E1000_ERR_PHY;
1848
1849 /* Remove min & max AGC values from calculation. */
1850 if (e1000_igp_2_cable_length_table[min_agc_index] >
1851 e1000_igp_2_cable_length_table[cur_agc_index])
1852 min_agc_index = cur_agc_index;
1853 if (e1000_igp_2_cable_length_table[max_agc_index] <
1854 e1000_igp_2_cable_length_table[cur_agc_index])
1855 max_agc_index = cur_agc_index;
1856
1857 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1858 }
1859
1860 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1861 e1000_igp_2_cable_length_table[max_agc_index]);
1862 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1863
1864 /* Calculate cable length with the error range of +/- 10 meters. */
1865 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1866 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1867 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1868
1869 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1870
1871 return 0;
1872}
1873
1874/**
1875 * e1000e_get_phy_info_m88 - Retrieve PHY information
1876 * @hw: pointer to the HW structure
1877 *
1878 * Valid for only copper links. Read the PHY status register (sticky read)
1879 * to verify that link is up. Read the PHY special control register to
1880 * determine the polarity and 10base-T extended distance. Read the PHY
1881 * special status register to determine MDI/MDIx and current speed. If
1882 * speed is 1000, then determine cable length, local and remote receiver.
1883 **/
1884s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1885{
1886 struct e1000_phy_info *phy = &hw->phy;
1887 s32 ret_val;
1888 u16 phy_data;
1889 bool link;
1890
1891 if (phy->media_type != e1000_media_type_copper) {
1892 e_dbg("Phy info is only valid for copper media\n");
1893 return -E1000_ERR_CONFIG;
1894 }
1895
1896 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1897 if (ret_val)
1898 return ret_val;
1899
1900 if (!link) {
1901 e_dbg("Phy info is only valid if link is up\n");
1902 return -E1000_ERR_CONFIG;
1903 }
1904
1905 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1906 if (ret_val)
1907 return ret_val;
1908
1909 phy->polarity_correction = !!(phy_data &
1910 M88E1000_PSCR_POLARITY_REVERSAL);
1911
1912 ret_val = e1000_check_polarity_m88(hw);
1913 if (ret_val)
1914 return ret_val;
1915
1916 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1917 if (ret_val)
1918 return ret_val;
1919
1920 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1921
1922 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1923 ret_val = hw->phy.ops.get_cable_length(hw);
1924 if (ret_val)
1925 return ret_val;
1926
1927 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1928 if (ret_val)
1929 return ret_val;
1930
1931 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1932 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1933
1934 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1935 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1936 } else {
1937 /* Set values to "undefined" */
1938 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1939 phy->local_rx = e1000_1000t_rx_status_undefined;
1940 phy->remote_rx = e1000_1000t_rx_status_undefined;
1941 }
1942
1943 return ret_val;
1944}
1945
1946/**
1947 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1948 * @hw: pointer to the HW structure
1949 *
1950 * Read PHY status to determine if link is up. If link is up, then
1951 * set/determine 10base-T extended distance and polarity correction. Read
1952 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1953 * determine on the cable length, local and remote receiver.
1954 **/
1955s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1956{
1957 struct e1000_phy_info *phy = &hw->phy;
1958 s32 ret_val;
1959 u16 data;
1960 bool link;
1961
1962 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1963 if (ret_val)
1964 return ret_val;
1965
1966 if (!link) {
1967 e_dbg("Phy info is only valid if link is up\n");
1968 return -E1000_ERR_CONFIG;
1969 }
1970
1971 phy->polarity_correction = true;
1972
1973 ret_val = e1000_check_polarity_igp(hw);
1974 if (ret_val)
1975 return ret_val;
1976
1977 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1978 if (ret_val)
1979 return ret_val;
1980
1981 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1982
1983 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1984 IGP01E1000_PSSR_SPEED_1000MBPS) {
1985 ret_val = phy->ops.get_cable_length(hw);
1986 if (ret_val)
1987 return ret_val;
1988
1989 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
1990 if (ret_val)
1991 return ret_val;
1992
1993 phy->local_rx = (data & LPA_1000LOCALRXOK)
1994 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1995
1996 phy->remote_rx = (data & LPA_1000REMRXOK)
1997 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1998 } else {
1999 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2000 phy->local_rx = e1000_1000t_rx_status_undefined;
2001 phy->remote_rx = e1000_1000t_rx_status_undefined;
2002 }
2003
2004 return ret_val;
2005}
2006
2007/**
2008 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2009 * @hw: pointer to the HW structure
2010 *
2011 * Populates "phy" structure with various feature states.
2012 **/
2013s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2014{
2015 struct e1000_phy_info *phy = &hw->phy;
2016 s32 ret_val;
2017 u16 data;
2018 bool link;
2019
2020 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2021 if (ret_val)
2022 return ret_val;
2023
2024 if (!link) {
2025 e_dbg("Phy info is only valid if link is up\n");
2026 return -E1000_ERR_CONFIG;
2027 }
2028
2029 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2030 if (ret_val)
2031 return ret_val;
2032 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2033
2034 if (phy->polarity_correction) {
2035 ret_val = e1000_check_polarity_ife(hw);
2036 if (ret_val)
2037 return ret_val;
2038 } else {
2039 /* Polarity is forced */
2040 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2041 ? e1000_rev_polarity_reversed
2042 : e1000_rev_polarity_normal);
2043 }
2044
2045 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2046 if (ret_val)
2047 return ret_val;
2048
2049 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2050
2051 /* The following parameters are undefined for 10/100 operation. */
2052 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2053 phy->local_rx = e1000_1000t_rx_status_undefined;
2054 phy->remote_rx = e1000_1000t_rx_status_undefined;
2055
2056 return 0;
2057}
2058
2059/**
2060 * e1000e_phy_sw_reset - PHY software reset
2061 * @hw: pointer to the HW structure
2062 *
2063 * Does a software reset of the PHY by reading the PHY control register and
2064 * setting/write the control register reset bit to the PHY.
2065 **/
2066s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2067{
2068 s32 ret_val;
2069 u16 phy_ctrl;
2070
2071 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2072 if (ret_val)
2073 return ret_val;
2074
2075 phy_ctrl |= BMCR_RESET;
2076 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2077 if (ret_val)
2078 return ret_val;
2079
2080 udelay(1);
2081
2082 return ret_val;
2083}
2084
2085/**
2086 * e1000e_phy_hw_reset_generic - PHY hardware reset
2087 * @hw: pointer to the HW structure
2088 *
2089 * Verify the reset block is not blocking us from resetting. Acquire
2090 * semaphore (if necessary) and read/set/write the device control reset
2091 * bit in the PHY. Wait the appropriate delay time for the device to
2092 * reset and release the semaphore (if necessary).
2093 **/
2094s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2095{
2096 struct e1000_phy_info *phy = &hw->phy;
2097 s32 ret_val;
2098 u32 ctrl;
2099
2100 if (phy->ops.check_reset_block) {
2101 ret_val = phy->ops.check_reset_block(hw);
2102 if (ret_val)
2103 return 0;
2104 }
2105
2106 ret_val = phy->ops.acquire(hw);
2107 if (ret_val)
2108 return ret_val;
2109
2110 ctrl = er32(CTRL);
2111 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2112 e1e_flush();
2113
2114 udelay(phy->reset_delay_us);
2115
2116 ew32(CTRL, ctrl);
2117 e1e_flush();
2118
2119 usleep_range(150, 300);
2120
2121 phy->ops.release(hw);
2122
2123 return phy->ops.get_cfg_done(hw);
2124}
2125
2126/**
2127 * e1000e_get_cfg_done_generic - Generic configuration done
2128 * @hw: pointer to the HW structure
2129 *
2130 * Generic function to wait 10 milli-seconds for configuration to complete
2131 * and return success.
2132 **/
2133s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2134{
2135 mdelay(10);
2136
2137 return 0;
2138}
2139
2140/**
2141 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2142 * @hw: pointer to the HW structure
2143 *
2144 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2145 **/
2146s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2147{
2148 e_dbg("Running IGP 3 PHY init script\n");
2149
2150 /* PHY init IGP 3 */
2151 /* Enable rise/fall, 10-mode work in class-A */
2152 e1e_wphy(hw, 0x2F5B, 0x9018);
2153 /* Remove all caps from Replica path filter */
2154 e1e_wphy(hw, 0x2F52, 0x0000);
2155 /* Bias trimming for ADC, AFE and Driver (Default) */
2156 e1e_wphy(hw, 0x2FB1, 0x8B24);
2157 /* Increase Hybrid poly bias */
2158 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2159 /* Add 4% to Tx amplitude in Gig mode */
2160 e1e_wphy(hw, 0x2010, 0x10B0);
2161 /* Disable trimming (TTT) */
2162 e1e_wphy(hw, 0x2011, 0x0000);
2163 /* Poly DC correction to 94.6% + 2% for all channels */
2164 e1e_wphy(hw, 0x20DD, 0x249A);
2165 /* ABS DC correction to 95.9% */
2166 e1e_wphy(hw, 0x20DE, 0x00D3);
2167 /* BG temp curve trim */
2168 e1e_wphy(hw, 0x28B4, 0x04CE);
2169 /* Increasing ADC OPAMP stage 1 currents to max */
2170 e1e_wphy(hw, 0x2F70, 0x29E4);
2171 /* Force 1000 ( required for enabling PHY regs configuration) */
2172 e1e_wphy(hw, 0x0000, 0x0140);
2173 /* Set upd_freq to 6 */
2174 e1e_wphy(hw, 0x1F30, 0x1606);
2175 /* Disable NPDFE */
2176 e1e_wphy(hw, 0x1F31, 0xB814);
2177 /* Disable adaptive fixed FFE (Default) */
2178 e1e_wphy(hw, 0x1F35, 0x002A);
2179 /* Enable FFE hysteresis */
2180 e1e_wphy(hw, 0x1F3E, 0x0067);
2181 /* Fixed FFE for short cable lengths */
2182 e1e_wphy(hw, 0x1F54, 0x0065);
2183 /* Fixed FFE for medium cable lengths */
2184 e1e_wphy(hw, 0x1F55, 0x002A);
2185 /* Fixed FFE for long cable lengths */
2186 e1e_wphy(hw, 0x1F56, 0x002A);
2187 /* Enable Adaptive Clip Threshold */
2188 e1e_wphy(hw, 0x1F72, 0x3FB0);
2189 /* AHT reset limit to 1 */
2190 e1e_wphy(hw, 0x1F76, 0xC0FF);
2191 /* Set AHT master delay to 127 msec */
2192 e1e_wphy(hw, 0x1F77, 0x1DEC);
2193 /* Set scan bits for AHT */
2194 e1e_wphy(hw, 0x1F78, 0xF9EF);
2195 /* Set AHT Preset bits */
2196 e1e_wphy(hw, 0x1F79, 0x0210);
2197 /* Change integ_factor of channel A to 3 */
2198 e1e_wphy(hw, 0x1895, 0x0003);
2199 /* Change prop_factor of channels BCD to 8 */
2200 e1e_wphy(hw, 0x1796, 0x0008);
2201 /* Change cg_icount + enable integbp for channels BCD */
2202 e1e_wphy(hw, 0x1798, 0xD008);
2203 /* Change cg_icount + enable integbp + change prop_factor_master
2204 * to 8 for channel A
2205 */
2206 e1e_wphy(hw, 0x1898, 0xD918);
2207 /* Disable AHT in Slave mode on channel A */
2208 e1e_wphy(hw, 0x187A, 0x0800);
2209 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2210 * Enable SPD+B2B
2211 */
2212 e1e_wphy(hw, 0x0019, 0x008D);
2213 /* Enable restart AN on an1000_dis change */
2214 e1e_wphy(hw, 0x001B, 0x2080);
2215 /* Enable wh_fifo read clock in 10/100 modes */
2216 e1e_wphy(hw, 0x0014, 0x0045);
2217 /* Restart AN, Speed selection is 1000 */
2218 e1e_wphy(hw, 0x0000, 0x1340);
2219
2220 return 0;
2221}
2222
2223/**
2224 * e1000e_get_phy_type_from_id - Get PHY type from id
2225 * @phy_id: phy_id read from the phy
2226 *
2227 * Returns the phy type from the id.
2228 **/
2229enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2230{
2231 enum e1000_phy_type phy_type = e1000_phy_unknown;
2232
2233 switch (phy_id) {
2234 case M88E1000_I_PHY_ID:
2235 case M88E1000_E_PHY_ID:
2236 case M88E1111_I_PHY_ID:
2237 case M88E1011_I_PHY_ID:
2238 phy_type = e1000_phy_m88;
2239 break;
2240 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2241 phy_type = e1000_phy_igp_2;
2242 break;
2243 case GG82563_E_PHY_ID:
2244 phy_type = e1000_phy_gg82563;
2245 break;
2246 case IGP03E1000_E_PHY_ID:
2247 phy_type = e1000_phy_igp_3;
2248 break;
2249 case IFE_E_PHY_ID:
2250 case IFE_PLUS_E_PHY_ID:
2251 case IFE_C_E_PHY_ID:
2252 phy_type = e1000_phy_ife;
2253 break;
2254 case BME1000_E_PHY_ID:
2255 case BME1000_E_PHY_ID_R2:
2256 phy_type = e1000_phy_bm;
2257 break;
2258 case I82578_E_PHY_ID:
2259 phy_type = e1000_phy_82578;
2260 break;
2261 case I82577_E_PHY_ID:
2262 phy_type = e1000_phy_82577;
2263 break;
2264 case I82579_E_PHY_ID:
2265 phy_type = e1000_phy_82579;
2266 break;
2267 case I217_E_PHY_ID:
2268 phy_type = e1000_phy_i217;
2269 break;
2270 default:
2271 phy_type = e1000_phy_unknown;
2272 break;
2273 }
2274 return phy_type;
2275}
2276
2277/**
2278 * e1000e_determine_phy_address - Determines PHY address.
2279 * @hw: pointer to the HW structure
2280 *
2281 * This uses a trial and error method to loop through possible PHY
2282 * addresses. It tests each by reading the PHY ID registers and
2283 * checking for a match.
2284 **/
2285s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2286{
2287 u32 phy_addr = 0;
2288 u32 i;
2289 enum e1000_phy_type phy_type = e1000_phy_unknown;
2290
2291 hw->phy.id = phy_type;
2292
2293 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2294 hw->phy.addr = phy_addr;
2295 i = 0;
2296
2297 do {
2298 e1000e_get_phy_id(hw);
2299 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2300
2301 /* If phy_type is valid, break - we found our
2302 * PHY address
2303 */
2304 if (phy_type != e1000_phy_unknown)
2305 return 0;
2306
2307 usleep_range(1000, 2000);
2308 i++;
2309 } while (i < 10);
2310 }
2311
2312 return -E1000_ERR_PHY_TYPE;
2313}
2314
2315/**
2316 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2317 * @page: page to access
2318 * @reg: register to check
2319 *
2320 * Returns the phy address for the page requested.
2321 **/
2322static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2323{
2324 u32 phy_addr = 2;
2325
2326 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2327 phy_addr = 1;
2328
2329 return phy_addr;
2330}
2331
2332/**
2333 * e1000e_write_phy_reg_bm - Write BM PHY register
2334 * @hw: pointer to the HW structure
2335 * @offset: register offset to write to
2336 * @data: data to write at register offset
2337 *
2338 * Acquires semaphore, if necessary, then writes the data to PHY register
2339 * at the offset. Release any acquired semaphores before exiting.
2340 **/
2341s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2342{
2343 s32 ret_val;
2344 u32 page = offset >> IGP_PAGE_SHIFT;
2345
2346 ret_val = hw->phy.ops.acquire(hw);
2347 if (ret_val)
2348 return ret_val;
2349
2350 /* Page 800 works differently than the rest so it has its own func */
2351 if (page == BM_WUC_PAGE) {
2352 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2353 false, false);
2354 goto release;
2355 }
2356
2357 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2358
2359 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2360 u32 page_shift, page_select;
2361
2362 /* Page select is register 31 for phy address 1 and 22 for
2363 * phy address 2 and 3. Page select is shifted only for
2364 * phy address 1.
2365 */
2366 if (hw->phy.addr == 1) {
2367 page_shift = IGP_PAGE_SHIFT;
2368 page_select = IGP01E1000_PHY_PAGE_SELECT;
2369 } else {
2370 page_shift = 0;
2371 page_select = BM_PHY_PAGE_SELECT;
2372 }
2373
2374 /* Page is shifted left, PHY expects (page x 32) */
2375 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2376 (page << page_shift));
2377 if (ret_val)
2378 goto release;
2379 }
2380
2381 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2382 data);
2383
2384release:
2385 hw->phy.ops.release(hw);
2386 return ret_val;
2387}
2388
2389/**
2390 * e1000e_read_phy_reg_bm - Read BM PHY register
2391 * @hw: pointer to the HW structure
2392 * @offset: register offset to be read
2393 * @data: pointer to the read data
2394 *
2395 * Acquires semaphore, if necessary, then reads the PHY register at offset
2396 * and storing the retrieved information in data. Release any acquired
2397 * semaphores before exiting.
2398 **/
2399s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2400{
2401 s32 ret_val;
2402 u32 page = offset >> IGP_PAGE_SHIFT;
2403
2404 ret_val = hw->phy.ops.acquire(hw);
2405 if (ret_val)
2406 return ret_val;
2407
2408 /* Page 800 works differently than the rest so it has its own func */
2409 if (page == BM_WUC_PAGE) {
2410 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2411 true, false);
2412 goto release;
2413 }
2414
2415 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2416
2417 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2418 u32 page_shift, page_select;
2419
2420 /* Page select is register 31 for phy address 1 and 22 for
2421 * phy address 2 and 3. Page select is shifted only for
2422 * phy address 1.
2423 */
2424 if (hw->phy.addr == 1) {
2425 page_shift = IGP_PAGE_SHIFT;
2426 page_select = IGP01E1000_PHY_PAGE_SELECT;
2427 } else {
2428 page_shift = 0;
2429 page_select = BM_PHY_PAGE_SELECT;
2430 }
2431
2432 /* Page is shifted left, PHY expects (page x 32) */
2433 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2434 (page << page_shift));
2435 if (ret_val)
2436 goto release;
2437 }
2438
2439 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2440 data);
2441release:
2442 hw->phy.ops.release(hw);
2443 return ret_val;
2444}
2445
2446/**
2447 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2448 * @hw: pointer to the HW structure
2449 * @offset: register offset to be read
2450 * @data: pointer to the read data
2451 *
2452 * Acquires semaphore, if necessary, then reads the PHY register at offset
2453 * and storing the retrieved information in data. Release any acquired
2454 * semaphores before exiting.
2455 **/
2456s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2457{
2458 s32 ret_val;
2459 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2460
2461 ret_val = hw->phy.ops.acquire(hw);
2462 if (ret_val)
2463 return ret_val;
2464
2465 /* Page 800 works differently than the rest so it has its own func */
2466 if (page == BM_WUC_PAGE) {
2467 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2468 true, false);
2469 goto release;
2470 }
2471
2472 hw->phy.addr = 1;
2473
2474 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2475 /* Page is shifted left, PHY expects (page x 32) */
2476 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2477 page);
2478
2479 if (ret_val)
2480 goto release;
2481 }
2482
2483 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2484 data);
2485release:
2486 hw->phy.ops.release(hw);
2487 return ret_val;
2488}
2489
2490/**
2491 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2492 * @hw: pointer to the HW structure
2493 * @offset: register offset to write to
2494 * @data: data to write at register offset
2495 *
2496 * Acquires semaphore, if necessary, then writes the data to PHY register
2497 * at the offset. Release any acquired semaphores before exiting.
2498 **/
2499s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2500{
2501 s32 ret_val;
2502 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2503
2504 ret_val = hw->phy.ops.acquire(hw);
2505 if (ret_val)
2506 return ret_val;
2507
2508 /* Page 800 works differently than the rest so it has its own func */
2509 if (page == BM_WUC_PAGE) {
2510 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2511 false, false);
2512 goto release;
2513 }
2514
2515 hw->phy.addr = 1;
2516
2517 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2518 /* Page is shifted left, PHY expects (page x 32) */
2519 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2520 page);
2521
2522 if (ret_val)
2523 goto release;
2524 }
2525
2526 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2527 data);
2528
2529release:
2530 hw->phy.ops.release(hw);
2531 return ret_val;
2532}
2533
2534/**
2535 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2536 * @hw: pointer to the HW structure
2537 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2538 *
2539 * Assumes semaphore already acquired and phy_reg points to a valid memory
2540 * address to store contents of the BM_WUC_ENABLE_REG register.
2541 **/
2542s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2543{
2544 s32 ret_val;
2545 u16 temp;
2546
2547 /* All page select, port ctrl and wakeup registers use phy address 1 */
2548 hw->phy.addr = 1;
2549
2550 /* Select Port Control Registers page */
2551 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2552 if (ret_val) {
2553 e_dbg("Could not set Port Control page\n");
2554 return ret_val;
2555 }
2556
2557 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2558 if (ret_val) {
2559 e_dbg("Could not read PHY register %d.%d\n",
2560 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2561 return ret_val;
2562 }
2563
2564 /* Enable both PHY wakeup mode and Wakeup register page writes.
2565 * Prevent a power state change by disabling ME and Host PHY wakeup.
2566 */
2567 temp = *phy_reg;
2568 temp |= BM_WUC_ENABLE_BIT;
2569 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2570
2571 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2572 if (ret_val) {
2573 e_dbg("Could not write PHY register %d.%d\n",
2574 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2575 return ret_val;
2576 }
2577
2578 /* Select Host Wakeup Registers page - caller now able to write
2579 * registers on the Wakeup registers page
2580 */
2581 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2582}
2583
2584/**
2585 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2586 * @hw: pointer to the HW structure
2587 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2588 *
2589 * Restore BM_WUC_ENABLE_REG to its original value.
2590 *
2591 * Assumes semaphore already acquired and *phy_reg is the contents of the
2592 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2593 * caller.
2594 **/
2595s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2596{
2597 s32 ret_val;
2598
2599 /* Select Port Control Registers page */
2600 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2601 if (ret_val) {
2602 e_dbg("Could not set Port Control page\n");
2603 return ret_val;
2604 }
2605
2606 /* Restore 769.17 to its original value */
2607 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2608 if (ret_val)
2609 e_dbg("Could not restore PHY register %d.%d\n",
2610 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2611
2612 return ret_val;
2613}
2614
2615/**
2616 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2617 * @hw: pointer to the HW structure
2618 * @offset: register offset to be read or written
2619 * @data: pointer to the data to read or write
2620 * @read: determines if operation is read or write
2621 * @page_set: BM_WUC_PAGE already set and access enabled
2622 *
2623 * Read the PHY register at offset and store the retrieved information in
2624 * data, or write data to PHY register at offset. Note the procedure to
2625 * access the PHY wakeup registers is different than reading the other PHY
2626 * registers. It works as such:
2627 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2628 * 2) Set page to 800 for host (801 if we were manageability)
2629 * 3) Write the address using the address opcode (0x11)
2630 * 4) Read or write the data using the data opcode (0x12)
2631 * 5) Restore 769.17.2 to its original value
2632 *
2633 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2634 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2635 *
2636 * Assumes semaphore is already acquired. When page_set==true, assumes
2637 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2638 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2639 **/
2640static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2641 u16 *data, bool read, bool page_set)
2642{
2643 s32 ret_val;
2644 u16 reg = BM_PHY_REG_NUM(offset);
2645 u16 page = BM_PHY_REG_PAGE(offset);
2646 u16 phy_reg = 0;
2647
2648 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2649 if ((hw->mac.type == e1000_pchlan) &&
2650 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2651 e_dbg("Attempting to access page %d while gig enabled.\n",
2652 page);
2653
2654 if (!page_set) {
2655 /* Enable access to PHY wakeup registers */
2656 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2657 if (ret_val) {
2658 e_dbg("Could not enable PHY wakeup reg access\n");
2659 return ret_val;
2660 }
2661 }
2662
2663 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2664
2665 /* Write the Wakeup register page offset value using opcode 0x11 */
2666 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2667 if (ret_val) {
2668 e_dbg("Could not write address opcode to page %d\n", page);
2669 return ret_val;
2670 }
2671
2672 if (read) {
2673 /* Read the Wakeup register page value using opcode 0x12 */
2674 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2675 data);
2676 } else {
2677 /* Write the Wakeup register page value using opcode 0x12 */
2678 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2679 *data);
2680 }
2681
2682 if (ret_val) {
2683 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2684 return ret_val;
2685 }
2686
2687 if (!page_set)
2688 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2689
2690 return ret_val;
2691}
2692
2693/**
2694 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2695 * @hw: pointer to the HW structure
2696 *
2697 * In the case of a PHY power down to save power, or to turn off link during a
2698 * driver unload, or wake on lan is not enabled, restore the link to previous
2699 * settings.
2700 **/
2701void e1000_power_up_phy_copper(struct e1000_hw *hw)
2702{
2703 u16 mii_reg = 0;
2704 int ret;
2705
2706 /* The PHY will retain its settings across a power down/up cycle */
2707 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2708 if (ret) {
2709 e_dbg("Error reading PHY register\n");
2710 return;
2711 }
2712 mii_reg &= ~BMCR_PDOWN;
2713 e1e_wphy(hw, MII_BMCR, mii_reg);
2714}
2715
2716/**
2717 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2718 * @hw: pointer to the HW structure
2719 *
2720 * In the case of a PHY power down to save power, or to turn off link during a
2721 * driver unload, or wake on lan is not enabled, restore the link to previous
2722 * settings.
2723 **/
2724void e1000_power_down_phy_copper(struct e1000_hw *hw)
2725{
2726 u16 mii_reg = 0;
2727 int ret;
2728
2729 /* The PHY will retain its settings across a power down/up cycle */
2730 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2731 if (ret) {
2732 e_dbg("Error reading PHY register\n");
2733 return;
2734 }
2735 mii_reg |= BMCR_PDOWN;
2736 e1e_wphy(hw, MII_BMCR, mii_reg);
2737 usleep_range(1000, 2000);
2738}
2739
2740/**
2741 * __e1000_read_phy_reg_hv - Read HV PHY register
2742 * @hw: pointer to the HW structure
2743 * @offset: register offset to be read
2744 * @data: pointer to the read data
2745 * @locked: semaphore has already been acquired or not
2746 * @page_set: BM_WUC_PAGE already set and access enabled
2747 *
2748 * Acquires semaphore, if necessary, then reads the PHY register at offset
2749 * and stores the retrieved information in data. Release any acquired
2750 * semaphore before exiting.
2751 **/
2752static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2753 bool locked, bool page_set)
2754{
2755 s32 ret_val;
2756 u16 page = BM_PHY_REG_PAGE(offset);
2757 u16 reg = BM_PHY_REG_NUM(offset);
2758 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2759
2760 if (!locked) {
2761 ret_val = hw->phy.ops.acquire(hw);
2762 if (ret_val)
2763 return ret_val;
2764 }
2765
2766 /* Page 800 works differently than the rest so it has its own func */
2767 if (page == BM_WUC_PAGE) {
2768 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2769 true, page_set);
2770 goto out;
2771 }
2772
2773 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2774 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2775 data, true);
2776 goto out;
2777 }
2778
2779 if (!page_set) {
2780 if (page == HV_INTC_FC_PAGE_START)
2781 page = 0;
2782
2783 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2784 /* Page is shifted left, PHY expects (page x 32) */
2785 ret_val = e1000_set_page_igp(hw,
2786 (page << IGP_PAGE_SHIFT));
2787
2788 hw->phy.addr = phy_addr;
2789
2790 if (ret_val)
2791 goto out;
2792 }
2793 }
2794
2795 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2796 page << IGP_PAGE_SHIFT, reg);
2797
2798 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2799out:
2800 if (!locked)
2801 hw->phy.ops.release(hw);
2802
2803 return ret_val;
2804}
2805
2806/**
2807 * e1000_read_phy_reg_hv - Read HV PHY register
2808 * @hw: pointer to the HW structure
2809 * @offset: register offset to be read
2810 * @data: pointer to the read data
2811 *
2812 * Acquires semaphore then reads the PHY register at offset and stores
2813 * the retrieved information in data. Release the acquired semaphore
2814 * before exiting.
2815 **/
2816s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2817{
2818 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2819}
2820
2821/**
2822 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2823 * @hw: pointer to the HW structure
2824 * @offset: register offset to be read
2825 * @data: pointer to the read data
2826 *
2827 * Reads the PHY register at offset and stores the retrieved information
2828 * in data. Assumes semaphore already acquired.
2829 **/
2830s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2831{
2832 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2833}
2834
2835/**
2836 * e1000_read_phy_reg_page_hv - Read HV PHY register
2837 * @hw: pointer to the HW structure
2838 * @offset: register offset to write to
2839 * @data: data to write at register offset
2840 *
2841 * Reads the PHY register at offset and stores the retrieved information
2842 * in data. Assumes semaphore already acquired and page already set.
2843 **/
2844s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2845{
2846 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2847}
2848
2849/**
2850 * __e1000_write_phy_reg_hv - Write HV PHY register
2851 * @hw: pointer to the HW structure
2852 * @offset: register offset to write to
2853 * @data: data to write at register offset
2854 * @locked: semaphore has already been acquired or not
2855 * @page_set: BM_WUC_PAGE already set and access enabled
2856 *
2857 * Acquires semaphore, if necessary, then writes the data to PHY register
2858 * at the offset. Release any acquired semaphores before exiting.
2859 **/
2860static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2861 bool locked, bool page_set)
2862{
2863 s32 ret_val;
2864 u16 page = BM_PHY_REG_PAGE(offset);
2865 u16 reg = BM_PHY_REG_NUM(offset);
2866 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2867
2868 if (!locked) {
2869 ret_val = hw->phy.ops.acquire(hw);
2870 if (ret_val)
2871 return ret_val;
2872 }
2873
2874 /* Page 800 works differently than the rest so it has its own func */
2875 if (page == BM_WUC_PAGE) {
2876 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2877 false, page_set);
2878 goto out;
2879 }
2880
2881 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2882 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2883 &data, false);
2884 goto out;
2885 }
2886
2887 if (!page_set) {
2888 if (page == HV_INTC_FC_PAGE_START)
2889 page = 0;
2890
2891 /* Workaround MDIO accesses being disabled after entering IEEE
2892 * Power Down (when bit 11 of the PHY Control register is set)
2893 */
2894 if ((hw->phy.type == e1000_phy_82578) &&
2895 (hw->phy.revision >= 1) &&
2896 (hw->phy.addr == 2) &&
2897 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2898 u16 data2 = 0x7EFF;
2899
2900 ret_val = e1000_access_phy_debug_regs_hv(hw,
2901 BIT(6) | 0x3,
2902 &data2, false);
2903 if (ret_val)
2904 goto out;
2905 }
2906
2907 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2908 /* Page is shifted left, PHY expects (page x 32) */
2909 ret_val = e1000_set_page_igp(hw,
2910 (page << IGP_PAGE_SHIFT));
2911
2912 hw->phy.addr = phy_addr;
2913
2914 if (ret_val)
2915 goto out;
2916 }
2917 }
2918
2919 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2920 page << IGP_PAGE_SHIFT, reg);
2921
2922 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2923 data);
2924
2925out:
2926 if (!locked)
2927 hw->phy.ops.release(hw);
2928
2929 return ret_val;
2930}
2931
2932/**
2933 * e1000_write_phy_reg_hv - Write HV PHY register
2934 * @hw: pointer to the HW structure
2935 * @offset: register offset to write to
2936 * @data: data to write at register offset
2937 *
2938 * Acquires semaphore then writes the data to PHY register at the offset.
2939 * Release the acquired semaphores before exiting.
2940 **/
2941s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2942{
2943 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2944}
2945
2946/**
2947 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2948 * @hw: pointer to the HW structure
2949 * @offset: register offset to write to
2950 * @data: data to write at register offset
2951 *
2952 * Writes the data to PHY register at the offset. Assumes semaphore
2953 * already acquired.
2954 **/
2955s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2956{
2957 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2958}
2959
2960/**
2961 * e1000_write_phy_reg_page_hv - Write HV PHY register
2962 * @hw: pointer to the HW structure
2963 * @offset: register offset to write to
2964 * @data: data to write at register offset
2965 *
2966 * Writes the data to PHY register at the offset. Assumes semaphore
2967 * already acquired and page already set.
2968 **/
2969s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2970{
2971 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2972}
2973
2974/**
2975 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2976 * @page: page to be accessed
2977 **/
2978static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2979{
2980 u32 phy_addr = 2;
2981
2982 if (page >= HV_INTC_FC_PAGE_START)
2983 phy_addr = 1;
2984
2985 return phy_addr;
2986}
2987
2988/**
2989 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2990 * @hw: pointer to the HW structure
2991 * @offset: register offset to be read or written
2992 * @data: pointer to the data to be read or written
2993 * @read: determines if operation is read or write
2994 *
2995 * Reads the PHY register at offset and stores the retrieved information
2996 * in data. Assumes semaphore already acquired. Note that the procedure
2997 * to access these regs uses the address port and data port to read/write.
2998 * These accesses done with PHY address 2 and without using pages.
2999 **/
3000static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3001 u16 *data, bool read)
3002{
3003 s32 ret_val;
3004 u32 addr_reg;
3005 u32 data_reg;
3006
3007 /* This takes care of the difference with desktop vs mobile phy */
3008 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3009 I82578_ADDR_REG : I82577_ADDR_REG);
3010 data_reg = addr_reg + 1;
3011
3012 /* All operations in this function are phy address 2 */
3013 hw->phy.addr = 2;
3014
3015 /* masking with 0x3F to remove the page from offset */
3016 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3017 if (ret_val) {
3018 e_dbg("Could not write the Address Offset port register\n");
3019 return ret_val;
3020 }
3021
3022 /* Read or write the data value next */
3023 if (read)
3024 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3025 else
3026 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3027
3028 if (ret_val)
3029 e_dbg("Could not access the Data port register\n");
3030
3031 return ret_val;
3032}
3033
3034/**
3035 * e1000_link_stall_workaround_hv - Si workaround
3036 * @hw: pointer to the HW structure
3037 *
3038 * This function works around a Si bug where the link partner can get
3039 * a link up indication before the PHY does. If small packets are sent
3040 * by the link partner they can be placed in the packet buffer without
3041 * being properly accounted for by the PHY and will stall preventing
3042 * further packets from being received. The workaround is to clear the
3043 * packet buffer after the PHY detects link up.
3044 **/
3045s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3046{
3047 s32 ret_val = 0;
3048 u16 data;
3049
3050 if (hw->phy.type != e1000_phy_82578)
3051 return 0;
3052
3053 /* Do not apply workaround if in PHY loopback bit 14 set */
3054 ret_val = e1e_rphy(hw, MII_BMCR, &data);
3055 if (ret_val) {
3056 e_dbg("Error reading PHY register\n");
3057 return ret_val;
3058 }
3059 if (data & BMCR_LOOPBACK)
3060 return 0;
3061
3062 /* check if link is up and at 1Gbps */
3063 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3064 if (ret_val)
3065 return ret_val;
3066
3067 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3068 BM_CS_STATUS_SPEED_MASK);
3069
3070 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3071 BM_CS_STATUS_SPEED_1000))
3072 return 0;
3073
3074 msleep(200);
3075
3076 /* flush the packets in the fifo buffer */
3077 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3078 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3079 HV_MUX_DATA_CTRL_FORCE_SPEED));
3080 if (ret_val)
3081 return ret_val;
3082
3083 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3084}
3085
3086/**
3087 * e1000_check_polarity_82577 - Checks the polarity.
3088 * @hw: pointer to the HW structure
3089 *
3090 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3091 *
3092 * Polarity is determined based on the PHY specific status register.
3093 **/
3094s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3095{
3096 struct e1000_phy_info *phy = &hw->phy;
3097 s32 ret_val;
3098 u16 data;
3099
3100 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3101
3102 if (!ret_val)
3103 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3104 ? e1000_rev_polarity_reversed
3105 : e1000_rev_polarity_normal);
3106
3107 return ret_val;
3108}
3109
3110/**
3111 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3112 * @hw: pointer to the HW structure
3113 *
3114 * Calls the PHY setup function to force speed and duplex.
3115 **/
3116s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3117{
3118 struct e1000_phy_info *phy = &hw->phy;
3119 s32 ret_val;
3120 u16 phy_data;
3121 bool link;
3122
3123 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3124 if (ret_val)
3125 return ret_val;
3126
3127 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3128
3129 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3130 if (ret_val)
3131 return ret_val;
3132
3133 udelay(1);
3134
3135 if (phy->autoneg_wait_to_complete) {
3136 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3137
3138 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3139 100000, &link);
3140 if (ret_val)
3141 return ret_val;
3142
3143 if (!link)
3144 e_dbg("Link taking longer than expected.\n");
3145
3146 /* Try once more */
3147 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3148 100000, &link);
3149 }
3150
3151 return ret_val;
3152}
3153
3154/**
3155 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3156 * @hw: pointer to the HW structure
3157 *
3158 * Read PHY status to determine if link is up. If link is up, then
3159 * set/determine 10base-T extended distance and polarity correction. Read
3160 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3161 * determine on the cable length, local and remote receiver.
3162 **/
3163s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3164{
3165 struct e1000_phy_info *phy = &hw->phy;
3166 s32 ret_val;
3167 u16 data;
3168 bool link;
3169
3170 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3171 if (ret_val)
3172 return ret_val;
3173
3174 if (!link) {
3175 e_dbg("Phy info is only valid if link is up\n");
3176 return -E1000_ERR_CONFIG;
3177 }
3178
3179 phy->polarity_correction = true;
3180
3181 ret_val = e1000_check_polarity_82577(hw);
3182 if (ret_val)
3183 return ret_val;
3184
3185 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3186 if (ret_val)
3187 return ret_val;
3188
3189 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3190
3191 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3192 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3193 ret_val = hw->phy.ops.get_cable_length(hw);
3194 if (ret_val)
3195 return ret_val;
3196
3197 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3198 if (ret_val)
3199 return ret_val;
3200
3201 phy->local_rx = (data & LPA_1000LOCALRXOK)
3202 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3203
3204 phy->remote_rx = (data & LPA_1000REMRXOK)
3205 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3206 } else {
3207 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3208 phy->local_rx = e1000_1000t_rx_status_undefined;
3209 phy->remote_rx = e1000_1000t_rx_status_undefined;
3210 }
3211
3212 return 0;
3213}
3214
3215/**
3216 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3217 * @hw: pointer to the HW structure
3218 *
3219 * Reads the diagnostic status register and verifies result is valid before
3220 * placing it in the phy_cable_length field.
3221 **/
3222s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3223{
3224 struct e1000_phy_info *phy = &hw->phy;
3225 s32 ret_val;
3226 u16 phy_data, length;
3227
3228 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3229 if (ret_val)
3230 return ret_val;
3231
3232 length = FIELD_GET(I82577_DSTATUS_CABLE_LENGTH, phy_data);
3233
3234 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3235 return -E1000_ERR_PHY;
3236
3237 phy->cable_length = length;
3238
3239 return 0;
3240}
1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22#include "e1000.h"
23
24static s32 e1000_wait_autoneg(struct e1000_hw *hw);
25static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
26 u16 *data, bool read, bool page_set);
27static u32 e1000_get_phy_addr_for_hv_page(u32 page);
28static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
29 u16 *data, bool read);
30
31/* Cable length tables */
32static const u16 e1000_m88_cable_length_table[] = {
33 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
34};
35
36#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
37 ARRAY_SIZE(e1000_m88_cable_length_table)
38
39static const u16 e1000_igp_2_cable_length_table[] = {
40 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
41 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
42 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
43 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
44 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
45 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
46 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
47 124
48};
49
50#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
51 ARRAY_SIZE(e1000_igp_2_cable_length_table)
52
53/**
54 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
55 * @hw: pointer to the HW structure
56 *
57 * Read the PHY management control register and check whether a PHY reset
58 * is blocked. If a reset is not blocked return 0, otherwise
59 * return E1000_BLK_PHY_RESET (12).
60 **/
61s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
62{
63 u32 manc;
64
65 manc = er32(MANC);
66
67 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
68}
69
70/**
71 * e1000e_get_phy_id - Retrieve the PHY ID and revision
72 * @hw: pointer to the HW structure
73 *
74 * Reads the PHY registers and stores the PHY ID and possibly the PHY
75 * revision in the hardware structure.
76 **/
77s32 e1000e_get_phy_id(struct e1000_hw *hw)
78{
79 struct e1000_phy_info *phy = &hw->phy;
80 s32 ret_val = 0;
81 u16 phy_id;
82 u16 retry_count = 0;
83
84 if (!phy->ops.read_reg)
85 return 0;
86
87 while (retry_count < 2) {
88 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
89 if (ret_val)
90 return ret_val;
91
92 phy->id = (u32)(phy_id << 16);
93 usleep_range(20, 40);
94 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
95 if (ret_val)
96 return ret_val;
97
98 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
99 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
100
101 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
102 return 0;
103
104 retry_count++;
105 }
106
107 return 0;
108}
109
110/**
111 * e1000e_phy_reset_dsp - Reset PHY DSP
112 * @hw: pointer to the HW structure
113 *
114 * Reset the digital signal processor.
115 **/
116s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
117{
118 s32 ret_val;
119
120 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
121 if (ret_val)
122 return ret_val;
123
124 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
125}
126
127/**
128 * e1000e_read_phy_reg_mdic - Read MDI control register
129 * @hw: pointer to the HW structure
130 * @offset: register offset to be read
131 * @data: pointer to the read data
132 *
133 * Reads the MDI control register in the PHY at offset and stores the
134 * information read to data.
135 **/
136s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
137{
138 struct e1000_phy_info *phy = &hw->phy;
139 u32 i, mdic = 0;
140
141 if (offset > MAX_PHY_REG_ADDRESS) {
142 e_dbg("PHY Address %d is out of range\n", offset);
143 return -E1000_ERR_PARAM;
144 }
145
146 /* Set up Op-code, Phy Address, and register offset in the MDI
147 * Control register. The MAC will take care of interfacing with the
148 * PHY to retrieve the desired data.
149 */
150 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
151 (phy->addr << E1000_MDIC_PHY_SHIFT) |
152 (E1000_MDIC_OP_READ));
153
154 ew32(MDIC, mdic);
155
156 /* Poll the ready bit to see if the MDI read completed
157 * Increasing the time out as testing showed failures with
158 * the lower time out
159 */
160 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
161 udelay(50);
162 mdic = er32(MDIC);
163 if (mdic & E1000_MDIC_READY)
164 break;
165 }
166 if (!(mdic & E1000_MDIC_READY)) {
167 e_dbg("MDI Read did not complete\n");
168 return -E1000_ERR_PHY;
169 }
170 if (mdic & E1000_MDIC_ERROR) {
171 e_dbg("MDI Error\n");
172 return -E1000_ERR_PHY;
173 }
174 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
175 e_dbg("MDI Read offset error - requested %d, returned %d\n",
176 offset,
177 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
178 return -E1000_ERR_PHY;
179 }
180 *data = (u16)mdic;
181
182 /* Allow some time after each MDIC transaction to avoid
183 * reading duplicate data in the next MDIC transaction.
184 */
185 if (hw->mac.type == e1000_pch2lan)
186 udelay(100);
187
188 return 0;
189}
190
191/**
192 * e1000e_write_phy_reg_mdic - Write MDI control register
193 * @hw: pointer to the HW structure
194 * @offset: register offset to write to
195 * @data: data to write to register at offset
196 *
197 * Writes data to MDI control register in the PHY at offset.
198 **/
199s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
200{
201 struct e1000_phy_info *phy = &hw->phy;
202 u32 i, mdic = 0;
203
204 if (offset > MAX_PHY_REG_ADDRESS) {
205 e_dbg("PHY Address %d is out of range\n", offset);
206 return -E1000_ERR_PARAM;
207 }
208
209 /* Set up Op-code, Phy Address, and register offset in the MDI
210 * Control register. The MAC will take care of interfacing with the
211 * PHY to retrieve the desired data.
212 */
213 mdic = (((u32)data) |
214 (offset << E1000_MDIC_REG_SHIFT) |
215 (phy->addr << E1000_MDIC_PHY_SHIFT) |
216 (E1000_MDIC_OP_WRITE));
217
218 ew32(MDIC, mdic);
219
220 /* Poll the ready bit to see if the MDI read completed
221 * Increasing the time out as testing showed failures with
222 * the lower time out
223 */
224 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
225 udelay(50);
226 mdic = er32(MDIC);
227 if (mdic & E1000_MDIC_READY)
228 break;
229 }
230 if (!(mdic & E1000_MDIC_READY)) {
231 e_dbg("MDI Write did not complete\n");
232 return -E1000_ERR_PHY;
233 }
234 if (mdic & E1000_MDIC_ERROR) {
235 e_dbg("MDI Error\n");
236 return -E1000_ERR_PHY;
237 }
238 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
239 e_dbg("MDI Write offset error - requested %d, returned %d\n",
240 offset,
241 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
242 return -E1000_ERR_PHY;
243 }
244
245 /* Allow some time after each MDIC transaction to avoid
246 * reading duplicate data in the next MDIC transaction.
247 */
248 if (hw->mac.type == e1000_pch2lan)
249 udelay(100);
250
251 return 0;
252}
253
254/**
255 * e1000e_read_phy_reg_m88 - Read m88 PHY register
256 * @hw: pointer to the HW structure
257 * @offset: register offset to be read
258 * @data: pointer to the read data
259 *
260 * Acquires semaphore, if necessary, then reads the PHY register at offset
261 * and storing the retrieved information in data. Release any acquired
262 * semaphores before exiting.
263 **/
264s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
265{
266 s32 ret_val;
267
268 ret_val = hw->phy.ops.acquire(hw);
269 if (ret_val)
270 return ret_val;
271
272 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
273 data);
274
275 hw->phy.ops.release(hw);
276
277 return ret_val;
278}
279
280/**
281 * e1000e_write_phy_reg_m88 - Write m88 PHY register
282 * @hw: pointer to the HW structure
283 * @offset: register offset to write to
284 * @data: data to write at register offset
285 *
286 * Acquires semaphore, if necessary, then writes the data to PHY register
287 * at the offset. Release any acquired semaphores before exiting.
288 **/
289s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
290{
291 s32 ret_val;
292
293 ret_val = hw->phy.ops.acquire(hw);
294 if (ret_val)
295 return ret_val;
296
297 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
298 data);
299
300 hw->phy.ops.release(hw);
301
302 return ret_val;
303}
304
305/**
306 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
307 * @hw: pointer to the HW structure
308 * @page: page to set (shifted left when necessary)
309 *
310 * Sets PHY page required for PHY register access. Assumes semaphore is
311 * already acquired. Note, this function sets phy.addr to 1 so the caller
312 * must set it appropriately (if necessary) after this function returns.
313 **/
314s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
315{
316 e_dbg("Setting page 0x%x\n", page);
317
318 hw->phy.addr = 1;
319
320 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
321}
322
323/**
324 * __e1000e_read_phy_reg_igp - Read igp PHY register
325 * @hw: pointer to the HW structure
326 * @offset: register offset to be read
327 * @data: pointer to the read data
328 * @locked: semaphore has already been acquired or not
329 *
330 * Acquires semaphore, if necessary, then reads the PHY register at offset
331 * and stores the retrieved information in data. Release any acquired
332 * semaphores before exiting.
333 **/
334static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
335 bool locked)
336{
337 s32 ret_val = 0;
338
339 if (!locked) {
340 if (!hw->phy.ops.acquire)
341 return 0;
342
343 ret_val = hw->phy.ops.acquire(hw);
344 if (ret_val)
345 return ret_val;
346 }
347
348 if (offset > MAX_PHY_MULTI_PAGE_REG)
349 ret_val = e1000e_write_phy_reg_mdic(hw,
350 IGP01E1000_PHY_PAGE_SELECT,
351 (u16)offset);
352 if (!ret_val)
353 ret_val = e1000e_read_phy_reg_mdic(hw,
354 MAX_PHY_REG_ADDRESS & offset,
355 data);
356 if (!locked)
357 hw->phy.ops.release(hw);
358
359 return ret_val;
360}
361
362/**
363 * e1000e_read_phy_reg_igp - Read igp PHY register
364 * @hw: pointer to the HW structure
365 * @offset: register offset to be read
366 * @data: pointer to the read data
367 *
368 * Acquires semaphore then reads the PHY register at offset and stores the
369 * retrieved information in data.
370 * Release the acquired semaphore before exiting.
371 **/
372s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
373{
374 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
375}
376
377/**
378 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
379 * @hw: pointer to the HW structure
380 * @offset: register offset to be read
381 * @data: pointer to the read data
382 *
383 * Reads the PHY register at offset and stores the retrieved information
384 * in data. Assumes semaphore already acquired.
385 **/
386s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
387{
388 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
389}
390
391/**
392 * e1000e_write_phy_reg_igp - Write igp PHY register
393 * @hw: pointer to the HW structure
394 * @offset: register offset to write to
395 * @data: data to write at register offset
396 * @locked: semaphore has already been acquired or not
397 *
398 * Acquires semaphore, if necessary, then writes the data to PHY register
399 * at the offset. Release any acquired semaphores before exiting.
400 **/
401static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
402 bool locked)
403{
404 s32 ret_val = 0;
405
406 if (!locked) {
407 if (!hw->phy.ops.acquire)
408 return 0;
409
410 ret_val = hw->phy.ops.acquire(hw);
411 if (ret_val)
412 return ret_val;
413 }
414
415 if (offset > MAX_PHY_MULTI_PAGE_REG)
416 ret_val = e1000e_write_phy_reg_mdic(hw,
417 IGP01E1000_PHY_PAGE_SELECT,
418 (u16)offset);
419 if (!ret_val)
420 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
421 offset, data);
422 if (!locked)
423 hw->phy.ops.release(hw);
424
425 return ret_val;
426}
427
428/**
429 * e1000e_write_phy_reg_igp - Write igp PHY register
430 * @hw: pointer to the HW structure
431 * @offset: register offset to write to
432 * @data: data to write at register offset
433 *
434 * Acquires semaphore then writes the data to PHY register
435 * at the offset. Release any acquired semaphores before exiting.
436 **/
437s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
438{
439 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
440}
441
442/**
443 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
444 * @hw: pointer to the HW structure
445 * @offset: register offset to write to
446 * @data: data to write at register offset
447 *
448 * Writes the data to PHY register at the offset.
449 * Assumes semaphore already acquired.
450 **/
451s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
452{
453 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
454}
455
456/**
457 * __e1000_read_kmrn_reg - Read kumeran register
458 * @hw: pointer to the HW structure
459 * @offset: register offset to be read
460 * @data: pointer to the read data
461 * @locked: semaphore has already been acquired or not
462 *
463 * Acquires semaphore, if necessary. Then reads the PHY register at offset
464 * using the kumeran interface. The information retrieved is stored in data.
465 * Release any acquired semaphores before exiting.
466 **/
467static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
468 bool locked)
469{
470 u32 kmrnctrlsta;
471
472 if (!locked) {
473 s32 ret_val = 0;
474
475 if (!hw->phy.ops.acquire)
476 return 0;
477
478 ret_val = hw->phy.ops.acquire(hw);
479 if (ret_val)
480 return ret_val;
481 }
482
483 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
484 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
485 ew32(KMRNCTRLSTA, kmrnctrlsta);
486 e1e_flush();
487
488 udelay(2);
489
490 kmrnctrlsta = er32(KMRNCTRLSTA);
491 *data = (u16)kmrnctrlsta;
492
493 if (!locked)
494 hw->phy.ops.release(hw);
495
496 return 0;
497}
498
499/**
500 * e1000e_read_kmrn_reg - Read kumeran register
501 * @hw: pointer to the HW structure
502 * @offset: register offset to be read
503 * @data: pointer to the read data
504 *
505 * Acquires semaphore then reads the PHY register at offset using the
506 * kumeran interface. The information retrieved is stored in data.
507 * Release the acquired semaphore before exiting.
508 **/
509s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
510{
511 return __e1000_read_kmrn_reg(hw, offset, data, false);
512}
513
514/**
515 * e1000e_read_kmrn_reg_locked - Read kumeran register
516 * @hw: pointer to the HW structure
517 * @offset: register offset to be read
518 * @data: pointer to the read data
519 *
520 * Reads the PHY register at offset using the kumeran interface. The
521 * information retrieved is stored in data.
522 * Assumes semaphore already acquired.
523 **/
524s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
525{
526 return __e1000_read_kmrn_reg(hw, offset, data, true);
527}
528
529/**
530 * __e1000_write_kmrn_reg - Write kumeran register
531 * @hw: pointer to the HW structure
532 * @offset: register offset to write to
533 * @data: data to write at register offset
534 * @locked: semaphore has already been acquired or not
535 *
536 * Acquires semaphore, if necessary. Then write the data to PHY register
537 * at the offset using the kumeran interface. Release any acquired semaphores
538 * before exiting.
539 **/
540static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
541 bool locked)
542{
543 u32 kmrnctrlsta;
544
545 if (!locked) {
546 s32 ret_val = 0;
547
548 if (!hw->phy.ops.acquire)
549 return 0;
550
551 ret_val = hw->phy.ops.acquire(hw);
552 if (ret_val)
553 return ret_val;
554 }
555
556 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
557 E1000_KMRNCTRLSTA_OFFSET) | data;
558 ew32(KMRNCTRLSTA, kmrnctrlsta);
559 e1e_flush();
560
561 udelay(2);
562
563 if (!locked)
564 hw->phy.ops.release(hw);
565
566 return 0;
567}
568
569/**
570 * e1000e_write_kmrn_reg - Write kumeran register
571 * @hw: pointer to the HW structure
572 * @offset: register offset to write to
573 * @data: data to write at register offset
574 *
575 * Acquires semaphore then writes the data to the PHY register at the offset
576 * using the kumeran interface. Release the acquired semaphore before exiting.
577 **/
578s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
579{
580 return __e1000_write_kmrn_reg(hw, offset, data, false);
581}
582
583/**
584 * e1000e_write_kmrn_reg_locked - Write kumeran register
585 * @hw: pointer to the HW structure
586 * @offset: register offset to write to
587 * @data: data to write at register offset
588 *
589 * Write the data to PHY register at the offset using the kumeran interface.
590 * Assumes semaphore already acquired.
591 **/
592s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
593{
594 return __e1000_write_kmrn_reg(hw, offset, data, true);
595}
596
597/**
598 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
599 * @hw: pointer to the HW structure
600 *
601 * Sets up Master/slave mode
602 **/
603static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
604{
605 s32 ret_val;
606 u16 phy_data;
607
608 /* Resolve Master/Slave mode */
609 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
610 if (ret_val)
611 return ret_val;
612
613 /* load defaults for future use */
614 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
615 ((phy_data & CTL1000_AS_MASTER) ?
616 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
617
618 switch (hw->phy.ms_type) {
619 case e1000_ms_force_master:
620 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
621 break;
622 case e1000_ms_force_slave:
623 phy_data |= CTL1000_ENABLE_MASTER;
624 phy_data &= ~(CTL1000_AS_MASTER);
625 break;
626 case e1000_ms_auto:
627 phy_data &= ~CTL1000_ENABLE_MASTER;
628 /* fall-through */
629 default:
630 break;
631 }
632
633 return e1e_wphy(hw, MII_CTRL1000, phy_data);
634}
635
636/**
637 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
638 * @hw: pointer to the HW structure
639 *
640 * Sets up Carrier-sense on Transmit and downshift values.
641 **/
642s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
643{
644 s32 ret_val;
645 u16 phy_data;
646
647 /* Enable CRS on Tx. This must be set for half-duplex operation. */
648 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
649 if (ret_val)
650 return ret_val;
651
652 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
653
654 /* Enable downshift */
655 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
656
657 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
658 if (ret_val)
659 return ret_val;
660
661 /* Set MDI/MDIX mode */
662 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
663 if (ret_val)
664 return ret_val;
665 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
666 /* Options:
667 * 0 - Auto (default)
668 * 1 - MDI mode
669 * 2 - MDI-X mode
670 */
671 switch (hw->phy.mdix) {
672 case 1:
673 break;
674 case 2:
675 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
676 break;
677 case 0:
678 default:
679 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
680 break;
681 }
682 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
683 if (ret_val)
684 return ret_val;
685
686 return e1000_set_master_slave_mode(hw);
687}
688
689/**
690 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
691 * @hw: pointer to the HW structure
692 *
693 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
694 * and downshift values are set also.
695 **/
696s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
697{
698 struct e1000_phy_info *phy = &hw->phy;
699 s32 ret_val;
700 u16 phy_data;
701
702 /* Enable CRS on Tx. This must be set for half-duplex operation. */
703 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
704 if (ret_val)
705 return ret_val;
706
707 /* For BM PHY this bit is downshift enable */
708 if (phy->type != e1000_phy_bm)
709 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
710
711 /* Options:
712 * MDI/MDI-X = 0 (default)
713 * 0 - Auto for all speeds
714 * 1 - MDI mode
715 * 2 - MDI-X mode
716 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
717 */
718 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
719
720 switch (phy->mdix) {
721 case 1:
722 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
723 break;
724 case 2:
725 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
726 break;
727 case 3:
728 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
729 break;
730 case 0:
731 default:
732 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
733 break;
734 }
735
736 /* Options:
737 * disable_polarity_correction = 0 (default)
738 * Automatic Correction for Reversed Cable Polarity
739 * 0 - Disabled
740 * 1 - Enabled
741 */
742 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
743 if (phy->disable_polarity_correction)
744 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
745
746 /* Enable downshift on BM (disabled by default) */
747 if (phy->type == e1000_phy_bm) {
748 /* For 82574/82583, first disable then enable downshift */
749 if (phy->id == BME1000_E_PHY_ID_R2) {
750 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
751 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
752 phy_data);
753 if (ret_val)
754 return ret_val;
755 /* Commit the changes. */
756 ret_val = phy->ops.commit(hw);
757 if (ret_val) {
758 e_dbg("Error committing the PHY changes\n");
759 return ret_val;
760 }
761 }
762
763 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
764 }
765
766 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
767 if (ret_val)
768 return ret_val;
769
770 if ((phy->type == e1000_phy_m88) &&
771 (phy->revision < E1000_REVISION_4) &&
772 (phy->id != BME1000_E_PHY_ID_R2)) {
773 /* Force TX_CLK in the Extended PHY Specific Control Register
774 * to 25MHz clock.
775 */
776 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
777 if (ret_val)
778 return ret_val;
779
780 phy_data |= M88E1000_EPSCR_TX_CLK_25;
781
782 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
783 /* 82573L PHY - set the downshift counter to 5x. */
784 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
785 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
786 } else {
787 /* Configure Master and Slave downshift values */
788 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
789 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
790 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
791 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
792 }
793 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
794 if (ret_val)
795 return ret_val;
796 }
797
798 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
799 /* Set PHY page 0, register 29 to 0x0003 */
800 ret_val = e1e_wphy(hw, 29, 0x0003);
801 if (ret_val)
802 return ret_val;
803
804 /* Set PHY page 0, register 30 to 0x0000 */
805 ret_val = e1e_wphy(hw, 30, 0x0000);
806 if (ret_val)
807 return ret_val;
808 }
809
810 /* Commit the changes. */
811 if (phy->ops.commit) {
812 ret_val = phy->ops.commit(hw);
813 if (ret_val) {
814 e_dbg("Error committing the PHY changes\n");
815 return ret_val;
816 }
817 }
818
819 if (phy->type == e1000_phy_82578) {
820 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
821 if (ret_val)
822 return ret_val;
823
824 /* 82578 PHY - set the downshift count to 1x. */
825 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
826 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
827 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
828 if (ret_val)
829 return ret_val;
830 }
831
832 return 0;
833}
834
835/**
836 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
837 * @hw: pointer to the HW structure
838 *
839 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
840 * igp PHY's.
841 **/
842s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
843{
844 struct e1000_phy_info *phy = &hw->phy;
845 s32 ret_val;
846 u16 data;
847
848 ret_val = e1000_phy_hw_reset(hw);
849 if (ret_val) {
850 e_dbg("Error resetting the PHY.\n");
851 return ret_val;
852 }
853
854 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
855 * timeout issues when LFS is enabled.
856 */
857 msleep(100);
858
859 /* disable lplu d0 during driver init */
860 if (hw->phy.ops.set_d0_lplu_state) {
861 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
862 if (ret_val) {
863 e_dbg("Error Disabling LPLU D0\n");
864 return ret_val;
865 }
866 }
867 /* Configure mdi-mdix settings */
868 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
869 if (ret_val)
870 return ret_val;
871
872 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
873
874 switch (phy->mdix) {
875 case 1:
876 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
877 break;
878 case 2:
879 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
880 break;
881 case 0:
882 default:
883 data |= IGP01E1000_PSCR_AUTO_MDIX;
884 break;
885 }
886 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
887 if (ret_val)
888 return ret_val;
889
890 /* set auto-master slave resolution settings */
891 if (hw->mac.autoneg) {
892 /* when autonegotiation advertisement is only 1000Mbps then we
893 * should disable SmartSpeed and enable Auto MasterSlave
894 * resolution as hardware default.
895 */
896 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
897 /* Disable SmartSpeed */
898 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
899 &data);
900 if (ret_val)
901 return ret_val;
902
903 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
904 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
905 data);
906 if (ret_val)
907 return ret_val;
908
909 /* Set auto Master/Slave resolution process */
910 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
911 if (ret_val)
912 return ret_val;
913
914 data &= ~CTL1000_ENABLE_MASTER;
915 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
916 if (ret_val)
917 return ret_val;
918 }
919
920 ret_val = e1000_set_master_slave_mode(hw);
921 }
922
923 return ret_val;
924}
925
926/**
927 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
928 * @hw: pointer to the HW structure
929 *
930 * Reads the MII auto-neg advertisement register and/or the 1000T control
931 * register and if the PHY is already setup for auto-negotiation, then
932 * return successful. Otherwise, setup advertisement and flow control to
933 * the appropriate values for the wanted auto-negotiation.
934 **/
935static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
936{
937 struct e1000_phy_info *phy = &hw->phy;
938 s32 ret_val;
939 u16 mii_autoneg_adv_reg;
940 u16 mii_1000t_ctrl_reg = 0;
941
942 phy->autoneg_advertised &= phy->autoneg_mask;
943
944 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
945 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
946 if (ret_val)
947 return ret_val;
948
949 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
950 /* Read the MII 1000Base-T Control Register (Address 9). */
951 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
952 if (ret_val)
953 return ret_val;
954 }
955
956 /* Need to parse both autoneg_advertised and fc and set up
957 * the appropriate PHY registers. First we will parse for
958 * autoneg_advertised software override. Since we can advertise
959 * a plethora of combinations, we need to check each bit
960 * individually.
961 */
962
963 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
964 * Advertisement Register (Address 4) and the 1000 mb speed bits in
965 * the 1000Base-T Control Register (Address 9).
966 */
967 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
968 ADVERTISE_100HALF |
969 ADVERTISE_10FULL | ADVERTISE_10HALF);
970 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
971
972 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
973
974 /* Do we want to advertise 10 Mb Half Duplex? */
975 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
976 e_dbg("Advertise 10mb Half duplex\n");
977 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
978 }
979
980 /* Do we want to advertise 10 Mb Full Duplex? */
981 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
982 e_dbg("Advertise 10mb Full duplex\n");
983 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
984 }
985
986 /* Do we want to advertise 100 Mb Half Duplex? */
987 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
988 e_dbg("Advertise 100mb Half duplex\n");
989 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
990 }
991
992 /* Do we want to advertise 100 Mb Full Duplex? */
993 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
994 e_dbg("Advertise 100mb Full duplex\n");
995 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
996 }
997
998 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
999 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1000 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1001
1002 /* Do we want to advertise 1000 Mb Full Duplex? */
1003 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1004 e_dbg("Advertise 1000mb Full duplex\n");
1005 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1006 }
1007
1008 /* Check for a software override of the flow control settings, and
1009 * setup the PHY advertisement registers accordingly. If
1010 * auto-negotiation is enabled, then software will have to set the
1011 * "PAUSE" bits to the correct value in the Auto-Negotiation
1012 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1013 * negotiation.
1014 *
1015 * The possible values of the "fc" parameter are:
1016 * 0: Flow control is completely disabled
1017 * 1: Rx flow control is enabled (we can receive pause frames
1018 * but not send pause frames).
1019 * 2: Tx flow control is enabled (we can send pause frames
1020 * but we do not support receiving pause frames).
1021 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1022 * other: No software override. The flow control configuration
1023 * in the EEPROM is used.
1024 */
1025 switch (hw->fc.current_mode) {
1026 case e1000_fc_none:
1027 /* Flow control (Rx & Tx) is completely disabled by a
1028 * software over-ride.
1029 */
1030 mii_autoneg_adv_reg &=
1031 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1032 break;
1033 case e1000_fc_rx_pause:
1034 /* Rx Flow control is enabled, and Tx Flow control is
1035 * disabled, by a software over-ride.
1036 *
1037 * Since there really isn't a way to advertise that we are
1038 * capable of Rx Pause ONLY, we will advertise that we
1039 * support both symmetric and asymmetric Rx PAUSE. Later
1040 * (in e1000e_config_fc_after_link_up) we will disable the
1041 * hw's ability to send PAUSE frames.
1042 */
1043 mii_autoneg_adv_reg |=
1044 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1045 break;
1046 case e1000_fc_tx_pause:
1047 /* Tx Flow control is enabled, and Rx Flow control is
1048 * disabled, by a software over-ride.
1049 */
1050 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1051 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1052 break;
1053 case e1000_fc_full:
1054 /* Flow control (both Rx and Tx) is enabled by a software
1055 * over-ride.
1056 */
1057 mii_autoneg_adv_reg |=
1058 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1059 break;
1060 default:
1061 e_dbg("Flow control param set incorrectly\n");
1062 return -E1000_ERR_CONFIG;
1063 }
1064
1065 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1066 if (ret_val)
1067 return ret_val;
1068
1069 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1070
1071 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1072 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1073
1074 return ret_val;
1075}
1076
1077/**
1078 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1079 * @hw: pointer to the HW structure
1080 *
1081 * Performs initial bounds checking on autoneg advertisement parameter, then
1082 * configure to advertise the full capability. Setup the PHY to autoneg
1083 * and restart the negotiation process between the link partner. If
1084 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1085 **/
1086static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1087{
1088 struct e1000_phy_info *phy = &hw->phy;
1089 s32 ret_val;
1090 u16 phy_ctrl;
1091
1092 /* Perform some bounds checking on the autoneg advertisement
1093 * parameter.
1094 */
1095 phy->autoneg_advertised &= phy->autoneg_mask;
1096
1097 /* If autoneg_advertised is zero, we assume it was not defaulted
1098 * by the calling code so we set to advertise full capability.
1099 */
1100 if (!phy->autoneg_advertised)
1101 phy->autoneg_advertised = phy->autoneg_mask;
1102
1103 e_dbg("Reconfiguring auto-neg advertisement params\n");
1104 ret_val = e1000_phy_setup_autoneg(hw);
1105 if (ret_val) {
1106 e_dbg("Error Setting up Auto-Negotiation\n");
1107 return ret_val;
1108 }
1109 e_dbg("Restarting Auto-Neg\n");
1110
1111 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1112 * the Auto Neg Restart bit in the PHY control register.
1113 */
1114 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1115 if (ret_val)
1116 return ret_val;
1117
1118 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1119 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1120 if (ret_val)
1121 return ret_val;
1122
1123 /* Does the user want to wait for Auto-Neg to complete here, or
1124 * check at a later time (for example, callback routine).
1125 */
1126 if (phy->autoneg_wait_to_complete) {
1127 ret_val = e1000_wait_autoneg(hw);
1128 if (ret_val) {
1129 e_dbg("Error while waiting for autoneg to complete\n");
1130 return ret_val;
1131 }
1132 }
1133
1134 hw->mac.get_link_status = true;
1135
1136 return ret_val;
1137}
1138
1139/**
1140 * e1000e_setup_copper_link - Configure copper link settings
1141 * @hw: pointer to the HW structure
1142 *
1143 * Calls the appropriate function to configure the link for auto-neg or forced
1144 * speed and duplex. Then we check for link, once link is established calls
1145 * to configure collision distance and flow control are called. If link is
1146 * not established, we return -E1000_ERR_PHY (-2).
1147 **/
1148s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1149{
1150 s32 ret_val;
1151 bool link;
1152
1153 if (hw->mac.autoneg) {
1154 /* Setup autoneg and flow control advertisement and perform
1155 * autonegotiation.
1156 */
1157 ret_val = e1000_copper_link_autoneg(hw);
1158 if (ret_val)
1159 return ret_val;
1160 } else {
1161 /* PHY will be set to 10H, 10F, 100H or 100F
1162 * depending on user settings.
1163 */
1164 e_dbg("Forcing Speed and Duplex\n");
1165 ret_val = hw->phy.ops.force_speed_duplex(hw);
1166 if (ret_val) {
1167 e_dbg("Error Forcing Speed and Duplex\n");
1168 return ret_val;
1169 }
1170 }
1171
1172 /* Check link status. Wait up to 100 microseconds for link to become
1173 * valid.
1174 */
1175 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1176 &link);
1177 if (ret_val)
1178 return ret_val;
1179
1180 if (link) {
1181 e_dbg("Valid link established!!!\n");
1182 hw->mac.ops.config_collision_dist(hw);
1183 ret_val = e1000e_config_fc_after_link_up(hw);
1184 } else {
1185 e_dbg("Unable to establish link!!!\n");
1186 }
1187
1188 return ret_val;
1189}
1190
1191/**
1192 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1193 * @hw: pointer to the HW structure
1194 *
1195 * Calls the PHY setup function to force speed and duplex. Clears the
1196 * auto-crossover to force MDI manually. Waits for link and returns
1197 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1198 **/
1199s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1200{
1201 struct e1000_phy_info *phy = &hw->phy;
1202 s32 ret_val;
1203 u16 phy_data;
1204 bool link;
1205
1206 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1207 if (ret_val)
1208 return ret_val;
1209
1210 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1211
1212 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1213 if (ret_val)
1214 return ret_val;
1215
1216 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1217 * forced whenever speed and duplex are forced.
1218 */
1219 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1220 if (ret_val)
1221 return ret_val;
1222
1223 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1224 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1225
1226 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1227 if (ret_val)
1228 return ret_val;
1229
1230 e_dbg("IGP PSCR: %X\n", phy_data);
1231
1232 udelay(1);
1233
1234 if (phy->autoneg_wait_to_complete) {
1235 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1236
1237 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1238 100000, &link);
1239 if (ret_val)
1240 return ret_val;
1241
1242 if (!link)
1243 e_dbg("Link taking longer than expected.\n");
1244
1245 /* Try once more */
1246 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1247 100000, &link);
1248 }
1249
1250 return ret_val;
1251}
1252
1253/**
1254 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1255 * @hw: pointer to the HW structure
1256 *
1257 * Calls the PHY setup function to force speed and duplex. Clears the
1258 * auto-crossover to force MDI manually. Resets the PHY to commit the
1259 * changes. If time expires while waiting for link up, we reset the DSP.
1260 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1261 * successful completion, else return corresponding error code.
1262 **/
1263s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1264{
1265 struct e1000_phy_info *phy = &hw->phy;
1266 s32 ret_val;
1267 u16 phy_data;
1268 bool link;
1269
1270 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1271 * forced whenever speed and duplex are forced.
1272 */
1273 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1274 if (ret_val)
1275 return ret_val;
1276
1277 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1278 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1279 if (ret_val)
1280 return ret_val;
1281
1282 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1283
1284 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1285 if (ret_val)
1286 return ret_val;
1287
1288 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1289
1290 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1291 if (ret_val)
1292 return ret_val;
1293
1294 /* Reset the phy to commit changes. */
1295 if (hw->phy.ops.commit) {
1296 ret_val = hw->phy.ops.commit(hw);
1297 if (ret_val)
1298 return ret_val;
1299 }
1300
1301 if (phy->autoneg_wait_to_complete) {
1302 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1303
1304 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1305 100000, &link);
1306 if (ret_val)
1307 return ret_val;
1308
1309 if (!link) {
1310 if (hw->phy.type != e1000_phy_m88) {
1311 e_dbg("Link taking longer than expected.\n");
1312 } else {
1313 /* We didn't get link.
1314 * Reset the DSP and cross our fingers.
1315 */
1316 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1317 0x001d);
1318 if (ret_val)
1319 return ret_val;
1320 ret_val = e1000e_phy_reset_dsp(hw);
1321 if (ret_val)
1322 return ret_val;
1323 }
1324 }
1325
1326 /* Try once more */
1327 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1328 100000, &link);
1329 if (ret_val)
1330 return ret_val;
1331 }
1332
1333 if (hw->phy.type != e1000_phy_m88)
1334 return 0;
1335
1336 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1337 if (ret_val)
1338 return ret_val;
1339
1340 /* Resetting the phy means we need to re-force TX_CLK in the
1341 * Extended PHY Specific Control Register to 25MHz clock from
1342 * the reset value of 2.5MHz.
1343 */
1344 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1345 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1346 if (ret_val)
1347 return ret_val;
1348
1349 /* In addition, we must re-enable CRS on Tx for both half and full
1350 * duplex.
1351 */
1352 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1353 if (ret_val)
1354 return ret_val;
1355
1356 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1357 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1358
1359 return ret_val;
1360}
1361
1362/**
1363 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1364 * @hw: pointer to the HW structure
1365 *
1366 * Forces the speed and duplex settings of the PHY.
1367 * This is a function pointer entry point only called by
1368 * PHY setup routines.
1369 **/
1370s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1371{
1372 struct e1000_phy_info *phy = &hw->phy;
1373 s32 ret_val;
1374 u16 data;
1375 bool link;
1376
1377 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1378 if (ret_val)
1379 return ret_val;
1380
1381 e1000e_phy_force_speed_duplex_setup(hw, &data);
1382
1383 ret_val = e1e_wphy(hw, MII_BMCR, data);
1384 if (ret_val)
1385 return ret_val;
1386
1387 /* Disable MDI-X support for 10/100 */
1388 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1389 if (ret_val)
1390 return ret_val;
1391
1392 data &= ~IFE_PMC_AUTO_MDIX;
1393 data &= ~IFE_PMC_FORCE_MDIX;
1394
1395 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1396 if (ret_val)
1397 return ret_val;
1398
1399 e_dbg("IFE PMC: %X\n", data);
1400
1401 udelay(1);
1402
1403 if (phy->autoneg_wait_to_complete) {
1404 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1405
1406 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1407 100000, &link);
1408 if (ret_val)
1409 return ret_val;
1410
1411 if (!link)
1412 e_dbg("Link taking longer than expected.\n");
1413
1414 /* Try once more */
1415 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1416 100000, &link);
1417 if (ret_val)
1418 return ret_val;
1419 }
1420
1421 return 0;
1422}
1423
1424/**
1425 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1426 * @hw: pointer to the HW structure
1427 * @phy_ctrl: pointer to current value of MII_BMCR
1428 *
1429 * Forces speed and duplex on the PHY by doing the following: disable flow
1430 * control, force speed/duplex on the MAC, disable auto speed detection,
1431 * disable auto-negotiation, configure duplex, configure speed, configure
1432 * the collision distance, write configuration to CTRL register. The
1433 * caller must write to the MII_BMCR register for these settings to
1434 * take affect.
1435 **/
1436void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1437{
1438 struct e1000_mac_info *mac = &hw->mac;
1439 u32 ctrl;
1440
1441 /* Turn off flow control when forcing speed/duplex */
1442 hw->fc.current_mode = e1000_fc_none;
1443
1444 /* Force speed/duplex on the mac */
1445 ctrl = er32(CTRL);
1446 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1447 ctrl &= ~E1000_CTRL_SPD_SEL;
1448
1449 /* Disable Auto Speed Detection */
1450 ctrl &= ~E1000_CTRL_ASDE;
1451
1452 /* Disable autoneg on the phy */
1453 *phy_ctrl &= ~BMCR_ANENABLE;
1454
1455 /* Forcing Full or Half Duplex? */
1456 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1457 ctrl &= ~E1000_CTRL_FD;
1458 *phy_ctrl &= ~BMCR_FULLDPLX;
1459 e_dbg("Half Duplex\n");
1460 } else {
1461 ctrl |= E1000_CTRL_FD;
1462 *phy_ctrl |= BMCR_FULLDPLX;
1463 e_dbg("Full Duplex\n");
1464 }
1465
1466 /* Forcing 10mb or 100mb? */
1467 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1468 ctrl |= E1000_CTRL_SPD_100;
1469 *phy_ctrl |= BMCR_SPEED100;
1470 *phy_ctrl &= ~BMCR_SPEED1000;
1471 e_dbg("Forcing 100mb\n");
1472 } else {
1473 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1474 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1475 e_dbg("Forcing 10mb\n");
1476 }
1477
1478 hw->mac.ops.config_collision_dist(hw);
1479
1480 ew32(CTRL, ctrl);
1481}
1482
1483/**
1484 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1485 * @hw: pointer to the HW structure
1486 * @active: boolean used to enable/disable lplu
1487 *
1488 * Success returns 0, Failure returns 1
1489 *
1490 * The low power link up (lplu) state is set to the power management level D3
1491 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1492 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1493 * is used during Dx states where the power conservation is most important.
1494 * During driver activity, SmartSpeed should be enabled so performance is
1495 * maintained.
1496 **/
1497s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1498{
1499 struct e1000_phy_info *phy = &hw->phy;
1500 s32 ret_val;
1501 u16 data;
1502
1503 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1504 if (ret_val)
1505 return ret_val;
1506
1507 if (!active) {
1508 data &= ~IGP02E1000_PM_D3_LPLU;
1509 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1510 if (ret_val)
1511 return ret_val;
1512 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1513 * during Dx states where the power conservation is most
1514 * important. During driver activity we should enable
1515 * SmartSpeed, so performance is maintained.
1516 */
1517 if (phy->smart_speed == e1000_smart_speed_on) {
1518 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1519 &data);
1520 if (ret_val)
1521 return ret_val;
1522
1523 data |= IGP01E1000_PSCFR_SMART_SPEED;
1524 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1525 data);
1526 if (ret_val)
1527 return ret_val;
1528 } else if (phy->smart_speed == e1000_smart_speed_off) {
1529 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1530 &data);
1531 if (ret_val)
1532 return ret_val;
1533
1534 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1535 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1536 data);
1537 if (ret_val)
1538 return ret_val;
1539 }
1540 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1541 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1542 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1543 data |= IGP02E1000_PM_D3_LPLU;
1544 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1545 if (ret_val)
1546 return ret_val;
1547
1548 /* When LPLU is enabled, we should disable SmartSpeed */
1549 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1550 if (ret_val)
1551 return ret_val;
1552
1553 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1554 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1555 }
1556
1557 return ret_val;
1558}
1559
1560/**
1561 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1562 * @hw: pointer to the HW structure
1563 *
1564 * Success returns 0, Failure returns 1
1565 *
1566 * A downshift is detected by querying the PHY link health.
1567 **/
1568s32 e1000e_check_downshift(struct e1000_hw *hw)
1569{
1570 struct e1000_phy_info *phy = &hw->phy;
1571 s32 ret_val;
1572 u16 phy_data, offset, mask;
1573
1574 switch (phy->type) {
1575 case e1000_phy_m88:
1576 case e1000_phy_gg82563:
1577 case e1000_phy_bm:
1578 case e1000_phy_82578:
1579 offset = M88E1000_PHY_SPEC_STATUS;
1580 mask = M88E1000_PSSR_DOWNSHIFT;
1581 break;
1582 case e1000_phy_igp_2:
1583 case e1000_phy_igp_3:
1584 offset = IGP01E1000_PHY_LINK_HEALTH;
1585 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1586 break;
1587 default:
1588 /* speed downshift not supported */
1589 phy->speed_downgraded = false;
1590 return 0;
1591 }
1592
1593 ret_val = e1e_rphy(hw, offset, &phy_data);
1594
1595 if (!ret_val)
1596 phy->speed_downgraded = !!(phy_data & mask);
1597
1598 return ret_val;
1599}
1600
1601/**
1602 * e1000_check_polarity_m88 - Checks the polarity.
1603 * @hw: pointer to the HW structure
1604 *
1605 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1606 *
1607 * Polarity is determined based on the PHY specific status register.
1608 **/
1609s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1610{
1611 struct e1000_phy_info *phy = &hw->phy;
1612 s32 ret_val;
1613 u16 data;
1614
1615 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1616
1617 if (!ret_val)
1618 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1619 ? e1000_rev_polarity_reversed
1620 : e1000_rev_polarity_normal);
1621
1622 return ret_val;
1623}
1624
1625/**
1626 * e1000_check_polarity_igp - Checks the polarity.
1627 * @hw: pointer to the HW structure
1628 *
1629 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1630 *
1631 * Polarity is determined based on the PHY port status register, and the
1632 * current speed (since there is no polarity at 100Mbps).
1633 **/
1634s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1635{
1636 struct e1000_phy_info *phy = &hw->phy;
1637 s32 ret_val;
1638 u16 data, offset, mask;
1639
1640 /* Polarity is determined based on the speed of
1641 * our connection.
1642 */
1643 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1644 if (ret_val)
1645 return ret_val;
1646
1647 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1648 IGP01E1000_PSSR_SPEED_1000MBPS) {
1649 offset = IGP01E1000_PHY_PCS_INIT_REG;
1650 mask = IGP01E1000_PHY_POLARITY_MASK;
1651 } else {
1652 /* This really only applies to 10Mbps since
1653 * there is no polarity for 100Mbps (always 0).
1654 */
1655 offset = IGP01E1000_PHY_PORT_STATUS;
1656 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1657 }
1658
1659 ret_val = e1e_rphy(hw, offset, &data);
1660
1661 if (!ret_val)
1662 phy->cable_polarity = ((data & mask)
1663 ? e1000_rev_polarity_reversed
1664 : e1000_rev_polarity_normal);
1665
1666 return ret_val;
1667}
1668
1669/**
1670 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1671 * @hw: pointer to the HW structure
1672 *
1673 * Polarity is determined on the polarity reversal feature being enabled.
1674 **/
1675s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1676{
1677 struct e1000_phy_info *phy = &hw->phy;
1678 s32 ret_val;
1679 u16 phy_data, offset, mask;
1680
1681 /* Polarity is determined based on the reversal feature being enabled.
1682 */
1683 if (phy->polarity_correction) {
1684 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1685 mask = IFE_PESC_POLARITY_REVERSED;
1686 } else {
1687 offset = IFE_PHY_SPECIAL_CONTROL;
1688 mask = IFE_PSC_FORCE_POLARITY;
1689 }
1690
1691 ret_val = e1e_rphy(hw, offset, &phy_data);
1692
1693 if (!ret_val)
1694 phy->cable_polarity = ((phy_data & mask)
1695 ? e1000_rev_polarity_reversed
1696 : e1000_rev_polarity_normal);
1697
1698 return ret_val;
1699}
1700
1701/**
1702 * e1000_wait_autoneg - Wait for auto-neg completion
1703 * @hw: pointer to the HW structure
1704 *
1705 * Waits for auto-negotiation to complete or for the auto-negotiation time
1706 * limit to expire, which ever happens first.
1707 **/
1708static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1709{
1710 s32 ret_val = 0;
1711 u16 i, phy_status;
1712
1713 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1714 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1715 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1716 if (ret_val)
1717 break;
1718 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1719 if (ret_val)
1720 break;
1721 if (phy_status & BMSR_ANEGCOMPLETE)
1722 break;
1723 msleep(100);
1724 }
1725
1726 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1727 * has completed.
1728 */
1729 return ret_val;
1730}
1731
1732/**
1733 * e1000e_phy_has_link_generic - Polls PHY for link
1734 * @hw: pointer to the HW structure
1735 * @iterations: number of times to poll for link
1736 * @usec_interval: delay between polling attempts
1737 * @success: pointer to whether polling was successful or not
1738 *
1739 * Polls the PHY status register for link, 'iterations' number of times.
1740 **/
1741s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1742 u32 usec_interval, bool *success)
1743{
1744 s32 ret_val = 0;
1745 u16 i, phy_status;
1746
1747 for (i = 0; i < iterations; i++) {
1748 /* Some PHYs require the MII_BMSR register to be read
1749 * twice due to the link bit being sticky. No harm doing
1750 * it across the board.
1751 */
1752 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1753 if (ret_val) {
1754 /* If the first read fails, another entity may have
1755 * ownership of the resources, wait and try again to
1756 * see if they have relinquished the resources yet.
1757 */
1758 if (usec_interval >= 1000)
1759 msleep(usec_interval / 1000);
1760 else
1761 udelay(usec_interval);
1762 }
1763 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1764 if (ret_val)
1765 break;
1766 if (phy_status & BMSR_LSTATUS)
1767 break;
1768 if (usec_interval >= 1000)
1769 msleep(usec_interval / 1000);
1770 else
1771 udelay(usec_interval);
1772 }
1773
1774 *success = (i < iterations);
1775
1776 return ret_val;
1777}
1778
1779/**
1780 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1781 * @hw: pointer to the HW structure
1782 *
1783 * Reads the PHY specific status register to retrieve the cable length
1784 * information. The cable length is determined by averaging the minimum and
1785 * maximum values to get the "average" cable length. The m88 PHY has four
1786 * possible cable length values, which are:
1787 * Register Value Cable Length
1788 * 0 < 50 meters
1789 * 1 50 - 80 meters
1790 * 2 80 - 110 meters
1791 * 3 110 - 140 meters
1792 * 4 > 140 meters
1793 **/
1794s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1795{
1796 struct e1000_phy_info *phy = &hw->phy;
1797 s32 ret_val;
1798 u16 phy_data, index;
1799
1800 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1801 if (ret_val)
1802 return ret_val;
1803
1804 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1805 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1806
1807 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1808 return -E1000_ERR_PHY;
1809
1810 phy->min_cable_length = e1000_m88_cable_length_table[index];
1811 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1812
1813 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1814
1815 return 0;
1816}
1817
1818/**
1819 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1820 * @hw: pointer to the HW structure
1821 *
1822 * The automatic gain control (agc) normalizes the amplitude of the
1823 * received signal, adjusting for the attenuation produced by the
1824 * cable. By reading the AGC registers, which represent the
1825 * combination of coarse and fine gain value, the value can be put
1826 * into a lookup table to obtain the approximate cable length
1827 * for each channel.
1828 **/
1829s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1830{
1831 struct e1000_phy_info *phy = &hw->phy;
1832 s32 ret_val;
1833 u16 phy_data, i, agc_value = 0;
1834 u16 cur_agc_index, max_agc_index = 0;
1835 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1836 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1837 IGP02E1000_PHY_AGC_A,
1838 IGP02E1000_PHY_AGC_B,
1839 IGP02E1000_PHY_AGC_C,
1840 IGP02E1000_PHY_AGC_D
1841 };
1842
1843 /* Read the AGC registers for all channels */
1844 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1845 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1846 if (ret_val)
1847 return ret_val;
1848
1849 /* Getting bits 15:9, which represent the combination of
1850 * coarse and fine gain values. The result is a number
1851 * that can be put into the lookup table to obtain the
1852 * approximate cable length.
1853 */
1854 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1855 IGP02E1000_AGC_LENGTH_MASK);
1856
1857 /* Array index bound check. */
1858 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1859 (cur_agc_index == 0))
1860 return -E1000_ERR_PHY;
1861
1862 /* Remove min & max AGC values from calculation. */
1863 if (e1000_igp_2_cable_length_table[min_agc_index] >
1864 e1000_igp_2_cable_length_table[cur_agc_index])
1865 min_agc_index = cur_agc_index;
1866 if (e1000_igp_2_cable_length_table[max_agc_index] <
1867 e1000_igp_2_cable_length_table[cur_agc_index])
1868 max_agc_index = cur_agc_index;
1869
1870 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1871 }
1872
1873 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1874 e1000_igp_2_cable_length_table[max_agc_index]);
1875 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1876
1877 /* Calculate cable length with the error range of +/- 10 meters. */
1878 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1879 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1880 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1881
1882 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1883
1884 return 0;
1885}
1886
1887/**
1888 * e1000e_get_phy_info_m88 - Retrieve PHY information
1889 * @hw: pointer to the HW structure
1890 *
1891 * Valid for only copper links. Read the PHY status register (sticky read)
1892 * to verify that link is up. Read the PHY special control register to
1893 * determine the polarity and 10base-T extended distance. Read the PHY
1894 * special status register to determine MDI/MDIx and current speed. If
1895 * speed is 1000, then determine cable length, local and remote receiver.
1896 **/
1897s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1898{
1899 struct e1000_phy_info *phy = &hw->phy;
1900 s32 ret_val;
1901 u16 phy_data;
1902 bool link;
1903
1904 if (phy->media_type != e1000_media_type_copper) {
1905 e_dbg("Phy info is only valid for copper media\n");
1906 return -E1000_ERR_CONFIG;
1907 }
1908
1909 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1910 if (ret_val)
1911 return ret_val;
1912
1913 if (!link) {
1914 e_dbg("Phy info is only valid if link is up\n");
1915 return -E1000_ERR_CONFIG;
1916 }
1917
1918 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1919 if (ret_val)
1920 return ret_val;
1921
1922 phy->polarity_correction = !!(phy_data &
1923 M88E1000_PSCR_POLARITY_REVERSAL);
1924
1925 ret_val = e1000_check_polarity_m88(hw);
1926 if (ret_val)
1927 return ret_val;
1928
1929 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1930 if (ret_val)
1931 return ret_val;
1932
1933 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1934
1935 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1936 ret_val = hw->phy.ops.get_cable_length(hw);
1937 if (ret_val)
1938 return ret_val;
1939
1940 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1941 if (ret_val)
1942 return ret_val;
1943
1944 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1945 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1946
1947 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1948 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1949 } else {
1950 /* Set values to "undefined" */
1951 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1952 phy->local_rx = e1000_1000t_rx_status_undefined;
1953 phy->remote_rx = e1000_1000t_rx_status_undefined;
1954 }
1955
1956 return ret_val;
1957}
1958
1959/**
1960 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1961 * @hw: pointer to the HW structure
1962 *
1963 * Read PHY status to determine if link is up. If link is up, then
1964 * set/determine 10base-T extended distance and polarity correction. Read
1965 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1966 * determine on the cable length, local and remote receiver.
1967 **/
1968s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1969{
1970 struct e1000_phy_info *phy = &hw->phy;
1971 s32 ret_val;
1972 u16 data;
1973 bool link;
1974
1975 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1976 if (ret_val)
1977 return ret_val;
1978
1979 if (!link) {
1980 e_dbg("Phy info is only valid if link is up\n");
1981 return -E1000_ERR_CONFIG;
1982 }
1983
1984 phy->polarity_correction = true;
1985
1986 ret_val = e1000_check_polarity_igp(hw);
1987 if (ret_val)
1988 return ret_val;
1989
1990 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1991 if (ret_val)
1992 return ret_val;
1993
1994 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1995
1996 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1997 IGP01E1000_PSSR_SPEED_1000MBPS) {
1998 ret_val = phy->ops.get_cable_length(hw);
1999 if (ret_val)
2000 return ret_val;
2001
2002 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
2003 if (ret_val)
2004 return ret_val;
2005
2006 phy->local_rx = (data & LPA_1000LOCALRXOK)
2007 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2008
2009 phy->remote_rx = (data & LPA_1000REMRXOK)
2010 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2011 } else {
2012 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2013 phy->local_rx = e1000_1000t_rx_status_undefined;
2014 phy->remote_rx = e1000_1000t_rx_status_undefined;
2015 }
2016
2017 return ret_val;
2018}
2019
2020/**
2021 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2022 * @hw: pointer to the HW structure
2023 *
2024 * Populates "phy" structure with various feature states.
2025 **/
2026s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2027{
2028 struct e1000_phy_info *phy = &hw->phy;
2029 s32 ret_val;
2030 u16 data;
2031 bool link;
2032
2033 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2034 if (ret_val)
2035 return ret_val;
2036
2037 if (!link) {
2038 e_dbg("Phy info is only valid if link is up\n");
2039 return -E1000_ERR_CONFIG;
2040 }
2041
2042 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2043 if (ret_val)
2044 return ret_val;
2045 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2046
2047 if (phy->polarity_correction) {
2048 ret_val = e1000_check_polarity_ife(hw);
2049 if (ret_val)
2050 return ret_val;
2051 } else {
2052 /* Polarity is forced */
2053 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2054 ? e1000_rev_polarity_reversed
2055 : e1000_rev_polarity_normal);
2056 }
2057
2058 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2059 if (ret_val)
2060 return ret_val;
2061
2062 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2063
2064 /* The following parameters are undefined for 10/100 operation. */
2065 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2066 phy->local_rx = e1000_1000t_rx_status_undefined;
2067 phy->remote_rx = e1000_1000t_rx_status_undefined;
2068
2069 return 0;
2070}
2071
2072/**
2073 * e1000e_phy_sw_reset - PHY software reset
2074 * @hw: pointer to the HW structure
2075 *
2076 * Does a software reset of the PHY by reading the PHY control register and
2077 * setting/write the control register reset bit to the PHY.
2078 **/
2079s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2080{
2081 s32 ret_val;
2082 u16 phy_ctrl;
2083
2084 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2085 if (ret_val)
2086 return ret_val;
2087
2088 phy_ctrl |= BMCR_RESET;
2089 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2090 if (ret_val)
2091 return ret_val;
2092
2093 udelay(1);
2094
2095 return ret_val;
2096}
2097
2098/**
2099 * e1000e_phy_hw_reset_generic - PHY hardware reset
2100 * @hw: pointer to the HW structure
2101 *
2102 * Verify the reset block is not blocking us from resetting. Acquire
2103 * semaphore (if necessary) and read/set/write the device control reset
2104 * bit in the PHY. Wait the appropriate delay time for the device to
2105 * reset and release the semaphore (if necessary).
2106 **/
2107s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2108{
2109 struct e1000_phy_info *phy = &hw->phy;
2110 s32 ret_val;
2111 u32 ctrl;
2112
2113 if (phy->ops.check_reset_block) {
2114 ret_val = phy->ops.check_reset_block(hw);
2115 if (ret_val)
2116 return 0;
2117 }
2118
2119 ret_val = phy->ops.acquire(hw);
2120 if (ret_val)
2121 return ret_val;
2122
2123 ctrl = er32(CTRL);
2124 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2125 e1e_flush();
2126
2127 udelay(phy->reset_delay_us);
2128
2129 ew32(CTRL, ctrl);
2130 e1e_flush();
2131
2132 usleep_range(150, 300);
2133
2134 phy->ops.release(hw);
2135
2136 return phy->ops.get_cfg_done(hw);
2137}
2138
2139/**
2140 * e1000e_get_cfg_done_generic - Generic configuration done
2141 * @hw: pointer to the HW structure
2142 *
2143 * Generic function to wait 10 milli-seconds for configuration to complete
2144 * and return success.
2145 **/
2146s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2147{
2148 mdelay(10);
2149
2150 return 0;
2151}
2152
2153/**
2154 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2155 * @hw: pointer to the HW structure
2156 *
2157 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2158 **/
2159s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2160{
2161 e_dbg("Running IGP 3 PHY init script\n");
2162
2163 /* PHY init IGP 3 */
2164 /* Enable rise/fall, 10-mode work in class-A */
2165 e1e_wphy(hw, 0x2F5B, 0x9018);
2166 /* Remove all caps from Replica path filter */
2167 e1e_wphy(hw, 0x2F52, 0x0000);
2168 /* Bias trimming for ADC, AFE and Driver (Default) */
2169 e1e_wphy(hw, 0x2FB1, 0x8B24);
2170 /* Increase Hybrid poly bias */
2171 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2172 /* Add 4% to Tx amplitude in Gig mode */
2173 e1e_wphy(hw, 0x2010, 0x10B0);
2174 /* Disable trimming (TTT) */
2175 e1e_wphy(hw, 0x2011, 0x0000);
2176 /* Poly DC correction to 94.6% + 2% for all channels */
2177 e1e_wphy(hw, 0x20DD, 0x249A);
2178 /* ABS DC correction to 95.9% */
2179 e1e_wphy(hw, 0x20DE, 0x00D3);
2180 /* BG temp curve trim */
2181 e1e_wphy(hw, 0x28B4, 0x04CE);
2182 /* Increasing ADC OPAMP stage 1 currents to max */
2183 e1e_wphy(hw, 0x2F70, 0x29E4);
2184 /* Force 1000 ( required for enabling PHY regs configuration) */
2185 e1e_wphy(hw, 0x0000, 0x0140);
2186 /* Set upd_freq to 6 */
2187 e1e_wphy(hw, 0x1F30, 0x1606);
2188 /* Disable NPDFE */
2189 e1e_wphy(hw, 0x1F31, 0xB814);
2190 /* Disable adaptive fixed FFE (Default) */
2191 e1e_wphy(hw, 0x1F35, 0x002A);
2192 /* Enable FFE hysteresis */
2193 e1e_wphy(hw, 0x1F3E, 0x0067);
2194 /* Fixed FFE for short cable lengths */
2195 e1e_wphy(hw, 0x1F54, 0x0065);
2196 /* Fixed FFE for medium cable lengths */
2197 e1e_wphy(hw, 0x1F55, 0x002A);
2198 /* Fixed FFE for long cable lengths */
2199 e1e_wphy(hw, 0x1F56, 0x002A);
2200 /* Enable Adaptive Clip Threshold */
2201 e1e_wphy(hw, 0x1F72, 0x3FB0);
2202 /* AHT reset limit to 1 */
2203 e1e_wphy(hw, 0x1F76, 0xC0FF);
2204 /* Set AHT master delay to 127 msec */
2205 e1e_wphy(hw, 0x1F77, 0x1DEC);
2206 /* Set scan bits for AHT */
2207 e1e_wphy(hw, 0x1F78, 0xF9EF);
2208 /* Set AHT Preset bits */
2209 e1e_wphy(hw, 0x1F79, 0x0210);
2210 /* Change integ_factor of channel A to 3 */
2211 e1e_wphy(hw, 0x1895, 0x0003);
2212 /* Change prop_factor of channels BCD to 8 */
2213 e1e_wphy(hw, 0x1796, 0x0008);
2214 /* Change cg_icount + enable integbp for channels BCD */
2215 e1e_wphy(hw, 0x1798, 0xD008);
2216 /* Change cg_icount + enable integbp + change prop_factor_master
2217 * to 8 for channel A
2218 */
2219 e1e_wphy(hw, 0x1898, 0xD918);
2220 /* Disable AHT in Slave mode on channel A */
2221 e1e_wphy(hw, 0x187A, 0x0800);
2222 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2223 * Enable SPD+B2B
2224 */
2225 e1e_wphy(hw, 0x0019, 0x008D);
2226 /* Enable restart AN on an1000_dis change */
2227 e1e_wphy(hw, 0x001B, 0x2080);
2228 /* Enable wh_fifo read clock in 10/100 modes */
2229 e1e_wphy(hw, 0x0014, 0x0045);
2230 /* Restart AN, Speed selection is 1000 */
2231 e1e_wphy(hw, 0x0000, 0x1340);
2232
2233 return 0;
2234}
2235
2236/**
2237 * e1000e_get_phy_type_from_id - Get PHY type from id
2238 * @phy_id: phy_id read from the phy
2239 *
2240 * Returns the phy type from the id.
2241 **/
2242enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2243{
2244 enum e1000_phy_type phy_type = e1000_phy_unknown;
2245
2246 switch (phy_id) {
2247 case M88E1000_I_PHY_ID:
2248 case M88E1000_E_PHY_ID:
2249 case M88E1111_I_PHY_ID:
2250 case M88E1011_I_PHY_ID:
2251 phy_type = e1000_phy_m88;
2252 break;
2253 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2254 phy_type = e1000_phy_igp_2;
2255 break;
2256 case GG82563_E_PHY_ID:
2257 phy_type = e1000_phy_gg82563;
2258 break;
2259 case IGP03E1000_E_PHY_ID:
2260 phy_type = e1000_phy_igp_3;
2261 break;
2262 case IFE_E_PHY_ID:
2263 case IFE_PLUS_E_PHY_ID:
2264 case IFE_C_E_PHY_ID:
2265 phy_type = e1000_phy_ife;
2266 break;
2267 case BME1000_E_PHY_ID:
2268 case BME1000_E_PHY_ID_R2:
2269 phy_type = e1000_phy_bm;
2270 break;
2271 case I82578_E_PHY_ID:
2272 phy_type = e1000_phy_82578;
2273 break;
2274 case I82577_E_PHY_ID:
2275 phy_type = e1000_phy_82577;
2276 break;
2277 case I82579_E_PHY_ID:
2278 phy_type = e1000_phy_82579;
2279 break;
2280 case I217_E_PHY_ID:
2281 phy_type = e1000_phy_i217;
2282 break;
2283 default:
2284 phy_type = e1000_phy_unknown;
2285 break;
2286 }
2287 return phy_type;
2288}
2289
2290/**
2291 * e1000e_determine_phy_address - Determines PHY address.
2292 * @hw: pointer to the HW structure
2293 *
2294 * This uses a trial and error method to loop through possible PHY
2295 * addresses. It tests each by reading the PHY ID registers and
2296 * checking for a match.
2297 **/
2298s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2299{
2300 u32 phy_addr = 0;
2301 u32 i;
2302 enum e1000_phy_type phy_type = e1000_phy_unknown;
2303
2304 hw->phy.id = phy_type;
2305
2306 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2307 hw->phy.addr = phy_addr;
2308 i = 0;
2309
2310 do {
2311 e1000e_get_phy_id(hw);
2312 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2313
2314 /* If phy_type is valid, break - we found our
2315 * PHY address
2316 */
2317 if (phy_type != e1000_phy_unknown)
2318 return 0;
2319
2320 usleep_range(1000, 2000);
2321 i++;
2322 } while (i < 10);
2323 }
2324
2325 return -E1000_ERR_PHY_TYPE;
2326}
2327
2328/**
2329 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2330 * @page: page to access
2331 *
2332 * Returns the phy address for the page requested.
2333 **/
2334static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2335{
2336 u32 phy_addr = 2;
2337
2338 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2339 phy_addr = 1;
2340
2341 return phy_addr;
2342}
2343
2344/**
2345 * e1000e_write_phy_reg_bm - Write BM PHY register
2346 * @hw: pointer to the HW structure
2347 * @offset: register offset to write to
2348 * @data: data to write at register offset
2349 *
2350 * Acquires semaphore, if necessary, then writes the data to PHY register
2351 * at the offset. Release any acquired semaphores before exiting.
2352 **/
2353s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2354{
2355 s32 ret_val;
2356 u32 page = offset >> IGP_PAGE_SHIFT;
2357
2358 ret_val = hw->phy.ops.acquire(hw);
2359 if (ret_val)
2360 return ret_val;
2361
2362 /* Page 800 works differently than the rest so it has its own func */
2363 if (page == BM_WUC_PAGE) {
2364 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2365 false, false);
2366 goto release;
2367 }
2368
2369 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2370
2371 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2372 u32 page_shift, page_select;
2373
2374 /* Page select is register 31 for phy address 1 and 22 for
2375 * phy address 2 and 3. Page select is shifted only for
2376 * phy address 1.
2377 */
2378 if (hw->phy.addr == 1) {
2379 page_shift = IGP_PAGE_SHIFT;
2380 page_select = IGP01E1000_PHY_PAGE_SELECT;
2381 } else {
2382 page_shift = 0;
2383 page_select = BM_PHY_PAGE_SELECT;
2384 }
2385
2386 /* Page is shifted left, PHY expects (page x 32) */
2387 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2388 (page << page_shift));
2389 if (ret_val)
2390 goto release;
2391 }
2392
2393 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2394 data);
2395
2396release:
2397 hw->phy.ops.release(hw);
2398 return ret_val;
2399}
2400
2401/**
2402 * e1000e_read_phy_reg_bm - Read BM PHY register
2403 * @hw: pointer to the HW structure
2404 * @offset: register offset to be read
2405 * @data: pointer to the read data
2406 *
2407 * Acquires semaphore, if necessary, then reads the PHY register at offset
2408 * and storing the retrieved information in data. Release any acquired
2409 * semaphores before exiting.
2410 **/
2411s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2412{
2413 s32 ret_val;
2414 u32 page = offset >> IGP_PAGE_SHIFT;
2415
2416 ret_val = hw->phy.ops.acquire(hw);
2417 if (ret_val)
2418 return ret_val;
2419
2420 /* Page 800 works differently than the rest so it has its own func */
2421 if (page == BM_WUC_PAGE) {
2422 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2423 true, false);
2424 goto release;
2425 }
2426
2427 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2428
2429 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2430 u32 page_shift, page_select;
2431
2432 /* Page select is register 31 for phy address 1 and 22 for
2433 * phy address 2 and 3. Page select is shifted only for
2434 * phy address 1.
2435 */
2436 if (hw->phy.addr == 1) {
2437 page_shift = IGP_PAGE_SHIFT;
2438 page_select = IGP01E1000_PHY_PAGE_SELECT;
2439 } else {
2440 page_shift = 0;
2441 page_select = BM_PHY_PAGE_SELECT;
2442 }
2443
2444 /* Page is shifted left, PHY expects (page x 32) */
2445 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2446 (page << page_shift));
2447 if (ret_val)
2448 goto release;
2449 }
2450
2451 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2452 data);
2453release:
2454 hw->phy.ops.release(hw);
2455 return ret_val;
2456}
2457
2458/**
2459 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2460 * @hw: pointer to the HW structure
2461 * @offset: register offset to be read
2462 * @data: pointer to the read data
2463 *
2464 * Acquires semaphore, if necessary, then reads the PHY register at offset
2465 * and storing the retrieved information in data. Release any acquired
2466 * semaphores before exiting.
2467 **/
2468s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2469{
2470 s32 ret_val;
2471 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2472
2473 ret_val = hw->phy.ops.acquire(hw);
2474 if (ret_val)
2475 return ret_val;
2476
2477 /* Page 800 works differently than the rest so it has its own func */
2478 if (page == BM_WUC_PAGE) {
2479 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2480 true, false);
2481 goto release;
2482 }
2483
2484 hw->phy.addr = 1;
2485
2486 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2487 /* Page is shifted left, PHY expects (page x 32) */
2488 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2489 page);
2490
2491 if (ret_val)
2492 goto release;
2493 }
2494
2495 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2496 data);
2497release:
2498 hw->phy.ops.release(hw);
2499 return ret_val;
2500}
2501
2502/**
2503 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2504 * @hw: pointer to the HW structure
2505 * @offset: register offset to write to
2506 * @data: data to write at register offset
2507 *
2508 * Acquires semaphore, if necessary, then writes the data to PHY register
2509 * at the offset. Release any acquired semaphores before exiting.
2510 **/
2511s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2512{
2513 s32 ret_val;
2514 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2515
2516 ret_val = hw->phy.ops.acquire(hw);
2517 if (ret_val)
2518 return ret_val;
2519
2520 /* Page 800 works differently than the rest so it has its own func */
2521 if (page == BM_WUC_PAGE) {
2522 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2523 false, false);
2524 goto release;
2525 }
2526
2527 hw->phy.addr = 1;
2528
2529 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2530 /* Page is shifted left, PHY expects (page x 32) */
2531 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2532 page);
2533
2534 if (ret_val)
2535 goto release;
2536 }
2537
2538 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2539 data);
2540
2541release:
2542 hw->phy.ops.release(hw);
2543 return ret_val;
2544}
2545
2546/**
2547 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2548 * @hw: pointer to the HW structure
2549 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2550 *
2551 * Assumes semaphore already acquired and phy_reg points to a valid memory
2552 * address to store contents of the BM_WUC_ENABLE_REG register.
2553 **/
2554s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2555{
2556 s32 ret_val;
2557 u16 temp;
2558
2559 /* All page select, port ctrl and wakeup registers use phy address 1 */
2560 hw->phy.addr = 1;
2561
2562 /* Select Port Control Registers page */
2563 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2564 if (ret_val) {
2565 e_dbg("Could not set Port Control page\n");
2566 return ret_val;
2567 }
2568
2569 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2570 if (ret_val) {
2571 e_dbg("Could not read PHY register %d.%d\n",
2572 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2573 return ret_val;
2574 }
2575
2576 /* Enable both PHY wakeup mode and Wakeup register page writes.
2577 * Prevent a power state change by disabling ME and Host PHY wakeup.
2578 */
2579 temp = *phy_reg;
2580 temp |= BM_WUC_ENABLE_BIT;
2581 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2582
2583 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2584 if (ret_val) {
2585 e_dbg("Could not write PHY register %d.%d\n",
2586 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2587 return ret_val;
2588 }
2589
2590 /* Select Host Wakeup Registers page - caller now able to write
2591 * registers on the Wakeup registers page
2592 */
2593 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2594}
2595
2596/**
2597 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2598 * @hw: pointer to the HW structure
2599 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2600 *
2601 * Restore BM_WUC_ENABLE_REG to its original value.
2602 *
2603 * Assumes semaphore already acquired and *phy_reg is the contents of the
2604 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2605 * caller.
2606 **/
2607s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2608{
2609 s32 ret_val;
2610
2611 /* Select Port Control Registers page */
2612 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2613 if (ret_val) {
2614 e_dbg("Could not set Port Control page\n");
2615 return ret_val;
2616 }
2617
2618 /* Restore 769.17 to its original value */
2619 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2620 if (ret_val)
2621 e_dbg("Could not restore PHY register %d.%d\n",
2622 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2623
2624 return ret_val;
2625}
2626
2627/**
2628 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2629 * @hw: pointer to the HW structure
2630 * @offset: register offset to be read or written
2631 * @data: pointer to the data to read or write
2632 * @read: determines if operation is read or write
2633 * @page_set: BM_WUC_PAGE already set and access enabled
2634 *
2635 * Read the PHY register at offset and store the retrieved information in
2636 * data, or write data to PHY register at offset. Note the procedure to
2637 * access the PHY wakeup registers is different than reading the other PHY
2638 * registers. It works as such:
2639 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2640 * 2) Set page to 800 for host (801 if we were manageability)
2641 * 3) Write the address using the address opcode (0x11)
2642 * 4) Read or write the data using the data opcode (0x12)
2643 * 5) Restore 769.17.2 to its original value
2644 *
2645 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2646 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2647 *
2648 * Assumes semaphore is already acquired. When page_set==true, assumes
2649 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2650 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2651 **/
2652static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2653 u16 *data, bool read, bool page_set)
2654{
2655 s32 ret_val;
2656 u16 reg = BM_PHY_REG_NUM(offset);
2657 u16 page = BM_PHY_REG_PAGE(offset);
2658 u16 phy_reg = 0;
2659
2660 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2661 if ((hw->mac.type == e1000_pchlan) &&
2662 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2663 e_dbg("Attempting to access page %d while gig enabled.\n",
2664 page);
2665
2666 if (!page_set) {
2667 /* Enable access to PHY wakeup registers */
2668 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2669 if (ret_val) {
2670 e_dbg("Could not enable PHY wakeup reg access\n");
2671 return ret_val;
2672 }
2673 }
2674
2675 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2676
2677 /* Write the Wakeup register page offset value using opcode 0x11 */
2678 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2679 if (ret_val) {
2680 e_dbg("Could not write address opcode to page %d\n", page);
2681 return ret_val;
2682 }
2683
2684 if (read) {
2685 /* Read the Wakeup register page value using opcode 0x12 */
2686 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2687 data);
2688 } else {
2689 /* Write the Wakeup register page value using opcode 0x12 */
2690 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2691 *data);
2692 }
2693
2694 if (ret_val) {
2695 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2696 return ret_val;
2697 }
2698
2699 if (!page_set)
2700 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2701
2702 return ret_val;
2703}
2704
2705/**
2706 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2707 * @hw: pointer to the HW structure
2708 *
2709 * In the case of a PHY power down to save power, or to turn off link during a
2710 * driver unload, or wake on lan is not enabled, restore the link to previous
2711 * settings.
2712 **/
2713void e1000_power_up_phy_copper(struct e1000_hw *hw)
2714{
2715 u16 mii_reg = 0;
2716
2717 /* The PHY will retain its settings across a power down/up cycle */
2718 e1e_rphy(hw, MII_BMCR, &mii_reg);
2719 mii_reg &= ~BMCR_PDOWN;
2720 e1e_wphy(hw, MII_BMCR, mii_reg);
2721}
2722
2723/**
2724 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2725 * @hw: pointer to the HW structure
2726 *
2727 * In the case of a PHY power down to save power, or to turn off link during a
2728 * driver unload, or wake on lan is not enabled, restore the link to previous
2729 * settings.
2730 **/
2731void e1000_power_down_phy_copper(struct e1000_hw *hw)
2732{
2733 u16 mii_reg = 0;
2734
2735 /* The PHY will retain its settings across a power down/up cycle */
2736 e1e_rphy(hw, MII_BMCR, &mii_reg);
2737 mii_reg |= BMCR_PDOWN;
2738 e1e_wphy(hw, MII_BMCR, mii_reg);
2739 usleep_range(1000, 2000);
2740}
2741
2742/**
2743 * __e1000_read_phy_reg_hv - Read HV PHY register
2744 * @hw: pointer to the HW structure
2745 * @offset: register offset to be read
2746 * @data: pointer to the read data
2747 * @locked: semaphore has already been acquired or not
2748 *
2749 * Acquires semaphore, if necessary, then reads the PHY register at offset
2750 * and stores the retrieved information in data. Release any acquired
2751 * semaphore before exiting.
2752 **/
2753static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2754 bool locked, bool page_set)
2755{
2756 s32 ret_val;
2757 u16 page = BM_PHY_REG_PAGE(offset);
2758 u16 reg = BM_PHY_REG_NUM(offset);
2759 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2760
2761 if (!locked) {
2762 ret_val = hw->phy.ops.acquire(hw);
2763 if (ret_val)
2764 return ret_val;
2765 }
2766
2767 /* Page 800 works differently than the rest so it has its own func */
2768 if (page == BM_WUC_PAGE) {
2769 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2770 true, page_set);
2771 goto out;
2772 }
2773
2774 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2775 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2776 data, true);
2777 goto out;
2778 }
2779
2780 if (!page_set) {
2781 if (page == HV_INTC_FC_PAGE_START)
2782 page = 0;
2783
2784 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2785 /* Page is shifted left, PHY expects (page x 32) */
2786 ret_val = e1000_set_page_igp(hw,
2787 (page << IGP_PAGE_SHIFT));
2788
2789 hw->phy.addr = phy_addr;
2790
2791 if (ret_val)
2792 goto out;
2793 }
2794 }
2795
2796 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2797 page << IGP_PAGE_SHIFT, reg);
2798
2799 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2800out:
2801 if (!locked)
2802 hw->phy.ops.release(hw);
2803
2804 return ret_val;
2805}
2806
2807/**
2808 * e1000_read_phy_reg_hv - Read HV PHY register
2809 * @hw: pointer to the HW structure
2810 * @offset: register offset to be read
2811 * @data: pointer to the read data
2812 *
2813 * Acquires semaphore then reads the PHY register at offset and stores
2814 * the retrieved information in data. Release the acquired semaphore
2815 * before exiting.
2816 **/
2817s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2818{
2819 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2820}
2821
2822/**
2823 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2824 * @hw: pointer to the HW structure
2825 * @offset: register offset to be read
2826 * @data: pointer to the read data
2827 *
2828 * Reads the PHY register at offset and stores the retrieved information
2829 * in data. Assumes semaphore already acquired.
2830 **/
2831s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2832{
2833 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2834}
2835
2836/**
2837 * e1000_read_phy_reg_page_hv - Read HV PHY register
2838 * @hw: pointer to the HW structure
2839 * @offset: register offset to write to
2840 * @data: data to write at register offset
2841 *
2842 * Reads the PHY register at offset and stores the retrieved information
2843 * in data. Assumes semaphore already acquired and page already set.
2844 **/
2845s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2846{
2847 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2848}
2849
2850/**
2851 * __e1000_write_phy_reg_hv - Write HV PHY register
2852 * @hw: pointer to the HW structure
2853 * @offset: register offset to write to
2854 * @data: data to write at register offset
2855 * @locked: semaphore has already been acquired or not
2856 *
2857 * Acquires semaphore, if necessary, then writes the data to PHY register
2858 * at the offset. Release any acquired semaphores before exiting.
2859 **/
2860static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2861 bool locked, bool page_set)
2862{
2863 s32 ret_val;
2864 u16 page = BM_PHY_REG_PAGE(offset);
2865 u16 reg = BM_PHY_REG_NUM(offset);
2866 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2867
2868 if (!locked) {
2869 ret_val = hw->phy.ops.acquire(hw);
2870 if (ret_val)
2871 return ret_val;
2872 }
2873
2874 /* Page 800 works differently than the rest so it has its own func */
2875 if (page == BM_WUC_PAGE) {
2876 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2877 false, page_set);
2878 goto out;
2879 }
2880
2881 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2882 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2883 &data, false);
2884 goto out;
2885 }
2886
2887 if (!page_set) {
2888 if (page == HV_INTC_FC_PAGE_START)
2889 page = 0;
2890
2891 /* Workaround MDIO accesses being disabled after entering IEEE
2892 * Power Down (when bit 11 of the PHY Control register is set)
2893 */
2894 if ((hw->phy.type == e1000_phy_82578) &&
2895 (hw->phy.revision >= 1) &&
2896 (hw->phy.addr == 2) &&
2897 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
2898 u16 data2 = 0x7EFF;
2899 ret_val = e1000_access_phy_debug_regs_hv(hw,
2900 (1 << 6) | 0x3,
2901 &data2, false);
2902 if (ret_val)
2903 goto out;
2904 }
2905
2906 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2907 /* Page is shifted left, PHY expects (page x 32) */
2908 ret_val = e1000_set_page_igp(hw,
2909 (page << IGP_PAGE_SHIFT));
2910
2911 hw->phy.addr = phy_addr;
2912
2913 if (ret_val)
2914 goto out;
2915 }
2916 }
2917
2918 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2919 page << IGP_PAGE_SHIFT, reg);
2920
2921 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2922 data);
2923
2924out:
2925 if (!locked)
2926 hw->phy.ops.release(hw);
2927
2928 return ret_val;
2929}
2930
2931/**
2932 * e1000_write_phy_reg_hv - Write HV PHY register
2933 * @hw: pointer to the HW structure
2934 * @offset: register offset to write to
2935 * @data: data to write at register offset
2936 *
2937 * Acquires semaphore then writes the data to PHY register at the offset.
2938 * Release the acquired semaphores before exiting.
2939 **/
2940s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2941{
2942 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2943}
2944
2945/**
2946 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2947 * @hw: pointer to the HW structure
2948 * @offset: register offset to write to
2949 * @data: data to write at register offset
2950 *
2951 * Writes the data to PHY register at the offset. Assumes semaphore
2952 * already acquired.
2953 **/
2954s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2955{
2956 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2957}
2958
2959/**
2960 * e1000_write_phy_reg_page_hv - Write HV PHY register
2961 * @hw: pointer to the HW structure
2962 * @offset: register offset to write to
2963 * @data: data to write at register offset
2964 *
2965 * Writes the data to PHY register at the offset. Assumes semaphore
2966 * already acquired and page already set.
2967 **/
2968s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2969{
2970 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2971}
2972
2973/**
2974 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2975 * @page: page to be accessed
2976 **/
2977static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2978{
2979 u32 phy_addr = 2;
2980
2981 if (page >= HV_INTC_FC_PAGE_START)
2982 phy_addr = 1;
2983
2984 return phy_addr;
2985}
2986
2987/**
2988 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2989 * @hw: pointer to the HW structure
2990 * @offset: register offset to be read or written
2991 * @data: pointer to the data to be read or written
2992 * @read: determines if operation is read or write
2993 *
2994 * Reads the PHY register at offset and stores the retreived information
2995 * in data. Assumes semaphore already acquired. Note that the procedure
2996 * to access these regs uses the address port and data port to read/write.
2997 * These accesses done with PHY address 2 and without using pages.
2998 **/
2999static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3000 u16 *data, bool read)
3001{
3002 s32 ret_val;
3003 u32 addr_reg;
3004 u32 data_reg;
3005
3006 /* This takes care of the difference with desktop vs mobile phy */
3007 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3008 I82578_ADDR_REG : I82577_ADDR_REG);
3009 data_reg = addr_reg + 1;
3010
3011 /* All operations in this function are phy address 2 */
3012 hw->phy.addr = 2;
3013
3014 /* masking with 0x3F to remove the page from offset */
3015 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3016 if (ret_val) {
3017 e_dbg("Could not write the Address Offset port register\n");
3018 return ret_val;
3019 }
3020
3021 /* Read or write the data value next */
3022 if (read)
3023 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3024 else
3025 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3026
3027 if (ret_val)
3028 e_dbg("Could not access the Data port register\n");
3029
3030 return ret_val;
3031}
3032
3033/**
3034 * e1000_link_stall_workaround_hv - Si workaround
3035 * @hw: pointer to the HW structure
3036 *
3037 * This function works around a Si bug where the link partner can get
3038 * a link up indication before the PHY does. If small packets are sent
3039 * by the link partner they can be placed in the packet buffer without
3040 * being properly accounted for by the PHY and will stall preventing
3041 * further packets from being received. The workaround is to clear the
3042 * packet buffer after the PHY detects link up.
3043 **/
3044s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3045{
3046 s32 ret_val = 0;
3047 u16 data;
3048
3049 if (hw->phy.type != e1000_phy_82578)
3050 return 0;
3051
3052 /* Do not apply workaround if in PHY loopback bit 14 set */
3053 e1e_rphy(hw, MII_BMCR, &data);
3054 if (data & BMCR_LOOPBACK)
3055 return 0;
3056
3057 /* check if link is up and at 1Gbps */
3058 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3059 if (ret_val)
3060 return ret_val;
3061
3062 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3063 BM_CS_STATUS_SPEED_MASK);
3064
3065 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3066 BM_CS_STATUS_SPEED_1000))
3067 return 0;
3068
3069 msleep(200);
3070
3071 /* flush the packets in the fifo buffer */
3072 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3073 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3074 HV_MUX_DATA_CTRL_FORCE_SPEED));
3075 if (ret_val)
3076 return ret_val;
3077
3078 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3079}
3080
3081/**
3082 * e1000_check_polarity_82577 - Checks the polarity.
3083 * @hw: pointer to the HW structure
3084 *
3085 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3086 *
3087 * Polarity is determined based on the PHY specific status register.
3088 **/
3089s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3090{
3091 struct e1000_phy_info *phy = &hw->phy;
3092 s32 ret_val;
3093 u16 data;
3094
3095 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3096
3097 if (!ret_val)
3098 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3099 ? e1000_rev_polarity_reversed
3100 : e1000_rev_polarity_normal);
3101
3102 return ret_val;
3103}
3104
3105/**
3106 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3107 * @hw: pointer to the HW structure
3108 *
3109 * Calls the PHY setup function to force speed and duplex.
3110 **/
3111s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3112{
3113 struct e1000_phy_info *phy = &hw->phy;
3114 s32 ret_val;
3115 u16 phy_data;
3116 bool link;
3117
3118 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3119 if (ret_val)
3120 return ret_val;
3121
3122 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3123
3124 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3125 if (ret_val)
3126 return ret_val;
3127
3128 udelay(1);
3129
3130 if (phy->autoneg_wait_to_complete) {
3131 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3132
3133 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3134 100000, &link);
3135 if (ret_val)
3136 return ret_val;
3137
3138 if (!link)
3139 e_dbg("Link taking longer than expected.\n");
3140
3141 /* Try once more */
3142 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3143 100000, &link);
3144 }
3145
3146 return ret_val;
3147}
3148
3149/**
3150 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3151 * @hw: pointer to the HW structure
3152 *
3153 * Read PHY status to determine if link is up. If link is up, then
3154 * set/determine 10base-T extended distance and polarity correction. Read
3155 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3156 * determine on the cable length, local and remote receiver.
3157 **/
3158s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3159{
3160 struct e1000_phy_info *phy = &hw->phy;
3161 s32 ret_val;
3162 u16 data;
3163 bool link;
3164
3165 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3166 if (ret_val)
3167 return ret_val;
3168
3169 if (!link) {
3170 e_dbg("Phy info is only valid if link is up\n");
3171 return -E1000_ERR_CONFIG;
3172 }
3173
3174 phy->polarity_correction = true;
3175
3176 ret_val = e1000_check_polarity_82577(hw);
3177 if (ret_val)
3178 return ret_val;
3179
3180 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3181 if (ret_val)
3182 return ret_val;
3183
3184 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3185
3186 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3187 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3188 ret_val = hw->phy.ops.get_cable_length(hw);
3189 if (ret_val)
3190 return ret_val;
3191
3192 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3193 if (ret_val)
3194 return ret_val;
3195
3196 phy->local_rx = (data & LPA_1000LOCALRXOK)
3197 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3198
3199 phy->remote_rx = (data & LPA_1000REMRXOK)
3200 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3201 } else {
3202 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3203 phy->local_rx = e1000_1000t_rx_status_undefined;
3204 phy->remote_rx = e1000_1000t_rx_status_undefined;
3205 }
3206
3207 return 0;
3208}
3209
3210/**
3211 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3212 * @hw: pointer to the HW structure
3213 *
3214 * Reads the diagnostic status register and verifies result is valid before
3215 * placing it in the phy_cable_length field.
3216 **/
3217s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3218{
3219 struct e1000_phy_info *phy = &hw->phy;
3220 s32 ret_val;
3221 u16 phy_data, length;
3222
3223 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3224 if (ret_val)
3225 return ret_val;
3226
3227 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3228 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3229
3230 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3231 return -E1000_ERR_PHY;
3232
3233 phy->cable_length = length;
3234
3235 return 0;
3236}