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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * linux/arch/arm/plat-omap/dmtimer.c
4 *
5 * OMAP Dual-Mode Timers
6 *
7 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
8 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * dmtimer adaptation to platform_driver.
12 *
13 * Copyright (C) 2005 Nokia Corporation
14 * OMAP2 support by Juha Yrjola
15 * API improvements and OMAP2 clock framework support by Timo Teras
16 *
17 * Copyright (C) 2009 Texas Instruments
18 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
19 */
20
21#include <linux/clk.h>
22#include <linux/clk-provider.h>
23#include <linux/cpu_pm.h>
24#include <linux/module.h>
25#include <linux/io.h>
26#include <linux/device.h>
27#include <linux/err.h>
28#include <linux/pm_runtime.h>
29#include <linux/of.h>
30#include <linux/platform_device.h>
31#include <linux/platform_data/dmtimer-omap.h>
32
33#include <clocksource/timer-ti-dm.h>
34
35/*
36 * timer errata flags
37 *
38 * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
39 * errata prevents us from using posted mode on these devices, unless the
40 * timer counter register is never read. For more details please refer to
41 * the OMAP3/4/5 errata documents.
42 */
43#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
44
45/* posted mode types */
46#define OMAP_TIMER_NONPOSTED 0x00
47#define OMAP_TIMER_POSTED 0x01
48
49/* register offsets with the write pending bit encoded */
50#define WPSHIFT 16
51
52#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
53 | (WP_NONE << WPSHIFT))
54
55#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
56 | (WP_TCLR << WPSHIFT))
57
58#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
59 | (WP_TCRR << WPSHIFT))
60
61#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
62 | (WP_TLDR << WPSHIFT))
63
64#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
65 | (WP_TTGR << WPSHIFT))
66
67#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
68 | (WP_NONE << WPSHIFT))
69
70#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
71 | (WP_TMAR << WPSHIFT))
72
73#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
74 | (WP_NONE << WPSHIFT))
75
76#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
77 | (WP_NONE << WPSHIFT))
78
79#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
80 | (WP_NONE << WPSHIFT))
81
82#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
83 | (WP_TPIR << WPSHIFT))
84
85#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
86 | (WP_TNIR << WPSHIFT))
87
88#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
89 | (WP_TCVR << WPSHIFT))
90
91#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
92 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
93
94#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
95 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
96
97struct timer_regs {
98 u32 ocp_cfg;
99 u32 tidr;
100 u32 tier;
101 u32 twer;
102 u32 tclr;
103 u32 tcrr;
104 u32 tldr;
105 u32 ttrg;
106 u32 twps;
107 u32 tmar;
108 u32 tcar1;
109 u32 tsicr;
110 u32 tcar2;
111 u32 tpir;
112 u32 tnir;
113 u32 tcvr;
114 u32 tocr;
115 u32 towr;
116};
117
118struct dmtimer {
119 struct omap_dm_timer cookie;
120 int id;
121 int irq;
122 struct clk *fclk;
123
124 void __iomem *io_base;
125 int irq_stat; /* TISR/IRQSTATUS interrupt status */
126 int irq_ena; /* irq enable */
127 int irq_dis; /* irq disable, only on v2 ip */
128 void __iomem *pend; /* write pending */
129 void __iomem *func_base; /* function register base */
130
131 atomic_t enabled;
132 unsigned long rate;
133 unsigned reserved:1;
134 unsigned posted:1;
135 unsigned omap1:1;
136 struct timer_regs context;
137 int revision;
138 u32 capability;
139 u32 errata;
140 struct platform_device *pdev;
141 struct list_head node;
142 struct notifier_block nb;
143 struct notifier_block fclk_nb;
144 unsigned long fclk_rate;
145};
146
147static u32 omap_reserved_systimers;
148static LIST_HEAD(omap_timer_list);
149static DEFINE_SPINLOCK(dm_timer_lock);
150
151enum {
152 REQUEST_ANY = 0,
153 REQUEST_BY_ID,
154 REQUEST_BY_CAP,
155 REQUEST_BY_NODE,
156};
157
158/**
159 * dmtimer_read - read timer registers in posted and non-posted mode
160 * @timer: timer pointer over which read operation to perform
161 * @reg: lowest byte holds the register offset
162 *
163 * The posted mode bit is encoded in reg. Note that in posted mode, write
164 * pending bit must be checked. Otherwise a read of a non completed write
165 * will produce an error.
166 */
167static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg)
168{
169 u16 wp, offset;
170
171 wp = reg >> WPSHIFT;
172 offset = reg & 0xff;
173
174 /* Wait for a possible write pending bit in posted mode */
175 if (wp && timer->posted)
176 while (readl_relaxed(timer->pend) & wp)
177 cpu_relax();
178
179 return readl_relaxed(timer->func_base + offset);
180}
181
182/**
183 * dmtimer_write - write timer registers in posted and non-posted mode
184 * @timer: timer pointer over which write operation is to perform
185 * @reg: lowest byte holds the register offset
186 * @val: data to write into the register
187 *
188 * The posted mode bit is encoded in reg. Note that in posted mode, the write
189 * pending bit must be checked. Otherwise a write on a register which has a
190 * pending write will be lost.
191 */
192static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val)
193{
194 u16 wp, offset;
195
196 wp = reg >> WPSHIFT;
197 offset = reg & 0xff;
198
199 /* Wait for a possible write pending bit in posted mode */
200 if (wp && timer->posted)
201 while (readl_relaxed(timer->pend) & wp)
202 cpu_relax();
203
204 writel_relaxed(val, timer->func_base + offset);
205}
206
207static inline void __omap_dm_timer_init_regs(struct dmtimer *timer)
208{
209 u32 tidr;
210
211 /* Assume v1 ip if bits [31:16] are zero */
212 tidr = readl_relaxed(timer->io_base);
213 if (!(tidr >> 16)) {
214 timer->revision = 1;
215 timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
216 timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
217 timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET;
218 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
219 timer->func_base = timer->io_base;
220 } else {
221 timer->revision = 2;
222 timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET;
223 timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET;
224 timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET;
225 timer->pend = timer->io_base +
226 _OMAP_TIMER_WRITE_PEND_OFFSET +
227 OMAP_TIMER_V2_FUNC_OFFSET;
228 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
229 }
230}
231
232/*
233 * __omap_dm_timer_enable_posted - enables write posted mode
234 * @timer: pointer to timer instance handle
235 *
236 * Enables the write posted mode for the timer. When posted mode is enabled
237 * writes to certain timer registers are immediately acknowledged by the
238 * internal bus and hence prevents stalling the CPU waiting for the write to
239 * complete. Enabling this feature can improve performance for writing to the
240 * timer registers.
241 */
242static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer)
243{
244 if (timer->posted)
245 return;
246
247 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
248 timer->posted = OMAP_TIMER_NONPOSTED;
249 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0);
250 return;
251 }
252
253 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED);
254 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
255 timer->posted = OMAP_TIMER_POSTED;
256}
257
258static inline void __omap_dm_timer_stop(struct dmtimer *timer)
259{
260 u32 l;
261
262 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
263 if (l & OMAP_TIMER_CTRL_ST) {
264 l &= ~0x1;
265 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
266#ifdef CONFIG_ARCH_OMAP2PLUS
267 /* Readback to make sure write has completed */
268 dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
269 /*
270 * Wait for functional clock period x 3.5 to make sure that
271 * timer is stopped
272 */
273 udelay(3500000 / timer->fclk_rate + 1);
274#endif
275 }
276
277 /* Ack possibly pending interrupt */
278 dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW);
279}
280
281static inline void __omap_dm_timer_int_enable(struct dmtimer *timer,
282 unsigned int value)
283{
284 dmtimer_write(timer, timer->irq_ena, value);
285 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
286}
287
288static inline unsigned int
289__omap_dm_timer_read_counter(struct dmtimer *timer)
290{
291 return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG);
292}
293
294static inline void __omap_dm_timer_write_status(struct dmtimer *timer,
295 unsigned int value)
296{
297 dmtimer_write(timer, timer->irq_stat, value);
298}
299
300static void omap_timer_restore_context(struct dmtimer *timer)
301{
302 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg);
303
304 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer);
305 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr);
306 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
307 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
308 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
309 dmtimer_write(timer, timer->irq_ena, timer->context.tier);
310 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
311}
312
313static void omap_timer_save_context(struct dmtimer *timer)
314{
315 timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
316
317 timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
318 timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
319 timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
320 timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
321 timer->context.tier = dmtimer_read(timer, timer->irq_ena);
322 timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
323}
324
325static int omap_timer_context_notifier(struct notifier_block *nb,
326 unsigned long cmd, void *v)
327{
328 struct dmtimer *timer;
329
330 timer = container_of(nb, struct dmtimer, nb);
331
332 switch (cmd) {
333 case CPU_CLUSTER_PM_ENTER:
334 if ((timer->capability & OMAP_TIMER_ALWON) ||
335 !atomic_read(&timer->enabled))
336 break;
337 omap_timer_save_context(timer);
338 break;
339 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
340 break;
341 case CPU_CLUSTER_PM_EXIT:
342 if ((timer->capability & OMAP_TIMER_ALWON) ||
343 !atomic_read(&timer->enabled))
344 break;
345 omap_timer_restore_context(timer);
346 break;
347 }
348
349 return NOTIFY_OK;
350}
351
352static int omap_timer_fclk_notifier(struct notifier_block *nb,
353 unsigned long event, void *data)
354{
355 struct clk_notifier_data *clk_data = data;
356 struct dmtimer *timer = container_of(nb, struct dmtimer, fclk_nb);
357
358 switch (event) {
359 case POST_RATE_CHANGE:
360 timer->fclk_rate = clk_data->new_rate;
361 return NOTIFY_OK;
362 default:
363 return NOTIFY_DONE;
364 }
365}
366
367static int omap_dm_timer_reset(struct dmtimer *timer)
368{
369 u32 l, timeout = 100000;
370
371 if (timer->revision != 1)
372 return -EINVAL;
373
374 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
375
376 do {
377 l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
378 } while (!l && timeout--);
379
380 if (!timeout) {
381 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
382 return -ETIMEDOUT;
383 }
384
385 /* Configure timer for smart-idle mode */
386 l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
387 l |= 0x2 << 0x3;
388 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l);
389
390 timer->posted = 0;
391
392 return 0;
393}
394
395/*
396 * Functions exposed to PWM and remoteproc drivers via platform_data.
397 * Do not use these in the driver, these will get deprecated and will
398 * will be replaced by Linux generic framework functions such as
399 * chained interrupts and clock framework.
400 */
401static struct dmtimer *to_dmtimer(struct omap_dm_timer *cookie)
402{
403 if (!cookie)
404 return NULL;
405
406 return container_of(cookie, struct dmtimer, cookie);
407}
408
409static int omap_dm_timer_set_source(struct omap_dm_timer *cookie, int source)
410{
411 int ret;
412 const char *parent_name;
413 struct clk *parent;
414 struct dmtimer_platform_data *pdata;
415 struct dmtimer *timer;
416
417 timer = to_dmtimer(cookie);
418 if (unlikely(!timer) || IS_ERR(timer->fclk))
419 return -EINVAL;
420
421 switch (source) {
422 case OMAP_TIMER_SRC_SYS_CLK:
423 parent_name = "timer_sys_ck";
424 break;
425 case OMAP_TIMER_SRC_32_KHZ:
426 parent_name = "timer_32k_ck";
427 break;
428 case OMAP_TIMER_SRC_EXT_CLK:
429 parent_name = "timer_ext_ck";
430 break;
431 default:
432 return -EINVAL;
433 }
434
435 pdata = timer->pdev->dev.platform_data;
436
437 /*
438 * FIXME: Used for OMAP1 devices only because they do not currently
439 * use the clock framework to set the parent clock. To be removed
440 * once OMAP1 migrated to using clock framework for dmtimers
441 */
442 if (timer->omap1 && pdata && pdata->set_timer_src)
443 return pdata->set_timer_src(timer->pdev, source);
444
445#if defined(CONFIG_COMMON_CLK)
446 /* Check if the clock has configurable parents */
447 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
448 return 0;
449#endif
450
451 parent = clk_get(&timer->pdev->dev, parent_name);
452 if (IS_ERR(parent)) {
453 pr_err("%s: %s not found\n", __func__, parent_name);
454 return -EINVAL;
455 }
456
457 ret = clk_set_parent(timer->fclk, parent);
458 if (ret < 0)
459 pr_err("%s: failed to set %s as parent\n", __func__,
460 parent_name);
461
462 clk_put(parent);
463
464 return ret;
465}
466
467static void omap_dm_timer_enable(struct omap_dm_timer *cookie)
468{
469 struct dmtimer *timer = to_dmtimer(cookie);
470 struct device *dev = &timer->pdev->dev;
471 int rc;
472
473 rc = pm_runtime_resume_and_get(dev);
474 if (rc)
475 dev_err(dev, "could not enable timer\n");
476}
477
478static void omap_dm_timer_disable(struct omap_dm_timer *cookie)
479{
480 struct dmtimer *timer = to_dmtimer(cookie);
481 struct device *dev = &timer->pdev->dev;
482
483 pm_runtime_put_sync(dev);
484}
485
486static int omap_dm_timer_prepare(struct dmtimer *timer)
487{
488 struct device *dev = &timer->pdev->dev;
489 int rc;
490
491 rc = pm_runtime_resume_and_get(dev);
492 if (rc)
493 return rc;
494
495 if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
496 rc = omap_dm_timer_reset(timer);
497 if (rc) {
498 pm_runtime_put_sync(dev);
499 return rc;
500 }
501 }
502
503 __omap_dm_timer_enable_posted(timer);
504 pm_runtime_put_sync(dev);
505
506 return 0;
507}
508
509static inline u32 omap_dm_timer_reserved_systimer(int id)
510{
511 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
512}
513
514static struct dmtimer *_omap_dm_timer_request(int req_type, void *data)
515{
516 struct dmtimer *timer = NULL, *t;
517 struct device_node *np = NULL;
518 unsigned long flags;
519 u32 cap = 0;
520 int id = 0;
521
522 switch (req_type) {
523 case REQUEST_BY_ID:
524 id = *(int *)data;
525 break;
526 case REQUEST_BY_CAP:
527 cap = *(u32 *)data;
528 break;
529 case REQUEST_BY_NODE:
530 np = (struct device_node *)data;
531 break;
532 default:
533 /* REQUEST_ANY */
534 break;
535 }
536
537 spin_lock_irqsave(&dm_timer_lock, flags);
538 list_for_each_entry(t, &omap_timer_list, node) {
539 if (t->reserved)
540 continue;
541
542 switch (req_type) {
543 case REQUEST_BY_ID:
544 if (id == t->pdev->id) {
545 timer = t;
546 timer->reserved = 1;
547 goto found;
548 }
549 break;
550 case REQUEST_BY_CAP:
551 if (cap == (t->capability & cap)) {
552 /*
553 * If timer is not NULL, we have already found
554 * one timer. But it was not an exact match
555 * because it had more capabilities than what
556 * was required. Therefore, unreserve the last
557 * timer found and see if this one is a better
558 * match.
559 */
560 if (timer)
561 timer->reserved = 0;
562 timer = t;
563 timer->reserved = 1;
564
565 /* Exit loop early if we find an exact match */
566 if (t->capability == cap)
567 goto found;
568 }
569 break;
570 case REQUEST_BY_NODE:
571 if (np == t->pdev->dev.of_node) {
572 timer = t;
573 timer->reserved = 1;
574 goto found;
575 }
576 break;
577 default:
578 /* REQUEST_ANY */
579 timer = t;
580 timer->reserved = 1;
581 goto found;
582 }
583 }
584found:
585 spin_unlock_irqrestore(&dm_timer_lock, flags);
586
587 if (timer && omap_dm_timer_prepare(timer)) {
588 timer->reserved = 0;
589 timer = NULL;
590 }
591
592 if (!timer)
593 pr_debug("%s: timer request failed!\n", __func__);
594
595 return timer;
596}
597
598static struct omap_dm_timer *omap_dm_timer_request(void)
599{
600 struct dmtimer *timer;
601
602 timer = _omap_dm_timer_request(REQUEST_ANY, NULL);
603 if (!timer)
604 return NULL;
605
606 return &timer->cookie;
607}
608
609static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
610{
611 struct dmtimer *timer;
612
613 /* Requesting timer by ID is not supported when device tree is used */
614 if (of_have_populated_dt()) {
615 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
616 __func__);
617 return NULL;
618 }
619
620 timer = _omap_dm_timer_request(REQUEST_BY_ID, &id);
621 if (!timer)
622 return NULL;
623
624 return &timer->cookie;
625}
626
627/**
628 * omap_dm_timer_request_by_node - Request a timer by device-tree node
629 * @np: Pointer to device-tree timer node
630 *
631 * Request a timer based upon a device node pointer. Returns pointer to
632 * timer handle on success and a NULL pointer on failure.
633 */
634static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
635{
636 struct dmtimer *timer;
637
638 if (!np)
639 return NULL;
640
641 timer = _omap_dm_timer_request(REQUEST_BY_NODE, np);
642 if (!timer)
643 return NULL;
644
645 return &timer->cookie;
646}
647
648static int omap_dm_timer_free(struct omap_dm_timer *cookie)
649{
650 struct dmtimer *timer;
651 struct device *dev;
652 int rc;
653
654 timer = to_dmtimer(cookie);
655 if (unlikely(!timer))
656 return -EINVAL;
657
658 WARN_ON(!timer->reserved);
659 timer->reserved = 0;
660
661 dev = &timer->pdev->dev;
662 rc = pm_runtime_resume_and_get(dev);
663 if (rc)
664 return rc;
665
666 /* Clear timer configuration */
667 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
668
669 pm_runtime_put_sync(dev);
670
671 return 0;
672}
673
674static int omap_dm_timer_get_irq(struct omap_dm_timer *cookie)
675{
676 struct dmtimer *timer = to_dmtimer(cookie);
677 if (timer)
678 return timer->irq;
679 return -EINVAL;
680}
681
682#if defined(CONFIG_ARCH_OMAP1)
683#include <linux/soc/ti/omap1-io.h>
684
685static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
686{
687 return NULL;
688}
689
690/**
691 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
692 * @inputmask: current value of idlect mask
693 */
694__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
695{
696 int i = 0;
697 struct dmtimer *timer = NULL;
698 unsigned long flags;
699
700 /* If ARMXOR cannot be idled this function call is unnecessary */
701 if (!(inputmask & (1 << 1)))
702 return inputmask;
703
704 /* If any active timer is using ARMXOR return modified mask */
705 spin_lock_irqsave(&dm_timer_lock, flags);
706 list_for_each_entry(timer, &omap_timer_list, node) {
707 u32 l;
708
709 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
710 if (l & OMAP_TIMER_CTRL_ST) {
711 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
712 inputmask &= ~(1 << 1);
713 else
714 inputmask &= ~(1 << 2);
715 }
716 i++;
717 }
718 spin_unlock_irqrestore(&dm_timer_lock, flags);
719
720 return inputmask;
721}
722
723#else
724
725static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
726{
727 struct dmtimer *timer = to_dmtimer(cookie);
728
729 if (timer && !IS_ERR(timer->fclk))
730 return timer->fclk;
731 return NULL;
732}
733
734__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
735{
736 BUG();
737
738 return 0;
739}
740
741#endif
742
743static int omap_dm_timer_start(struct omap_dm_timer *cookie)
744{
745 struct dmtimer *timer;
746 struct device *dev;
747 int rc;
748 u32 l;
749
750 timer = to_dmtimer(cookie);
751 if (unlikely(!timer))
752 return -EINVAL;
753
754 dev = &timer->pdev->dev;
755
756 rc = pm_runtime_resume_and_get(dev);
757 if (rc)
758 return rc;
759
760 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
761 if (!(l & OMAP_TIMER_CTRL_ST)) {
762 l |= OMAP_TIMER_CTRL_ST;
763 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
764 }
765
766 return 0;
767}
768
769static int omap_dm_timer_stop(struct omap_dm_timer *cookie)
770{
771 struct dmtimer *timer;
772 struct device *dev;
773
774 timer = to_dmtimer(cookie);
775 if (unlikely(!timer))
776 return -EINVAL;
777
778 dev = &timer->pdev->dev;
779
780 __omap_dm_timer_stop(timer);
781
782 pm_runtime_put_sync(dev);
783
784 return 0;
785}
786
787static int omap_dm_timer_set_load(struct omap_dm_timer *cookie,
788 unsigned int load)
789{
790 struct dmtimer *timer;
791 struct device *dev;
792 int rc;
793
794 timer = to_dmtimer(cookie);
795 if (unlikely(!timer))
796 return -EINVAL;
797
798 dev = &timer->pdev->dev;
799 rc = pm_runtime_resume_and_get(dev);
800 if (rc)
801 return rc;
802
803 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load);
804
805 pm_runtime_put_sync(dev);
806
807 return 0;
808}
809
810static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable,
811 unsigned int match)
812{
813 struct dmtimer *timer;
814 struct device *dev;
815 int rc;
816 u32 l;
817
818 timer = to_dmtimer(cookie);
819 if (unlikely(!timer))
820 return -EINVAL;
821
822 dev = &timer->pdev->dev;
823 rc = pm_runtime_resume_and_get(dev);
824 if (rc)
825 return rc;
826
827 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
828 if (enable)
829 l |= OMAP_TIMER_CTRL_CE;
830 else
831 l &= ~OMAP_TIMER_CTRL_CE;
832 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match);
833 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
834
835 pm_runtime_put_sync(dev);
836
837 return 0;
838}
839
840static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on,
841 int toggle, int trigger, int autoreload)
842{
843 struct dmtimer *timer;
844 struct device *dev;
845 int rc;
846 u32 l;
847
848 timer = to_dmtimer(cookie);
849 if (unlikely(!timer))
850 return -EINVAL;
851
852 dev = &timer->pdev->dev;
853 rc = pm_runtime_resume_and_get(dev);
854 if (rc)
855 return rc;
856
857 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
858 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
859 OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
860 if (def_on)
861 l |= OMAP_TIMER_CTRL_SCPWM;
862 if (toggle)
863 l |= OMAP_TIMER_CTRL_PT;
864 l |= trigger << 10;
865 if (autoreload)
866 l |= OMAP_TIMER_CTRL_AR;
867 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
868
869 pm_runtime_put_sync(dev);
870
871 return 0;
872}
873
874static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *cookie)
875{
876 struct dmtimer *timer;
877 struct device *dev;
878 int rc;
879 u32 l;
880
881 timer = to_dmtimer(cookie);
882 if (unlikely(!timer))
883 return -EINVAL;
884
885 dev = &timer->pdev->dev;
886 rc = pm_runtime_resume_and_get(dev);
887 if (rc)
888 return rc;
889
890 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
891
892 pm_runtime_put_sync(dev);
893
894 return l;
895}
896
897static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie,
898 int prescaler)
899{
900 struct dmtimer *timer;
901 struct device *dev;
902 int rc;
903 u32 l;
904
905 timer = to_dmtimer(cookie);
906 if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
907 return -EINVAL;
908
909 dev = &timer->pdev->dev;
910 rc = pm_runtime_resume_and_get(dev);
911 if (rc)
912 return rc;
913
914 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
915 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
916 if (prescaler >= 0) {
917 l |= OMAP_TIMER_CTRL_PRE;
918 l |= prescaler << 2;
919 }
920 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
921
922 pm_runtime_put_sync(dev);
923
924 return 0;
925}
926
927static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie,
928 unsigned int value)
929{
930 struct dmtimer *timer;
931 struct device *dev;
932 int rc;
933
934 timer = to_dmtimer(cookie);
935 if (unlikely(!timer))
936 return -EINVAL;
937
938 dev = &timer->pdev->dev;
939 rc = pm_runtime_resume_and_get(dev);
940 if (rc)
941 return rc;
942
943 __omap_dm_timer_int_enable(timer, value);
944
945 pm_runtime_put_sync(dev);
946
947 return 0;
948}
949
950/**
951 * omap_dm_timer_set_int_disable - disable timer interrupts
952 * @cookie: pointer to timer cookie
953 * @mask: bit mask of interrupts to be disabled
954 *
955 * Disables the specified timer interrupts for a timer.
956 */
957static int omap_dm_timer_set_int_disable(struct omap_dm_timer *cookie, u32 mask)
958{
959 struct dmtimer *timer;
960 struct device *dev;
961 u32 l = mask;
962 int rc;
963
964 timer = to_dmtimer(cookie);
965 if (unlikely(!timer))
966 return -EINVAL;
967
968 dev = &timer->pdev->dev;
969 rc = pm_runtime_resume_and_get(dev);
970 if (rc)
971 return rc;
972
973 if (timer->revision == 1)
974 l = dmtimer_read(timer, timer->irq_ena) & ~mask;
975
976 dmtimer_write(timer, timer->irq_dis, l);
977 l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
978 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
979
980 pm_runtime_put_sync(dev);
981
982 return 0;
983}
984
985static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *cookie)
986{
987 struct dmtimer *timer;
988 unsigned int l;
989
990 timer = to_dmtimer(cookie);
991 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
992 pr_err("%s: timer not available or enabled.\n", __func__);
993 return 0;
994 }
995
996 l = dmtimer_read(timer, timer->irq_stat);
997
998 return l;
999}
1000
1001static int omap_dm_timer_write_status(struct omap_dm_timer *cookie, unsigned int value)
1002{
1003 struct dmtimer *timer;
1004
1005 timer = to_dmtimer(cookie);
1006 if (unlikely(!timer || !atomic_read(&timer->enabled)))
1007 return -EINVAL;
1008
1009 __omap_dm_timer_write_status(timer, value);
1010
1011 return 0;
1012}
1013
1014static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *cookie)
1015{
1016 struct dmtimer *timer;
1017
1018 timer = to_dmtimer(cookie);
1019 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1020 pr_err("%s: timer not iavailable or enabled.\n", __func__);
1021 return 0;
1022 }
1023
1024 return __omap_dm_timer_read_counter(timer);
1025}
1026
1027static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsigned int value)
1028{
1029 struct dmtimer *timer;
1030
1031 timer = to_dmtimer(cookie);
1032 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1033 pr_err("%s: timer not available or enabled.\n", __func__);
1034 return -EINVAL;
1035 }
1036
1037 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value);
1038
1039 /* Save the context */
1040 timer->context.tcrr = value;
1041 return 0;
1042}
1043
1044static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
1045{
1046 struct dmtimer *timer = dev_get_drvdata(dev);
1047
1048 atomic_set(&timer->enabled, 0);
1049
1050 if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
1051 return 0;
1052
1053 omap_timer_save_context(timer);
1054
1055 return 0;
1056}
1057
1058static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
1059{
1060 struct dmtimer *timer = dev_get_drvdata(dev);
1061
1062 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
1063 omap_timer_restore_context(timer);
1064
1065 atomic_set(&timer->enabled, 1);
1066
1067 return 0;
1068}
1069
1070static const struct dev_pm_ops omap_dm_timer_pm_ops = {
1071 SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend,
1072 omap_dm_timer_runtime_resume, NULL)
1073};
1074
1075static const struct of_device_id omap_timer_match[];
1076
1077/**
1078 * omap_dm_timer_probe - probe function called for every registered device
1079 * @pdev: pointer to current timer platform device
1080 *
1081 * Called by driver framework at the end of device registration for all
1082 * timer devices.
1083 */
1084static int omap_dm_timer_probe(struct platform_device *pdev)
1085{
1086 unsigned long flags;
1087 struct dmtimer *timer;
1088 struct device *dev = &pdev->dev;
1089 const struct dmtimer_platform_data *pdata;
1090 int ret;
1091
1092 pdata = of_device_get_match_data(dev);
1093 if (!pdata)
1094 pdata = dev_get_platdata(dev);
1095 else
1096 dev->platform_data = (void *)pdata;
1097
1098 if (!pdata) {
1099 dev_err(dev, "%s: no platform data.\n", __func__);
1100 return -ENODEV;
1101 }
1102
1103 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
1104 if (!timer)
1105 return -ENOMEM;
1106
1107 timer->irq = platform_get_irq(pdev, 0);
1108 if (timer->irq < 0)
1109 return timer->irq;
1110
1111 timer->io_base = devm_platform_ioremap_resource(pdev, 0);
1112 if (IS_ERR(timer->io_base))
1113 return PTR_ERR(timer->io_base);
1114
1115 platform_set_drvdata(pdev, timer);
1116
1117 if (dev->of_node) {
1118 if (of_property_read_bool(dev->of_node, "ti,timer-alwon"))
1119 timer->capability |= OMAP_TIMER_ALWON;
1120 if (of_property_read_bool(dev->of_node, "ti,timer-dsp"))
1121 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
1122 if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
1123 timer->capability |= OMAP_TIMER_HAS_PWM;
1124 if (of_property_read_bool(dev->of_node, "ti,timer-secure"))
1125 timer->capability |= OMAP_TIMER_SECURE;
1126 } else {
1127 timer->id = pdev->id;
1128 timer->capability = pdata->timer_capability;
1129 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
1130 }
1131
1132 timer->omap1 = timer->capability & OMAP_TIMER_NEEDS_RESET;
1133
1134 /* OMAP1 devices do not yet use the clock framework for dmtimers */
1135 if (!timer->omap1) {
1136 timer->fclk = devm_clk_get(dev, "fck");
1137 if (IS_ERR(timer->fclk))
1138 return PTR_ERR(timer->fclk);
1139
1140 timer->fclk_nb.notifier_call = omap_timer_fclk_notifier;
1141 ret = devm_clk_notifier_register(dev, timer->fclk,
1142 &timer->fclk_nb);
1143 if (ret)
1144 return ret;
1145
1146 timer->fclk_rate = clk_get_rate(timer->fclk);
1147 } else {
1148 timer->fclk = ERR_PTR(-ENODEV);
1149 }
1150
1151 if (!(timer->capability & OMAP_TIMER_ALWON)) {
1152 timer->nb.notifier_call = omap_timer_context_notifier;
1153 cpu_pm_register_notifier(&timer->nb);
1154 }
1155
1156 timer->errata = pdata->timer_errata;
1157
1158 timer->pdev = pdev;
1159
1160 pm_runtime_enable(dev);
1161
1162 if (!timer->reserved) {
1163 ret = pm_runtime_resume_and_get(dev);
1164 if (ret) {
1165 dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
1166 __func__);
1167 goto err_disable;
1168 }
1169 __omap_dm_timer_init_regs(timer);
1170
1171 /* Clear timer configuration */
1172 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
1173
1174 pm_runtime_put(dev);
1175 }
1176
1177 /* add the timer element to the list */
1178 spin_lock_irqsave(&dm_timer_lock, flags);
1179 list_add_tail(&timer->node, &omap_timer_list);
1180 spin_unlock_irqrestore(&dm_timer_lock, flags);
1181
1182 dev_dbg(dev, "Device Probed.\n");
1183
1184 return 0;
1185
1186err_disable:
1187 pm_runtime_disable(dev);
1188 return ret;
1189}
1190
1191/**
1192 * omap_dm_timer_remove - cleanup a registered timer device
1193 * @pdev: pointer to current timer platform device
1194 *
1195 * Called by driver framework whenever a timer device is unregistered.
1196 * In addition to freeing platform resources it also deletes the timer
1197 * entry from the local list.
1198 */
1199static void omap_dm_timer_remove(struct platform_device *pdev)
1200{
1201 struct dmtimer *timer;
1202 unsigned long flags;
1203 int ret = -EINVAL;
1204
1205 spin_lock_irqsave(&dm_timer_lock, flags);
1206 list_for_each_entry(timer, &omap_timer_list, node)
1207 if (!strcmp(dev_name(&timer->pdev->dev),
1208 dev_name(&pdev->dev))) {
1209 if (!(timer->capability & OMAP_TIMER_ALWON))
1210 cpu_pm_unregister_notifier(&timer->nb);
1211 list_del(&timer->node);
1212 ret = 0;
1213 break;
1214 }
1215 spin_unlock_irqrestore(&dm_timer_lock, flags);
1216
1217 pm_runtime_disable(&pdev->dev);
1218
1219 if (ret)
1220 dev_err(&pdev->dev, "Unable to determine timer entry in list of drivers on remove\n");
1221}
1222
1223static const struct omap_dm_timer_ops dmtimer_ops = {
1224 .request_by_node = omap_dm_timer_request_by_node,
1225 .request_specific = omap_dm_timer_request_specific,
1226 .request = omap_dm_timer_request,
1227 .set_source = omap_dm_timer_set_source,
1228 .get_irq = omap_dm_timer_get_irq,
1229 .set_int_enable = omap_dm_timer_set_int_enable,
1230 .set_int_disable = omap_dm_timer_set_int_disable,
1231 .free = omap_dm_timer_free,
1232 .enable = omap_dm_timer_enable,
1233 .disable = omap_dm_timer_disable,
1234 .get_fclk = omap_dm_timer_get_fclk,
1235 .start = omap_dm_timer_start,
1236 .stop = omap_dm_timer_stop,
1237 .set_load = omap_dm_timer_set_load,
1238 .set_match = omap_dm_timer_set_match,
1239 .set_pwm = omap_dm_timer_set_pwm,
1240 .get_pwm_status = omap_dm_timer_get_pwm_status,
1241 .set_prescaler = omap_dm_timer_set_prescaler,
1242 .read_counter = omap_dm_timer_read_counter,
1243 .write_counter = omap_dm_timer_write_counter,
1244 .read_status = omap_dm_timer_read_status,
1245 .write_status = omap_dm_timer_write_status,
1246};
1247
1248static const struct dmtimer_platform_data omap3plus_pdata = {
1249 .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
1250 .timer_ops = &dmtimer_ops,
1251};
1252
1253static const struct dmtimer_platform_data am6_pdata = {
1254 .timer_ops = &dmtimer_ops,
1255};
1256
1257static const struct of_device_id omap_timer_match[] = {
1258 {
1259 .compatible = "ti,omap2420-timer",
1260 },
1261 {
1262 .compatible = "ti,omap3430-timer",
1263 .data = &omap3plus_pdata,
1264 },
1265 {
1266 .compatible = "ti,omap4430-timer",
1267 .data = &omap3plus_pdata,
1268 },
1269 {
1270 .compatible = "ti,omap5430-timer",
1271 .data = &omap3plus_pdata,
1272 },
1273 {
1274 .compatible = "ti,am335x-timer",
1275 .data = &omap3plus_pdata,
1276 },
1277 {
1278 .compatible = "ti,am335x-timer-1ms",
1279 .data = &omap3plus_pdata,
1280 },
1281 {
1282 .compatible = "ti,dm816-timer",
1283 .data = &omap3plus_pdata,
1284 },
1285 {
1286 .compatible = "ti,am654-timer",
1287 .data = &am6_pdata,
1288 },
1289 {},
1290};
1291MODULE_DEVICE_TABLE(of, omap_timer_match);
1292
1293static struct platform_driver omap_dm_timer_driver = {
1294 .probe = omap_dm_timer_probe,
1295 .remove_new = omap_dm_timer_remove,
1296 .driver = {
1297 .name = "omap_timer",
1298 .of_match_table = omap_timer_match,
1299 .pm = &omap_dm_timer_pm_ops,
1300 },
1301};
1302
1303module_platform_driver(omap_dm_timer_driver);
1304
1305MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
1306MODULE_AUTHOR("Texas Instruments Inc");
1/*
2 * linux/arch/arm/plat-omap/dmtimer.c
3 *
4 * OMAP Dual-Mode Timers
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * dmtimer adaptation to platform_driver.
11 *
12 * Copyright (C) 2005 Nokia Corporation
13 * OMAP2 support by Juha Yrjola
14 * API improvements and OMAP2 clock framework support by Timo Teras
15 *
16 * Copyright (C) 2009 Texas Instruments
17 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/clk.h>
39#include <linux/clk-provider.h>
40#include <linux/module.h>
41#include <linux/io.h>
42#include <linux/device.h>
43#include <linux/err.h>
44#include <linux/pm_runtime.h>
45#include <linux/of.h>
46#include <linux/of_device.h>
47#include <linux/platform_device.h>
48#include <linux/platform_data/dmtimer-omap.h>
49
50#include <clocksource/timer-ti-dm.h>
51
52static u32 omap_reserved_systimers;
53static LIST_HEAD(omap_timer_list);
54static DEFINE_SPINLOCK(dm_timer_lock);
55
56enum {
57 REQUEST_ANY = 0,
58 REQUEST_BY_ID,
59 REQUEST_BY_CAP,
60 REQUEST_BY_NODE,
61};
62
63/**
64 * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
65 * @timer: timer pointer over which read operation to perform
66 * @reg: lowest byte holds the register offset
67 *
68 * The posted mode bit is encoded in reg. Note that in posted mode write
69 * pending bit must be checked. Otherwise a read of a non completed write
70 * will produce an error.
71 */
72static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
73{
74 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
75 return __omap_dm_timer_read(timer, reg, timer->posted);
76}
77
78/**
79 * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
80 * @timer: timer pointer over which write operation is to perform
81 * @reg: lowest byte holds the register offset
82 * @value: data to write into the register
83 *
84 * The posted mode bit is encoded in reg. Note that in posted mode the write
85 * pending bit must be checked. Otherwise a write on a register which has a
86 * pending write will be lost.
87 */
88static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
89 u32 value)
90{
91 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
92 __omap_dm_timer_write(timer, reg, value, timer->posted);
93}
94
95static void omap_timer_restore_context(struct omap_dm_timer *timer)
96{
97 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
98 timer->context.twer);
99 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
100 timer->context.tcrr);
101 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
102 timer->context.tldr);
103 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
104 timer->context.tmar);
105 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
106 timer->context.tsicr);
107 writel_relaxed(timer->context.tier, timer->irq_ena);
108 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
109 timer->context.tclr);
110}
111
112static int omap_dm_timer_reset(struct omap_dm_timer *timer)
113{
114 u32 l, timeout = 100000;
115
116 if (timer->revision != 1)
117 return -EINVAL;
118
119 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
120
121 do {
122 l = __omap_dm_timer_read(timer,
123 OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
124 } while (!l && timeout--);
125
126 if (!timeout) {
127 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
128 return -ETIMEDOUT;
129 }
130
131 /* Configure timer for smart-idle mode */
132 l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
133 l |= 0x2 << 0x3;
134 __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
135
136 timer->posted = 0;
137
138 return 0;
139}
140
141static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer)
142{
143 int ret;
144 struct clk *parent;
145
146 /*
147 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
148 * do not call clk_get() for these devices.
149 */
150 if (!timer->fclk)
151 return -ENODEV;
152
153 parent = clk_get(&timer->pdev->dev, NULL);
154 if (IS_ERR(parent))
155 return -ENODEV;
156
157 ret = clk_set_parent(timer->fclk, parent);
158 if (ret < 0)
159 pr_err("%s: failed to set parent\n", __func__);
160
161 clk_put(parent);
162
163 return ret;
164}
165
166static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
167{
168 int ret;
169 const char *parent_name;
170 struct clk *parent;
171 struct dmtimer_platform_data *pdata;
172
173 if (unlikely(!timer) || IS_ERR(timer->fclk))
174 return -EINVAL;
175
176 switch (source) {
177 case OMAP_TIMER_SRC_SYS_CLK:
178 parent_name = "timer_sys_ck";
179 break;
180 case OMAP_TIMER_SRC_32_KHZ:
181 parent_name = "timer_32k_ck";
182 break;
183 case OMAP_TIMER_SRC_EXT_CLK:
184 parent_name = "timer_ext_ck";
185 break;
186 default:
187 return -EINVAL;
188 }
189
190 pdata = timer->pdev->dev.platform_data;
191
192 /*
193 * FIXME: Used for OMAP1 devices only because they do not currently
194 * use the clock framework to set the parent clock. To be removed
195 * once OMAP1 migrated to using clock framework for dmtimers
196 */
197 if (pdata && pdata->set_timer_src)
198 return pdata->set_timer_src(timer->pdev, source);
199
200#if defined(CONFIG_COMMON_CLK)
201 /* Check if the clock has configurable parents */
202 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
203 return 0;
204#endif
205
206 parent = clk_get(&timer->pdev->dev, parent_name);
207 if (IS_ERR(parent)) {
208 pr_err("%s: %s not found\n", __func__, parent_name);
209 return -EINVAL;
210 }
211
212 ret = clk_set_parent(timer->fclk, parent);
213 if (ret < 0)
214 pr_err("%s: failed to set %s as parent\n", __func__,
215 parent_name);
216
217 clk_put(parent);
218
219 return ret;
220}
221
222static void omap_dm_timer_enable(struct omap_dm_timer *timer)
223{
224 int c;
225
226 pm_runtime_get_sync(&timer->pdev->dev);
227
228 if (!(timer->capability & OMAP_TIMER_ALWON)) {
229 if (timer->get_context_loss_count) {
230 c = timer->get_context_loss_count(&timer->pdev->dev);
231 if (c != timer->ctx_loss_count) {
232 omap_timer_restore_context(timer);
233 timer->ctx_loss_count = c;
234 }
235 } else {
236 omap_timer_restore_context(timer);
237 }
238 }
239}
240
241static void omap_dm_timer_disable(struct omap_dm_timer *timer)
242{
243 pm_runtime_put_sync(&timer->pdev->dev);
244}
245
246static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
247{
248 int rc;
249
250 /*
251 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
252 * do not call clk_get() for these devices.
253 */
254 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
255 timer->fclk = clk_get(&timer->pdev->dev, "fck");
256 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
257 dev_err(&timer->pdev->dev, ": No fclk handle.\n");
258 return -EINVAL;
259 }
260 }
261
262 omap_dm_timer_enable(timer);
263
264 if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
265 rc = omap_dm_timer_reset(timer);
266 if (rc) {
267 omap_dm_timer_disable(timer);
268 return rc;
269 }
270 }
271
272 __omap_dm_timer_enable_posted(timer);
273 omap_dm_timer_disable(timer);
274
275 rc = omap_dm_timer_of_set_source(timer);
276 if (rc == -ENODEV)
277 return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
278
279 return rc;
280}
281
282static inline u32 omap_dm_timer_reserved_systimer(int id)
283{
284 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
285}
286
287int omap_dm_timer_reserve_systimer(int id)
288{
289 if (omap_dm_timer_reserved_systimer(id))
290 return -ENODEV;
291
292 omap_reserved_systimers |= (1 << (id - 1));
293
294 return 0;
295}
296
297static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
298{
299 struct omap_dm_timer *timer = NULL, *t;
300 struct device_node *np = NULL;
301 unsigned long flags;
302 u32 cap = 0;
303 int id = 0;
304
305 switch (req_type) {
306 case REQUEST_BY_ID:
307 id = *(int *)data;
308 break;
309 case REQUEST_BY_CAP:
310 cap = *(u32 *)data;
311 break;
312 case REQUEST_BY_NODE:
313 np = (struct device_node *)data;
314 break;
315 default:
316 /* REQUEST_ANY */
317 break;
318 }
319
320 spin_lock_irqsave(&dm_timer_lock, flags);
321 list_for_each_entry(t, &omap_timer_list, node) {
322 if (t->reserved)
323 continue;
324
325 switch (req_type) {
326 case REQUEST_BY_ID:
327 if (id == t->pdev->id) {
328 timer = t;
329 timer->reserved = 1;
330 goto found;
331 }
332 break;
333 case REQUEST_BY_CAP:
334 if (cap == (t->capability & cap)) {
335 /*
336 * If timer is not NULL, we have already found
337 * one timer. But it was not an exact match
338 * because it had more capabilities than what
339 * was required. Therefore, unreserve the last
340 * timer found and see if this one is a better
341 * match.
342 */
343 if (timer)
344 timer->reserved = 0;
345 timer = t;
346 timer->reserved = 1;
347
348 /* Exit loop early if we find an exact match */
349 if (t->capability == cap)
350 goto found;
351 }
352 break;
353 case REQUEST_BY_NODE:
354 if (np == t->pdev->dev.of_node) {
355 timer = t;
356 timer->reserved = 1;
357 goto found;
358 }
359 break;
360 default:
361 /* REQUEST_ANY */
362 timer = t;
363 timer->reserved = 1;
364 goto found;
365 }
366 }
367found:
368 spin_unlock_irqrestore(&dm_timer_lock, flags);
369
370 if (timer && omap_dm_timer_prepare(timer)) {
371 timer->reserved = 0;
372 timer = NULL;
373 }
374
375 if (!timer)
376 pr_debug("%s: timer request failed!\n", __func__);
377
378 return timer;
379}
380
381static struct omap_dm_timer *omap_dm_timer_request(void)
382{
383 return _omap_dm_timer_request(REQUEST_ANY, NULL);
384}
385
386static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
387{
388 /* Requesting timer by ID is not supported when device tree is used */
389 if (of_have_populated_dt()) {
390 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
391 __func__);
392 return NULL;
393 }
394
395 return _omap_dm_timer_request(REQUEST_BY_ID, &id);
396}
397
398/**
399 * omap_dm_timer_request_by_cap - Request a timer by capability
400 * @cap: Bit mask of capabilities to match
401 *
402 * Find a timer based upon capabilities bit mask. Callers of this function
403 * should use the definitions found in the plat/dmtimer.h file under the
404 * comment "timer capabilities used in hwmod database". Returns pointer to
405 * timer handle on success and a NULL pointer on failure.
406 */
407struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
408{
409 return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
410}
411
412/**
413 * omap_dm_timer_request_by_node - Request a timer by device-tree node
414 * @np: Pointer to device-tree timer node
415 *
416 * Request a timer based upon a device node pointer. Returns pointer to
417 * timer handle on success and a NULL pointer on failure.
418 */
419static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
420{
421 if (!np)
422 return NULL;
423
424 return _omap_dm_timer_request(REQUEST_BY_NODE, np);
425}
426
427static int omap_dm_timer_free(struct omap_dm_timer *timer)
428{
429 if (unlikely(!timer))
430 return -EINVAL;
431
432 clk_put(timer->fclk);
433
434 WARN_ON(!timer->reserved);
435 timer->reserved = 0;
436 return 0;
437}
438
439int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
440{
441 if (timer)
442 return timer->irq;
443 return -EINVAL;
444}
445
446#if defined(CONFIG_ARCH_OMAP1)
447#include <mach/hardware.h>
448
449static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
450{
451 return NULL;
452}
453
454/**
455 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
456 * @inputmask: current value of idlect mask
457 */
458__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
459{
460 int i = 0;
461 struct omap_dm_timer *timer = NULL;
462 unsigned long flags;
463
464 /* If ARMXOR cannot be idled this function call is unnecessary */
465 if (!(inputmask & (1 << 1)))
466 return inputmask;
467
468 /* If any active timer is using ARMXOR return modified mask */
469 spin_lock_irqsave(&dm_timer_lock, flags);
470 list_for_each_entry(timer, &omap_timer_list, node) {
471 u32 l;
472
473 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
474 if (l & OMAP_TIMER_CTRL_ST) {
475 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
476 inputmask &= ~(1 << 1);
477 else
478 inputmask &= ~(1 << 2);
479 }
480 i++;
481 }
482 spin_unlock_irqrestore(&dm_timer_lock, flags);
483
484 return inputmask;
485}
486
487#else
488
489static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
490{
491 if (timer && !IS_ERR(timer->fclk))
492 return timer->fclk;
493 return NULL;
494}
495
496__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
497{
498 BUG();
499
500 return 0;
501}
502
503#endif
504
505int omap_dm_timer_trigger(struct omap_dm_timer *timer)
506{
507 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
508 pr_err("%s: timer not available or enabled.\n", __func__);
509 return -EINVAL;
510 }
511
512 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
513 return 0;
514}
515
516static int omap_dm_timer_start(struct omap_dm_timer *timer)
517{
518 u32 l;
519
520 if (unlikely(!timer))
521 return -EINVAL;
522
523 omap_dm_timer_enable(timer);
524
525 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
526 if (!(l & OMAP_TIMER_CTRL_ST)) {
527 l |= OMAP_TIMER_CTRL_ST;
528 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
529 }
530
531 /* Save the context */
532 timer->context.tclr = l;
533 return 0;
534}
535
536static int omap_dm_timer_stop(struct omap_dm_timer *timer)
537{
538 unsigned long rate = 0;
539
540 if (unlikely(!timer))
541 return -EINVAL;
542
543 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
544 rate = clk_get_rate(timer->fclk);
545
546 __omap_dm_timer_stop(timer, timer->posted, rate);
547
548 /*
549 * Since the register values are computed and written within
550 * __omap_dm_timer_stop, we need to use read to retrieve the
551 * context.
552 */
553 timer->context.tclr =
554 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
555 omap_dm_timer_disable(timer);
556 return 0;
557}
558
559static int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
560 unsigned int load)
561{
562 u32 l;
563
564 if (unlikely(!timer))
565 return -EINVAL;
566
567 omap_dm_timer_enable(timer);
568 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
569 if (autoreload)
570 l |= OMAP_TIMER_CTRL_AR;
571 else
572 l &= ~OMAP_TIMER_CTRL_AR;
573 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
574 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
575
576 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
577 /* Save the context */
578 timer->context.tclr = l;
579 timer->context.tldr = load;
580 omap_dm_timer_disable(timer);
581 return 0;
582}
583
584/* Optimized set_load which removes costly spin wait in timer_start */
585int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
586 unsigned int load)
587{
588 u32 l;
589
590 if (unlikely(!timer))
591 return -EINVAL;
592
593 omap_dm_timer_enable(timer);
594
595 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
596 if (autoreload) {
597 l |= OMAP_TIMER_CTRL_AR;
598 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
599 } else {
600 l &= ~OMAP_TIMER_CTRL_AR;
601 }
602 l |= OMAP_TIMER_CTRL_ST;
603
604 __omap_dm_timer_load_start(timer, l, load, timer->posted);
605
606 /* Save the context */
607 timer->context.tclr = l;
608 timer->context.tldr = load;
609 timer->context.tcrr = load;
610 return 0;
611}
612static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
613 unsigned int match)
614{
615 u32 l;
616
617 if (unlikely(!timer))
618 return -EINVAL;
619
620 omap_dm_timer_enable(timer);
621 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
622 if (enable)
623 l |= OMAP_TIMER_CTRL_CE;
624 else
625 l &= ~OMAP_TIMER_CTRL_CE;
626 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
627 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
628
629 /* Save the context */
630 timer->context.tclr = l;
631 timer->context.tmar = match;
632 omap_dm_timer_disable(timer);
633 return 0;
634}
635
636static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
637 int toggle, int trigger)
638{
639 u32 l;
640
641 if (unlikely(!timer))
642 return -EINVAL;
643
644 omap_dm_timer_enable(timer);
645 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
646 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
647 OMAP_TIMER_CTRL_PT | (0x03 << 10));
648 if (def_on)
649 l |= OMAP_TIMER_CTRL_SCPWM;
650 if (toggle)
651 l |= OMAP_TIMER_CTRL_PT;
652 l |= trigger << 10;
653 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
654
655 /* Save the context */
656 timer->context.tclr = l;
657 omap_dm_timer_disable(timer);
658 return 0;
659}
660
661static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
662 int prescaler)
663{
664 u32 l;
665
666 if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
667 return -EINVAL;
668
669 omap_dm_timer_enable(timer);
670 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
671 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
672 if (prescaler >= 0) {
673 l |= OMAP_TIMER_CTRL_PRE;
674 l |= prescaler << 2;
675 }
676 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
677
678 /* Save the context */
679 timer->context.tclr = l;
680 omap_dm_timer_disable(timer);
681 return 0;
682}
683
684static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
685 unsigned int value)
686{
687 if (unlikely(!timer))
688 return -EINVAL;
689
690 omap_dm_timer_enable(timer);
691 __omap_dm_timer_int_enable(timer, value);
692
693 /* Save the context */
694 timer->context.tier = value;
695 timer->context.twer = value;
696 omap_dm_timer_disable(timer);
697 return 0;
698}
699
700/**
701 * omap_dm_timer_set_int_disable - disable timer interrupts
702 * @timer: pointer to timer handle
703 * @mask: bit mask of interrupts to be disabled
704 *
705 * Disables the specified timer interrupts for a timer.
706 */
707static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
708{
709 u32 l = mask;
710
711 if (unlikely(!timer))
712 return -EINVAL;
713
714 omap_dm_timer_enable(timer);
715
716 if (timer->revision == 1)
717 l = readl_relaxed(timer->irq_ena) & ~mask;
718
719 writel_relaxed(l, timer->irq_dis);
720 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
721 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
722
723 /* Save the context */
724 timer->context.tier &= ~mask;
725 timer->context.twer &= ~mask;
726 omap_dm_timer_disable(timer);
727 return 0;
728}
729
730static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
731{
732 unsigned int l;
733
734 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
735 pr_err("%s: timer not available or enabled.\n", __func__);
736 return 0;
737 }
738
739 l = readl_relaxed(timer->irq_stat);
740
741 return l;
742}
743
744static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
745{
746 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
747 return -EINVAL;
748
749 __omap_dm_timer_write_status(timer, value);
750
751 return 0;
752}
753
754static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
755{
756 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
757 pr_err("%s: timer not iavailable or enabled.\n", __func__);
758 return 0;
759 }
760
761 return __omap_dm_timer_read_counter(timer, timer->posted);
762}
763
764static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
765{
766 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
767 pr_err("%s: timer not available or enabled.\n", __func__);
768 return -EINVAL;
769 }
770
771 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
772
773 /* Save the context */
774 timer->context.tcrr = value;
775 return 0;
776}
777
778int omap_dm_timers_active(void)
779{
780 struct omap_dm_timer *timer;
781
782 list_for_each_entry(timer, &omap_timer_list, node) {
783 if (!timer->reserved)
784 continue;
785
786 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
787 OMAP_TIMER_CTRL_ST) {
788 return 1;
789 }
790 }
791 return 0;
792}
793
794static const struct of_device_id omap_timer_match[];
795
796/**
797 * omap_dm_timer_probe - probe function called for every registered device
798 * @pdev: pointer to current timer platform device
799 *
800 * Called by driver framework at the end of device registration for all
801 * timer devices.
802 */
803static int omap_dm_timer_probe(struct platform_device *pdev)
804{
805 unsigned long flags;
806 struct omap_dm_timer *timer;
807 struct resource *mem, *irq;
808 struct device *dev = &pdev->dev;
809 const struct dmtimer_platform_data *pdata;
810 int ret;
811
812 pdata = of_device_get_match_data(dev);
813 if (!pdata)
814 pdata = dev_get_platdata(dev);
815 else
816 dev->platform_data = (void *)pdata;
817
818 if (!pdata) {
819 dev_err(dev, "%s: no platform data.\n", __func__);
820 return -ENODEV;
821 }
822
823 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
824 if (unlikely(!irq)) {
825 dev_err(dev, "%s: no IRQ resource.\n", __func__);
826 return -ENODEV;
827 }
828
829 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 if (unlikely(!mem)) {
831 dev_err(dev, "%s: no memory resource.\n", __func__);
832 return -ENODEV;
833 }
834
835 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
836 if (!timer)
837 return -ENOMEM;
838
839 timer->fclk = ERR_PTR(-ENODEV);
840 timer->io_base = devm_ioremap_resource(dev, mem);
841 if (IS_ERR(timer->io_base))
842 return PTR_ERR(timer->io_base);
843
844 if (dev->of_node) {
845 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
846 timer->capability |= OMAP_TIMER_ALWON;
847 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
848 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
849 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
850 timer->capability |= OMAP_TIMER_HAS_PWM;
851 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
852 timer->capability |= OMAP_TIMER_SECURE;
853 } else {
854 timer->id = pdev->id;
855 timer->capability = pdata->timer_capability;
856 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
857 timer->get_context_loss_count = pdata->get_context_loss_count;
858 }
859
860 if (pdata)
861 timer->errata = pdata->timer_errata;
862
863 timer->irq = irq->start;
864 timer->pdev = pdev;
865
866 pm_runtime_enable(dev);
867 pm_runtime_irq_safe(dev);
868
869 if (!timer->reserved) {
870 ret = pm_runtime_get_sync(dev);
871 if (ret < 0) {
872 dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
873 __func__);
874 goto err_get_sync;
875 }
876 __omap_dm_timer_init_regs(timer);
877 pm_runtime_put(dev);
878 }
879
880 /* add the timer element to the list */
881 spin_lock_irqsave(&dm_timer_lock, flags);
882 list_add_tail(&timer->node, &omap_timer_list);
883 spin_unlock_irqrestore(&dm_timer_lock, flags);
884
885 dev_dbg(dev, "Device Probed.\n");
886
887 return 0;
888
889err_get_sync:
890 pm_runtime_put_noidle(dev);
891 pm_runtime_disable(dev);
892 return ret;
893}
894
895/**
896 * omap_dm_timer_remove - cleanup a registered timer device
897 * @pdev: pointer to current timer platform device
898 *
899 * Called by driver framework whenever a timer device is unregistered.
900 * In addition to freeing platform resources it also deletes the timer
901 * entry from the local list.
902 */
903static int omap_dm_timer_remove(struct platform_device *pdev)
904{
905 struct omap_dm_timer *timer;
906 unsigned long flags;
907 int ret = -EINVAL;
908
909 spin_lock_irqsave(&dm_timer_lock, flags);
910 list_for_each_entry(timer, &omap_timer_list, node)
911 if (!strcmp(dev_name(&timer->pdev->dev),
912 dev_name(&pdev->dev))) {
913 list_del(&timer->node);
914 ret = 0;
915 break;
916 }
917 spin_unlock_irqrestore(&dm_timer_lock, flags);
918
919 pm_runtime_disable(&pdev->dev);
920
921 return ret;
922}
923
924const static struct omap_dm_timer_ops dmtimer_ops = {
925 .request_by_node = omap_dm_timer_request_by_node,
926 .request_specific = omap_dm_timer_request_specific,
927 .request = omap_dm_timer_request,
928 .set_source = omap_dm_timer_set_source,
929 .get_irq = omap_dm_timer_get_irq,
930 .set_int_enable = omap_dm_timer_set_int_enable,
931 .set_int_disable = omap_dm_timer_set_int_disable,
932 .free = omap_dm_timer_free,
933 .enable = omap_dm_timer_enable,
934 .disable = omap_dm_timer_disable,
935 .get_fclk = omap_dm_timer_get_fclk,
936 .start = omap_dm_timer_start,
937 .stop = omap_dm_timer_stop,
938 .set_load = omap_dm_timer_set_load,
939 .set_match = omap_dm_timer_set_match,
940 .set_pwm = omap_dm_timer_set_pwm,
941 .set_prescaler = omap_dm_timer_set_prescaler,
942 .read_counter = omap_dm_timer_read_counter,
943 .write_counter = omap_dm_timer_write_counter,
944 .read_status = omap_dm_timer_read_status,
945 .write_status = omap_dm_timer_write_status,
946};
947
948static const struct dmtimer_platform_data omap3plus_pdata = {
949 .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
950 .timer_ops = &dmtimer_ops,
951};
952
953static const struct of_device_id omap_timer_match[] = {
954 {
955 .compatible = "ti,omap2420-timer",
956 },
957 {
958 .compatible = "ti,omap3430-timer",
959 .data = &omap3plus_pdata,
960 },
961 {
962 .compatible = "ti,omap4430-timer",
963 .data = &omap3plus_pdata,
964 },
965 {
966 .compatible = "ti,omap5430-timer",
967 .data = &omap3plus_pdata,
968 },
969 {
970 .compatible = "ti,am335x-timer",
971 .data = &omap3plus_pdata,
972 },
973 {
974 .compatible = "ti,am335x-timer-1ms",
975 .data = &omap3plus_pdata,
976 },
977 {
978 .compatible = "ti,dm816-timer",
979 .data = &omap3plus_pdata,
980 },
981 {},
982};
983MODULE_DEVICE_TABLE(of, omap_timer_match);
984
985static struct platform_driver omap_dm_timer_driver = {
986 .probe = omap_dm_timer_probe,
987 .remove = omap_dm_timer_remove,
988 .driver = {
989 .name = "omap_timer",
990 .of_match_table = of_match_ptr(omap_timer_match),
991 },
992};
993
994early_platform_init("earlytimer", &omap_dm_timer_driver);
995module_platform_driver(omap_dm_timer_driver);
996
997MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
998MODULE_LICENSE("GPL");
999MODULE_ALIAS("platform:" DRIVER_NAME);
1000MODULE_AUTHOR("Texas Instruments Inc");