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1/*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21#undef DEBUG
22#undef DEBUG_LOW
23
24#define pr_fmt(fmt) "hash-mmu: " fmt
25#include <linux/spinlock.h>
26#include <linux/errno.h>
27#include <linux/sched/mm.h>
28#include <linux/proc_fs.h>
29#include <linux/stat.h>
30#include <linux/sysctl.h>
31#include <linux/export.h>
32#include <linux/ctype.h>
33#include <linux/cache.h>
34#include <linux/init.h>
35#include <linux/signal.h>
36#include <linux/memblock.h>
37#include <linux/context_tracking.h>
38#include <linux/libfdt.h>
39#include <linux/pkeys.h>
40
41#include <asm/debugfs.h>
42#include <asm/processor.h>
43#include <asm/pgtable.h>
44#include <asm/mmu.h>
45#include <asm/mmu_context.h>
46#include <asm/page.h>
47#include <asm/types.h>
48#include <linux/uaccess.h>
49#include <asm/machdep.h>
50#include <asm/prom.h>
51#include <asm/tlbflush.h>
52#include <asm/io.h>
53#include <asm/eeh.h>
54#include <asm/tlb.h>
55#include <asm/cacheflush.h>
56#include <asm/cputable.h>
57#include <asm/sections.h>
58#include <asm/copro.h>
59#include <asm/udbg.h>
60#include <asm/code-patching.h>
61#include <asm/fadump.h>
62#include <asm/firmware.h>
63#include <asm/tm.h>
64#include <asm/trace.h>
65#include <asm/ps3.h>
66#include <asm/pte-walk.h>
67
68#ifdef DEBUG
69#define DBG(fmt...) udbg_printf(fmt)
70#else
71#define DBG(fmt...)
72#endif
73
74#ifdef DEBUG_LOW
75#define DBG_LOW(fmt...) udbg_printf(fmt)
76#else
77#define DBG_LOW(fmt...)
78#endif
79
80#define KB (1024)
81#define MB (1024*KB)
82#define GB (1024L*MB)
83
84/*
85 * Note: pte --> Linux PTE
86 * HPTE --> PowerPC Hashed Page Table Entry
87 *
88 * Execution context:
89 * htab_initialize is called with the MMU off (of course), but
90 * the kernel has been copied down to zero so it can directly
91 * reference global data. At this point it is very difficult
92 * to print debug info.
93 *
94 */
95
96static unsigned long _SDR1;
97struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
98EXPORT_SYMBOL_GPL(mmu_psize_defs);
99
100u8 hpte_page_sizes[1 << LP_BITS];
101EXPORT_SYMBOL_GPL(hpte_page_sizes);
102
103struct hash_pte *htab_address;
104unsigned long htab_size_bytes;
105unsigned long htab_hash_mask;
106EXPORT_SYMBOL_GPL(htab_hash_mask);
107int mmu_linear_psize = MMU_PAGE_4K;
108EXPORT_SYMBOL_GPL(mmu_linear_psize);
109int mmu_virtual_psize = MMU_PAGE_4K;
110int mmu_vmalloc_psize = MMU_PAGE_4K;
111#ifdef CONFIG_SPARSEMEM_VMEMMAP
112int mmu_vmemmap_psize = MMU_PAGE_4K;
113#endif
114int mmu_io_psize = MMU_PAGE_4K;
115int mmu_kernel_ssize = MMU_SEGSIZE_256M;
116EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
117int mmu_highuser_ssize = MMU_SEGSIZE_256M;
118u16 mmu_slb_size = 64;
119EXPORT_SYMBOL_GPL(mmu_slb_size);
120#ifdef CONFIG_PPC_64K_PAGES
121int mmu_ci_restrictions;
122#endif
123#ifdef CONFIG_DEBUG_PAGEALLOC
124static u8 *linear_map_hash_slots;
125static unsigned long linear_map_hash_count;
126static DEFINE_SPINLOCK(linear_map_hash_lock);
127#endif /* CONFIG_DEBUG_PAGEALLOC */
128struct mmu_hash_ops mmu_hash_ops;
129EXPORT_SYMBOL(mmu_hash_ops);
130
131/* There are definitions of page sizes arrays to be used when none
132 * is provided by the firmware.
133 */
134
135/*
136 * Fallback (4k pages only)
137 */
138static struct mmu_psize_def mmu_psize_defaults[] = {
139 [MMU_PAGE_4K] = {
140 .shift = 12,
141 .sllp = 0,
142 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
143 .avpnm = 0,
144 .tlbiel = 0,
145 },
146};
147
148/* POWER4, GPUL, POWER5
149 *
150 * Support for 16Mb large pages
151 */
152static struct mmu_psize_def mmu_psize_defaults_gp[] = {
153 [MMU_PAGE_4K] = {
154 .shift = 12,
155 .sllp = 0,
156 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
157 .avpnm = 0,
158 .tlbiel = 1,
159 },
160 [MMU_PAGE_16M] = {
161 .shift = 24,
162 .sllp = SLB_VSID_L,
163 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
164 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
165 .avpnm = 0x1UL,
166 .tlbiel = 0,
167 },
168};
169
170/*
171 * 'R' and 'C' update notes:
172 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
173 * create writeable HPTEs without C set, because the hcall H_PROTECT
174 * that we use in that case will not update C
175 * - The above is however not a problem, because we also don't do that
176 * fancy "no flush" variant of eviction and we use H_REMOVE which will
177 * do the right thing and thus we don't have the race I described earlier
178 *
179 * - Under bare metal, we do have the race, so we need R and C set
180 * - We make sure R is always set and never lost
181 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
182 */
183unsigned long htab_convert_pte_flags(unsigned long pteflags)
184{
185 unsigned long rflags = 0;
186
187 /* _PAGE_EXEC -> NOEXEC */
188 if ((pteflags & _PAGE_EXEC) == 0)
189 rflags |= HPTE_R_N;
190 /*
191 * PPP bits:
192 * Linux uses slb key 0 for kernel and 1 for user.
193 * kernel RW areas are mapped with PPP=0b000
194 * User area is mapped with PPP=0b010 for read/write
195 * or PPP=0b011 for read-only (including writeable but clean pages).
196 */
197 if (pteflags & _PAGE_PRIVILEGED) {
198 /*
199 * Kernel read only mapped with ppp bits 0b110
200 */
201 if (!(pteflags & _PAGE_WRITE)) {
202 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
203 rflags |= (HPTE_R_PP0 | 0x2);
204 else
205 rflags |= 0x3;
206 }
207 } else {
208 if (pteflags & _PAGE_RWX)
209 rflags |= 0x2;
210 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
211 rflags |= 0x1;
212 }
213 /*
214 * We can't allow hardware to update hpte bits. Hence always
215 * set 'R' bit and set 'C' if it is a write fault
216 */
217 rflags |= HPTE_R_R;
218
219 if (pteflags & _PAGE_DIRTY)
220 rflags |= HPTE_R_C;
221 /*
222 * Add in WIG bits
223 */
224
225 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
226 rflags |= HPTE_R_I;
227 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
228 rflags |= (HPTE_R_I | HPTE_R_G);
229 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
230 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
231 else
232 /*
233 * Add memory coherence if cache inhibited is not set
234 */
235 rflags |= HPTE_R_M;
236
237 rflags |= pte_to_hpte_pkey_bits(pteflags);
238 return rflags;
239}
240
241int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
242 unsigned long pstart, unsigned long prot,
243 int psize, int ssize)
244{
245 unsigned long vaddr, paddr;
246 unsigned int step, shift;
247 int ret = 0;
248
249 shift = mmu_psize_defs[psize].shift;
250 step = 1 << shift;
251
252 prot = htab_convert_pte_flags(prot);
253
254 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
255 vstart, vend, pstart, prot, psize, ssize);
256
257 for (vaddr = vstart, paddr = pstart; vaddr < vend;
258 vaddr += step, paddr += step) {
259 unsigned long hash, hpteg;
260 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
261 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
262 unsigned long tprot = prot;
263
264 /*
265 * If we hit a bad address return error.
266 */
267 if (!vsid)
268 return -1;
269 /* Make kernel text executable */
270 if (overlaps_kernel_text(vaddr, vaddr + step))
271 tprot &= ~HPTE_R_N;
272
273 /* Make kvm guest trampolines executable */
274 if (overlaps_kvm_tmp(vaddr, vaddr + step))
275 tprot &= ~HPTE_R_N;
276
277 /*
278 * If relocatable, check if it overlaps interrupt vectors that
279 * are copied down to real 0. For relocatable kernel
280 * (e.g. kdump case) we copy interrupt vectors down to real
281 * address 0. Mark that region as executable. This is
282 * because on p8 system with relocation on exception feature
283 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
284 * in order to execute the interrupt handlers in virtual
285 * mode the vector region need to be marked as executable.
286 */
287 if ((PHYSICAL_START > MEMORY_START) &&
288 overlaps_interrupt_vector_text(vaddr, vaddr + step))
289 tprot &= ~HPTE_R_N;
290
291 hash = hpt_hash(vpn, shift, ssize);
292 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
293
294 BUG_ON(!mmu_hash_ops.hpte_insert);
295 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
296 HPTE_V_BOLTED, psize, psize,
297 ssize);
298
299 if (ret < 0)
300 break;
301
302#ifdef CONFIG_DEBUG_PAGEALLOC
303 if (debug_pagealloc_enabled() &&
304 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
305 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
306#endif /* CONFIG_DEBUG_PAGEALLOC */
307 }
308 return ret < 0 ? ret : 0;
309}
310
311int htab_remove_mapping(unsigned long vstart, unsigned long vend,
312 int psize, int ssize)
313{
314 unsigned long vaddr;
315 unsigned int step, shift;
316 int rc;
317 int ret = 0;
318
319 shift = mmu_psize_defs[psize].shift;
320 step = 1 << shift;
321
322 if (!mmu_hash_ops.hpte_removebolted)
323 return -ENODEV;
324
325 for (vaddr = vstart; vaddr < vend; vaddr += step) {
326 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
327 if (rc == -ENOENT) {
328 ret = -ENOENT;
329 continue;
330 }
331 if (rc < 0)
332 return rc;
333 }
334
335 return ret;
336}
337
338static bool disable_1tb_segments = false;
339
340static int __init parse_disable_1tb_segments(char *p)
341{
342 disable_1tb_segments = true;
343 return 0;
344}
345early_param("disable_1tb_segments", parse_disable_1tb_segments);
346
347static int __init htab_dt_scan_seg_sizes(unsigned long node,
348 const char *uname, int depth,
349 void *data)
350{
351 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
352 const __be32 *prop;
353 int size = 0;
354
355 /* We are scanning "cpu" nodes only */
356 if (type == NULL || strcmp(type, "cpu") != 0)
357 return 0;
358
359 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
360 if (prop == NULL)
361 return 0;
362 for (; size >= 4; size -= 4, ++prop) {
363 if (be32_to_cpu(prop[0]) == 40) {
364 DBG("1T segment support detected\n");
365
366 if (disable_1tb_segments) {
367 DBG("1T segments disabled by command line\n");
368 break;
369 }
370
371 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
372 return 1;
373 }
374 }
375 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
376 return 0;
377}
378
379static int __init get_idx_from_shift(unsigned int shift)
380{
381 int idx = -1;
382
383 switch (shift) {
384 case 0xc:
385 idx = MMU_PAGE_4K;
386 break;
387 case 0x10:
388 idx = MMU_PAGE_64K;
389 break;
390 case 0x14:
391 idx = MMU_PAGE_1M;
392 break;
393 case 0x18:
394 idx = MMU_PAGE_16M;
395 break;
396 case 0x22:
397 idx = MMU_PAGE_16G;
398 break;
399 }
400 return idx;
401}
402
403static int __init htab_dt_scan_page_sizes(unsigned long node,
404 const char *uname, int depth,
405 void *data)
406{
407 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
408 const __be32 *prop;
409 int size = 0;
410
411 /* We are scanning "cpu" nodes only */
412 if (type == NULL || strcmp(type, "cpu") != 0)
413 return 0;
414
415 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
416 if (!prop)
417 return 0;
418
419 pr_info("Page sizes from device-tree:\n");
420 size /= 4;
421 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
422 while(size > 0) {
423 unsigned int base_shift = be32_to_cpu(prop[0]);
424 unsigned int slbenc = be32_to_cpu(prop[1]);
425 unsigned int lpnum = be32_to_cpu(prop[2]);
426 struct mmu_psize_def *def;
427 int idx, base_idx;
428
429 size -= 3; prop += 3;
430 base_idx = get_idx_from_shift(base_shift);
431 if (base_idx < 0) {
432 /* skip the pte encoding also */
433 prop += lpnum * 2; size -= lpnum * 2;
434 continue;
435 }
436 def = &mmu_psize_defs[base_idx];
437 if (base_idx == MMU_PAGE_16M)
438 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
439
440 def->shift = base_shift;
441 if (base_shift <= 23)
442 def->avpnm = 0;
443 else
444 def->avpnm = (1 << (base_shift - 23)) - 1;
445 def->sllp = slbenc;
446 /*
447 * We don't know for sure what's up with tlbiel, so
448 * for now we only set it for 4K and 64K pages
449 */
450 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
451 def->tlbiel = 1;
452 else
453 def->tlbiel = 0;
454
455 while (size > 0 && lpnum) {
456 unsigned int shift = be32_to_cpu(prop[0]);
457 int penc = be32_to_cpu(prop[1]);
458
459 prop += 2; size -= 2;
460 lpnum--;
461
462 idx = get_idx_from_shift(shift);
463 if (idx < 0)
464 continue;
465
466 if (penc == -1)
467 pr_err("Invalid penc for base_shift=%d "
468 "shift=%d\n", base_shift, shift);
469
470 def->penc[idx] = penc;
471 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
472 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
473 base_shift, shift, def->sllp,
474 def->avpnm, def->tlbiel, def->penc[idx]);
475 }
476 }
477
478 return 1;
479}
480
481#ifdef CONFIG_HUGETLB_PAGE
482/* Scan for 16G memory blocks that have been set aside for huge pages
483 * and reserve those blocks for 16G huge pages.
484 */
485static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
486 const char *uname, int depth,
487 void *data) {
488 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
489 const __be64 *addr_prop;
490 const __be32 *page_count_prop;
491 unsigned int expected_pages;
492 long unsigned int phys_addr;
493 long unsigned int block_size;
494
495 /* We are scanning "memory" nodes only */
496 if (type == NULL || strcmp(type, "memory") != 0)
497 return 0;
498
499 /* This property is the log base 2 of the number of virtual pages that
500 * will represent this memory block. */
501 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
502 if (page_count_prop == NULL)
503 return 0;
504 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
505 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
506 if (addr_prop == NULL)
507 return 0;
508 phys_addr = be64_to_cpu(addr_prop[0]);
509 block_size = be64_to_cpu(addr_prop[1]);
510 if (block_size != (16 * GB))
511 return 0;
512 printk(KERN_INFO "Huge page(16GB) memory: "
513 "addr = 0x%lX size = 0x%lX pages = %d\n",
514 phys_addr, block_size, expected_pages);
515 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
516 memblock_reserve(phys_addr, block_size * expected_pages);
517 pseries_add_gpage(phys_addr, block_size, expected_pages);
518 }
519 return 0;
520}
521#endif /* CONFIG_HUGETLB_PAGE */
522
523static void mmu_psize_set_default_penc(void)
524{
525 int bpsize, apsize;
526 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
527 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
528 mmu_psize_defs[bpsize].penc[apsize] = -1;
529}
530
531#ifdef CONFIG_PPC_64K_PAGES
532
533static bool might_have_hea(void)
534{
535 /*
536 * The HEA ethernet adapter requires awareness of the
537 * GX bus. Without that awareness we can easily assume
538 * we will never see an HEA ethernet device.
539 */
540#ifdef CONFIG_IBMEBUS
541 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
542 firmware_has_feature(FW_FEATURE_SPLPAR);
543#else
544 return false;
545#endif
546}
547
548#endif /* #ifdef CONFIG_PPC_64K_PAGES */
549
550static void __init htab_scan_page_sizes(void)
551{
552 int rc;
553
554 /* se the invalid penc to -1 */
555 mmu_psize_set_default_penc();
556
557 /* Default to 4K pages only */
558 memcpy(mmu_psize_defs, mmu_psize_defaults,
559 sizeof(mmu_psize_defaults));
560
561 /*
562 * Try to find the available page sizes in the device-tree
563 */
564 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
565 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
566 /*
567 * Nothing in the device-tree, but the CPU supports 16M pages,
568 * so let's fallback on a known size list for 16M capable CPUs.
569 */
570 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
571 sizeof(mmu_psize_defaults_gp));
572 }
573
574#ifdef CONFIG_HUGETLB_PAGE
575 /* Reserve 16G huge page memory sections for huge pages */
576 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
577#endif /* CONFIG_HUGETLB_PAGE */
578}
579
580/*
581 * Fill in the hpte_page_sizes[] array.
582 * We go through the mmu_psize_defs[] array looking for all the
583 * supported base/actual page size combinations. Each combination
584 * has a unique pagesize encoding (penc) value in the low bits of
585 * the LP field of the HPTE. For actual page sizes less than 1MB,
586 * some of the upper LP bits are used for RPN bits, meaning that
587 * we need to fill in several entries in hpte_page_sizes[].
588 *
589 * In diagrammatic form, with r = RPN bits and z = page size bits:
590 * PTE LP actual page size
591 * rrrr rrrz >=8KB
592 * rrrr rrzz >=16KB
593 * rrrr rzzz >=32KB
594 * rrrr zzzz >=64KB
595 * ...
596 *
597 * The zzzz bits are implementation-specific but are chosen so that
598 * no encoding for a larger page size uses the same value in its
599 * low-order N bits as the encoding for the 2^(12+N) byte page size
600 * (if it exists).
601 */
602static void init_hpte_page_sizes(void)
603{
604 long int ap, bp;
605 long int shift, penc;
606
607 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
608 if (!mmu_psize_defs[bp].shift)
609 continue; /* not a supported page size */
610 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
611 penc = mmu_psize_defs[bp].penc[ap];
612 if (penc == -1 || !mmu_psize_defs[ap].shift)
613 continue;
614 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
615 if (shift <= 0)
616 continue; /* should never happen */
617 /*
618 * For page sizes less than 1MB, this loop
619 * replicates the entry for all possible values
620 * of the rrrr bits.
621 */
622 while (penc < (1 << LP_BITS)) {
623 hpte_page_sizes[penc] = (ap << 4) | bp;
624 penc += 1 << shift;
625 }
626 }
627 }
628}
629
630static void __init htab_init_page_sizes(void)
631{
632 init_hpte_page_sizes();
633
634 if (!debug_pagealloc_enabled()) {
635 /*
636 * Pick a size for the linear mapping. Currently, we only
637 * support 16M, 1M and 4K which is the default
638 */
639 if (mmu_psize_defs[MMU_PAGE_16M].shift)
640 mmu_linear_psize = MMU_PAGE_16M;
641 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
642 mmu_linear_psize = MMU_PAGE_1M;
643 }
644
645#ifdef CONFIG_PPC_64K_PAGES
646 /*
647 * Pick a size for the ordinary pages. Default is 4K, we support
648 * 64K for user mappings and vmalloc if supported by the processor.
649 * We only use 64k for ioremap if the processor
650 * (and firmware) support cache-inhibited large pages.
651 * If not, we use 4k and set mmu_ci_restrictions so that
652 * hash_page knows to switch processes that use cache-inhibited
653 * mappings to 4k pages.
654 */
655 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
656 mmu_virtual_psize = MMU_PAGE_64K;
657 mmu_vmalloc_psize = MMU_PAGE_64K;
658 if (mmu_linear_psize == MMU_PAGE_4K)
659 mmu_linear_psize = MMU_PAGE_64K;
660 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
661 /*
662 * When running on pSeries using 64k pages for ioremap
663 * would stop us accessing the HEA ethernet. So if we
664 * have the chance of ever seeing one, stay at 4k.
665 */
666 if (!might_have_hea())
667 mmu_io_psize = MMU_PAGE_64K;
668 } else
669 mmu_ci_restrictions = 1;
670 }
671#endif /* CONFIG_PPC_64K_PAGES */
672
673#ifdef CONFIG_SPARSEMEM_VMEMMAP
674 /* We try to use 16M pages for vmemmap if that is supported
675 * and we have at least 1G of RAM at boot
676 */
677 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
678 memblock_phys_mem_size() >= 0x40000000)
679 mmu_vmemmap_psize = MMU_PAGE_16M;
680 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
681 mmu_vmemmap_psize = MMU_PAGE_64K;
682 else
683 mmu_vmemmap_psize = MMU_PAGE_4K;
684#endif /* CONFIG_SPARSEMEM_VMEMMAP */
685
686 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
687 "virtual = %d, io = %d"
688#ifdef CONFIG_SPARSEMEM_VMEMMAP
689 ", vmemmap = %d"
690#endif
691 "\n",
692 mmu_psize_defs[mmu_linear_psize].shift,
693 mmu_psize_defs[mmu_virtual_psize].shift,
694 mmu_psize_defs[mmu_io_psize].shift
695#ifdef CONFIG_SPARSEMEM_VMEMMAP
696 ,mmu_psize_defs[mmu_vmemmap_psize].shift
697#endif
698 );
699}
700
701static int __init htab_dt_scan_pftsize(unsigned long node,
702 const char *uname, int depth,
703 void *data)
704{
705 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
706 const __be32 *prop;
707
708 /* We are scanning "cpu" nodes only */
709 if (type == NULL || strcmp(type, "cpu") != 0)
710 return 0;
711
712 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
713 if (prop != NULL) {
714 /* pft_size[0] is the NUMA CEC cookie */
715 ppc64_pft_size = be32_to_cpu(prop[1]);
716 return 1;
717 }
718 return 0;
719}
720
721unsigned htab_shift_for_mem_size(unsigned long mem_size)
722{
723 unsigned memshift = __ilog2(mem_size);
724 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
725 unsigned pteg_shift;
726
727 /* round mem_size up to next power of 2 */
728 if ((1UL << memshift) < mem_size)
729 memshift += 1;
730
731 /* aim for 2 pages / pteg */
732 pteg_shift = memshift - (pshift + 1);
733
734 /*
735 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
736 * size permitted by the architecture.
737 */
738 return max(pteg_shift + 7, 18U);
739}
740
741static unsigned long __init htab_get_table_size(void)
742{
743 /* If hash size isn't already provided by the platform, we try to
744 * retrieve it from the device-tree. If it's not there neither, we
745 * calculate it now based on the total RAM size
746 */
747 if (ppc64_pft_size == 0)
748 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
749 if (ppc64_pft_size)
750 return 1UL << ppc64_pft_size;
751
752 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
753}
754
755#ifdef CONFIG_MEMORY_HOTPLUG
756void resize_hpt_for_hotplug(unsigned long new_mem_size)
757{
758 unsigned target_hpt_shift;
759
760 if (!mmu_hash_ops.resize_hpt)
761 return;
762
763 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
764
765 /*
766 * To avoid lots of HPT resizes if memory size is fluctuating
767 * across a boundary, we deliberately have some hysterisis
768 * here: we immediately increase the HPT size if the target
769 * shift exceeds the current shift, but we won't attempt to
770 * reduce unless the target shift is at least 2 below the
771 * current shift
772 */
773 if ((target_hpt_shift > ppc64_pft_size)
774 || (target_hpt_shift < (ppc64_pft_size - 1))) {
775 int rc;
776
777 rc = mmu_hash_ops.resize_hpt(target_hpt_shift);
778 if (rc && (rc != -ENODEV))
779 printk(KERN_WARNING
780 "Unable to resize hash page table to target order %d: %d\n",
781 target_hpt_shift, rc);
782 }
783}
784
785int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
786{
787 int rc = htab_bolt_mapping(start, end, __pa(start),
788 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
789 mmu_kernel_ssize);
790
791 if (rc < 0) {
792 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
793 mmu_kernel_ssize);
794 BUG_ON(rc2 && (rc2 != -ENOENT));
795 }
796 return rc;
797}
798
799int hash__remove_section_mapping(unsigned long start, unsigned long end)
800{
801 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
802 mmu_kernel_ssize);
803 WARN_ON(rc < 0);
804 return rc;
805}
806#endif /* CONFIG_MEMORY_HOTPLUG */
807
808static void update_hid_for_hash(void)
809{
810 unsigned long hid0;
811 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
812
813 asm volatile("ptesync": : :"memory");
814 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
815 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
816 : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
817 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
818 trace_tlbie(0, 0, rb, 0, 2, 0, 0);
819
820 /*
821 * now switch the HID
822 */
823 hid0 = mfspr(SPRN_HID0);
824 hid0 &= ~HID0_POWER9_RADIX;
825 mtspr(SPRN_HID0, hid0);
826 asm volatile("isync": : :"memory");
827
828 /* Wait for it to happen */
829 while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
830 cpu_relax();
831}
832
833static void __init hash_init_partition_table(phys_addr_t hash_table,
834 unsigned long htab_size)
835{
836 mmu_partition_table_init();
837
838 /*
839 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
840 * For now, UPRT is 0 and we have no segment table.
841 */
842 htab_size = __ilog2(htab_size) - 18;
843 mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
844 pr_info("Partition table %p\n", partition_tb);
845 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
846 update_hid_for_hash();
847}
848
849static void __init htab_initialize(void)
850{
851 unsigned long table;
852 unsigned long pteg_count;
853 unsigned long prot;
854 unsigned long base = 0, size = 0;
855 struct memblock_region *reg;
856
857 DBG(" -> htab_initialize()\n");
858
859 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
860 mmu_kernel_ssize = MMU_SEGSIZE_1T;
861 mmu_highuser_ssize = MMU_SEGSIZE_1T;
862 printk(KERN_INFO "Using 1TB segments\n");
863 }
864
865 /*
866 * Calculate the required size of the htab. We want the number of
867 * PTEGs to equal one half the number of real pages.
868 */
869 htab_size_bytes = htab_get_table_size();
870 pteg_count = htab_size_bytes >> 7;
871
872 htab_hash_mask = pteg_count - 1;
873
874 if (firmware_has_feature(FW_FEATURE_LPAR) ||
875 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
876 /* Using a hypervisor which owns the htab */
877 htab_address = NULL;
878 _SDR1 = 0;
879 /*
880 * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall
881 * to inform the hypervisor that we wish to use the HPT.
882 */
883 if (cpu_has_feature(CPU_FTR_ARCH_300))
884 register_process_table(0, 0, 0);
885#ifdef CONFIG_FA_DUMP
886 /*
887 * If firmware assisted dump is active firmware preserves
888 * the contents of htab along with entire partition memory.
889 * Clear the htab if firmware assisted dump is active so
890 * that we dont end up using old mappings.
891 */
892 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
893 mmu_hash_ops.hpte_clear_all();
894#endif
895 } else {
896 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
897
898#ifdef CONFIG_PPC_CELL
899 /*
900 * Cell may require the hash table down low when using the
901 * Axon IOMMU in order to fit the dynamic region over it, see
902 * comments in cell/iommu.c
903 */
904 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
905 limit = 0x80000000;
906 pr_info("Hash table forced below 2G for Axon IOMMU\n");
907 }
908#endif /* CONFIG_PPC_CELL */
909
910 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
911 limit);
912
913 DBG("Hash table allocated at %lx, size: %lx\n", table,
914 htab_size_bytes);
915
916 htab_address = __va(table);
917
918 /* htab absolute addr + encoded htabsize */
919 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
920
921 /* Initialize the HPT with no entries */
922 memset((void *)table, 0, htab_size_bytes);
923
924 if (!cpu_has_feature(CPU_FTR_ARCH_300))
925 /* Set SDR1 */
926 mtspr(SPRN_SDR1, _SDR1);
927 else
928 hash_init_partition_table(table, htab_size_bytes);
929 }
930
931 prot = pgprot_val(PAGE_KERNEL);
932
933#ifdef CONFIG_DEBUG_PAGEALLOC
934 if (debug_pagealloc_enabled()) {
935 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
936 linear_map_hash_slots = __va(memblock_alloc_base(
937 linear_map_hash_count, 1, ppc64_rma_size));
938 memset(linear_map_hash_slots, 0, linear_map_hash_count);
939 }
940#endif /* CONFIG_DEBUG_PAGEALLOC */
941
942 /* create bolted the linear mapping in the hash table */
943 for_each_memblock(memory, reg) {
944 base = (unsigned long)__va(reg->base);
945 size = reg->size;
946
947 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
948 base, size, prot);
949
950 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
951 prot, mmu_linear_psize, mmu_kernel_ssize));
952 }
953 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
954
955 /*
956 * If we have a memory_limit and we've allocated TCEs then we need to
957 * explicitly map the TCE area at the top of RAM. We also cope with the
958 * case that the TCEs start below memory_limit.
959 * tce_alloc_start/end are 16MB aligned so the mapping should work
960 * for either 4K or 16MB pages.
961 */
962 if (tce_alloc_start) {
963 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
964 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
965
966 if (base + size >= tce_alloc_start)
967 tce_alloc_start = base + size + 1;
968
969 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
970 __pa(tce_alloc_start), prot,
971 mmu_linear_psize, mmu_kernel_ssize));
972 }
973
974
975 DBG(" <- htab_initialize()\n");
976}
977#undef KB
978#undef MB
979
980void __init hash__early_init_devtree(void)
981{
982 /* Initialize segment sizes */
983 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
984
985 /* Initialize page sizes */
986 htab_scan_page_sizes();
987}
988
989void __init hash__early_init_mmu(void)
990{
991#ifndef CONFIG_PPC_64K_PAGES
992 /*
993 * We have code in __hash_page_4K() and elsewhere, which assumes it can
994 * do the following:
995 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
996 *
997 * Where the slot number is between 0-15, and values of 8-15 indicate
998 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
999 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
1000 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
1001 * with a BUILD_BUG_ON().
1002 */
1003 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
1004#endif /* CONFIG_PPC_64K_PAGES */
1005
1006 htab_init_page_sizes();
1007
1008 /*
1009 * initialize page table size
1010 */
1011 __pte_frag_nr = H_PTE_FRAG_NR;
1012 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1013
1014 __pte_index_size = H_PTE_INDEX_SIZE;
1015 __pmd_index_size = H_PMD_INDEX_SIZE;
1016 __pud_index_size = H_PUD_INDEX_SIZE;
1017 __pgd_index_size = H_PGD_INDEX_SIZE;
1018 __pud_cache_index = H_PUD_CACHE_INDEX;
1019 __pmd_cache_index = H_PMD_CACHE_INDEX;
1020 __pte_table_size = H_PTE_TABLE_SIZE;
1021 __pmd_table_size = H_PMD_TABLE_SIZE;
1022 __pud_table_size = H_PUD_TABLE_SIZE;
1023 __pgd_table_size = H_PGD_TABLE_SIZE;
1024 /*
1025 * 4k use hugepd format, so for hash set then to
1026 * zero
1027 */
1028 __pmd_val_bits = 0;
1029 __pud_val_bits = 0;
1030 __pgd_val_bits = 0;
1031
1032 __kernel_virt_start = H_KERN_VIRT_START;
1033 __kernel_virt_size = H_KERN_VIRT_SIZE;
1034 __vmalloc_start = H_VMALLOC_START;
1035 __vmalloc_end = H_VMALLOC_END;
1036 __kernel_io_start = H_KERN_IO_START;
1037 vmemmap = (struct page *)H_VMEMMAP_BASE;
1038 ioremap_bot = IOREMAP_BASE;
1039
1040#ifdef CONFIG_PCI
1041 pci_io_base = ISA_IO_BASE;
1042#endif
1043
1044 /* Select appropriate backend */
1045 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1046 ps3_early_mm_init();
1047 else if (firmware_has_feature(FW_FEATURE_LPAR))
1048 hpte_init_pseries();
1049 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1050 hpte_init_native();
1051
1052 if (!mmu_hash_ops.hpte_insert)
1053 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1054
1055 /* Initialize the MMU Hash table and create the linear mapping
1056 * of memory. Has to be done before SLB initialization as this is
1057 * currently where the page size encoding is obtained.
1058 */
1059 htab_initialize();
1060
1061 pr_info("Initializing hash mmu with SLB\n");
1062 /* Initialize SLB management */
1063 slb_initialize();
1064
1065 if (cpu_has_feature(CPU_FTR_ARCH_206)
1066 && cpu_has_feature(CPU_FTR_HVMODE))
1067 tlbiel_all();
1068}
1069
1070#ifdef CONFIG_SMP
1071void hash__early_init_mmu_secondary(void)
1072{
1073 /* Initialize hash table for that CPU */
1074 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1075
1076 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
1077 update_hid_for_hash();
1078
1079 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1080 mtspr(SPRN_SDR1, _SDR1);
1081 else
1082 mtspr(SPRN_PTCR,
1083 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1084 }
1085 /* Initialize SLB */
1086 slb_initialize();
1087
1088 if (cpu_has_feature(CPU_FTR_ARCH_206)
1089 && cpu_has_feature(CPU_FTR_HVMODE))
1090 tlbiel_all();
1091}
1092#endif /* CONFIG_SMP */
1093
1094/*
1095 * Called by asm hashtable.S for doing lazy icache flush
1096 */
1097unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1098{
1099 struct page *page;
1100
1101 if (!pfn_valid(pte_pfn(pte)))
1102 return pp;
1103
1104 page = pte_page(pte);
1105
1106 /* page is dirty */
1107 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1108 if (trap == 0x400) {
1109 flush_dcache_icache_page(page);
1110 set_bit(PG_arch_1, &page->flags);
1111 } else
1112 pp |= HPTE_R_N;
1113 }
1114 return pp;
1115}
1116
1117#ifdef CONFIG_PPC_MM_SLICES
1118static unsigned int get_paca_psize(unsigned long addr)
1119{
1120 unsigned char *psizes;
1121 unsigned long index, mask_index;
1122
1123 if (addr < SLICE_LOW_TOP) {
1124 psizes = get_paca()->mm_ctx_low_slices_psize;
1125 index = GET_LOW_SLICE_INDEX(addr);
1126 } else {
1127 psizes = get_paca()->mm_ctx_high_slices_psize;
1128 index = GET_HIGH_SLICE_INDEX(addr);
1129 }
1130 mask_index = index & 0x1;
1131 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1132}
1133
1134#else
1135unsigned int get_paca_psize(unsigned long addr)
1136{
1137 return get_paca()->mm_ctx_user_psize;
1138}
1139#endif
1140
1141/*
1142 * Demote a segment to using 4k pages.
1143 * For now this makes the whole process use 4k pages.
1144 */
1145#ifdef CONFIG_PPC_64K_PAGES
1146void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1147{
1148 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1149 return;
1150 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1151 copro_flush_all_slbs(mm);
1152 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1153
1154 copy_mm_to_paca(mm);
1155 slb_flush_and_rebolt();
1156 }
1157}
1158#endif /* CONFIG_PPC_64K_PAGES */
1159
1160#ifdef CONFIG_PPC_SUBPAGE_PROT
1161/*
1162 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1163 * Userspace sets the subpage permissions using the subpage_prot system call.
1164 *
1165 * Result is 0: full permissions, _PAGE_RW: read-only,
1166 * _PAGE_RWX: no access.
1167 */
1168static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1169{
1170 struct subpage_prot_table *spt = &mm->context.spt;
1171 u32 spp = 0;
1172 u32 **sbpm, *sbpp;
1173
1174 if (ea >= spt->maxaddr)
1175 return 0;
1176 if (ea < 0x100000000UL) {
1177 /* addresses below 4GB use spt->low_prot */
1178 sbpm = spt->low_prot;
1179 } else {
1180 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1181 if (!sbpm)
1182 return 0;
1183 }
1184 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1185 if (!sbpp)
1186 return 0;
1187 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1188
1189 /* extract 2-bit bitfield for this 4k subpage */
1190 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1191
1192 /*
1193 * 0 -> full premission
1194 * 1 -> Read only
1195 * 2 -> no access.
1196 * We return the flag that need to be cleared.
1197 */
1198 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1199 return spp;
1200}
1201
1202#else /* CONFIG_PPC_SUBPAGE_PROT */
1203static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1204{
1205 return 0;
1206}
1207#endif
1208
1209void hash_failure_debug(unsigned long ea, unsigned long access,
1210 unsigned long vsid, unsigned long trap,
1211 int ssize, int psize, int lpsize, unsigned long pte)
1212{
1213 if (!printk_ratelimit())
1214 return;
1215 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1216 ea, access, current->comm);
1217 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1218 trap, vsid, ssize, psize, lpsize, pte);
1219}
1220
1221static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1222 int psize, bool user_region)
1223{
1224 if (user_region) {
1225 if (psize != get_paca_psize(ea)) {
1226 copy_mm_to_paca(mm);
1227 slb_flush_and_rebolt();
1228 }
1229 } else if (get_paca()->vmalloc_sllp !=
1230 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1231 get_paca()->vmalloc_sllp =
1232 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1233 slb_vmalloc_update();
1234 }
1235}
1236
1237/* Result code is:
1238 * 0 - handled
1239 * 1 - normal page fault
1240 * -1 - critical hash insertion error
1241 * -2 - access not permitted by subpage protection mechanism
1242 */
1243int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1244 unsigned long access, unsigned long trap,
1245 unsigned long flags)
1246{
1247 bool is_thp;
1248 enum ctx_state prev_state = exception_enter();
1249 pgd_t *pgdir;
1250 unsigned long vsid;
1251 pte_t *ptep;
1252 unsigned hugeshift;
1253 int rc, user_region = 0;
1254 int psize, ssize;
1255
1256 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1257 ea, access, trap);
1258 trace_hash_fault(ea, access, trap);
1259
1260 /* Get region & vsid */
1261 switch (REGION_ID(ea)) {
1262 case USER_REGION_ID:
1263 user_region = 1;
1264 if (! mm) {
1265 DBG_LOW(" user region with no mm !\n");
1266 rc = 1;
1267 goto bail;
1268 }
1269 psize = get_slice_psize(mm, ea);
1270 ssize = user_segment_size(ea);
1271 vsid = get_user_vsid(&mm->context, ea, ssize);
1272 break;
1273 case VMALLOC_REGION_ID:
1274 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1275 if (ea < VMALLOC_END)
1276 psize = mmu_vmalloc_psize;
1277 else
1278 psize = mmu_io_psize;
1279 ssize = mmu_kernel_ssize;
1280 break;
1281 default:
1282 /* Not a valid range
1283 * Send the problem up to do_page_fault
1284 */
1285 rc = 1;
1286 goto bail;
1287 }
1288 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1289
1290 /* Bad address. */
1291 if (!vsid) {
1292 DBG_LOW("Bad address!\n");
1293 rc = 1;
1294 goto bail;
1295 }
1296 /* Get pgdir */
1297 pgdir = mm->pgd;
1298 if (pgdir == NULL) {
1299 rc = 1;
1300 goto bail;
1301 }
1302
1303 /* Check CPU locality */
1304 if (user_region && mm_is_thread_local(mm))
1305 flags |= HPTE_LOCAL_UPDATE;
1306
1307#ifndef CONFIG_PPC_64K_PAGES
1308 /* If we use 4K pages and our psize is not 4K, then we might
1309 * be hitting a special driver mapping, and need to align the
1310 * address before we fetch the PTE.
1311 *
1312 * It could also be a hugepage mapping, in which case this is
1313 * not necessary, but it's not harmful, either.
1314 */
1315 if (psize != MMU_PAGE_4K)
1316 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1317#endif /* CONFIG_PPC_64K_PAGES */
1318
1319 /* Get PTE and page size from page tables */
1320 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1321 if (ptep == NULL || !pte_present(*ptep)) {
1322 DBG_LOW(" no PTE !\n");
1323 rc = 1;
1324 goto bail;
1325 }
1326
1327 /* Add _PAGE_PRESENT to the required access perm */
1328 access |= _PAGE_PRESENT;
1329
1330 /* Pre-check access permissions (will be re-checked atomically
1331 * in __hash_page_XX but this pre-check is a fast path
1332 */
1333 if (!check_pte_access(access, pte_val(*ptep))) {
1334 DBG_LOW(" no access !\n");
1335 rc = 1;
1336 goto bail;
1337 }
1338
1339 if (hugeshift) {
1340 if (is_thp)
1341 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1342 trap, flags, ssize, psize);
1343#ifdef CONFIG_HUGETLB_PAGE
1344 else
1345 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1346 flags, ssize, hugeshift, psize);
1347#else
1348 else {
1349 /*
1350 * if we have hugeshift, and is not transhuge with
1351 * hugetlb disabled, something is really wrong.
1352 */
1353 rc = 1;
1354 WARN_ON(1);
1355 }
1356#endif
1357 if (current->mm == mm)
1358 check_paca_psize(ea, mm, psize, user_region);
1359
1360 goto bail;
1361 }
1362
1363#ifndef CONFIG_PPC_64K_PAGES
1364 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1365#else
1366 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1367 pte_val(*(ptep + PTRS_PER_PTE)));
1368#endif
1369 /* Do actual hashing */
1370#ifdef CONFIG_PPC_64K_PAGES
1371 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1372 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1373 demote_segment_4k(mm, ea);
1374 psize = MMU_PAGE_4K;
1375 }
1376
1377 /* If this PTE is non-cacheable and we have restrictions on
1378 * using non cacheable large pages, then we switch to 4k
1379 */
1380 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1381 if (user_region) {
1382 demote_segment_4k(mm, ea);
1383 psize = MMU_PAGE_4K;
1384 } else if (ea < VMALLOC_END) {
1385 /*
1386 * some driver did a non-cacheable mapping
1387 * in vmalloc space, so switch vmalloc
1388 * to 4k pages
1389 */
1390 printk(KERN_ALERT "Reducing vmalloc segment "
1391 "to 4kB pages because of "
1392 "non-cacheable mapping\n");
1393 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1394 copro_flush_all_slbs(mm);
1395 }
1396 }
1397
1398#endif /* CONFIG_PPC_64K_PAGES */
1399
1400 if (current->mm == mm)
1401 check_paca_psize(ea, mm, psize, user_region);
1402
1403#ifdef CONFIG_PPC_64K_PAGES
1404 if (psize == MMU_PAGE_64K)
1405 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1406 flags, ssize);
1407 else
1408#endif /* CONFIG_PPC_64K_PAGES */
1409 {
1410 int spp = subpage_protection(mm, ea);
1411 if (access & spp)
1412 rc = -2;
1413 else
1414 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1415 flags, ssize, spp);
1416 }
1417
1418 /* Dump some info in case of hash insertion failure, they should
1419 * never happen so it is really useful to know if/when they do
1420 */
1421 if (rc == -1)
1422 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1423 psize, pte_val(*ptep));
1424#ifndef CONFIG_PPC_64K_PAGES
1425 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1426#else
1427 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1428 pte_val(*(ptep + PTRS_PER_PTE)));
1429#endif
1430 DBG_LOW(" -> rc=%d\n", rc);
1431
1432bail:
1433 exception_exit(prev_state);
1434 return rc;
1435}
1436EXPORT_SYMBOL_GPL(hash_page_mm);
1437
1438int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1439 unsigned long dsisr)
1440{
1441 unsigned long flags = 0;
1442 struct mm_struct *mm = current->mm;
1443
1444 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1445 mm = &init_mm;
1446
1447 if (dsisr & DSISR_NOHPTE)
1448 flags |= HPTE_NOHPTE_UPDATE;
1449
1450 return hash_page_mm(mm, ea, access, trap, flags);
1451}
1452EXPORT_SYMBOL_GPL(hash_page);
1453
1454int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1455 unsigned long dsisr)
1456{
1457 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1458 unsigned long flags = 0;
1459 struct mm_struct *mm = current->mm;
1460
1461 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1462 mm = &init_mm;
1463
1464 if (dsisr & DSISR_NOHPTE)
1465 flags |= HPTE_NOHPTE_UPDATE;
1466
1467 if (dsisr & DSISR_ISSTORE)
1468 access |= _PAGE_WRITE;
1469 /*
1470 * We set _PAGE_PRIVILEGED only when
1471 * kernel mode access kernel space.
1472 *
1473 * _PAGE_PRIVILEGED is NOT set
1474 * 1) when kernel mode access user space
1475 * 2) user space access kernel space.
1476 */
1477 access |= _PAGE_PRIVILEGED;
1478 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1479 access &= ~_PAGE_PRIVILEGED;
1480
1481 if (trap == 0x400)
1482 access |= _PAGE_EXEC;
1483
1484 return hash_page_mm(mm, ea, access, trap, flags);
1485}
1486
1487#ifdef CONFIG_PPC_MM_SLICES
1488static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1489{
1490 int psize = get_slice_psize(mm, ea);
1491
1492 /* We only prefault standard pages for now */
1493 if (unlikely(psize != mm->context.user_psize))
1494 return false;
1495
1496 /*
1497 * Don't prefault if subpage protection is enabled for the EA.
1498 */
1499 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1500 return false;
1501
1502 return true;
1503}
1504#else
1505static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1506{
1507 return true;
1508}
1509#endif
1510
1511void hash_preload(struct mm_struct *mm, unsigned long ea,
1512 unsigned long access, unsigned long trap)
1513{
1514 int hugepage_shift;
1515 unsigned long vsid;
1516 pgd_t *pgdir;
1517 pte_t *ptep;
1518 unsigned long flags;
1519 int rc, ssize, update_flags = 0;
1520
1521 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1522
1523 if (!should_hash_preload(mm, ea))
1524 return;
1525
1526 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1527 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1528
1529 /* Get Linux PTE if available */
1530 pgdir = mm->pgd;
1531 if (pgdir == NULL)
1532 return;
1533
1534 /* Get VSID */
1535 ssize = user_segment_size(ea);
1536 vsid = get_user_vsid(&mm->context, ea, ssize);
1537 if (!vsid)
1538 return;
1539 /*
1540 * Hash doesn't like irqs. Walking linux page table with irq disabled
1541 * saves us from holding multiple locks.
1542 */
1543 local_irq_save(flags);
1544
1545 /*
1546 * THP pages use update_mmu_cache_pmd. We don't do
1547 * hash preload there. Hence can ignore THP here
1548 */
1549 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1550 if (!ptep)
1551 goto out_exit;
1552
1553 WARN_ON(hugepage_shift);
1554#ifdef CONFIG_PPC_64K_PAGES
1555 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1556 * a 64K kernel), then we don't preload, hash_page() will take
1557 * care of it once we actually try to access the page.
1558 * That way we don't have to duplicate all of the logic for segment
1559 * page size demotion here
1560 */
1561 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1562 goto out_exit;
1563#endif /* CONFIG_PPC_64K_PAGES */
1564
1565 /* Is that local to this CPU ? */
1566 if (mm_is_thread_local(mm))
1567 update_flags |= HPTE_LOCAL_UPDATE;
1568
1569 /* Hash it in */
1570#ifdef CONFIG_PPC_64K_PAGES
1571 if (mm->context.user_psize == MMU_PAGE_64K)
1572 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1573 update_flags, ssize);
1574 else
1575#endif /* CONFIG_PPC_64K_PAGES */
1576 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1577 ssize, subpage_protection(mm, ea));
1578
1579 /* Dump some info in case of hash insertion failure, they should
1580 * never happen so it is really useful to know if/when they do
1581 */
1582 if (rc == -1)
1583 hash_failure_debug(ea, access, vsid, trap, ssize,
1584 mm->context.user_psize,
1585 mm->context.user_psize,
1586 pte_val(*ptep));
1587out_exit:
1588 local_irq_restore(flags);
1589}
1590
1591#ifdef CONFIG_PPC_MEM_KEYS
1592/*
1593 * Return the protection key associated with the given address and the
1594 * mm_struct.
1595 */
1596u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1597{
1598 pte_t *ptep;
1599 u16 pkey = 0;
1600 unsigned long flags;
1601
1602 if (!mm || !mm->pgd)
1603 return 0;
1604
1605 local_irq_save(flags);
1606 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1607 if (ptep)
1608 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1609 local_irq_restore(flags);
1610
1611 return pkey;
1612}
1613#endif /* CONFIG_PPC_MEM_KEYS */
1614
1615#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1616static inline void tm_flush_hash_page(int local)
1617{
1618 /*
1619 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1620 * page back to a block device w/PIO could pick up transactional data
1621 * (bad!) so we force an abort here. Before the sync the page will be
1622 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1623 * kernel uses a page from userspace without unmapping it first, it may
1624 * see the speculated version.
1625 */
1626 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1627 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1628 tm_enable();
1629 tm_abort(TM_CAUSE_TLBI);
1630 }
1631}
1632#else
1633static inline void tm_flush_hash_page(int local)
1634{
1635}
1636#endif
1637
1638/*
1639 * Return the global hash slot, corresponding to the given PTE, which contains
1640 * the HPTE.
1641 */
1642unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1643 int ssize, real_pte_t rpte, unsigned int subpg_index)
1644{
1645 unsigned long hash, gslot, hidx;
1646
1647 hash = hpt_hash(vpn, shift, ssize);
1648 hidx = __rpte_to_hidx(rpte, subpg_index);
1649 if (hidx & _PTEIDX_SECONDARY)
1650 hash = ~hash;
1651 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1652 gslot += hidx & _PTEIDX_GROUP_IX;
1653 return gslot;
1654}
1655
1656/* WARNING: This is called from hash_low_64.S, if you change this prototype,
1657 * do not forget to update the assembly call site !
1658 */
1659void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1660 unsigned long flags)
1661{
1662 unsigned long index, shift, gslot;
1663 int local = flags & HPTE_LOCAL_UPDATE;
1664
1665 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1666 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1667 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1668 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1669 /*
1670 * We use same base page size and actual psize, because we don't
1671 * use these functions for hugepage
1672 */
1673 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1674 ssize, local);
1675 } pte_iterate_hashed_end();
1676
1677 tm_flush_hash_page(local);
1678}
1679
1680#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1681void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1682 pmd_t *pmdp, unsigned int psize, int ssize,
1683 unsigned long flags)
1684{
1685 int i, max_hpte_count, valid;
1686 unsigned long s_addr;
1687 unsigned char *hpte_slot_array;
1688 unsigned long hidx, shift, vpn, hash, slot;
1689 int local = flags & HPTE_LOCAL_UPDATE;
1690
1691 s_addr = addr & HPAGE_PMD_MASK;
1692 hpte_slot_array = get_hpte_slot_array(pmdp);
1693 /*
1694 * IF we try to do a HUGE PTE update after a withdraw is done.
1695 * we will find the below NULL. This happens when we do
1696 * split_huge_page_pmd
1697 */
1698 if (!hpte_slot_array)
1699 return;
1700
1701 if (mmu_hash_ops.hugepage_invalidate) {
1702 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1703 psize, ssize, local);
1704 goto tm_abort;
1705 }
1706 /*
1707 * No bluk hpte removal support, invalidate each entry
1708 */
1709 shift = mmu_psize_defs[psize].shift;
1710 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1711 for (i = 0; i < max_hpte_count; i++) {
1712 /*
1713 * 8 bits per each hpte entries
1714 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1715 */
1716 valid = hpte_valid(hpte_slot_array, i);
1717 if (!valid)
1718 continue;
1719 hidx = hpte_hash_index(hpte_slot_array, i);
1720
1721 /* get the vpn */
1722 addr = s_addr + (i * (1ul << shift));
1723 vpn = hpt_vpn(addr, vsid, ssize);
1724 hash = hpt_hash(vpn, shift, ssize);
1725 if (hidx & _PTEIDX_SECONDARY)
1726 hash = ~hash;
1727
1728 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1729 slot += hidx & _PTEIDX_GROUP_IX;
1730 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1731 MMU_PAGE_16M, ssize, local);
1732 }
1733tm_abort:
1734 tm_flush_hash_page(local);
1735}
1736#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1737
1738void flush_hash_range(unsigned long number, int local)
1739{
1740 if (mmu_hash_ops.flush_hash_range)
1741 mmu_hash_ops.flush_hash_range(number, local);
1742 else {
1743 int i;
1744 struct ppc64_tlb_batch *batch =
1745 this_cpu_ptr(&ppc64_tlb_batch);
1746
1747 for (i = 0; i < number; i++)
1748 flush_hash_page(batch->vpn[i], batch->pte[i],
1749 batch->psize, batch->ssize, local);
1750 }
1751}
1752
1753/*
1754 * low_hash_fault is called when we the low level hash code failed
1755 * to instert a PTE due to an hypervisor error
1756 */
1757void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1758{
1759 enum ctx_state prev_state = exception_enter();
1760
1761 if (user_mode(regs)) {
1762#ifdef CONFIG_PPC_SUBPAGE_PROT
1763 if (rc == -2)
1764 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1765 else
1766#endif
1767 _exception(SIGBUS, regs, BUS_ADRERR, address);
1768 } else
1769 bad_page_fault(regs, address, SIGBUS);
1770
1771 exception_exit(prev_state);
1772}
1773
1774long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1775 unsigned long pa, unsigned long rflags,
1776 unsigned long vflags, int psize, int ssize)
1777{
1778 unsigned long hpte_group;
1779 long slot;
1780
1781repeat:
1782 hpte_group = ((hash & htab_hash_mask) *
1783 HPTES_PER_GROUP) & ~0x7UL;
1784
1785 /* Insert into the hash table, primary slot */
1786 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1787 psize, psize, ssize);
1788
1789 /* Primary is full, try the secondary */
1790 if (unlikely(slot == -1)) {
1791 hpte_group = ((~hash & htab_hash_mask) *
1792 HPTES_PER_GROUP) & ~0x7UL;
1793 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1794 vflags | HPTE_V_SECONDARY,
1795 psize, psize, ssize);
1796 if (slot == -1) {
1797 if (mftb() & 0x1)
1798 hpte_group = ((hash & htab_hash_mask) *
1799 HPTES_PER_GROUP)&~0x7UL;
1800
1801 mmu_hash_ops.hpte_remove(hpte_group);
1802 goto repeat;
1803 }
1804 }
1805
1806 return slot;
1807}
1808
1809#ifdef CONFIG_DEBUG_PAGEALLOC
1810static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1811{
1812 unsigned long hash;
1813 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1814 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1815 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1816 long ret;
1817
1818 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1819
1820 /* Don't create HPTE entries for bad address */
1821 if (!vsid)
1822 return;
1823
1824 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1825 HPTE_V_BOLTED,
1826 mmu_linear_psize, mmu_kernel_ssize);
1827
1828 BUG_ON (ret < 0);
1829 spin_lock(&linear_map_hash_lock);
1830 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1831 linear_map_hash_slots[lmi] = ret | 0x80;
1832 spin_unlock(&linear_map_hash_lock);
1833}
1834
1835static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1836{
1837 unsigned long hash, hidx, slot;
1838 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1839 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1840
1841 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1842 spin_lock(&linear_map_hash_lock);
1843 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1844 hidx = linear_map_hash_slots[lmi] & 0x7f;
1845 linear_map_hash_slots[lmi] = 0;
1846 spin_unlock(&linear_map_hash_lock);
1847 if (hidx & _PTEIDX_SECONDARY)
1848 hash = ~hash;
1849 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1850 slot += hidx & _PTEIDX_GROUP_IX;
1851 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1852 mmu_linear_psize,
1853 mmu_kernel_ssize, 0);
1854}
1855
1856void __kernel_map_pages(struct page *page, int numpages, int enable)
1857{
1858 unsigned long flags, vaddr, lmi;
1859 int i;
1860
1861 local_irq_save(flags);
1862 for (i = 0; i < numpages; i++, page++) {
1863 vaddr = (unsigned long)page_address(page);
1864 lmi = __pa(vaddr) >> PAGE_SHIFT;
1865 if (lmi >= linear_map_hash_count)
1866 continue;
1867 if (enable)
1868 kernel_map_linear_page(vaddr, lmi);
1869 else
1870 kernel_unmap_linear_page(vaddr, lmi);
1871 }
1872 local_irq_restore(flags);
1873}
1874#endif /* CONFIG_DEBUG_PAGEALLOC */
1875
1876void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1877 phys_addr_t first_memblock_size)
1878{
1879 /* We don't currently support the first MEMBLOCK not mapping 0
1880 * physical on those processors
1881 */
1882 BUG_ON(first_memblock_base != 0);
1883
1884 /*
1885 * On virtualized systems the first entry is our RMA region aka VRMA,
1886 * non-virtualized 64-bit hash MMU systems don't have a limitation
1887 * on real mode access.
1888 *
1889 * For guests on platforms before POWER9, we clamp the it limit to 1G
1890 * to avoid some funky things such as RTAS bugs etc...
1891 */
1892 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1893 ppc64_rma_size = first_memblock_size;
1894 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1895 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1896
1897 /* Finally limit subsequent allocations */
1898 memblock_set_current_limit(ppc64_rma_size);
1899 } else {
1900 ppc64_rma_size = ULONG_MAX;
1901 }
1902}
1903
1904#ifdef CONFIG_DEBUG_FS
1905
1906static int hpt_order_get(void *data, u64 *val)
1907{
1908 *val = ppc64_pft_size;
1909 return 0;
1910}
1911
1912static int hpt_order_set(void *data, u64 val)
1913{
1914 if (!mmu_hash_ops.resize_hpt)
1915 return -ENODEV;
1916
1917 return mmu_hash_ops.resize_hpt(val);
1918}
1919
1920DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1921
1922static int __init hash64_debugfs(void)
1923{
1924 if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root,
1925 NULL, &fops_hpt_order)) {
1926 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1927 }
1928
1929 return 0;
1930}
1931machine_device_initcall(pseries, hash64_debugfs);
1932#endif /* CONFIG_DEBUG_FS */