1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
   4 * with Common Isochronous Packet (IEC 61883-1) headers
   5 *
   6 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
 
   7 */
   8
   9#include <linux/device.h>
  10#include <linux/err.h>
  11#include <linux/firewire.h>
  12#include <linux/firewire-constants.h>
  13#include <linux/module.h>
  14#include <linux/slab.h>
  15#include <sound/pcm.h>
  16#include <sound/pcm_params.h>
  17#include "amdtp-stream.h"
  18
  19#define TICKS_PER_CYCLE		3072
  20#define CYCLES_PER_SECOND	8000
  21#define TICKS_PER_SECOND	(TICKS_PER_CYCLE * CYCLES_PER_SECOND)
  22
  23#define OHCI_SECOND_MODULUS		8
  24
  25/* Always support Linux tracing subsystem. */
  26#define CREATE_TRACE_POINTS
  27#include "amdtp-stream-trace.h"
  28
  29#define TRANSFER_DELAY_TICKS	0x2e00 /* 479.17 microseconds */
  30
  31/* isochronous header parameters */
  32#define ISO_DATA_LENGTH_SHIFT	16
  33#define TAG_NO_CIP_HEADER	0
  34#define TAG_CIP			1
  35
  36// Common Isochronous Packet (CIP) header parameters. Use two quadlets CIP header when supported.
  37#define CIP_HEADER_QUADLETS	2
  38#define CIP_EOH_SHIFT		31
  39#define CIP_EOH			(1u << CIP_EOH_SHIFT)
  40#define CIP_EOH_MASK		0x80000000
  41#define CIP_SID_SHIFT		24
  42#define CIP_SID_MASK		0x3f000000
  43#define CIP_DBS_MASK		0x00ff0000
  44#define CIP_DBS_SHIFT		16
  45#define CIP_SPH_MASK		0x00000400
  46#define CIP_SPH_SHIFT		10
  47#define CIP_DBC_MASK		0x000000ff
  48#define CIP_FMT_SHIFT		24
  49#define CIP_FMT_MASK		0x3f000000
  50#define CIP_FDF_MASK		0x00ff0000
  51#define CIP_FDF_SHIFT		16
  52#define CIP_FDF_NO_DATA		0xff
  53#define CIP_SYT_MASK		0x0000ffff
  54#define CIP_SYT_NO_INFO		0xffff
  55#define CIP_SYT_CYCLE_MODULUS	16
  56#define CIP_NO_DATA		((CIP_FDF_NO_DATA << CIP_FDF_SHIFT) | CIP_SYT_NO_INFO)
  57
  58#define CIP_HEADER_SIZE		(sizeof(__be32) * CIP_HEADER_QUADLETS)
  59
  60/* Audio and Music transfer protocol specific parameters */
  61#define CIP_FMT_AM		0x10
  62#define AMDTP_FDF_NO_DATA	0xff
  63
  64// For iso header and tstamp.
  65#define IR_CTX_HEADER_DEFAULT_QUADLETS	2
  66// Add nothing.
  67#define IR_CTX_HEADER_SIZE_NO_CIP	(sizeof(__be32) * IR_CTX_HEADER_DEFAULT_QUADLETS)
  68// Add two quadlets CIP header.
  69#define IR_CTX_HEADER_SIZE_CIP		(IR_CTX_HEADER_SIZE_NO_CIP + CIP_HEADER_SIZE)
  70#define HEADER_TSTAMP_MASK	0x0000ffff
  71
  72#define IT_PKT_HEADER_SIZE_CIP		CIP_HEADER_SIZE
  73#define IT_PKT_HEADER_SIZE_NO_CIP	0 // Nothing.
  74
  75// The initial firmware of OXFW970 can postpone transmission of packet during finishing
  76// asynchronous transaction. This module accepts 5 cycles to skip as maximum to avoid buffer
  77// overrun. Actual device can skip more, then this module stops the packet streaming.
  78#define IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES	5
  79
  80/**
  81 * amdtp_stream_init - initialize an AMDTP stream structure
  82 * @s: the AMDTP stream to initialize
  83 * @unit: the target of the stream
  84 * @dir: the direction of stream
  85 * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants.
  86 * @fmt: the value of fmt field in CIP header
  87 * @process_ctx_payloads: callback handler to process payloads of isoc context
  88 * @protocol_size: the size to allocate newly for protocol
  89 */
  90int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
  91		      enum amdtp_stream_direction dir, unsigned int flags,
  92		      unsigned int fmt,
  93		      amdtp_stream_process_ctx_payloads_t process_ctx_payloads,
  94		      unsigned int protocol_size)
  95{
  96	if (process_ctx_payloads == NULL)
  97		return -EINVAL;
  98
  99	s->protocol = kzalloc(protocol_size, GFP_KERNEL);
 100	if (!s->protocol)
 101		return -ENOMEM;
 102
 103	s->unit = unit;
 104	s->direction = dir;
 105	s->flags = flags;
 106	s->context = ERR_PTR(-1);
 107	mutex_init(&s->mutex);
 
 108	s->packet_index = 0;
 109
 110	init_waitqueue_head(&s->ready_wait);
 
 111
 112	s->fmt = fmt;
 113	s->process_ctx_payloads = process_ctx_payloads;
 114
 115	return 0;
 116}
 117EXPORT_SYMBOL(amdtp_stream_init);
 118
 119/**
 120 * amdtp_stream_destroy - free stream resources
 121 * @s: the AMDTP stream to destroy
 122 */
 123void amdtp_stream_destroy(struct amdtp_stream *s)
 124{
 125	/* Not initialized. */
 126	if (s->protocol == NULL)
 127		return;
 128
 129	WARN_ON(amdtp_stream_running(s));
 130	kfree(s->protocol);
 131	mutex_destroy(&s->mutex);
 132}
 133EXPORT_SYMBOL(amdtp_stream_destroy);
 134
 135const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
 136	[CIP_SFC_32000]  =  8,
 137	[CIP_SFC_44100]  =  8,
 138	[CIP_SFC_48000]  =  8,
 139	[CIP_SFC_88200]  = 16,
 140	[CIP_SFC_96000]  = 16,
 141	[CIP_SFC_176400] = 32,
 142	[CIP_SFC_192000] = 32,
 143};
 144EXPORT_SYMBOL(amdtp_syt_intervals);
 145
 146const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = {
 147	[CIP_SFC_32000]  =  32000,
 148	[CIP_SFC_44100]  =  44100,
 149	[CIP_SFC_48000]  =  48000,
 150	[CIP_SFC_88200]  =  88200,
 151	[CIP_SFC_96000]  =  96000,
 152	[CIP_SFC_176400] = 176400,
 153	[CIP_SFC_192000] = 192000,
 154};
 155EXPORT_SYMBOL(amdtp_rate_table);
 156
 157static int apply_constraint_to_size(struct snd_pcm_hw_params *params,
 158				    struct snd_pcm_hw_rule *rule)
 159{
 160	struct snd_interval *s = hw_param_interval(params, rule->var);
 161	const struct snd_interval *r =
 162		hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
 163	struct snd_interval t = {0};
 164	unsigned int step = 0;
 165	int i;
 166
 167	for (i = 0; i < CIP_SFC_COUNT; ++i) {
 168		if (snd_interval_test(r, amdtp_rate_table[i]))
 169			step = max(step, amdtp_syt_intervals[i]);
 170	}
 171
 172	t.min = roundup(s->min, step);
 173	t.max = rounddown(s->max, step);
 174	t.integer = 1;
 175
 176	return snd_interval_refine(s, &t);
 177}
 178
 179/**
 180 * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream
 181 * @s:		the AMDTP stream, which must be initialized.
 182 * @runtime:	the PCM substream runtime
 183 */
 184int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s,
 185					struct snd_pcm_runtime *runtime)
 186{
 187	struct snd_pcm_hardware *hw = &runtime->hw;
 188	unsigned int ctx_header_size;
 189	unsigned int maximum_usec_per_period;
 190	int err;
 191
 192	hw->info = SNDRV_PCM_INFO_BLOCK_TRANSFER |
 193		   SNDRV_PCM_INFO_INTERLEAVED |
 194		   SNDRV_PCM_INFO_JOINT_DUPLEX |
 195		   SNDRV_PCM_INFO_MMAP |
 196		   SNDRV_PCM_INFO_MMAP_VALID |
 197		   SNDRV_PCM_INFO_NO_PERIOD_WAKEUP;
 198
 199	hw->periods_min = 2;
 200	hw->periods_max = UINT_MAX;
 201
 202	/* bytes for a frame */
 203	hw->period_bytes_min = 4 * hw->channels_max;
 204
 205	/* Just to prevent from allocating much pages. */
 206	hw->period_bytes_max = hw->period_bytes_min * 2048;
 207	hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min;
 208
 209	// Linux driver for 1394 OHCI controller voluntarily flushes isoc
 210	// context when total size of accumulated context header reaches
 211	// PAGE_SIZE. This kicks work for the isoc context and brings
 212	// callback in the middle of scheduled interrupts.
 213	// Although AMDTP streams in the same domain use the same events per
 214	// IRQ, use the largest size of context header between IT/IR contexts.
 215	// Here, use the value of context header in IR context is for both
 216	// contexts.
 217	if (!(s->flags & CIP_NO_HEADER))
 218		ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
 219	else
 220		ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
 221	maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE /
 222				  CYCLES_PER_SECOND / ctx_header_size;
 223
 224	// In IEC 61883-6, one isoc packet can transfer events up to the value
 225	// of syt interval. This comes from the interval of isoc cycle. As 1394
 226	// OHCI controller can generate hardware IRQ per isoc packet, the
 227	// interval is 125 usec.
 228	// However, there are two ways of transmission in IEC 61883-6; blocking
 229	// and non-blocking modes. In blocking mode, the sequence of isoc packet
 230	// includes 'empty' or 'NODATA' packets which include no event. In
 231	// non-blocking mode, the number of events per packet is variable up to
 232	// the syt interval.
 233	// Due to the above protocol design, the minimum PCM frames per
 234	// interrupt should be double of the value of syt interval, thus it is
 235	// 250 usec.
 236	err = snd_pcm_hw_constraint_minmax(runtime,
 237					   SNDRV_PCM_HW_PARAM_PERIOD_TIME,
 238					   250, maximum_usec_per_period);
 239	if (err < 0)
 240		goto end;
 241
 242	/* Non-Blocking stream has no more constraints */
 243	if (!(s->flags & CIP_BLOCKING))
 244		goto end;
 245
 246	/*
 247	 * One AMDTP packet can include some frames. In blocking mode, the
 248	 * number equals to SYT_INTERVAL. So the number is 8, 16 or 32,
 249	 * depending on its sampling rate. For accurate period interrupt, it's
 250	 * preferrable to align period/buffer sizes to current SYT_INTERVAL.
 
 
 
 251	 */
 252	err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 253				  apply_constraint_to_size, NULL,
 254				  SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 255				  SNDRV_PCM_HW_PARAM_RATE, -1);
 256	if (err < 0)
 257		goto end;
 258	err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 259				  apply_constraint_to_size, NULL,
 260				  SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 261				  SNDRV_PCM_HW_PARAM_RATE, -1);
 262	if (err < 0)
 263		goto end;
 
 
 264end:
 265	return err;
 266}
 267EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints);
 268
 269/**
 270 * amdtp_stream_set_parameters - set stream parameters
 271 * @s: the AMDTP stream to configure
 272 * @rate: the sample rate
 273 * @data_block_quadlets: the size of a data block in quadlet unit
 274 * @pcm_frame_multiplier: the multiplier to compute the number of PCM frames by the number of AMDTP
 275 *			  events.
 276 *
 277 * The parameters must be set before the stream is started, and must not be
 278 * changed while the stream is running.
 279 */
 280int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate,
 281				unsigned int data_block_quadlets, unsigned int pcm_frame_multiplier)
 282{
 283	unsigned int sfc;
 284
 285	for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
 286		if (amdtp_rate_table[sfc] == rate)
 287			break;
 288	}
 289	if (sfc == ARRAY_SIZE(amdtp_rate_table))
 290		return -EINVAL;
 291
 292	s->sfc = sfc;
 293	s->data_block_quadlets = data_block_quadlets;
 294	s->syt_interval = amdtp_syt_intervals[sfc];
 295
 296	// default buffering in the device.
 297	s->transfer_delay = TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
 298
 299	// additional buffering needed to adjust for no-data packets.
 300	if (s->flags & CIP_BLOCKING)
 
 301		s->transfer_delay += TICKS_PER_SECOND * s->syt_interval / rate;
 302
 303	s->pcm_frame_multiplier = pcm_frame_multiplier;
 304
 305	return 0;
 306}
 307EXPORT_SYMBOL(amdtp_stream_set_parameters);
 308
 309// The CIP header is processed in context header apart from context payload.
 310static int amdtp_stream_get_max_ctx_payload_size(struct amdtp_stream *s)
 311{
 312	unsigned int multiplier;
 313
 314	if (s->flags & CIP_JUMBO_PAYLOAD)
 315		multiplier = IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES;
 316	else
 317		multiplier = 1;
 318
 319	return s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier;
 320}
 321
 322/**
 323 * amdtp_stream_get_max_payload - get the stream's packet size
 324 * @s: the AMDTP stream
 325 *
 326 * This function must not be called before the stream has been configured
 327 * with amdtp_stream_set_parameters().
 328 */
 329unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s)
 330{
 331	unsigned int cip_header_size;
 332
 333	if (!(s->flags & CIP_NO_HEADER))
 334		cip_header_size = CIP_HEADER_SIZE;
 335	else
 336		cip_header_size = 0;
 337
 338	return cip_header_size + amdtp_stream_get_max_ctx_payload_size(s);
 339}
 340EXPORT_SYMBOL(amdtp_stream_get_max_payload);
 341
 342/**
 343 * amdtp_stream_pcm_prepare - prepare PCM device for running
 344 * @s: the AMDTP stream
 345 *
 346 * This function should be called from the PCM device's .prepare callback.
 347 */
 348void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
 349{
 
 350	s->pcm_buffer_pointer = 0;
 351	s->pcm_period_pointer = 0;
 352}
 353EXPORT_SYMBOL(amdtp_stream_pcm_prepare);
 354
 355#define prev_packet_desc(s, desc) \
 356	list_prev_entry_circular(desc, &s->packet_descs_list, link)
 357
 358static void pool_blocking_data_blocks(struct amdtp_stream *s, struct seq_desc *descs,
 359				      unsigned int size, unsigned int pos, unsigned int count)
 360{
 361	const unsigned int syt_interval = s->syt_interval;
 362	int i;
 363
 364	for (i = 0; i < count; ++i) {
 365		struct seq_desc *desc = descs + pos;
 366
 367		if (desc->syt_offset != CIP_SYT_NO_INFO)
 368			desc->data_blocks = syt_interval;
 
 
 
 369		else
 370			desc->data_blocks = 0;
 371
 372		pos = (pos + 1) % size;
 373	}
 374}
 375
 376static void pool_ideal_nonblocking_data_blocks(struct amdtp_stream *s, struct seq_desc *descs,
 377					       unsigned int size, unsigned int pos,
 378					       unsigned int count)
 379{
 380	const enum cip_sfc sfc = s->sfc;
 381	unsigned int state = s->ctx_data.rx.data_block_state;
 382	int i;
 383
 384	for (i = 0; i < count; ++i) {
 385		struct seq_desc *desc = descs + pos;
 386
 387		if (!cip_sfc_is_base_44100(sfc)) {
 388			// Sample_rate / 8000 is an integer, and precomputed.
 389			desc->data_blocks = state;
 390		} else {
 391			unsigned int phase = state;
 392
 393		/*
 394		 * This calculates the number of data blocks per packet so that
 395		 * 1) the overall rate is correct and exactly synchronized to
 396		 *    the bus clock, and
 397		 * 2) packets with a rounded-up number of blocks occur as early
 398		 *    as possible in the sequence (to prevent underruns of the
 399		 *    device's buffer).
 400		 */
 401			if (sfc == CIP_SFC_44100)
 402				/* 6 6 5 6 5 6 5 ... */
 403				desc->data_blocks = 5 + ((phase & 1) ^ (phase == 0 || phase >= 40));
 
 404			else
 405				/* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
 406				desc->data_blocks = 11 * (sfc >> 1) + (phase == 0);
 407			if (++phase >= (80 >> (sfc >> 1)))
 408				phase = 0;
 409			state = phase;
 410		}
 411
 412		pos = (pos + 1) % size;
 413	}
 414
 415	s->ctx_data.rx.data_block_state = state;
 416}
 417
 418static unsigned int calculate_syt_offset(unsigned int *last_syt_offset,
 419			unsigned int *syt_offset_state, enum cip_sfc sfc)
 420{
 421	unsigned int syt_offset;
 422
 423	if (*last_syt_offset < TICKS_PER_CYCLE) {
 424		if (!cip_sfc_is_base_44100(sfc))
 425			syt_offset = *last_syt_offset + *syt_offset_state;
 426		else {
 427		/*
 428		 * The time, in ticks, of the n'th SYT_INTERVAL sample is:
 429		 *   n * SYT_INTERVAL * 24576000 / sample_rate
 430		 * Modulo TICKS_PER_CYCLE, the difference between successive
 431		 * elements is about 1386.23.  Rounding the results of this
 432		 * formula to the SYT precision results in a sequence of
 433		 * differences that begins with:
 434		 *   1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
 435		 * This code generates _exactly_ the same sequence.
 436		 */
 437			unsigned int phase = *syt_offset_state;
 438			unsigned int index = phase % 13;
 439
 440			syt_offset = *last_syt_offset;
 441			syt_offset += 1386 + ((index && !(index & 3)) ||
 442					      phase == 146);
 443			if (++phase >= 147)
 444				phase = 0;
 445			*syt_offset_state = phase;
 446		}
 447	} else
 448		syt_offset = *last_syt_offset - TICKS_PER_CYCLE;
 449	*last_syt_offset = syt_offset;
 450
 451	if (syt_offset >= TICKS_PER_CYCLE)
 452		syt_offset = CIP_SYT_NO_INFO;
 453
 454	return syt_offset;
 455}
 456
 457static void pool_ideal_syt_offsets(struct amdtp_stream *s, struct seq_desc *descs,
 458				   unsigned int size, unsigned int pos, unsigned int count)
 459{
 460	const enum cip_sfc sfc = s->sfc;
 461	unsigned int last = s->ctx_data.rx.last_syt_offset;
 462	unsigned int state = s->ctx_data.rx.syt_offset_state;
 463	int i;
 464
 465	for (i = 0; i < count; ++i) {
 466		struct seq_desc *desc = descs + pos;
 467
 468		desc->syt_offset = calculate_syt_offset(&last, &state, sfc);
 469
 470		pos = (pos + 1) % size;
 471	}
 472
 473	s->ctx_data.rx.last_syt_offset = last;
 474	s->ctx_data.rx.syt_offset_state = state;
 475}
 476
 477static unsigned int compute_syt_offset(unsigned int syt, unsigned int cycle,
 478				       unsigned int transfer_delay)
 479{
 480	unsigned int cycle_lo = (cycle % CYCLES_PER_SECOND) & 0x0f;
 481	unsigned int syt_cycle_lo = (syt & 0xf000) >> 12;
 482	unsigned int syt_offset;
 483
 484	// Round up.
 485	if (syt_cycle_lo < cycle_lo)
 486		syt_cycle_lo += CIP_SYT_CYCLE_MODULUS;
 487	syt_cycle_lo -= cycle_lo;
 488
 489	// Subtract transfer delay so that the synchronization offset is not so large
 490	// at transmission.
 491	syt_offset = syt_cycle_lo * TICKS_PER_CYCLE + (syt & 0x0fff);
 492	if (syt_offset < transfer_delay)
 493		syt_offset += CIP_SYT_CYCLE_MODULUS * TICKS_PER_CYCLE;
 494
 495	return syt_offset - transfer_delay;
 496}
 497
 498// Both of the producer and consumer of the queue runs in the same clock of IEEE 1394 bus.
 499// Additionally, the sequence of tx packets is severely checked against any discontinuity
 500// before filling entries in the queue. The calculation is safe even if it looks fragile by
 501// overrun.
 502static unsigned int calculate_cached_cycle_count(struct amdtp_stream *s, unsigned int head)
 503{
 504	const unsigned int cache_size = s->ctx_data.tx.cache.size;
 505	unsigned int cycles = s->ctx_data.tx.cache.pos;
 506
 507	if (cycles < head)
 508		cycles += cache_size;
 509	cycles -= head;
 510
 511	return cycles;
 512}
 513
 514static void cache_seq(struct amdtp_stream *s, const struct pkt_desc *src, unsigned int desc_count)
 515{
 516	const unsigned int transfer_delay = s->transfer_delay;
 517	const unsigned int cache_size = s->ctx_data.tx.cache.size;
 518	struct seq_desc *cache = s->ctx_data.tx.cache.descs;
 519	unsigned int cache_pos = s->ctx_data.tx.cache.pos;
 520	bool aware_syt = !(s->flags & CIP_UNAWARE_SYT);
 521	int i;
 522
 523	for (i = 0; i < desc_count; ++i) {
 524		struct seq_desc *dst = cache + cache_pos;
 525
 526		if (aware_syt && src->syt != CIP_SYT_NO_INFO)
 527			dst->syt_offset = compute_syt_offset(src->syt, src->cycle, transfer_delay);
 528		else
 529			dst->syt_offset = CIP_SYT_NO_INFO;
 530		dst->data_blocks = src->data_blocks;
 531
 532		cache_pos = (cache_pos + 1) % cache_size;
 533		src = amdtp_stream_next_packet_desc(s, src);
 534	}
 535
 536	s->ctx_data.tx.cache.pos = cache_pos;
 537}
 538
 539static void pool_ideal_seq_descs(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size,
 540				 unsigned int pos, unsigned int count)
 541{
 542	pool_ideal_syt_offsets(s, descs, size, pos, count);
 543
 544	if (s->flags & CIP_BLOCKING)
 545		pool_blocking_data_blocks(s, descs, size, pos, count);
 546	else
 547		pool_ideal_nonblocking_data_blocks(s, descs, size, pos, count);
 548}
 549
 550static void pool_replayed_seq(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size,
 551			      unsigned int pos, unsigned int count)
 552{
 553	struct amdtp_stream *target = s->ctx_data.rx.replay_target;
 554	const struct seq_desc *cache = target->ctx_data.tx.cache.descs;
 555	const unsigned int cache_size = target->ctx_data.tx.cache.size;
 556	unsigned int cache_pos = s->ctx_data.rx.cache_pos;
 557	int i;
 558
 559	for (i = 0; i < count; ++i) {
 560		descs[pos] = cache[cache_pos];
 561		cache_pos = (cache_pos + 1) % cache_size;
 562		pos = (pos + 1) % size;
 563	}
 564
 565	s->ctx_data.rx.cache_pos = cache_pos;
 566}
 567
 568static void pool_seq_descs(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size,
 569			   unsigned int pos, unsigned int count)
 570{
 571	struct amdtp_domain *d = s->domain;
 572	void (*pool_seq_descs)(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size,
 573			       unsigned int pos, unsigned int count);
 574
 575	if (!d->replay.enable || !s->ctx_data.rx.replay_target) {
 576		pool_seq_descs = pool_ideal_seq_descs;
 577	} else {
 578		if (!d->replay.on_the_fly) {
 579			pool_seq_descs = pool_replayed_seq;
 580		} else {
 581			struct amdtp_stream *tx = s->ctx_data.rx.replay_target;
 582			const unsigned int cache_size = tx->ctx_data.tx.cache.size;
 583			const unsigned int cache_pos = s->ctx_data.rx.cache_pos;
 584			unsigned int cached_cycles = calculate_cached_cycle_count(tx, cache_pos);
 585
 586			if (cached_cycles > count && cached_cycles > cache_size / 2)
 587				pool_seq_descs = pool_replayed_seq;
 588			else
 589				pool_seq_descs = pool_ideal_seq_descs;
 590		}
 591	}
 592
 593	pool_seq_descs(s, descs, size, pos, count);
 594}
 595
 596static void update_pcm_pointers(struct amdtp_stream *s,
 597				struct snd_pcm_substream *pcm,
 598				unsigned int frames)
 599{
 600	unsigned int ptr;
 601
 602	ptr = s->pcm_buffer_pointer + frames;
 603	if (ptr >= pcm->runtime->buffer_size)
 604		ptr -= pcm->runtime->buffer_size;
 605	WRITE_ONCE(s->pcm_buffer_pointer, ptr);
 606
 607	s->pcm_period_pointer += frames;
 608	if (s->pcm_period_pointer >= pcm->runtime->period_size) {
 609		s->pcm_period_pointer -= pcm->runtime->period_size;
 610
 611		// The program in user process should periodically check the status of intermediate
 612		// buffer associated to PCM substream to process PCM frames in the buffer, instead
 613		// of receiving notification of period elapsed by poll wait.
 614		if (!pcm->runtime->no_period_wakeup) {
 615			if (in_softirq()) {
 616				// In software IRQ context for 1394 OHCI.
 617				snd_pcm_period_elapsed(pcm);
 618			} else {
 619				// In process context of ALSA PCM application under acquired lock of
 620				// PCM substream.
 621				snd_pcm_period_elapsed_under_stream_lock(pcm);
 622			}
 623		}
 624	}
 625}
 626
 627static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params,
 628			bool sched_irq)
 629{
 630	int err;
 
 
 
 
 
 
 
 
 
 
 
 631
 632	params->interrupt = sched_irq;
 633	params->tag = s->tag;
 634	params->sy = 0;
 635
 636	err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer,
 
 
 
 
 
 
 
 637				   s->buffer.packets[s->packet_index].offset);
 638	if (err < 0) {
 639		dev_err(&s->unit->device, "queueing error: %d\n", err);
 640		goto end;
 641	}
 642
 643	if (++s->packet_index >= s->queue_size)
 644		s->packet_index = 0;
 645end:
 646	return err;
 647}
 648
 649static inline int queue_out_packet(struct amdtp_stream *s,
 650				   struct fw_iso_packet *params, bool sched_irq)
 651{
 652	params->skip =
 653		!!(params->header_length == 0 && params->payload_length == 0);
 654	return queue_packet(s, params, sched_irq);
 655}
 656
 657static inline int queue_in_packet(struct amdtp_stream *s,
 658				  struct fw_iso_packet *params)
 659{
 660	// Queue one packet for IR context.
 661	params->header_length = s->ctx_data.tx.ctx_header_size;
 662	params->payload_length = s->ctx_data.tx.max_ctx_payload_length;
 663	params->skip = false;
 664	return queue_packet(s, params, false);
 665}
 666
 667static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2],
 668			unsigned int data_block_counter, unsigned int syt)
 669{
 670	cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
 
 
 
 
 
 
 
 
 
 
 
 
 671				(s->data_block_quadlets << CIP_DBS_SHIFT) |
 672				((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) |
 673				data_block_counter);
 674	cip_header[1] = cpu_to_be32(CIP_EOH |
 675			((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) |
 676			((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) |
 677			(syt & CIP_SYT_MASK));
 678}
 679
 680static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle,
 681				struct fw_iso_packet *params, unsigned int header_length,
 682				unsigned int data_blocks,
 683				unsigned int data_block_counter,
 684				unsigned int syt, unsigned int index, u32 curr_cycle_time)
 685{
 686	unsigned int payload_length;
 687	__be32 *cip_header;
 688
 689	payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets;
 690	params->payload_length = payload_length;
 691
 692	if (header_length > 0) {
 693		cip_header = (__be32 *)params->header;
 694		generate_cip_header(s, cip_header, data_block_counter, syt);
 695		params->header_length = header_length;
 696	} else {
 697		cip_header = NULL;
 698	}
 699
 700	trace_amdtp_packet(s, cycle, cip_header, payload_length + header_length, data_blocks,
 701			   data_block_counter, s->packet_index, index, curr_cycle_time);
 702}
 703
 704static int check_cip_header(struct amdtp_stream *s, const __be32 *buf,
 705			    unsigned int payload_length,
 706			    unsigned int *data_blocks,
 707			    unsigned int *data_block_counter, unsigned int *syt)
 708{
 
 709	u32 cip_header[2];
 710	unsigned int sph;
 711	unsigned int fmt;
 712	unsigned int fdf;
 713	unsigned int dbc;
 
 714	bool lost;
 715
 716	cip_header[0] = be32_to_cpu(buf[0]);
 717	cip_header[1] = be32_to_cpu(buf[1]);
 
 
 
 718
 719	/*
 720	 * This module supports 'Two-quadlet CIP header with SYT field'.
 721	 * For convenience, also check FMT field is AM824 or not.
 722	 */
 723	if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
 724	     ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) &&
 725	    (!(s->flags & CIP_HEADER_WITHOUT_EOH))) {
 726		dev_info_ratelimited(&s->unit->device,
 727				"Invalid CIP header for AMDTP: %08X:%08X\n",
 728				cip_header[0], cip_header[1]);
 729		return -EAGAIN;
 
 
 730	}
 731
 732	/* Check valid protocol or not. */
 733	sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
 734	fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT;
 735	if (sph != s->sph || fmt != s->fmt) {
 736		dev_info_ratelimited(&s->unit->device,
 737				     "Detect unexpected protocol: %08x %08x\n",
 738				     cip_header[0], cip_header[1]);
 739		return -EAGAIN;
 
 
 740	}
 741
 742	/* Calculate data blocks */
 743	fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT;
 744	if (payload_length == 0 || (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
 745		*data_blocks = 0;
 
 746	} else {
 747		unsigned int data_block_quadlets =
 748				(cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
 749		/* avoid division by zero */
 750		if (data_block_quadlets == 0) {
 751			dev_err(&s->unit->device,
 752				"Detect invalid value in dbs field: %08X\n",
 753				cip_header[0]);
 754			return -EPROTO;
 755		}
 756		if (s->flags & CIP_WRONG_DBS)
 757			data_block_quadlets = s->data_block_quadlets;
 758
 759		*data_blocks = payload_length / sizeof(__be32) / data_block_quadlets;
 760	}
 761
 762	/* Check data block counter continuity */
 763	dbc = cip_header[0] & CIP_DBC_MASK;
 764	if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
 765	    *data_block_counter != UINT_MAX)
 766		dbc = *data_block_counter;
 767
 768	if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) ||
 769	    *data_block_counter == UINT_MAX) {
 
 770		lost = false;
 771	} else if (!(s->flags & CIP_DBC_IS_END_EVENT)) {
 772		lost = dbc != *data_block_counter;
 773	} else {
 774		unsigned int dbc_interval;
 775
 776		if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
 777			dbc_interval = s->ctx_data.tx.dbc_interval;
 778		else
 779			dbc_interval = *data_blocks;
 780
 781		lost = dbc != ((*data_block_counter + dbc_interval) & 0xff);
 
 782	}
 783
 784	if (lost) {
 785		dev_err(&s->unit->device,
 786			"Detect discontinuity of CIP: %02X %02X\n",
 787			*data_block_counter, dbc);
 788		return -EIO;
 789	}
 790
 791	*data_block_counter = dbc;
 
 792
 793	if (!(s->flags & CIP_UNAWARE_SYT))
 794		*syt = cip_header[1] & CIP_SYT_MASK;
 795
 796	return 0;
 797}
 798
 799static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle,
 800			       const __be32 *ctx_header,
 801			       unsigned int *data_blocks,
 802			       unsigned int *data_block_counter,
 803			       unsigned int *syt, unsigned int packet_index, unsigned int index,
 804			       u32 curr_cycle_time)
 805{
 806	unsigned int payload_length;
 807	const __be32 *cip_header;
 808	unsigned int cip_header_size;
 809
 810	payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
 811
 812	if (!(s->flags & CIP_NO_HEADER))
 813		cip_header_size = CIP_HEADER_SIZE;
 814	else
 815		cip_header_size = 0;
 816
 817	if (payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) {
 818		dev_err(&s->unit->device,
 819			"Detect jumbo payload: %04x %04x\n",
 820			payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length);
 821		return -EIO;
 822	}
 823
 824	if (cip_header_size > 0) {
 825		if (payload_length >= cip_header_size) {
 826			int err;
 827
 828			cip_header = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS;
 829			err = check_cip_header(s, cip_header, payload_length - cip_header_size,
 830					       data_blocks, data_block_counter, syt);
 831			if (err < 0)
 832				return err;
 833		} else {
 834			// Handle the cycle so that empty packet arrives.
 835			cip_header = NULL;
 836			*data_blocks = 0;
 837			*syt = 0;
 838		}
 839	} else {
 840		cip_header = NULL;
 841		*data_blocks = payload_length / sizeof(__be32) / s->data_block_quadlets;
 842		*syt = 0;
 843
 844		if (*data_block_counter == UINT_MAX)
 845			*data_block_counter = 0;
 846	}
 847
 848	trace_amdtp_packet(s, cycle, cip_header, payload_length, *data_blocks,
 849			   *data_block_counter, packet_index, index, curr_cycle_time);
 850
 851	return 0;
 852}
 853
 854// In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On
 855// the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent
 856// it. Thus, via Linux firewire subsystem, we can get the 3 bits for second.
 857static inline u32 compute_ohci_iso_ctx_cycle_count(u32 tstamp)
 858{
 859	return (((tstamp >> 13) & 0x07) * CYCLES_PER_SECOND) + (tstamp & 0x1fff);
 860}
 861
 862static inline u32 compute_ohci_cycle_count(__be32 ctx_header_tstamp)
 863{
 864	u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK;
 865	return compute_ohci_iso_ctx_cycle_count(tstamp);
 866}
 867
 868static inline u32 increment_ohci_cycle_count(u32 cycle, unsigned int addend)
 869{
 870	cycle += addend;
 871	if (cycle >= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND)
 872		cycle -= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND;
 873	return cycle;
 874}
 875
 876static inline u32 decrement_ohci_cycle_count(u32 minuend, u32 subtrahend)
 877{
 878	if (minuend < subtrahend)
 879		minuend += OHCI_SECOND_MODULUS * CYCLES_PER_SECOND;
 880
 881	return minuend - subtrahend;
 882}
 883
 884static int compare_ohci_cycle_count(u32 lval, u32 rval)
 885{
 886	if (lval == rval)
 887		return 0;
 888	else if (lval < rval && rval - lval < OHCI_SECOND_MODULUS * CYCLES_PER_SECOND / 2)
 889		return -1;
 890	else
 891		return 1;
 892}
 893
 894// Align to actual cycle count for the packet which is going to be scheduled.
 895// This module queued the same number of isochronous cycle as the size of queue
 896// to kip isochronous cycle, therefore it's OK to just increment the cycle by
 897// the size of queue for scheduled cycle.
 898static inline u32 compute_ohci_it_cycle(const __be32 ctx_header_tstamp,
 899					unsigned int queue_size)
 900{
 901	u32 cycle = compute_ohci_cycle_count(ctx_header_tstamp);
 902	return increment_ohci_cycle_count(cycle, queue_size);
 903}
 904
 905static int generate_tx_packet_descs(struct amdtp_stream *s, struct pkt_desc *desc,
 906				    const __be32 *ctx_header, unsigned int packet_count,
 907				    unsigned int *desc_count)
 908{
 909	unsigned int next_cycle = s->next_cycle;
 910	unsigned int dbc = s->data_block_counter;
 911	unsigned int packet_index = s->packet_index;
 912	unsigned int queue_size = s->queue_size;
 913	u32 curr_cycle_time = 0;
 914	int i;
 915	int err;
 916
 917	if (trace_amdtp_packet_enabled())
 918		(void)fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &curr_cycle_time);
 919
 920	*desc_count = 0;
 921	for (i = 0; i < packet_count; ++i) {
 922		unsigned int cycle;
 923		bool lost;
 924		unsigned int data_blocks;
 925		unsigned int syt;
 926
 927		cycle = compute_ohci_cycle_count(ctx_header[1]);
 928		lost = (next_cycle != cycle);
 929		if (lost) {
 930			if (s->flags & CIP_NO_HEADER) {
 931				// Fireface skips transmission just for an isoc cycle corresponding
 932				// to empty packet.
 933				unsigned int prev_cycle = next_cycle;
 934
 935				next_cycle = increment_ohci_cycle_count(next_cycle, 1);
 936				lost = (next_cycle != cycle);
 937				if (!lost) {
 938					// Prepare a description for the skipped cycle for
 939					// sequence replay.
 940					desc->cycle = prev_cycle;
 941					desc->syt = 0;
 942					desc->data_blocks = 0;
 943					desc->data_block_counter = dbc;
 944					desc->ctx_payload = NULL;
 945					desc = amdtp_stream_next_packet_desc(s, desc);
 946					++(*desc_count);
 947				}
 948			} else if (s->flags & CIP_JUMBO_PAYLOAD) {
 949				// OXFW970 skips transmission for several isoc cycles during
 950				// asynchronous transaction. The sequence replay is impossible due
 951				// to the reason.
 952				unsigned int safe_cycle = increment_ohci_cycle_count(next_cycle,
 953								IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES);
 954				lost = (compare_ohci_cycle_count(safe_cycle, cycle) < 0);
 955			}
 956			if (lost) {
 957				dev_err(&s->unit->device, "Detect discontinuity of cycle: %d %d\n",
 958					next_cycle, cycle);
 959				return -EIO;
 960			}
 961		}
 962
 963		err = parse_ir_ctx_header(s, cycle, ctx_header, &data_blocks, &dbc, &syt,
 964					  packet_index, i, curr_cycle_time);
 965		if (err < 0)
 966			return err;
 967
 968		desc->cycle = cycle;
 969		desc->syt = syt;
 970		desc->data_blocks = data_blocks;
 971		desc->data_block_counter = dbc;
 972		desc->ctx_payload = s->buffer.packets[packet_index].buffer;
 973
 974		if (!(s->flags & CIP_DBC_IS_END_EVENT))
 975			dbc = (dbc + desc->data_blocks) & 0xff;
 976
 977		next_cycle = increment_ohci_cycle_count(next_cycle, 1);
 978		desc = amdtp_stream_next_packet_desc(s, desc);
 979		++(*desc_count);
 980		ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
 981		packet_index = (packet_index + 1) % queue_size;
 982	}
 983
 984	s->next_cycle = next_cycle;
 985	s->data_block_counter = dbc;
 986
 987	return 0;
 988}
 989
 990static unsigned int compute_syt(unsigned int syt_offset, unsigned int cycle,
 991				unsigned int transfer_delay)
 992{
 993	unsigned int syt;
 994
 995	syt_offset += transfer_delay;
 996	syt = ((cycle + syt_offset / TICKS_PER_CYCLE) << 12) |
 997	      (syt_offset % TICKS_PER_CYCLE);
 998	return syt & CIP_SYT_MASK;
 999}
1000
1001static void generate_rx_packet_descs(struct amdtp_stream *s, struct pkt_desc *desc,
1002				     const __be32 *ctx_header, unsigned int packet_count)
1003{
1004	struct seq_desc *seq_descs = s->ctx_data.rx.seq.descs;
1005	unsigned int seq_size = s->ctx_data.rx.seq.size;
1006	unsigned int seq_pos = s->ctx_data.rx.seq.pos;
1007	unsigned int dbc = s->data_block_counter;
1008	bool aware_syt = !(s->flags & CIP_UNAWARE_SYT);
1009	int i;
1010
1011	pool_seq_descs(s, seq_descs, seq_size, seq_pos, packet_count);
1012
1013	for (i = 0; i < packet_count; ++i) {
1014		unsigned int index = (s->packet_index + i) % s->queue_size;
1015		const struct seq_desc *seq = seq_descs + seq_pos;
1016
1017		desc->cycle = compute_ohci_it_cycle(*ctx_header, s->queue_size);
1018
1019		if (aware_syt && seq->syt_offset != CIP_SYT_NO_INFO)
1020			desc->syt = compute_syt(seq->syt_offset, desc->cycle, s->transfer_delay);
1021		else
1022			desc->syt = CIP_SYT_NO_INFO;
1023
1024		desc->data_blocks = seq->data_blocks;
1025
1026		if (s->flags & CIP_DBC_IS_END_EVENT)
1027			dbc = (dbc + desc->data_blocks) & 0xff;
1028
1029		desc->data_block_counter = dbc;
1030
1031		if (!(s->flags & CIP_DBC_IS_END_EVENT))
1032			dbc = (dbc + desc->data_blocks) & 0xff;
1033
1034		desc->ctx_payload = s->buffer.packets[index].buffer;
1035
1036		seq_pos = (seq_pos + 1) % seq_size;
1037		desc = amdtp_stream_next_packet_desc(s, desc);
1038
1039		++ctx_header;
1040	}
1041
1042	s->data_block_counter = dbc;
1043	s->ctx_data.rx.seq.pos = seq_pos;
1044}
1045
1046static inline void cancel_stream(struct amdtp_stream *s)
1047{
1048	s->packet_index = -1;
1049	if (in_softirq())
1050		amdtp_stream_pcm_abort(s);
1051	WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN);
1052}
1053
1054static snd_pcm_sframes_t compute_pcm_extra_delay(struct amdtp_stream *s,
1055						 const struct pkt_desc *desc, unsigned int count)
1056{
1057	unsigned int data_block_count = 0;
1058	u32 latest_cycle;
1059	u32 cycle_time;
1060	u32 curr_cycle;
1061	u32 cycle_gap;
1062	int i, err;
1063
1064	if (count == 0)
1065		goto end;
1066
1067	// Forward to the latest record.
1068	for (i = 0; i < count - 1; ++i)
1069		desc = amdtp_stream_next_packet_desc(s, desc);
1070	latest_cycle = desc->cycle;
1071
1072	err = fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &cycle_time);
1073	if (err < 0)
1074		goto end;
1075
1076	// Compute cycle count with lower 3 bits of second field and cycle field like timestamp
1077	// format of 1394 OHCI isochronous context.
1078	curr_cycle = compute_ohci_iso_ctx_cycle_count((cycle_time >> 12) & 0x0000ffff);
1079
1080	if (s->direction == AMDTP_IN_STREAM) {
1081		// NOTE: The AMDTP packet descriptor should be for the past isochronous cycle since
1082		// it corresponds to arrived isochronous packet.
1083		if (compare_ohci_cycle_count(latest_cycle, curr_cycle) > 0)
1084			goto end;
1085		cycle_gap = decrement_ohci_cycle_count(curr_cycle, latest_cycle);
1086
1087		// NOTE: estimate delay by recent history of arrived AMDTP packets. The estimated
1088		// value expectedly corresponds to a few packets (0-2) since the packet arrived at
1089		// the most recent isochronous cycle has been already processed.
1090		for (i = 0; i < cycle_gap; ++i) {
1091			desc = amdtp_stream_next_packet_desc(s, desc);
1092			data_block_count += desc->data_blocks;
1093		}
1094	} else {
1095		// NOTE: The AMDTP packet descriptor should be for the future isochronous cycle
1096		// since it was already scheduled.
1097		if (compare_ohci_cycle_count(latest_cycle, curr_cycle) < 0)
1098			goto end;
1099		cycle_gap = decrement_ohci_cycle_count(latest_cycle, curr_cycle);
1100
1101		// NOTE: use history of scheduled packets.
1102		for (i = 0; i < cycle_gap; ++i) {
1103			data_block_count += desc->data_blocks;
1104			desc = prev_packet_desc(s, desc);
1105		}
1106	}
1107end:
1108	return data_block_count * s->pcm_frame_multiplier;
1109}
1110
1111static void process_ctx_payloads(struct amdtp_stream *s,
1112				 const struct pkt_desc *desc,
1113				 unsigned int count)
1114{
1115	struct snd_pcm_substream *pcm;
1116	int i;
1117
1118	pcm = READ_ONCE(s->pcm);
1119	s->process_ctx_payloads(s, desc, count, pcm);
1120
1121	if (pcm) {
1122		unsigned int data_block_count = 0;
1123
1124		pcm->runtime->delay = compute_pcm_extra_delay(s, desc, count);
1125
1126		for (i = 0; i < count; ++i) {
1127			data_block_count += desc->data_blocks;
1128			desc = amdtp_stream_next_packet_desc(s, desc);
1129		}
1130
1131		update_pcm_pointers(s, pcm, data_block_count * s->pcm_frame_multiplier);
1132	}
1133}
1134
1135static void process_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1136			       void *header, void *private_data)
 
1137{
1138	struct amdtp_stream *s = private_data;
1139	const struct amdtp_domain *d = s->domain;
1140	const __be32 *ctx_header = header;
1141	const unsigned int events_per_period = d->events_per_period;
1142	unsigned int event_count = s->ctx_data.rx.event_count;
1143	struct pkt_desc *desc = s->packet_descs_cursor;
1144	unsigned int pkt_header_length;
1145	unsigned int packets;
1146	u32 curr_cycle_time;
1147	bool need_hw_irq;
1148	int i;
1149
1150	if (s->packet_index < 0)
1151		return;
1152
1153	// Calculate the number of packets in buffer and check XRUN.
1154	packets = header_length / sizeof(*ctx_header);
1155
1156	generate_rx_packet_descs(s, desc, ctx_header, packets);
1157
1158	process_ctx_payloads(s, desc, packets);
1159
1160	if (!(s->flags & CIP_NO_HEADER))
1161		pkt_header_length = IT_PKT_HEADER_SIZE_CIP;
1162	else
1163		pkt_header_length = 0;
1164
1165	if (s == d->irq_target) {
1166		// At NO_PERIOD_WAKEUP mode, the packets for all IT/IR contexts are processed by
1167		// the tasks of user process operating ALSA PCM character device by calling ioctl(2)
1168		// with some requests, instead of scheduled hardware IRQ of an IT context.
1169		struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
1170		need_hw_irq = !pcm || !pcm->runtime->no_period_wakeup;
1171	} else {
1172		need_hw_irq = false;
1173	}
1174
1175	if (trace_amdtp_packet_enabled())
1176		(void)fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &curr_cycle_time);
1177
1178	for (i = 0; i < packets; ++i) {
1179		struct {
1180			struct fw_iso_packet params;
1181			__be32 header[CIP_HEADER_QUADLETS];
1182		} template = { {0}, {0} };
1183		bool sched_irq = false;
1184
1185		build_it_pkt_header(s, desc->cycle, &template.params, pkt_header_length,
1186				    desc->data_blocks, desc->data_block_counter,
1187				    desc->syt, i, curr_cycle_time);
1188
1189		if (s == s->domain->irq_target) {
1190			event_count += desc->data_blocks;
1191			if (event_count >= events_per_period) {
1192				event_count -= events_per_period;
1193				sched_irq = need_hw_irq;
1194			}
1195		}
1196
1197		if (queue_out_packet(s, &template.params, sched_irq) < 0) {
1198			cancel_stream(s);
1199			return;
1200		}
1201
1202		desc = amdtp_stream_next_packet_desc(s, desc);
1203	}
1204
1205	s->ctx_data.rx.event_count = event_count;
1206	s->packet_descs_cursor = desc;
1207}
1208
1209static void skip_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1210			    void *header, void *private_data)
 
1211{
1212	struct amdtp_stream *s = private_data;
1213	struct amdtp_domain *d = s->domain;
1214	const __be32 *ctx_header = header;
1215	unsigned int packets;
1216	unsigned int cycle;
1217	int i;
1218
1219	if (s->packet_index < 0)
1220		return;
1221
1222	packets = header_length / sizeof(*ctx_header);
1223
1224	cycle = compute_ohci_it_cycle(ctx_header[packets - 1], s->queue_size);
1225	s->next_cycle = increment_ohci_cycle_count(cycle, 1);
1226
1227	for (i = 0; i < packets; ++i) {
1228		struct fw_iso_packet params = {
1229			.header_length = 0,
1230			.payload_length = 0,
1231		};
1232		bool sched_irq = (s == d->irq_target && i == packets - 1);
1233
1234		if (queue_out_packet(s, &params, sched_irq) < 0) {
1235			cancel_stream(s);
1236			return;
1237		}
1238	}
1239}
1240
1241static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1242				void *header, void *private_data);
1243
1244static void process_rx_packets_intermediately(struct fw_iso_context *context, u32 tstamp,
1245					size_t header_length, void *header, void *private_data)
1246{
1247	struct amdtp_stream *s = private_data;
1248	struct amdtp_domain *d = s->domain;
1249	__be32 *ctx_header = header;
1250	const unsigned int queue_size = s->queue_size;
1251	unsigned int packets;
1252	unsigned int offset;
1253
1254	if (s->packet_index < 0)
1255		return;
1256
1257	packets = header_length / sizeof(*ctx_header);
 
1258
1259	offset = 0;
1260	while (offset < packets) {
1261		unsigned int cycle = compute_ohci_it_cycle(ctx_header[offset], queue_size);
1262
1263		if (compare_ohci_cycle_count(cycle, d->processing_cycle.rx_start) >= 0)
 
 
 
 
 
 
1264			break;
1265
1266		++offset;
1267	}
1268
1269	if (offset > 0) {
1270		unsigned int length = sizeof(*ctx_header) * offset;
1271
1272		skip_rx_packets(context, tstamp, length, ctx_header, private_data);
1273		if (amdtp_streaming_error(s))
1274			return;
1275
1276		ctx_header += offset;
1277		header_length -= length;
1278	}
1279
1280	if (offset < packets) {
1281		s->ready_processing = true;
1282		wake_up(&s->ready_wait);
1283
1284		if (d->replay.enable)
1285			s->ctx_data.rx.cache_pos = 0;
1286
1287		process_rx_packets(context, tstamp, header_length, ctx_header, private_data);
1288		if (amdtp_streaming_error(s))
1289			return;
1290
1291		if (s == d->irq_target)
1292			s->context->callback.sc = irq_target_callback;
1293		else
1294			s->context->callback.sc = process_rx_packets;
1295	}
1296}
1297
1298static void process_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1299			       void *header, void *private_data)
1300{
1301	struct amdtp_stream *s = private_data;
1302	__be32 *ctx_header = header;
1303	struct pkt_desc *desc = s->packet_descs_cursor;
1304	unsigned int packet_count;
1305	unsigned int desc_count;
1306	int i;
1307	int err;
1308
1309	if (s->packet_index < 0)
1310		return;
1311
1312	// Calculate the number of packets in buffer and check XRUN.
1313	packet_count = header_length / s->ctx_data.tx.ctx_header_size;
1314
1315	desc_count = 0;
1316	err = generate_tx_packet_descs(s, desc, ctx_header, packet_count, &desc_count);
1317	if (err < 0) {
1318		if (err != -EAGAIN) {
1319			cancel_stream(s);
1320			return;
1321		}
1322	} else {
1323		struct amdtp_domain *d = s->domain;
1324
1325		process_ctx_payloads(s, desc, desc_count);
1326
1327		if (d->replay.enable)
1328			cache_seq(s, desc, desc_count);
1329
1330		for (i = 0; i < desc_count; ++i)
1331			desc = amdtp_stream_next_packet_desc(s, desc);
1332		s->packet_descs_cursor = desc;
1333	}
1334
1335	for (i = 0; i < packet_count; ++i) {
1336		struct fw_iso_packet params = {0};
1337
1338		if (queue_in_packet(s, &params) < 0) {
1339			cancel_stream(s);
1340			return;
1341		}
1342	}
1343}
1344
1345static void drop_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1346			    void *header, void *private_data)
1347{
1348	struct amdtp_stream *s = private_data;
1349	const __be32 *ctx_header = header;
1350	unsigned int packets;
1351	unsigned int cycle;
1352	int i;
1353
1354	if (s->packet_index < 0)
1355		return;
1356
1357	packets = header_length / s->ctx_data.tx.ctx_header_size;
1358
1359	ctx_header += (packets - 1) * s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
1360	cycle = compute_ohci_cycle_count(ctx_header[1]);
1361	s->next_cycle = increment_ohci_cycle_count(cycle, 1);
1362
1363	for (i = 0; i < packets; ++i) {
1364		struct fw_iso_packet params = {0};
1365
1366		if (queue_in_packet(s, &params) < 0) {
1367			cancel_stream(s);
1368			return;
1369		}
1370	}
1371}
1372
1373static void process_tx_packets_intermediately(struct fw_iso_context *context, u32 tstamp,
1374					size_t header_length, void *header, void *private_data)
1375{
1376	struct amdtp_stream *s = private_data;
1377	struct amdtp_domain *d = s->domain;
1378	__be32 *ctx_header;
1379	unsigned int packets;
1380	unsigned int offset;
1381
1382	if (s->packet_index < 0)
1383		return;
1384
1385	packets = header_length / s->ctx_data.tx.ctx_header_size;
1386
1387	offset = 0;
1388	ctx_header = header;
1389	while (offset < packets) {
1390		unsigned int cycle = compute_ohci_cycle_count(ctx_header[1]);
1391
1392		if (compare_ohci_cycle_count(cycle, d->processing_cycle.tx_start) >= 0)
1393			break;
1394
1395		ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32);
1396		++offset;
1397	}
1398
1399	ctx_header = header;
1400
1401	if (offset > 0) {
1402		size_t length = s->ctx_data.tx.ctx_header_size * offset;
1403
1404		drop_tx_packets(context, tstamp, length, ctx_header, s);
1405		if (amdtp_streaming_error(s))
1406			return;
1407
1408		ctx_header += length / sizeof(*ctx_header);
1409		header_length -= length;
1410	}
1411
1412	if (offset < packets) {
1413		s->ready_processing = true;
1414		wake_up(&s->ready_wait);
1415
1416		process_tx_packets(context, tstamp, header_length, ctx_header, s);
1417		if (amdtp_streaming_error(s))
1418			return;
1419
1420		context->callback.sc = process_tx_packets;
1421	}
1422}
1423
1424static void drop_tx_packets_initially(struct fw_iso_context *context, u32 tstamp,
1425				      size_t header_length, void *header, void *private_data)
1426{
1427	struct amdtp_stream *s = private_data;
1428	struct amdtp_domain *d = s->domain;
1429	__be32 *ctx_header;
1430	unsigned int count;
1431	unsigned int events;
1432	int i;
1433
1434	if (s->packet_index < 0)
1435		return;
1436
1437	count = header_length / s->ctx_data.tx.ctx_header_size;
1438
1439	// Attempt to detect any event in the batch of packets.
1440	events = 0;
1441	ctx_header = header;
1442	for (i = 0; i < count; ++i) {
1443		unsigned int payload_quads =
1444			(be32_to_cpu(*ctx_header) >> ISO_DATA_LENGTH_SHIFT) / sizeof(__be32);
1445		unsigned int data_blocks;
1446
1447		if (s->flags & CIP_NO_HEADER) {
1448			data_blocks = payload_quads / s->data_block_quadlets;
1449		} else {
1450			__be32 *cip_headers = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS;
1451
1452			if (payload_quads < CIP_HEADER_QUADLETS) {
1453				data_blocks = 0;
1454			} else {
1455				payload_quads -= CIP_HEADER_QUADLETS;
1456
1457				if (s->flags & CIP_UNAWARE_SYT) {
1458					data_blocks = payload_quads / s->data_block_quadlets;
1459				} else {
1460					u32 cip1 = be32_to_cpu(cip_headers[1]);
1461
1462					// NODATA packet can includes any data blocks but they are
1463					// not available as event.
1464					if ((cip1 & CIP_NO_DATA) == CIP_NO_DATA)
1465						data_blocks = 0;
1466					else
1467						data_blocks = payload_quads / s->data_block_quadlets;
1468				}
1469			}
1470		}
1471
1472		events += data_blocks;
1473
1474		ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32);
1475	}
1476
1477	drop_tx_packets(context, tstamp, header_length, header, s);
1478
1479	if (events > 0)
1480		s->ctx_data.tx.event_starts = true;
1481
1482	// Decide the cycle count to begin processing content of packet in IR contexts.
1483	{
1484		unsigned int stream_count = 0;
1485		unsigned int event_starts_count = 0;
1486		unsigned int cycle = UINT_MAX;
1487
1488		list_for_each_entry(s, &d->streams, list) {
1489			if (s->direction == AMDTP_IN_STREAM) {
1490				++stream_count;
1491				if (s->ctx_data.tx.event_starts)
1492					++event_starts_count;
1493			}
1494		}
1495
1496		if (stream_count == event_starts_count) {
1497			unsigned int next_cycle;
1498
1499			list_for_each_entry(s, &d->streams, list) {
1500				if (s->direction != AMDTP_IN_STREAM)
1501					continue;
1502
1503				next_cycle = increment_ohci_cycle_count(s->next_cycle,
1504								d->processing_cycle.tx_init_skip);
1505				if (cycle == UINT_MAX ||
1506				    compare_ohci_cycle_count(next_cycle, cycle) > 0)
1507					cycle = next_cycle;
1508
1509				s->context->callback.sc = process_tx_packets_intermediately;
1510			}
1511
1512			d->processing_cycle.tx_start = cycle;
1513		}
1514	}
1515}
1516
1517static void process_ctxs_in_domain(struct amdtp_domain *d)
1518{
1519	struct amdtp_stream *s;
1520
1521	list_for_each_entry(s, &d->streams, list) {
1522		if (s != d->irq_target && amdtp_stream_running(s))
1523			fw_iso_context_flush_completions(s->context);
1524
1525		if (amdtp_streaming_error(s))
1526			goto error;
1527	}
1528
1529	return;
1530error:
1531	if (amdtp_stream_running(d->irq_target))
1532		cancel_stream(d->irq_target);
1533
1534	list_for_each_entry(s, &d->streams, list) {
1535		if (amdtp_stream_running(s))
1536			cancel_stream(s);
1537	}
1538}
1539
1540static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1541				void *header, void *private_data)
1542{
1543	struct amdtp_stream *s = private_data;
1544	struct amdtp_domain *d = s->domain;
1545
1546	process_rx_packets(context, tstamp, header_length, header, private_data);
1547	process_ctxs_in_domain(d);
1548}
1549
1550static void irq_target_callback_intermediately(struct fw_iso_context *context, u32 tstamp,
1551					size_t header_length, void *header, void *private_data)
1552{
1553	struct amdtp_stream *s = private_data;
1554	struct amdtp_domain *d = s->domain;
1555
1556	process_rx_packets_intermediately(context, tstamp, header_length, header, private_data);
1557	process_ctxs_in_domain(d);
1558}
1559
1560static void irq_target_callback_skip(struct fw_iso_context *context, u32 tstamp,
1561				     size_t header_length, void *header, void *private_data)
1562{
1563	struct amdtp_stream *s = private_data;
1564	struct amdtp_domain *d = s->domain;
1565	bool ready_to_start;
1566
1567	skip_rx_packets(context, tstamp, header_length, header, private_data);
1568	process_ctxs_in_domain(d);
1569
1570	if (d->replay.enable && !d->replay.on_the_fly) {
1571		unsigned int rx_count = 0;
1572		unsigned int rx_ready_count = 0;
1573		struct amdtp_stream *rx;
1574
1575		list_for_each_entry(rx, &d->streams, list) {
1576			struct amdtp_stream *tx;
1577			unsigned int cached_cycles;
1578
1579			if (rx->direction != AMDTP_OUT_STREAM)
1580				continue;
1581			++rx_count;
1582
1583			tx = rx->ctx_data.rx.replay_target;
1584			cached_cycles = calculate_cached_cycle_count(tx, 0);
1585			if (cached_cycles > tx->ctx_data.tx.cache.size / 2)
1586				++rx_ready_count;
1587		}
1588
1589		ready_to_start = (rx_count == rx_ready_count);
1590	} else {
1591		ready_to_start = true;
1592	}
1593
1594	// Decide the cycle count to begin processing content of packet in IT contexts. All of IT
1595	// contexts are expected to start and get callback when reaching here.
1596	if (ready_to_start) {
1597		unsigned int cycle = s->next_cycle;
1598		list_for_each_entry(s, &d->streams, list) {
1599			if (s->direction != AMDTP_OUT_STREAM)
1600				continue;
1601
1602			if (compare_ohci_cycle_count(s->next_cycle, cycle) > 0)
1603				cycle = s->next_cycle;
1604
1605			if (s == d->irq_target)
1606				s->context->callback.sc = irq_target_callback_intermediately;
1607			else
1608				s->context->callback.sc = process_rx_packets_intermediately;
1609		}
1610
1611		d->processing_cycle.rx_start = cycle;
1612	}
1613}
1614
1615// This is executed one time. For in-stream, first packet has come. For out-stream, prepared to
1616// transmit first packet.
1617static void amdtp_stream_first_callback(struct fw_iso_context *context,
1618					u32 tstamp, size_t header_length,
1619					void *header, void *private_data)
1620{
1621	struct amdtp_stream *s = private_data;
1622	struct amdtp_domain *d = s->domain;
1623
1624	if (s->direction == AMDTP_IN_STREAM) {
1625		context->callback.sc = drop_tx_packets_initially;
1626	} else {
1627		if (s == d->irq_target)
1628			context->callback.sc = irq_target_callback_skip;
1629		else
1630			context->callback.sc = skip_rx_packets;
1631	}
 
 
 
1632
1633	context->callback.sc(context, tstamp, header_length, header, s);
1634}
1635
1636/**
1637 * amdtp_stream_start - start transferring packets
1638 * @s: the AMDTP stream to start
1639 * @channel: the isochronous channel on the bus
1640 * @speed: firewire speed code
1641 * @queue_size: The number of packets in the queue.
1642 * @idle_irq_interval: the interval to queue packet during initial state.
1643 *
1644 * The stream cannot be started until it has been configured with
1645 * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI
1646 * device can be started.
1647 */
1648static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
1649			      unsigned int queue_size, unsigned int idle_irq_interval)
1650{
1651	bool is_irq_target = (s == s->domain->irq_target);
1652	unsigned int ctx_header_size;
1653	unsigned int max_ctx_payload_size;
 
 
 
 
 
 
 
 
 
 
1654	enum dma_data_direction dir;
1655	struct pkt_desc *descs;
1656	int i, type, tag, err;
1657
1658	mutex_lock(&s->mutex);
1659
1660	if (WARN_ON(amdtp_stream_running(s) ||
1661		    (s->data_block_quadlets < 1))) {
1662		err = -EBADFD;
1663		goto err_unlock;
1664	}
1665
1666	if (s->direction == AMDTP_IN_STREAM) {
1667		// NOTE: IT context should be used for constant IRQ.
1668		if (is_irq_target) {
1669			err = -EINVAL;
1670			goto err_unlock;
1671		}
1672
1673		s->data_block_counter = UINT_MAX;
1674	} else {
1675		s->data_block_counter = 0;
1676	}
 
 
1677
1678	// initialize packet buffer.
1679	if (s->direction == AMDTP_IN_STREAM) {
1680		dir = DMA_FROM_DEVICE;
1681		type = FW_ISO_CONTEXT_RECEIVE;
1682		if (!(s->flags & CIP_NO_HEADER))
1683			ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
1684		else
1685			ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
1686	} else {
1687		dir = DMA_TO_DEVICE;
1688		type = FW_ISO_CONTEXT_TRANSMIT;
1689		ctx_header_size = 0;	// No effect for IT context.
1690	}
1691	max_ctx_payload_size = amdtp_stream_get_max_ctx_payload_size(s);
1692
1693	err = iso_packets_buffer_init(&s->buffer, s->unit, queue_size, max_ctx_payload_size, dir);
1694	if (err < 0)
1695		goto err_unlock;
1696	s->queue_size = queue_size;
1697
1698	s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
1699					  type, channel, speed, ctx_header_size,
1700					  amdtp_stream_first_callback, s);
1701	if (IS_ERR(s->context)) {
1702		err = PTR_ERR(s->context);
1703		if (err == -EBUSY)
1704			dev_err(&s->unit->device,
1705				"no free stream on this controller\n");
1706		goto err_buffer;
1707	}
1708
1709	amdtp_stream_update(s);
1710
1711	if (s->direction == AMDTP_IN_STREAM) {
1712		s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
1713		s->ctx_data.tx.ctx_header_size = ctx_header_size;
1714		s->ctx_data.tx.event_starts = false;
1715
1716		if (s->domain->replay.enable) {
1717			// struct fw_iso_context.drop_overflow_headers is false therefore it's
1718			// possible to cache much unexpectedly.
1719			s->ctx_data.tx.cache.size = max_t(unsigned int, s->syt_interval * 2,
1720							  queue_size * 3 / 2);
1721			s->ctx_data.tx.cache.pos = 0;
1722			s->ctx_data.tx.cache.descs = kcalloc(s->ctx_data.tx.cache.size,
1723						sizeof(*s->ctx_data.tx.cache.descs), GFP_KERNEL);
1724			if (!s->ctx_data.tx.cache.descs) {
1725				err = -ENOMEM;
1726				goto err_context;
1727			}
1728		}
1729	} else {
1730		static const struct {
1731			unsigned int data_block;
1732			unsigned int syt_offset;
1733		} *entry, initial_state[] = {
1734			[CIP_SFC_32000]  = {  4, 3072 },
1735			[CIP_SFC_48000]  = {  6, 1024 },
1736			[CIP_SFC_96000]  = { 12, 1024 },
1737			[CIP_SFC_192000] = { 24, 1024 },
1738			[CIP_SFC_44100]  = {  0,   67 },
1739			[CIP_SFC_88200]  = {  0,   67 },
1740			[CIP_SFC_176400] = {  0,   67 },
1741		};
1742
1743		s->ctx_data.rx.seq.descs = kcalloc(queue_size, sizeof(*s->ctx_data.rx.seq.descs), GFP_KERNEL);
1744		if (!s->ctx_data.rx.seq.descs) {
1745			err = -ENOMEM;
1746			goto err_context;
1747		}
1748		s->ctx_data.rx.seq.size = queue_size;
1749		s->ctx_data.rx.seq.pos = 0;
1750
1751		entry = &initial_state[s->sfc];
1752		s->ctx_data.rx.data_block_state = entry->data_block;
1753		s->ctx_data.rx.syt_offset_state = entry->syt_offset;
1754		s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE;
1755
1756		s->ctx_data.rx.event_count = 0;
1757	}
1758
1759	if (s->flags & CIP_NO_HEADER)
1760		s->tag = TAG_NO_CIP_HEADER;
1761	else
1762		s->tag = TAG_CIP;
1763
1764	// NOTE: When operating without hardIRQ/softIRQ, applications tends to call ioctl request
1765	// for runtime of PCM substream in the interval equivalent to the size of PCM buffer. It
1766	// could take a round over queue of AMDTP packet descriptors and small loss of history. For
1767	// safe, keep more 8 elements for the queue, equivalent to 1 ms.
1768	descs = kcalloc(s->queue_size + 8, sizeof(*descs), GFP_KERNEL);
1769	if (!descs) {
1770		err = -ENOMEM;
1771		goto err_context;
1772	}
1773	s->packet_descs = descs;
1774
1775	INIT_LIST_HEAD(&s->packet_descs_list);
1776	for (i = 0; i < s->queue_size; ++i) {
1777		INIT_LIST_HEAD(&descs->link);
1778		list_add_tail(&descs->link, &s->packet_descs_list);
1779		++descs;
1780	}
1781	s->packet_descs_cursor = list_first_entry(&s->packet_descs_list, struct pkt_desc, link);
1782
1783	s->packet_index = 0;
1784	do {
1785		struct fw_iso_packet params;
1786
1787		if (s->direction == AMDTP_IN_STREAM) {
1788			err = queue_in_packet(s, &params);
1789		} else {
1790			bool sched_irq = false;
1791
1792			params.header_length = 0;
1793			params.payload_length = 0;
1794
1795			if (is_irq_target) {
1796				sched_irq = !((s->packet_index + 1) %
1797					      idle_irq_interval);
1798			}
1799
1800			err = queue_out_packet(s, &params, sched_irq);
1801		}
1802		if (err < 0)
1803			goto err_pkt_descs;
1804	} while (s->packet_index > 0);
1805
1806	/* NOTE: TAG1 matches CIP. This just affects in stream. */
1807	tag = FW_ISO_CONTEXT_MATCH_TAG1;
1808	if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER))
1809		tag |= FW_ISO_CONTEXT_MATCH_TAG0;
1810
1811	s->ready_processing = false;
1812	err = fw_iso_context_start(s->context, -1, 0, tag);
1813	if (err < 0)
1814		goto err_pkt_descs;
1815
1816	mutex_unlock(&s->mutex);
1817
1818	return 0;
1819err_pkt_descs:
1820	kfree(s->packet_descs);
1821	s->packet_descs = NULL;
1822err_context:
1823	if (s->direction == AMDTP_OUT_STREAM) {
1824		kfree(s->ctx_data.rx.seq.descs);
1825	} else {
1826		if (s->domain->replay.enable)
1827			kfree(s->ctx_data.tx.cache.descs);
1828	}
1829	fw_iso_context_destroy(s->context);
1830	s->context = ERR_PTR(-1);
1831err_buffer:
1832	iso_packets_buffer_destroy(&s->buffer, s->unit);
1833err_unlock:
1834	mutex_unlock(&s->mutex);
1835
1836	return err;
1837}
 
1838
1839/**
1840 * amdtp_domain_stream_pcm_pointer - get the PCM buffer position
1841 * @d: the AMDTP domain.
1842 * @s: the AMDTP stream that transports the PCM data
1843 *
1844 * Returns the current buffer position, in frames.
1845 */
1846unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d,
1847					      struct amdtp_stream *s)
1848{
1849	struct amdtp_stream *irq_target = d->irq_target;
1850
1851	// Process isochronous packets queued till recent isochronous cycle to handle PCM frames.
1852	if (irq_target && amdtp_stream_running(irq_target)) {
1853		// In software IRQ context, the call causes dead-lock to disable the tasklet
1854		// synchronously.
1855		if (!in_softirq())
1856			fw_iso_context_flush_completions(irq_target->context);
1857	}
1858
1859	return READ_ONCE(s->pcm_buffer_pointer);
1860}
1861EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_pointer);
1862
1863/**
1864 * amdtp_domain_stream_pcm_ack - acknowledge queued PCM frames
1865 * @d: the AMDTP domain.
1866 * @s: the AMDTP stream that transfers the PCM frames
1867 *
1868 * Returns zero always.
1869 */
1870int amdtp_domain_stream_pcm_ack(struct amdtp_domain *d, struct amdtp_stream *s)
1871{
1872	struct amdtp_stream *irq_target = d->irq_target;
1873
1874	// Process isochronous packets for recent isochronous cycle to handle
1875	// queued PCM frames.
1876	if (irq_target && amdtp_stream_running(irq_target))
1877		fw_iso_context_flush_completions(irq_target->context);
 
 
 
 
 
 
 
 
 
 
 
 
1878
1879	return 0;
1880}
1881EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_ack);
1882
1883/**
1884 * amdtp_stream_update - update the stream after a bus reset
1885 * @s: the AMDTP stream
1886 */
1887void amdtp_stream_update(struct amdtp_stream *s)
1888{
1889	/* Precomputing. */
1890	WRITE_ONCE(s->source_node_id_field,
1891                   (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK);
 
1892}
1893EXPORT_SYMBOL(amdtp_stream_update);
1894
1895/**
1896 * amdtp_stream_stop - stop sending packets
1897 * @s: the AMDTP stream to stop
1898 *
1899 * All PCM and MIDI devices of the stream must be stopped before the stream
1900 * itself can be stopped.
1901 */
1902static void amdtp_stream_stop(struct amdtp_stream *s)
1903{
1904	mutex_lock(&s->mutex);
1905
1906	if (!amdtp_stream_running(s)) {
1907		mutex_unlock(&s->mutex);
1908		return;
1909	}
1910
 
1911	fw_iso_context_stop(s->context);
1912	fw_iso_context_destroy(s->context);
1913	s->context = ERR_PTR(-1);
1914	iso_packets_buffer_destroy(&s->buffer, s->unit);
1915	kfree(s->packet_descs);
1916	s->packet_descs = NULL;
1917
1918	if (s->direction == AMDTP_OUT_STREAM) {
1919		kfree(s->ctx_data.rx.seq.descs);
1920	} else {
1921		if (s->domain->replay.enable)
1922			kfree(s->ctx_data.tx.cache.descs);
1923	}
1924
1925	mutex_unlock(&s->mutex);
1926}
 
1927
1928/**
1929 * amdtp_stream_pcm_abort - abort the running PCM device
1930 * @s: the AMDTP stream about to be stopped
1931 *
1932 * If the isochronous stream needs to be stopped asynchronously, call this
1933 * function first to stop the PCM device.
1934 */
1935void amdtp_stream_pcm_abort(struct amdtp_stream *s)
1936{
1937	struct snd_pcm_substream *pcm;
1938
1939	pcm = READ_ONCE(s->pcm);
1940	if (pcm)
1941		snd_pcm_stop_xrun(pcm);
1942}
1943EXPORT_SYMBOL(amdtp_stream_pcm_abort);
1944
1945/**
1946 * amdtp_domain_init - initialize an AMDTP domain structure
1947 * @d: the AMDTP domain to initialize.
1948 */
1949int amdtp_domain_init(struct amdtp_domain *d)
1950{
1951	INIT_LIST_HEAD(&d->streams);
1952
1953	d->events_per_period = 0;
1954
1955	return 0;
1956}
1957EXPORT_SYMBOL_GPL(amdtp_domain_init);
1958
1959/**
1960 * amdtp_domain_destroy - destroy an AMDTP domain structure
1961 * @d: the AMDTP domain to destroy.
1962 */
1963void amdtp_domain_destroy(struct amdtp_domain *d)
1964{
1965	// At present nothing to do.
1966	return;
1967}
1968EXPORT_SYMBOL_GPL(amdtp_domain_destroy);
1969
1970/**
1971 * amdtp_domain_add_stream - register isoc context into the domain.
1972 * @d: the AMDTP domain.
1973 * @s: the AMDTP stream.
1974 * @channel: the isochronous channel on the bus.
1975 * @speed: firewire speed code.
1976 */
1977int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s,
1978			    int channel, int speed)
1979{
1980	struct amdtp_stream *tmp;
1981
1982	list_for_each_entry(tmp, &d->streams, list) {
1983		if (s == tmp)
1984			return -EBUSY;
1985	}
1986
1987	list_add(&s->list, &d->streams);
1988
1989	s->channel = channel;
1990	s->speed = speed;
1991	s->domain = d;
1992
1993	return 0;
1994}
1995EXPORT_SYMBOL_GPL(amdtp_domain_add_stream);
1996
1997// Make the reference from rx stream to tx stream for sequence replay. When the number of tx streams
1998// is less than the number of rx streams, the first tx stream is selected.
1999static int make_association(struct amdtp_domain *d)
2000{
2001	unsigned int dst_index = 0;
2002	struct amdtp_stream *rx;
2003
2004	// Make association to replay target.
2005	list_for_each_entry(rx, &d->streams, list) {
2006		if (rx->direction == AMDTP_OUT_STREAM) {
2007			unsigned int src_index = 0;
2008			struct amdtp_stream *tx = NULL;
2009			struct amdtp_stream *s;
2010
2011			list_for_each_entry(s, &d->streams, list) {
2012				if (s->direction == AMDTP_IN_STREAM) {
2013					if (dst_index == src_index) {
2014						tx = s;
2015						break;
2016					}
2017
2018					++src_index;
2019				}
2020			}
2021			if (!tx) {
2022				// Select the first entry.
2023				list_for_each_entry(s, &d->streams, list) {
2024					if (s->direction == AMDTP_IN_STREAM) {
2025						tx = s;
2026						break;
2027					}
2028				}
2029				// No target is available to replay sequence.
2030				if (!tx)
2031					return -EINVAL;
2032			}
2033
2034			rx->ctx_data.rx.replay_target = tx;
2035
2036			++dst_index;
2037		}
2038	}
2039
2040	return 0;
2041}
2042
2043/**
2044 * amdtp_domain_start - start sending packets for isoc context in the domain.
2045 * @d: the AMDTP domain.
2046 * @tx_init_skip_cycles: the number of cycles to skip processing packets at initial stage of IR
2047 *			 contexts.
2048 * @replay_seq: whether to replay the sequence of packet in IR context for the sequence of packet in
2049 *		IT context.
2050 * @replay_on_the_fly: transfer rx packets according to nominal frequency, then begin to replay
2051 *		       according to arrival of events in tx packets.
2052 */
2053int amdtp_domain_start(struct amdtp_domain *d, unsigned int tx_init_skip_cycles, bool replay_seq,
2054		       bool replay_on_the_fly)
2055{
2056	unsigned int events_per_buffer = d->events_per_buffer;
2057	unsigned int events_per_period = d->events_per_period;
2058	unsigned int queue_size;
2059	struct amdtp_stream *s;
2060	bool found = false;
2061	int err;
2062
2063	if (replay_seq) {
2064		err = make_association(d);
2065		if (err < 0)
2066			return err;
2067	}
2068	d->replay.enable = replay_seq;
2069	d->replay.on_the_fly = replay_on_the_fly;
2070
2071	// Select an IT context as IRQ target.
2072	list_for_each_entry(s, &d->streams, list) {
2073		if (s->direction == AMDTP_OUT_STREAM) {
2074			found = true;
2075			break;
2076		}
2077	}
2078	if (!found)
2079		return -ENXIO;
2080	d->irq_target = s;
2081
2082	d->processing_cycle.tx_init_skip = tx_init_skip_cycles;
2083
2084	// This is a case that AMDTP streams in domain run just for MIDI
2085	// substream. Use the number of events equivalent to 10 msec as
2086	// interval of hardware IRQ.
2087	if (events_per_period == 0)
2088		events_per_period = amdtp_rate_table[d->irq_target->sfc] / 100;
2089	if (events_per_buffer == 0)
2090		events_per_buffer = events_per_period * 3;
2091
2092	queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer,
2093				  amdtp_rate_table[d->irq_target->sfc]);
2094
2095	list_for_each_entry(s, &d->streams, list) {
2096		unsigned int idle_irq_interval = 0;
2097
2098		if (s->direction == AMDTP_OUT_STREAM && s == d->irq_target) {
2099			idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period,
2100							 amdtp_rate_table[d->irq_target->sfc]);
2101		}
2102
2103		// Starts immediately but actually DMA context starts several hundred cycles later.
2104		err = amdtp_stream_start(s, s->channel, s->speed, queue_size, idle_irq_interval);
2105		if (err < 0)
2106			goto error;
2107	}
2108
2109	return 0;
2110error:
2111	list_for_each_entry(s, &d->streams, list)
2112		amdtp_stream_stop(s);
2113	return err;
2114}
2115EXPORT_SYMBOL_GPL(amdtp_domain_start);
2116
2117/**
2118 * amdtp_domain_stop - stop sending packets for isoc context in the same domain.
2119 * @d: the AMDTP domain to which the isoc contexts belong.
2120 */
2121void amdtp_domain_stop(struct amdtp_domain *d)
2122{
2123	struct amdtp_stream *s, *next;
2124
2125	if (d->irq_target)
2126		amdtp_stream_stop(d->irq_target);
2127
2128	list_for_each_entry_safe(s, next, &d->streams, list) {
2129		list_del(&s->list);
2130
2131		if (s != d->irq_target)
2132			amdtp_stream_stop(s);
2133	}
2134
2135	d->events_per_period = 0;
2136	d->irq_target = NULL;
2137}
2138EXPORT_SYMBOL_GPL(amdtp_domain_stop);