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1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static const char driver_name[] = "SyncLink GT";
91static const char tty_dev_prefix[] = "ttySLG";
92MODULE_LICENSE("GPL");
93#define MAX_DEVICES 32
94
95static const struct pci_device_id pci_table[] = {
96 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT_DEVICE_ID) },
97 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT2_DEVICE_ID) },
98 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT4_DEVICE_ID) },
99 { PCI_VDEVICE(MICROGATE, SYNCLINK_AC_DEVICE_ID) },
100 { 0 }, /* terminate list */
101};
102MODULE_DEVICE_TABLE(pci, pci_table);
103
104static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
105static void remove_one(struct pci_dev *dev);
106static struct pci_driver pci_driver = {
107 .name = "synclink_gt",
108 .id_table = pci_table,
109 .probe = init_one,
110 .remove = remove_one,
111};
112
113static bool pci_registered;
114
115/*
116 * module configuration and status
117 */
118static struct slgt_info *slgt_device_list;
119static int slgt_device_count;
120
121static int ttymajor;
122static int debug_level;
123static int maxframe[MAX_DEVICES];
124
125module_param(ttymajor, int, 0);
126module_param(debug_level, int, 0);
127module_param_array(maxframe, int, NULL, 0);
128
129MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
130MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
131MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
132
133/*
134 * tty support and callbacks
135 */
136static struct tty_driver *serial_driver;
137
138static void wait_until_sent(struct tty_struct *tty, int timeout);
139static void flush_buffer(struct tty_struct *tty);
140static void tx_release(struct tty_struct *tty);
141
142/*
143 * generic HDLC support
144 */
145#define dev_to_port(D) (dev_to_hdlc(D)->priv)
146
147
148/*
149 * device specific structures, macros and functions
150 */
151
152#define SLGT_MAX_PORTS 4
153#define SLGT_REG_SIZE 256
154
155/*
156 * conditional wait facility
157 */
158struct cond_wait {
159 struct cond_wait *next;
160 wait_queue_head_t q;
161 wait_queue_entry_t wait;
162 unsigned int data;
163};
164static void flush_cond_wait(struct cond_wait **head);
165
166/*
167 * DMA buffer descriptor and access macros
168 */
169struct slgt_desc
170{
171 __le16 count;
172 __le16 status;
173 __le32 pbuf; /* physical address of data buffer */
174 __le32 next; /* physical address of next descriptor */
175
176 /* driver book keeping */
177 char *buf; /* virtual address of data buffer */
178 unsigned int pdesc; /* physical address of this descriptor */
179 dma_addr_t buf_dma_addr;
180 unsigned short buf_count;
181};
182
183#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
184#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
185#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
186#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
187#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
188#define desc_count(a) (le16_to_cpu((a).count))
189#define desc_status(a) (le16_to_cpu((a).status))
190#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
191#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
192#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
193#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
194#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
195
196struct _input_signal_events {
197 int ri_up;
198 int ri_down;
199 int dsr_up;
200 int dsr_down;
201 int dcd_up;
202 int dcd_down;
203 int cts_up;
204 int cts_down;
205};
206
207/*
208 * device instance data structure
209 */
210struct slgt_info {
211 void *if_ptr; /* General purpose pointer (used by SPPP) */
212 struct tty_port port;
213
214 struct slgt_info *next_device; /* device list link */
215
216 char device_name[25];
217 struct pci_dev *pdev;
218
219 int port_count; /* count of ports on adapter */
220 int adapter_num; /* adapter instance number */
221 int port_num; /* port instance number */
222
223 /* array of pointers to port contexts on this adapter */
224 struct slgt_info *port_array[SLGT_MAX_PORTS];
225
226 int line; /* tty line instance number */
227
228 struct mgsl_icount icount;
229
230 int timeout;
231 int x_char; /* xon/xoff character */
232 unsigned int read_status_mask;
233 unsigned int ignore_status_mask;
234
235 wait_queue_head_t status_event_wait_q;
236 wait_queue_head_t event_wait_q;
237 struct timer_list tx_timer;
238 struct timer_list rx_timer;
239
240 unsigned int gpio_present;
241 struct cond_wait *gpio_wait_q;
242
243 spinlock_t lock; /* spinlock for synchronizing with ISR */
244
245 struct work_struct task;
246 u32 pending_bh;
247 bool bh_requested;
248 bool bh_running;
249
250 int isr_overflow;
251 bool irq_requested; /* true if IRQ requested */
252 bool irq_occurred; /* for diagnostics use */
253
254 /* device configuration */
255
256 unsigned int bus_type;
257 unsigned int irq_level;
258 unsigned long irq_flags;
259
260 unsigned char __iomem * reg_addr; /* memory mapped registers address */
261 u32 phys_reg_addr;
262 bool reg_addr_requested;
263
264 MGSL_PARAMS params; /* communications parameters */
265 u32 idle_mode;
266 u32 max_frame_size; /* as set by device config */
267
268 unsigned int rbuf_fill_level;
269 unsigned int rx_pio;
270 unsigned int if_mode;
271 unsigned int base_clock;
272 unsigned int xsync;
273 unsigned int xctrl;
274
275 /* device status */
276
277 bool rx_enabled;
278 bool rx_restart;
279
280 bool tx_enabled;
281 bool tx_active;
282
283 unsigned char signals; /* serial signal states */
284 int init_error; /* initialization error */
285
286 unsigned char *tx_buf;
287 int tx_count;
288
289 bool drop_rts_on_tx_done;
290 struct _input_signal_events input_signal_events;
291
292 int dcd_chkcount; /* check counts to prevent */
293 int cts_chkcount; /* too many IRQs if a signal */
294 int dsr_chkcount; /* is floating */
295 int ri_chkcount;
296
297 char *bufs; /* virtual address of DMA buffer lists */
298 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
299
300 unsigned int rbuf_count;
301 struct slgt_desc *rbufs;
302 unsigned int rbuf_current;
303 unsigned int rbuf_index;
304 unsigned int rbuf_fill_index;
305 unsigned short rbuf_fill_count;
306
307 unsigned int tbuf_count;
308 struct slgt_desc *tbufs;
309 unsigned int tbuf_current;
310 unsigned int tbuf_start;
311
312 unsigned char *tmp_rbuf;
313 unsigned int tmp_rbuf_count;
314
315 /* SPPP/Cisco HDLC device parts */
316
317 int netcount;
318 spinlock_t netlock;
319#if SYNCLINK_GENERIC_HDLC
320 struct net_device *netdev;
321#endif
322
323};
324
325static const MGSL_PARAMS default_params = {
326 .mode = MGSL_MODE_HDLC,
327 .loopback = 0,
328 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
329 .encoding = HDLC_ENCODING_NRZI_SPACE,
330 .clock_speed = 0,
331 .addr_filter = 0xff,
332 .crc_type = HDLC_CRC_16_CCITT,
333 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
334 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
335 .data_rate = 9600,
336 .data_bits = 8,
337 .stop_bits = 1,
338 .parity = ASYNC_PARITY_NONE
339};
340
341
342#define BH_RECEIVE 1
343#define BH_TRANSMIT 2
344#define BH_STATUS 4
345#define IO_PIN_SHUTDOWN_LIMIT 100
346
347#define DMABUFSIZE 256
348#define DESC_LIST_SIZE 4096
349
350#define MASK_PARITY BIT1
351#define MASK_FRAMING BIT0
352#define MASK_BREAK BIT14
353#define MASK_OVERRUN BIT4
354
355#define GSR 0x00 /* global status */
356#define JCR 0x04 /* JTAG control */
357#define IODR 0x08 /* GPIO direction */
358#define IOER 0x0c /* GPIO interrupt enable */
359#define IOVR 0x10 /* GPIO value */
360#define IOSR 0x14 /* GPIO interrupt status */
361#define TDR 0x80 /* tx data */
362#define RDR 0x80 /* rx data */
363#define TCR 0x82 /* tx control */
364#define TIR 0x84 /* tx idle */
365#define TPR 0x85 /* tx preamble */
366#define RCR 0x86 /* rx control */
367#define VCR 0x88 /* V.24 control */
368#define CCR 0x89 /* clock control */
369#define BDR 0x8a /* baud divisor */
370#define SCR 0x8c /* serial control */
371#define SSR 0x8e /* serial status */
372#define RDCSR 0x90 /* rx DMA control/status */
373#define TDCSR 0x94 /* tx DMA control/status */
374#define RDDAR 0x98 /* rx DMA descriptor address */
375#define TDDAR 0x9c /* tx DMA descriptor address */
376#define XSR 0x40 /* extended sync pattern */
377#define XCR 0x44 /* extended control */
378
379#define RXIDLE BIT14
380#define RXBREAK BIT14
381#define IRQ_TXDATA BIT13
382#define IRQ_TXIDLE BIT12
383#define IRQ_TXUNDER BIT11 /* HDLC */
384#define IRQ_RXDATA BIT10
385#define IRQ_RXIDLE BIT9 /* HDLC */
386#define IRQ_RXBREAK BIT9 /* async */
387#define IRQ_RXOVER BIT8
388#define IRQ_DSR BIT7
389#define IRQ_CTS BIT6
390#define IRQ_DCD BIT5
391#define IRQ_RI BIT4
392#define IRQ_ALL 0x3ff0
393#define IRQ_MASTER BIT0
394
395#define slgt_irq_on(info, mask) \
396 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
397#define slgt_irq_off(info, mask) \
398 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
399
400static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
401static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
402static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
403static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
404static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
405static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
406
407static void msc_set_vcr(struct slgt_info *info);
408
409static int startup(struct slgt_info *info);
410static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
411static void shutdown(struct slgt_info *info);
412static void program_hw(struct slgt_info *info);
413static void change_params(struct slgt_info *info);
414
415static int adapter_test(struct slgt_info *info);
416
417static void reset_port(struct slgt_info *info);
418static void async_mode(struct slgt_info *info);
419static void sync_mode(struct slgt_info *info);
420
421static void rx_stop(struct slgt_info *info);
422static void rx_start(struct slgt_info *info);
423static void reset_rbufs(struct slgt_info *info);
424static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
425static bool rx_get_frame(struct slgt_info *info);
426static bool rx_get_buf(struct slgt_info *info);
427
428static void tx_start(struct slgt_info *info);
429static void tx_stop(struct slgt_info *info);
430static void tx_set_idle(struct slgt_info *info);
431static unsigned int tbuf_bytes(struct slgt_info *info);
432static void reset_tbufs(struct slgt_info *info);
433static void tdma_reset(struct slgt_info *info);
434static bool tx_load(struct slgt_info *info, const u8 *buf, unsigned int count);
435
436static void get_gtsignals(struct slgt_info *info);
437static void set_gtsignals(struct slgt_info *info);
438static void set_rate(struct slgt_info *info, u32 data_rate);
439
440static void bh_transmit(struct slgt_info *info);
441static void isr_txeom(struct slgt_info *info, unsigned short status);
442
443static void tx_timeout(struct timer_list *t);
444static void rx_timeout(struct timer_list *t);
445
446/*
447 * ioctl handlers
448 */
449static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
450static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
451static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
452static int get_txidle(struct slgt_info *info, int __user *idle_mode);
453static int set_txidle(struct slgt_info *info, int idle_mode);
454static int tx_enable(struct slgt_info *info, int enable);
455static int tx_abort(struct slgt_info *info);
456static int rx_enable(struct slgt_info *info, int enable);
457static int modem_input_wait(struct slgt_info *info,int arg);
458static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
459static int get_interface(struct slgt_info *info, int __user *if_mode);
460static int set_interface(struct slgt_info *info, int if_mode);
461static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
462static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
463static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
464static int get_xsync(struct slgt_info *info, int __user *if_mode);
465static int set_xsync(struct slgt_info *info, int if_mode);
466static int get_xctrl(struct slgt_info *info, int __user *if_mode);
467static int set_xctrl(struct slgt_info *info, int if_mode);
468
469/*
470 * driver functions
471 */
472static void release_resources(struct slgt_info *info);
473
474/*
475 * DEBUG OUTPUT CODE
476 */
477#ifndef DBGINFO
478#define DBGINFO(fmt)
479#endif
480#ifndef DBGERR
481#define DBGERR(fmt)
482#endif
483#ifndef DBGBH
484#define DBGBH(fmt)
485#endif
486#ifndef DBGISR
487#define DBGISR(fmt)
488#endif
489
490#ifdef DBGDATA
491static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
492{
493 int i;
494 int linecount;
495 printk("%s %s data:\n",info->device_name, label);
496 while(count) {
497 linecount = (count > 16) ? 16 : count;
498 for(i=0; i < linecount; i++)
499 printk("%02X ",(unsigned char)data[i]);
500 for(;i<17;i++)
501 printk(" ");
502 for(i=0;i<linecount;i++) {
503 if (data[i]>=040 && data[i]<=0176)
504 printk("%c",data[i]);
505 else
506 printk(".");
507 }
508 printk("\n");
509 data += linecount;
510 count -= linecount;
511 }
512}
513#else
514#define DBGDATA(info, buf, size, label)
515#endif
516
517#ifdef DBGTBUF
518static void dump_tbufs(struct slgt_info *info)
519{
520 int i;
521 printk("tbuf_current=%d\n", info->tbuf_current);
522 for (i=0 ; i < info->tbuf_count ; i++) {
523 printk("%d: count=%04X status=%04X\n",
524 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
525 }
526}
527#else
528#define DBGTBUF(info)
529#endif
530
531#ifdef DBGRBUF
532static void dump_rbufs(struct slgt_info *info)
533{
534 int i;
535 printk("rbuf_current=%d\n", info->rbuf_current);
536 for (i=0 ; i < info->rbuf_count ; i++) {
537 printk("%d: count=%04X status=%04X\n",
538 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
539 }
540}
541#else
542#define DBGRBUF(info)
543#endif
544
545static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
546{
547#ifdef SANITY_CHECK
548 if (!info) {
549 printk("null struct slgt_info for (%s) in %s\n", devname, name);
550 return 1;
551 }
552#else
553 if (!info)
554 return 1;
555#endif
556 return 0;
557}
558
559/*
560 * line discipline callback wrappers
561 *
562 * The wrappers maintain line discipline references
563 * while calling into the line discipline.
564 *
565 * ldisc_receive_buf - pass receive data to line discipline
566 */
567static void ldisc_receive_buf(struct tty_struct *tty,
568 const __u8 *data, char *flags, int count)
569{
570 struct tty_ldisc *ld;
571 if (!tty)
572 return;
573 ld = tty_ldisc_ref(tty);
574 if (ld) {
575 if (ld->ops->receive_buf)
576 ld->ops->receive_buf(tty, data, flags, count);
577 tty_ldisc_deref(ld);
578 }
579}
580
581/* tty callbacks */
582
583static int open(struct tty_struct *tty, struct file *filp)
584{
585 struct slgt_info *info;
586 int retval, line;
587 unsigned long flags;
588
589 line = tty->index;
590 if (line >= slgt_device_count) {
591 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
592 return -ENODEV;
593 }
594
595 info = slgt_device_list;
596 while(info && info->line != line)
597 info = info->next_device;
598 if (sanity_check(info, tty->name, "open"))
599 return -ENODEV;
600 if (info->init_error) {
601 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
602 return -ENODEV;
603 }
604
605 tty->driver_data = info;
606 info->port.tty = tty;
607
608 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
609
610 mutex_lock(&info->port.mutex);
611
612 spin_lock_irqsave(&info->netlock, flags);
613 if (info->netcount) {
614 retval = -EBUSY;
615 spin_unlock_irqrestore(&info->netlock, flags);
616 mutex_unlock(&info->port.mutex);
617 goto cleanup;
618 }
619 info->port.count++;
620 spin_unlock_irqrestore(&info->netlock, flags);
621
622 if (info->port.count == 1) {
623 /* 1st open on this device, init hardware */
624 retval = startup(info);
625 if (retval < 0) {
626 mutex_unlock(&info->port.mutex);
627 goto cleanup;
628 }
629 }
630 mutex_unlock(&info->port.mutex);
631 retval = block_til_ready(tty, filp, info);
632 if (retval) {
633 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
634 goto cleanup;
635 }
636
637 retval = 0;
638
639cleanup:
640 if (retval) {
641 if (tty->count == 1)
642 info->port.tty = NULL; /* tty layer will release tty struct */
643 if(info->port.count)
644 info->port.count--;
645 }
646
647 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
648 return retval;
649}
650
651static void close(struct tty_struct *tty, struct file *filp)
652{
653 struct slgt_info *info = tty->driver_data;
654
655 if (sanity_check(info, tty->name, "close"))
656 return;
657 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
658
659 if (tty_port_close_start(&info->port, tty, filp) == 0)
660 goto cleanup;
661
662 mutex_lock(&info->port.mutex);
663 if (tty_port_initialized(&info->port))
664 wait_until_sent(tty, info->timeout);
665 flush_buffer(tty);
666 tty_ldisc_flush(tty);
667
668 shutdown(info);
669 mutex_unlock(&info->port.mutex);
670
671 tty_port_close_end(&info->port, tty);
672 info->port.tty = NULL;
673cleanup:
674 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
675}
676
677static void hangup(struct tty_struct *tty)
678{
679 struct slgt_info *info = tty->driver_data;
680 unsigned long flags;
681
682 if (sanity_check(info, tty->name, "hangup"))
683 return;
684 DBGINFO(("%s hangup\n", info->device_name));
685
686 flush_buffer(tty);
687
688 mutex_lock(&info->port.mutex);
689 shutdown(info);
690
691 spin_lock_irqsave(&info->port.lock, flags);
692 info->port.count = 0;
693 info->port.tty = NULL;
694 spin_unlock_irqrestore(&info->port.lock, flags);
695 tty_port_set_active(&info->port, false);
696 mutex_unlock(&info->port.mutex);
697
698 wake_up_interruptible(&info->port.open_wait);
699}
700
701static void set_termios(struct tty_struct *tty,
702 const struct ktermios *old_termios)
703{
704 struct slgt_info *info = tty->driver_data;
705 unsigned long flags;
706
707 DBGINFO(("%s set_termios\n", tty->driver->name));
708
709 change_params(info);
710
711 /* Handle transition to B0 status */
712 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
713 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
714 spin_lock_irqsave(&info->lock,flags);
715 set_gtsignals(info);
716 spin_unlock_irqrestore(&info->lock,flags);
717 }
718
719 /* Handle transition away from B0 status */
720 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
721 info->signals |= SerialSignal_DTR;
722 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
723 info->signals |= SerialSignal_RTS;
724 spin_lock_irqsave(&info->lock,flags);
725 set_gtsignals(info);
726 spin_unlock_irqrestore(&info->lock,flags);
727 }
728
729 /* Handle turning off CRTSCTS */
730 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
731 tty->hw_stopped = false;
732 tx_release(tty);
733 }
734}
735
736static void update_tx_timer(struct slgt_info *info)
737{
738 /*
739 * use worst case speed of 1200bps to calculate transmit timeout
740 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
741 */
742 if (info->params.mode == MGSL_MODE_HDLC) {
743 int timeout = (tbuf_bytes(info) * 7) + 1000;
744 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
745 }
746}
747
748static ssize_t write(struct tty_struct *tty, const u8 *buf, size_t count)
749{
750 int ret = 0;
751 struct slgt_info *info = tty->driver_data;
752 unsigned long flags;
753
754 if (sanity_check(info, tty->name, "write"))
755 return -EIO;
756
757 DBGINFO(("%s write count=%zu\n", info->device_name, count));
758
759 if (!info->tx_buf || (count > info->max_frame_size))
760 return -EIO;
761
762 if (!count || tty->flow.stopped || tty->hw_stopped)
763 return 0;
764
765 spin_lock_irqsave(&info->lock, flags);
766
767 if (info->tx_count) {
768 /* send accumulated data from send_char() */
769 if (!tx_load(info, info->tx_buf, info->tx_count))
770 goto cleanup;
771 info->tx_count = 0;
772 }
773
774 if (tx_load(info, buf, count))
775 ret = count;
776
777cleanup:
778 spin_unlock_irqrestore(&info->lock, flags);
779 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
780 return ret;
781}
782
783static int put_char(struct tty_struct *tty, u8 ch)
784{
785 struct slgt_info *info = tty->driver_data;
786 unsigned long flags;
787 int ret = 0;
788
789 if (sanity_check(info, tty->name, "put_char"))
790 return 0;
791 DBGINFO(("%s put_char(%u)\n", info->device_name, ch));
792 if (!info->tx_buf)
793 return 0;
794 spin_lock_irqsave(&info->lock,flags);
795 if (info->tx_count < info->max_frame_size) {
796 info->tx_buf[info->tx_count++] = ch;
797 ret = 1;
798 }
799 spin_unlock_irqrestore(&info->lock,flags);
800 return ret;
801}
802
803static void send_xchar(struct tty_struct *tty, char ch)
804{
805 struct slgt_info *info = tty->driver_data;
806 unsigned long flags;
807
808 if (sanity_check(info, tty->name, "send_xchar"))
809 return;
810 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
811 info->x_char = ch;
812 if (ch) {
813 spin_lock_irqsave(&info->lock,flags);
814 if (!info->tx_enabled)
815 tx_start(info);
816 spin_unlock_irqrestore(&info->lock,flags);
817 }
818}
819
820static void wait_until_sent(struct tty_struct *tty, int timeout)
821{
822 struct slgt_info *info = tty->driver_data;
823 unsigned long orig_jiffies, char_time;
824
825 if (!info )
826 return;
827 if (sanity_check(info, tty->name, "wait_until_sent"))
828 return;
829 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
830 if (!tty_port_initialized(&info->port))
831 goto exit;
832
833 orig_jiffies = jiffies;
834
835 /* Set check interval to 1/5 of estimated time to
836 * send a character, and make it at least 1. The check
837 * interval should also be less than the timeout.
838 * Note: use tight timings here to satisfy the NIST-PCTS.
839 */
840
841 if (info->params.data_rate) {
842 char_time = info->timeout/(32 * 5);
843 if (!char_time)
844 char_time++;
845 } else
846 char_time = 1;
847
848 if (timeout)
849 char_time = min_t(unsigned long, char_time, timeout);
850
851 while (info->tx_active) {
852 msleep_interruptible(jiffies_to_msecs(char_time));
853 if (signal_pending(current))
854 break;
855 if (timeout && time_after(jiffies, orig_jiffies + timeout))
856 break;
857 }
858exit:
859 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
860}
861
862static unsigned int write_room(struct tty_struct *tty)
863{
864 struct slgt_info *info = tty->driver_data;
865 unsigned int ret;
866
867 if (sanity_check(info, tty->name, "write_room"))
868 return 0;
869 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
870 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
871 return ret;
872}
873
874static void flush_chars(struct tty_struct *tty)
875{
876 struct slgt_info *info = tty->driver_data;
877 unsigned long flags;
878
879 if (sanity_check(info, tty->name, "flush_chars"))
880 return;
881 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
882
883 if (info->tx_count <= 0 || tty->flow.stopped ||
884 tty->hw_stopped || !info->tx_buf)
885 return;
886
887 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
888
889 spin_lock_irqsave(&info->lock,flags);
890 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
891 info->tx_count = 0;
892 spin_unlock_irqrestore(&info->lock,flags);
893}
894
895static void flush_buffer(struct tty_struct *tty)
896{
897 struct slgt_info *info = tty->driver_data;
898 unsigned long flags;
899
900 if (sanity_check(info, tty->name, "flush_buffer"))
901 return;
902 DBGINFO(("%s flush_buffer\n", info->device_name));
903
904 spin_lock_irqsave(&info->lock, flags);
905 info->tx_count = 0;
906 spin_unlock_irqrestore(&info->lock, flags);
907
908 tty_wakeup(tty);
909}
910
911/*
912 * throttle (stop) transmitter
913 */
914static void tx_hold(struct tty_struct *tty)
915{
916 struct slgt_info *info = tty->driver_data;
917 unsigned long flags;
918
919 if (sanity_check(info, tty->name, "tx_hold"))
920 return;
921 DBGINFO(("%s tx_hold\n", info->device_name));
922 spin_lock_irqsave(&info->lock,flags);
923 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
924 tx_stop(info);
925 spin_unlock_irqrestore(&info->lock,flags);
926}
927
928/*
929 * release (start) transmitter
930 */
931static void tx_release(struct tty_struct *tty)
932{
933 struct slgt_info *info = tty->driver_data;
934 unsigned long flags;
935
936 if (sanity_check(info, tty->name, "tx_release"))
937 return;
938 DBGINFO(("%s tx_release\n", info->device_name));
939 spin_lock_irqsave(&info->lock, flags);
940 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
941 info->tx_count = 0;
942 spin_unlock_irqrestore(&info->lock, flags);
943}
944
945/*
946 * Service an IOCTL request
947 *
948 * Arguments
949 *
950 * tty pointer to tty instance data
951 * cmd IOCTL command code
952 * arg command argument/context
953 *
954 * Return 0 if success, otherwise error code
955 */
956static int ioctl(struct tty_struct *tty,
957 unsigned int cmd, unsigned long arg)
958{
959 struct slgt_info *info = tty->driver_data;
960 void __user *argp = (void __user *)arg;
961 int ret;
962
963 if (sanity_check(info, tty->name, "ioctl"))
964 return -ENODEV;
965 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
966
967 if (cmd != TIOCMIWAIT) {
968 if (tty_io_error(tty))
969 return -EIO;
970 }
971
972 switch (cmd) {
973 case MGSL_IOCWAITEVENT:
974 return wait_mgsl_event(info, argp);
975 case TIOCMIWAIT:
976 return modem_input_wait(info,(int)arg);
977 case MGSL_IOCSGPIO:
978 return set_gpio(info, argp);
979 case MGSL_IOCGGPIO:
980 return get_gpio(info, argp);
981 case MGSL_IOCWAITGPIO:
982 return wait_gpio(info, argp);
983 case MGSL_IOCGXSYNC:
984 return get_xsync(info, argp);
985 case MGSL_IOCSXSYNC:
986 return set_xsync(info, (int)arg);
987 case MGSL_IOCGXCTRL:
988 return get_xctrl(info, argp);
989 case MGSL_IOCSXCTRL:
990 return set_xctrl(info, (int)arg);
991 }
992 mutex_lock(&info->port.mutex);
993 switch (cmd) {
994 case MGSL_IOCGPARAMS:
995 ret = get_params(info, argp);
996 break;
997 case MGSL_IOCSPARAMS:
998 ret = set_params(info, argp);
999 break;
1000 case MGSL_IOCGTXIDLE:
1001 ret = get_txidle(info, argp);
1002 break;
1003 case MGSL_IOCSTXIDLE:
1004 ret = set_txidle(info, (int)arg);
1005 break;
1006 case MGSL_IOCTXENABLE:
1007 ret = tx_enable(info, (int)arg);
1008 break;
1009 case MGSL_IOCRXENABLE:
1010 ret = rx_enable(info, (int)arg);
1011 break;
1012 case MGSL_IOCTXABORT:
1013 ret = tx_abort(info);
1014 break;
1015 case MGSL_IOCGSTATS:
1016 ret = get_stats(info, argp);
1017 break;
1018 case MGSL_IOCGIF:
1019 ret = get_interface(info, argp);
1020 break;
1021 case MGSL_IOCSIF:
1022 ret = set_interface(info,(int)arg);
1023 break;
1024 default:
1025 ret = -ENOIOCTLCMD;
1026 }
1027 mutex_unlock(&info->port.mutex);
1028 return ret;
1029}
1030
1031static int get_icount(struct tty_struct *tty,
1032 struct serial_icounter_struct *icount)
1033
1034{
1035 struct slgt_info *info = tty->driver_data;
1036 struct mgsl_icount cnow; /* kernel counter temps */
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&info->lock,flags);
1040 cnow = info->icount;
1041 spin_unlock_irqrestore(&info->lock,flags);
1042
1043 icount->cts = cnow.cts;
1044 icount->dsr = cnow.dsr;
1045 icount->rng = cnow.rng;
1046 icount->dcd = cnow.dcd;
1047 icount->rx = cnow.rx;
1048 icount->tx = cnow.tx;
1049 icount->frame = cnow.frame;
1050 icount->overrun = cnow.overrun;
1051 icount->parity = cnow.parity;
1052 icount->brk = cnow.brk;
1053 icount->buf_overrun = cnow.buf_overrun;
1054
1055 return 0;
1056}
1057
1058/*
1059 * support for 32 bit ioctl calls on 64 bit systems
1060 */
1061#ifdef CONFIG_COMPAT
1062static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1063{
1064 struct MGSL_PARAMS32 tmp_params;
1065
1066 DBGINFO(("%s get_params32\n", info->device_name));
1067 memset(&tmp_params, 0, sizeof(tmp_params));
1068 tmp_params.mode = (compat_ulong_t)info->params.mode;
1069 tmp_params.loopback = info->params.loopback;
1070 tmp_params.flags = info->params.flags;
1071 tmp_params.encoding = info->params.encoding;
1072 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1073 tmp_params.addr_filter = info->params.addr_filter;
1074 tmp_params.crc_type = info->params.crc_type;
1075 tmp_params.preamble_length = info->params.preamble_length;
1076 tmp_params.preamble = info->params.preamble;
1077 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1078 tmp_params.data_bits = info->params.data_bits;
1079 tmp_params.stop_bits = info->params.stop_bits;
1080 tmp_params.parity = info->params.parity;
1081 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1082 return -EFAULT;
1083 return 0;
1084}
1085
1086static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1087{
1088 struct MGSL_PARAMS32 tmp_params;
1089 unsigned long flags;
1090
1091 DBGINFO(("%s set_params32\n", info->device_name));
1092 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1093 return -EFAULT;
1094
1095 spin_lock_irqsave(&info->lock, flags);
1096 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1097 info->base_clock = tmp_params.clock_speed;
1098 } else {
1099 info->params.mode = tmp_params.mode;
1100 info->params.loopback = tmp_params.loopback;
1101 info->params.flags = tmp_params.flags;
1102 info->params.encoding = tmp_params.encoding;
1103 info->params.clock_speed = tmp_params.clock_speed;
1104 info->params.addr_filter = tmp_params.addr_filter;
1105 info->params.crc_type = tmp_params.crc_type;
1106 info->params.preamble_length = tmp_params.preamble_length;
1107 info->params.preamble = tmp_params.preamble;
1108 info->params.data_rate = tmp_params.data_rate;
1109 info->params.data_bits = tmp_params.data_bits;
1110 info->params.stop_bits = tmp_params.stop_bits;
1111 info->params.parity = tmp_params.parity;
1112 }
1113 spin_unlock_irqrestore(&info->lock, flags);
1114
1115 program_hw(info);
1116
1117 return 0;
1118}
1119
1120static long slgt_compat_ioctl(struct tty_struct *tty,
1121 unsigned int cmd, unsigned long arg)
1122{
1123 struct slgt_info *info = tty->driver_data;
1124 int rc;
1125
1126 if (sanity_check(info, tty->name, "compat_ioctl"))
1127 return -ENODEV;
1128 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1129
1130 switch (cmd) {
1131 case MGSL_IOCSPARAMS32:
1132 rc = set_params32(info, compat_ptr(arg));
1133 break;
1134
1135 case MGSL_IOCGPARAMS32:
1136 rc = get_params32(info, compat_ptr(arg));
1137 break;
1138
1139 case MGSL_IOCGPARAMS:
1140 case MGSL_IOCSPARAMS:
1141 case MGSL_IOCGTXIDLE:
1142 case MGSL_IOCGSTATS:
1143 case MGSL_IOCWAITEVENT:
1144 case MGSL_IOCGIF:
1145 case MGSL_IOCSGPIO:
1146 case MGSL_IOCGGPIO:
1147 case MGSL_IOCWAITGPIO:
1148 case MGSL_IOCGXSYNC:
1149 case MGSL_IOCGXCTRL:
1150 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1151 break;
1152 default:
1153 rc = ioctl(tty, cmd, arg);
1154 }
1155 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1156 return rc;
1157}
1158#else
1159#define slgt_compat_ioctl NULL
1160#endif /* ifdef CONFIG_COMPAT */
1161
1162/*
1163 * proc fs support
1164 */
1165static inline void line_info(struct seq_file *m, struct slgt_info *info)
1166{
1167 char stat_buf[30];
1168 unsigned long flags;
1169
1170 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1171 info->device_name, info->phys_reg_addr,
1172 info->irq_level, info->max_frame_size);
1173
1174 /* output current serial signal states */
1175 spin_lock_irqsave(&info->lock,flags);
1176 get_gtsignals(info);
1177 spin_unlock_irqrestore(&info->lock,flags);
1178
1179 stat_buf[0] = 0;
1180 stat_buf[1] = 0;
1181 if (info->signals & SerialSignal_RTS)
1182 strcat(stat_buf, "|RTS");
1183 if (info->signals & SerialSignal_CTS)
1184 strcat(stat_buf, "|CTS");
1185 if (info->signals & SerialSignal_DTR)
1186 strcat(stat_buf, "|DTR");
1187 if (info->signals & SerialSignal_DSR)
1188 strcat(stat_buf, "|DSR");
1189 if (info->signals & SerialSignal_DCD)
1190 strcat(stat_buf, "|CD");
1191 if (info->signals & SerialSignal_RI)
1192 strcat(stat_buf, "|RI");
1193
1194 if (info->params.mode != MGSL_MODE_ASYNC) {
1195 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1196 info->icount.txok, info->icount.rxok);
1197 if (info->icount.txunder)
1198 seq_printf(m, " txunder:%d", info->icount.txunder);
1199 if (info->icount.txabort)
1200 seq_printf(m, " txabort:%d", info->icount.txabort);
1201 if (info->icount.rxshort)
1202 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1203 if (info->icount.rxlong)
1204 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1205 if (info->icount.rxover)
1206 seq_printf(m, " rxover:%d", info->icount.rxover);
1207 if (info->icount.rxcrc)
1208 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1209 } else {
1210 seq_printf(m, "\tASYNC tx:%d rx:%d",
1211 info->icount.tx, info->icount.rx);
1212 if (info->icount.frame)
1213 seq_printf(m, " fe:%d", info->icount.frame);
1214 if (info->icount.parity)
1215 seq_printf(m, " pe:%d", info->icount.parity);
1216 if (info->icount.brk)
1217 seq_printf(m, " brk:%d", info->icount.brk);
1218 if (info->icount.overrun)
1219 seq_printf(m, " oe:%d", info->icount.overrun);
1220 }
1221
1222 /* Append serial signal status to end */
1223 seq_printf(m, " %s\n", stat_buf+1);
1224
1225 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1226 info->tx_active,info->bh_requested,info->bh_running,
1227 info->pending_bh);
1228}
1229
1230/* Called to print information about devices
1231 */
1232static int synclink_gt_proc_show(struct seq_file *m, void *v)
1233{
1234 struct slgt_info *info;
1235
1236 seq_puts(m, "synclink_gt driver\n");
1237
1238 info = slgt_device_list;
1239 while( info ) {
1240 line_info(m, info);
1241 info = info->next_device;
1242 }
1243 return 0;
1244}
1245
1246/*
1247 * return count of bytes in transmit buffer
1248 */
1249static unsigned int chars_in_buffer(struct tty_struct *tty)
1250{
1251 struct slgt_info *info = tty->driver_data;
1252 unsigned int count;
1253 if (sanity_check(info, tty->name, "chars_in_buffer"))
1254 return 0;
1255 count = tbuf_bytes(info);
1256 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1257 return count;
1258}
1259
1260/*
1261 * signal remote device to throttle send data (our receive data)
1262 */
1263static void throttle(struct tty_struct * tty)
1264{
1265 struct slgt_info *info = tty->driver_data;
1266 unsigned long flags;
1267
1268 if (sanity_check(info, tty->name, "throttle"))
1269 return;
1270 DBGINFO(("%s throttle\n", info->device_name));
1271 if (I_IXOFF(tty))
1272 send_xchar(tty, STOP_CHAR(tty));
1273 if (C_CRTSCTS(tty)) {
1274 spin_lock_irqsave(&info->lock,flags);
1275 info->signals &= ~SerialSignal_RTS;
1276 set_gtsignals(info);
1277 spin_unlock_irqrestore(&info->lock,flags);
1278 }
1279}
1280
1281/*
1282 * signal remote device to stop throttling send data (our receive data)
1283 */
1284static void unthrottle(struct tty_struct * tty)
1285{
1286 struct slgt_info *info = tty->driver_data;
1287 unsigned long flags;
1288
1289 if (sanity_check(info, tty->name, "unthrottle"))
1290 return;
1291 DBGINFO(("%s unthrottle\n", info->device_name));
1292 if (I_IXOFF(tty)) {
1293 if (info->x_char)
1294 info->x_char = 0;
1295 else
1296 send_xchar(tty, START_CHAR(tty));
1297 }
1298 if (C_CRTSCTS(tty)) {
1299 spin_lock_irqsave(&info->lock,flags);
1300 info->signals |= SerialSignal_RTS;
1301 set_gtsignals(info);
1302 spin_unlock_irqrestore(&info->lock,flags);
1303 }
1304}
1305
1306/*
1307 * set or clear transmit break condition
1308 * break_state -1=set break condition, 0=clear
1309 */
1310static int set_break(struct tty_struct *tty, int break_state)
1311{
1312 struct slgt_info *info = tty->driver_data;
1313 unsigned short value;
1314 unsigned long flags;
1315
1316 if (sanity_check(info, tty->name, "set_break"))
1317 return -EINVAL;
1318 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1319
1320 spin_lock_irqsave(&info->lock,flags);
1321 value = rd_reg16(info, TCR);
1322 if (break_state == -1)
1323 value |= BIT6;
1324 else
1325 value &= ~BIT6;
1326 wr_reg16(info, TCR, value);
1327 spin_unlock_irqrestore(&info->lock,flags);
1328 return 0;
1329}
1330
1331#if SYNCLINK_GENERIC_HDLC
1332
1333/**
1334 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1335 * @dev: pointer to network device structure
1336 * @encoding: serial encoding setting
1337 * @parity: FCS setting
1338 *
1339 * Set encoding and frame check sequence (FCS) options.
1340 *
1341 * Return: 0 if success, otherwise error code
1342 */
1343static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1344 unsigned short parity)
1345{
1346 struct slgt_info *info = dev_to_port(dev);
1347 unsigned char new_encoding;
1348 unsigned short new_crctype;
1349
1350 /* return error if TTY interface open */
1351 if (info->port.count)
1352 return -EBUSY;
1353
1354 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1355
1356 switch (encoding)
1357 {
1358 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1359 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1360 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1361 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1362 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1363 default: return -EINVAL;
1364 }
1365
1366 switch (parity)
1367 {
1368 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1369 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1370 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1371 default: return -EINVAL;
1372 }
1373
1374 info->params.encoding = new_encoding;
1375 info->params.crc_type = new_crctype;
1376
1377 /* if network interface up, reprogram hardware */
1378 if (info->netcount)
1379 program_hw(info);
1380
1381 return 0;
1382}
1383
1384/**
1385 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1386 * @skb: socket buffer containing HDLC frame
1387 * @dev: pointer to network device structure
1388 */
1389static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1390 struct net_device *dev)
1391{
1392 struct slgt_info *info = dev_to_port(dev);
1393 unsigned long flags;
1394
1395 DBGINFO(("%s hdlc_xmit\n", dev->name));
1396
1397 if (!skb->len)
1398 return NETDEV_TX_OK;
1399
1400 /* stop sending until this frame completes */
1401 netif_stop_queue(dev);
1402
1403 /* update network statistics */
1404 dev->stats.tx_packets++;
1405 dev->stats.tx_bytes += skb->len;
1406
1407 /* save start time for transmit timeout detection */
1408 netif_trans_update(dev);
1409
1410 spin_lock_irqsave(&info->lock, flags);
1411 tx_load(info, skb->data, skb->len);
1412 spin_unlock_irqrestore(&info->lock, flags);
1413
1414 /* done with socket buffer, so free it */
1415 dev_kfree_skb(skb);
1416
1417 return NETDEV_TX_OK;
1418}
1419
1420/**
1421 * hdlcdev_open - called by network layer when interface enabled
1422 * @dev: pointer to network device structure
1423 *
1424 * Claim resources and initialize hardware.
1425 *
1426 * Return: 0 if success, otherwise error code
1427 */
1428static int hdlcdev_open(struct net_device *dev)
1429{
1430 struct slgt_info *info = dev_to_port(dev);
1431 int rc;
1432 unsigned long flags;
1433
1434 DBGINFO(("%s hdlcdev_open\n", dev->name));
1435
1436 /* arbitrate between network and tty opens */
1437 spin_lock_irqsave(&info->netlock, flags);
1438 if (info->port.count != 0 || info->netcount != 0) {
1439 DBGINFO(("%s hdlc_open busy\n", dev->name));
1440 spin_unlock_irqrestore(&info->netlock, flags);
1441 return -EBUSY;
1442 }
1443 info->netcount=1;
1444 spin_unlock_irqrestore(&info->netlock, flags);
1445
1446 /* claim resources and init adapter */
1447 if ((rc = startup(info)) != 0) {
1448 spin_lock_irqsave(&info->netlock, flags);
1449 info->netcount=0;
1450 spin_unlock_irqrestore(&info->netlock, flags);
1451 return rc;
1452 }
1453
1454 /* generic HDLC layer open processing */
1455 rc = hdlc_open(dev);
1456 if (rc) {
1457 shutdown(info);
1458 spin_lock_irqsave(&info->netlock, flags);
1459 info->netcount = 0;
1460 spin_unlock_irqrestore(&info->netlock, flags);
1461 return rc;
1462 }
1463
1464 /* assert RTS and DTR, apply hardware settings */
1465 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1466 program_hw(info);
1467
1468 /* enable network layer transmit */
1469 netif_trans_update(dev);
1470 netif_start_queue(dev);
1471
1472 /* inform generic HDLC layer of current DCD status */
1473 spin_lock_irqsave(&info->lock, flags);
1474 get_gtsignals(info);
1475 spin_unlock_irqrestore(&info->lock, flags);
1476 if (info->signals & SerialSignal_DCD)
1477 netif_carrier_on(dev);
1478 else
1479 netif_carrier_off(dev);
1480 return 0;
1481}
1482
1483/**
1484 * hdlcdev_close - called by network layer when interface is disabled
1485 * @dev: pointer to network device structure
1486 *
1487 * Shutdown hardware and release resources.
1488 *
1489 * Return: 0 if success, otherwise error code
1490 */
1491static int hdlcdev_close(struct net_device *dev)
1492{
1493 struct slgt_info *info = dev_to_port(dev);
1494 unsigned long flags;
1495
1496 DBGINFO(("%s hdlcdev_close\n", dev->name));
1497
1498 netif_stop_queue(dev);
1499
1500 /* shutdown adapter and release resources */
1501 shutdown(info);
1502
1503 hdlc_close(dev);
1504
1505 spin_lock_irqsave(&info->netlock, flags);
1506 info->netcount=0;
1507 spin_unlock_irqrestore(&info->netlock, flags);
1508
1509 return 0;
1510}
1511
1512/**
1513 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1514 * @dev: pointer to network device structure
1515 * @ifr: pointer to network interface request structure
1516 * @cmd: IOCTL command code
1517 *
1518 * Return: 0 if success, otherwise error code
1519 */
1520static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1521{
1522 const size_t size = sizeof(sync_serial_settings);
1523 sync_serial_settings new_line;
1524 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1525 struct slgt_info *info = dev_to_port(dev);
1526 unsigned int flags;
1527
1528 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1529
1530 /* return error if TTY interface open */
1531 if (info->port.count)
1532 return -EBUSY;
1533
1534 memset(&new_line, 0, sizeof(new_line));
1535
1536 switch (ifs->type) {
1537 case IF_GET_IFACE: /* return current sync_serial_settings */
1538
1539 ifs->type = IF_IFACE_SYNC_SERIAL;
1540 if (ifs->size < size) {
1541 ifs->size = size; /* data size wanted */
1542 return -ENOBUFS;
1543 }
1544
1545 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1546 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1547 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1548 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1549
1550 switch (flags){
1551 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1552 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1553 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1554 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1555 default: new_line.clock_type = CLOCK_DEFAULT;
1556 }
1557
1558 new_line.clock_rate = info->params.clock_speed;
1559 new_line.loopback = info->params.loopback ? 1:0;
1560
1561 if (copy_to_user(line, &new_line, size))
1562 return -EFAULT;
1563 return 0;
1564
1565 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1566
1567 if(!capable(CAP_NET_ADMIN))
1568 return -EPERM;
1569 if (copy_from_user(&new_line, line, size))
1570 return -EFAULT;
1571
1572 switch (new_line.clock_type)
1573 {
1574 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1575 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1576 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1577 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1578 case CLOCK_DEFAULT: flags = info->params.flags &
1579 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1580 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1581 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1582 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1583 default: return -EINVAL;
1584 }
1585
1586 if (new_line.loopback != 0 && new_line.loopback != 1)
1587 return -EINVAL;
1588
1589 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1590 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1591 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1592 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1593 info->params.flags |= flags;
1594
1595 info->params.loopback = new_line.loopback;
1596
1597 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1598 info->params.clock_speed = new_line.clock_rate;
1599 else
1600 info->params.clock_speed = 0;
1601
1602 /* if network interface up, reprogram hardware */
1603 if (info->netcount)
1604 program_hw(info);
1605 return 0;
1606
1607 default:
1608 return hdlc_ioctl(dev, ifs);
1609 }
1610}
1611
1612/**
1613 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1614 * @dev: pointer to network device structure
1615 * @txqueue: unused
1616 */
1617static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1618{
1619 struct slgt_info *info = dev_to_port(dev);
1620 unsigned long flags;
1621
1622 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1623
1624 dev->stats.tx_errors++;
1625 dev->stats.tx_aborted_errors++;
1626
1627 spin_lock_irqsave(&info->lock,flags);
1628 tx_stop(info);
1629 spin_unlock_irqrestore(&info->lock,flags);
1630
1631 netif_wake_queue(dev);
1632}
1633
1634/**
1635 * hdlcdev_tx_done - called by device driver when transmit completes
1636 * @info: pointer to device instance information
1637 *
1638 * Reenable network layer transmit if stopped.
1639 */
1640static void hdlcdev_tx_done(struct slgt_info *info)
1641{
1642 if (netif_queue_stopped(info->netdev))
1643 netif_wake_queue(info->netdev);
1644}
1645
1646/**
1647 * hdlcdev_rx - called by device driver when frame received
1648 * @info: pointer to device instance information
1649 * @buf: pointer to buffer contianing frame data
1650 * @size: count of data bytes in buf
1651 *
1652 * Pass frame to network layer.
1653 */
1654static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1655{
1656 struct sk_buff *skb = dev_alloc_skb(size);
1657 struct net_device *dev = info->netdev;
1658
1659 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1660
1661 if (skb == NULL) {
1662 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1663 dev->stats.rx_dropped++;
1664 return;
1665 }
1666
1667 skb_put_data(skb, buf, size);
1668
1669 skb->protocol = hdlc_type_trans(skb, dev);
1670
1671 dev->stats.rx_packets++;
1672 dev->stats.rx_bytes += size;
1673
1674 netif_rx(skb);
1675}
1676
1677static const struct net_device_ops hdlcdev_ops = {
1678 .ndo_open = hdlcdev_open,
1679 .ndo_stop = hdlcdev_close,
1680 .ndo_start_xmit = hdlc_start_xmit,
1681 .ndo_siocwandev = hdlcdev_ioctl,
1682 .ndo_tx_timeout = hdlcdev_tx_timeout,
1683};
1684
1685/**
1686 * hdlcdev_init - called by device driver when adding device instance
1687 * @info: pointer to device instance information
1688 *
1689 * Do generic HDLC initialization.
1690 *
1691 * Return: 0 if success, otherwise error code
1692 */
1693static int hdlcdev_init(struct slgt_info *info)
1694{
1695 int rc;
1696 struct net_device *dev;
1697 hdlc_device *hdlc;
1698
1699 /* allocate and initialize network and HDLC layer objects */
1700
1701 dev = alloc_hdlcdev(info);
1702 if (!dev) {
1703 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1704 return -ENOMEM;
1705 }
1706
1707 /* for network layer reporting purposes only */
1708 dev->mem_start = info->phys_reg_addr;
1709 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1710 dev->irq = info->irq_level;
1711
1712 /* network layer callbacks and settings */
1713 dev->netdev_ops = &hdlcdev_ops;
1714 dev->watchdog_timeo = 10 * HZ;
1715 dev->tx_queue_len = 50;
1716
1717 /* generic HDLC layer callbacks and settings */
1718 hdlc = dev_to_hdlc(dev);
1719 hdlc->attach = hdlcdev_attach;
1720 hdlc->xmit = hdlcdev_xmit;
1721
1722 /* register objects with HDLC layer */
1723 rc = register_hdlc_device(dev);
1724 if (rc) {
1725 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1726 free_netdev(dev);
1727 return rc;
1728 }
1729
1730 info->netdev = dev;
1731 return 0;
1732}
1733
1734/**
1735 * hdlcdev_exit - called by device driver when removing device instance
1736 * @info: pointer to device instance information
1737 *
1738 * Do generic HDLC cleanup.
1739 */
1740static void hdlcdev_exit(struct slgt_info *info)
1741{
1742 if (!info->netdev)
1743 return;
1744 unregister_hdlc_device(info->netdev);
1745 free_netdev(info->netdev);
1746 info->netdev = NULL;
1747}
1748
1749#endif /* ifdef CONFIG_HDLC */
1750
1751/*
1752 * get async data from rx DMA buffers
1753 */
1754static void rx_async(struct slgt_info *info)
1755{
1756 struct mgsl_icount *icount = &info->icount;
1757 unsigned int start, end;
1758 unsigned char *p;
1759 unsigned char status;
1760 struct slgt_desc *bufs = info->rbufs;
1761 int i, count;
1762 int chars = 0;
1763 int stat;
1764 unsigned char ch;
1765
1766 start = end = info->rbuf_current;
1767
1768 while(desc_complete(bufs[end])) {
1769 count = desc_count(bufs[end]) - info->rbuf_index;
1770 p = bufs[end].buf + info->rbuf_index;
1771
1772 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1773 DBGDATA(info, p, count, "rx");
1774
1775 for(i=0 ; i < count; i+=2, p+=2) {
1776 ch = *p;
1777 icount->rx++;
1778
1779 stat = 0;
1780
1781 status = *(p + 1) & (BIT1 + BIT0);
1782 if (status) {
1783 if (status & BIT1)
1784 icount->parity++;
1785 else if (status & BIT0)
1786 icount->frame++;
1787 /* discard char if tty control flags say so */
1788 if (status & info->ignore_status_mask)
1789 continue;
1790 if (status & BIT1)
1791 stat = TTY_PARITY;
1792 else if (status & BIT0)
1793 stat = TTY_FRAME;
1794 }
1795 tty_insert_flip_char(&info->port, ch, stat);
1796 chars++;
1797 }
1798
1799 if (i < count) {
1800 /* receive buffer not completed */
1801 info->rbuf_index += i;
1802 mod_timer(&info->rx_timer, jiffies + 1);
1803 break;
1804 }
1805
1806 info->rbuf_index = 0;
1807 free_rbufs(info, end, end);
1808
1809 if (++end == info->rbuf_count)
1810 end = 0;
1811
1812 /* if entire list searched then no frame available */
1813 if (end == start)
1814 break;
1815 }
1816
1817 if (chars)
1818 tty_flip_buffer_push(&info->port);
1819}
1820
1821/*
1822 * return next bottom half action to perform
1823 */
1824static int bh_action(struct slgt_info *info)
1825{
1826 unsigned long flags;
1827 int rc;
1828
1829 spin_lock_irqsave(&info->lock,flags);
1830
1831 if (info->pending_bh & BH_RECEIVE) {
1832 info->pending_bh &= ~BH_RECEIVE;
1833 rc = BH_RECEIVE;
1834 } else if (info->pending_bh & BH_TRANSMIT) {
1835 info->pending_bh &= ~BH_TRANSMIT;
1836 rc = BH_TRANSMIT;
1837 } else if (info->pending_bh & BH_STATUS) {
1838 info->pending_bh &= ~BH_STATUS;
1839 rc = BH_STATUS;
1840 } else {
1841 /* Mark BH routine as complete */
1842 info->bh_running = false;
1843 info->bh_requested = false;
1844 rc = 0;
1845 }
1846
1847 spin_unlock_irqrestore(&info->lock,flags);
1848
1849 return rc;
1850}
1851
1852/*
1853 * perform bottom half processing
1854 */
1855static void bh_handler(struct work_struct *work)
1856{
1857 struct slgt_info *info = container_of(work, struct slgt_info, task);
1858 int action;
1859
1860 info->bh_running = true;
1861
1862 while((action = bh_action(info))) {
1863 switch (action) {
1864 case BH_RECEIVE:
1865 DBGBH(("%s bh receive\n", info->device_name));
1866 switch(info->params.mode) {
1867 case MGSL_MODE_ASYNC:
1868 rx_async(info);
1869 break;
1870 case MGSL_MODE_HDLC:
1871 while(rx_get_frame(info));
1872 break;
1873 case MGSL_MODE_RAW:
1874 case MGSL_MODE_MONOSYNC:
1875 case MGSL_MODE_BISYNC:
1876 case MGSL_MODE_XSYNC:
1877 while(rx_get_buf(info));
1878 break;
1879 }
1880 /* restart receiver if rx DMA buffers exhausted */
1881 if (info->rx_restart)
1882 rx_start(info);
1883 break;
1884 case BH_TRANSMIT:
1885 bh_transmit(info);
1886 break;
1887 case BH_STATUS:
1888 DBGBH(("%s bh status\n", info->device_name));
1889 info->ri_chkcount = 0;
1890 info->dsr_chkcount = 0;
1891 info->dcd_chkcount = 0;
1892 info->cts_chkcount = 0;
1893 break;
1894 default:
1895 DBGBH(("%s unknown action\n", info->device_name));
1896 break;
1897 }
1898 }
1899 DBGBH(("%s bh_handler exit\n", info->device_name));
1900}
1901
1902static void bh_transmit(struct slgt_info *info)
1903{
1904 struct tty_struct *tty = info->port.tty;
1905
1906 DBGBH(("%s bh_transmit\n", info->device_name));
1907 if (tty)
1908 tty_wakeup(tty);
1909}
1910
1911static void dsr_change(struct slgt_info *info, unsigned short status)
1912{
1913 if (status & BIT3) {
1914 info->signals |= SerialSignal_DSR;
1915 info->input_signal_events.dsr_up++;
1916 } else {
1917 info->signals &= ~SerialSignal_DSR;
1918 info->input_signal_events.dsr_down++;
1919 }
1920 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1921 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1922 slgt_irq_off(info, IRQ_DSR);
1923 return;
1924 }
1925 info->icount.dsr++;
1926 wake_up_interruptible(&info->status_event_wait_q);
1927 wake_up_interruptible(&info->event_wait_q);
1928 info->pending_bh |= BH_STATUS;
1929}
1930
1931static void cts_change(struct slgt_info *info, unsigned short status)
1932{
1933 if (status & BIT2) {
1934 info->signals |= SerialSignal_CTS;
1935 info->input_signal_events.cts_up++;
1936 } else {
1937 info->signals &= ~SerialSignal_CTS;
1938 info->input_signal_events.cts_down++;
1939 }
1940 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1941 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1942 slgt_irq_off(info, IRQ_CTS);
1943 return;
1944 }
1945 info->icount.cts++;
1946 wake_up_interruptible(&info->status_event_wait_q);
1947 wake_up_interruptible(&info->event_wait_q);
1948 info->pending_bh |= BH_STATUS;
1949
1950 if (tty_port_cts_enabled(&info->port)) {
1951 if (info->port.tty) {
1952 if (info->port.tty->hw_stopped) {
1953 if (info->signals & SerialSignal_CTS) {
1954 info->port.tty->hw_stopped = false;
1955 info->pending_bh |= BH_TRANSMIT;
1956 return;
1957 }
1958 } else {
1959 if (!(info->signals & SerialSignal_CTS))
1960 info->port.tty->hw_stopped = true;
1961 }
1962 }
1963 }
1964}
1965
1966static void dcd_change(struct slgt_info *info, unsigned short status)
1967{
1968 if (status & BIT1) {
1969 info->signals |= SerialSignal_DCD;
1970 info->input_signal_events.dcd_up++;
1971 } else {
1972 info->signals &= ~SerialSignal_DCD;
1973 info->input_signal_events.dcd_down++;
1974 }
1975 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1976 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1977 slgt_irq_off(info, IRQ_DCD);
1978 return;
1979 }
1980 info->icount.dcd++;
1981#if SYNCLINK_GENERIC_HDLC
1982 if (info->netcount) {
1983 if (info->signals & SerialSignal_DCD)
1984 netif_carrier_on(info->netdev);
1985 else
1986 netif_carrier_off(info->netdev);
1987 }
1988#endif
1989 wake_up_interruptible(&info->status_event_wait_q);
1990 wake_up_interruptible(&info->event_wait_q);
1991 info->pending_bh |= BH_STATUS;
1992
1993 if (tty_port_check_carrier(&info->port)) {
1994 if (info->signals & SerialSignal_DCD)
1995 wake_up_interruptible(&info->port.open_wait);
1996 else {
1997 if (info->port.tty)
1998 tty_hangup(info->port.tty);
1999 }
2000 }
2001}
2002
2003static void ri_change(struct slgt_info *info, unsigned short status)
2004{
2005 if (status & BIT0) {
2006 info->signals |= SerialSignal_RI;
2007 info->input_signal_events.ri_up++;
2008 } else {
2009 info->signals &= ~SerialSignal_RI;
2010 info->input_signal_events.ri_down++;
2011 }
2012 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2013 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2014 slgt_irq_off(info, IRQ_RI);
2015 return;
2016 }
2017 info->icount.rng++;
2018 wake_up_interruptible(&info->status_event_wait_q);
2019 wake_up_interruptible(&info->event_wait_q);
2020 info->pending_bh |= BH_STATUS;
2021}
2022
2023static void isr_rxdata(struct slgt_info *info)
2024{
2025 unsigned int count = info->rbuf_fill_count;
2026 unsigned int i = info->rbuf_fill_index;
2027 unsigned short reg;
2028
2029 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2030 reg = rd_reg16(info, RDR);
2031 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2032 if (desc_complete(info->rbufs[i])) {
2033 /* all buffers full */
2034 rx_stop(info);
2035 info->rx_restart = true;
2036 continue;
2037 }
2038 info->rbufs[i].buf[count++] = (unsigned char)reg;
2039 /* async mode saves status byte to buffer for each data byte */
2040 if (info->params.mode == MGSL_MODE_ASYNC)
2041 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2042 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2043 /* buffer full or end of frame */
2044 set_desc_count(info->rbufs[i], count);
2045 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2046 info->rbuf_fill_count = count = 0;
2047 if (++i == info->rbuf_count)
2048 i = 0;
2049 info->pending_bh |= BH_RECEIVE;
2050 }
2051 }
2052
2053 info->rbuf_fill_index = i;
2054 info->rbuf_fill_count = count;
2055}
2056
2057static void isr_serial(struct slgt_info *info)
2058{
2059 unsigned short status = rd_reg16(info, SSR);
2060
2061 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2062
2063 wr_reg16(info, SSR, status); /* clear pending */
2064
2065 info->irq_occurred = true;
2066
2067 if (info->params.mode == MGSL_MODE_ASYNC) {
2068 if (status & IRQ_TXIDLE) {
2069 if (info->tx_active)
2070 isr_txeom(info, status);
2071 }
2072 if (info->rx_pio && (status & IRQ_RXDATA))
2073 isr_rxdata(info);
2074 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2075 info->icount.brk++;
2076 /* process break detection if tty control allows */
2077 if (info->port.tty) {
2078 if (!(status & info->ignore_status_mask)) {
2079 if (info->read_status_mask & MASK_BREAK) {
2080 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2081 if (info->port.flags & ASYNC_SAK)
2082 do_SAK(info->port.tty);
2083 }
2084 }
2085 }
2086 }
2087 } else {
2088 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2089 isr_txeom(info, status);
2090 if (info->rx_pio && (status & IRQ_RXDATA))
2091 isr_rxdata(info);
2092 if (status & IRQ_RXIDLE) {
2093 if (status & RXIDLE)
2094 info->icount.rxidle++;
2095 else
2096 info->icount.exithunt++;
2097 wake_up_interruptible(&info->event_wait_q);
2098 }
2099
2100 if (status & IRQ_RXOVER)
2101 rx_start(info);
2102 }
2103
2104 if (status & IRQ_DSR)
2105 dsr_change(info, status);
2106 if (status & IRQ_CTS)
2107 cts_change(info, status);
2108 if (status & IRQ_DCD)
2109 dcd_change(info, status);
2110 if (status & IRQ_RI)
2111 ri_change(info, status);
2112}
2113
2114static void isr_rdma(struct slgt_info *info)
2115{
2116 unsigned int status = rd_reg32(info, RDCSR);
2117
2118 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2119
2120 /* RDCSR (rx DMA control/status)
2121 *
2122 * 31..07 reserved
2123 * 06 save status byte to DMA buffer
2124 * 05 error
2125 * 04 eol (end of list)
2126 * 03 eob (end of buffer)
2127 * 02 IRQ enable
2128 * 01 reset
2129 * 00 enable
2130 */
2131 wr_reg32(info, RDCSR, status); /* clear pending */
2132
2133 if (status & (BIT5 + BIT4)) {
2134 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2135 info->rx_restart = true;
2136 }
2137 info->pending_bh |= BH_RECEIVE;
2138}
2139
2140static void isr_tdma(struct slgt_info *info)
2141{
2142 unsigned int status = rd_reg32(info, TDCSR);
2143
2144 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2145
2146 /* TDCSR (tx DMA control/status)
2147 *
2148 * 31..06 reserved
2149 * 05 error
2150 * 04 eol (end of list)
2151 * 03 eob (end of buffer)
2152 * 02 IRQ enable
2153 * 01 reset
2154 * 00 enable
2155 */
2156 wr_reg32(info, TDCSR, status); /* clear pending */
2157
2158 if (status & (BIT5 + BIT4 + BIT3)) {
2159 // another transmit buffer has completed
2160 // run bottom half to get more send data from user
2161 info->pending_bh |= BH_TRANSMIT;
2162 }
2163}
2164
2165/*
2166 * return true if there are unsent tx DMA buffers, otherwise false
2167 *
2168 * if there are unsent buffers then info->tbuf_start
2169 * is set to index of first unsent buffer
2170 */
2171static bool unsent_tbufs(struct slgt_info *info)
2172{
2173 unsigned int i = info->tbuf_current;
2174 bool rc = false;
2175
2176 /*
2177 * search backwards from last loaded buffer (precedes tbuf_current)
2178 * for first unsent buffer (desc_count > 0)
2179 */
2180
2181 do {
2182 if (i)
2183 i--;
2184 else
2185 i = info->tbuf_count - 1;
2186 if (!desc_count(info->tbufs[i]))
2187 break;
2188 info->tbuf_start = i;
2189 rc = true;
2190 } while (i != info->tbuf_current);
2191
2192 return rc;
2193}
2194
2195static void isr_txeom(struct slgt_info *info, unsigned short status)
2196{
2197 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2198
2199 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2200 tdma_reset(info);
2201 if (status & IRQ_TXUNDER) {
2202 unsigned short val = rd_reg16(info, TCR);
2203 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2204 wr_reg16(info, TCR, val); /* clear reset bit */
2205 }
2206
2207 if (info->tx_active) {
2208 if (info->params.mode != MGSL_MODE_ASYNC) {
2209 if (status & IRQ_TXUNDER)
2210 info->icount.txunder++;
2211 else if (status & IRQ_TXIDLE)
2212 info->icount.txok++;
2213 }
2214
2215 if (unsent_tbufs(info)) {
2216 tx_start(info);
2217 update_tx_timer(info);
2218 return;
2219 }
2220 info->tx_active = false;
2221
2222 del_timer(&info->tx_timer);
2223
2224 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2225 info->signals &= ~SerialSignal_RTS;
2226 info->drop_rts_on_tx_done = false;
2227 set_gtsignals(info);
2228 }
2229
2230#if SYNCLINK_GENERIC_HDLC
2231 if (info->netcount)
2232 hdlcdev_tx_done(info);
2233 else
2234#endif
2235 {
2236 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2237 tx_stop(info);
2238 return;
2239 }
2240 info->pending_bh |= BH_TRANSMIT;
2241 }
2242 }
2243}
2244
2245static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2246{
2247 struct cond_wait *w, *prev;
2248
2249 /* wake processes waiting for specific transitions */
2250 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2251 if (w->data & changed) {
2252 w->data = state;
2253 wake_up_interruptible(&w->q);
2254 if (prev != NULL)
2255 prev->next = w->next;
2256 else
2257 info->gpio_wait_q = w->next;
2258 } else
2259 prev = w;
2260 }
2261}
2262
2263/* interrupt service routine
2264 *
2265 * irq interrupt number
2266 * dev_id device ID supplied during interrupt registration
2267 */
2268static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2269{
2270 struct slgt_info *info = dev_id;
2271 unsigned int gsr;
2272 unsigned int i;
2273
2274 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2275
2276 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2277 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2278 info->irq_occurred = true;
2279 for(i=0; i < info->port_count ; i++) {
2280 if (info->port_array[i] == NULL)
2281 continue;
2282 spin_lock(&info->port_array[i]->lock);
2283 if (gsr & (BIT8 << i))
2284 isr_serial(info->port_array[i]);
2285 if (gsr & (BIT16 << (i*2)))
2286 isr_rdma(info->port_array[i]);
2287 if (gsr & (BIT17 << (i*2)))
2288 isr_tdma(info->port_array[i]);
2289 spin_unlock(&info->port_array[i]->lock);
2290 }
2291 }
2292
2293 if (info->gpio_present) {
2294 unsigned int state;
2295 unsigned int changed;
2296 spin_lock(&info->lock);
2297 while ((changed = rd_reg32(info, IOSR)) != 0) {
2298 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2299 /* read latched state of GPIO signals */
2300 state = rd_reg32(info, IOVR);
2301 /* clear pending GPIO interrupt bits */
2302 wr_reg32(info, IOSR, changed);
2303 for (i=0 ; i < info->port_count ; i++) {
2304 if (info->port_array[i] != NULL)
2305 isr_gpio(info->port_array[i], changed, state);
2306 }
2307 }
2308 spin_unlock(&info->lock);
2309 }
2310
2311 for(i=0; i < info->port_count ; i++) {
2312 struct slgt_info *port = info->port_array[i];
2313 if (port == NULL)
2314 continue;
2315 spin_lock(&port->lock);
2316 if ((port->port.count || port->netcount) &&
2317 port->pending_bh && !port->bh_running &&
2318 !port->bh_requested) {
2319 DBGISR(("%s bh queued\n", port->device_name));
2320 schedule_work(&port->task);
2321 port->bh_requested = true;
2322 }
2323 spin_unlock(&port->lock);
2324 }
2325
2326 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2327 return IRQ_HANDLED;
2328}
2329
2330static int startup(struct slgt_info *info)
2331{
2332 DBGINFO(("%s startup\n", info->device_name));
2333
2334 if (tty_port_initialized(&info->port))
2335 return 0;
2336
2337 if (!info->tx_buf) {
2338 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2339 if (!info->tx_buf) {
2340 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2341 return -ENOMEM;
2342 }
2343 }
2344
2345 info->pending_bh = 0;
2346
2347 memset(&info->icount, 0, sizeof(info->icount));
2348
2349 /* program hardware for current parameters */
2350 change_params(info);
2351
2352 if (info->port.tty)
2353 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2354
2355 tty_port_set_initialized(&info->port, true);
2356
2357 return 0;
2358}
2359
2360/*
2361 * called by close() and hangup() to shutdown hardware
2362 */
2363static void shutdown(struct slgt_info *info)
2364{
2365 unsigned long flags;
2366
2367 if (!tty_port_initialized(&info->port))
2368 return;
2369
2370 DBGINFO(("%s shutdown\n", info->device_name));
2371
2372 /* clear status wait queue because status changes */
2373 /* can't happen after shutting down the hardware */
2374 wake_up_interruptible(&info->status_event_wait_q);
2375 wake_up_interruptible(&info->event_wait_q);
2376
2377 del_timer_sync(&info->tx_timer);
2378 del_timer_sync(&info->rx_timer);
2379
2380 kfree(info->tx_buf);
2381 info->tx_buf = NULL;
2382
2383 spin_lock_irqsave(&info->lock,flags);
2384
2385 tx_stop(info);
2386 rx_stop(info);
2387
2388 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2389
2390 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2391 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2392 set_gtsignals(info);
2393 }
2394
2395 flush_cond_wait(&info->gpio_wait_q);
2396
2397 spin_unlock_irqrestore(&info->lock,flags);
2398
2399 if (info->port.tty)
2400 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2401
2402 tty_port_set_initialized(&info->port, false);
2403}
2404
2405static void program_hw(struct slgt_info *info)
2406{
2407 unsigned long flags;
2408
2409 spin_lock_irqsave(&info->lock,flags);
2410
2411 rx_stop(info);
2412 tx_stop(info);
2413
2414 if (info->params.mode != MGSL_MODE_ASYNC ||
2415 info->netcount)
2416 sync_mode(info);
2417 else
2418 async_mode(info);
2419
2420 set_gtsignals(info);
2421
2422 info->dcd_chkcount = 0;
2423 info->cts_chkcount = 0;
2424 info->ri_chkcount = 0;
2425 info->dsr_chkcount = 0;
2426
2427 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2428 get_gtsignals(info);
2429
2430 if (info->netcount ||
2431 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2432 rx_start(info);
2433
2434 spin_unlock_irqrestore(&info->lock,flags);
2435}
2436
2437/*
2438 * reconfigure adapter based on new parameters
2439 */
2440static void change_params(struct slgt_info *info)
2441{
2442 unsigned cflag;
2443 int bits_per_char;
2444
2445 if (!info->port.tty)
2446 return;
2447 DBGINFO(("%s change_params\n", info->device_name));
2448
2449 cflag = info->port.tty->termios.c_cflag;
2450
2451 /* if B0 rate (hangup) specified then negate RTS and DTR */
2452 /* otherwise assert RTS and DTR */
2453 if (cflag & CBAUD)
2454 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2455 else
2456 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2457
2458 /* byte size and parity */
2459
2460 info->params.data_bits = tty_get_char_size(cflag);
2461 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2462
2463 if (cflag & PARENB)
2464 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2465 else
2466 info->params.parity = ASYNC_PARITY_NONE;
2467
2468 /* calculate number of jiffies to transmit a full
2469 * FIFO (32 bytes) at specified data rate
2470 */
2471 bits_per_char = info->params.data_bits +
2472 info->params.stop_bits + 1;
2473
2474 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2475
2476 if (info->params.data_rate) {
2477 info->timeout = (32*HZ*bits_per_char) /
2478 info->params.data_rate;
2479 }
2480 info->timeout += HZ/50; /* Add .02 seconds of slop */
2481
2482 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2483 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2484
2485 /* process tty input control flags */
2486
2487 info->read_status_mask = IRQ_RXOVER;
2488 if (I_INPCK(info->port.tty))
2489 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2490 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2491 info->read_status_mask |= MASK_BREAK;
2492 if (I_IGNPAR(info->port.tty))
2493 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2494 if (I_IGNBRK(info->port.tty)) {
2495 info->ignore_status_mask |= MASK_BREAK;
2496 /* If ignoring parity and break indicators, ignore
2497 * overruns too. (For real raw support).
2498 */
2499 if (I_IGNPAR(info->port.tty))
2500 info->ignore_status_mask |= MASK_OVERRUN;
2501 }
2502
2503 program_hw(info);
2504}
2505
2506static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2507{
2508 DBGINFO(("%s get_stats\n", info->device_name));
2509 if (!user_icount) {
2510 memset(&info->icount, 0, sizeof(info->icount));
2511 } else {
2512 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2513 return -EFAULT;
2514 }
2515 return 0;
2516}
2517
2518static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2519{
2520 DBGINFO(("%s get_params\n", info->device_name));
2521 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2522 return -EFAULT;
2523 return 0;
2524}
2525
2526static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2527{
2528 unsigned long flags;
2529 MGSL_PARAMS tmp_params;
2530
2531 DBGINFO(("%s set_params\n", info->device_name));
2532 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2533 return -EFAULT;
2534
2535 spin_lock_irqsave(&info->lock, flags);
2536 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2537 info->base_clock = tmp_params.clock_speed;
2538 else
2539 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2540 spin_unlock_irqrestore(&info->lock, flags);
2541
2542 program_hw(info);
2543
2544 return 0;
2545}
2546
2547static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2548{
2549 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2550 if (put_user(info->idle_mode, idle_mode))
2551 return -EFAULT;
2552 return 0;
2553}
2554
2555static int set_txidle(struct slgt_info *info, int idle_mode)
2556{
2557 unsigned long flags;
2558 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2559 spin_lock_irqsave(&info->lock,flags);
2560 info->idle_mode = idle_mode;
2561 if (info->params.mode != MGSL_MODE_ASYNC)
2562 tx_set_idle(info);
2563 spin_unlock_irqrestore(&info->lock,flags);
2564 return 0;
2565}
2566
2567static int tx_enable(struct slgt_info *info, int enable)
2568{
2569 unsigned long flags;
2570 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2571 spin_lock_irqsave(&info->lock,flags);
2572 if (enable) {
2573 if (!info->tx_enabled)
2574 tx_start(info);
2575 } else {
2576 if (info->tx_enabled)
2577 tx_stop(info);
2578 }
2579 spin_unlock_irqrestore(&info->lock,flags);
2580 return 0;
2581}
2582
2583/*
2584 * abort transmit HDLC frame
2585 */
2586static int tx_abort(struct slgt_info *info)
2587{
2588 unsigned long flags;
2589 DBGINFO(("%s tx_abort\n", info->device_name));
2590 spin_lock_irqsave(&info->lock,flags);
2591 tdma_reset(info);
2592 spin_unlock_irqrestore(&info->lock,flags);
2593 return 0;
2594}
2595
2596static int rx_enable(struct slgt_info *info, int enable)
2597{
2598 unsigned long flags;
2599 unsigned int rbuf_fill_level;
2600 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2601 spin_lock_irqsave(&info->lock,flags);
2602 /*
2603 * enable[31..16] = receive DMA buffer fill level
2604 * 0 = noop (leave fill level unchanged)
2605 * fill level must be multiple of 4 and <= buffer size
2606 */
2607 rbuf_fill_level = ((unsigned int)enable) >> 16;
2608 if (rbuf_fill_level) {
2609 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2610 spin_unlock_irqrestore(&info->lock, flags);
2611 return -EINVAL;
2612 }
2613 info->rbuf_fill_level = rbuf_fill_level;
2614 if (rbuf_fill_level < 128)
2615 info->rx_pio = 1; /* PIO mode */
2616 else
2617 info->rx_pio = 0; /* DMA mode */
2618 rx_stop(info); /* restart receiver to use new fill level */
2619 }
2620
2621 /*
2622 * enable[1..0] = receiver enable command
2623 * 0 = disable
2624 * 1 = enable
2625 * 2 = enable or force hunt mode if already enabled
2626 */
2627 enable &= 3;
2628 if (enable) {
2629 if (!info->rx_enabled)
2630 rx_start(info);
2631 else if (enable == 2) {
2632 /* force hunt mode (write 1 to RCR[3]) */
2633 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2634 }
2635 } else {
2636 if (info->rx_enabled)
2637 rx_stop(info);
2638 }
2639 spin_unlock_irqrestore(&info->lock,flags);
2640 return 0;
2641}
2642
2643/*
2644 * wait for specified event to occur
2645 */
2646static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2647{
2648 unsigned long flags;
2649 int s;
2650 int rc=0;
2651 struct mgsl_icount cprev, cnow;
2652 int events;
2653 int mask;
2654 struct _input_signal_events oldsigs, newsigs;
2655 DECLARE_WAITQUEUE(wait, current);
2656
2657 if (get_user(mask, mask_ptr))
2658 return -EFAULT;
2659
2660 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2661
2662 spin_lock_irqsave(&info->lock,flags);
2663
2664 /* return immediately if state matches requested events */
2665 get_gtsignals(info);
2666 s = info->signals;
2667
2668 events = mask &
2669 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2670 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2671 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2672 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2673 if (events) {
2674 spin_unlock_irqrestore(&info->lock,flags);
2675 goto exit;
2676 }
2677
2678 /* save current irq counts */
2679 cprev = info->icount;
2680 oldsigs = info->input_signal_events;
2681
2682 /* enable hunt and idle irqs if needed */
2683 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2684 unsigned short val = rd_reg16(info, SCR);
2685 if (!(val & IRQ_RXIDLE))
2686 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2687 }
2688
2689 set_current_state(TASK_INTERRUPTIBLE);
2690 add_wait_queue(&info->event_wait_q, &wait);
2691
2692 spin_unlock_irqrestore(&info->lock,flags);
2693
2694 for(;;) {
2695 schedule();
2696 if (signal_pending(current)) {
2697 rc = -ERESTARTSYS;
2698 break;
2699 }
2700
2701 /* get current irq counts */
2702 spin_lock_irqsave(&info->lock,flags);
2703 cnow = info->icount;
2704 newsigs = info->input_signal_events;
2705 set_current_state(TASK_INTERRUPTIBLE);
2706 spin_unlock_irqrestore(&info->lock,flags);
2707
2708 /* if no change, wait aborted for some reason */
2709 if (newsigs.dsr_up == oldsigs.dsr_up &&
2710 newsigs.dsr_down == oldsigs.dsr_down &&
2711 newsigs.dcd_up == oldsigs.dcd_up &&
2712 newsigs.dcd_down == oldsigs.dcd_down &&
2713 newsigs.cts_up == oldsigs.cts_up &&
2714 newsigs.cts_down == oldsigs.cts_down &&
2715 newsigs.ri_up == oldsigs.ri_up &&
2716 newsigs.ri_down == oldsigs.ri_down &&
2717 cnow.exithunt == cprev.exithunt &&
2718 cnow.rxidle == cprev.rxidle) {
2719 rc = -EIO;
2720 break;
2721 }
2722
2723 events = mask &
2724 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2725 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2726 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2727 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2728 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2729 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2730 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2731 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2732 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2733 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2734 if (events)
2735 break;
2736
2737 cprev = cnow;
2738 oldsigs = newsigs;
2739 }
2740
2741 remove_wait_queue(&info->event_wait_q, &wait);
2742 set_current_state(TASK_RUNNING);
2743
2744
2745 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2746 spin_lock_irqsave(&info->lock,flags);
2747 if (!waitqueue_active(&info->event_wait_q)) {
2748 /* disable enable exit hunt mode/idle rcvd IRQs */
2749 wr_reg16(info, SCR,
2750 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2751 }
2752 spin_unlock_irqrestore(&info->lock,flags);
2753 }
2754exit:
2755 if (rc == 0)
2756 rc = put_user(events, mask_ptr);
2757 return rc;
2758}
2759
2760static int get_interface(struct slgt_info *info, int __user *if_mode)
2761{
2762 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2763 if (put_user(info->if_mode, if_mode))
2764 return -EFAULT;
2765 return 0;
2766}
2767
2768static int set_interface(struct slgt_info *info, int if_mode)
2769{
2770 unsigned long flags;
2771 unsigned short val;
2772
2773 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2774 spin_lock_irqsave(&info->lock,flags);
2775 info->if_mode = if_mode;
2776
2777 msc_set_vcr(info);
2778
2779 /* TCR (tx control) 07 1=RTS driver control */
2780 val = rd_reg16(info, TCR);
2781 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2782 val |= BIT7;
2783 else
2784 val &= ~BIT7;
2785 wr_reg16(info, TCR, val);
2786
2787 spin_unlock_irqrestore(&info->lock,flags);
2788 return 0;
2789}
2790
2791static int get_xsync(struct slgt_info *info, int __user *xsync)
2792{
2793 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2794 if (put_user(info->xsync, xsync))
2795 return -EFAULT;
2796 return 0;
2797}
2798
2799/*
2800 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2801 *
2802 * sync pattern is contained in least significant bytes of value
2803 * most significant byte of sync pattern is oldest (1st sent/detected)
2804 */
2805static int set_xsync(struct slgt_info *info, int xsync)
2806{
2807 unsigned long flags;
2808
2809 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2810 spin_lock_irqsave(&info->lock, flags);
2811 info->xsync = xsync;
2812 wr_reg32(info, XSR, xsync);
2813 spin_unlock_irqrestore(&info->lock, flags);
2814 return 0;
2815}
2816
2817static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2818{
2819 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2820 if (put_user(info->xctrl, xctrl))
2821 return -EFAULT;
2822 return 0;
2823}
2824
2825/*
2826 * set extended control options
2827 *
2828 * xctrl[31:19] reserved, must be zero
2829 * xctrl[18:17] extended sync pattern length in bytes
2830 * 00 = 1 byte in xsr[7:0]
2831 * 01 = 2 bytes in xsr[15:0]
2832 * 10 = 3 bytes in xsr[23:0]
2833 * 11 = 4 bytes in xsr[31:0]
2834 * xctrl[16] 1 = enable terminal count, 0=disabled
2835 * xctrl[15:0] receive terminal count for fixed length packets
2836 * value is count minus one (0 = 1 byte packet)
2837 * when terminal count is reached, receiver
2838 * automatically returns to hunt mode and receive
2839 * FIFO contents are flushed to DMA buffers with
2840 * end of frame (EOF) status
2841 */
2842static int set_xctrl(struct slgt_info *info, int xctrl)
2843{
2844 unsigned long flags;
2845
2846 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2847 spin_lock_irqsave(&info->lock, flags);
2848 info->xctrl = xctrl;
2849 wr_reg32(info, XCR, xctrl);
2850 spin_unlock_irqrestore(&info->lock, flags);
2851 return 0;
2852}
2853
2854/*
2855 * set general purpose IO pin state and direction
2856 *
2857 * user_gpio fields:
2858 * state each bit indicates a pin state
2859 * smask set bit indicates pin state to set
2860 * dir each bit indicates a pin direction (0=input, 1=output)
2861 * dmask set bit indicates pin direction to set
2862 */
2863static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2864{
2865 unsigned long flags;
2866 struct gpio_desc gpio;
2867 __u32 data;
2868
2869 if (!info->gpio_present)
2870 return -EINVAL;
2871 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2872 return -EFAULT;
2873 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2874 info->device_name, gpio.state, gpio.smask,
2875 gpio.dir, gpio.dmask));
2876
2877 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2878 if (gpio.dmask) {
2879 data = rd_reg32(info, IODR);
2880 data |= gpio.dmask & gpio.dir;
2881 data &= ~(gpio.dmask & ~gpio.dir);
2882 wr_reg32(info, IODR, data);
2883 }
2884 if (gpio.smask) {
2885 data = rd_reg32(info, IOVR);
2886 data |= gpio.smask & gpio.state;
2887 data &= ~(gpio.smask & ~gpio.state);
2888 wr_reg32(info, IOVR, data);
2889 }
2890 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2891
2892 return 0;
2893}
2894
2895/*
2896 * get general purpose IO pin state and direction
2897 */
2898static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2899{
2900 struct gpio_desc gpio;
2901 if (!info->gpio_present)
2902 return -EINVAL;
2903 gpio.state = rd_reg32(info, IOVR);
2904 gpio.smask = 0xffffffff;
2905 gpio.dir = rd_reg32(info, IODR);
2906 gpio.dmask = 0xffffffff;
2907 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2908 return -EFAULT;
2909 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2910 info->device_name, gpio.state, gpio.dir));
2911 return 0;
2912}
2913
2914/*
2915 * conditional wait facility
2916 */
2917static void init_cond_wait(struct cond_wait *w, unsigned int data)
2918{
2919 init_waitqueue_head(&w->q);
2920 init_waitqueue_entry(&w->wait, current);
2921 w->data = data;
2922}
2923
2924static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2925{
2926 set_current_state(TASK_INTERRUPTIBLE);
2927 add_wait_queue(&w->q, &w->wait);
2928 w->next = *head;
2929 *head = w;
2930}
2931
2932static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2933{
2934 struct cond_wait *w, *prev;
2935 remove_wait_queue(&cw->q, &cw->wait);
2936 set_current_state(TASK_RUNNING);
2937 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2938 if (w == cw) {
2939 if (prev != NULL)
2940 prev->next = w->next;
2941 else
2942 *head = w->next;
2943 break;
2944 }
2945 }
2946}
2947
2948static void flush_cond_wait(struct cond_wait **head)
2949{
2950 while (*head != NULL) {
2951 wake_up_interruptible(&(*head)->q);
2952 *head = (*head)->next;
2953 }
2954}
2955
2956/*
2957 * wait for general purpose I/O pin(s) to enter specified state
2958 *
2959 * user_gpio fields:
2960 * state - bit indicates target pin state
2961 * smask - set bit indicates watched pin
2962 *
2963 * The wait ends when at least one watched pin enters the specified
2964 * state. When 0 (no error) is returned, user_gpio->state is set to the
2965 * state of all GPIO pins when the wait ends.
2966 *
2967 * Note: Each pin may be a dedicated input, dedicated output, or
2968 * configurable input/output. The number and configuration of pins
2969 * varies with the specific adapter model. Only input pins (dedicated
2970 * or configured) can be monitored with this function.
2971 */
2972static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2973{
2974 unsigned long flags;
2975 int rc = 0;
2976 struct gpio_desc gpio;
2977 struct cond_wait wait;
2978 u32 state;
2979
2980 if (!info->gpio_present)
2981 return -EINVAL;
2982 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2983 return -EFAULT;
2984 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2985 info->device_name, gpio.state, gpio.smask));
2986 /* ignore output pins identified by set IODR bit */
2987 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2988 return -EINVAL;
2989 init_cond_wait(&wait, gpio.smask);
2990
2991 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2992 /* enable interrupts for watched pins */
2993 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2994 /* get current pin states */
2995 state = rd_reg32(info, IOVR);
2996
2997 if (gpio.smask & ~(state ^ gpio.state)) {
2998 /* already in target state */
2999 gpio.state = state;
3000 } else {
3001 /* wait for target state */
3002 add_cond_wait(&info->gpio_wait_q, &wait);
3003 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3004 schedule();
3005 if (signal_pending(current))
3006 rc = -ERESTARTSYS;
3007 else
3008 gpio.state = wait.data;
3009 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3010 remove_cond_wait(&info->gpio_wait_q, &wait);
3011 }
3012
3013 /* disable all GPIO interrupts if no waiting processes */
3014 if (info->gpio_wait_q == NULL)
3015 wr_reg32(info, IOER, 0);
3016 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3017
3018 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3019 rc = -EFAULT;
3020 return rc;
3021}
3022
3023static int modem_input_wait(struct slgt_info *info,int arg)
3024{
3025 unsigned long flags;
3026 int rc;
3027 struct mgsl_icount cprev, cnow;
3028 DECLARE_WAITQUEUE(wait, current);
3029
3030 /* save current irq counts */
3031 spin_lock_irqsave(&info->lock,flags);
3032 cprev = info->icount;
3033 add_wait_queue(&info->status_event_wait_q, &wait);
3034 set_current_state(TASK_INTERRUPTIBLE);
3035 spin_unlock_irqrestore(&info->lock,flags);
3036
3037 for(;;) {
3038 schedule();
3039 if (signal_pending(current)) {
3040 rc = -ERESTARTSYS;
3041 break;
3042 }
3043
3044 /* get new irq counts */
3045 spin_lock_irqsave(&info->lock,flags);
3046 cnow = info->icount;
3047 set_current_state(TASK_INTERRUPTIBLE);
3048 spin_unlock_irqrestore(&info->lock,flags);
3049
3050 /* if no change, wait aborted for some reason */
3051 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3052 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3053 rc = -EIO;
3054 break;
3055 }
3056
3057 /* check for change in caller specified modem input */
3058 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3059 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3060 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3061 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3062 rc = 0;
3063 break;
3064 }
3065
3066 cprev = cnow;
3067 }
3068 remove_wait_queue(&info->status_event_wait_q, &wait);
3069 set_current_state(TASK_RUNNING);
3070 return rc;
3071}
3072
3073/*
3074 * return state of serial control and status signals
3075 */
3076static int tiocmget(struct tty_struct *tty)
3077{
3078 struct slgt_info *info = tty->driver_data;
3079 unsigned int result;
3080 unsigned long flags;
3081
3082 spin_lock_irqsave(&info->lock,flags);
3083 get_gtsignals(info);
3084 spin_unlock_irqrestore(&info->lock,flags);
3085
3086 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3087 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3088 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3089 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3090 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3091 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3092
3093 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3094 return result;
3095}
3096
3097/*
3098 * set modem control signals (DTR/RTS)
3099 *
3100 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3101 * TIOCMSET = set/clear signal values
3102 * value bit mask for command
3103 */
3104static int tiocmset(struct tty_struct *tty,
3105 unsigned int set, unsigned int clear)
3106{
3107 struct slgt_info *info = tty->driver_data;
3108 unsigned long flags;
3109
3110 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3111
3112 if (set & TIOCM_RTS)
3113 info->signals |= SerialSignal_RTS;
3114 if (set & TIOCM_DTR)
3115 info->signals |= SerialSignal_DTR;
3116 if (clear & TIOCM_RTS)
3117 info->signals &= ~SerialSignal_RTS;
3118 if (clear & TIOCM_DTR)
3119 info->signals &= ~SerialSignal_DTR;
3120
3121 spin_lock_irqsave(&info->lock,flags);
3122 set_gtsignals(info);
3123 spin_unlock_irqrestore(&info->lock,flags);
3124 return 0;
3125}
3126
3127static bool carrier_raised(struct tty_port *port)
3128{
3129 unsigned long flags;
3130 struct slgt_info *info = container_of(port, struct slgt_info, port);
3131
3132 spin_lock_irqsave(&info->lock,flags);
3133 get_gtsignals(info);
3134 spin_unlock_irqrestore(&info->lock,flags);
3135
3136 return info->signals & SerialSignal_DCD;
3137}
3138
3139static void dtr_rts(struct tty_port *port, bool active)
3140{
3141 unsigned long flags;
3142 struct slgt_info *info = container_of(port, struct slgt_info, port);
3143
3144 spin_lock_irqsave(&info->lock,flags);
3145 if (active)
3146 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3147 else
3148 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3149 set_gtsignals(info);
3150 spin_unlock_irqrestore(&info->lock,flags);
3151}
3152
3153
3154/*
3155 * block current process until the device is ready to open
3156 */
3157static int block_til_ready(struct tty_struct *tty, struct file *filp,
3158 struct slgt_info *info)
3159{
3160 DECLARE_WAITQUEUE(wait, current);
3161 int retval;
3162 bool do_clocal = false;
3163 unsigned long flags;
3164 bool cd;
3165 struct tty_port *port = &info->port;
3166
3167 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3168
3169 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3170 /* nonblock mode is set or port is not enabled */
3171 tty_port_set_active(port, true);
3172 return 0;
3173 }
3174
3175 if (C_CLOCAL(tty))
3176 do_clocal = true;
3177
3178 /* Wait for carrier detect and the line to become
3179 * free (i.e., not in use by the callout). While we are in
3180 * this loop, port->count is dropped by one, so that
3181 * close() knows when to free things. We restore it upon
3182 * exit, either normal or abnormal.
3183 */
3184
3185 retval = 0;
3186 add_wait_queue(&port->open_wait, &wait);
3187
3188 spin_lock_irqsave(&info->lock, flags);
3189 port->count--;
3190 spin_unlock_irqrestore(&info->lock, flags);
3191 port->blocked_open++;
3192
3193 while (1) {
3194 if (C_BAUD(tty) && tty_port_initialized(port))
3195 tty_port_raise_dtr_rts(port);
3196
3197 set_current_state(TASK_INTERRUPTIBLE);
3198
3199 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3200 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3201 -EAGAIN : -ERESTARTSYS;
3202 break;
3203 }
3204
3205 cd = tty_port_carrier_raised(port);
3206 if (do_clocal || cd)
3207 break;
3208
3209 if (signal_pending(current)) {
3210 retval = -ERESTARTSYS;
3211 break;
3212 }
3213
3214 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3215 tty_unlock(tty);
3216 schedule();
3217 tty_lock(tty);
3218 }
3219
3220 set_current_state(TASK_RUNNING);
3221 remove_wait_queue(&port->open_wait, &wait);
3222
3223 if (!tty_hung_up_p(filp))
3224 port->count++;
3225 port->blocked_open--;
3226
3227 if (!retval)
3228 tty_port_set_active(port, true);
3229
3230 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3231 return retval;
3232}
3233
3234/*
3235 * allocate buffers used for calling line discipline receive_buf
3236 * directly in synchronous mode
3237 * note: add 5 bytes to max frame size to allow appending
3238 * 32-bit CRC and status byte when configured to do so
3239 */
3240static int alloc_tmp_rbuf(struct slgt_info *info)
3241{
3242 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3243 if (info->tmp_rbuf == NULL)
3244 return -ENOMEM;
3245
3246 return 0;
3247}
3248
3249static void free_tmp_rbuf(struct slgt_info *info)
3250{
3251 kfree(info->tmp_rbuf);
3252 info->tmp_rbuf = NULL;
3253}
3254
3255/*
3256 * allocate DMA descriptor lists.
3257 */
3258static int alloc_desc(struct slgt_info *info)
3259{
3260 unsigned int i;
3261 unsigned int pbufs;
3262
3263 /* allocate memory to hold descriptor lists */
3264 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3265 &info->bufs_dma_addr, GFP_KERNEL);
3266 if (info->bufs == NULL)
3267 return -ENOMEM;
3268
3269 info->rbufs = (struct slgt_desc*)info->bufs;
3270 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3271
3272 pbufs = (unsigned int)info->bufs_dma_addr;
3273
3274 /*
3275 * Build circular lists of descriptors
3276 */
3277
3278 for (i=0; i < info->rbuf_count; i++) {
3279 /* physical address of this descriptor */
3280 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3281
3282 /* physical address of next descriptor */
3283 if (i == info->rbuf_count - 1)
3284 info->rbufs[i].next = cpu_to_le32(pbufs);
3285 else
3286 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3287 set_desc_count(info->rbufs[i], DMABUFSIZE);
3288 }
3289
3290 for (i=0; i < info->tbuf_count; i++) {
3291 /* physical address of this descriptor */
3292 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3293
3294 /* physical address of next descriptor */
3295 if (i == info->tbuf_count - 1)
3296 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3297 else
3298 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3299 }
3300
3301 return 0;
3302}
3303
3304static void free_desc(struct slgt_info *info)
3305{
3306 if (info->bufs != NULL) {
3307 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3308 info->bufs, info->bufs_dma_addr);
3309 info->bufs = NULL;
3310 info->rbufs = NULL;
3311 info->tbufs = NULL;
3312 }
3313}
3314
3315static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3316{
3317 int i;
3318 for (i=0; i < count; i++) {
3319 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3320 &bufs[i].buf_dma_addr, GFP_KERNEL);
3321 if (!bufs[i].buf)
3322 return -ENOMEM;
3323 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3324 }
3325 return 0;
3326}
3327
3328static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3329{
3330 int i;
3331 for (i=0; i < count; i++) {
3332 if (bufs[i].buf == NULL)
3333 continue;
3334 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3335 bufs[i].buf_dma_addr);
3336 bufs[i].buf = NULL;
3337 }
3338}
3339
3340static int alloc_dma_bufs(struct slgt_info *info)
3341{
3342 info->rbuf_count = 32;
3343 info->tbuf_count = 32;
3344
3345 if (alloc_desc(info) < 0 ||
3346 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3347 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3348 alloc_tmp_rbuf(info) < 0) {
3349 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3350 return -ENOMEM;
3351 }
3352 reset_rbufs(info);
3353 return 0;
3354}
3355
3356static void free_dma_bufs(struct slgt_info *info)
3357{
3358 if (info->bufs) {
3359 free_bufs(info, info->rbufs, info->rbuf_count);
3360 free_bufs(info, info->tbufs, info->tbuf_count);
3361 free_desc(info);
3362 }
3363 free_tmp_rbuf(info);
3364}
3365
3366static int claim_resources(struct slgt_info *info)
3367{
3368 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3369 DBGERR(("%s reg addr conflict, addr=%08X\n",
3370 info->device_name, info->phys_reg_addr));
3371 info->init_error = DiagStatus_AddressConflict;
3372 goto errout;
3373 }
3374 else
3375 info->reg_addr_requested = true;
3376
3377 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3378 if (!info->reg_addr) {
3379 DBGERR(("%s can't map device registers, addr=%08X\n",
3380 info->device_name, info->phys_reg_addr));
3381 info->init_error = DiagStatus_CantAssignPciResources;
3382 goto errout;
3383 }
3384 return 0;
3385
3386errout:
3387 release_resources(info);
3388 return -ENODEV;
3389}
3390
3391static void release_resources(struct slgt_info *info)
3392{
3393 if (info->irq_requested) {
3394 free_irq(info->irq_level, info);
3395 info->irq_requested = false;
3396 }
3397
3398 if (info->reg_addr_requested) {
3399 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3400 info->reg_addr_requested = false;
3401 }
3402
3403 if (info->reg_addr) {
3404 iounmap(info->reg_addr);
3405 info->reg_addr = NULL;
3406 }
3407}
3408
3409/* Add the specified device instance data structure to the
3410 * global linked list of devices and increment the device count.
3411 */
3412static void add_device(struct slgt_info *info)
3413{
3414 char *devstr;
3415
3416 info->next_device = NULL;
3417 info->line = slgt_device_count;
3418 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3419
3420 if (info->line < MAX_DEVICES) {
3421 if (maxframe[info->line])
3422 info->max_frame_size = maxframe[info->line];
3423 }
3424
3425 slgt_device_count++;
3426
3427 if (!slgt_device_list)
3428 slgt_device_list = info;
3429 else {
3430 struct slgt_info *current_dev = slgt_device_list;
3431 while(current_dev->next_device)
3432 current_dev = current_dev->next_device;
3433 current_dev->next_device = info;
3434 }
3435
3436 if (info->max_frame_size < 4096)
3437 info->max_frame_size = 4096;
3438 else if (info->max_frame_size > 65535)
3439 info->max_frame_size = 65535;
3440
3441 switch(info->pdev->device) {
3442 case SYNCLINK_GT_DEVICE_ID:
3443 devstr = "GT";
3444 break;
3445 case SYNCLINK_GT2_DEVICE_ID:
3446 devstr = "GT2";
3447 break;
3448 case SYNCLINK_GT4_DEVICE_ID:
3449 devstr = "GT4";
3450 break;
3451 case SYNCLINK_AC_DEVICE_ID:
3452 devstr = "AC";
3453 info->params.mode = MGSL_MODE_ASYNC;
3454 break;
3455 default:
3456 devstr = "(unknown model)";
3457 }
3458 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3459 devstr, info->device_name, info->phys_reg_addr,
3460 info->irq_level, info->max_frame_size);
3461
3462#if SYNCLINK_GENERIC_HDLC
3463 hdlcdev_init(info);
3464#endif
3465}
3466
3467static const struct tty_port_operations slgt_port_ops = {
3468 .carrier_raised = carrier_raised,
3469 .dtr_rts = dtr_rts,
3470};
3471
3472/*
3473 * allocate device instance structure, return NULL on failure
3474 */
3475static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3476{
3477 struct slgt_info *info;
3478
3479 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3480
3481 if (!info) {
3482 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3483 driver_name, adapter_num, port_num));
3484 } else {
3485 tty_port_init(&info->port);
3486 info->port.ops = &slgt_port_ops;
3487 INIT_WORK(&info->task, bh_handler);
3488 info->max_frame_size = 4096;
3489 info->base_clock = 14745600;
3490 info->rbuf_fill_level = DMABUFSIZE;
3491 init_waitqueue_head(&info->status_event_wait_q);
3492 init_waitqueue_head(&info->event_wait_q);
3493 spin_lock_init(&info->netlock);
3494 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3495 info->idle_mode = HDLC_TXIDLE_FLAGS;
3496 info->adapter_num = adapter_num;
3497 info->port_num = port_num;
3498
3499 timer_setup(&info->tx_timer, tx_timeout, 0);
3500 timer_setup(&info->rx_timer, rx_timeout, 0);
3501
3502 /* Copy configuration info to device instance data */
3503 info->pdev = pdev;
3504 info->irq_level = pdev->irq;
3505 info->phys_reg_addr = pci_resource_start(pdev,0);
3506
3507 info->bus_type = MGSL_BUS_TYPE_PCI;
3508 info->irq_flags = IRQF_SHARED;
3509
3510 info->init_error = -1; /* assume error, set to 0 on successful init */
3511 }
3512
3513 return info;
3514}
3515
3516static void device_init(int adapter_num, struct pci_dev *pdev)
3517{
3518 struct slgt_info *port_array[SLGT_MAX_PORTS];
3519 int i;
3520 int port_count = 1;
3521
3522 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3523 port_count = 2;
3524 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3525 port_count = 4;
3526
3527 /* allocate device instances for all ports */
3528 for (i=0; i < port_count; ++i) {
3529 port_array[i] = alloc_dev(adapter_num, i, pdev);
3530 if (port_array[i] == NULL) {
3531 for (--i; i >= 0; --i) {
3532 tty_port_destroy(&port_array[i]->port);
3533 kfree(port_array[i]);
3534 }
3535 return;
3536 }
3537 }
3538
3539 /* give copy of port_array to all ports and add to device list */
3540 for (i=0; i < port_count; ++i) {
3541 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3542 add_device(port_array[i]);
3543 port_array[i]->port_count = port_count;
3544 spin_lock_init(&port_array[i]->lock);
3545 }
3546
3547 /* Allocate and claim adapter resources */
3548 if (!claim_resources(port_array[0])) {
3549
3550 alloc_dma_bufs(port_array[0]);
3551
3552 /* copy resource information from first port to others */
3553 for (i = 1; i < port_count; ++i) {
3554 port_array[i]->irq_level = port_array[0]->irq_level;
3555 port_array[i]->reg_addr = port_array[0]->reg_addr;
3556 alloc_dma_bufs(port_array[i]);
3557 }
3558
3559 if (request_irq(port_array[0]->irq_level,
3560 slgt_interrupt,
3561 port_array[0]->irq_flags,
3562 port_array[0]->device_name,
3563 port_array[0]) < 0) {
3564 DBGERR(("%s request_irq failed IRQ=%d\n",
3565 port_array[0]->device_name,
3566 port_array[0]->irq_level));
3567 } else {
3568 port_array[0]->irq_requested = true;
3569 adapter_test(port_array[0]);
3570 for (i=1 ; i < port_count ; i++) {
3571 port_array[i]->init_error = port_array[0]->init_error;
3572 port_array[i]->gpio_present = port_array[0]->gpio_present;
3573 }
3574 }
3575 }
3576
3577 for (i = 0; i < port_count; ++i) {
3578 struct slgt_info *info = port_array[i];
3579 tty_port_register_device(&info->port, serial_driver, info->line,
3580 &info->pdev->dev);
3581 }
3582}
3583
3584static int init_one(struct pci_dev *dev,
3585 const struct pci_device_id *ent)
3586{
3587 if (pci_enable_device(dev)) {
3588 printk("error enabling pci device %p\n", dev);
3589 return -EIO;
3590 }
3591 pci_set_master(dev);
3592 device_init(slgt_device_count, dev);
3593 return 0;
3594}
3595
3596static void remove_one(struct pci_dev *dev)
3597{
3598}
3599
3600static const struct tty_operations ops = {
3601 .open = open,
3602 .close = close,
3603 .write = write,
3604 .put_char = put_char,
3605 .flush_chars = flush_chars,
3606 .write_room = write_room,
3607 .chars_in_buffer = chars_in_buffer,
3608 .flush_buffer = flush_buffer,
3609 .ioctl = ioctl,
3610 .compat_ioctl = slgt_compat_ioctl,
3611 .throttle = throttle,
3612 .unthrottle = unthrottle,
3613 .send_xchar = send_xchar,
3614 .break_ctl = set_break,
3615 .wait_until_sent = wait_until_sent,
3616 .set_termios = set_termios,
3617 .stop = tx_hold,
3618 .start = tx_release,
3619 .hangup = hangup,
3620 .tiocmget = tiocmget,
3621 .tiocmset = tiocmset,
3622 .get_icount = get_icount,
3623 .proc_show = synclink_gt_proc_show,
3624};
3625
3626static void slgt_cleanup(void)
3627{
3628 struct slgt_info *info;
3629 struct slgt_info *tmp;
3630
3631 if (serial_driver) {
3632 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3633 tty_unregister_device(serial_driver, info->line);
3634 tty_unregister_driver(serial_driver);
3635 tty_driver_kref_put(serial_driver);
3636 }
3637
3638 /* reset devices */
3639 info = slgt_device_list;
3640 while(info) {
3641 reset_port(info);
3642 info = info->next_device;
3643 }
3644
3645 /* release devices */
3646 info = slgt_device_list;
3647 while(info) {
3648#if SYNCLINK_GENERIC_HDLC
3649 hdlcdev_exit(info);
3650#endif
3651 free_dma_bufs(info);
3652 free_tmp_rbuf(info);
3653 if (info->port_num == 0)
3654 release_resources(info);
3655 tmp = info;
3656 info = info->next_device;
3657 tty_port_destroy(&tmp->port);
3658 kfree(tmp);
3659 }
3660
3661 if (pci_registered)
3662 pci_unregister_driver(&pci_driver);
3663}
3664
3665/*
3666 * Driver initialization entry point.
3667 */
3668static int __init slgt_init(void)
3669{
3670 int rc;
3671
3672 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3673 TTY_DRIVER_DYNAMIC_DEV);
3674 if (IS_ERR(serial_driver)) {
3675 printk("%s can't allocate tty driver\n", driver_name);
3676 return PTR_ERR(serial_driver);
3677 }
3678
3679 /* Initialize the tty_driver structure */
3680
3681 serial_driver->driver_name = "synclink_gt";
3682 serial_driver->name = tty_dev_prefix;
3683 serial_driver->major = ttymajor;
3684 serial_driver->minor_start = 64;
3685 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3686 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3687 serial_driver->init_termios = tty_std_termios;
3688 serial_driver->init_termios.c_cflag =
3689 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3690 serial_driver->init_termios.c_ispeed = 9600;
3691 serial_driver->init_termios.c_ospeed = 9600;
3692 tty_set_operations(serial_driver, &ops);
3693 if ((rc = tty_register_driver(serial_driver)) < 0) {
3694 DBGERR(("%s can't register serial driver\n", driver_name));
3695 tty_driver_kref_put(serial_driver);
3696 serial_driver = NULL;
3697 goto error;
3698 }
3699
3700 slgt_device_count = 0;
3701 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3702 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3703 goto error;
3704 }
3705 pci_registered = true;
3706
3707 return 0;
3708
3709error:
3710 slgt_cleanup();
3711 return rc;
3712}
3713
3714static void __exit slgt_exit(void)
3715{
3716 slgt_cleanup();
3717}
3718
3719module_init(slgt_init);
3720module_exit(slgt_exit);
3721
3722/*
3723 * register access routines
3724 */
3725
3726static inline void __iomem *calc_regaddr(struct slgt_info *info,
3727 unsigned int addr)
3728{
3729 void __iomem *reg_addr = info->reg_addr + addr;
3730
3731 if (addr >= 0x80)
3732 reg_addr += info->port_num * 32;
3733 else if (addr >= 0x40)
3734 reg_addr += info->port_num * 16;
3735
3736 return reg_addr;
3737}
3738
3739static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3740{
3741 return readb(calc_regaddr(info, addr));
3742}
3743
3744static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3745{
3746 writeb(value, calc_regaddr(info, addr));
3747}
3748
3749static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3750{
3751 return readw(calc_regaddr(info, addr));
3752}
3753
3754static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3755{
3756 writew(value, calc_regaddr(info, addr));
3757}
3758
3759static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3760{
3761 return readl(calc_regaddr(info, addr));
3762}
3763
3764static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3765{
3766 writel(value, calc_regaddr(info, addr));
3767}
3768
3769static void rdma_reset(struct slgt_info *info)
3770{
3771 unsigned int i;
3772
3773 /* set reset bit */
3774 wr_reg32(info, RDCSR, BIT1);
3775
3776 /* wait for enable bit cleared */
3777 for(i=0 ; i < 1000 ; i++)
3778 if (!(rd_reg32(info, RDCSR) & BIT0))
3779 break;
3780}
3781
3782static void tdma_reset(struct slgt_info *info)
3783{
3784 unsigned int i;
3785
3786 /* set reset bit */
3787 wr_reg32(info, TDCSR, BIT1);
3788
3789 /* wait for enable bit cleared */
3790 for(i=0 ; i < 1000 ; i++)
3791 if (!(rd_reg32(info, TDCSR) & BIT0))
3792 break;
3793}
3794
3795/*
3796 * enable internal loopback
3797 * TxCLK and RxCLK are generated from BRG
3798 * and TxD is looped back to RxD internally.
3799 */
3800static void enable_loopback(struct slgt_info *info)
3801{
3802 /* SCR (serial control) BIT2=loopback enable */
3803 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3804
3805 if (info->params.mode != MGSL_MODE_ASYNC) {
3806 /* CCR (clock control)
3807 * 07..05 tx clock source (010 = BRG)
3808 * 04..02 rx clock source (010 = BRG)
3809 * 01 auxclk enable (0 = disable)
3810 * 00 BRG enable (1 = enable)
3811 *
3812 * 0100 1001
3813 */
3814 wr_reg8(info, CCR, 0x49);
3815
3816 /* set speed if available, otherwise use default */
3817 if (info->params.clock_speed)
3818 set_rate(info, info->params.clock_speed);
3819 else
3820 set_rate(info, 3686400);
3821 }
3822}
3823
3824/*
3825 * set baud rate generator to specified rate
3826 */
3827static void set_rate(struct slgt_info *info, u32 rate)
3828{
3829 unsigned int div;
3830 unsigned int osc = info->base_clock;
3831
3832 /* div = osc/rate - 1
3833 *
3834 * Round div up if osc/rate is not integer to
3835 * force to next slowest rate.
3836 */
3837
3838 if (rate) {
3839 div = osc/rate;
3840 if (!(osc % rate) && div)
3841 div--;
3842 wr_reg16(info, BDR, (unsigned short)div);
3843 }
3844}
3845
3846static void rx_stop(struct slgt_info *info)
3847{
3848 unsigned short val;
3849
3850 /* disable and reset receiver */
3851 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3852 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3853 wr_reg16(info, RCR, val); /* clear reset bit */
3854
3855 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3856
3857 /* clear pending rx interrupts */
3858 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3859
3860 rdma_reset(info);
3861
3862 info->rx_enabled = false;
3863 info->rx_restart = false;
3864}
3865
3866static void rx_start(struct slgt_info *info)
3867{
3868 unsigned short val;
3869
3870 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3871
3872 /* clear pending rx overrun IRQ */
3873 wr_reg16(info, SSR, IRQ_RXOVER);
3874
3875 /* reset and disable receiver */
3876 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3877 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3878 wr_reg16(info, RCR, val); /* clear reset bit */
3879
3880 rdma_reset(info);
3881 reset_rbufs(info);
3882
3883 if (info->rx_pio) {
3884 /* rx request when rx FIFO not empty */
3885 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3886 slgt_irq_on(info, IRQ_RXDATA);
3887 if (info->params.mode == MGSL_MODE_ASYNC) {
3888 /* enable saving of rx status */
3889 wr_reg32(info, RDCSR, BIT6);
3890 }
3891 } else {
3892 /* rx request when rx FIFO half full */
3893 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3894 /* set 1st descriptor address */
3895 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3896
3897 if (info->params.mode != MGSL_MODE_ASYNC) {
3898 /* enable rx DMA and DMA interrupt */
3899 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3900 } else {
3901 /* enable saving of rx status, rx DMA and DMA interrupt */
3902 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3903 }
3904 }
3905
3906 slgt_irq_on(info, IRQ_RXOVER);
3907
3908 /* enable receiver */
3909 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3910
3911 info->rx_restart = false;
3912 info->rx_enabled = true;
3913}
3914
3915static void tx_start(struct slgt_info *info)
3916{
3917 if (!info->tx_enabled) {
3918 wr_reg16(info, TCR,
3919 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3920 info->tx_enabled = true;
3921 }
3922
3923 if (desc_count(info->tbufs[info->tbuf_start])) {
3924 info->drop_rts_on_tx_done = false;
3925
3926 if (info->params.mode != MGSL_MODE_ASYNC) {
3927 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3928 get_gtsignals(info);
3929 if (!(info->signals & SerialSignal_RTS)) {
3930 info->signals |= SerialSignal_RTS;
3931 set_gtsignals(info);
3932 info->drop_rts_on_tx_done = true;
3933 }
3934 }
3935
3936 slgt_irq_off(info, IRQ_TXDATA);
3937 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3938 /* clear tx idle and underrun status bits */
3939 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3940 } else {
3941 slgt_irq_off(info, IRQ_TXDATA);
3942 slgt_irq_on(info, IRQ_TXIDLE);
3943 /* clear tx idle status bit */
3944 wr_reg16(info, SSR, IRQ_TXIDLE);
3945 }
3946 /* set 1st descriptor address and start DMA */
3947 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3948 wr_reg32(info, TDCSR, BIT2 + BIT0);
3949 info->tx_active = true;
3950 }
3951}
3952
3953static void tx_stop(struct slgt_info *info)
3954{
3955 unsigned short val;
3956
3957 del_timer(&info->tx_timer);
3958
3959 tdma_reset(info);
3960
3961 /* reset and disable transmitter */
3962 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3963 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3964
3965 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3966
3967 /* clear tx idle and underrun status bit */
3968 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3969
3970 reset_tbufs(info);
3971
3972 info->tx_enabled = false;
3973 info->tx_active = false;
3974}
3975
3976static void reset_port(struct slgt_info *info)
3977{
3978 if (!info->reg_addr)
3979 return;
3980
3981 tx_stop(info);
3982 rx_stop(info);
3983
3984 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3985 set_gtsignals(info);
3986
3987 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3988}
3989
3990static void reset_adapter(struct slgt_info *info)
3991{
3992 int i;
3993 for (i=0; i < info->port_count; ++i) {
3994 if (info->port_array[i])
3995 reset_port(info->port_array[i]);
3996 }
3997}
3998
3999static void async_mode(struct slgt_info *info)
4000{
4001 unsigned short val;
4002
4003 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4004 tx_stop(info);
4005 rx_stop(info);
4006
4007 /* TCR (tx control)
4008 *
4009 * 15..13 mode, 010=async
4010 * 12..10 encoding, 000=NRZ
4011 * 09 parity enable
4012 * 08 1=odd parity, 0=even parity
4013 * 07 1=RTS driver control
4014 * 06 1=break enable
4015 * 05..04 character length
4016 * 00=5 bits
4017 * 01=6 bits
4018 * 10=7 bits
4019 * 11=8 bits
4020 * 03 0=1 stop bit, 1=2 stop bits
4021 * 02 reset
4022 * 01 enable
4023 * 00 auto-CTS enable
4024 */
4025 val = 0x4000;
4026
4027 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4028 val |= BIT7;
4029
4030 if (info->params.parity != ASYNC_PARITY_NONE) {
4031 val |= BIT9;
4032 if (info->params.parity == ASYNC_PARITY_ODD)
4033 val |= BIT8;
4034 }
4035
4036 switch (info->params.data_bits)
4037 {
4038 case 6: val |= BIT4; break;
4039 case 7: val |= BIT5; break;
4040 case 8: val |= BIT5 + BIT4; break;
4041 }
4042
4043 if (info->params.stop_bits != 1)
4044 val |= BIT3;
4045
4046 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4047 val |= BIT0;
4048
4049 wr_reg16(info, TCR, val);
4050
4051 /* RCR (rx control)
4052 *
4053 * 15..13 mode, 010=async
4054 * 12..10 encoding, 000=NRZ
4055 * 09 parity enable
4056 * 08 1=odd parity, 0=even parity
4057 * 07..06 reserved, must be 0
4058 * 05..04 character length
4059 * 00=5 bits
4060 * 01=6 bits
4061 * 10=7 bits
4062 * 11=8 bits
4063 * 03 reserved, must be zero
4064 * 02 reset
4065 * 01 enable
4066 * 00 auto-DCD enable
4067 */
4068 val = 0x4000;
4069
4070 if (info->params.parity != ASYNC_PARITY_NONE) {
4071 val |= BIT9;
4072 if (info->params.parity == ASYNC_PARITY_ODD)
4073 val |= BIT8;
4074 }
4075
4076 switch (info->params.data_bits)
4077 {
4078 case 6: val |= BIT4; break;
4079 case 7: val |= BIT5; break;
4080 case 8: val |= BIT5 + BIT4; break;
4081 }
4082
4083 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4084 val |= BIT0;
4085
4086 wr_reg16(info, RCR, val);
4087
4088 /* CCR (clock control)
4089 *
4090 * 07..05 011 = tx clock source is BRG/16
4091 * 04..02 010 = rx clock source is BRG
4092 * 01 0 = auxclk disabled
4093 * 00 1 = BRG enabled
4094 *
4095 * 0110 1001
4096 */
4097 wr_reg8(info, CCR, 0x69);
4098
4099 msc_set_vcr(info);
4100
4101 /* SCR (serial control)
4102 *
4103 * 15 1=tx req on FIFO half empty
4104 * 14 1=rx req on FIFO half full
4105 * 13 tx data IRQ enable
4106 * 12 tx idle IRQ enable
4107 * 11 rx break on IRQ enable
4108 * 10 rx data IRQ enable
4109 * 09 rx break off IRQ enable
4110 * 08 overrun IRQ enable
4111 * 07 DSR IRQ enable
4112 * 06 CTS IRQ enable
4113 * 05 DCD IRQ enable
4114 * 04 RI IRQ enable
4115 * 03 0=16x sampling, 1=8x sampling
4116 * 02 1=txd->rxd internal loopback enable
4117 * 01 reserved, must be zero
4118 * 00 1=master IRQ enable
4119 */
4120 val = BIT15 + BIT14 + BIT0;
4121 /* JCR[8] : 1 = x8 async mode feature available */
4122 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4123 ((info->base_clock < (info->params.data_rate * 16)) ||
4124 (info->base_clock % (info->params.data_rate * 16)))) {
4125 /* use 8x sampling */
4126 val |= BIT3;
4127 set_rate(info, info->params.data_rate * 8);
4128 } else {
4129 /* use 16x sampling */
4130 set_rate(info, info->params.data_rate * 16);
4131 }
4132 wr_reg16(info, SCR, val);
4133
4134 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4135
4136 if (info->params.loopback)
4137 enable_loopback(info);
4138}
4139
4140static void sync_mode(struct slgt_info *info)
4141{
4142 unsigned short val;
4143
4144 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4145 tx_stop(info);
4146 rx_stop(info);
4147
4148 /* TCR (tx control)
4149 *
4150 * 15..13 mode
4151 * 000=HDLC/SDLC
4152 * 001=raw bit synchronous
4153 * 010=asynchronous/isochronous
4154 * 011=monosync byte synchronous
4155 * 100=bisync byte synchronous
4156 * 101=xsync byte synchronous
4157 * 12..10 encoding
4158 * 09 CRC enable
4159 * 08 CRC32
4160 * 07 1=RTS driver control
4161 * 06 preamble enable
4162 * 05..04 preamble length
4163 * 03 share open/close flag
4164 * 02 reset
4165 * 01 enable
4166 * 00 auto-CTS enable
4167 */
4168 val = BIT2;
4169
4170 switch(info->params.mode) {
4171 case MGSL_MODE_XSYNC:
4172 val |= BIT15 + BIT13;
4173 break;
4174 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4175 case MGSL_MODE_BISYNC: val |= BIT15; break;
4176 case MGSL_MODE_RAW: val |= BIT13; break;
4177 }
4178 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4179 val |= BIT7;
4180
4181 switch(info->params.encoding)
4182 {
4183 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4184 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4185 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4186 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4187 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4188 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4189 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4190 }
4191
4192 switch (info->params.crc_type & HDLC_CRC_MASK)
4193 {
4194 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4195 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4196 }
4197
4198 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4199 val |= BIT6;
4200
4201 switch (info->params.preamble_length)
4202 {
4203 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4204 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4205 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4206 }
4207
4208 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4209 val |= BIT0;
4210
4211 wr_reg16(info, TCR, val);
4212
4213 /* TPR (transmit preamble) */
4214
4215 switch (info->params.preamble)
4216 {
4217 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4218 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4219 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4220 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4221 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4222 default: val = 0x7e; break;
4223 }
4224 wr_reg8(info, TPR, (unsigned char)val);
4225
4226 /* RCR (rx control)
4227 *
4228 * 15..13 mode
4229 * 000=HDLC/SDLC
4230 * 001=raw bit synchronous
4231 * 010=asynchronous/isochronous
4232 * 011=monosync byte synchronous
4233 * 100=bisync byte synchronous
4234 * 101=xsync byte synchronous
4235 * 12..10 encoding
4236 * 09 CRC enable
4237 * 08 CRC32
4238 * 07..03 reserved, must be 0
4239 * 02 reset
4240 * 01 enable
4241 * 00 auto-DCD enable
4242 */
4243 val = 0;
4244
4245 switch(info->params.mode) {
4246 case MGSL_MODE_XSYNC:
4247 val |= BIT15 + BIT13;
4248 break;
4249 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4250 case MGSL_MODE_BISYNC: val |= BIT15; break;
4251 case MGSL_MODE_RAW: val |= BIT13; break;
4252 }
4253
4254 switch(info->params.encoding)
4255 {
4256 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4257 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4258 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4259 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4260 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4261 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4262 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4263 }
4264
4265 switch (info->params.crc_type & HDLC_CRC_MASK)
4266 {
4267 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4268 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4269 }
4270
4271 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4272 val |= BIT0;
4273
4274 wr_reg16(info, RCR, val);
4275
4276 /* CCR (clock control)
4277 *
4278 * 07..05 tx clock source
4279 * 04..02 rx clock source
4280 * 01 auxclk enable
4281 * 00 BRG enable
4282 */
4283 val = 0;
4284
4285 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4286 {
4287 // when RxC source is DPLL, BRG generates 16X DPLL
4288 // reference clock, so take TxC from BRG/16 to get
4289 // transmit clock at actual data rate
4290 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4291 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4292 else
4293 val |= BIT6; /* 010, txclk = BRG */
4294 }
4295 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4296 val |= BIT7; /* 100, txclk = DPLL Input */
4297 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4298 val |= BIT5; /* 001, txclk = RXC Input */
4299
4300 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4301 val |= BIT3; /* 010, rxclk = BRG */
4302 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4303 val |= BIT4; /* 100, rxclk = DPLL */
4304 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4305 val |= BIT2; /* 001, rxclk = TXC Input */
4306
4307 if (info->params.clock_speed)
4308 val |= BIT1 + BIT0;
4309
4310 wr_reg8(info, CCR, (unsigned char)val);
4311
4312 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4313 {
4314 // program DPLL mode
4315 switch(info->params.encoding)
4316 {
4317 case HDLC_ENCODING_BIPHASE_MARK:
4318 case HDLC_ENCODING_BIPHASE_SPACE:
4319 val = BIT7; break;
4320 case HDLC_ENCODING_BIPHASE_LEVEL:
4321 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4322 val = BIT7 + BIT6; break;
4323 default: val = BIT6; // NRZ encodings
4324 }
4325 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4326
4327 // DPLL requires a 16X reference clock from BRG
4328 set_rate(info, info->params.clock_speed * 16);
4329 }
4330 else
4331 set_rate(info, info->params.clock_speed);
4332
4333 tx_set_idle(info);
4334
4335 msc_set_vcr(info);
4336
4337 /* SCR (serial control)
4338 *
4339 * 15 1=tx req on FIFO half empty
4340 * 14 1=rx req on FIFO half full
4341 * 13 tx data IRQ enable
4342 * 12 tx idle IRQ enable
4343 * 11 underrun IRQ enable
4344 * 10 rx data IRQ enable
4345 * 09 rx idle IRQ enable
4346 * 08 overrun IRQ enable
4347 * 07 DSR IRQ enable
4348 * 06 CTS IRQ enable
4349 * 05 DCD IRQ enable
4350 * 04 RI IRQ enable
4351 * 03 reserved, must be zero
4352 * 02 1=txd->rxd internal loopback enable
4353 * 01 reserved, must be zero
4354 * 00 1=master IRQ enable
4355 */
4356 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4357
4358 if (info->params.loopback)
4359 enable_loopback(info);
4360}
4361
4362/*
4363 * set transmit idle mode
4364 */
4365static void tx_set_idle(struct slgt_info *info)
4366{
4367 unsigned char val;
4368 unsigned short tcr;
4369
4370 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4371 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4372 */
4373 tcr = rd_reg16(info, TCR);
4374 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4375 /* disable preamble, set idle size to 16 bits */
4376 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4377 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4378 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4379 } else if (!(tcr & BIT6)) {
4380 /* preamble is disabled, set idle size to 8 bits */
4381 tcr &= ~(BIT5 + BIT4);
4382 }
4383 wr_reg16(info, TCR, tcr);
4384
4385 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4386 /* LSB of custom tx idle specified in tx idle register */
4387 val = (unsigned char)(info->idle_mode & 0xff);
4388 } else {
4389 /* standard 8 bit idle patterns */
4390 switch(info->idle_mode)
4391 {
4392 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4393 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4394 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4395 case HDLC_TXIDLE_ZEROS:
4396 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4397 default: val = 0xff;
4398 }
4399 }
4400
4401 wr_reg8(info, TIR, val);
4402}
4403
4404/*
4405 * get state of V24 status (input) signals
4406 */
4407static void get_gtsignals(struct slgt_info *info)
4408{
4409 unsigned short status = rd_reg16(info, SSR);
4410
4411 /* clear all serial signals except RTS and DTR */
4412 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4413
4414 if (status & BIT3)
4415 info->signals |= SerialSignal_DSR;
4416 if (status & BIT2)
4417 info->signals |= SerialSignal_CTS;
4418 if (status & BIT1)
4419 info->signals |= SerialSignal_DCD;
4420 if (status & BIT0)
4421 info->signals |= SerialSignal_RI;
4422}
4423
4424/*
4425 * set V.24 Control Register based on current configuration
4426 */
4427static void msc_set_vcr(struct slgt_info *info)
4428{
4429 unsigned char val = 0;
4430
4431 /* VCR (V.24 control)
4432 *
4433 * 07..04 serial IF select
4434 * 03 DTR
4435 * 02 RTS
4436 * 01 LL
4437 * 00 RL
4438 */
4439
4440 switch(info->if_mode & MGSL_INTERFACE_MASK)
4441 {
4442 case MGSL_INTERFACE_RS232:
4443 val |= BIT5; /* 0010 */
4444 break;
4445 case MGSL_INTERFACE_V35:
4446 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4447 break;
4448 case MGSL_INTERFACE_RS422:
4449 val |= BIT6; /* 0100 */
4450 break;
4451 }
4452
4453 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4454 val |= BIT4;
4455 if (info->signals & SerialSignal_DTR)
4456 val |= BIT3;
4457 if (info->signals & SerialSignal_RTS)
4458 val |= BIT2;
4459 if (info->if_mode & MGSL_INTERFACE_LL)
4460 val |= BIT1;
4461 if (info->if_mode & MGSL_INTERFACE_RL)
4462 val |= BIT0;
4463 wr_reg8(info, VCR, val);
4464}
4465
4466/*
4467 * set state of V24 control (output) signals
4468 */
4469static void set_gtsignals(struct slgt_info *info)
4470{
4471 unsigned char val = rd_reg8(info, VCR);
4472 if (info->signals & SerialSignal_DTR)
4473 val |= BIT3;
4474 else
4475 val &= ~BIT3;
4476 if (info->signals & SerialSignal_RTS)
4477 val |= BIT2;
4478 else
4479 val &= ~BIT2;
4480 wr_reg8(info, VCR, val);
4481}
4482
4483/*
4484 * free range of receive DMA buffers (i to last)
4485 */
4486static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4487{
4488 int done = 0;
4489
4490 while(!done) {
4491 /* reset current buffer for reuse */
4492 info->rbufs[i].status = 0;
4493 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4494 if (i == last)
4495 done = 1;
4496 if (++i == info->rbuf_count)
4497 i = 0;
4498 }
4499 info->rbuf_current = i;
4500}
4501
4502/*
4503 * mark all receive DMA buffers as free
4504 */
4505static void reset_rbufs(struct slgt_info *info)
4506{
4507 free_rbufs(info, 0, info->rbuf_count - 1);
4508 info->rbuf_fill_index = 0;
4509 info->rbuf_fill_count = 0;
4510}
4511
4512/*
4513 * pass receive HDLC frame to upper layer
4514 *
4515 * return true if frame available, otherwise false
4516 */
4517static bool rx_get_frame(struct slgt_info *info)
4518{
4519 unsigned int start, end;
4520 unsigned short status;
4521 unsigned int framesize = 0;
4522 unsigned long flags;
4523 struct tty_struct *tty = info->port.tty;
4524 unsigned char addr_field = 0xff;
4525 unsigned int crc_size = 0;
4526
4527 switch (info->params.crc_type & HDLC_CRC_MASK) {
4528 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4529 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4530 }
4531
4532check_again:
4533
4534 framesize = 0;
4535 addr_field = 0xff;
4536 start = end = info->rbuf_current;
4537
4538 for (;;) {
4539 if (!desc_complete(info->rbufs[end]))
4540 goto cleanup;
4541
4542 if (framesize == 0 && info->params.addr_filter != 0xff)
4543 addr_field = info->rbufs[end].buf[0];
4544
4545 framesize += desc_count(info->rbufs[end]);
4546
4547 if (desc_eof(info->rbufs[end]))
4548 break;
4549
4550 if (++end == info->rbuf_count)
4551 end = 0;
4552
4553 if (end == info->rbuf_current) {
4554 if (info->rx_enabled){
4555 spin_lock_irqsave(&info->lock,flags);
4556 rx_start(info);
4557 spin_unlock_irqrestore(&info->lock,flags);
4558 }
4559 goto cleanup;
4560 }
4561 }
4562
4563 /* status
4564 *
4565 * 15 buffer complete
4566 * 14..06 reserved
4567 * 05..04 residue
4568 * 02 eof (end of frame)
4569 * 01 CRC error
4570 * 00 abort
4571 */
4572 status = desc_status(info->rbufs[end]);
4573
4574 /* ignore CRC bit if not using CRC (bit is undefined) */
4575 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4576 status &= ~BIT1;
4577
4578 if (framesize == 0 ||
4579 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4580 free_rbufs(info, start, end);
4581 goto check_again;
4582 }
4583
4584 if (framesize < (2 + crc_size) || status & BIT0) {
4585 info->icount.rxshort++;
4586 framesize = 0;
4587 } else if (status & BIT1) {
4588 info->icount.rxcrc++;
4589 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4590 framesize = 0;
4591 }
4592
4593#if SYNCLINK_GENERIC_HDLC
4594 if (framesize == 0) {
4595 info->netdev->stats.rx_errors++;
4596 info->netdev->stats.rx_frame_errors++;
4597 }
4598#endif
4599
4600 DBGBH(("%s rx frame status=%04X size=%d\n",
4601 info->device_name, status, framesize));
4602 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4603
4604 if (framesize) {
4605 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4606 framesize -= crc_size;
4607 crc_size = 0;
4608 }
4609
4610 if (framesize > info->max_frame_size + crc_size)
4611 info->icount.rxlong++;
4612 else {
4613 /* copy dma buffer(s) to contiguous temp buffer */
4614 int copy_count = framesize;
4615 int i = start;
4616 unsigned char *p = info->tmp_rbuf;
4617 info->tmp_rbuf_count = framesize;
4618
4619 info->icount.rxok++;
4620
4621 while(copy_count) {
4622 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4623 memcpy(p, info->rbufs[i].buf, partial_count);
4624 p += partial_count;
4625 copy_count -= partial_count;
4626 if (++i == info->rbuf_count)
4627 i = 0;
4628 }
4629
4630 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4631 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4632 framesize++;
4633 }
4634
4635#if SYNCLINK_GENERIC_HDLC
4636 if (info->netcount)
4637 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4638 else
4639#endif
4640 ldisc_receive_buf(tty, info->tmp_rbuf, NULL,
4641 framesize);
4642 }
4643 }
4644 free_rbufs(info, start, end);
4645 return true;
4646
4647cleanup:
4648 return false;
4649}
4650
4651/*
4652 * pass receive buffer (RAW synchronous mode) to tty layer
4653 * return true if buffer available, otherwise false
4654 */
4655static bool rx_get_buf(struct slgt_info *info)
4656{
4657 unsigned int i = info->rbuf_current;
4658 unsigned int count;
4659
4660 if (!desc_complete(info->rbufs[i]))
4661 return false;
4662 count = desc_count(info->rbufs[i]);
4663 switch(info->params.mode) {
4664 case MGSL_MODE_MONOSYNC:
4665 case MGSL_MODE_BISYNC:
4666 case MGSL_MODE_XSYNC:
4667 /* ignore residue in byte synchronous modes */
4668 if (desc_residue(info->rbufs[i]))
4669 count--;
4670 break;
4671 }
4672 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4673 DBGINFO(("rx_get_buf size=%d\n", count));
4674 if (count)
4675 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, NULL,
4676 count);
4677 free_rbufs(info, i, i);
4678 return true;
4679}
4680
4681static void reset_tbufs(struct slgt_info *info)
4682{
4683 unsigned int i;
4684 info->tbuf_current = 0;
4685 for (i=0 ; i < info->tbuf_count ; i++) {
4686 info->tbufs[i].status = 0;
4687 info->tbufs[i].count = 0;
4688 }
4689}
4690
4691/*
4692 * return number of free transmit DMA buffers
4693 */
4694static unsigned int free_tbuf_count(struct slgt_info *info)
4695{
4696 unsigned int count = 0;
4697 unsigned int i = info->tbuf_current;
4698
4699 do
4700 {
4701 if (desc_count(info->tbufs[i]))
4702 break; /* buffer in use */
4703 ++count;
4704 if (++i == info->tbuf_count)
4705 i=0;
4706 } while (i != info->tbuf_current);
4707
4708 /* if tx DMA active, last zero count buffer is in use */
4709 if (count && (rd_reg32(info, TDCSR) & BIT0))
4710 --count;
4711
4712 return count;
4713}
4714
4715/*
4716 * return number of bytes in unsent transmit DMA buffers
4717 * and the serial controller tx FIFO
4718 */
4719static unsigned int tbuf_bytes(struct slgt_info *info)
4720{
4721 unsigned int total_count = 0;
4722 unsigned int i = info->tbuf_current;
4723 unsigned int reg_value;
4724 unsigned int count;
4725 unsigned int active_buf_count = 0;
4726
4727 /*
4728 * Add descriptor counts for all tx DMA buffers.
4729 * If count is zero (cleared by DMA controller after read),
4730 * the buffer is complete or is actively being read from.
4731 *
4732 * Record buf_count of last buffer with zero count starting
4733 * from current ring position. buf_count is mirror
4734 * copy of count and is not cleared by serial controller.
4735 * If DMA controller is active, that buffer is actively
4736 * being read so add to total.
4737 */
4738 do {
4739 count = desc_count(info->tbufs[i]);
4740 if (count)
4741 total_count += count;
4742 else if (!total_count)
4743 active_buf_count = info->tbufs[i].buf_count;
4744 if (++i == info->tbuf_count)
4745 i = 0;
4746 } while (i != info->tbuf_current);
4747
4748 /* read tx DMA status register */
4749 reg_value = rd_reg32(info, TDCSR);
4750
4751 /* if tx DMA active, last zero count buffer is in use */
4752 if (reg_value & BIT0)
4753 total_count += active_buf_count;
4754
4755 /* add tx FIFO count = reg_value[15..8] */
4756 total_count += (reg_value >> 8) & 0xff;
4757
4758 /* if transmitter active add one byte for shift register */
4759 if (info->tx_active)
4760 total_count++;
4761
4762 return total_count;
4763}
4764
4765/*
4766 * load data into transmit DMA buffer ring and start transmitter if needed
4767 * return true if data accepted, otherwise false (buffers full)
4768 */
4769static bool tx_load(struct slgt_info *info, const u8 *buf, unsigned int size)
4770{
4771 unsigned short count;
4772 unsigned int i;
4773 struct slgt_desc *d;
4774
4775 /* check required buffer space */
4776 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4777 return false;
4778
4779 DBGDATA(info, buf, size, "tx");
4780
4781 /*
4782 * copy data to one or more DMA buffers in circular ring
4783 * tbuf_start = first buffer for this data
4784 * tbuf_current = next free buffer
4785 *
4786 * Copy all data before making data visible to DMA controller by
4787 * setting descriptor count of the first buffer.
4788 * This prevents an active DMA controller from reading the first DMA
4789 * buffers of a frame and stopping before the final buffers are filled.
4790 */
4791
4792 info->tbuf_start = i = info->tbuf_current;
4793
4794 while (size) {
4795 d = &info->tbufs[i];
4796
4797 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4798 memcpy(d->buf, buf, count);
4799
4800 size -= count;
4801 buf += count;
4802
4803 /*
4804 * set EOF bit for last buffer of HDLC frame or
4805 * for every buffer in raw mode
4806 */
4807 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4808 info->params.mode == MGSL_MODE_RAW)
4809 set_desc_eof(*d, 1);
4810 else
4811 set_desc_eof(*d, 0);
4812
4813 /* set descriptor count for all but first buffer */
4814 if (i != info->tbuf_start)
4815 set_desc_count(*d, count);
4816 d->buf_count = count;
4817
4818 if (++i == info->tbuf_count)
4819 i = 0;
4820 }
4821
4822 info->tbuf_current = i;
4823
4824 /* set first buffer count to make new data visible to DMA controller */
4825 d = &info->tbufs[info->tbuf_start];
4826 set_desc_count(*d, d->buf_count);
4827
4828 /* start transmitter if needed and update transmit timeout */
4829 if (!info->tx_active)
4830 tx_start(info);
4831 update_tx_timer(info);
4832
4833 return true;
4834}
4835
4836static int register_test(struct slgt_info *info)
4837{
4838 static unsigned short patterns[] =
4839 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4840 static unsigned int count = ARRAY_SIZE(patterns);
4841 unsigned int i;
4842 int rc = 0;
4843
4844 for (i=0 ; i < count ; i++) {
4845 wr_reg16(info, TIR, patterns[i]);
4846 wr_reg16(info, BDR, patterns[(i+1)%count]);
4847 if ((rd_reg16(info, TIR) != patterns[i]) ||
4848 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4849 rc = -ENODEV;
4850 break;
4851 }
4852 }
4853 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4854 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4855 return rc;
4856}
4857
4858static int irq_test(struct slgt_info *info)
4859{
4860 unsigned long timeout;
4861 unsigned long flags;
4862 struct tty_struct *oldtty = info->port.tty;
4863 u32 speed = info->params.data_rate;
4864
4865 info->params.data_rate = 921600;
4866 info->port.tty = NULL;
4867
4868 spin_lock_irqsave(&info->lock, flags);
4869 async_mode(info);
4870 slgt_irq_on(info, IRQ_TXIDLE);
4871
4872 /* enable transmitter */
4873 wr_reg16(info, TCR,
4874 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4875
4876 /* write one byte and wait for tx idle */
4877 wr_reg16(info, TDR, 0);
4878
4879 /* assume failure */
4880 info->init_error = DiagStatus_IrqFailure;
4881 info->irq_occurred = false;
4882
4883 spin_unlock_irqrestore(&info->lock, flags);
4884
4885 timeout=100;
4886 while(timeout-- && !info->irq_occurred)
4887 msleep_interruptible(10);
4888
4889 spin_lock_irqsave(&info->lock,flags);
4890 reset_port(info);
4891 spin_unlock_irqrestore(&info->lock,flags);
4892
4893 info->params.data_rate = speed;
4894 info->port.tty = oldtty;
4895
4896 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4897 return info->irq_occurred ? 0 : -ENODEV;
4898}
4899
4900static int loopback_test_rx(struct slgt_info *info)
4901{
4902 unsigned char *src, *dest;
4903 int count;
4904
4905 if (desc_complete(info->rbufs[0])) {
4906 count = desc_count(info->rbufs[0]);
4907 src = info->rbufs[0].buf;
4908 dest = info->tmp_rbuf;
4909
4910 for( ; count ; count-=2, src+=2) {
4911 /* src=data byte (src+1)=status byte */
4912 if (!(*(src+1) & (BIT9 + BIT8))) {
4913 *dest = *src;
4914 dest++;
4915 info->tmp_rbuf_count++;
4916 }
4917 }
4918 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4919 return 1;
4920 }
4921 return 0;
4922}
4923
4924static int loopback_test(struct slgt_info *info)
4925{
4926#define TESTFRAMESIZE 20
4927
4928 unsigned long timeout;
4929 u16 count;
4930 unsigned char buf[TESTFRAMESIZE];
4931 int rc = -ENODEV;
4932 unsigned long flags;
4933
4934 struct tty_struct *oldtty = info->port.tty;
4935 MGSL_PARAMS params;
4936
4937 memcpy(¶ms, &info->params, sizeof(params));
4938
4939 info->params.mode = MGSL_MODE_ASYNC;
4940 info->params.data_rate = 921600;
4941 info->params.loopback = 1;
4942 info->port.tty = NULL;
4943
4944 /* build and send transmit frame */
4945 for (count = 0; count < TESTFRAMESIZE; ++count)
4946 buf[count] = (unsigned char)count;
4947
4948 info->tmp_rbuf_count = 0;
4949 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4950
4951 /* program hardware for HDLC and enabled receiver */
4952 spin_lock_irqsave(&info->lock,flags);
4953 async_mode(info);
4954 rx_start(info);
4955 tx_load(info, buf, count);
4956 spin_unlock_irqrestore(&info->lock, flags);
4957
4958 /* wait for receive complete */
4959 for (timeout = 100; timeout; --timeout) {
4960 msleep_interruptible(10);
4961 if (loopback_test_rx(info)) {
4962 rc = 0;
4963 break;
4964 }
4965 }
4966
4967 /* verify received frame length and contents */
4968 if (!rc && (info->tmp_rbuf_count != count ||
4969 memcmp(buf, info->tmp_rbuf, count))) {
4970 rc = -ENODEV;
4971 }
4972
4973 spin_lock_irqsave(&info->lock,flags);
4974 reset_adapter(info);
4975 spin_unlock_irqrestore(&info->lock,flags);
4976
4977 memcpy(&info->params, ¶ms, sizeof(info->params));
4978 info->port.tty = oldtty;
4979
4980 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4981 return rc;
4982}
4983
4984static int adapter_test(struct slgt_info *info)
4985{
4986 DBGINFO(("testing %s\n", info->device_name));
4987 if (register_test(info) < 0) {
4988 printk("register test failure %s addr=%08X\n",
4989 info->device_name, info->phys_reg_addr);
4990 } else if (irq_test(info) < 0) {
4991 printk("IRQ test failure %s IRQ=%d\n",
4992 info->device_name, info->irq_level);
4993 } else if (loopback_test(info) < 0) {
4994 printk("loopback test failure %s\n", info->device_name);
4995 }
4996 return info->init_error;
4997}
4998
4999/*
5000 * transmit timeout handler
5001 */
5002static void tx_timeout(struct timer_list *t)
5003{
5004 struct slgt_info *info = from_timer(info, t, tx_timer);
5005 unsigned long flags;
5006
5007 DBGINFO(("%s tx_timeout\n", info->device_name));
5008 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5009 info->icount.txtimeout++;
5010 }
5011 spin_lock_irqsave(&info->lock,flags);
5012 tx_stop(info);
5013 spin_unlock_irqrestore(&info->lock,flags);
5014
5015#if SYNCLINK_GENERIC_HDLC
5016 if (info->netcount)
5017 hdlcdev_tx_done(info);
5018 else
5019#endif
5020 bh_transmit(info);
5021}
5022
5023/*
5024 * receive buffer polling timer
5025 */
5026static void rx_timeout(struct timer_list *t)
5027{
5028 struct slgt_info *info = from_timer(info, t, rx_timer);
5029 unsigned long flags;
5030
5031 DBGINFO(("%s rx_timeout\n", info->device_name));
5032 spin_lock_irqsave(&info->lock, flags);
5033 info->pending_bh |= BH_RECEIVE;
5034 spin_unlock_irqrestore(&info->lock, flags);
5035 bh_handler(&info->task);
5036}
5037
1/*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24/*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43/*#define DBGTBUF(info) dump_tbufs(info)*/
44/*#define DBGRBUF(info) dump_rbufs(info)*/
45
46
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/signal.h>
50#include <linux/sched.h>
51#include <linux/timer.h>
52#include <linux/interrupt.h>
53#include <linux/pci.h>
54#include <linux/tty.h>
55#include <linux/tty_flip.h>
56#include <linux/serial.h>
57#include <linux/major.h>
58#include <linux/string.h>
59#include <linux/fcntl.h>
60#include <linux/ptrace.h>
61#include <linux/ioport.h>
62#include <linux/mm.h>
63#include <linux/seq_file.h>
64#include <linux/slab.h>
65#include <linux/netdevice.h>
66#include <linux/vmalloc.h>
67#include <linux/init.h>
68#include <linux/delay.h>
69#include <linux/ioctl.h>
70#include <linux/termios.h>
71#include <linux/bitops.h>
72#include <linux/workqueue.h>
73#include <linux/hdlc.h>
74#include <linux/synclink.h>
75
76#include <asm/io.h>
77#include <asm/irq.h>
78#include <asm/dma.h>
79#include <asm/types.h>
80#include <linux/uaccess.h>
81
82#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
83#define SYNCLINK_GENERIC_HDLC 1
84#else
85#define SYNCLINK_GENERIC_HDLC 0
86#endif
87
88/*
89 * module identification
90 */
91static char *driver_name = "SyncLink GT";
92static char *slgt_driver_name = "synclink_gt";
93static char *tty_dev_prefix = "ttySLG";
94MODULE_LICENSE("GPL");
95#define MGSL_MAGIC 0x5401
96#define MAX_DEVICES 32
97
98static struct pci_device_id pci_table[] = {
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {0,}, /* terminate list */
104};
105MODULE_DEVICE_TABLE(pci, pci_table);
106
107static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108static void remove_one(struct pci_dev *dev);
109static struct pci_driver pci_driver = {
110 .name = "synclink_gt",
111 .id_table = pci_table,
112 .probe = init_one,
113 .remove = remove_one,
114};
115
116static bool pci_registered;
117
118/*
119 * module configuration and status
120 */
121static struct slgt_info *slgt_device_list;
122static int slgt_device_count;
123
124static int ttymajor;
125static int debug_level;
126static int maxframe[MAX_DEVICES];
127
128module_param(ttymajor, int, 0);
129module_param(debug_level, int, 0);
130module_param_array(maxframe, int, NULL, 0);
131
132MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
135
136/*
137 * tty support and callbacks
138 */
139static struct tty_driver *serial_driver;
140
141static int open(struct tty_struct *tty, struct file * filp);
142static void close(struct tty_struct *tty, struct file * filp);
143static void hangup(struct tty_struct *tty);
144static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
145
146static int write(struct tty_struct *tty, const unsigned char *buf, int count);
147static int put_char(struct tty_struct *tty, unsigned char ch);
148static void send_xchar(struct tty_struct *tty, char ch);
149static void wait_until_sent(struct tty_struct *tty, int timeout);
150static int write_room(struct tty_struct *tty);
151static void flush_chars(struct tty_struct *tty);
152static void flush_buffer(struct tty_struct *tty);
153static void tx_hold(struct tty_struct *tty);
154static void tx_release(struct tty_struct *tty);
155
156static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157static int chars_in_buffer(struct tty_struct *tty);
158static void throttle(struct tty_struct * tty);
159static void unthrottle(struct tty_struct * tty);
160static int set_break(struct tty_struct *tty, int break_state);
161
162/*
163 * generic HDLC support and callbacks
164 */
165#if SYNCLINK_GENERIC_HDLC
166#define dev_to_port(D) (dev_to_hdlc(D)->priv)
167static void hdlcdev_tx_done(struct slgt_info *info);
168static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169static int hdlcdev_init(struct slgt_info *info);
170static void hdlcdev_exit(struct slgt_info *info);
171#endif
172
173
174/*
175 * device specific structures, macros and functions
176 */
177
178#define SLGT_MAX_PORTS 4
179#define SLGT_REG_SIZE 256
180
181/*
182 * conditional wait facility
183 */
184struct cond_wait {
185 struct cond_wait *next;
186 wait_queue_head_t q;
187 wait_queue_t wait;
188 unsigned int data;
189};
190static void init_cond_wait(struct cond_wait *w, unsigned int data);
191static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193static void flush_cond_wait(struct cond_wait **head);
194
195/*
196 * DMA buffer descriptor and access macros
197 */
198struct slgt_desc
199{
200 __le16 count;
201 __le16 status;
202 __le32 pbuf; /* physical address of data buffer */
203 __le32 next; /* physical address of next descriptor */
204
205 /* driver book keeping */
206 char *buf; /* virtual address of data buffer */
207 unsigned int pdesc; /* physical address of this descriptor */
208 dma_addr_t buf_dma_addr;
209 unsigned short buf_count;
210};
211
212#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
214#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
215#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217#define desc_count(a) (le16_to_cpu((a).count))
218#define desc_status(a) (le16_to_cpu((a).status))
219#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
224
225struct _input_signal_events {
226 int ri_up;
227 int ri_down;
228 int dsr_up;
229 int dsr_down;
230 int dcd_up;
231 int dcd_down;
232 int cts_up;
233 int cts_down;
234};
235
236/*
237 * device instance data structure
238 */
239struct slgt_info {
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
242
243 struct slgt_info *next_device; /* device list link */
244
245 int magic;
246
247 char device_name[25];
248 struct pci_dev *pdev;
249
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
253
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
256
257 int line; /* tty line instance number */
258
259 struct mgsl_icount icount;
260
261 int timeout;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
265
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
270
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
273
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
275
276 struct work_struct task;
277 u32 pending_bh;
278 bool bh_requested;
279 bool bh_running;
280
281 int isr_overflow;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
284
285 /* device configuration */
286
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
290
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
292 u32 phys_reg_addr;
293 bool reg_addr_requested;
294
295 MGSL_PARAMS params; /* communications parameters */
296 u32 idle_mode;
297 u32 max_frame_size; /* as set by device config */
298
299 unsigned int rbuf_fill_level;
300 unsigned int rx_pio;
301 unsigned int if_mode;
302 unsigned int base_clock;
303 unsigned int xsync;
304 unsigned int xctrl;
305
306 /* device status */
307
308 bool rx_enabled;
309 bool rx_restart;
310
311 bool tx_enabled;
312 bool tx_active;
313
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
316
317 unsigned char *tx_buf;
318 int tx_count;
319
320 char *flag_buf;
321 bool drop_rts_on_tx_done;
322 struct _input_signal_events input_signal_events;
323
324 int dcd_chkcount; /* check counts to prevent */
325 int cts_chkcount; /* too many IRQs if a signal */
326 int dsr_chkcount; /* is floating */
327 int ri_chkcount;
328
329 char *bufs; /* virtual address of DMA buffer lists */
330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
331
332 unsigned int rbuf_count;
333 struct slgt_desc *rbufs;
334 unsigned int rbuf_current;
335 unsigned int rbuf_index;
336 unsigned int rbuf_fill_index;
337 unsigned short rbuf_fill_count;
338
339 unsigned int tbuf_count;
340 struct slgt_desc *tbufs;
341 unsigned int tbuf_current;
342 unsigned int tbuf_start;
343
344 unsigned char *tmp_rbuf;
345 unsigned int tmp_rbuf_count;
346
347 /* SPPP/Cisco HDLC device parts */
348
349 int netcount;
350 spinlock_t netlock;
351#if SYNCLINK_GENERIC_HDLC
352 struct net_device *netdev;
353#endif
354
355};
356
357static MGSL_PARAMS default_params = {
358 .mode = MGSL_MODE_HDLC,
359 .loopback = 0,
360 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
361 .encoding = HDLC_ENCODING_NRZI_SPACE,
362 .clock_speed = 0,
363 .addr_filter = 0xff,
364 .crc_type = HDLC_CRC_16_CCITT,
365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
367 .data_rate = 9600,
368 .data_bits = 8,
369 .stop_bits = 1,
370 .parity = ASYNC_PARITY_NONE
371};
372
373
374#define BH_RECEIVE 1
375#define BH_TRANSMIT 2
376#define BH_STATUS 4
377#define IO_PIN_SHUTDOWN_LIMIT 100
378
379#define DMABUFSIZE 256
380#define DESC_LIST_SIZE 4096
381
382#define MASK_PARITY BIT1
383#define MASK_FRAMING BIT0
384#define MASK_BREAK BIT14
385#define MASK_OVERRUN BIT4
386
387#define GSR 0x00 /* global status */
388#define JCR 0x04 /* JTAG control */
389#define IODR 0x08 /* GPIO direction */
390#define IOER 0x0c /* GPIO interrupt enable */
391#define IOVR 0x10 /* GPIO value */
392#define IOSR 0x14 /* GPIO interrupt status */
393#define TDR 0x80 /* tx data */
394#define RDR 0x80 /* rx data */
395#define TCR 0x82 /* tx control */
396#define TIR 0x84 /* tx idle */
397#define TPR 0x85 /* tx preamble */
398#define RCR 0x86 /* rx control */
399#define VCR 0x88 /* V.24 control */
400#define CCR 0x89 /* clock control */
401#define BDR 0x8a /* baud divisor */
402#define SCR 0x8c /* serial control */
403#define SSR 0x8e /* serial status */
404#define RDCSR 0x90 /* rx DMA control/status */
405#define TDCSR 0x94 /* tx DMA control/status */
406#define RDDAR 0x98 /* rx DMA descriptor address */
407#define TDDAR 0x9c /* tx DMA descriptor address */
408#define XSR 0x40 /* extended sync pattern */
409#define XCR 0x44 /* extended control */
410
411#define RXIDLE BIT14
412#define RXBREAK BIT14
413#define IRQ_TXDATA BIT13
414#define IRQ_TXIDLE BIT12
415#define IRQ_TXUNDER BIT11 /* HDLC */
416#define IRQ_RXDATA BIT10
417#define IRQ_RXIDLE BIT9 /* HDLC */
418#define IRQ_RXBREAK BIT9 /* async */
419#define IRQ_RXOVER BIT8
420#define IRQ_DSR BIT7
421#define IRQ_CTS BIT6
422#define IRQ_DCD BIT5
423#define IRQ_RI BIT4
424#define IRQ_ALL 0x3ff0
425#define IRQ_MASTER BIT0
426
427#define slgt_irq_on(info, mask) \
428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429#define slgt_irq_off(info, mask) \
430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
431
432static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
433static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
434static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
435static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
436static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
437static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
438
439static void msc_set_vcr(struct slgt_info *info);
440
441static int startup(struct slgt_info *info);
442static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
443static void shutdown(struct slgt_info *info);
444static void program_hw(struct slgt_info *info);
445static void change_params(struct slgt_info *info);
446
447static int register_test(struct slgt_info *info);
448static int irq_test(struct slgt_info *info);
449static int loopback_test(struct slgt_info *info);
450static int adapter_test(struct slgt_info *info);
451
452static void reset_adapter(struct slgt_info *info);
453static void reset_port(struct slgt_info *info);
454static void async_mode(struct slgt_info *info);
455static void sync_mode(struct slgt_info *info);
456
457static void rx_stop(struct slgt_info *info);
458static void rx_start(struct slgt_info *info);
459static void reset_rbufs(struct slgt_info *info);
460static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
461static void rdma_reset(struct slgt_info *info);
462static bool rx_get_frame(struct slgt_info *info);
463static bool rx_get_buf(struct slgt_info *info);
464
465static void tx_start(struct slgt_info *info);
466static void tx_stop(struct slgt_info *info);
467static void tx_set_idle(struct slgt_info *info);
468static unsigned int free_tbuf_count(struct slgt_info *info);
469static unsigned int tbuf_bytes(struct slgt_info *info);
470static void reset_tbufs(struct slgt_info *info);
471static void tdma_reset(struct slgt_info *info);
472static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
473
474static void get_signals(struct slgt_info *info);
475static void set_signals(struct slgt_info *info);
476static void enable_loopback(struct slgt_info *info);
477static void set_rate(struct slgt_info *info, u32 data_rate);
478
479static int bh_action(struct slgt_info *info);
480static void bh_handler(struct work_struct *work);
481static void bh_transmit(struct slgt_info *info);
482static void isr_serial(struct slgt_info *info);
483static void isr_rdma(struct slgt_info *info);
484static void isr_txeom(struct slgt_info *info, unsigned short status);
485static void isr_tdma(struct slgt_info *info);
486
487static int alloc_dma_bufs(struct slgt_info *info);
488static void free_dma_bufs(struct slgt_info *info);
489static int alloc_desc(struct slgt_info *info);
490static void free_desc(struct slgt_info *info);
491static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
493
494static int alloc_tmp_rbuf(struct slgt_info *info);
495static void free_tmp_rbuf(struct slgt_info *info);
496
497static void tx_timeout(unsigned long context);
498static void rx_timeout(unsigned long context);
499
500/*
501 * ioctl handlers
502 */
503static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
504static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506static int get_txidle(struct slgt_info *info, int __user *idle_mode);
507static int set_txidle(struct slgt_info *info, int idle_mode);
508static int tx_enable(struct slgt_info *info, int enable);
509static int tx_abort(struct slgt_info *info);
510static int rx_enable(struct slgt_info *info, int enable);
511static int modem_input_wait(struct slgt_info *info,int arg);
512static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
513static int tiocmget(struct tty_struct *tty);
514static int tiocmset(struct tty_struct *tty,
515 unsigned int set, unsigned int clear);
516static int set_break(struct tty_struct *tty, int break_state);
517static int get_interface(struct slgt_info *info, int __user *if_mode);
518static int set_interface(struct slgt_info *info, int if_mode);
519static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522static int get_xsync(struct slgt_info *info, int __user *if_mode);
523static int set_xsync(struct slgt_info *info, int if_mode);
524static int get_xctrl(struct slgt_info *info, int __user *if_mode);
525static int set_xctrl(struct slgt_info *info, int if_mode);
526
527/*
528 * driver functions
529 */
530static void add_device(struct slgt_info *info);
531static void device_init(int adapter_num, struct pci_dev *pdev);
532static int claim_resources(struct slgt_info *info);
533static void release_resources(struct slgt_info *info);
534
535/*
536 * DEBUG OUTPUT CODE
537 */
538#ifndef DBGINFO
539#define DBGINFO(fmt)
540#endif
541#ifndef DBGERR
542#define DBGERR(fmt)
543#endif
544#ifndef DBGBH
545#define DBGBH(fmt)
546#endif
547#ifndef DBGISR
548#define DBGISR(fmt)
549#endif
550
551#ifdef DBGDATA
552static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
553{
554 int i;
555 int linecount;
556 printk("%s %s data:\n",info->device_name, label);
557 while(count) {
558 linecount = (count > 16) ? 16 : count;
559 for(i=0; i < linecount; i++)
560 printk("%02X ",(unsigned char)data[i]);
561 for(;i<17;i++)
562 printk(" ");
563 for(i=0;i<linecount;i++) {
564 if (data[i]>=040 && data[i]<=0176)
565 printk("%c",data[i]);
566 else
567 printk(".");
568 }
569 printk("\n");
570 data += linecount;
571 count -= linecount;
572 }
573}
574#else
575#define DBGDATA(info, buf, size, label)
576#endif
577
578#ifdef DBGTBUF
579static void dump_tbufs(struct slgt_info *info)
580{
581 int i;
582 printk("tbuf_current=%d\n", info->tbuf_current);
583 for (i=0 ; i < info->tbuf_count ; i++) {
584 printk("%d: count=%04X status=%04X\n",
585 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
586 }
587}
588#else
589#define DBGTBUF(info)
590#endif
591
592#ifdef DBGRBUF
593static void dump_rbufs(struct slgt_info *info)
594{
595 int i;
596 printk("rbuf_current=%d\n", info->rbuf_current);
597 for (i=0 ; i < info->rbuf_count ; i++) {
598 printk("%d: count=%04X status=%04X\n",
599 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
600 }
601}
602#else
603#define DBGRBUF(info)
604#endif
605
606static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
607{
608#ifdef SANITY_CHECK
609 if (!info) {
610 printk("null struct slgt_info for (%s) in %s\n", devname, name);
611 return 1;
612 }
613 if (info->magic != MGSL_MAGIC) {
614 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
615 return 1;
616 }
617#else
618 if (!info)
619 return 1;
620#endif
621 return 0;
622}
623
624/**
625 * line discipline callback wrappers
626 *
627 * The wrappers maintain line discipline references
628 * while calling into the line discipline.
629 *
630 * ldisc_receive_buf - pass receive data to line discipline
631 */
632static void ldisc_receive_buf(struct tty_struct *tty,
633 const __u8 *data, char *flags, int count)
634{
635 struct tty_ldisc *ld;
636 if (!tty)
637 return;
638 ld = tty_ldisc_ref(tty);
639 if (ld) {
640 if (ld->ops->receive_buf)
641 ld->ops->receive_buf(tty, data, flags, count);
642 tty_ldisc_deref(ld);
643 }
644}
645
646/* tty callbacks */
647
648static int open(struct tty_struct *tty, struct file *filp)
649{
650 struct slgt_info *info;
651 int retval, line;
652 unsigned long flags;
653
654 line = tty->index;
655 if (line >= slgt_device_count) {
656 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
657 return -ENODEV;
658 }
659
660 info = slgt_device_list;
661 while(info && info->line != line)
662 info = info->next_device;
663 if (sanity_check(info, tty->name, "open"))
664 return -ENODEV;
665 if (info->init_error) {
666 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
667 return -ENODEV;
668 }
669
670 tty->driver_data = info;
671 info->port.tty = tty;
672
673 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
674
675 mutex_lock(&info->port.mutex);
676 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
677
678 spin_lock_irqsave(&info->netlock, flags);
679 if (info->netcount) {
680 retval = -EBUSY;
681 spin_unlock_irqrestore(&info->netlock, flags);
682 mutex_unlock(&info->port.mutex);
683 goto cleanup;
684 }
685 info->port.count++;
686 spin_unlock_irqrestore(&info->netlock, flags);
687
688 if (info->port.count == 1) {
689 /* 1st open on this device, init hardware */
690 retval = startup(info);
691 if (retval < 0) {
692 mutex_unlock(&info->port.mutex);
693 goto cleanup;
694 }
695 }
696 mutex_unlock(&info->port.mutex);
697 retval = block_til_ready(tty, filp, info);
698 if (retval) {
699 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
700 goto cleanup;
701 }
702
703 retval = 0;
704
705cleanup:
706 if (retval) {
707 if (tty->count == 1)
708 info->port.tty = NULL; /* tty layer will release tty struct */
709 if(info->port.count)
710 info->port.count--;
711 }
712
713 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
714 return retval;
715}
716
717static void close(struct tty_struct *tty, struct file *filp)
718{
719 struct slgt_info *info = tty->driver_data;
720
721 if (sanity_check(info, tty->name, "close"))
722 return;
723 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
724
725 if (tty_port_close_start(&info->port, tty, filp) == 0)
726 goto cleanup;
727
728 mutex_lock(&info->port.mutex);
729 if (tty_port_initialized(&info->port))
730 wait_until_sent(tty, info->timeout);
731 flush_buffer(tty);
732 tty_ldisc_flush(tty);
733
734 shutdown(info);
735 mutex_unlock(&info->port.mutex);
736
737 tty_port_close_end(&info->port, tty);
738 info->port.tty = NULL;
739cleanup:
740 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
741}
742
743static void hangup(struct tty_struct *tty)
744{
745 struct slgt_info *info = tty->driver_data;
746 unsigned long flags;
747
748 if (sanity_check(info, tty->name, "hangup"))
749 return;
750 DBGINFO(("%s hangup\n", info->device_name));
751
752 flush_buffer(tty);
753
754 mutex_lock(&info->port.mutex);
755 shutdown(info);
756
757 spin_lock_irqsave(&info->port.lock, flags);
758 info->port.count = 0;
759 info->port.tty = NULL;
760 spin_unlock_irqrestore(&info->port.lock, flags);
761 tty_port_set_active(&info->port, 0);
762 mutex_unlock(&info->port.mutex);
763
764 wake_up_interruptible(&info->port.open_wait);
765}
766
767static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
768{
769 struct slgt_info *info = tty->driver_data;
770 unsigned long flags;
771
772 DBGINFO(("%s set_termios\n", tty->driver->name));
773
774 change_params(info);
775
776 /* Handle transition to B0 status */
777 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
778 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
779 spin_lock_irqsave(&info->lock,flags);
780 set_signals(info);
781 spin_unlock_irqrestore(&info->lock,flags);
782 }
783
784 /* Handle transition away from B0 status */
785 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
786 info->signals |= SerialSignal_DTR;
787 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
788 info->signals |= SerialSignal_RTS;
789 spin_lock_irqsave(&info->lock,flags);
790 set_signals(info);
791 spin_unlock_irqrestore(&info->lock,flags);
792 }
793
794 /* Handle turning off CRTSCTS */
795 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
796 tty->hw_stopped = 0;
797 tx_release(tty);
798 }
799}
800
801static void update_tx_timer(struct slgt_info *info)
802{
803 /*
804 * use worst case speed of 1200bps to calculate transmit timeout
805 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
806 */
807 if (info->params.mode == MGSL_MODE_HDLC) {
808 int timeout = (tbuf_bytes(info) * 7) + 1000;
809 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
810 }
811}
812
813static int write(struct tty_struct *tty,
814 const unsigned char *buf, int count)
815{
816 int ret = 0;
817 struct slgt_info *info = tty->driver_data;
818 unsigned long flags;
819
820 if (sanity_check(info, tty->name, "write"))
821 return -EIO;
822
823 DBGINFO(("%s write count=%d\n", info->device_name, count));
824
825 if (!info->tx_buf || (count > info->max_frame_size))
826 return -EIO;
827
828 if (!count || tty->stopped || tty->hw_stopped)
829 return 0;
830
831 spin_lock_irqsave(&info->lock, flags);
832
833 if (info->tx_count) {
834 /* send accumulated data from send_char() */
835 if (!tx_load(info, info->tx_buf, info->tx_count))
836 goto cleanup;
837 info->tx_count = 0;
838 }
839
840 if (tx_load(info, buf, count))
841 ret = count;
842
843cleanup:
844 spin_unlock_irqrestore(&info->lock, flags);
845 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
846 return ret;
847}
848
849static int put_char(struct tty_struct *tty, unsigned char ch)
850{
851 struct slgt_info *info = tty->driver_data;
852 unsigned long flags;
853 int ret = 0;
854
855 if (sanity_check(info, tty->name, "put_char"))
856 return 0;
857 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
858 if (!info->tx_buf)
859 return 0;
860 spin_lock_irqsave(&info->lock,flags);
861 if (info->tx_count < info->max_frame_size) {
862 info->tx_buf[info->tx_count++] = ch;
863 ret = 1;
864 }
865 spin_unlock_irqrestore(&info->lock,flags);
866 return ret;
867}
868
869static void send_xchar(struct tty_struct *tty, char ch)
870{
871 struct slgt_info *info = tty->driver_data;
872 unsigned long flags;
873
874 if (sanity_check(info, tty->name, "send_xchar"))
875 return;
876 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
877 info->x_char = ch;
878 if (ch) {
879 spin_lock_irqsave(&info->lock,flags);
880 if (!info->tx_enabled)
881 tx_start(info);
882 spin_unlock_irqrestore(&info->lock,flags);
883 }
884}
885
886static void wait_until_sent(struct tty_struct *tty, int timeout)
887{
888 struct slgt_info *info = tty->driver_data;
889 unsigned long orig_jiffies, char_time;
890
891 if (!info )
892 return;
893 if (sanity_check(info, tty->name, "wait_until_sent"))
894 return;
895 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
896 if (!tty_port_initialized(&info->port))
897 goto exit;
898
899 orig_jiffies = jiffies;
900
901 /* Set check interval to 1/5 of estimated time to
902 * send a character, and make it at least 1. The check
903 * interval should also be less than the timeout.
904 * Note: use tight timings here to satisfy the NIST-PCTS.
905 */
906
907 if (info->params.data_rate) {
908 char_time = info->timeout/(32 * 5);
909 if (!char_time)
910 char_time++;
911 } else
912 char_time = 1;
913
914 if (timeout)
915 char_time = min_t(unsigned long, char_time, timeout);
916
917 while (info->tx_active) {
918 msleep_interruptible(jiffies_to_msecs(char_time));
919 if (signal_pending(current))
920 break;
921 if (timeout && time_after(jiffies, orig_jiffies + timeout))
922 break;
923 }
924exit:
925 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
926}
927
928static int write_room(struct tty_struct *tty)
929{
930 struct slgt_info *info = tty->driver_data;
931 int ret;
932
933 if (sanity_check(info, tty->name, "write_room"))
934 return 0;
935 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
936 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
937 return ret;
938}
939
940static void flush_chars(struct tty_struct *tty)
941{
942 struct slgt_info *info = tty->driver_data;
943 unsigned long flags;
944
945 if (sanity_check(info, tty->name, "flush_chars"))
946 return;
947 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
948
949 if (info->tx_count <= 0 || tty->stopped ||
950 tty->hw_stopped || !info->tx_buf)
951 return;
952
953 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
954
955 spin_lock_irqsave(&info->lock,flags);
956 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
957 info->tx_count = 0;
958 spin_unlock_irqrestore(&info->lock,flags);
959}
960
961static void flush_buffer(struct tty_struct *tty)
962{
963 struct slgt_info *info = tty->driver_data;
964 unsigned long flags;
965
966 if (sanity_check(info, tty->name, "flush_buffer"))
967 return;
968 DBGINFO(("%s flush_buffer\n", info->device_name));
969
970 spin_lock_irqsave(&info->lock, flags);
971 info->tx_count = 0;
972 spin_unlock_irqrestore(&info->lock, flags);
973
974 tty_wakeup(tty);
975}
976
977/*
978 * throttle (stop) transmitter
979 */
980static void tx_hold(struct tty_struct *tty)
981{
982 struct slgt_info *info = tty->driver_data;
983 unsigned long flags;
984
985 if (sanity_check(info, tty->name, "tx_hold"))
986 return;
987 DBGINFO(("%s tx_hold\n", info->device_name));
988 spin_lock_irqsave(&info->lock,flags);
989 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
990 tx_stop(info);
991 spin_unlock_irqrestore(&info->lock,flags);
992}
993
994/*
995 * release (start) transmitter
996 */
997static void tx_release(struct tty_struct *tty)
998{
999 struct slgt_info *info = tty->driver_data;
1000 unsigned long flags;
1001
1002 if (sanity_check(info, tty->name, "tx_release"))
1003 return;
1004 DBGINFO(("%s tx_release\n", info->device_name));
1005 spin_lock_irqsave(&info->lock, flags);
1006 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1007 info->tx_count = 0;
1008 spin_unlock_irqrestore(&info->lock, flags);
1009}
1010
1011/*
1012 * Service an IOCTL request
1013 *
1014 * Arguments
1015 *
1016 * tty pointer to tty instance data
1017 * cmd IOCTL command code
1018 * arg command argument/context
1019 *
1020 * Return 0 if success, otherwise error code
1021 */
1022static int ioctl(struct tty_struct *tty,
1023 unsigned int cmd, unsigned long arg)
1024{
1025 struct slgt_info *info = tty->driver_data;
1026 void __user *argp = (void __user *)arg;
1027 int ret;
1028
1029 if (sanity_check(info, tty->name, "ioctl"))
1030 return -ENODEV;
1031 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1032
1033 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1034 (cmd != TIOCMIWAIT)) {
1035 if (tty_io_error(tty))
1036 return -EIO;
1037 }
1038
1039 switch (cmd) {
1040 case MGSL_IOCWAITEVENT:
1041 return wait_mgsl_event(info, argp);
1042 case TIOCMIWAIT:
1043 return modem_input_wait(info,(int)arg);
1044 case MGSL_IOCSGPIO:
1045 return set_gpio(info, argp);
1046 case MGSL_IOCGGPIO:
1047 return get_gpio(info, argp);
1048 case MGSL_IOCWAITGPIO:
1049 return wait_gpio(info, argp);
1050 case MGSL_IOCGXSYNC:
1051 return get_xsync(info, argp);
1052 case MGSL_IOCSXSYNC:
1053 return set_xsync(info, (int)arg);
1054 case MGSL_IOCGXCTRL:
1055 return get_xctrl(info, argp);
1056 case MGSL_IOCSXCTRL:
1057 return set_xctrl(info, (int)arg);
1058 }
1059 mutex_lock(&info->port.mutex);
1060 switch (cmd) {
1061 case MGSL_IOCGPARAMS:
1062 ret = get_params(info, argp);
1063 break;
1064 case MGSL_IOCSPARAMS:
1065 ret = set_params(info, argp);
1066 break;
1067 case MGSL_IOCGTXIDLE:
1068 ret = get_txidle(info, argp);
1069 break;
1070 case MGSL_IOCSTXIDLE:
1071 ret = set_txidle(info, (int)arg);
1072 break;
1073 case MGSL_IOCTXENABLE:
1074 ret = tx_enable(info, (int)arg);
1075 break;
1076 case MGSL_IOCRXENABLE:
1077 ret = rx_enable(info, (int)arg);
1078 break;
1079 case MGSL_IOCTXABORT:
1080 ret = tx_abort(info);
1081 break;
1082 case MGSL_IOCGSTATS:
1083 ret = get_stats(info, argp);
1084 break;
1085 case MGSL_IOCGIF:
1086 ret = get_interface(info, argp);
1087 break;
1088 case MGSL_IOCSIF:
1089 ret = set_interface(info,(int)arg);
1090 break;
1091 default:
1092 ret = -ENOIOCTLCMD;
1093 }
1094 mutex_unlock(&info->port.mutex);
1095 return ret;
1096}
1097
1098static int get_icount(struct tty_struct *tty,
1099 struct serial_icounter_struct *icount)
1100
1101{
1102 struct slgt_info *info = tty->driver_data;
1103 struct mgsl_icount cnow; /* kernel counter temps */
1104 unsigned long flags;
1105
1106 spin_lock_irqsave(&info->lock,flags);
1107 cnow = info->icount;
1108 spin_unlock_irqrestore(&info->lock,flags);
1109
1110 icount->cts = cnow.cts;
1111 icount->dsr = cnow.dsr;
1112 icount->rng = cnow.rng;
1113 icount->dcd = cnow.dcd;
1114 icount->rx = cnow.rx;
1115 icount->tx = cnow.tx;
1116 icount->frame = cnow.frame;
1117 icount->overrun = cnow.overrun;
1118 icount->parity = cnow.parity;
1119 icount->brk = cnow.brk;
1120 icount->buf_overrun = cnow.buf_overrun;
1121
1122 return 0;
1123}
1124
1125/*
1126 * support for 32 bit ioctl calls on 64 bit systems
1127 */
1128#ifdef CONFIG_COMPAT
1129static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1130{
1131 struct MGSL_PARAMS32 tmp_params;
1132
1133 DBGINFO(("%s get_params32\n", info->device_name));
1134 memset(&tmp_params, 0, sizeof(tmp_params));
1135 tmp_params.mode = (compat_ulong_t)info->params.mode;
1136 tmp_params.loopback = info->params.loopback;
1137 tmp_params.flags = info->params.flags;
1138 tmp_params.encoding = info->params.encoding;
1139 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1140 tmp_params.addr_filter = info->params.addr_filter;
1141 tmp_params.crc_type = info->params.crc_type;
1142 tmp_params.preamble_length = info->params.preamble_length;
1143 tmp_params.preamble = info->params.preamble;
1144 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1145 tmp_params.data_bits = info->params.data_bits;
1146 tmp_params.stop_bits = info->params.stop_bits;
1147 tmp_params.parity = info->params.parity;
1148 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1149 return -EFAULT;
1150 return 0;
1151}
1152
1153static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1154{
1155 struct MGSL_PARAMS32 tmp_params;
1156
1157 DBGINFO(("%s set_params32\n", info->device_name));
1158 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1159 return -EFAULT;
1160
1161 spin_lock(&info->lock);
1162 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1163 info->base_clock = tmp_params.clock_speed;
1164 } else {
1165 info->params.mode = tmp_params.mode;
1166 info->params.loopback = tmp_params.loopback;
1167 info->params.flags = tmp_params.flags;
1168 info->params.encoding = tmp_params.encoding;
1169 info->params.clock_speed = tmp_params.clock_speed;
1170 info->params.addr_filter = tmp_params.addr_filter;
1171 info->params.crc_type = tmp_params.crc_type;
1172 info->params.preamble_length = tmp_params.preamble_length;
1173 info->params.preamble = tmp_params.preamble;
1174 info->params.data_rate = tmp_params.data_rate;
1175 info->params.data_bits = tmp_params.data_bits;
1176 info->params.stop_bits = tmp_params.stop_bits;
1177 info->params.parity = tmp_params.parity;
1178 }
1179 spin_unlock(&info->lock);
1180
1181 program_hw(info);
1182
1183 return 0;
1184}
1185
1186static long slgt_compat_ioctl(struct tty_struct *tty,
1187 unsigned int cmd, unsigned long arg)
1188{
1189 struct slgt_info *info = tty->driver_data;
1190 int rc = -ENOIOCTLCMD;
1191
1192 if (sanity_check(info, tty->name, "compat_ioctl"))
1193 return -ENODEV;
1194 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1195
1196 switch (cmd) {
1197
1198 case MGSL_IOCSPARAMS32:
1199 rc = set_params32(info, compat_ptr(arg));
1200 break;
1201
1202 case MGSL_IOCGPARAMS32:
1203 rc = get_params32(info, compat_ptr(arg));
1204 break;
1205
1206 case MGSL_IOCGPARAMS:
1207 case MGSL_IOCSPARAMS:
1208 case MGSL_IOCGTXIDLE:
1209 case MGSL_IOCGSTATS:
1210 case MGSL_IOCWAITEVENT:
1211 case MGSL_IOCGIF:
1212 case MGSL_IOCSGPIO:
1213 case MGSL_IOCGGPIO:
1214 case MGSL_IOCWAITGPIO:
1215 case MGSL_IOCGXSYNC:
1216 case MGSL_IOCGXCTRL:
1217 case MGSL_IOCSTXIDLE:
1218 case MGSL_IOCTXENABLE:
1219 case MGSL_IOCRXENABLE:
1220 case MGSL_IOCTXABORT:
1221 case TIOCMIWAIT:
1222 case MGSL_IOCSIF:
1223 case MGSL_IOCSXSYNC:
1224 case MGSL_IOCSXCTRL:
1225 rc = ioctl(tty, cmd, arg);
1226 break;
1227 }
1228
1229 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1230 return rc;
1231}
1232#else
1233#define slgt_compat_ioctl NULL
1234#endif /* ifdef CONFIG_COMPAT */
1235
1236/*
1237 * proc fs support
1238 */
1239static inline void line_info(struct seq_file *m, struct slgt_info *info)
1240{
1241 char stat_buf[30];
1242 unsigned long flags;
1243
1244 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1245 info->device_name, info->phys_reg_addr,
1246 info->irq_level, info->max_frame_size);
1247
1248 /* output current serial signal states */
1249 spin_lock_irqsave(&info->lock,flags);
1250 get_signals(info);
1251 spin_unlock_irqrestore(&info->lock,flags);
1252
1253 stat_buf[0] = 0;
1254 stat_buf[1] = 0;
1255 if (info->signals & SerialSignal_RTS)
1256 strcat(stat_buf, "|RTS");
1257 if (info->signals & SerialSignal_CTS)
1258 strcat(stat_buf, "|CTS");
1259 if (info->signals & SerialSignal_DTR)
1260 strcat(stat_buf, "|DTR");
1261 if (info->signals & SerialSignal_DSR)
1262 strcat(stat_buf, "|DSR");
1263 if (info->signals & SerialSignal_DCD)
1264 strcat(stat_buf, "|CD");
1265 if (info->signals & SerialSignal_RI)
1266 strcat(stat_buf, "|RI");
1267
1268 if (info->params.mode != MGSL_MODE_ASYNC) {
1269 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1270 info->icount.txok, info->icount.rxok);
1271 if (info->icount.txunder)
1272 seq_printf(m, " txunder:%d", info->icount.txunder);
1273 if (info->icount.txabort)
1274 seq_printf(m, " txabort:%d", info->icount.txabort);
1275 if (info->icount.rxshort)
1276 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1277 if (info->icount.rxlong)
1278 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1279 if (info->icount.rxover)
1280 seq_printf(m, " rxover:%d", info->icount.rxover);
1281 if (info->icount.rxcrc)
1282 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1283 } else {
1284 seq_printf(m, "\tASYNC tx:%d rx:%d",
1285 info->icount.tx, info->icount.rx);
1286 if (info->icount.frame)
1287 seq_printf(m, " fe:%d", info->icount.frame);
1288 if (info->icount.parity)
1289 seq_printf(m, " pe:%d", info->icount.parity);
1290 if (info->icount.brk)
1291 seq_printf(m, " brk:%d", info->icount.brk);
1292 if (info->icount.overrun)
1293 seq_printf(m, " oe:%d", info->icount.overrun);
1294 }
1295
1296 /* Append serial signal status to end */
1297 seq_printf(m, " %s\n", stat_buf+1);
1298
1299 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1300 info->tx_active,info->bh_requested,info->bh_running,
1301 info->pending_bh);
1302}
1303
1304/* Called to print information about devices
1305 */
1306static int synclink_gt_proc_show(struct seq_file *m, void *v)
1307{
1308 struct slgt_info *info;
1309
1310 seq_puts(m, "synclink_gt driver\n");
1311
1312 info = slgt_device_list;
1313 while( info ) {
1314 line_info(m, info);
1315 info = info->next_device;
1316 }
1317 return 0;
1318}
1319
1320static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1321{
1322 return single_open(file, synclink_gt_proc_show, NULL);
1323}
1324
1325static const struct file_operations synclink_gt_proc_fops = {
1326 .owner = THIS_MODULE,
1327 .open = synclink_gt_proc_open,
1328 .read = seq_read,
1329 .llseek = seq_lseek,
1330 .release = single_release,
1331};
1332
1333/*
1334 * return count of bytes in transmit buffer
1335 */
1336static int chars_in_buffer(struct tty_struct *tty)
1337{
1338 struct slgt_info *info = tty->driver_data;
1339 int count;
1340 if (sanity_check(info, tty->name, "chars_in_buffer"))
1341 return 0;
1342 count = tbuf_bytes(info);
1343 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1344 return count;
1345}
1346
1347/*
1348 * signal remote device to throttle send data (our receive data)
1349 */
1350static void throttle(struct tty_struct * tty)
1351{
1352 struct slgt_info *info = tty->driver_data;
1353 unsigned long flags;
1354
1355 if (sanity_check(info, tty->name, "throttle"))
1356 return;
1357 DBGINFO(("%s throttle\n", info->device_name));
1358 if (I_IXOFF(tty))
1359 send_xchar(tty, STOP_CHAR(tty));
1360 if (C_CRTSCTS(tty)) {
1361 spin_lock_irqsave(&info->lock,flags);
1362 info->signals &= ~SerialSignal_RTS;
1363 set_signals(info);
1364 spin_unlock_irqrestore(&info->lock,flags);
1365 }
1366}
1367
1368/*
1369 * signal remote device to stop throttling send data (our receive data)
1370 */
1371static void unthrottle(struct tty_struct * tty)
1372{
1373 struct slgt_info *info = tty->driver_data;
1374 unsigned long flags;
1375
1376 if (sanity_check(info, tty->name, "unthrottle"))
1377 return;
1378 DBGINFO(("%s unthrottle\n", info->device_name));
1379 if (I_IXOFF(tty)) {
1380 if (info->x_char)
1381 info->x_char = 0;
1382 else
1383 send_xchar(tty, START_CHAR(tty));
1384 }
1385 if (C_CRTSCTS(tty)) {
1386 spin_lock_irqsave(&info->lock,flags);
1387 info->signals |= SerialSignal_RTS;
1388 set_signals(info);
1389 spin_unlock_irqrestore(&info->lock,flags);
1390 }
1391}
1392
1393/*
1394 * set or clear transmit break condition
1395 * break_state -1=set break condition, 0=clear
1396 */
1397static int set_break(struct tty_struct *tty, int break_state)
1398{
1399 struct slgt_info *info = tty->driver_data;
1400 unsigned short value;
1401 unsigned long flags;
1402
1403 if (sanity_check(info, tty->name, "set_break"))
1404 return -EINVAL;
1405 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1406
1407 spin_lock_irqsave(&info->lock,flags);
1408 value = rd_reg16(info, TCR);
1409 if (break_state == -1)
1410 value |= BIT6;
1411 else
1412 value &= ~BIT6;
1413 wr_reg16(info, TCR, value);
1414 spin_unlock_irqrestore(&info->lock,flags);
1415 return 0;
1416}
1417
1418#if SYNCLINK_GENERIC_HDLC
1419
1420/**
1421 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1422 * set encoding and frame check sequence (FCS) options
1423 *
1424 * dev pointer to network device structure
1425 * encoding serial encoding setting
1426 * parity FCS setting
1427 *
1428 * returns 0 if success, otherwise error code
1429 */
1430static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1431 unsigned short parity)
1432{
1433 struct slgt_info *info = dev_to_port(dev);
1434 unsigned char new_encoding;
1435 unsigned short new_crctype;
1436
1437 /* return error if TTY interface open */
1438 if (info->port.count)
1439 return -EBUSY;
1440
1441 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1442
1443 switch (encoding)
1444 {
1445 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1446 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1447 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1448 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1449 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1450 default: return -EINVAL;
1451 }
1452
1453 switch (parity)
1454 {
1455 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1456 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1457 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1458 default: return -EINVAL;
1459 }
1460
1461 info->params.encoding = new_encoding;
1462 info->params.crc_type = new_crctype;
1463
1464 /* if network interface up, reprogram hardware */
1465 if (info->netcount)
1466 program_hw(info);
1467
1468 return 0;
1469}
1470
1471/**
1472 * called by generic HDLC layer to send frame
1473 *
1474 * skb socket buffer containing HDLC frame
1475 * dev pointer to network device structure
1476 */
1477static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1478 struct net_device *dev)
1479{
1480 struct slgt_info *info = dev_to_port(dev);
1481 unsigned long flags;
1482
1483 DBGINFO(("%s hdlc_xmit\n", dev->name));
1484
1485 if (!skb->len)
1486 return NETDEV_TX_OK;
1487
1488 /* stop sending until this frame completes */
1489 netif_stop_queue(dev);
1490
1491 /* update network statistics */
1492 dev->stats.tx_packets++;
1493 dev->stats.tx_bytes += skb->len;
1494
1495 /* save start time for transmit timeout detection */
1496 netif_trans_update(dev);
1497
1498 spin_lock_irqsave(&info->lock, flags);
1499 tx_load(info, skb->data, skb->len);
1500 spin_unlock_irqrestore(&info->lock, flags);
1501
1502 /* done with socket buffer, so free it */
1503 dev_kfree_skb(skb);
1504
1505 return NETDEV_TX_OK;
1506}
1507
1508/**
1509 * called by network layer when interface enabled
1510 * claim resources and initialize hardware
1511 *
1512 * dev pointer to network device structure
1513 *
1514 * returns 0 if success, otherwise error code
1515 */
1516static int hdlcdev_open(struct net_device *dev)
1517{
1518 struct slgt_info *info = dev_to_port(dev);
1519 int rc;
1520 unsigned long flags;
1521
1522 if (!try_module_get(THIS_MODULE))
1523 return -EBUSY;
1524
1525 DBGINFO(("%s hdlcdev_open\n", dev->name));
1526
1527 /* generic HDLC layer open processing */
1528 rc = hdlc_open(dev);
1529 if (rc)
1530 return rc;
1531
1532 /* arbitrate between network and tty opens */
1533 spin_lock_irqsave(&info->netlock, flags);
1534 if (info->port.count != 0 || info->netcount != 0) {
1535 DBGINFO(("%s hdlc_open busy\n", dev->name));
1536 spin_unlock_irqrestore(&info->netlock, flags);
1537 return -EBUSY;
1538 }
1539 info->netcount=1;
1540 spin_unlock_irqrestore(&info->netlock, flags);
1541
1542 /* claim resources and init adapter */
1543 if ((rc = startup(info)) != 0) {
1544 spin_lock_irqsave(&info->netlock, flags);
1545 info->netcount=0;
1546 spin_unlock_irqrestore(&info->netlock, flags);
1547 return rc;
1548 }
1549
1550 /* assert RTS and DTR, apply hardware settings */
1551 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1552 program_hw(info);
1553
1554 /* enable network layer transmit */
1555 netif_trans_update(dev);
1556 netif_start_queue(dev);
1557
1558 /* inform generic HDLC layer of current DCD status */
1559 spin_lock_irqsave(&info->lock, flags);
1560 get_signals(info);
1561 spin_unlock_irqrestore(&info->lock, flags);
1562 if (info->signals & SerialSignal_DCD)
1563 netif_carrier_on(dev);
1564 else
1565 netif_carrier_off(dev);
1566 return 0;
1567}
1568
1569/**
1570 * called by network layer when interface is disabled
1571 * shutdown hardware and release resources
1572 *
1573 * dev pointer to network device structure
1574 *
1575 * returns 0 if success, otherwise error code
1576 */
1577static int hdlcdev_close(struct net_device *dev)
1578{
1579 struct slgt_info *info = dev_to_port(dev);
1580 unsigned long flags;
1581
1582 DBGINFO(("%s hdlcdev_close\n", dev->name));
1583
1584 netif_stop_queue(dev);
1585
1586 /* shutdown adapter and release resources */
1587 shutdown(info);
1588
1589 hdlc_close(dev);
1590
1591 spin_lock_irqsave(&info->netlock, flags);
1592 info->netcount=0;
1593 spin_unlock_irqrestore(&info->netlock, flags);
1594
1595 module_put(THIS_MODULE);
1596 return 0;
1597}
1598
1599/**
1600 * called by network layer to process IOCTL call to network device
1601 *
1602 * dev pointer to network device structure
1603 * ifr pointer to network interface request structure
1604 * cmd IOCTL command code
1605 *
1606 * returns 0 if success, otherwise error code
1607 */
1608static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1609{
1610 const size_t size = sizeof(sync_serial_settings);
1611 sync_serial_settings new_line;
1612 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1613 struct slgt_info *info = dev_to_port(dev);
1614 unsigned int flags;
1615
1616 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1617
1618 /* return error if TTY interface open */
1619 if (info->port.count)
1620 return -EBUSY;
1621
1622 if (cmd != SIOCWANDEV)
1623 return hdlc_ioctl(dev, ifr, cmd);
1624
1625 memset(&new_line, 0, sizeof(new_line));
1626
1627 switch(ifr->ifr_settings.type) {
1628 case IF_GET_IFACE: /* return current sync_serial_settings */
1629
1630 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1631 if (ifr->ifr_settings.size < size) {
1632 ifr->ifr_settings.size = size; /* data size wanted */
1633 return -ENOBUFS;
1634 }
1635
1636 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1637 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1638 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1639 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1640
1641 switch (flags){
1642 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1643 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1644 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1645 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1646 default: new_line.clock_type = CLOCK_DEFAULT;
1647 }
1648
1649 new_line.clock_rate = info->params.clock_speed;
1650 new_line.loopback = info->params.loopback ? 1:0;
1651
1652 if (copy_to_user(line, &new_line, size))
1653 return -EFAULT;
1654 return 0;
1655
1656 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1657
1658 if(!capable(CAP_NET_ADMIN))
1659 return -EPERM;
1660 if (copy_from_user(&new_line, line, size))
1661 return -EFAULT;
1662
1663 switch (new_line.clock_type)
1664 {
1665 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1666 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1667 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1668 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1669 case CLOCK_DEFAULT: flags = info->params.flags &
1670 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1671 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1672 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1673 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1674 default: return -EINVAL;
1675 }
1676
1677 if (new_line.loopback != 0 && new_line.loopback != 1)
1678 return -EINVAL;
1679
1680 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1681 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1682 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1683 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1684 info->params.flags |= flags;
1685
1686 info->params.loopback = new_line.loopback;
1687
1688 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1689 info->params.clock_speed = new_line.clock_rate;
1690 else
1691 info->params.clock_speed = 0;
1692
1693 /* if network interface up, reprogram hardware */
1694 if (info->netcount)
1695 program_hw(info);
1696 return 0;
1697
1698 default:
1699 return hdlc_ioctl(dev, ifr, cmd);
1700 }
1701}
1702
1703/**
1704 * called by network layer when transmit timeout is detected
1705 *
1706 * dev pointer to network device structure
1707 */
1708static void hdlcdev_tx_timeout(struct net_device *dev)
1709{
1710 struct slgt_info *info = dev_to_port(dev);
1711 unsigned long flags;
1712
1713 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1714
1715 dev->stats.tx_errors++;
1716 dev->stats.tx_aborted_errors++;
1717
1718 spin_lock_irqsave(&info->lock,flags);
1719 tx_stop(info);
1720 spin_unlock_irqrestore(&info->lock,flags);
1721
1722 netif_wake_queue(dev);
1723}
1724
1725/**
1726 * called by device driver when transmit completes
1727 * reenable network layer transmit if stopped
1728 *
1729 * info pointer to device instance information
1730 */
1731static void hdlcdev_tx_done(struct slgt_info *info)
1732{
1733 if (netif_queue_stopped(info->netdev))
1734 netif_wake_queue(info->netdev);
1735}
1736
1737/**
1738 * called by device driver when frame received
1739 * pass frame to network layer
1740 *
1741 * info pointer to device instance information
1742 * buf pointer to buffer contianing frame data
1743 * size count of data bytes in buf
1744 */
1745static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1746{
1747 struct sk_buff *skb = dev_alloc_skb(size);
1748 struct net_device *dev = info->netdev;
1749
1750 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1751
1752 if (skb == NULL) {
1753 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1754 dev->stats.rx_dropped++;
1755 return;
1756 }
1757
1758 memcpy(skb_put(skb, size), buf, size);
1759
1760 skb->protocol = hdlc_type_trans(skb, dev);
1761
1762 dev->stats.rx_packets++;
1763 dev->stats.rx_bytes += size;
1764
1765 netif_rx(skb);
1766}
1767
1768static const struct net_device_ops hdlcdev_ops = {
1769 .ndo_open = hdlcdev_open,
1770 .ndo_stop = hdlcdev_close,
1771 .ndo_start_xmit = hdlc_start_xmit,
1772 .ndo_do_ioctl = hdlcdev_ioctl,
1773 .ndo_tx_timeout = hdlcdev_tx_timeout,
1774};
1775
1776/**
1777 * called by device driver when adding device instance
1778 * do generic HDLC initialization
1779 *
1780 * info pointer to device instance information
1781 *
1782 * returns 0 if success, otherwise error code
1783 */
1784static int hdlcdev_init(struct slgt_info *info)
1785{
1786 int rc;
1787 struct net_device *dev;
1788 hdlc_device *hdlc;
1789
1790 /* allocate and initialize network and HDLC layer objects */
1791
1792 dev = alloc_hdlcdev(info);
1793 if (!dev) {
1794 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1795 return -ENOMEM;
1796 }
1797
1798 /* for network layer reporting purposes only */
1799 dev->mem_start = info->phys_reg_addr;
1800 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1801 dev->irq = info->irq_level;
1802
1803 /* network layer callbacks and settings */
1804 dev->netdev_ops = &hdlcdev_ops;
1805 dev->watchdog_timeo = 10 * HZ;
1806 dev->tx_queue_len = 50;
1807
1808 /* generic HDLC layer callbacks and settings */
1809 hdlc = dev_to_hdlc(dev);
1810 hdlc->attach = hdlcdev_attach;
1811 hdlc->xmit = hdlcdev_xmit;
1812
1813 /* register objects with HDLC layer */
1814 rc = register_hdlc_device(dev);
1815 if (rc) {
1816 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1817 free_netdev(dev);
1818 return rc;
1819 }
1820
1821 info->netdev = dev;
1822 return 0;
1823}
1824
1825/**
1826 * called by device driver when removing device instance
1827 * do generic HDLC cleanup
1828 *
1829 * info pointer to device instance information
1830 */
1831static void hdlcdev_exit(struct slgt_info *info)
1832{
1833 unregister_hdlc_device(info->netdev);
1834 free_netdev(info->netdev);
1835 info->netdev = NULL;
1836}
1837
1838#endif /* ifdef CONFIG_HDLC */
1839
1840/*
1841 * get async data from rx DMA buffers
1842 */
1843static void rx_async(struct slgt_info *info)
1844{
1845 struct mgsl_icount *icount = &info->icount;
1846 unsigned int start, end;
1847 unsigned char *p;
1848 unsigned char status;
1849 struct slgt_desc *bufs = info->rbufs;
1850 int i, count;
1851 int chars = 0;
1852 int stat;
1853 unsigned char ch;
1854
1855 start = end = info->rbuf_current;
1856
1857 while(desc_complete(bufs[end])) {
1858 count = desc_count(bufs[end]) - info->rbuf_index;
1859 p = bufs[end].buf + info->rbuf_index;
1860
1861 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1862 DBGDATA(info, p, count, "rx");
1863
1864 for(i=0 ; i < count; i+=2, p+=2) {
1865 ch = *p;
1866 icount->rx++;
1867
1868 stat = 0;
1869
1870 status = *(p + 1) & (BIT1 + BIT0);
1871 if (status) {
1872 if (status & BIT1)
1873 icount->parity++;
1874 else if (status & BIT0)
1875 icount->frame++;
1876 /* discard char if tty control flags say so */
1877 if (status & info->ignore_status_mask)
1878 continue;
1879 if (status & BIT1)
1880 stat = TTY_PARITY;
1881 else if (status & BIT0)
1882 stat = TTY_FRAME;
1883 }
1884 tty_insert_flip_char(&info->port, ch, stat);
1885 chars++;
1886 }
1887
1888 if (i < count) {
1889 /* receive buffer not completed */
1890 info->rbuf_index += i;
1891 mod_timer(&info->rx_timer, jiffies + 1);
1892 break;
1893 }
1894
1895 info->rbuf_index = 0;
1896 free_rbufs(info, end, end);
1897
1898 if (++end == info->rbuf_count)
1899 end = 0;
1900
1901 /* if entire list searched then no frame available */
1902 if (end == start)
1903 break;
1904 }
1905
1906 if (chars)
1907 tty_flip_buffer_push(&info->port);
1908}
1909
1910/*
1911 * return next bottom half action to perform
1912 */
1913static int bh_action(struct slgt_info *info)
1914{
1915 unsigned long flags;
1916 int rc;
1917
1918 spin_lock_irqsave(&info->lock,flags);
1919
1920 if (info->pending_bh & BH_RECEIVE) {
1921 info->pending_bh &= ~BH_RECEIVE;
1922 rc = BH_RECEIVE;
1923 } else if (info->pending_bh & BH_TRANSMIT) {
1924 info->pending_bh &= ~BH_TRANSMIT;
1925 rc = BH_TRANSMIT;
1926 } else if (info->pending_bh & BH_STATUS) {
1927 info->pending_bh &= ~BH_STATUS;
1928 rc = BH_STATUS;
1929 } else {
1930 /* Mark BH routine as complete */
1931 info->bh_running = false;
1932 info->bh_requested = false;
1933 rc = 0;
1934 }
1935
1936 spin_unlock_irqrestore(&info->lock,flags);
1937
1938 return rc;
1939}
1940
1941/*
1942 * perform bottom half processing
1943 */
1944static void bh_handler(struct work_struct *work)
1945{
1946 struct slgt_info *info = container_of(work, struct slgt_info, task);
1947 int action;
1948
1949 info->bh_running = true;
1950
1951 while((action = bh_action(info))) {
1952 switch (action) {
1953 case BH_RECEIVE:
1954 DBGBH(("%s bh receive\n", info->device_name));
1955 switch(info->params.mode) {
1956 case MGSL_MODE_ASYNC:
1957 rx_async(info);
1958 break;
1959 case MGSL_MODE_HDLC:
1960 while(rx_get_frame(info));
1961 break;
1962 case MGSL_MODE_RAW:
1963 case MGSL_MODE_MONOSYNC:
1964 case MGSL_MODE_BISYNC:
1965 case MGSL_MODE_XSYNC:
1966 while(rx_get_buf(info));
1967 break;
1968 }
1969 /* restart receiver if rx DMA buffers exhausted */
1970 if (info->rx_restart)
1971 rx_start(info);
1972 break;
1973 case BH_TRANSMIT:
1974 bh_transmit(info);
1975 break;
1976 case BH_STATUS:
1977 DBGBH(("%s bh status\n", info->device_name));
1978 info->ri_chkcount = 0;
1979 info->dsr_chkcount = 0;
1980 info->dcd_chkcount = 0;
1981 info->cts_chkcount = 0;
1982 break;
1983 default:
1984 DBGBH(("%s unknown action\n", info->device_name));
1985 break;
1986 }
1987 }
1988 DBGBH(("%s bh_handler exit\n", info->device_name));
1989}
1990
1991static void bh_transmit(struct slgt_info *info)
1992{
1993 struct tty_struct *tty = info->port.tty;
1994
1995 DBGBH(("%s bh_transmit\n", info->device_name));
1996 if (tty)
1997 tty_wakeup(tty);
1998}
1999
2000static void dsr_change(struct slgt_info *info, unsigned short status)
2001{
2002 if (status & BIT3) {
2003 info->signals |= SerialSignal_DSR;
2004 info->input_signal_events.dsr_up++;
2005 } else {
2006 info->signals &= ~SerialSignal_DSR;
2007 info->input_signal_events.dsr_down++;
2008 }
2009 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2010 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2011 slgt_irq_off(info, IRQ_DSR);
2012 return;
2013 }
2014 info->icount.dsr++;
2015 wake_up_interruptible(&info->status_event_wait_q);
2016 wake_up_interruptible(&info->event_wait_q);
2017 info->pending_bh |= BH_STATUS;
2018}
2019
2020static void cts_change(struct slgt_info *info, unsigned short status)
2021{
2022 if (status & BIT2) {
2023 info->signals |= SerialSignal_CTS;
2024 info->input_signal_events.cts_up++;
2025 } else {
2026 info->signals &= ~SerialSignal_CTS;
2027 info->input_signal_events.cts_down++;
2028 }
2029 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2030 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2031 slgt_irq_off(info, IRQ_CTS);
2032 return;
2033 }
2034 info->icount.cts++;
2035 wake_up_interruptible(&info->status_event_wait_q);
2036 wake_up_interruptible(&info->event_wait_q);
2037 info->pending_bh |= BH_STATUS;
2038
2039 if (tty_port_cts_enabled(&info->port)) {
2040 if (info->port.tty) {
2041 if (info->port.tty->hw_stopped) {
2042 if (info->signals & SerialSignal_CTS) {
2043 info->port.tty->hw_stopped = 0;
2044 info->pending_bh |= BH_TRANSMIT;
2045 return;
2046 }
2047 } else {
2048 if (!(info->signals & SerialSignal_CTS))
2049 info->port.tty->hw_stopped = 1;
2050 }
2051 }
2052 }
2053}
2054
2055static void dcd_change(struct slgt_info *info, unsigned short status)
2056{
2057 if (status & BIT1) {
2058 info->signals |= SerialSignal_DCD;
2059 info->input_signal_events.dcd_up++;
2060 } else {
2061 info->signals &= ~SerialSignal_DCD;
2062 info->input_signal_events.dcd_down++;
2063 }
2064 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2065 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2066 slgt_irq_off(info, IRQ_DCD);
2067 return;
2068 }
2069 info->icount.dcd++;
2070#if SYNCLINK_GENERIC_HDLC
2071 if (info->netcount) {
2072 if (info->signals & SerialSignal_DCD)
2073 netif_carrier_on(info->netdev);
2074 else
2075 netif_carrier_off(info->netdev);
2076 }
2077#endif
2078 wake_up_interruptible(&info->status_event_wait_q);
2079 wake_up_interruptible(&info->event_wait_q);
2080 info->pending_bh |= BH_STATUS;
2081
2082 if (tty_port_check_carrier(&info->port)) {
2083 if (info->signals & SerialSignal_DCD)
2084 wake_up_interruptible(&info->port.open_wait);
2085 else {
2086 if (info->port.tty)
2087 tty_hangup(info->port.tty);
2088 }
2089 }
2090}
2091
2092static void ri_change(struct slgt_info *info, unsigned short status)
2093{
2094 if (status & BIT0) {
2095 info->signals |= SerialSignal_RI;
2096 info->input_signal_events.ri_up++;
2097 } else {
2098 info->signals &= ~SerialSignal_RI;
2099 info->input_signal_events.ri_down++;
2100 }
2101 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2102 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2103 slgt_irq_off(info, IRQ_RI);
2104 return;
2105 }
2106 info->icount.rng++;
2107 wake_up_interruptible(&info->status_event_wait_q);
2108 wake_up_interruptible(&info->event_wait_q);
2109 info->pending_bh |= BH_STATUS;
2110}
2111
2112static void isr_rxdata(struct slgt_info *info)
2113{
2114 unsigned int count = info->rbuf_fill_count;
2115 unsigned int i = info->rbuf_fill_index;
2116 unsigned short reg;
2117
2118 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2119 reg = rd_reg16(info, RDR);
2120 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2121 if (desc_complete(info->rbufs[i])) {
2122 /* all buffers full */
2123 rx_stop(info);
2124 info->rx_restart = 1;
2125 continue;
2126 }
2127 info->rbufs[i].buf[count++] = (unsigned char)reg;
2128 /* async mode saves status byte to buffer for each data byte */
2129 if (info->params.mode == MGSL_MODE_ASYNC)
2130 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2131 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2132 /* buffer full or end of frame */
2133 set_desc_count(info->rbufs[i], count);
2134 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2135 info->rbuf_fill_count = count = 0;
2136 if (++i == info->rbuf_count)
2137 i = 0;
2138 info->pending_bh |= BH_RECEIVE;
2139 }
2140 }
2141
2142 info->rbuf_fill_index = i;
2143 info->rbuf_fill_count = count;
2144}
2145
2146static void isr_serial(struct slgt_info *info)
2147{
2148 unsigned short status = rd_reg16(info, SSR);
2149
2150 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2151
2152 wr_reg16(info, SSR, status); /* clear pending */
2153
2154 info->irq_occurred = true;
2155
2156 if (info->params.mode == MGSL_MODE_ASYNC) {
2157 if (status & IRQ_TXIDLE) {
2158 if (info->tx_active)
2159 isr_txeom(info, status);
2160 }
2161 if (info->rx_pio && (status & IRQ_RXDATA))
2162 isr_rxdata(info);
2163 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2164 info->icount.brk++;
2165 /* process break detection if tty control allows */
2166 if (info->port.tty) {
2167 if (!(status & info->ignore_status_mask)) {
2168 if (info->read_status_mask & MASK_BREAK) {
2169 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2170 if (info->port.flags & ASYNC_SAK)
2171 do_SAK(info->port.tty);
2172 }
2173 }
2174 }
2175 }
2176 } else {
2177 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2178 isr_txeom(info, status);
2179 if (info->rx_pio && (status & IRQ_RXDATA))
2180 isr_rxdata(info);
2181 if (status & IRQ_RXIDLE) {
2182 if (status & RXIDLE)
2183 info->icount.rxidle++;
2184 else
2185 info->icount.exithunt++;
2186 wake_up_interruptible(&info->event_wait_q);
2187 }
2188
2189 if (status & IRQ_RXOVER)
2190 rx_start(info);
2191 }
2192
2193 if (status & IRQ_DSR)
2194 dsr_change(info, status);
2195 if (status & IRQ_CTS)
2196 cts_change(info, status);
2197 if (status & IRQ_DCD)
2198 dcd_change(info, status);
2199 if (status & IRQ_RI)
2200 ri_change(info, status);
2201}
2202
2203static void isr_rdma(struct slgt_info *info)
2204{
2205 unsigned int status = rd_reg32(info, RDCSR);
2206
2207 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2208
2209 /* RDCSR (rx DMA control/status)
2210 *
2211 * 31..07 reserved
2212 * 06 save status byte to DMA buffer
2213 * 05 error
2214 * 04 eol (end of list)
2215 * 03 eob (end of buffer)
2216 * 02 IRQ enable
2217 * 01 reset
2218 * 00 enable
2219 */
2220 wr_reg32(info, RDCSR, status); /* clear pending */
2221
2222 if (status & (BIT5 + BIT4)) {
2223 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2224 info->rx_restart = true;
2225 }
2226 info->pending_bh |= BH_RECEIVE;
2227}
2228
2229static void isr_tdma(struct slgt_info *info)
2230{
2231 unsigned int status = rd_reg32(info, TDCSR);
2232
2233 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2234
2235 /* TDCSR (tx DMA control/status)
2236 *
2237 * 31..06 reserved
2238 * 05 error
2239 * 04 eol (end of list)
2240 * 03 eob (end of buffer)
2241 * 02 IRQ enable
2242 * 01 reset
2243 * 00 enable
2244 */
2245 wr_reg32(info, TDCSR, status); /* clear pending */
2246
2247 if (status & (BIT5 + BIT4 + BIT3)) {
2248 // another transmit buffer has completed
2249 // run bottom half to get more send data from user
2250 info->pending_bh |= BH_TRANSMIT;
2251 }
2252}
2253
2254/*
2255 * return true if there are unsent tx DMA buffers, otherwise false
2256 *
2257 * if there are unsent buffers then info->tbuf_start
2258 * is set to index of first unsent buffer
2259 */
2260static bool unsent_tbufs(struct slgt_info *info)
2261{
2262 unsigned int i = info->tbuf_current;
2263 bool rc = false;
2264
2265 /*
2266 * search backwards from last loaded buffer (precedes tbuf_current)
2267 * for first unsent buffer (desc_count > 0)
2268 */
2269
2270 do {
2271 if (i)
2272 i--;
2273 else
2274 i = info->tbuf_count - 1;
2275 if (!desc_count(info->tbufs[i]))
2276 break;
2277 info->tbuf_start = i;
2278 rc = true;
2279 } while (i != info->tbuf_current);
2280
2281 return rc;
2282}
2283
2284static void isr_txeom(struct slgt_info *info, unsigned short status)
2285{
2286 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2287
2288 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2289 tdma_reset(info);
2290 if (status & IRQ_TXUNDER) {
2291 unsigned short val = rd_reg16(info, TCR);
2292 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2293 wr_reg16(info, TCR, val); /* clear reset bit */
2294 }
2295
2296 if (info->tx_active) {
2297 if (info->params.mode != MGSL_MODE_ASYNC) {
2298 if (status & IRQ_TXUNDER)
2299 info->icount.txunder++;
2300 else if (status & IRQ_TXIDLE)
2301 info->icount.txok++;
2302 }
2303
2304 if (unsent_tbufs(info)) {
2305 tx_start(info);
2306 update_tx_timer(info);
2307 return;
2308 }
2309 info->tx_active = false;
2310
2311 del_timer(&info->tx_timer);
2312
2313 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2314 info->signals &= ~SerialSignal_RTS;
2315 info->drop_rts_on_tx_done = false;
2316 set_signals(info);
2317 }
2318
2319#if SYNCLINK_GENERIC_HDLC
2320 if (info->netcount)
2321 hdlcdev_tx_done(info);
2322 else
2323#endif
2324 {
2325 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2326 tx_stop(info);
2327 return;
2328 }
2329 info->pending_bh |= BH_TRANSMIT;
2330 }
2331 }
2332}
2333
2334static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2335{
2336 struct cond_wait *w, *prev;
2337
2338 /* wake processes waiting for specific transitions */
2339 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2340 if (w->data & changed) {
2341 w->data = state;
2342 wake_up_interruptible(&w->q);
2343 if (prev != NULL)
2344 prev->next = w->next;
2345 else
2346 info->gpio_wait_q = w->next;
2347 } else
2348 prev = w;
2349 }
2350}
2351
2352/* interrupt service routine
2353 *
2354 * irq interrupt number
2355 * dev_id device ID supplied during interrupt registration
2356 */
2357static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2358{
2359 struct slgt_info *info = dev_id;
2360 unsigned int gsr;
2361 unsigned int i;
2362
2363 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2364
2365 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2366 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2367 info->irq_occurred = true;
2368 for(i=0; i < info->port_count ; i++) {
2369 if (info->port_array[i] == NULL)
2370 continue;
2371 spin_lock(&info->port_array[i]->lock);
2372 if (gsr & (BIT8 << i))
2373 isr_serial(info->port_array[i]);
2374 if (gsr & (BIT16 << (i*2)))
2375 isr_rdma(info->port_array[i]);
2376 if (gsr & (BIT17 << (i*2)))
2377 isr_tdma(info->port_array[i]);
2378 spin_unlock(&info->port_array[i]->lock);
2379 }
2380 }
2381
2382 if (info->gpio_present) {
2383 unsigned int state;
2384 unsigned int changed;
2385 spin_lock(&info->lock);
2386 while ((changed = rd_reg32(info, IOSR)) != 0) {
2387 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2388 /* read latched state of GPIO signals */
2389 state = rd_reg32(info, IOVR);
2390 /* clear pending GPIO interrupt bits */
2391 wr_reg32(info, IOSR, changed);
2392 for (i=0 ; i < info->port_count ; i++) {
2393 if (info->port_array[i] != NULL)
2394 isr_gpio(info->port_array[i], changed, state);
2395 }
2396 }
2397 spin_unlock(&info->lock);
2398 }
2399
2400 for(i=0; i < info->port_count ; i++) {
2401 struct slgt_info *port = info->port_array[i];
2402 if (port == NULL)
2403 continue;
2404 spin_lock(&port->lock);
2405 if ((port->port.count || port->netcount) &&
2406 port->pending_bh && !port->bh_running &&
2407 !port->bh_requested) {
2408 DBGISR(("%s bh queued\n", port->device_name));
2409 schedule_work(&port->task);
2410 port->bh_requested = true;
2411 }
2412 spin_unlock(&port->lock);
2413 }
2414
2415 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2416 return IRQ_HANDLED;
2417}
2418
2419static int startup(struct slgt_info *info)
2420{
2421 DBGINFO(("%s startup\n", info->device_name));
2422
2423 if (tty_port_initialized(&info->port))
2424 return 0;
2425
2426 if (!info->tx_buf) {
2427 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2428 if (!info->tx_buf) {
2429 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2430 return -ENOMEM;
2431 }
2432 }
2433
2434 info->pending_bh = 0;
2435
2436 memset(&info->icount, 0, sizeof(info->icount));
2437
2438 /* program hardware for current parameters */
2439 change_params(info);
2440
2441 if (info->port.tty)
2442 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2443
2444 tty_port_set_initialized(&info->port, 1);
2445
2446 return 0;
2447}
2448
2449/*
2450 * called by close() and hangup() to shutdown hardware
2451 */
2452static void shutdown(struct slgt_info *info)
2453{
2454 unsigned long flags;
2455
2456 if (!tty_port_initialized(&info->port))
2457 return;
2458
2459 DBGINFO(("%s shutdown\n", info->device_name));
2460
2461 /* clear status wait queue because status changes */
2462 /* can't happen after shutting down the hardware */
2463 wake_up_interruptible(&info->status_event_wait_q);
2464 wake_up_interruptible(&info->event_wait_q);
2465
2466 del_timer_sync(&info->tx_timer);
2467 del_timer_sync(&info->rx_timer);
2468
2469 kfree(info->tx_buf);
2470 info->tx_buf = NULL;
2471
2472 spin_lock_irqsave(&info->lock,flags);
2473
2474 tx_stop(info);
2475 rx_stop(info);
2476
2477 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2478
2479 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2480 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2481 set_signals(info);
2482 }
2483
2484 flush_cond_wait(&info->gpio_wait_q);
2485
2486 spin_unlock_irqrestore(&info->lock,flags);
2487
2488 if (info->port.tty)
2489 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2490
2491 tty_port_set_initialized(&info->port, 0);
2492}
2493
2494static void program_hw(struct slgt_info *info)
2495{
2496 unsigned long flags;
2497
2498 spin_lock_irqsave(&info->lock,flags);
2499
2500 rx_stop(info);
2501 tx_stop(info);
2502
2503 if (info->params.mode != MGSL_MODE_ASYNC ||
2504 info->netcount)
2505 sync_mode(info);
2506 else
2507 async_mode(info);
2508
2509 set_signals(info);
2510
2511 info->dcd_chkcount = 0;
2512 info->cts_chkcount = 0;
2513 info->ri_chkcount = 0;
2514 info->dsr_chkcount = 0;
2515
2516 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2517 get_signals(info);
2518
2519 if (info->netcount ||
2520 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2521 rx_start(info);
2522
2523 spin_unlock_irqrestore(&info->lock,flags);
2524}
2525
2526/*
2527 * reconfigure adapter based on new parameters
2528 */
2529static void change_params(struct slgt_info *info)
2530{
2531 unsigned cflag;
2532 int bits_per_char;
2533
2534 if (!info->port.tty)
2535 return;
2536 DBGINFO(("%s change_params\n", info->device_name));
2537
2538 cflag = info->port.tty->termios.c_cflag;
2539
2540 /* if B0 rate (hangup) specified then negate RTS and DTR */
2541 /* otherwise assert RTS and DTR */
2542 if (cflag & CBAUD)
2543 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2544 else
2545 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2546
2547 /* byte size and parity */
2548
2549 switch (cflag & CSIZE) {
2550 case CS5: info->params.data_bits = 5; break;
2551 case CS6: info->params.data_bits = 6; break;
2552 case CS7: info->params.data_bits = 7; break;
2553 case CS8: info->params.data_bits = 8; break;
2554 default: info->params.data_bits = 7; break;
2555 }
2556
2557 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2558
2559 if (cflag & PARENB)
2560 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2561 else
2562 info->params.parity = ASYNC_PARITY_NONE;
2563
2564 /* calculate number of jiffies to transmit a full
2565 * FIFO (32 bytes) at specified data rate
2566 */
2567 bits_per_char = info->params.data_bits +
2568 info->params.stop_bits + 1;
2569
2570 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2571
2572 if (info->params.data_rate) {
2573 info->timeout = (32*HZ*bits_per_char) /
2574 info->params.data_rate;
2575 }
2576 info->timeout += HZ/50; /* Add .02 seconds of slop */
2577
2578 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2579 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2580
2581 /* process tty input control flags */
2582
2583 info->read_status_mask = IRQ_RXOVER;
2584 if (I_INPCK(info->port.tty))
2585 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2586 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2587 info->read_status_mask |= MASK_BREAK;
2588 if (I_IGNPAR(info->port.tty))
2589 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2590 if (I_IGNBRK(info->port.tty)) {
2591 info->ignore_status_mask |= MASK_BREAK;
2592 /* If ignoring parity and break indicators, ignore
2593 * overruns too. (For real raw support).
2594 */
2595 if (I_IGNPAR(info->port.tty))
2596 info->ignore_status_mask |= MASK_OVERRUN;
2597 }
2598
2599 program_hw(info);
2600}
2601
2602static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2603{
2604 DBGINFO(("%s get_stats\n", info->device_name));
2605 if (!user_icount) {
2606 memset(&info->icount, 0, sizeof(info->icount));
2607 } else {
2608 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2609 return -EFAULT;
2610 }
2611 return 0;
2612}
2613
2614static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2615{
2616 DBGINFO(("%s get_params\n", info->device_name));
2617 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2618 return -EFAULT;
2619 return 0;
2620}
2621
2622static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2623{
2624 unsigned long flags;
2625 MGSL_PARAMS tmp_params;
2626
2627 DBGINFO(("%s set_params\n", info->device_name));
2628 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2629 return -EFAULT;
2630
2631 spin_lock_irqsave(&info->lock, flags);
2632 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2633 info->base_clock = tmp_params.clock_speed;
2634 else
2635 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2636 spin_unlock_irqrestore(&info->lock, flags);
2637
2638 program_hw(info);
2639
2640 return 0;
2641}
2642
2643static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2644{
2645 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2646 if (put_user(info->idle_mode, idle_mode))
2647 return -EFAULT;
2648 return 0;
2649}
2650
2651static int set_txidle(struct slgt_info *info, int idle_mode)
2652{
2653 unsigned long flags;
2654 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2655 spin_lock_irqsave(&info->lock,flags);
2656 info->idle_mode = idle_mode;
2657 if (info->params.mode != MGSL_MODE_ASYNC)
2658 tx_set_idle(info);
2659 spin_unlock_irqrestore(&info->lock,flags);
2660 return 0;
2661}
2662
2663static int tx_enable(struct slgt_info *info, int enable)
2664{
2665 unsigned long flags;
2666 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2667 spin_lock_irqsave(&info->lock,flags);
2668 if (enable) {
2669 if (!info->tx_enabled)
2670 tx_start(info);
2671 } else {
2672 if (info->tx_enabled)
2673 tx_stop(info);
2674 }
2675 spin_unlock_irqrestore(&info->lock,flags);
2676 return 0;
2677}
2678
2679/*
2680 * abort transmit HDLC frame
2681 */
2682static int tx_abort(struct slgt_info *info)
2683{
2684 unsigned long flags;
2685 DBGINFO(("%s tx_abort\n", info->device_name));
2686 spin_lock_irqsave(&info->lock,flags);
2687 tdma_reset(info);
2688 spin_unlock_irqrestore(&info->lock,flags);
2689 return 0;
2690}
2691
2692static int rx_enable(struct slgt_info *info, int enable)
2693{
2694 unsigned long flags;
2695 unsigned int rbuf_fill_level;
2696 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2697 spin_lock_irqsave(&info->lock,flags);
2698 /*
2699 * enable[31..16] = receive DMA buffer fill level
2700 * 0 = noop (leave fill level unchanged)
2701 * fill level must be multiple of 4 and <= buffer size
2702 */
2703 rbuf_fill_level = ((unsigned int)enable) >> 16;
2704 if (rbuf_fill_level) {
2705 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2706 spin_unlock_irqrestore(&info->lock, flags);
2707 return -EINVAL;
2708 }
2709 info->rbuf_fill_level = rbuf_fill_level;
2710 if (rbuf_fill_level < 128)
2711 info->rx_pio = 1; /* PIO mode */
2712 else
2713 info->rx_pio = 0; /* DMA mode */
2714 rx_stop(info); /* restart receiver to use new fill level */
2715 }
2716
2717 /*
2718 * enable[1..0] = receiver enable command
2719 * 0 = disable
2720 * 1 = enable
2721 * 2 = enable or force hunt mode if already enabled
2722 */
2723 enable &= 3;
2724 if (enable) {
2725 if (!info->rx_enabled)
2726 rx_start(info);
2727 else if (enable == 2) {
2728 /* force hunt mode (write 1 to RCR[3]) */
2729 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2730 }
2731 } else {
2732 if (info->rx_enabled)
2733 rx_stop(info);
2734 }
2735 spin_unlock_irqrestore(&info->lock,flags);
2736 return 0;
2737}
2738
2739/*
2740 * wait for specified event to occur
2741 */
2742static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2743{
2744 unsigned long flags;
2745 int s;
2746 int rc=0;
2747 struct mgsl_icount cprev, cnow;
2748 int events;
2749 int mask;
2750 struct _input_signal_events oldsigs, newsigs;
2751 DECLARE_WAITQUEUE(wait, current);
2752
2753 if (get_user(mask, mask_ptr))
2754 return -EFAULT;
2755
2756 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2757
2758 spin_lock_irqsave(&info->lock,flags);
2759
2760 /* return immediately if state matches requested events */
2761 get_signals(info);
2762 s = info->signals;
2763
2764 events = mask &
2765 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2766 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2767 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2768 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2769 if (events) {
2770 spin_unlock_irqrestore(&info->lock,flags);
2771 goto exit;
2772 }
2773
2774 /* save current irq counts */
2775 cprev = info->icount;
2776 oldsigs = info->input_signal_events;
2777
2778 /* enable hunt and idle irqs if needed */
2779 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2780 unsigned short val = rd_reg16(info, SCR);
2781 if (!(val & IRQ_RXIDLE))
2782 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2783 }
2784
2785 set_current_state(TASK_INTERRUPTIBLE);
2786 add_wait_queue(&info->event_wait_q, &wait);
2787
2788 spin_unlock_irqrestore(&info->lock,flags);
2789
2790 for(;;) {
2791 schedule();
2792 if (signal_pending(current)) {
2793 rc = -ERESTARTSYS;
2794 break;
2795 }
2796
2797 /* get current irq counts */
2798 spin_lock_irqsave(&info->lock,flags);
2799 cnow = info->icount;
2800 newsigs = info->input_signal_events;
2801 set_current_state(TASK_INTERRUPTIBLE);
2802 spin_unlock_irqrestore(&info->lock,flags);
2803
2804 /* if no change, wait aborted for some reason */
2805 if (newsigs.dsr_up == oldsigs.dsr_up &&
2806 newsigs.dsr_down == oldsigs.dsr_down &&
2807 newsigs.dcd_up == oldsigs.dcd_up &&
2808 newsigs.dcd_down == oldsigs.dcd_down &&
2809 newsigs.cts_up == oldsigs.cts_up &&
2810 newsigs.cts_down == oldsigs.cts_down &&
2811 newsigs.ri_up == oldsigs.ri_up &&
2812 newsigs.ri_down == oldsigs.ri_down &&
2813 cnow.exithunt == cprev.exithunt &&
2814 cnow.rxidle == cprev.rxidle) {
2815 rc = -EIO;
2816 break;
2817 }
2818
2819 events = mask &
2820 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2821 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2822 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2823 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2824 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2825 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2826 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2827 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2828 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2829 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2830 if (events)
2831 break;
2832
2833 cprev = cnow;
2834 oldsigs = newsigs;
2835 }
2836
2837 remove_wait_queue(&info->event_wait_q, &wait);
2838 set_current_state(TASK_RUNNING);
2839
2840
2841 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2842 spin_lock_irqsave(&info->lock,flags);
2843 if (!waitqueue_active(&info->event_wait_q)) {
2844 /* disable enable exit hunt mode/idle rcvd IRQs */
2845 wr_reg16(info, SCR,
2846 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2847 }
2848 spin_unlock_irqrestore(&info->lock,flags);
2849 }
2850exit:
2851 if (rc == 0)
2852 rc = put_user(events, mask_ptr);
2853 return rc;
2854}
2855
2856static int get_interface(struct slgt_info *info, int __user *if_mode)
2857{
2858 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2859 if (put_user(info->if_mode, if_mode))
2860 return -EFAULT;
2861 return 0;
2862}
2863
2864static int set_interface(struct slgt_info *info, int if_mode)
2865{
2866 unsigned long flags;
2867 unsigned short val;
2868
2869 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2870 spin_lock_irqsave(&info->lock,flags);
2871 info->if_mode = if_mode;
2872
2873 msc_set_vcr(info);
2874
2875 /* TCR (tx control) 07 1=RTS driver control */
2876 val = rd_reg16(info, TCR);
2877 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2878 val |= BIT7;
2879 else
2880 val &= ~BIT7;
2881 wr_reg16(info, TCR, val);
2882
2883 spin_unlock_irqrestore(&info->lock,flags);
2884 return 0;
2885}
2886
2887static int get_xsync(struct slgt_info *info, int __user *xsync)
2888{
2889 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2890 if (put_user(info->xsync, xsync))
2891 return -EFAULT;
2892 return 0;
2893}
2894
2895/*
2896 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2897 *
2898 * sync pattern is contained in least significant bytes of value
2899 * most significant byte of sync pattern is oldest (1st sent/detected)
2900 */
2901static int set_xsync(struct slgt_info *info, int xsync)
2902{
2903 unsigned long flags;
2904
2905 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2906 spin_lock_irqsave(&info->lock, flags);
2907 info->xsync = xsync;
2908 wr_reg32(info, XSR, xsync);
2909 spin_unlock_irqrestore(&info->lock, flags);
2910 return 0;
2911}
2912
2913static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2914{
2915 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2916 if (put_user(info->xctrl, xctrl))
2917 return -EFAULT;
2918 return 0;
2919}
2920
2921/*
2922 * set extended control options
2923 *
2924 * xctrl[31:19] reserved, must be zero
2925 * xctrl[18:17] extended sync pattern length in bytes
2926 * 00 = 1 byte in xsr[7:0]
2927 * 01 = 2 bytes in xsr[15:0]
2928 * 10 = 3 bytes in xsr[23:0]
2929 * 11 = 4 bytes in xsr[31:0]
2930 * xctrl[16] 1 = enable terminal count, 0=disabled
2931 * xctrl[15:0] receive terminal count for fixed length packets
2932 * value is count minus one (0 = 1 byte packet)
2933 * when terminal count is reached, receiver
2934 * automatically returns to hunt mode and receive
2935 * FIFO contents are flushed to DMA buffers with
2936 * end of frame (EOF) status
2937 */
2938static int set_xctrl(struct slgt_info *info, int xctrl)
2939{
2940 unsigned long flags;
2941
2942 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2943 spin_lock_irqsave(&info->lock, flags);
2944 info->xctrl = xctrl;
2945 wr_reg32(info, XCR, xctrl);
2946 spin_unlock_irqrestore(&info->lock, flags);
2947 return 0;
2948}
2949
2950/*
2951 * set general purpose IO pin state and direction
2952 *
2953 * user_gpio fields:
2954 * state each bit indicates a pin state
2955 * smask set bit indicates pin state to set
2956 * dir each bit indicates a pin direction (0=input, 1=output)
2957 * dmask set bit indicates pin direction to set
2958 */
2959static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2960{
2961 unsigned long flags;
2962 struct gpio_desc gpio;
2963 __u32 data;
2964
2965 if (!info->gpio_present)
2966 return -EINVAL;
2967 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2968 return -EFAULT;
2969 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2970 info->device_name, gpio.state, gpio.smask,
2971 gpio.dir, gpio.dmask));
2972
2973 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2974 if (gpio.dmask) {
2975 data = rd_reg32(info, IODR);
2976 data |= gpio.dmask & gpio.dir;
2977 data &= ~(gpio.dmask & ~gpio.dir);
2978 wr_reg32(info, IODR, data);
2979 }
2980 if (gpio.smask) {
2981 data = rd_reg32(info, IOVR);
2982 data |= gpio.smask & gpio.state;
2983 data &= ~(gpio.smask & ~gpio.state);
2984 wr_reg32(info, IOVR, data);
2985 }
2986 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2987
2988 return 0;
2989}
2990
2991/*
2992 * get general purpose IO pin state and direction
2993 */
2994static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2995{
2996 struct gpio_desc gpio;
2997 if (!info->gpio_present)
2998 return -EINVAL;
2999 gpio.state = rd_reg32(info, IOVR);
3000 gpio.smask = 0xffffffff;
3001 gpio.dir = rd_reg32(info, IODR);
3002 gpio.dmask = 0xffffffff;
3003 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3004 return -EFAULT;
3005 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3006 info->device_name, gpio.state, gpio.dir));
3007 return 0;
3008}
3009
3010/*
3011 * conditional wait facility
3012 */
3013static void init_cond_wait(struct cond_wait *w, unsigned int data)
3014{
3015 init_waitqueue_head(&w->q);
3016 init_waitqueue_entry(&w->wait, current);
3017 w->data = data;
3018}
3019
3020static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3021{
3022 set_current_state(TASK_INTERRUPTIBLE);
3023 add_wait_queue(&w->q, &w->wait);
3024 w->next = *head;
3025 *head = w;
3026}
3027
3028static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3029{
3030 struct cond_wait *w, *prev;
3031 remove_wait_queue(&cw->q, &cw->wait);
3032 set_current_state(TASK_RUNNING);
3033 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3034 if (w == cw) {
3035 if (prev != NULL)
3036 prev->next = w->next;
3037 else
3038 *head = w->next;
3039 break;
3040 }
3041 }
3042}
3043
3044static void flush_cond_wait(struct cond_wait **head)
3045{
3046 while (*head != NULL) {
3047 wake_up_interruptible(&(*head)->q);
3048 *head = (*head)->next;
3049 }
3050}
3051
3052/*
3053 * wait for general purpose I/O pin(s) to enter specified state
3054 *
3055 * user_gpio fields:
3056 * state - bit indicates target pin state
3057 * smask - set bit indicates watched pin
3058 *
3059 * The wait ends when at least one watched pin enters the specified
3060 * state. When 0 (no error) is returned, user_gpio->state is set to the
3061 * state of all GPIO pins when the wait ends.
3062 *
3063 * Note: Each pin may be a dedicated input, dedicated output, or
3064 * configurable input/output. The number and configuration of pins
3065 * varies with the specific adapter model. Only input pins (dedicated
3066 * or configured) can be monitored with this function.
3067 */
3068static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3069{
3070 unsigned long flags;
3071 int rc = 0;
3072 struct gpio_desc gpio;
3073 struct cond_wait wait;
3074 u32 state;
3075
3076 if (!info->gpio_present)
3077 return -EINVAL;
3078 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3079 return -EFAULT;
3080 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3081 info->device_name, gpio.state, gpio.smask));
3082 /* ignore output pins identified by set IODR bit */
3083 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3084 return -EINVAL;
3085 init_cond_wait(&wait, gpio.smask);
3086
3087 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3088 /* enable interrupts for watched pins */
3089 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3090 /* get current pin states */
3091 state = rd_reg32(info, IOVR);
3092
3093 if (gpio.smask & ~(state ^ gpio.state)) {
3094 /* already in target state */
3095 gpio.state = state;
3096 } else {
3097 /* wait for target state */
3098 add_cond_wait(&info->gpio_wait_q, &wait);
3099 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3100 schedule();
3101 if (signal_pending(current))
3102 rc = -ERESTARTSYS;
3103 else
3104 gpio.state = wait.data;
3105 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3106 remove_cond_wait(&info->gpio_wait_q, &wait);
3107 }
3108
3109 /* disable all GPIO interrupts if no waiting processes */
3110 if (info->gpio_wait_q == NULL)
3111 wr_reg32(info, IOER, 0);
3112 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3113
3114 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3115 rc = -EFAULT;
3116 return rc;
3117}
3118
3119static int modem_input_wait(struct slgt_info *info,int arg)
3120{
3121 unsigned long flags;
3122 int rc;
3123 struct mgsl_icount cprev, cnow;
3124 DECLARE_WAITQUEUE(wait, current);
3125
3126 /* save current irq counts */
3127 spin_lock_irqsave(&info->lock,flags);
3128 cprev = info->icount;
3129 add_wait_queue(&info->status_event_wait_q, &wait);
3130 set_current_state(TASK_INTERRUPTIBLE);
3131 spin_unlock_irqrestore(&info->lock,flags);
3132
3133 for(;;) {
3134 schedule();
3135 if (signal_pending(current)) {
3136 rc = -ERESTARTSYS;
3137 break;
3138 }
3139
3140 /* get new irq counts */
3141 spin_lock_irqsave(&info->lock,flags);
3142 cnow = info->icount;
3143 set_current_state(TASK_INTERRUPTIBLE);
3144 spin_unlock_irqrestore(&info->lock,flags);
3145
3146 /* if no change, wait aborted for some reason */
3147 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3148 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3149 rc = -EIO;
3150 break;
3151 }
3152
3153 /* check for change in caller specified modem input */
3154 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3155 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3156 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3157 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3158 rc = 0;
3159 break;
3160 }
3161
3162 cprev = cnow;
3163 }
3164 remove_wait_queue(&info->status_event_wait_q, &wait);
3165 set_current_state(TASK_RUNNING);
3166 return rc;
3167}
3168
3169/*
3170 * return state of serial control and status signals
3171 */
3172static int tiocmget(struct tty_struct *tty)
3173{
3174 struct slgt_info *info = tty->driver_data;
3175 unsigned int result;
3176 unsigned long flags;
3177
3178 spin_lock_irqsave(&info->lock,flags);
3179 get_signals(info);
3180 spin_unlock_irqrestore(&info->lock,flags);
3181
3182 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3183 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3184 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3185 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3186 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3187 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3188
3189 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3190 return result;
3191}
3192
3193/*
3194 * set modem control signals (DTR/RTS)
3195 *
3196 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3197 * TIOCMSET = set/clear signal values
3198 * value bit mask for command
3199 */
3200static int tiocmset(struct tty_struct *tty,
3201 unsigned int set, unsigned int clear)
3202{
3203 struct slgt_info *info = tty->driver_data;
3204 unsigned long flags;
3205
3206 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3207
3208 if (set & TIOCM_RTS)
3209 info->signals |= SerialSignal_RTS;
3210 if (set & TIOCM_DTR)
3211 info->signals |= SerialSignal_DTR;
3212 if (clear & TIOCM_RTS)
3213 info->signals &= ~SerialSignal_RTS;
3214 if (clear & TIOCM_DTR)
3215 info->signals &= ~SerialSignal_DTR;
3216
3217 spin_lock_irqsave(&info->lock,flags);
3218 set_signals(info);
3219 spin_unlock_irqrestore(&info->lock,flags);
3220 return 0;
3221}
3222
3223static int carrier_raised(struct tty_port *port)
3224{
3225 unsigned long flags;
3226 struct slgt_info *info = container_of(port, struct slgt_info, port);
3227
3228 spin_lock_irqsave(&info->lock,flags);
3229 get_signals(info);
3230 spin_unlock_irqrestore(&info->lock,flags);
3231 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3232}
3233
3234static void dtr_rts(struct tty_port *port, int on)
3235{
3236 unsigned long flags;
3237 struct slgt_info *info = container_of(port, struct slgt_info, port);
3238
3239 spin_lock_irqsave(&info->lock,flags);
3240 if (on)
3241 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3242 else
3243 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3244 set_signals(info);
3245 spin_unlock_irqrestore(&info->lock,flags);
3246}
3247
3248
3249/*
3250 * block current process until the device is ready to open
3251 */
3252static int block_til_ready(struct tty_struct *tty, struct file *filp,
3253 struct slgt_info *info)
3254{
3255 DECLARE_WAITQUEUE(wait, current);
3256 int retval;
3257 bool do_clocal = false;
3258 unsigned long flags;
3259 int cd;
3260 struct tty_port *port = &info->port;
3261
3262 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3263
3264 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3265 /* nonblock mode is set or port is not enabled */
3266 tty_port_set_active(port, 1);
3267 return 0;
3268 }
3269
3270 if (C_CLOCAL(tty))
3271 do_clocal = true;
3272
3273 /* Wait for carrier detect and the line to become
3274 * free (i.e., not in use by the callout). While we are in
3275 * this loop, port->count is dropped by one, so that
3276 * close() knows when to free things. We restore it upon
3277 * exit, either normal or abnormal.
3278 */
3279
3280 retval = 0;
3281 add_wait_queue(&port->open_wait, &wait);
3282
3283 spin_lock_irqsave(&info->lock, flags);
3284 port->count--;
3285 spin_unlock_irqrestore(&info->lock, flags);
3286 port->blocked_open++;
3287
3288 while (1) {
3289 if (C_BAUD(tty) && tty_port_initialized(port))
3290 tty_port_raise_dtr_rts(port);
3291
3292 set_current_state(TASK_INTERRUPTIBLE);
3293
3294 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3295 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3296 -EAGAIN : -ERESTARTSYS;
3297 break;
3298 }
3299
3300 cd = tty_port_carrier_raised(port);
3301 if (do_clocal || cd)
3302 break;
3303
3304 if (signal_pending(current)) {
3305 retval = -ERESTARTSYS;
3306 break;
3307 }
3308
3309 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3310 tty_unlock(tty);
3311 schedule();
3312 tty_lock(tty);
3313 }
3314
3315 set_current_state(TASK_RUNNING);
3316 remove_wait_queue(&port->open_wait, &wait);
3317
3318 if (!tty_hung_up_p(filp))
3319 port->count++;
3320 port->blocked_open--;
3321
3322 if (!retval)
3323 tty_port_set_active(port, 1);
3324
3325 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3326 return retval;
3327}
3328
3329/*
3330 * allocate buffers used for calling line discipline receive_buf
3331 * directly in synchronous mode
3332 * note: add 5 bytes to max frame size to allow appending
3333 * 32-bit CRC and status byte when configured to do so
3334 */
3335static int alloc_tmp_rbuf(struct slgt_info *info)
3336{
3337 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3338 if (info->tmp_rbuf == NULL)
3339 return -ENOMEM;
3340 /* unused flag buffer to satisfy receive_buf calling interface */
3341 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3342 if (!info->flag_buf) {
3343 kfree(info->tmp_rbuf);
3344 info->tmp_rbuf = NULL;
3345 return -ENOMEM;
3346 }
3347 return 0;
3348}
3349
3350static void free_tmp_rbuf(struct slgt_info *info)
3351{
3352 kfree(info->tmp_rbuf);
3353 info->tmp_rbuf = NULL;
3354 kfree(info->flag_buf);
3355 info->flag_buf = NULL;
3356}
3357
3358/*
3359 * allocate DMA descriptor lists.
3360 */
3361static int alloc_desc(struct slgt_info *info)
3362{
3363 unsigned int i;
3364 unsigned int pbufs;
3365
3366 /* allocate memory to hold descriptor lists */
3367 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3368 &info->bufs_dma_addr);
3369 if (info->bufs == NULL)
3370 return -ENOMEM;
3371
3372 info->rbufs = (struct slgt_desc*)info->bufs;
3373 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3374
3375 pbufs = (unsigned int)info->bufs_dma_addr;
3376
3377 /*
3378 * Build circular lists of descriptors
3379 */
3380
3381 for (i=0; i < info->rbuf_count; i++) {
3382 /* physical address of this descriptor */
3383 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3384
3385 /* physical address of next descriptor */
3386 if (i == info->rbuf_count - 1)
3387 info->rbufs[i].next = cpu_to_le32(pbufs);
3388 else
3389 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3390 set_desc_count(info->rbufs[i], DMABUFSIZE);
3391 }
3392
3393 for (i=0; i < info->tbuf_count; i++) {
3394 /* physical address of this descriptor */
3395 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3396
3397 /* physical address of next descriptor */
3398 if (i == info->tbuf_count - 1)
3399 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3400 else
3401 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3402 }
3403
3404 return 0;
3405}
3406
3407static void free_desc(struct slgt_info *info)
3408{
3409 if (info->bufs != NULL) {
3410 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3411 info->bufs = NULL;
3412 info->rbufs = NULL;
3413 info->tbufs = NULL;
3414 }
3415}
3416
3417static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3418{
3419 int i;
3420 for (i=0; i < count; i++) {
3421 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3422 return -ENOMEM;
3423 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3424 }
3425 return 0;
3426}
3427
3428static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3429{
3430 int i;
3431 for (i=0; i < count; i++) {
3432 if (bufs[i].buf == NULL)
3433 continue;
3434 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3435 bufs[i].buf = NULL;
3436 }
3437}
3438
3439static int alloc_dma_bufs(struct slgt_info *info)
3440{
3441 info->rbuf_count = 32;
3442 info->tbuf_count = 32;
3443
3444 if (alloc_desc(info) < 0 ||
3445 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3446 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3447 alloc_tmp_rbuf(info) < 0) {
3448 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3449 return -ENOMEM;
3450 }
3451 reset_rbufs(info);
3452 return 0;
3453}
3454
3455static void free_dma_bufs(struct slgt_info *info)
3456{
3457 if (info->bufs) {
3458 free_bufs(info, info->rbufs, info->rbuf_count);
3459 free_bufs(info, info->tbufs, info->tbuf_count);
3460 free_desc(info);
3461 }
3462 free_tmp_rbuf(info);
3463}
3464
3465static int claim_resources(struct slgt_info *info)
3466{
3467 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3468 DBGERR(("%s reg addr conflict, addr=%08X\n",
3469 info->device_name, info->phys_reg_addr));
3470 info->init_error = DiagStatus_AddressConflict;
3471 goto errout;
3472 }
3473 else
3474 info->reg_addr_requested = true;
3475
3476 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3477 if (!info->reg_addr) {
3478 DBGERR(("%s can't map device registers, addr=%08X\n",
3479 info->device_name, info->phys_reg_addr));
3480 info->init_error = DiagStatus_CantAssignPciResources;
3481 goto errout;
3482 }
3483 return 0;
3484
3485errout:
3486 release_resources(info);
3487 return -ENODEV;
3488}
3489
3490static void release_resources(struct slgt_info *info)
3491{
3492 if (info->irq_requested) {
3493 free_irq(info->irq_level, info);
3494 info->irq_requested = false;
3495 }
3496
3497 if (info->reg_addr_requested) {
3498 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3499 info->reg_addr_requested = false;
3500 }
3501
3502 if (info->reg_addr) {
3503 iounmap(info->reg_addr);
3504 info->reg_addr = NULL;
3505 }
3506}
3507
3508/* Add the specified device instance data structure to the
3509 * global linked list of devices and increment the device count.
3510 */
3511static void add_device(struct slgt_info *info)
3512{
3513 char *devstr;
3514
3515 info->next_device = NULL;
3516 info->line = slgt_device_count;
3517 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3518
3519 if (info->line < MAX_DEVICES) {
3520 if (maxframe[info->line])
3521 info->max_frame_size = maxframe[info->line];
3522 }
3523
3524 slgt_device_count++;
3525
3526 if (!slgt_device_list)
3527 slgt_device_list = info;
3528 else {
3529 struct slgt_info *current_dev = slgt_device_list;
3530 while(current_dev->next_device)
3531 current_dev = current_dev->next_device;
3532 current_dev->next_device = info;
3533 }
3534
3535 if (info->max_frame_size < 4096)
3536 info->max_frame_size = 4096;
3537 else if (info->max_frame_size > 65535)
3538 info->max_frame_size = 65535;
3539
3540 switch(info->pdev->device) {
3541 case SYNCLINK_GT_DEVICE_ID:
3542 devstr = "GT";
3543 break;
3544 case SYNCLINK_GT2_DEVICE_ID:
3545 devstr = "GT2";
3546 break;
3547 case SYNCLINK_GT4_DEVICE_ID:
3548 devstr = "GT4";
3549 break;
3550 case SYNCLINK_AC_DEVICE_ID:
3551 devstr = "AC";
3552 info->params.mode = MGSL_MODE_ASYNC;
3553 break;
3554 default:
3555 devstr = "(unknown model)";
3556 }
3557 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3558 devstr, info->device_name, info->phys_reg_addr,
3559 info->irq_level, info->max_frame_size);
3560
3561#if SYNCLINK_GENERIC_HDLC
3562 hdlcdev_init(info);
3563#endif
3564}
3565
3566static const struct tty_port_operations slgt_port_ops = {
3567 .carrier_raised = carrier_raised,
3568 .dtr_rts = dtr_rts,
3569};
3570
3571/*
3572 * allocate device instance structure, return NULL on failure
3573 */
3574static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3575{
3576 struct slgt_info *info;
3577
3578 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3579
3580 if (!info) {
3581 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3582 driver_name, adapter_num, port_num));
3583 } else {
3584 tty_port_init(&info->port);
3585 info->port.ops = &slgt_port_ops;
3586 info->magic = MGSL_MAGIC;
3587 INIT_WORK(&info->task, bh_handler);
3588 info->max_frame_size = 4096;
3589 info->base_clock = 14745600;
3590 info->rbuf_fill_level = DMABUFSIZE;
3591 info->port.close_delay = 5*HZ/10;
3592 info->port.closing_wait = 30*HZ;
3593 init_waitqueue_head(&info->status_event_wait_q);
3594 init_waitqueue_head(&info->event_wait_q);
3595 spin_lock_init(&info->netlock);
3596 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3597 info->idle_mode = HDLC_TXIDLE_FLAGS;
3598 info->adapter_num = adapter_num;
3599 info->port_num = port_num;
3600
3601 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3602 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3603
3604 /* Copy configuration info to device instance data */
3605 info->pdev = pdev;
3606 info->irq_level = pdev->irq;
3607 info->phys_reg_addr = pci_resource_start(pdev,0);
3608
3609 info->bus_type = MGSL_BUS_TYPE_PCI;
3610 info->irq_flags = IRQF_SHARED;
3611
3612 info->init_error = -1; /* assume error, set to 0 on successful init */
3613 }
3614
3615 return info;
3616}
3617
3618static void device_init(int adapter_num, struct pci_dev *pdev)
3619{
3620 struct slgt_info *port_array[SLGT_MAX_PORTS];
3621 int i;
3622 int port_count = 1;
3623
3624 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3625 port_count = 2;
3626 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3627 port_count = 4;
3628
3629 /* allocate device instances for all ports */
3630 for (i=0; i < port_count; ++i) {
3631 port_array[i] = alloc_dev(adapter_num, i, pdev);
3632 if (port_array[i] == NULL) {
3633 for (--i; i >= 0; --i) {
3634 tty_port_destroy(&port_array[i]->port);
3635 kfree(port_array[i]);
3636 }
3637 return;
3638 }
3639 }
3640
3641 /* give copy of port_array to all ports and add to device list */
3642 for (i=0; i < port_count; ++i) {
3643 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3644 add_device(port_array[i]);
3645 port_array[i]->port_count = port_count;
3646 spin_lock_init(&port_array[i]->lock);
3647 }
3648
3649 /* Allocate and claim adapter resources */
3650 if (!claim_resources(port_array[0])) {
3651
3652 alloc_dma_bufs(port_array[0]);
3653
3654 /* copy resource information from first port to others */
3655 for (i = 1; i < port_count; ++i) {
3656 port_array[i]->irq_level = port_array[0]->irq_level;
3657 port_array[i]->reg_addr = port_array[0]->reg_addr;
3658 alloc_dma_bufs(port_array[i]);
3659 }
3660
3661 if (request_irq(port_array[0]->irq_level,
3662 slgt_interrupt,
3663 port_array[0]->irq_flags,
3664 port_array[0]->device_name,
3665 port_array[0]) < 0) {
3666 DBGERR(("%s request_irq failed IRQ=%d\n",
3667 port_array[0]->device_name,
3668 port_array[0]->irq_level));
3669 } else {
3670 port_array[0]->irq_requested = true;
3671 adapter_test(port_array[0]);
3672 for (i=1 ; i < port_count ; i++) {
3673 port_array[i]->init_error = port_array[0]->init_error;
3674 port_array[i]->gpio_present = port_array[0]->gpio_present;
3675 }
3676 }
3677 }
3678
3679 for (i = 0; i < port_count; ++i) {
3680 struct slgt_info *info = port_array[i];
3681 tty_port_register_device(&info->port, serial_driver, info->line,
3682 &info->pdev->dev);
3683 }
3684}
3685
3686static int init_one(struct pci_dev *dev,
3687 const struct pci_device_id *ent)
3688{
3689 if (pci_enable_device(dev)) {
3690 printk("error enabling pci device %p\n", dev);
3691 return -EIO;
3692 }
3693 pci_set_master(dev);
3694 device_init(slgt_device_count, dev);
3695 return 0;
3696}
3697
3698static void remove_one(struct pci_dev *dev)
3699{
3700}
3701
3702static const struct tty_operations ops = {
3703 .open = open,
3704 .close = close,
3705 .write = write,
3706 .put_char = put_char,
3707 .flush_chars = flush_chars,
3708 .write_room = write_room,
3709 .chars_in_buffer = chars_in_buffer,
3710 .flush_buffer = flush_buffer,
3711 .ioctl = ioctl,
3712 .compat_ioctl = slgt_compat_ioctl,
3713 .throttle = throttle,
3714 .unthrottle = unthrottle,
3715 .send_xchar = send_xchar,
3716 .break_ctl = set_break,
3717 .wait_until_sent = wait_until_sent,
3718 .set_termios = set_termios,
3719 .stop = tx_hold,
3720 .start = tx_release,
3721 .hangup = hangup,
3722 .tiocmget = tiocmget,
3723 .tiocmset = tiocmset,
3724 .get_icount = get_icount,
3725 .proc_fops = &synclink_gt_proc_fops,
3726};
3727
3728static void slgt_cleanup(void)
3729{
3730 int rc;
3731 struct slgt_info *info;
3732 struct slgt_info *tmp;
3733
3734 printk(KERN_INFO "unload %s\n", driver_name);
3735
3736 if (serial_driver) {
3737 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3738 tty_unregister_device(serial_driver, info->line);
3739 rc = tty_unregister_driver(serial_driver);
3740 if (rc)
3741 DBGERR(("tty_unregister_driver error=%d\n", rc));
3742 put_tty_driver(serial_driver);
3743 }
3744
3745 /* reset devices */
3746 info = slgt_device_list;
3747 while(info) {
3748 reset_port(info);
3749 info = info->next_device;
3750 }
3751
3752 /* release devices */
3753 info = slgt_device_list;
3754 while(info) {
3755#if SYNCLINK_GENERIC_HDLC
3756 hdlcdev_exit(info);
3757#endif
3758 free_dma_bufs(info);
3759 free_tmp_rbuf(info);
3760 if (info->port_num == 0)
3761 release_resources(info);
3762 tmp = info;
3763 info = info->next_device;
3764 tty_port_destroy(&tmp->port);
3765 kfree(tmp);
3766 }
3767
3768 if (pci_registered)
3769 pci_unregister_driver(&pci_driver);
3770}
3771
3772/*
3773 * Driver initialization entry point.
3774 */
3775static int __init slgt_init(void)
3776{
3777 int rc;
3778
3779 printk(KERN_INFO "%s\n", driver_name);
3780
3781 serial_driver = alloc_tty_driver(MAX_DEVICES);
3782 if (!serial_driver) {
3783 printk("%s can't allocate tty driver\n", driver_name);
3784 return -ENOMEM;
3785 }
3786
3787 /* Initialize the tty_driver structure */
3788
3789 serial_driver->driver_name = slgt_driver_name;
3790 serial_driver->name = tty_dev_prefix;
3791 serial_driver->major = ttymajor;
3792 serial_driver->minor_start = 64;
3793 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3794 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3795 serial_driver->init_termios = tty_std_termios;
3796 serial_driver->init_termios.c_cflag =
3797 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3798 serial_driver->init_termios.c_ispeed = 9600;
3799 serial_driver->init_termios.c_ospeed = 9600;
3800 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3801 tty_set_operations(serial_driver, &ops);
3802 if ((rc = tty_register_driver(serial_driver)) < 0) {
3803 DBGERR(("%s can't register serial driver\n", driver_name));
3804 put_tty_driver(serial_driver);
3805 serial_driver = NULL;
3806 goto error;
3807 }
3808
3809 printk(KERN_INFO "%s, tty major#%d\n",
3810 driver_name, serial_driver->major);
3811
3812 slgt_device_count = 0;
3813 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3814 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3815 goto error;
3816 }
3817 pci_registered = true;
3818
3819 if (!slgt_device_list)
3820 printk("%s no devices found\n",driver_name);
3821
3822 return 0;
3823
3824error:
3825 slgt_cleanup();
3826 return rc;
3827}
3828
3829static void __exit slgt_exit(void)
3830{
3831 slgt_cleanup();
3832}
3833
3834module_init(slgt_init);
3835module_exit(slgt_exit);
3836
3837/*
3838 * register access routines
3839 */
3840
3841#define CALC_REGADDR() \
3842 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3843 if (addr >= 0x80) \
3844 reg_addr += (info->port_num) * 32; \
3845 else if (addr >= 0x40) \
3846 reg_addr += (info->port_num) * 16;
3847
3848static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3849{
3850 CALC_REGADDR();
3851 return readb((void __iomem *)reg_addr);
3852}
3853
3854static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3855{
3856 CALC_REGADDR();
3857 writeb(value, (void __iomem *)reg_addr);
3858}
3859
3860static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3861{
3862 CALC_REGADDR();
3863 return readw((void __iomem *)reg_addr);
3864}
3865
3866static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3867{
3868 CALC_REGADDR();
3869 writew(value, (void __iomem *)reg_addr);
3870}
3871
3872static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3873{
3874 CALC_REGADDR();
3875 return readl((void __iomem *)reg_addr);
3876}
3877
3878static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3879{
3880 CALC_REGADDR();
3881 writel(value, (void __iomem *)reg_addr);
3882}
3883
3884static void rdma_reset(struct slgt_info *info)
3885{
3886 unsigned int i;
3887
3888 /* set reset bit */
3889 wr_reg32(info, RDCSR, BIT1);
3890
3891 /* wait for enable bit cleared */
3892 for(i=0 ; i < 1000 ; i++)
3893 if (!(rd_reg32(info, RDCSR) & BIT0))
3894 break;
3895}
3896
3897static void tdma_reset(struct slgt_info *info)
3898{
3899 unsigned int i;
3900
3901 /* set reset bit */
3902 wr_reg32(info, TDCSR, BIT1);
3903
3904 /* wait for enable bit cleared */
3905 for(i=0 ; i < 1000 ; i++)
3906 if (!(rd_reg32(info, TDCSR) & BIT0))
3907 break;
3908}
3909
3910/*
3911 * enable internal loopback
3912 * TxCLK and RxCLK are generated from BRG
3913 * and TxD is looped back to RxD internally.
3914 */
3915static void enable_loopback(struct slgt_info *info)
3916{
3917 /* SCR (serial control) BIT2=loopback enable */
3918 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3919
3920 if (info->params.mode != MGSL_MODE_ASYNC) {
3921 /* CCR (clock control)
3922 * 07..05 tx clock source (010 = BRG)
3923 * 04..02 rx clock source (010 = BRG)
3924 * 01 auxclk enable (0 = disable)
3925 * 00 BRG enable (1 = enable)
3926 *
3927 * 0100 1001
3928 */
3929 wr_reg8(info, CCR, 0x49);
3930
3931 /* set speed if available, otherwise use default */
3932 if (info->params.clock_speed)
3933 set_rate(info, info->params.clock_speed);
3934 else
3935 set_rate(info, 3686400);
3936 }
3937}
3938
3939/*
3940 * set baud rate generator to specified rate
3941 */
3942static void set_rate(struct slgt_info *info, u32 rate)
3943{
3944 unsigned int div;
3945 unsigned int osc = info->base_clock;
3946
3947 /* div = osc/rate - 1
3948 *
3949 * Round div up if osc/rate is not integer to
3950 * force to next slowest rate.
3951 */
3952
3953 if (rate) {
3954 div = osc/rate;
3955 if (!(osc % rate) && div)
3956 div--;
3957 wr_reg16(info, BDR, (unsigned short)div);
3958 }
3959}
3960
3961static void rx_stop(struct slgt_info *info)
3962{
3963 unsigned short val;
3964
3965 /* disable and reset receiver */
3966 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3967 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3968 wr_reg16(info, RCR, val); /* clear reset bit */
3969
3970 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3971
3972 /* clear pending rx interrupts */
3973 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3974
3975 rdma_reset(info);
3976
3977 info->rx_enabled = false;
3978 info->rx_restart = false;
3979}
3980
3981static void rx_start(struct slgt_info *info)
3982{
3983 unsigned short val;
3984
3985 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3986
3987 /* clear pending rx overrun IRQ */
3988 wr_reg16(info, SSR, IRQ_RXOVER);
3989
3990 /* reset and disable receiver */
3991 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3992 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3993 wr_reg16(info, RCR, val); /* clear reset bit */
3994
3995 rdma_reset(info);
3996 reset_rbufs(info);
3997
3998 if (info->rx_pio) {
3999 /* rx request when rx FIFO not empty */
4000 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4001 slgt_irq_on(info, IRQ_RXDATA);
4002 if (info->params.mode == MGSL_MODE_ASYNC) {
4003 /* enable saving of rx status */
4004 wr_reg32(info, RDCSR, BIT6);
4005 }
4006 } else {
4007 /* rx request when rx FIFO half full */
4008 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4009 /* set 1st descriptor address */
4010 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4011
4012 if (info->params.mode != MGSL_MODE_ASYNC) {
4013 /* enable rx DMA and DMA interrupt */
4014 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4015 } else {
4016 /* enable saving of rx status, rx DMA and DMA interrupt */
4017 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4018 }
4019 }
4020
4021 slgt_irq_on(info, IRQ_RXOVER);
4022
4023 /* enable receiver */
4024 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4025
4026 info->rx_restart = false;
4027 info->rx_enabled = true;
4028}
4029
4030static void tx_start(struct slgt_info *info)
4031{
4032 if (!info->tx_enabled) {
4033 wr_reg16(info, TCR,
4034 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4035 info->tx_enabled = true;
4036 }
4037
4038 if (desc_count(info->tbufs[info->tbuf_start])) {
4039 info->drop_rts_on_tx_done = false;
4040
4041 if (info->params.mode != MGSL_MODE_ASYNC) {
4042 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4043 get_signals(info);
4044 if (!(info->signals & SerialSignal_RTS)) {
4045 info->signals |= SerialSignal_RTS;
4046 set_signals(info);
4047 info->drop_rts_on_tx_done = true;
4048 }
4049 }
4050
4051 slgt_irq_off(info, IRQ_TXDATA);
4052 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4053 /* clear tx idle and underrun status bits */
4054 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4055 } else {
4056 slgt_irq_off(info, IRQ_TXDATA);
4057 slgt_irq_on(info, IRQ_TXIDLE);
4058 /* clear tx idle status bit */
4059 wr_reg16(info, SSR, IRQ_TXIDLE);
4060 }
4061 /* set 1st descriptor address and start DMA */
4062 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4063 wr_reg32(info, TDCSR, BIT2 + BIT0);
4064 info->tx_active = true;
4065 }
4066}
4067
4068static void tx_stop(struct slgt_info *info)
4069{
4070 unsigned short val;
4071
4072 del_timer(&info->tx_timer);
4073
4074 tdma_reset(info);
4075
4076 /* reset and disable transmitter */
4077 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4078 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4079
4080 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4081
4082 /* clear tx idle and underrun status bit */
4083 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4084
4085 reset_tbufs(info);
4086
4087 info->tx_enabled = false;
4088 info->tx_active = false;
4089}
4090
4091static void reset_port(struct slgt_info *info)
4092{
4093 if (!info->reg_addr)
4094 return;
4095
4096 tx_stop(info);
4097 rx_stop(info);
4098
4099 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4100 set_signals(info);
4101
4102 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4103}
4104
4105static void reset_adapter(struct slgt_info *info)
4106{
4107 int i;
4108 for (i=0; i < info->port_count; ++i) {
4109 if (info->port_array[i])
4110 reset_port(info->port_array[i]);
4111 }
4112}
4113
4114static void async_mode(struct slgt_info *info)
4115{
4116 unsigned short val;
4117
4118 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4119 tx_stop(info);
4120 rx_stop(info);
4121
4122 /* TCR (tx control)
4123 *
4124 * 15..13 mode, 010=async
4125 * 12..10 encoding, 000=NRZ
4126 * 09 parity enable
4127 * 08 1=odd parity, 0=even parity
4128 * 07 1=RTS driver control
4129 * 06 1=break enable
4130 * 05..04 character length
4131 * 00=5 bits
4132 * 01=6 bits
4133 * 10=7 bits
4134 * 11=8 bits
4135 * 03 0=1 stop bit, 1=2 stop bits
4136 * 02 reset
4137 * 01 enable
4138 * 00 auto-CTS enable
4139 */
4140 val = 0x4000;
4141
4142 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4143 val |= BIT7;
4144
4145 if (info->params.parity != ASYNC_PARITY_NONE) {
4146 val |= BIT9;
4147 if (info->params.parity == ASYNC_PARITY_ODD)
4148 val |= BIT8;
4149 }
4150
4151 switch (info->params.data_bits)
4152 {
4153 case 6: val |= BIT4; break;
4154 case 7: val |= BIT5; break;
4155 case 8: val |= BIT5 + BIT4; break;
4156 }
4157
4158 if (info->params.stop_bits != 1)
4159 val |= BIT3;
4160
4161 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4162 val |= BIT0;
4163
4164 wr_reg16(info, TCR, val);
4165
4166 /* RCR (rx control)
4167 *
4168 * 15..13 mode, 010=async
4169 * 12..10 encoding, 000=NRZ
4170 * 09 parity enable
4171 * 08 1=odd parity, 0=even parity
4172 * 07..06 reserved, must be 0
4173 * 05..04 character length
4174 * 00=5 bits
4175 * 01=6 bits
4176 * 10=7 bits
4177 * 11=8 bits
4178 * 03 reserved, must be zero
4179 * 02 reset
4180 * 01 enable
4181 * 00 auto-DCD enable
4182 */
4183 val = 0x4000;
4184
4185 if (info->params.parity != ASYNC_PARITY_NONE) {
4186 val |= BIT9;
4187 if (info->params.parity == ASYNC_PARITY_ODD)
4188 val |= BIT8;
4189 }
4190
4191 switch (info->params.data_bits)
4192 {
4193 case 6: val |= BIT4; break;
4194 case 7: val |= BIT5; break;
4195 case 8: val |= BIT5 + BIT4; break;
4196 }
4197
4198 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4199 val |= BIT0;
4200
4201 wr_reg16(info, RCR, val);
4202
4203 /* CCR (clock control)
4204 *
4205 * 07..05 011 = tx clock source is BRG/16
4206 * 04..02 010 = rx clock source is BRG
4207 * 01 0 = auxclk disabled
4208 * 00 1 = BRG enabled
4209 *
4210 * 0110 1001
4211 */
4212 wr_reg8(info, CCR, 0x69);
4213
4214 msc_set_vcr(info);
4215
4216 /* SCR (serial control)
4217 *
4218 * 15 1=tx req on FIFO half empty
4219 * 14 1=rx req on FIFO half full
4220 * 13 tx data IRQ enable
4221 * 12 tx idle IRQ enable
4222 * 11 rx break on IRQ enable
4223 * 10 rx data IRQ enable
4224 * 09 rx break off IRQ enable
4225 * 08 overrun IRQ enable
4226 * 07 DSR IRQ enable
4227 * 06 CTS IRQ enable
4228 * 05 DCD IRQ enable
4229 * 04 RI IRQ enable
4230 * 03 0=16x sampling, 1=8x sampling
4231 * 02 1=txd->rxd internal loopback enable
4232 * 01 reserved, must be zero
4233 * 00 1=master IRQ enable
4234 */
4235 val = BIT15 + BIT14 + BIT0;
4236 /* JCR[8] : 1 = x8 async mode feature available */
4237 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4238 ((info->base_clock < (info->params.data_rate * 16)) ||
4239 (info->base_clock % (info->params.data_rate * 16)))) {
4240 /* use 8x sampling */
4241 val |= BIT3;
4242 set_rate(info, info->params.data_rate * 8);
4243 } else {
4244 /* use 16x sampling */
4245 set_rate(info, info->params.data_rate * 16);
4246 }
4247 wr_reg16(info, SCR, val);
4248
4249 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4250
4251 if (info->params.loopback)
4252 enable_loopback(info);
4253}
4254
4255static void sync_mode(struct slgt_info *info)
4256{
4257 unsigned short val;
4258
4259 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4260 tx_stop(info);
4261 rx_stop(info);
4262
4263 /* TCR (tx control)
4264 *
4265 * 15..13 mode
4266 * 000=HDLC/SDLC
4267 * 001=raw bit synchronous
4268 * 010=asynchronous/isochronous
4269 * 011=monosync byte synchronous
4270 * 100=bisync byte synchronous
4271 * 101=xsync byte synchronous
4272 * 12..10 encoding
4273 * 09 CRC enable
4274 * 08 CRC32
4275 * 07 1=RTS driver control
4276 * 06 preamble enable
4277 * 05..04 preamble length
4278 * 03 share open/close flag
4279 * 02 reset
4280 * 01 enable
4281 * 00 auto-CTS enable
4282 */
4283 val = BIT2;
4284
4285 switch(info->params.mode) {
4286 case MGSL_MODE_XSYNC:
4287 val |= BIT15 + BIT13;
4288 break;
4289 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4290 case MGSL_MODE_BISYNC: val |= BIT15; break;
4291 case MGSL_MODE_RAW: val |= BIT13; break;
4292 }
4293 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4294 val |= BIT7;
4295
4296 switch(info->params.encoding)
4297 {
4298 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4299 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4300 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4301 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4302 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4303 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4304 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4305 }
4306
4307 switch (info->params.crc_type & HDLC_CRC_MASK)
4308 {
4309 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4310 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4311 }
4312
4313 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4314 val |= BIT6;
4315
4316 switch (info->params.preamble_length)
4317 {
4318 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4319 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4320 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4321 }
4322
4323 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4324 val |= BIT0;
4325
4326 wr_reg16(info, TCR, val);
4327
4328 /* TPR (transmit preamble) */
4329
4330 switch (info->params.preamble)
4331 {
4332 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4333 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4334 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4335 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4336 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4337 default: val = 0x7e; break;
4338 }
4339 wr_reg8(info, TPR, (unsigned char)val);
4340
4341 /* RCR (rx control)
4342 *
4343 * 15..13 mode
4344 * 000=HDLC/SDLC
4345 * 001=raw bit synchronous
4346 * 010=asynchronous/isochronous
4347 * 011=monosync byte synchronous
4348 * 100=bisync byte synchronous
4349 * 101=xsync byte synchronous
4350 * 12..10 encoding
4351 * 09 CRC enable
4352 * 08 CRC32
4353 * 07..03 reserved, must be 0
4354 * 02 reset
4355 * 01 enable
4356 * 00 auto-DCD enable
4357 */
4358 val = 0;
4359
4360 switch(info->params.mode) {
4361 case MGSL_MODE_XSYNC:
4362 val |= BIT15 + BIT13;
4363 break;
4364 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4365 case MGSL_MODE_BISYNC: val |= BIT15; break;
4366 case MGSL_MODE_RAW: val |= BIT13; break;
4367 }
4368
4369 switch(info->params.encoding)
4370 {
4371 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4372 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4373 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4374 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4375 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4376 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4377 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4378 }
4379
4380 switch (info->params.crc_type & HDLC_CRC_MASK)
4381 {
4382 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4383 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4384 }
4385
4386 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4387 val |= BIT0;
4388
4389 wr_reg16(info, RCR, val);
4390
4391 /* CCR (clock control)
4392 *
4393 * 07..05 tx clock source
4394 * 04..02 rx clock source
4395 * 01 auxclk enable
4396 * 00 BRG enable
4397 */
4398 val = 0;
4399
4400 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4401 {
4402 // when RxC source is DPLL, BRG generates 16X DPLL
4403 // reference clock, so take TxC from BRG/16 to get
4404 // transmit clock at actual data rate
4405 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4406 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4407 else
4408 val |= BIT6; /* 010, txclk = BRG */
4409 }
4410 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4411 val |= BIT7; /* 100, txclk = DPLL Input */
4412 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4413 val |= BIT5; /* 001, txclk = RXC Input */
4414
4415 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4416 val |= BIT3; /* 010, rxclk = BRG */
4417 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4418 val |= BIT4; /* 100, rxclk = DPLL */
4419 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4420 val |= BIT2; /* 001, rxclk = TXC Input */
4421
4422 if (info->params.clock_speed)
4423 val |= BIT1 + BIT0;
4424
4425 wr_reg8(info, CCR, (unsigned char)val);
4426
4427 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4428 {
4429 // program DPLL mode
4430 switch(info->params.encoding)
4431 {
4432 case HDLC_ENCODING_BIPHASE_MARK:
4433 case HDLC_ENCODING_BIPHASE_SPACE:
4434 val = BIT7; break;
4435 case HDLC_ENCODING_BIPHASE_LEVEL:
4436 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4437 val = BIT7 + BIT6; break;
4438 default: val = BIT6; // NRZ encodings
4439 }
4440 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4441
4442 // DPLL requires a 16X reference clock from BRG
4443 set_rate(info, info->params.clock_speed * 16);
4444 }
4445 else
4446 set_rate(info, info->params.clock_speed);
4447
4448 tx_set_idle(info);
4449
4450 msc_set_vcr(info);
4451
4452 /* SCR (serial control)
4453 *
4454 * 15 1=tx req on FIFO half empty
4455 * 14 1=rx req on FIFO half full
4456 * 13 tx data IRQ enable
4457 * 12 tx idle IRQ enable
4458 * 11 underrun IRQ enable
4459 * 10 rx data IRQ enable
4460 * 09 rx idle IRQ enable
4461 * 08 overrun IRQ enable
4462 * 07 DSR IRQ enable
4463 * 06 CTS IRQ enable
4464 * 05 DCD IRQ enable
4465 * 04 RI IRQ enable
4466 * 03 reserved, must be zero
4467 * 02 1=txd->rxd internal loopback enable
4468 * 01 reserved, must be zero
4469 * 00 1=master IRQ enable
4470 */
4471 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4472
4473 if (info->params.loopback)
4474 enable_loopback(info);
4475}
4476
4477/*
4478 * set transmit idle mode
4479 */
4480static void tx_set_idle(struct slgt_info *info)
4481{
4482 unsigned char val;
4483 unsigned short tcr;
4484
4485 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4486 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4487 */
4488 tcr = rd_reg16(info, TCR);
4489 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4490 /* disable preamble, set idle size to 16 bits */
4491 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4492 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4493 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4494 } else if (!(tcr & BIT6)) {
4495 /* preamble is disabled, set idle size to 8 bits */
4496 tcr &= ~(BIT5 + BIT4);
4497 }
4498 wr_reg16(info, TCR, tcr);
4499
4500 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4501 /* LSB of custom tx idle specified in tx idle register */
4502 val = (unsigned char)(info->idle_mode & 0xff);
4503 } else {
4504 /* standard 8 bit idle patterns */
4505 switch(info->idle_mode)
4506 {
4507 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4508 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4509 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4510 case HDLC_TXIDLE_ZEROS:
4511 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4512 default: val = 0xff;
4513 }
4514 }
4515
4516 wr_reg8(info, TIR, val);
4517}
4518
4519/*
4520 * get state of V24 status (input) signals
4521 */
4522static void get_signals(struct slgt_info *info)
4523{
4524 unsigned short status = rd_reg16(info, SSR);
4525
4526 /* clear all serial signals except RTS and DTR */
4527 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4528
4529 if (status & BIT3)
4530 info->signals |= SerialSignal_DSR;
4531 if (status & BIT2)
4532 info->signals |= SerialSignal_CTS;
4533 if (status & BIT1)
4534 info->signals |= SerialSignal_DCD;
4535 if (status & BIT0)
4536 info->signals |= SerialSignal_RI;
4537}
4538
4539/*
4540 * set V.24 Control Register based on current configuration
4541 */
4542static void msc_set_vcr(struct slgt_info *info)
4543{
4544 unsigned char val = 0;
4545
4546 /* VCR (V.24 control)
4547 *
4548 * 07..04 serial IF select
4549 * 03 DTR
4550 * 02 RTS
4551 * 01 LL
4552 * 00 RL
4553 */
4554
4555 switch(info->if_mode & MGSL_INTERFACE_MASK)
4556 {
4557 case MGSL_INTERFACE_RS232:
4558 val |= BIT5; /* 0010 */
4559 break;
4560 case MGSL_INTERFACE_V35:
4561 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4562 break;
4563 case MGSL_INTERFACE_RS422:
4564 val |= BIT6; /* 0100 */
4565 break;
4566 }
4567
4568 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4569 val |= BIT4;
4570 if (info->signals & SerialSignal_DTR)
4571 val |= BIT3;
4572 if (info->signals & SerialSignal_RTS)
4573 val |= BIT2;
4574 if (info->if_mode & MGSL_INTERFACE_LL)
4575 val |= BIT1;
4576 if (info->if_mode & MGSL_INTERFACE_RL)
4577 val |= BIT0;
4578 wr_reg8(info, VCR, val);
4579}
4580
4581/*
4582 * set state of V24 control (output) signals
4583 */
4584static void set_signals(struct slgt_info *info)
4585{
4586 unsigned char val = rd_reg8(info, VCR);
4587 if (info->signals & SerialSignal_DTR)
4588 val |= BIT3;
4589 else
4590 val &= ~BIT3;
4591 if (info->signals & SerialSignal_RTS)
4592 val |= BIT2;
4593 else
4594 val &= ~BIT2;
4595 wr_reg8(info, VCR, val);
4596}
4597
4598/*
4599 * free range of receive DMA buffers (i to last)
4600 */
4601static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4602{
4603 int done = 0;
4604
4605 while(!done) {
4606 /* reset current buffer for reuse */
4607 info->rbufs[i].status = 0;
4608 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4609 if (i == last)
4610 done = 1;
4611 if (++i == info->rbuf_count)
4612 i = 0;
4613 }
4614 info->rbuf_current = i;
4615}
4616
4617/*
4618 * mark all receive DMA buffers as free
4619 */
4620static void reset_rbufs(struct slgt_info *info)
4621{
4622 free_rbufs(info, 0, info->rbuf_count - 1);
4623 info->rbuf_fill_index = 0;
4624 info->rbuf_fill_count = 0;
4625}
4626
4627/*
4628 * pass receive HDLC frame to upper layer
4629 *
4630 * return true if frame available, otherwise false
4631 */
4632static bool rx_get_frame(struct slgt_info *info)
4633{
4634 unsigned int start, end;
4635 unsigned short status;
4636 unsigned int framesize = 0;
4637 unsigned long flags;
4638 struct tty_struct *tty = info->port.tty;
4639 unsigned char addr_field = 0xff;
4640 unsigned int crc_size = 0;
4641
4642 switch (info->params.crc_type & HDLC_CRC_MASK) {
4643 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4644 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4645 }
4646
4647check_again:
4648
4649 framesize = 0;
4650 addr_field = 0xff;
4651 start = end = info->rbuf_current;
4652
4653 for (;;) {
4654 if (!desc_complete(info->rbufs[end]))
4655 goto cleanup;
4656
4657 if (framesize == 0 && info->params.addr_filter != 0xff)
4658 addr_field = info->rbufs[end].buf[0];
4659
4660 framesize += desc_count(info->rbufs[end]);
4661
4662 if (desc_eof(info->rbufs[end]))
4663 break;
4664
4665 if (++end == info->rbuf_count)
4666 end = 0;
4667
4668 if (end == info->rbuf_current) {
4669 if (info->rx_enabled){
4670 spin_lock_irqsave(&info->lock,flags);
4671 rx_start(info);
4672 spin_unlock_irqrestore(&info->lock,flags);
4673 }
4674 goto cleanup;
4675 }
4676 }
4677
4678 /* status
4679 *
4680 * 15 buffer complete
4681 * 14..06 reserved
4682 * 05..04 residue
4683 * 02 eof (end of frame)
4684 * 01 CRC error
4685 * 00 abort
4686 */
4687 status = desc_status(info->rbufs[end]);
4688
4689 /* ignore CRC bit if not using CRC (bit is undefined) */
4690 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4691 status &= ~BIT1;
4692
4693 if (framesize == 0 ||
4694 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4695 free_rbufs(info, start, end);
4696 goto check_again;
4697 }
4698
4699 if (framesize < (2 + crc_size) || status & BIT0) {
4700 info->icount.rxshort++;
4701 framesize = 0;
4702 } else if (status & BIT1) {
4703 info->icount.rxcrc++;
4704 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4705 framesize = 0;
4706 }
4707
4708#if SYNCLINK_GENERIC_HDLC
4709 if (framesize == 0) {
4710 info->netdev->stats.rx_errors++;
4711 info->netdev->stats.rx_frame_errors++;
4712 }
4713#endif
4714
4715 DBGBH(("%s rx frame status=%04X size=%d\n",
4716 info->device_name, status, framesize));
4717 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4718
4719 if (framesize) {
4720 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4721 framesize -= crc_size;
4722 crc_size = 0;
4723 }
4724
4725 if (framesize > info->max_frame_size + crc_size)
4726 info->icount.rxlong++;
4727 else {
4728 /* copy dma buffer(s) to contiguous temp buffer */
4729 int copy_count = framesize;
4730 int i = start;
4731 unsigned char *p = info->tmp_rbuf;
4732 info->tmp_rbuf_count = framesize;
4733
4734 info->icount.rxok++;
4735
4736 while(copy_count) {
4737 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4738 memcpy(p, info->rbufs[i].buf, partial_count);
4739 p += partial_count;
4740 copy_count -= partial_count;
4741 if (++i == info->rbuf_count)
4742 i = 0;
4743 }
4744
4745 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4746 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4747 framesize++;
4748 }
4749
4750#if SYNCLINK_GENERIC_HDLC
4751 if (info->netcount)
4752 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4753 else
4754#endif
4755 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4756 }
4757 }
4758 free_rbufs(info, start, end);
4759 return true;
4760
4761cleanup:
4762 return false;
4763}
4764
4765/*
4766 * pass receive buffer (RAW synchronous mode) to tty layer
4767 * return true if buffer available, otherwise false
4768 */
4769static bool rx_get_buf(struct slgt_info *info)
4770{
4771 unsigned int i = info->rbuf_current;
4772 unsigned int count;
4773
4774 if (!desc_complete(info->rbufs[i]))
4775 return false;
4776 count = desc_count(info->rbufs[i]);
4777 switch(info->params.mode) {
4778 case MGSL_MODE_MONOSYNC:
4779 case MGSL_MODE_BISYNC:
4780 case MGSL_MODE_XSYNC:
4781 /* ignore residue in byte synchronous modes */
4782 if (desc_residue(info->rbufs[i]))
4783 count--;
4784 break;
4785 }
4786 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4787 DBGINFO(("rx_get_buf size=%d\n", count));
4788 if (count)
4789 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4790 info->flag_buf, count);
4791 free_rbufs(info, i, i);
4792 return true;
4793}
4794
4795static void reset_tbufs(struct slgt_info *info)
4796{
4797 unsigned int i;
4798 info->tbuf_current = 0;
4799 for (i=0 ; i < info->tbuf_count ; i++) {
4800 info->tbufs[i].status = 0;
4801 info->tbufs[i].count = 0;
4802 }
4803}
4804
4805/*
4806 * return number of free transmit DMA buffers
4807 */
4808static unsigned int free_tbuf_count(struct slgt_info *info)
4809{
4810 unsigned int count = 0;
4811 unsigned int i = info->tbuf_current;
4812
4813 do
4814 {
4815 if (desc_count(info->tbufs[i]))
4816 break; /* buffer in use */
4817 ++count;
4818 if (++i == info->tbuf_count)
4819 i=0;
4820 } while (i != info->tbuf_current);
4821
4822 /* if tx DMA active, last zero count buffer is in use */
4823 if (count && (rd_reg32(info, TDCSR) & BIT0))
4824 --count;
4825
4826 return count;
4827}
4828
4829/*
4830 * return number of bytes in unsent transmit DMA buffers
4831 * and the serial controller tx FIFO
4832 */
4833static unsigned int tbuf_bytes(struct slgt_info *info)
4834{
4835 unsigned int total_count = 0;
4836 unsigned int i = info->tbuf_current;
4837 unsigned int reg_value;
4838 unsigned int count;
4839 unsigned int active_buf_count = 0;
4840
4841 /*
4842 * Add descriptor counts for all tx DMA buffers.
4843 * If count is zero (cleared by DMA controller after read),
4844 * the buffer is complete or is actively being read from.
4845 *
4846 * Record buf_count of last buffer with zero count starting
4847 * from current ring position. buf_count is mirror
4848 * copy of count and is not cleared by serial controller.
4849 * If DMA controller is active, that buffer is actively
4850 * being read so add to total.
4851 */
4852 do {
4853 count = desc_count(info->tbufs[i]);
4854 if (count)
4855 total_count += count;
4856 else if (!total_count)
4857 active_buf_count = info->tbufs[i].buf_count;
4858 if (++i == info->tbuf_count)
4859 i = 0;
4860 } while (i != info->tbuf_current);
4861
4862 /* read tx DMA status register */
4863 reg_value = rd_reg32(info, TDCSR);
4864
4865 /* if tx DMA active, last zero count buffer is in use */
4866 if (reg_value & BIT0)
4867 total_count += active_buf_count;
4868
4869 /* add tx FIFO count = reg_value[15..8] */
4870 total_count += (reg_value >> 8) & 0xff;
4871
4872 /* if transmitter active add one byte for shift register */
4873 if (info->tx_active)
4874 total_count++;
4875
4876 return total_count;
4877}
4878
4879/*
4880 * load data into transmit DMA buffer ring and start transmitter if needed
4881 * return true if data accepted, otherwise false (buffers full)
4882 */
4883static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4884{
4885 unsigned short count;
4886 unsigned int i;
4887 struct slgt_desc *d;
4888
4889 /* check required buffer space */
4890 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4891 return false;
4892
4893 DBGDATA(info, buf, size, "tx");
4894
4895 /*
4896 * copy data to one or more DMA buffers in circular ring
4897 * tbuf_start = first buffer for this data
4898 * tbuf_current = next free buffer
4899 *
4900 * Copy all data before making data visible to DMA controller by
4901 * setting descriptor count of the first buffer.
4902 * This prevents an active DMA controller from reading the first DMA
4903 * buffers of a frame and stopping before the final buffers are filled.
4904 */
4905
4906 info->tbuf_start = i = info->tbuf_current;
4907
4908 while (size) {
4909 d = &info->tbufs[i];
4910
4911 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4912 memcpy(d->buf, buf, count);
4913
4914 size -= count;
4915 buf += count;
4916
4917 /*
4918 * set EOF bit for last buffer of HDLC frame or
4919 * for every buffer in raw mode
4920 */
4921 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4922 info->params.mode == MGSL_MODE_RAW)
4923 set_desc_eof(*d, 1);
4924 else
4925 set_desc_eof(*d, 0);
4926
4927 /* set descriptor count for all but first buffer */
4928 if (i != info->tbuf_start)
4929 set_desc_count(*d, count);
4930 d->buf_count = count;
4931
4932 if (++i == info->tbuf_count)
4933 i = 0;
4934 }
4935
4936 info->tbuf_current = i;
4937
4938 /* set first buffer count to make new data visible to DMA controller */
4939 d = &info->tbufs[info->tbuf_start];
4940 set_desc_count(*d, d->buf_count);
4941
4942 /* start transmitter if needed and update transmit timeout */
4943 if (!info->tx_active)
4944 tx_start(info);
4945 update_tx_timer(info);
4946
4947 return true;
4948}
4949
4950static int register_test(struct slgt_info *info)
4951{
4952 static unsigned short patterns[] =
4953 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4954 static unsigned int count = ARRAY_SIZE(patterns);
4955 unsigned int i;
4956 int rc = 0;
4957
4958 for (i=0 ; i < count ; i++) {
4959 wr_reg16(info, TIR, patterns[i]);
4960 wr_reg16(info, BDR, patterns[(i+1)%count]);
4961 if ((rd_reg16(info, TIR) != patterns[i]) ||
4962 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4963 rc = -ENODEV;
4964 break;
4965 }
4966 }
4967 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4968 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4969 return rc;
4970}
4971
4972static int irq_test(struct slgt_info *info)
4973{
4974 unsigned long timeout;
4975 unsigned long flags;
4976 struct tty_struct *oldtty = info->port.tty;
4977 u32 speed = info->params.data_rate;
4978
4979 info->params.data_rate = 921600;
4980 info->port.tty = NULL;
4981
4982 spin_lock_irqsave(&info->lock, flags);
4983 async_mode(info);
4984 slgt_irq_on(info, IRQ_TXIDLE);
4985
4986 /* enable transmitter */
4987 wr_reg16(info, TCR,
4988 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4989
4990 /* write one byte and wait for tx idle */
4991 wr_reg16(info, TDR, 0);
4992
4993 /* assume failure */
4994 info->init_error = DiagStatus_IrqFailure;
4995 info->irq_occurred = false;
4996
4997 spin_unlock_irqrestore(&info->lock, flags);
4998
4999 timeout=100;
5000 while(timeout-- && !info->irq_occurred)
5001 msleep_interruptible(10);
5002
5003 spin_lock_irqsave(&info->lock,flags);
5004 reset_port(info);
5005 spin_unlock_irqrestore(&info->lock,flags);
5006
5007 info->params.data_rate = speed;
5008 info->port.tty = oldtty;
5009
5010 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5011 return info->irq_occurred ? 0 : -ENODEV;
5012}
5013
5014static int loopback_test_rx(struct slgt_info *info)
5015{
5016 unsigned char *src, *dest;
5017 int count;
5018
5019 if (desc_complete(info->rbufs[0])) {
5020 count = desc_count(info->rbufs[0]);
5021 src = info->rbufs[0].buf;
5022 dest = info->tmp_rbuf;
5023
5024 for( ; count ; count-=2, src+=2) {
5025 /* src=data byte (src+1)=status byte */
5026 if (!(*(src+1) & (BIT9 + BIT8))) {
5027 *dest = *src;
5028 dest++;
5029 info->tmp_rbuf_count++;
5030 }
5031 }
5032 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5033 return 1;
5034 }
5035 return 0;
5036}
5037
5038static int loopback_test(struct slgt_info *info)
5039{
5040#define TESTFRAMESIZE 20
5041
5042 unsigned long timeout;
5043 u16 count = TESTFRAMESIZE;
5044 unsigned char buf[TESTFRAMESIZE];
5045 int rc = -ENODEV;
5046 unsigned long flags;
5047
5048 struct tty_struct *oldtty = info->port.tty;
5049 MGSL_PARAMS params;
5050
5051 memcpy(¶ms, &info->params, sizeof(params));
5052
5053 info->params.mode = MGSL_MODE_ASYNC;
5054 info->params.data_rate = 921600;
5055 info->params.loopback = 1;
5056 info->port.tty = NULL;
5057
5058 /* build and send transmit frame */
5059 for (count = 0; count < TESTFRAMESIZE; ++count)
5060 buf[count] = (unsigned char)count;
5061
5062 info->tmp_rbuf_count = 0;
5063 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5064
5065 /* program hardware for HDLC and enabled receiver */
5066 spin_lock_irqsave(&info->lock,flags);
5067 async_mode(info);
5068 rx_start(info);
5069 tx_load(info, buf, count);
5070 spin_unlock_irqrestore(&info->lock, flags);
5071
5072 /* wait for receive complete */
5073 for (timeout = 100; timeout; --timeout) {
5074 msleep_interruptible(10);
5075 if (loopback_test_rx(info)) {
5076 rc = 0;
5077 break;
5078 }
5079 }
5080
5081 /* verify received frame length and contents */
5082 if (!rc && (info->tmp_rbuf_count != count ||
5083 memcmp(buf, info->tmp_rbuf, count))) {
5084 rc = -ENODEV;
5085 }
5086
5087 spin_lock_irqsave(&info->lock,flags);
5088 reset_adapter(info);
5089 spin_unlock_irqrestore(&info->lock,flags);
5090
5091 memcpy(&info->params, ¶ms, sizeof(info->params));
5092 info->port.tty = oldtty;
5093
5094 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5095 return rc;
5096}
5097
5098static int adapter_test(struct slgt_info *info)
5099{
5100 DBGINFO(("testing %s\n", info->device_name));
5101 if (register_test(info) < 0) {
5102 printk("register test failure %s addr=%08X\n",
5103 info->device_name, info->phys_reg_addr);
5104 } else if (irq_test(info) < 0) {
5105 printk("IRQ test failure %s IRQ=%d\n",
5106 info->device_name, info->irq_level);
5107 } else if (loopback_test(info) < 0) {
5108 printk("loopback test failure %s\n", info->device_name);
5109 }
5110 return info->init_error;
5111}
5112
5113/*
5114 * transmit timeout handler
5115 */
5116static void tx_timeout(unsigned long context)
5117{
5118 struct slgt_info *info = (struct slgt_info*)context;
5119 unsigned long flags;
5120
5121 DBGINFO(("%s tx_timeout\n", info->device_name));
5122 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5123 info->icount.txtimeout++;
5124 }
5125 spin_lock_irqsave(&info->lock,flags);
5126 tx_stop(info);
5127 spin_unlock_irqrestore(&info->lock,flags);
5128
5129#if SYNCLINK_GENERIC_HDLC
5130 if (info->netcount)
5131 hdlcdev_tx_done(info);
5132 else
5133#endif
5134 bh_transmit(info);
5135}
5136
5137/*
5138 * receive buffer polling timer
5139 */
5140static void rx_timeout(unsigned long context)
5141{
5142 struct slgt_info *info = (struct slgt_info*)context;
5143 unsigned long flags;
5144
5145 DBGINFO(("%s rx_timeout\n", info->device_name));
5146 spin_lock_irqsave(&info->lock, flags);
5147 info->pending_bh |= BH_RECEIVE;
5148 spin_unlock_irqrestore(&info->lock, flags);
5149 bh_handler(&info->task);
5150}
5151