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1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static const char driver_name[] = "SyncLink GT";
91static const char tty_dev_prefix[] = "ttySLG";
92MODULE_LICENSE("GPL");
93#define MAX_DEVICES 32
94
95static const struct pci_device_id pci_table[] = {
96 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT_DEVICE_ID) },
97 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT2_DEVICE_ID) },
98 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT4_DEVICE_ID) },
99 { PCI_VDEVICE(MICROGATE, SYNCLINK_AC_DEVICE_ID) },
100 { 0 }, /* terminate list */
101};
102MODULE_DEVICE_TABLE(pci, pci_table);
103
104static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
105static void remove_one(struct pci_dev *dev);
106static struct pci_driver pci_driver = {
107 .name = "synclink_gt",
108 .id_table = pci_table,
109 .probe = init_one,
110 .remove = remove_one,
111};
112
113static bool pci_registered;
114
115/*
116 * module configuration and status
117 */
118static struct slgt_info *slgt_device_list;
119static int slgt_device_count;
120
121static int ttymajor;
122static int debug_level;
123static int maxframe[MAX_DEVICES];
124
125module_param(ttymajor, int, 0);
126module_param(debug_level, int, 0);
127module_param_array(maxframe, int, NULL, 0);
128
129MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
130MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
131MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
132
133/*
134 * tty support and callbacks
135 */
136static struct tty_driver *serial_driver;
137
138static void wait_until_sent(struct tty_struct *tty, int timeout);
139static void flush_buffer(struct tty_struct *tty);
140static void tx_release(struct tty_struct *tty);
141
142/*
143 * generic HDLC support
144 */
145#define dev_to_port(D) (dev_to_hdlc(D)->priv)
146
147
148/*
149 * device specific structures, macros and functions
150 */
151
152#define SLGT_MAX_PORTS 4
153#define SLGT_REG_SIZE 256
154
155/*
156 * conditional wait facility
157 */
158struct cond_wait {
159 struct cond_wait *next;
160 wait_queue_head_t q;
161 wait_queue_entry_t wait;
162 unsigned int data;
163};
164static void flush_cond_wait(struct cond_wait **head);
165
166/*
167 * DMA buffer descriptor and access macros
168 */
169struct slgt_desc
170{
171 __le16 count;
172 __le16 status;
173 __le32 pbuf; /* physical address of data buffer */
174 __le32 next; /* physical address of next descriptor */
175
176 /* driver book keeping */
177 char *buf; /* virtual address of data buffer */
178 unsigned int pdesc; /* physical address of this descriptor */
179 dma_addr_t buf_dma_addr;
180 unsigned short buf_count;
181};
182
183#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
184#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
185#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
186#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
187#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
188#define desc_count(a) (le16_to_cpu((a).count))
189#define desc_status(a) (le16_to_cpu((a).status))
190#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
191#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
192#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
193#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
194#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
195
196struct _input_signal_events {
197 int ri_up;
198 int ri_down;
199 int dsr_up;
200 int dsr_down;
201 int dcd_up;
202 int dcd_down;
203 int cts_up;
204 int cts_down;
205};
206
207/*
208 * device instance data structure
209 */
210struct slgt_info {
211 void *if_ptr; /* General purpose pointer (used by SPPP) */
212 struct tty_port port;
213
214 struct slgt_info *next_device; /* device list link */
215
216 char device_name[25];
217 struct pci_dev *pdev;
218
219 int port_count; /* count of ports on adapter */
220 int adapter_num; /* adapter instance number */
221 int port_num; /* port instance number */
222
223 /* array of pointers to port contexts on this adapter */
224 struct slgt_info *port_array[SLGT_MAX_PORTS];
225
226 int line; /* tty line instance number */
227
228 struct mgsl_icount icount;
229
230 int timeout;
231 int x_char; /* xon/xoff character */
232 unsigned int read_status_mask;
233 unsigned int ignore_status_mask;
234
235 wait_queue_head_t status_event_wait_q;
236 wait_queue_head_t event_wait_q;
237 struct timer_list tx_timer;
238 struct timer_list rx_timer;
239
240 unsigned int gpio_present;
241 struct cond_wait *gpio_wait_q;
242
243 spinlock_t lock; /* spinlock for synchronizing with ISR */
244
245 struct work_struct task;
246 u32 pending_bh;
247 bool bh_requested;
248 bool bh_running;
249
250 int isr_overflow;
251 bool irq_requested; /* true if IRQ requested */
252 bool irq_occurred; /* for diagnostics use */
253
254 /* device configuration */
255
256 unsigned int bus_type;
257 unsigned int irq_level;
258 unsigned long irq_flags;
259
260 unsigned char __iomem * reg_addr; /* memory mapped registers address */
261 u32 phys_reg_addr;
262 bool reg_addr_requested;
263
264 MGSL_PARAMS params; /* communications parameters */
265 u32 idle_mode;
266 u32 max_frame_size; /* as set by device config */
267
268 unsigned int rbuf_fill_level;
269 unsigned int rx_pio;
270 unsigned int if_mode;
271 unsigned int base_clock;
272 unsigned int xsync;
273 unsigned int xctrl;
274
275 /* device status */
276
277 bool rx_enabled;
278 bool rx_restart;
279
280 bool tx_enabled;
281 bool tx_active;
282
283 unsigned char signals; /* serial signal states */
284 int init_error; /* initialization error */
285
286 unsigned char *tx_buf;
287 int tx_count;
288
289 bool drop_rts_on_tx_done;
290 struct _input_signal_events input_signal_events;
291
292 int dcd_chkcount; /* check counts to prevent */
293 int cts_chkcount; /* too many IRQs if a signal */
294 int dsr_chkcount; /* is floating */
295 int ri_chkcount;
296
297 char *bufs; /* virtual address of DMA buffer lists */
298 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
299
300 unsigned int rbuf_count;
301 struct slgt_desc *rbufs;
302 unsigned int rbuf_current;
303 unsigned int rbuf_index;
304 unsigned int rbuf_fill_index;
305 unsigned short rbuf_fill_count;
306
307 unsigned int tbuf_count;
308 struct slgt_desc *tbufs;
309 unsigned int tbuf_current;
310 unsigned int tbuf_start;
311
312 unsigned char *tmp_rbuf;
313 unsigned int tmp_rbuf_count;
314
315 /* SPPP/Cisco HDLC device parts */
316
317 int netcount;
318 spinlock_t netlock;
319#if SYNCLINK_GENERIC_HDLC
320 struct net_device *netdev;
321#endif
322
323};
324
325static const MGSL_PARAMS default_params = {
326 .mode = MGSL_MODE_HDLC,
327 .loopback = 0,
328 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
329 .encoding = HDLC_ENCODING_NRZI_SPACE,
330 .clock_speed = 0,
331 .addr_filter = 0xff,
332 .crc_type = HDLC_CRC_16_CCITT,
333 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
334 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
335 .data_rate = 9600,
336 .data_bits = 8,
337 .stop_bits = 1,
338 .parity = ASYNC_PARITY_NONE
339};
340
341
342#define BH_RECEIVE 1
343#define BH_TRANSMIT 2
344#define BH_STATUS 4
345#define IO_PIN_SHUTDOWN_LIMIT 100
346
347#define DMABUFSIZE 256
348#define DESC_LIST_SIZE 4096
349
350#define MASK_PARITY BIT1
351#define MASK_FRAMING BIT0
352#define MASK_BREAK BIT14
353#define MASK_OVERRUN BIT4
354
355#define GSR 0x00 /* global status */
356#define JCR 0x04 /* JTAG control */
357#define IODR 0x08 /* GPIO direction */
358#define IOER 0x0c /* GPIO interrupt enable */
359#define IOVR 0x10 /* GPIO value */
360#define IOSR 0x14 /* GPIO interrupt status */
361#define TDR 0x80 /* tx data */
362#define RDR 0x80 /* rx data */
363#define TCR 0x82 /* tx control */
364#define TIR 0x84 /* tx idle */
365#define TPR 0x85 /* tx preamble */
366#define RCR 0x86 /* rx control */
367#define VCR 0x88 /* V.24 control */
368#define CCR 0x89 /* clock control */
369#define BDR 0x8a /* baud divisor */
370#define SCR 0x8c /* serial control */
371#define SSR 0x8e /* serial status */
372#define RDCSR 0x90 /* rx DMA control/status */
373#define TDCSR 0x94 /* tx DMA control/status */
374#define RDDAR 0x98 /* rx DMA descriptor address */
375#define TDDAR 0x9c /* tx DMA descriptor address */
376#define XSR 0x40 /* extended sync pattern */
377#define XCR 0x44 /* extended control */
378
379#define RXIDLE BIT14
380#define RXBREAK BIT14
381#define IRQ_TXDATA BIT13
382#define IRQ_TXIDLE BIT12
383#define IRQ_TXUNDER BIT11 /* HDLC */
384#define IRQ_RXDATA BIT10
385#define IRQ_RXIDLE BIT9 /* HDLC */
386#define IRQ_RXBREAK BIT9 /* async */
387#define IRQ_RXOVER BIT8
388#define IRQ_DSR BIT7
389#define IRQ_CTS BIT6
390#define IRQ_DCD BIT5
391#define IRQ_RI BIT4
392#define IRQ_ALL 0x3ff0
393#define IRQ_MASTER BIT0
394
395#define slgt_irq_on(info, mask) \
396 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
397#define slgt_irq_off(info, mask) \
398 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
399
400static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
401static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
402static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
403static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
404static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
405static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
406
407static void msc_set_vcr(struct slgt_info *info);
408
409static int startup(struct slgt_info *info);
410static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
411static void shutdown(struct slgt_info *info);
412static void program_hw(struct slgt_info *info);
413static void change_params(struct slgt_info *info);
414
415static int adapter_test(struct slgt_info *info);
416
417static void reset_port(struct slgt_info *info);
418static void async_mode(struct slgt_info *info);
419static void sync_mode(struct slgt_info *info);
420
421static void rx_stop(struct slgt_info *info);
422static void rx_start(struct slgt_info *info);
423static void reset_rbufs(struct slgt_info *info);
424static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
425static bool rx_get_frame(struct slgt_info *info);
426static bool rx_get_buf(struct slgt_info *info);
427
428static void tx_start(struct slgt_info *info);
429static void tx_stop(struct slgt_info *info);
430static void tx_set_idle(struct slgt_info *info);
431static unsigned int tbuf_bytes(struct slgt_info *info);
432static void reset_tbufs(struct slgt_info *info);
433static void tdma_reset(struct slgt_info *info);
434static bool tx_load(struct slgt_info *info, const u8 *buf, unsigned int count);
435
436static void get_gtsignals(struct slgt_info *info);
437static void set_gtsignals(struct slgt_info *info);
438static void set_rate(struct slgt_info *info, u32 data_rate);
439
440static void bh_transmit(struct slgt_info *info);
441static void isr_txeom(struct slgt_info *info, unsigned short status);
442
443static void tx_timeout(struct timer_list *t);
444static void rx_timeout(struct timer_list *t);
445
446/*
447 * ioctl handlers
448 */
449static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
450static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
451static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
452static int get_txidle(struct slgt_info *info, int __user *idle_mode);
453static int set_txidle(struct slgt_info *info, int idle_mode);
454static int tx_enable(struct slgt_info *info, int enable);
455static int tx_abort(struct slgt_info *info);
456static int rx_enable(struct slgt_info *info, int enable);
457static int modem_input_wait(struct slgt_info *info,int arg);
458static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
459static int get_interface(struct slgt_info *info, int __user *if_mode);
460static int set_interface(struct slgt_info *info, int if_mode);
461static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
462static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
463static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
464static int get_xsync(struct slgt_info *info, int __user *if_mode);
465static int set_xsync(struct slgt_info *info, int if_mode);
466static int get_xctrl(struct slgt_info *info, int __user *if_mode);
467static int set_xctrl(struct slgt_info *info, int if_mode);
468
469/*
470 * driver functions
471 */
472static void release_resources(struct slgt_info *info);
473
474/*
475 * DEBUG OUTPUT CODE
476 */
477#ifndef DBGINFO
478#define DBGINFO(fmt)
479#endif
480#ifndef DBGERR
481#define DBGERR(fmt)
482#endif
483#ifndef DBGBH
484#define DBGBH(fmt)
485#endif
486#ifndef DBGISR
487#define DBGISR(fmt)
488#endif
489
490#ifdef DBGDATA
491static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
492{
493 int i;
494 int linecount;
495 printk("%s %s data:\n",info->device_name, label);
496 while(count) {
497 linecount = (count > 16) ? 16 : count;
498 for(i=0; i < linecount; i++)
499 printk("%02X ",(unsigned char)data[i]);
500 for(;i<17;i++)
501 printk(" ");
502 for(i=0;i<linecount;i++) {
503 if (data[i]>=040 && data[i]<=0176)
504 printk("%c",data[i]);
505 else
506 printk(".");
507 }
508 printk("\n");
509 data += linecount;
510 count -= linecount;
511 }
512}
513#else
514#define DBGDATA(info, buf, size, label)
515#endif
516
517#ifdef DBGTBUF
518static void dump_tbufs(struct slgt_info *info)
519{
520 int i;
521 printk("tbuf_current=%d\n", info->tbuf_current);
522 for (i=0 ; i < info->tbuf_count ; i++) {
523 printk("%d: count=%04X status=%04X\n",
524 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
525 }
526}
527#else
528#define DBGTBUF(info)
529#endif
530
531#ifdef DBGRBUF
532static void dump_rbufs(struct slgt_info *info)
533{
534 int i;
535 printk("rbuf_current=%d\n", info->rbuf_current);
536 for (i=0 ; i < info->rbuf_count ; i++) {
537 printk("%d: count=%04X status=%04X\n",
538 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
539 }
540}
541#else
542#define DBGRBUF(info)
543#endif
544
545static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
546{
547#ifdef SANITY_CHECK
548 if (!info) {
549 printk("null struct slgt_info for (%s) in %s\n", devname, name);
550 return 1;
551 }
552#else
553 if (!info)
554 return 1;
555#endif
556 return 0;
557}
558
559/*
560 * line discipline callback wrappers
561 *
562 * The wrappers maintain line discipline references
563 * while calling into the line discipline.
564 *
565 * ldisc_receive_buf - pass receive data to line discipline
566 */
567static void ldisc_receive_buf(struct tty_struct *tty,
568 const __u8 *data, char *flags, int count)
569{
570 struct tty_ldisc *ld;
571 if (!tty)
572 return;
573 ld = tty_ldisc_ref(tty);
574 if (ld) {
575 if (ld->ops->receive_buf)
576 ld->ops->receive_buf(tty, data, flags, count);
577 tty_ldisc_deref(ld);
578 }
579}
580
581/* tty callbacks */
582
583static int open(struct tty_struct *tty, struct file *filp)
584{
585 struct slgt_info *info;
586 int retval, line;
587 unsigned long flags;
588
589 line = tty->index;
590 if (line >= slgt_device_count) {
591 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
592 return -ENODEV;
593 }
594
595 info = slgt_device_list;
596 while(info && info->line != line)
597 info = info->next_device;
598 if (sanity_check(info, tty->name, "open"))
599 return -ENODEV;
600 if (info->init_error) {
601 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
602 return -ENODEV;
603 }
604
605 tty->driver_data = info;
606 info->port.tty = tty;
607
608 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
609
610 mutex_lock(&info->port.mutex);
611
612 spin_lock_irqsave(&info->netlock, flags);
613 if (info->netcount) {
614 retval = -EBUSY;
615 spin_unlock_irqrestore(&info->netlock, flags);
616 mutex_unlock(&info->port.mutex);
617 goto cleanup;
618 }
619 info->port.count++;
620 spin_unlock_irqrestore(&info->netlock, flags);
621
622 if (info->port.count == 1) {
623 /* 1st open on this device, init hardware */
624 retval = startup(info);
625 if (retval < 0) {
626 mutex_unlock(&info->port.mutex);
627 goto cleanup;
628 }
629 }
630 mutex_unlock(&info->port.mutex);
631 retval = block_til_ready(tty, filp, info);
632 if (retval) {
633 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
634 goto cleanup;
635 }
636
637 retval = 0;
638
639cleanup:
640 if (retval) {
641 if (tty->count == 1)
642 info->port.tty = NULL; /* tty layer will release tty struct */
643 if(info->port.count)
644 info->port.count--;
645 }
646
647 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
648 return retval;
649}
650
651static void close(struct tty_struct *tty, struct file *filp)
652{
653 struct slgt_info *info = tty->driver_data;
654
655 if (sanity_check(info, tty->name, "close"))
656 return;
657 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
658
659 if (tty_port_close_start(&info->port, tty, filp) == 0)
660 goto cleanup;
661
662 mutex_lock(&info->port.mutex);
663 if (tty_port_initialized(&info->port))
664 wait_until_sent(tty, info->timeout);
665 flush_buffer(tty);
666 tty_ldisc_flush(tty);
667
668 shutdown(info);
669 mutex_unlock(&info->port.mutex);
670
671 tty_port_close_end(&info->port, tty);
672 info->port.tty = NULL;
673cleanup:
674 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
675}
676
677static void hangup(struct tty_struct *tty)
678{
679 struct slgt_info *info = tty->driver_data;
680 unsigned long flags;
681
682 if (sanity_check(info, tty->name, "hangup"))
683 return;
684 DBGINFO(("%s hangup\n", info->device_name));
685
686 flush_buffer(tty);
687
688 mutex_lock(&info->port.mutex);
689 shutdown(info);
690
691 spin_lock_irqsave(&info->port.lock, flags);
692 info->port.count = 0;
693 info->port.tty = NULL;
694 spin_unlock_irqrestore(&info->port.lock, flags);
695 tty_port_set_active(&info->port, false);
696 mutex_unlock(&info->port.mutex);
697
698 wake_up_interruptible(&info->port.open_wait);
699}
700
701static void set_termios(struct tty_struct *tty,
702 const struct ktermios *old_termios)
703{
704 struct slgt_info *info = tty->driver_data;
705 unsigned long flags;
706
707 DBGINFO(("%s set_termios\n", tty->driver->name));
708
709 change_params(info);
710
711 /* Handle transition to B0 status */
712 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
713 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
714 spin_lock_irqsave(&info->lock,flags);
715 set_gtsignals(info);
716 spin_unlock_irqrestore(&info->lock,flags);
717 }
718
719 /* Handle transition away from B0 status */
720 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
721 info->signals |= SerialSignal_DTR;
722 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
723 info->signals |= SerialSignal_RTS;
724 spin_lock_irqsave(&info->lock,flags);
725 set_gtsignals(info);
726 spin_unlock_irqrestore(&info->lock,flags);
727 }
728
729 /* Handle turning off CRTSCTS */
730 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
731 tty->hw_stopped = false;
732 tx_release(tty);
733 }
734}
735
736static void update_tx_timer(struct slgt_info *info)
737{
738 /*
739 * use worst case speed of 1200bps to calculate transmit timeout
740 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
741 */
742 if (info->params.mode == MGSL_MODE_HDLC) {
743 int timeout = (tbuf_bytes(info) * 7) + 1000;
744 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
745 }
746}
747
748static ssize_t write(struct tty_struct *tty, const u8 *buf, size_t count)
749{
750 int ret = 0;
751 struct slgt_info *info = tty->driver_data;
752 unsigned long flags;
753
754 if (sanity_check(info, tty->name, "write"))
755 return -EIO;
756
757 DBGINFO(("%s write count=%zu\n", info->device_name, count));
758
759 if (!info->tx_buf || (count > info->max_frame_size))
760 return -EIO;
761
762 if (!count || tty->flow.stopped || tty->hw_stopped)
763 return 0;
764
765 spin_lock_irqsave(&info->lock, flags);
766
767 if (info->tx_count) {
768 /* send accumulated data from send_char() */
769 if (!tx_load(info, info->tx_buf, info->tx_count))
770 goto cleanup;
771 info->tx_count = 0;
772 }
773
774 if (tx_load(info, buf, count))
775 ret = count;
776
777cleanup:
778 spin_unlock_irqrestore(&info->lock, flags);
779 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
780 return ret;
781}
782
783static int put_char(struct tty_struct *tty, u8 ch)
784{
785 struct slgt_info *info = tty->driver_data;
786 unsigned long flags;
787 int ret = 0;
788
789 if (sanity_check(info, tty->name, "put_char"))
790 return 0;
791 DBGINFO(("%s put_char(%u)\n", info->device_name, ch));
792 if (!info->tx_buf)
793 return 0;
794 spin_lock_irqsave(&info->lock,flags);
795 if (info->tx_count < info->max_frame_size) {
796 info->tx_buf[info->tx_count++] = ch;
797 ret = 1;
798 }
799 spin_unlock_irqrestore(&info->lock,flags);
800 return ret;
801}
802
803static void send_xchar(struct tty_struct *tty, char ch)
804{
805 struct slgt_info *info = tty->driver_data;
806 unsigned long flags;
807
808 if (sanity_check(info, tty->name, "send_xchar"))
809 return;
810 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
811 info->x_char = ch;
812 if (ch) {
813 spin_lock_irqsave(&info->lock,flags);
814 if (!info->tx_enabled)
815 tx_start(info);
816 spin_unlock_irqrestore(&info->lock,flags);
817 }
818}
819
820static void wait_until_sent(struct tty_struct *tty, int timeout)
821{
822 struct slgt_info *info = tty->driver_data;
823 unsigned long orig_jiffies, char_time;
824
825 if (!info )
826 return;
827 if (sanity_check(info, tty->name, "wait_until_sent"))
828 return;
829 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
830 if (!tty_port_initialized(&info->port))
831 goto exit;
832
833 orig_jiffies = jiffies;
834
835 /* Set check interval to 1/5 of estimated time to
836 * send a character, and make it at least 1. The check
837 * interval should also be less than the timeout.
838 * Note: use tight timings here to satisfy the NIST-PCTS.
839 */
840
841 if (info->params.data_rate) {
842 char_time = info->timeout/(32 * 5);
843 if (!char_time)
844 char_time++;
845 } else
846 char_time = 1;
847
848 if (timeout)
849 char_time = min_t(unsigned long, char_time, timeout);
850
851 while (info->tx_active) {
852 msleep_interruptible(jiffies_to_msecs(char_time));
853 if (signal_pending(current))
854 break;
855 if (timeout && time_after(jiffies, orig_jiffies + timeout))
856 break;
857 }
858exit:
859 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
860}
861
862static unsigned int write_room(struct tty_struct *tty)
863{
864 struct slgt_info *info = tty->driver_data;
865 unsigned int ret;
866
867 if (sanity_check(info, tty->name, "write_room"))
868 return 0;
869 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
870 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
871 return ret;
872}
873
874static void flush_chars(struct tty_struct *tty)
875{
876 struct slgt_info *info = tty->driver_data;
877 unsigned long flags;
878
879 if (sanity_check(info, tty->name, "flush_chars"))
880 return;
881 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
882
883 if (info->tx_count <= 0 || tty->flow.stopped ||
884 tty->hw_stopped || !info->tx_buf)
885 return;
886
887 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
888
889 spin_lock_irqsave(&info->lock,flags);
890 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
891 info->tx_count = 0;
892 spin_unlock_irqrestore(&info->lock,flags);
893}
894
895static void flush_buffer(struct tty_struct *tty)
896{
897 struct slgt_info *info = tty->driver_data;
898 unsigned long flags;
899
900 if (sanity_check(info, tty->name, "flush_buffer"))
901 return;
902 DBGINFO(("%s flush_buffer\n", info->device_name));
903
904 spin_lock_irqsave(&info->lock, flags);
905 info->tx_count = 0;
906 spin_unlock_irqrestore(&info->lock, flags);
907
908 tty_wakeup(tty);
909}
910
911/*
912 * throttle (stop) transmitter
913 */
914static void tx_hold(struct tty_struct *tty)
915{
916 struct slgt_info *info = tty->driver_data;
917 unsigned long flags;
918
919 if (sanity_check(info, tty->name, "tx_hold"))
920 return;
921 DBGINFO(("%s tx_hold\n", info->device_name));
922 spin_lock_irqsave(&info->lock,flags);
923 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
924 tx_stop(info);
925 spin_unlock_irqrestore(&info->lock,flags);
926}
927
928/*
929 * release (start) transmitter
930 */
931static void tx_release(struct tty_struct *tty)
932{
933 struct slgt_info *info = tty->driver_data;
934 unsigned long flags;
935
936 if (sanity_check(info, tty->name, "tx_release"))
937 return;
938 DBGINFO(("%s tx_release\n", info->device_name));
939 spin_lock_irqsave(&info->lock, flags);
940 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
941 info->tx_count = 0;
942 spin_unlock_irqrestore(&info->lock, flags);
943}
944
945/*
946 * Service an IOCTL request
947 *
948 * Arguments
949 *
950 * tty pointer to tty instance data
951 * cmd IOCTL command code
952 * arg command argument/context
953 *
954 * Return 0 if success, otherwise error code
955 */
956static int ioctl(struct tty_struct *tty,
957 unsigned int cmd, unsigned long arg)
958{
959 struct slgt_info *info = tty->driver_data;
960 void __user *argp = (void __user *)arg;
961 int ret;
962
963 if (sanity_check(info, tty->name, "ioctl"))
964 return -ENODEV;
965 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
966
967 if (cmd != TIOCMIWAIT) {
968 if (tty_io_error(tty))
969 return -EIO;
970 }
971
972 switch (cmd) {
973 case MGSL_IOCWAITEVENT:
974 return wait_mgsl_event(info, argp);
975 case TIOCMIWAIT:
976 return modem_input_wait(info,(int)arg);
977 case MGSL_IOCSGPIO:
978 return set_gpio(info, argp);
979 case MGSL_IOCGGPIO:
980 return get_gpio(info, argp);
981 case MGSL_IOCWAITGPIO:
982 return wait_gpio(info, argp);
983 case MGSL_IOCGXSYNC:
984 return get_xsync(info, argp);
985 case MGSL_IOCSXSYNC:
986 return set_xsync(info, (int)arg);
987 case MGSL_IOCGXCTRL:
988 return get_xctrl(info, argp);
989 case MGSL_IOCSXCTRL:
990 return set_xctrl(info, (int)arg);
991 }
992 mutex_lock(&info->port.mutex);
993 switch (cmd) {
994 case MGSL_IOCGPARAMS:
995 ret = get_params(info, argp);
996 break;
997 case MGSL_IOCSPARAMS:
998 ret = set_params(info, argp);
999 break;
1000 case MGSL_IOCGTXIDLE:
1001 ret = get_txidle(info, argp);
1002 break;
1003 case MGSL_IOCSTXIDLE:
1004 ret = set_txidle(info, (int)arg);
1005 break;
1006 case MGSL_IOCTXENABLE:
1007 ret = tx_enable(info, (int)arg);
1008 break;
1009 case MGSL_IOCRXENABLE:
1010 ret = rx_enable(info, (int)arg);
1011 break;
1012 case MGSL_IOCTXABORT:
1013 ret = tx_abort(info);
1014 break;
1015 case MGSL_IOCGSTATS:
1016 ret = get_stats(info, argp);
1017 break;
1018 case MGSL_IOCGIF:
1019 ret = get_interface(info, argp);
1020 break;
1021 case MGSL_IOCSIF:
1022 ret = set_interface(info,(int)arg);
1023 break;
1024 default:
1025 ret = -ENOIOCTLCMD;
1026 }
1027 mutex_unlock(&info->port.mutex);
1028 return ret;
1029}
1030
1031static int get_icount(struct tty_struct *tty,
1032 struct serial_icounter_struct *icount)
1033
1034{
1035 struct slgt_info *info = tty->driver_data;
1036 struct mgsl_icount cnow; /* kernel counter temps */
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&info->lock,flags);
1040 cnow = info->icount;
1041 spin_unlock_irqrestore(&info->lock,flags);
1042
1043 icount->cts = cnow.cts;
1044 icount->dsr = cnow.dsr;
1045 icount->rng = cnow.rng;
1046 icount->dcd = cnow.dcd;
1047 icount->rx = cnow.rx;
1048 icount->tx = cnow.tx;
1049 icount->frame = cnow.frame;
1050 icount->overrun = cnow.overrun;
1051 icount->parity = cnow.parity;
1052 icount->brk = cnow.brk;
1053 icount->buf_overrun = cnow.buf_overrun;
1054
1055 return 0;
1056}
1057
1058/*
1059 * support for 32 bit ioctl calls on 64 bit systems
1060 */
1061#ifdef CONFIG_COMPAT
1062static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1063{
1064 struct MGSL_PARAMS32 tmp_params;
1065
1066 DBGINFO(("%s get_params32\n", info->device_name));
1067 memset(&tmp_params, 0, sizeof(tmp_params));
1068 tmp_params.mode = (compat_ulong_t)info->params.mode;
1069 tmp_params.loopback = info->params.loopback;
1070 tmp_params.flags = info->params.flags;
1071 tmp_params.encoding = info->params.encoding;
1072 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1073 tmp_params.addr_filter = info->params.addr_filter;
1074 tmp_params.crc_type = info->params.crc_type;
1075 tmp_params.preamble_length = info->params.preamble_length;
1076 tmp_params.preamble = info->params.preamble;
1077 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1078 tmp_params.data_bits = info->params.data_bits;
1079 tmp_params.stop_bits = info->params.stop_bits;
1080 tmp_params.parity = info->params.parity;
1081 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1082 return -EFAULT;
1083 return 0;
1084}
1085
1086static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1087{
1088 struct MGSL_PARAMS32 tmp_params;
1089 unsigned long flags;
1090
1091 DBGINFO(("%s set_params32\n", info->device_name));
1092 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1093 return -EFAULT;
1094
1095 spin_lock_irqsave(&info->lock, flags);
1096 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1097 info->base_clock = tmp_params.clock_speed;
1098 } else {
1099 info->params.mode = tmp_params.mode;
1100 info->params.loopback = tmp_params.loopback;
1101 info->params.flags = tmp_params.flags;
1102 info->params.encoding = tmp_params.encoding;
1103 info->params.clock_speed = tmp_params.clock_speed;
1104 info->params.addr_filter = tmp_params.addr_filter;
1105 info->params.crc_type = tmp_params.crc_type;
1106 info->params.preamble_length = tmp_params.preamble_length;
1107 info->params.preamble = tmp_params.preamble;
1108 info->params.data_rate = tmp_params.data_rate;
1109 info->params.data_bits = tmp_params.data_bits;
1110 info->params.stop_bits = tmp_params.stop_bits;
1111 info->params.parity = tmp_params.parity;
1112 }
1113 spin_unlock_irqrestore(&info->lock, flags);
1114
1115 program_hw(info);
1116
1117 return 0;
1118}
1119
1120static long slgt_compat_ioctl(struct tty_struct *tty,
1121 unsigned int cmd, unsigned long arg)
1122{
1123 struct slgt_info *info = tty->driver_data;
1124 int rc;
1125
1126 if (sanity_check(info, tty->name, "compat_ioctl"))
1127 return -ENODEV;
1128 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1129
1130 switch (cmd) {
1131 case MGSL_IOCSPARAMS32:
1132 rc = set_params32(info, compat_ptr(arg));
1133 break;
1134
1135 case MGSL_IOCGPARAMS32:
1136 rc = get_params32(info, compat_ptr(arg));
1137 break;
1138
1139 case MGSL_IOCGPARAMS:
1140 case MGSL_IOCSPARAMS:
1141 case MGSL_IOCGTXIDLE:
1142 case MGSL_IOCGSTATS:
1143 case MGSL_IOCWAITEVENT:
1144 case MGSL_IOCGIF:
1145 case MGSL_IOCSGPIO:
1146 case MGSL_IOCGGPIO:
1147 case MGSL_IOCWAITGPIO:
1148 case MGSL_IOCGXSYNC:
1149 case MGSL_IOCGXCTRL:
1150 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1151 break;
1152 default:
1153 rc = ioctl(tty, cmd, arg);
1154 }
1155 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1156 return rc;
1157}
1158#else
1159#define slgt_compat_ioctl NULL
1160#endif /* ifdef CONFIG_COMPAT */
1161
1162/*
1163 * proc fs support
1164 */
1165static inline void line_info(struct seq_file *m, struct slgt_info *info)
1166{
1167 char stat_buf[30];
1168 unsigned long flags;
1169
1170 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1171 info->device_name, info->phys_reg_addr,
1172 info->irq_level, info->max_frame_size);
1173
1174 /* output current serial signal states */
1175 spin_lock_irqsave(&info->lock,flags);
1176 get_gtsignals(info);
1177 spin_unlock_irqrestore(&info->lock,flags);
1178
1179 stat_buf[0] = 0;
1180 stat_buf[1] = 0;
1181 if (info->signals & SerialSignal_RTS)
1182 strcat(stat_buf, "|RTS");
1183 if (info->signals & SerialSignal_CTS)
1184 strcat(stat_buf, "|CTS");
1185 if (info->signals & SerialSignal_DTR)
1186 strcat(stat_buf, "|DTR");
1187 if (info->signals & SerialSignal_DSR)
1188 strcat(stat_buf, "|DSR");
1189 if (info->signals & SerialSignal_DCD)
1190 strcat(stat_buf, "|CD");
1191 if (info->signals & SerialSignal_RI)
1192 strcat(stat_buf, "|RI");
1193
1194 if (info->params.mode != MGSL_MODE_ASYNC) {
1195 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1196 info->icount.txok, info->icount.rxok);
1197 if (info->icount.txunder)
1198 seq_printf(m, " txunder:%d", info->icount.txunder);
1199 if (info->icount.txabort)
1200 seq_printf(m, " txabort:%d", info->icount.txabort);
1201 if (info->icount.rxshort)
1202 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1203 if (info->icount.rxlong)
1204 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1205 if (info->icount.rxover)
1206 seq_printf(m, " rxover:%d", info->icount.rxover);
1207 if (info->icount.rxcrc)
1208 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1209 } else {
1210 seq_printf(m, "\tASYNC tx:%d rx:%d",
1211 info->icount.tx, info->icount.rx);
1212 if (info->icount.frame)
1213 seq_printf(m, " fe:%d", info->icount.frame);
1214 if (info->icount.parity)
1215 seq_printf(m, " pe:%d", info->icount.parity);
1216 if (info->icount.brk)
1217 seq_printf(m, " brk:%d", info->icount.brk);
1218 if (info->icount.overrun)
1219 seq_printf(m, " oe:%d", info->icount.overrun);
1220 }
1221
1222 /* Append serial signal status to end */
1223 seq_printf(m, " %s\n", stat_buf+1);
1224
1225 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1226 info->tx_active,info->bh_requested,info->bh_running,
1227 info->pending_bh);
1228}
1229
1230/* Called to print information about devices
1231 */
1232static int synclink_gt_proc_show(struct seq_file *m, void *v)
1233{
1234 struct slgt_info *info;
1235
1236 seq_puts(m, "synclink_gt driver\n");
1237
1238 info = slgt_device_list;
1239 while( info ) {
1240 line_info(m, info);
1241 info = info->next_device;
1242 }
1243 return 0;
1244}
1245
1246/*
1247 * return count of bytes in transmit buffer
1248 */
1249static unsigned int chars_in_buffer(struct tty_struct *tty)
1250{
1251 struct slgt_info *info = tty->driver_data;
1252 unsigned int count;
1253 if (sanity_check(info, tty->name, "chars_in_buffer"))
1254 return 0;
1255 count = tbuf_bytes(info);
1256 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1257 return count;
1258}
1259
1260/*
1261 * signal remote device to throttle send data (our receive data)
1262 */
1263static void throttle(struct tty_struct * tty)
1264{
1265 struct slgt_info *info = tty->driver_data;
1266 unsigned long flags;
1267
1268 if (sanity_check(info, tty->name, "throttle"))
1269 return;
1270 DBGINFO(("%s throttle\n", info->device_name));
1271 if (I_IXOFF(tty))
1272 send_xchar(tty, STOP_CHAR(tty));
1273 if (C_CRTSCTS(tty)) {
1274 spin_lock_irqsave(&info->lock,flags);
1275 info->signals &= ~SerialSignal_RTS;
1276 set_gtsignals(info);
1277 spin_unlock_irqrestore(&info->lock,flags);
1278 }
1279}
1280
1281/*
1282 * signal remote device to stop throttling send data (our receive data)
1283 */
1284static void unthrottle(struct tty_struct * tty)
1285{
1286 struct slgt_info *info = tty->driver_data;
1287 unsigned long flags;
1288
1289 if (sanity_check(info, tty->name, "unthrottle"))
1290 return;
1291 DBGINFO(("%s unthrottle\n", info->device_name));
1292 if (I_IXOFF(tty)) {
1293 if (info->x_char)
1294 info->x_char = 0;
1295 else
1296 send_xchar(tty, START_CHAR(tty));
1297 }
1298 if (C_CRTSCTS(tty)) {
1299 spin_lock_irqsave(&info->lock,flags);
1300 info->signals |= SerialSignal_RTS;
1301 set_gtsignals(info);
1302 spin_unlock_irqrestore(&info->lock,flags);
1303 }
1304}
1305
1306/*
1307 * set or clear transmit break condition
1308 * break_state -1=set break condition, 0=clear
1309 */
1310static int set_break(struct tty_struct *tty, int break_state)
1311{
1312 struct slgt_info *info = tty->driver_data;
1313 unsigned short value;
1314 unsigned long flags;
1315
1316 if (sanity_check(info, tty->name, "set_break"))
1317 return -EINVAL;
1318 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1319
1320 spin_lock_irqsave(&info->lock,flags);
1321 value = rd_reg16(info, TCR);
1322 if (break_state == -1)
1323 value |= BIT6;
1324 else
1325 value &= ~BIT6;
1326 wr_reg16(info, TCR, value);
1327 spin_unlock_irqrestore(&info->lock,flags);
1328 return 0;
1329}
1330
1331#if SYNCLINK_GENERIC_HDLC
1332
1333/**
1334 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1335 * @dev: pointer to network device structure
1336 * @encoding: serial encoding setting
1337 * @parity: FCS setting
1338 *
1339 * Set encoding and frame check sequence (FCS) options.
1340 *
1341 * Return: 0 if success, otherwise error code
1342 */
1343static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1344 unsigned short parity)
1345{
1346 struct slgt_info *info = dev_to_port(dev);
1347 unsigned char new_encoding;
1348 unsigned short new_crctype;
1349
1350 /* return error if TTY interface open */
1351 if (info->port.count)
1352 return -EBUSY;
1353
1354 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1355
1356 switch (encoding)
1357 {
1358 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1359 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1360 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1361 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1362 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1363 default: return -EINVAL;
1364 }
1365
1366 switch (parity)
1367 {
1368 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1369 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1370 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1371 default: return -EINVAL;
1372 }
1373
1374 info->params.encoding = new_encoding;
1375 info->params.crc_type = new_crctype;
1376
1377 /* if network interface up, reprogram hardware */
1378 if (info->netcount)
1379 program_hw(info);
1380
1381 return 0;
1382}
1383
1384/**
1385 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1386 * @skb: socket buffer containing HDLC frame
1387 * @dev: pointer to network device structure
1388 */
1389static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1390 struct net_device *dev)
1391{
1392 struct slgt_info *info = dev_to_port(dev);
1393 unsigned long flags;
1394
1395 DBGINFO(("%s hdlc_xmit\n", dev->name));
1396
1397 if (!skb->len)
1398 return NETDEV_TX_OK;
1399
1400 /* stop sending until this frame completes */
1401 netif_stop_queue(dev);
1402
1403 /* update network statistics */
1404 dev->stats.tx_packets++;
1405 dev->stats.tx_bytes += skb->len;
1406
1407 /* save start time for transmit timeout detection */
1408 netif_trans_update(dev);
1409
1410 spin_lock_irqsave(&info->lock, flags);
1411 tx_load(info, skb->data, skb->len);
1412 spin_unlock_irqrestore(&info->lock, flags);
1413
1414 /* done with socket buffer, so free it */
1415 dev_kfree_skb(skb);
1416
1417 return NETDEV_TX_OK;
1418}
1419
1420/**
1421 * hdlcdev_open - called by network layer when interface enabled
1422 * @dev: pointer to network device structure
1423 *
1424 * Claim resources and initialize hardware.
1425 *
1426 * Return: 0 if success, otherwise error code
1427 */
1428static int hdlcdev_open(struct net_device *dev)
1429{
1430 struct slgt_info *info = dev_to_port(dev);
1431 int rc;
1432 unsigned long flags;
1433
1434 DBGINFO(("%s hdlcdev_open\n", dev->name));
1435
1436 /* arbitrate between network and tty opens */
1437 spin_lock_irqsave(&info->netlock, flags);
1438 if (info->port.count != 0 || info->netcount != 0) {
1439 DBGINFO(("%s hdlc_open busy\n", dev->name));
1440 spin_unlock_irqrestore(&info->netlock, flags);
1441 return -EBUSY;
1442 }
1443 info->netcount=1;
1444 spin_unlock_irqrestore(&info->netlock, flags);
1445
1446 /* claim resources and init adapter */
1447 if ((rc = startup(info)) != 0) {
1448 spin_lock_irqsave(&info->netlock, flags);
1449 info->netcount=0;
1450 spin_unlock_irqrestore(&info->netlock, flags);
1451 return rc;
1452 }
1453
1454 /* generic HDLC layer open processing */
1455 rc = hdlc_open(dev);
1456 if (rc) {
1457 shutdown(info);
1458 spin_lock_irqsave(&info->netlock, flags);
1459 info->netcount = 0;
1460 spin_unlock_irqrestore(&info->netlock, flags);
1461 return rc;
1462 }
1463
1464 /* assert RTS and DTR, apply hardware settings */
1465 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1466 program_hw(info);
1467
1468 /* enable network layer transmit */
1469 netif_trans_update(dev);
1470 netif_start_queue(dev);
1471
1472 /* inform generic HDLC layer of current DCD status */
1473 spin_lock_irqsave(&info->lock, flags);
1474 get_gtsignals(info);
1475 spin_unlock_irqrestore(&info->lock, flags);
1476 if (info->signals & SerialSignal_DCD)
1477 netif_carrier_on(dev);
1478 else
1479 netif_carrier_off(dev);
1480 return 0;
1481}
1482
1483/**
1484 * hdlcdev_close - called by network layer when interface is disabled
1485 * @dev: pointer to network device structure
1486 *
1487 * Shutdown hardware and release resources.
1488 *
1489 * Return: 0 if success, otherwise error code
1490 */
1491static int hdlcdev_close(struct net_device *dev)
1492{
1493 struct slgt_info *info = dev_to_port(dev);
1494 unsigned long flags;
1495
1496 DBGINFO(("%s hdlcdev_close\n", dev->name));
1497
1498 netif_stop_queue(dev);
1499
1500 /* shutdown adapter and release resources */
1501 shutdown(info);
1502
1503 hdlc_close(dev);
1504
1505 spin_lock_irqsave(&info->netlock, flags);
1506 info->netcount=0;
1507 spin_unlock_irqrestore(&info->netlock, flags);
1508
1509 return 0;
1510}
1511
1512/**
1513 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1514 * @dev: pointer to network device structure
1515 * @ifr: pointer to network interface request structure
1516 * @cmd: IOCTL command code
1517 *
1518 * Return: 0 if success, otherwise error code
1519 */
1520static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1521{
1522 const size_t size = sizeof(sync_serial_settings);
1523 sync_serial_settings new_line;
1524 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1525 struct slgt_info *info = dev_to_port(dev);
1526 unsigned int flags;
1527
1528 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1529
1530 /* return error if TTY interface open */
1531 if (info->port.count)
1532 return -EBUSY;
1533
1534 memset(&new_line, 0, sizeof(new_line));
1535
1536 switch (ifs->type) {
1537 case IF_GET_IFACE: /* return current sync_serial_settings */
1538
1539 ifs->type = IF_IFACE_SYNC_SERIAL;
1540 if (ifs->size < size) {
1541 ifs->size = size; /* data size wanted */
1542 return -ENOBUFS;
1543 }
1544
1545 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1546 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1547 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1548 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1549
1550 switch (flags){
1551 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1552 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1553 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1554 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1555 default: new_line.clock_type = CLOCK_DEFAULT;
1556 }
1557
1558 new_line.clock_rate = info->params.clock_speed;
1559 new_line.loopback = info->params.loopback ? 1:0;
1560
1561 if (copy_to_user(line, &new_line, size))
1562 return -EFAULT;
1563 return 0;
1564
1565 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1566
1567 if(!capable(CAP_NET_ADMIN))
1568 return -EPERM;
1569 if (copy_from_user(&new_line, line, size))
1570 return -EFAULT;
1571
1572 switch (new_line.clock_type)
1573 {
1574 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1575 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1576 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1577 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1578 case CLOCK_DEFAULT: flags = info->params.flags &
1579 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1580 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1581 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1582 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1583 default: return -EINVAL;
1584 }
1585
1586 if (new_line.loopback != 0 && new_line.loopback != 1)
1587 return -EINVAL;
1588
1589 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1590 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1591 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1592 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1593 info->params.flags |= flags;
1594
1595 info->params.loopback = new_line.loopback;
1596
1597 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1598 info->params.clock_speed = new_line.clock_rate;
1599 else
1600 info->params.clock_speed = 0;
1601
1602 /* if network interface up, reprogram hardware */
1603 if (info->netcount)
1604 program_hw(info);
1605 return 0;
1606
1607 default:
1608 return hdlc_ioctl(dev, ifs);
1609 }
1610}
1611
1612/**
1613 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1614 * @dev: pointer to network device structure
1615 * @txqueue: unused
1616 */
1617static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1618{
1619 struct slgt_info *info = dev_to_port(dev);
1620 unsigned long flags;
1621
1622 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1623
1624 dev->stats.tx_errors++;
1625 dev->stats.tx_aborted_errors++;
1626
1627 spin_lock_irqsave(&info->lock,flags);
1628 tx_stop(info);
1629 spin_unlock_irqrestore(&info->lock,flags);
1630
1631 netif_wake_queue(dev);
1632}
1633
1634/**
1635 * hdlcdev_tx_done - called by device driver when transmit completes
1636 * @info: pointer to device instance information
1637 *
1638 * Reenable network layer transmit if stopped.
1639 */
1640static void hdlcdev_tx_done(struct slgt_info *info)
1641{
1642 if (netif_queue_stopped(info->netdev))
1643 netif_wake_queue(info->netdev);
1644}
1645
1646/**
1647 * hdlcdev_rx - called by device driver when frame received
1648 * @info: pointer to device instance information
1649 * @buf: pointer to buffer contianing frame data
1650 * @size: count of data bytes in buf
1651 *
1652 * Pass frame to network layer.
1653 */
1654static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1655{
1656 struct sk_buff *skb = dev_alloc_skb(size);
1657 struct net_device *dev = info->netdev;
1658
1659 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1660
1661 if (skb == NULL) {
1662 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1663 dev->stats.rx_dropped++;
1664 return;
1665 }
1666
1667 skb_put_data(skb, buf, size);
1668
1669 skb->protocol = hdlc_type_trans(skb, dev);
1670
1671 dev->stats.rx_packets++;
1672 dev->stats.rx_bytes += size;
1673
1674 netif_rx(skb);
1675}
1676
1677static const struct net_device_ops hdlcdev_ops = {
1678 .ndo_open = hdlcdev_open,
1679 .ndo_stop = hdlcdev_close,
1680 .ndo_start_xmit = hdlc_start_xmit,
1681 .ndo_siocwandev = hdlcdev_ioctl,
1682 .ndo_tx_timeout = hdlcdev_tx_timeout,
1683};
1684
1685/**
1686 * hdlcdev_init - called by device driver when adding device instance
1687 * @info: pointer to device instance information
1688 *
1689 * Do generic HDLC initialization.
1690 *
1691 * Return: 0 if success, otherwise error code
1692 */
1693static int hdlcdev_init(struct slgt_info *info)
1694{
1695 int rc;
1696 struct net_device *dev;
1697 hdlc_device *hdlc;
1698
1699 /* allocate and initialize network and HDLC layer objects */
1700
1701 dev = alloc_hdlcdev(info);
1702 if (!dev) {
1703 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1704 return -ENOMEM;
1705 }
1706
1707 /* for network layer reporting purposes only */
1708 dev->mem_start = info->phys_reg_addr;
1709 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1710 dev->irq = info->irq_level;
1711
1712 /* network layer callbacks and settings */
1713 dev->netdev_ops = &hdlcdev_ops;
1714 dev->watchdog_timeo = 10 * HZ;
1715 dev->tx_queue_len = 50;
1716
1717 /* generic HDLC layer callbacks and settings */
1718 hdlc = dev_to_hdlc(dev);
1719 hdlc->attach = hdlcdev_attach;
1720 hdlc->xmit = hdlcdev_xmit;
1721
1722 /* register objects with HDLC layer */
1723 rc = register_hdlc_device(dev);
1724 if (rc) {
1725 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1726 free_netdev(dev);
1727 return rc;
1728 }
1729
1730 info->netdev = dev;
1731 return 0;
1732}
1733
1734/**
1735 * hdlcdev_exit - called by device driver when removing device instance
1736 * @info: pointer to device instance information
1737 *
1738 * Do generic HDLC cleanup.
1739 */
1740static void hdlcdev_exit(struct slgt_info *info)
1741{
1742 if (!info->netdev)
1743 return;
1744 unregister_hdlc_device(info->netdev);
1745 free_netdev(info->netdev);
1746 info->netdev = NULL;
1747}
1748
1749#endif /* ifdef CONFIG_HDLC */
1750
1751/*
1752 * get async data from rx DMA buffers
1753 */
1754static void rx_async(struct slgt_info *info)
1755{
1756 struct mgsl_icount *icount = &info->icount;
1757 unsigned int start, end;
1758 unsigned char *p;
1759 unsigned char status;
1760 struct slgt_desc *bufs = info->rbufs;
1761 int i, count;
1762 int chars = 0;
1763 int stat;
1764 unsigned char ch;
1765
1766 start = end = info->rbuf_current;
1767
1768 while(desc_complete(bufs[end])) {
1769 count = desc_count(bufs[end]) - info->rbuf_index;
1770 p = bufs[end].buf + info->rbuf_index;
1771
1772 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1773 DBGDATA(info, p, count, "rx");
1774
1775 for(i=0 ; i < count; i+=2, p+=2) {
1776 ch = *p;
1777 icount->rx++;
1778
1779 stat = 0;
1780
1781 status = *(p + 1) & (BIT1 + BIT0);
1782 if (status) {
1783 if (status & BIT1)
1784 icount->parity++;
1785 else if (status & BIT0)
1786 icount->frame++;
1787 /* discard char if tty control flags say so */
1788 if (status & info->ignore_status_mask)
1789 continue;
1790 if (status & BIT1)
1791 stat = TTY_PARITY;
1792 else if (status & BIT0)
1793 stat = TTY_FRAME;
1794 }
1795 tty_insert_flip_char(&info->port, ch, stat);
1796 chars++;
1797 }
1798
1799 if (i < count) {
1800 /* receive buffer not completed */
1801 info->rbuf_index += i;
1802 mod_timer(&info->rx_timer, jiffies + 1);
1803 break;
1804 }
1805
1806 info->rbuf_index = 0;
1807 free_rbufs(info, end, end);
1808
1809 if (++end == info->rbuf_count)
1810 end = 0;
1811
1812 /* if entire list searched then no frame available */
1813 if (end == start)
1814 break;
1815 }
1816
1817 if (chars)
1818 tty_flip_buffer_push(&info->port);
1819}
1820
1821/*
1822 * return next bottom half action to perform
1823 */
1824static int bh_action(struct slgt_info *info)
1825{
1826 unsigned long flags;
1827 int rc;
1828
1829 spin_lock_irqsave(&info->lock,flags);
1830
1831 if (info->pending_bh & BH_RECEIVE) {
1832 info->pending_bh &= ~BH_RECEIVE;
1833 rc = BH_RECEIVE;
1834 } else if (info->pending_bh & BH_TRANSMIT) {
1835 info->pending_bh &= ~BH_TRANSMIT;
1836 rc = BH_TRANSMIT;
1837 } else if (info->pending_bh & BH_STATUS) {
1838 info->pending_bh &= ~BH_STATUS;
1839 rc = BH_STATUS;
1840 } else {
1841 /* Mark BH routine as complete */
1842 info->bh_running = false;
1843 info->bh_requested = false;
1844 rc = 0;
1845 }
1846
1847 spin_unlock_irqrestore(&info->lock,flags);
1848
1849 return rc;
1850}
1851
1852/*
1853 * perform bottom half processing
1854 */
1855static void bh_handler(struct work_struct *work)
1856{
1857 struct slgt_info *info = container_of(work, struct slgt_info, task);
1858 int action;
1859
1860 info->bh_running = true;
1861
1862 while((action = bh_action(info))) {
1863 switch (action) {
1864 case BH_RECEIVE:
1865 DBGBH(("%s bh receive\n", info->device_name));
1866 switch(info->params.mode) {
1867 case MGSL_MODE_ASYNC:
1868 rx_async(info);
1869 break;
1870 case MGSL_MODE_HDLC:
1871 while(rx_get_frame(info));
1872 break;
1873 case MGSL_MODE_RAW:
1874 case MGSL_MODE_MONOSYNC:
1875 case MGSL_MODE_BISYNC:
1876 case MGSL_MODE_XSYNC:
1877 while(rx_get_buf(info));
1878 break;
1879 }
1880 /* restart receiver if rx DMA buffers exhausted */
1881 if (info->rx_restart)
1882 rx_start(info);
1883 break;
1884 case BH_TRANSMIT:
1885 bh_transmit(info);
1886 break;
1887 case BH_STATUS:
1888 DBGBH(("%s bh status\n", info->device_name));
1889 info->ri_chkcount = 0;
1890 info->dsr_chkcount = 0;
1891 info->dcd_chkcount = 0;
1892 info->cts_chkcount = 0;
1893 break;
1894 default:
1895 DBGBH(("%s unknown action\n", info->device_name));
1896 break;
1897 }
1898 }
1899 DBGBH(("%s bh_handler exit\n", info->device_name));
1900}
1901
1902static void bh_transmit(struct slgt_info *info)
1903{
1904 struct tty_struct *tty = info->port.tty;
1905
1906 DBGBH(("%s bh_transmit\n", info->device_name));
1907 if (tty)
1908 tty_wakeup(tty);
1909}
1910
1911static void dsr_change(struct slgt_info *info, unsigned short status)
1912{
1913 if (status & BIT3) {
1914 info->signals |= SerialSignal_DSR;
1915 info->input_signal_events.dsr_up++;
1916 } else {
1917 info->signals &= ~SerialSignal_DSR;
1918 info->input_signal_events.dsr_down++;
1919 }
1920 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1921 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1922 slgt_irq_off(info, IRQ_DSR);
1923 return;
1924 }
1925 info->icount.dsr++;
1926 wake_up_interruptible(&info->status_event_wait_q);
1927 wake_up_interruptible(&info->event_wait_q);
1928 info->pending_bh |= BH_STATUS;
1929}
1930
1931static void cts_change(struct slgt_info *info, unsigned short status)
1932{
1933 if (status & BIT2) {
1934 info->signals |= SerialSignal_CTS;
1935 info->input_signal_events.cts_up++;
1936 } else {
1937 info->signals &= ~SerialSignal_CTS;
1938 info->input_signal_events.cts_down++;
1939 }
1940 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1941 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1942 slgt_irq_off(info, IRQ_CTS);
1943 return;
1944 }
1945 info->icount.cts++;
1946 wake_up_interruptible(&info->status_event_wait_q);
1947 wake_up_interruptible(&info->event_wait_q);
1948 info->pending_bh |= BH_STATUS;
1949
1950 if (tty_port_cts_enabled(&info->port)) {
1951 if (info->port.tty) {
1952 if (info->port.tty->hw_stopped) {
1953 if (info->signals & SerialSignal_CTS) {
1954 info->port.tty->hw_stopped = false;
1955 info->pending_bh |= BH_TRANSMIT;
1956 return;
1957 }
1958 } else {
1959 if (!(info->signals & SerialSignal_CTS))
1960 info->port.tty->hw_stopped = true;
1961 }
1962 }
1963 }
1964}
1965
1966static void dcd_change(struct slgt_info *info, unsigned short status)
1967{
1968 if (status & BIT1) {
1969 info->signals |= SerialSignal_DCD;
1970 info->input_signal_events.dcd_up++;
1971 } else {
1972 info->signals &= ~SerialSignal_DCD;
1973 info->input_signal_events.dcd_down++;
1974 }
1975 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1976 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1977 slgt_irq_off(info, IRQ_DCD);
1978 return;
1979 }
1980 info->icount.dcd++;
1981#if SYNCLINK_GENERIC_HDLC
1982 if (info->netcount) {
1983 if (info->signals & SerialSignal_DCD)
1984 netif_carrier_on(info->netdev);
1985 else
1986 netif_carrier_off(info->netdev);
1987 }
1988#endif
1989 wake_up_interruptible(&info->status_event_wait_q);
1990 wake_up_interruptible(&info->event_wait_q);
1991 info->pending_bh |= BH_STATUS;
1992
1993 if (tty_port_check_carrier(&info->port)) {
1994 if (info->signals & SerialSignal_DCD)
1995 wake_up_interruptible(&info->port.open_wait);
1996 else {
1997 if (info->port.tty)
1998 tty_hangup(info->port.tty);
1999 }
2000 }
2001}
2002
2003static void ri_change(struct slgt_info *info, unsigned short status)
2004{
2005 if (status & BIT0) {
2006 info->signals |= SerialSignal_RI;
2007 info->input_signal_events.ri_up++;
2008 } else {
2009 info->signals &= ~SerialSignal_RI;
2010 info->input_signal_events.ri_down++;
2011 }
2012 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2013 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2014 slgt_irq_off(info, IRQ_RI);
2015 return;
2016 }
2017 info->icount.rng++;
2018 wake_up_interruptible(&info->status_event_wait_q);
2019 wake_up_interruptible(&info->event_wait_q);
2020 info->pending_bh |= BH_STATUS;
2021}
2022
2023static void isr_rxdata(struct slgt_info *info)
2024{
2025 unsigned int count = info->rbuf_fill_count;
2026 unsigned int i = info->rbuf_fill_index;
2027 unsigned short reg;
2028
2029 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2030 reg = rd_reg16(info, RDR);
2031 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2032 if (desc_complete(info->rbufs[i])) {
2033 /* all buffers full */
2034 rx_stop(info);
2035 info->rx_restart = true;
2036 continue;
2037 }
2038 info->rbufs[i].buf[count++] = (unsigned char)reg;
2039 /* async mode saves status byte to buffer for each data byte */
2040 if (info->params.mode == MGSL_MODE_ASYNC)
2041 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2042 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2043 /* buffer full or end of frame */
2044 set_desc_count(info->rbufs[i], count);
2045 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2046 info->rbuf_fill_count = count = 0;
2047 if (++i == info->rbuf_count)
2048 i = 0;
2049 info->pending_bh |= BH_RECEIVE;
2050 }
2051 }
2052
2053 info->rbuf_fill_index = i;
2054 info->rbuf_fill_count = count;
2055}
2056
2057static void isr_serial(struct slgt_info *info)
2058{
2059 unsigned short status = rd_reg16(info, SSR);
2060
2061 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2062
2063 wr_reg16(info, SSR, status); /* clear pending */
2064
2065 info->irq_occurred = true;
2066
2067 if (info->params.mode == MGSL_MODE_ASYNC) {
2068 if (status & IRQ_TXIDLE) {
2069 if (info->tx_active)
2070 isr_txeom(info, status);
2071 }
2072 if (info->rx_pio && (status & IRQ_RXDATA))
2073 isr_rxdata(info);
2074 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2075 info->icount.brk++;
2076 /* process break detection if tty control allows */
2077 if (info->port.tty) {
2078 if (!(status & info->ignore_status_mask)) {
2079 if (info->read_status_mask & MASK_BREAK) {
2080 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2081 if (info->port.flags & ASYNC_SAK)
2082 do_SAK(info->port.tty);
2083 }
2084 }
2085 }
2086 }
2087 } else {
2088 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2089 isr_txeom(info, status);
2090 if (info->rx_pio && (status & IRQ_RXDATA))
2091 isr_rxdata(info);
2092 if (status & IRQ_RXIDLE) {
2093 if (status & RXIDLE)
2094 info->icount.rxidle++;
2095 else
2096 info->icount.exithunt++;
2097 wake_up_interruptible(&info->event_wait_q);
2098 }
2099
2100 if (status & IRQ_RXOVER)
2101 rx_start(info);
2102 }
2103
2104 if (status & IRQ_DSR)
2105 dsr_change(info, status);
2106 if (status & IRQ_CTS)
2107 cts_change(info, status);
2108 if (status & IRQ_DCD)
2109 dcd_change(info, status);
2110 if (status & IRQ_RI)
2111 ri_change(info, status);
2112}
2113
2114static void isr_rdma(struct slgt_info *info)
2115{
2116 unsigned int status = rd_reg32(info, RDCSR);
2117
2118 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2119
2120 /* RDCSR (rx DMA control/status)
2121 *
2122 * 31..07 reserved
2123 * 06 save status byte to DMA buffer
2124 * 05 error
2125 * 04 eol (end of list)
2126 * 03 eob (end of buffer)
2127 * 02 IRQ enable
2128 * 01 reset
2129 * 00 enable
2130 */
2131 wr_reg32(info, RDCSR, status); /* clear pending */
2132
2133 if (status & (BIT5 + BIT4)) {
2134 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2135 info->rx_restart = true;
2136 }
2137 info->pending_bh |= BH_RECEIVE;
2138}
2139
2140static void isr_tdma(struct slgt_info *info)
2141{
2142 unsigned int status = rd_reg32(info, TDCSR);
2143
2144 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2145
2146 /* TDCSR (tx DMA control/status)
2147 *
2148 * 31..06 reserved
2149 * 05 error
2150 * 04 eol (end of list)
2151 * 03 eob (end of buffer)
2152 * 02 IRQ enable
2153 * 01 reset
2154 * 00 enable
2155 */
2156 wr_reg32(info, TDCSR, status); /* clear pending */
2157
2158 if (status & (BIT5 + BIT4 + BIT3)) {
2159 // another transmit buffer has completed
2160 // run bottom half to get more send data from user
2161 info->pending_bh |= BH_TRANSMIT;
2162 }
2163}
2164
2165/*
2166 * return true if there are unsent tx DMA buffers, otherwise false
2167 *
2168 * if there are unsent buffers then info->tbuf_start
2169 * is set to index of first unsent buffer
2170 */
2171static bool unsent_tbufs(struct slgt_info *info)
2172{
2173 unsigned int i = info->tbuf_current;
2174 bool rc = false;
2175
2176 /*
2177 * search backwards from last loaded buffer (precedes tbuf_current)
2178 * for first unsent buffer (desc_count > 0)
2179 */
2180
2181 do {
2182 if (i)
2183 i--;
2184 else
2185 i = info->tbuf_count - 1;
2186 if (!desc_count(info->tbufs[i]))
2187 break;
2188 info->tbuf_start = i;
2189 rc = true;
2190 } while (i != info->tbuf_current);
2191
2192 return rc;
2193}
2194
2195static void isr_txeom(struct slgt_info *info, unsigned short status)
2196{
2197 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2198
2199 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2200 tdma_reset(info);
2201 if (status & IRQ_TXUNDER) {
2202 unsigned short val = rd_reg16(info, TCR);
2203 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2204 wr_reg16(info, TCR, val); /* clear reset bit */
2205 }
2206
2207 if (info->tx_active) {
2208 if (info->params.mode != MGSL_MODE_ASYNC) {
2209 if (status & IRQ_TXUNDER)
2210 info->icount.txunder++;
2211 else if (status & IRQ_TXIDLE)
2212 info->icount.txok++;
2213 }
2214
2215 if (unsent_tbufs(info)) {
2216 tx_start(info);
2217 update_tx_timer(info);
2218 return;
2219 }
2220 info->tx_active = false;
2221
2222 del_timer(&info->tx_timer);
2223
2224 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2225 info->signals &= ~SerialSignal_RTS;
2226 info->drop_rts_on_tx_done = false;
2227 set_gtsignals(info);
2228 }
2229
2230#if SYNCLINK_GENERIC_HDLC
2231 if (info->netcount)
2232 hdlcdev_tx_done(info);
2233 else
2234#endif
2235 {
2236 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2237 tx_stop(info);
2238 return;
2239 }
2240 info->pending_bh |= BH_TRANSMIT;
2241 }
2242 }
2243}
2244
2245static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2246{
2247 struct cond_wait *w, *prev;
2248
2249 /* wake processes waiting for specific transitions */
2250 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2251 if (w->data & changed) {
2252 w->data = state;
2253 wake_up_interruptible(&w->q);
2254 if (prev != NULL)
2255 prev->next = w->next;
2256 else
2257 info->gpio_wait_q = w->next;
2258 } else
2259 prev = w;
2260 }
2261}
2262
2263/* interrupt service routine
2264 *
2265 * irq interrupt number
2266 * dev_id device ID supplied during interrupt registration
2267 */
2268static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2269{
2270 struct slgt_info *info = dev_id;
2271 unsigned int gsr;
2272 unsigned int i;
2273
2274 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2275
2276 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2277 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2278 info->irq_occurred = true;
2279 for(i=0; i < info->port_count ; i++) {
2280 if (info->port_array[i] == NULL)
2281 continue;
2282 spin_lock(&info->port_array[i]->lock);
2283 if (gsr & (BIT8 << i))
2284 isr_serial(info->port_array[i]);
2285 if (gsr & (BIT16 << (i*2)))
2286 isr_rdma(info->port_array[i]);
2287 if (gsr & (BIT17 << (i*2)))
2288 isr_tdma(info->port_array[i]);
2289 spin_unlock(&info->port_array[i]->lock);
2290 }
2291 }
2292
2293 if (info->gpio_present) {
2294 unsigned int state;
2295 unsigned int changed;
2296 spin_lock(&info->lock);
2297 while ((changed = rd_reg32(info, IOSR)) != 0) {
2298 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2299 /* read latched state of GPIO signals */
2300 state = rd_reg32(info, IOVR);
2301 /* clear pending GPIO interrupt bits */
2302 wr_reg32(info, IOSR, changed);
2303 for (i=0 ; i < info->port_count ; i++) {
2304 if (info->port_array[i] != NULL)
2305 isr_gpio(info->port_array[i], changed, state);
2306 }
2307 }
2308 spin_unlock(&info->lock);
2309 }
2310
2311 for(i=0; i < info->port_count ; i++) {
2312 struct slgt_info *port = info->port_array[i];
2313 if (port == NULL)
2314 continue;
2315 spin_lock(&port->lock);
2316 if ((port->port.count || port->netcount) &&
2317 port->pending_bh && !port->bh_running &&
2318 !port->bh_requested) {
2319 DBGISR(("%s bh queued\n", port->device_name));
2320 schedule_work(&port->task);
2321 port->bh_requested = true;
2322 }
2323 spin_unlock(&port->lock);
2324 }
2325
2326 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2327 return IRQ_HANDLED;
2328}
2329
2330static int startup(struct slgt_info *info)
2331{
2332 DBGINFO(("%s startup\n", info->device_name));
2333
2334 if (tty_port_initialized(&info->port))
2335 return 0;
2336
2337 if (!info->tx_buf) {
2338 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2339 if (!info->tx_buf) {
2340 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2341 return -ENOMEM;
2342 }
2343 }
2344
2345 info->pending_bh = 0;
2346
2347 memset(&info->icount, 0, sizeof(info->icount));
2348
2349 /* program hardware for current parameters */
2350 change_params(info);
2351
2352 if (info->port.tty)
2353 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2354
2355 tty_port_set_initialized(&info->port, true);
2356
2357 return 0;
2358}
2359
2360/*
2361 * called by close() and hangup() to shutdown hardware
2362 */
2363static void shutdown(struct slgt_info *info)
2364{
2365 unsigned long flags;
2366
2367 if (!tty_port_initialized(&info->port))
2368 return;
2369
2370 DBGINFO(("%s shutdown\n", info->device_name));
2371
2372 /* clear status wait queue because status changes */
2373 /* can't happen after shutting down the hardware */
2374 wake_up_interruptible(&info->status_event_wait_q);
2375 wake_up_interruptible(&info->event_wait_q);
2376
2377 del_timer_sync(&info->tx_timer);
2378 del_timer_sync(&info->rx_timer);
2379
2380 kfree(info->tx_buf);
2381 info->tx_buf = NULL;
2382
2383 spin_lock_irqsave(&info->lock,flags);
2384
2385 tx_stop(info);
2386 rx_stop(info);
2387
2388 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2389
2390 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2391 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2392 set_gtsignals(info);
2393 }
2394
2395 flush_cond_wait(&info->gpio_wait_q);
2396
2397 spin_unlock_irqrestore(&info->lock,flags);
2398
2399 if (info->port.tty)
2400 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2401
2402 tty_port_set_initialized(&info->port, false);
2403}
2404
2405static void program_hw(struct slgt_info *info)
2406{
2407 unsigned long flags;
2408
2409 spin_lock_irqsave(&info->lock,flags);
2410
2411 rx_stop(info);
2412 tx_stop(info);
2413
2414 if (info->params.mode != MGSL_MODE_ASYNC ||
2415 info->netcount)
2416 sync_mode(info);
2417 else
2418 async_mode(info);
2419
2420 set_gtsignals(info);
2421
2422 info->dcd_chkcount = 0;
2423 info->cts_chkcount = 0;
2424 info->ri_chkcount = 0;
2425 info->dsr_chkcount = 0;
2426
2427 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2428 get_gtsignals(info);
2429
2430 if (info->netcount ||
2431 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2432 rx_start(info);
2433
2434 spin_unlock_irqrestore(&info->lock,flags);
2435}
2436
2437/*
2438 * reconfigure adapter based on new parameters
2439 */
2440static void change_params(struct slgt_info *info)
2441{
2442 unsigned cflag;
2443 int bits_per_char;
2444
2445 if (!info->port.tty)
2446 return;
2447 DBGINFO(("%s change_params\n", info->device_name));
2448
2449 cflag = info->port.tty->termios.c_cflag;
2450
2451 /* if B0 rate (hangup) specified then negate RTS and DTR */
2452 /* otherwise assert RTS and DTR */
2453 if (cflag & CBAUD)
2454 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2455 else
2456 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2457
2458 /* byte size and parity */
2459
2460 info->params.data_bits = tty_get_char_size(cflag);
2461 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2462
2463 if (cflag & PARENB)
2464 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2465 else
2466 info->params.parity = ASYNC_PARITY_NONE;
2467
2468 /* calculate number of jiffies to transmit a full
2469 * FIFO (32 bytes) at specified data rate
2470 */
2471 bits_per_char = info->params.data_bits +
2472 info->params.stop_bits + 1;
2473
2474 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2475
2476 if (info->params.data_rate) {
2477 info->timeout = (32*HZ*bits_per_char) /
2478 info->params.data_rate;
2479 }
2480 info->timeout += HZ/50; /* Add .02 seconds of slop */
2481
2482 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2483 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2484
2485 /* process tty input control flags */
2486
2487 info->read_status_mask = IRQ_RXOVER;
2488 if (I_INPCK(info->port.tty))
2489 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2490 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2491 info->read_status_mask |= MASK_BREAK;
2492 if (I_IGNPAR(info->port.tty))
2493 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2494 if (I_IGNBRK(info->port.tty)) {
2495 info->ignore_status_mask |= MASK_BREAK;
2496 /* If ignoring parity and break indicators, ignore
2497 * overruns too. (For real raw support).
2498 */
2499 if (I_IGNPAR(info->port.tty))
2500 info->ignore_status_mask |= MASK_OVERRUN;
2501 }
2502
2503 program_hw(info);
2504}
2505
2506static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2507{
2508 DBGINFO(("%s get_stats\n", info->device_name));
2509 if (!user_icount) {
2510 memset(&info->icount, 0, sizeof(info->icount));
2511 } else {
2512 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2513 return -EFAULT;
2514 }
2515 return 0;
2516}
2517
2518static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2519{
2520 DBGINFO(("%s get_params\n", info->device_name));
2521 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2522 return -EFAULT;
2523 return 0;
2524}
2525
2526static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2527{
2528 unsigned long flags;
2529 MGSL_PARAMS tmp_params;
2530
2531 DBGINFO(("%s set_params\n", info->device_name));
2532 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2533 return -EFAULT;
2534
2535 spin_lock_irqsave(&info->lock, flags);
2536 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2537 info->base_clock = tmp_params.clock_speed;
2538 else
2539 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2540 spin_unlock_irqrestore(&info->lock, flags);
2541
2542 program_hw(info);
2543
2544 return 0;
2545}
2546
2547static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2548{
2549 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2550 if (put_user(info->idle_mode, idle_mode))
2551 return -EFAULT;
2552 return 0;
2553}
2554
2555static int set_txidle(struct slgt_info *info, int idle_mode)
2556{
2557 unsigned long flags;
2558 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2559 spin_lock_irqsave(&info->lock,flags);
2560 info->idle_mode = idle_mode;
2561 if (info->params.mode != MGSL_MODE_ASYNC)
2562 tx_set_idle(info);
2563 spin_unlock_irqrestore(&info->lock,flags);
2564 return 0;
2565}
2566
2567static int tx_enable(struct slgt_info *info, int enable)
2568{
2569 unsigned long flags;
2570 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2571 spin_lock_irqsave(&info->lock,flags);
2572 if (enable) {
2573 if (!info->tx_enabled)
2574 tx_start(info);
2575 } else {
2576 if (info->tx_enabled)
2577 tx_stop(info);
2578 }
2579 spin_unlock_irqrestore(&info->lock,flags);
2580 return 0;
2581}
2582
2583/*
2584 * abort transmit HDLC frame
2585 */
2586static int tx_abort(struct slgt_info *info)
2587{
2588 unsigned long flags;
2589 DBGINFO(("%s tx_abort\n", info->device_name));
2590 spin_lock_irqsave(&info->lock,flags);
2591 tdma_reset(info);
2592 spin_unlock_irqrestore(&info->lock,flags);
2593 return 0;
2594}
2595
2596static int rx_enable(struct slgt_info *info, int enable)
2597{
2598 unsigned long flags;
2599 unsigned int rbuf_fill_level;
2600 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2601 spin_lock_irqsave(&info->lock,flags);
2602 /*
2603 * enable[31..16] = receive DMA buffer fill level
2604 * 0 = noop (leave fill level unchanged)
2605 * fill level must be multiple of 4 and <= buffer size
2606 */
2607 rbuf_fill_level = ((unsigned int)enable) >> 16;
2608 if (rbuf_fill_level) {
2609 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2610 spin_unlock_irqrestore(&info->lock, flags);
2611 return -EINVAL;
2612 }
2613 info->rbuf_fill_level = rbuf_fill_level;
2614 if (rbuf_fill_level < 128)
2615 info->rx_pio = 1; /* PIO mode */
2616 else
2617 info->rx_pio = 0; /* DMA mode */
2618 rx_stop(info); /* restart receiver to use new fill level */
2619 }
2620
2621 /*
2622 * enable[1..0] = receiver enable command
2623 * 0 = disable
2624 * 1 = enable
2625 * 2 = enable or force hunt mode if already enabled
2626 */
2627 enable &= 3;
2628 if (enable) {
2629 if (!info->rx_enabled)
2630 rx_start(info);
2631 else if (enable == 2) {
2632 /* force hunt mode (write 1 to RCR[3]) */
2633 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2634 }
2635 } else {
2636 if (info->rx_enabled)
2637 rx_stop(info);
2638 }
2639 spin_unlock_irqrestore(&info->lock,flags);
2640 return 0;
2641}
2642
2643/*
2644 * wait for specified event to occur
2645 */
2646static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2647{
2648 unsigned long flags;
2649 int s;
2650 int rc=0;
2651 struct mgsl_icount cprev, cnow;
2652 int events;
2653 int mask;
2654 struct _input_signal_events oldsigs, newsigs;
2655 DECLARE_WAITQUEUE(wait, current);
2656
2657 if (get_user(mask, mask_ptr))
2658 return -EFAULT;
2659
2660 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2661
2662 spin_lock_irqsave(&info->lock,flags);
2663
2664 /* return immediately if state matches requested events */
2665 get_gtsignals(info);
2666 s = info->signals;
2667
2668 events = mask &
2669 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2670 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2671 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2672 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2673 if (events) {
2674 spin_unlock_irqrestore(&info->lock,flags);
2675 goto exit;
2676 }
2677
2678 /* save current irq counts */
2679 cprev = info->icount;
2680 oldsigs = info->input_signal_events;
2681
2682 /* enable hunt and idle irqs if needed */
2683 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2684 unsigned short val = rd_reg16(info, SCR);
2685 if (!(val & IRQ_RXIDLE))
2686 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2687 }
2688
2689 set_current_state(TASK_INTERRUPTIBLE);
2690 add_wait_queue(&info->event_wait_q, &wait);
2691
2692 spin_unlock_irqrestore(&info->lock,flags);
2693
2694 for(;;) {
2695 schedule();
2696 if (signal_pending(current)) {
2697 rc = -ERESTARTSYS;
2698 break;
2699 }
2700
2701 /* get current irq counts */
2702 spin_lock_irqsave(&info->lock,flags);
2703 cnow = info->icount;
2704 newsigs = info->input_signal_events;
2705 set_current_state(TASK_INTERRUPTIBLE);
2706 spin_unlock_irqrestore(&info->lock,flags);
2707
2708 /* if no change, wait aborted for some reason */
2709 if (newsigs.dsr_up == oldsigs.dsr_up &&
2710 newsigs.dsr_down == oldsigs.dsr_down &&
2711 newsigs.dcd_up == oldsigs.dcd_up &&
2712 newsigs.dcd_down == oldsigs.dcd_down &&
2713 newsigs.cts_up == oldsigs.cts_up &&
2714 newsigs.cts_down == oldsigs.cts_down &&
2715 newsigs.ri_up == oldsigs.ri_up &&
2716 newsigs.ri_down == oldsigs.ri_down &&
2717 cnow.exithunt == cprev.exithunt &&
2718 cnow.rxidle == cprev.rxidle) {
2719 rc = -EIO;
2720 break;
2721 }
2722
2723 events = mask &
2724 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2725 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2726 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2727 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2728 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2729 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2730 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2731 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2732 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2733 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2734 if (events)
2735 break;
2736
2737 cprev = cnow;
2738 oldsigs = newsigs;
2739 }
2740
2741 remove_wait_queue(&info->event_wait_q, &wait);
2742 set_current_state(TASK_RUNNING);
2743
2744
2745 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2746 spin_lock_irqsave(&info->lock,flags);
2747 if (!waitqueue_active(&info->event_wait_q)) {
2748 /* disable enable exit hunt mode/idle rcvd IRQs */
2749 wr_reg16(info, SCR,
2750 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2751 }
2752 spin_unlock_irqrestore(&info->lock,flags);
2753 }
2754exit:
2755 if (rc == 0)
2756 rc = put_user(events, mask_ptr);
2757 return rc;
2758}
2759
2760static int get_interface(struct slgt_info *info, int __user *if_mode)
2761{
2762 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2763 if (put_user(info->if_mode, if_mode))
2764 return -EFAULT;
2765 return 0;
2766}
2767
2768static int set_interface(struct slgt_info *info, int if_mode)
2769{
2770 unsigned long flags;
2771 unsigned short val;
2772
2773 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2774 spin_lock_irqsave(&info->lock,flags);
2775 info->if_mode = if_mode;
2776
2777 msc_set_vcr(info);
2778
2779 /* TCR (tx control) 07 1=RTS driver control */
2780 val = rd_reg16(info, TCR);
2781 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2782 val |= BIT7;
2783 else
2784 val &= ~BIT7;
2785 wr_reg16(info, TCR, val);
2786
2787 spin_unlock_irqrestore(&info->lock,flags);
2788 return 0;
2789}
2790
2791static int get_xsync(struct slgt_info *info, int __user *xsync)
2792{
2793 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2794 if (put_user(info->xsync, xsync))
2795 return -EFAULT;
2796 return 0;
2797}
2798
2799/*
2800 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2801 *
2802 * sync pattern is contained in least significant bytes of value
2803 * most significant byte of sync pattern is oldest (1st sent/detected)
2804 */
2805static int set_xsync(struct slgt_info *info, int xsync)
2806{
2807 unsigned long flags;
2808
2809 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2810 spin_lock_irqsave(&info->lock, flags);
2811 info->xsync = xsync;
2812 wr_reg32(info, XSR, xsync);
2813 spin_unlock_irqrestore(&info->lock, flags);
2814 return 0;
2815}
2816
2817static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2818{
2819 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2820 if (put_user(info->xctrl, xctrl))
2821 return -EFAULT;
2822 return 0;
2823}
2824
2825/*
2826 * set extended control options
2827 *
2828 * xctrl[31:19] reserved, must be zero
2829 * xctrl[18:17] extended sync pattern length in bytes
2830 * 00 = 1 byte in xsr[7:0]
2831 * 01 = 2 bytes in xsr[15:0]
2832 * 10 = 3 bytes in xsr[23:0]
2833 * 11 = 4 bytes in xsr[31:0]
2834 * xctrl[16] 1 = enable terminal count, 0=disabled
2835 * xctrl[15:0] receive terminal count for fixed length packets
2836 * value is count minus one (0 = 1 byte packet)
2837 * when terminal count is reached, receiver
2838 * automatically returns to hunt mode and receive
2839 * FIFO contents are flushed to DMA buffers with
2840 * end of frame (EOF) status
2841 */
2842static int set_xctrl(struct slgt_info *info, int xctrl)
2843{
2844 unsigned long flags;
2845
2846 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2847 spin_lock_irqsave(&info->lock, flags);
2848 info->xctrl = xctrl;
2849 wr_reg32(info, XCR, xctrl);
2850 spin_unlock_irqrestore(&info->lock, flags);
2851 return 0;
2852}
2853
2854/*
2855 * set general purpose IO pin state and direction
2856 *
2857 * user_gpio fields:
2858 * state each bit indicates a pin state
2859 * smask set bit indicates pin state to set
2860 * dir each bit indicates a pin direction (0=input, 1=output)
2861 * dmask set bit indicates pin direction to set
2862 */
2863static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2864{
2865 unsigned long flags;
2866 struct gpio_desc gpio;
2867 __u32 data;
2868
2869 if (!info->gpio_present)
2870 return -EINVAL;
2871 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2872 return -EFAULT;
2873 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2874 info->device_name, gpio.state, gpio.smask,
2875 gpio.dir, gpio.dmask));
2876
2877 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2878 if (gpio.dmask) {
2879 data = rd_reg32(info, IODR);
2880 data |= gpio.dmask & gpio.dir;
2881 data &= ~(gpio.dmask & ~gpio.dir);
2882 wr_reg32(info, IODR, data);
2883 }
2884 if (gpio.smask) {
2885 data = rd_reg32(info, IOVR);
2886 data |= gpio.smask & gpio.state;
2887 data &= ~(gpio.smask & ~gpio.state);
2888 wr_reg32(info, IOVR, data);
2889 }
2890 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2891
2892 return 0;
2893}
2894
2895/*
2896 * get general purpose IO pin state and direction
2897 */
2898static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2899{
2900 struct gpio_desc gpio;
2901 if (!info->gpio_present)
2902 return -EINVAL;
2903 gpio.state = rd_reg32(info, IOVR);
2904 gpio.smask = 0xffffffff;
2905 gpio.dir = rd_reg32(info, IODR);
2906 gpio.dmask = 0xffffffff;
2907 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2908 return -EFAULT;
2909 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2910 info->device_name, gpio.state, gpio.dir));
2911 return 0;
2912}
2913
2914/*
2915 * conditional wait facility
2916 */
2917static void init_cond_wait(struct cond_wait *w, unsigned int data)
2918{
2919 init_waitqueue_head(&w->q);
2920 init_waitqueue_entry(&w->wait, current);
2921 w->data = data;
2922}
2923
2924static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2925{
2926 set_current_state(TASK_INTERRUPTIBLE);
2927 add_wait_queue(&w->q, &w->wait);
2928 w->next = *head;
2929 *head = w;
2930}
2931
2932static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2933{
2934 struct cond_wait *w, *prev;
2935 remove_wait_queue(&cw->q, &cw->wait);
2936 set_current_state(TASK_RUNNING);
2937 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2938 if (w == cw) {
2939 if (prev != NULL)
2940 prev->next = w->next;
2941 else
2942 *head = w->next;
2943 break;
2944 }
2945 }
2946}
2947
2948static void flush_cond_wait(struct cond_wait **head)
2949{
2950 while (*head != NULL) {
2951 wake_up_interruptible(&(*head)->q);
2952 *head = (*head)->next;
2953 }
2954}
2955
2956/*
2957 * wait for general purpose I/O pin(s) to enter specified state
2958 *
2959 * user_gpio fields:
2960 * state - bit indicates target pin state
2961 * smask - set bit indicates watched pin
2962 *
2963 * The wait ends when at least one watched pin enters the specified
2964 * state. When 0 (no error) is returned, user_gpio->state is set to the
2965 * state of all GPIO pins when the wait ends.
2966 *
2967 * Note: Each pin may be a dedicated input, dedicated output, or
2968 * configurable input/output. The number and configuration of pins
2969 * varies with the specific adapter model. Only input pins (dedicated
2970 * or configured) can be monitored with this function.
2971 */
2972static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2973{
2974 unsigned long flags;
2975 int rc = 0;
2976 struct gpio_desc gpio;
2977 struct cond_wait wait;
2978 u32 state;
2979
2980 if (!info->gpio_present)
2981 return -EINVAL;
2982 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2983 return -EFAULT;
2984 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2985 info->device_name, gpio.state, gpio.smask));
2986 /* ignore output pins identified by set IODR bit */
2987 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2988 return -EINVAL;
2989 init_cond_wait(&wait, gpio.smask);
2990
2991 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2992 /* enable interrupts for watched pins */
2993 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2994 /* get current pin states */
2995 state = rd_reg32(info, IOVR);
2996
2997 if (gpio.smask & ~(state ^ gpio.state)) {
2998 /* already in target state */
2999 gpio.state = state;
3000 } else {
3001 /* wait for target state */
3002 add_cond_wait(&info->gpio_wait_q, &wait);
3003 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3004 schedule();
3005 if (signal_pending(current))
3006 rc = -ERESTARTSYS;
3007 else
3008 gpio.state = wait.data;
3009 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3010 remove_cond_wait(&info->gpio_wait_q, &wait);
3011 }
3012
3013 /* disable all GPIO interrupts if no waiting processes */
3014 if (info->gpio_wait_q == NULL)
3015 wr_reg32(info, IOER, 0);
3016 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3017
3018 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3019 rc = -EFAULT;
3020 return rc;
3021}
3022
3023static int modem_input_wait(struct slgt_info *info,int arg)
3024{
3025 unsigned long flags;
3026 int rc;
3027 struct mgsl_icount cprev, cnow;
3028 DECLARE_WAITQUEUE(wait, current);
3029
3030 /* save current irq counts */
3031 spin_lock_irqsave(&info->lock,flags);
3032 cprev = info->icount;
3033 add_wait_queue(&info->status_event_wait_q, &wait);
3034 set_current_state(TASK_INTERRUPTIBLE);
3035 spin_unlock_irqrestore(&info->lock,flags);
3036
3037 for(;;) {
3038 schedule();
3039 if (signal_pending(current)) {
3040 rc = -ERESTARTSYS;
3041 break;
3042 }
3043
3044 /* get new irq counts */
3045 spin_lock_irqsave(&info->lock,flags);
3046 cnow = info->icount;
3047 set_current_state(TASK_INTERRUPTIBLE);
3048 spin_unlock_irqrestore(&info->lock,flags);
3049
3050 /* if no change, wait aborted for some reason */
3051 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3052 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3053 rc = -EIO;
3054 break;
3055 }
3056
3057 /* check for change in caller specified modem input */
3058 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3059 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3060 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3061 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3062 rc = 0;
3063 break;
3064 }
3065
3066 cprev = cnow;
3067 }
3068 remove_wait_queue(&info->status_event_wait_q, &wait);
3069 set_current_state(TASK_RUNNING);
3070 return rc;
3071}
3072
3073/*
3074 * return state of serial control and status signals
3075 */
3076static int tiocmget(struct tty_struct *tty)
3077{
3078 struct slgt_info *info = tty->driver_data;
3079 unsigned int result;
3080 unsigned long flags;
3081
3082 spin_lock_irqsave(&info->lock,flags);
3083 get_gtsignals(info);
3084 spin_unlock_irqrestore(&info->lock,flags);
3085
3086 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3087 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3088 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3089 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3090 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3091 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3092
3093 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3094 return result;
3095}
3096
3097/*
3098 * set modem control signals (DTR/RTS)
3099 *
3100 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3101 * TIOCMSET = set/clear signal values
3102 * value bit mask for command
3103 */
3104static int tiocmset(struct tty_struct *tty,
3105 unsigned int set, unsigned int clear)
3106{
3107 struct slgt_info *info = tty->driver_data;
3108 unsigned long flags;
3109
3110 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3111
3112 if (set & TIOCM_RTS)
3113 info->signals |= SerialSignal_RTS;
3114 if (set & TIOCM_DTR)
3115 info->signals |= SerialSignal_DTR;
3116 if (clear & TIOCM_RTS)
3117 info->signals &= ~SerialSignal_RTS;
3118 if (clear & TIOCM_DTR)
3119 info->signals &= ~SerialSignal_DTR;
3120
3121 spin_lock_irqsave(&info->lock,flags);
3122 set_gtsignals(info);
3123 spin_unlock_irqrestore(&info->lock,flags);
3124 return 0;
3125}
3126
3127static bool carrier_raised(struct tty_port *port)
3128{
3129 unsigned long flags;
3130 struct slgt_info *info = container_of(port, struct slgt_info, port);
3131
3132 spin_lock_irqsave(&info->lock,flags);
3133 get_gtsignals(info);
3134 spin_unlock_irqrestore(&info->lock,flags);
3135
3136 return info->signals & SerialSignal_DCD;
3137}
3138
3139static void dtr_rts(struct tty_port *port, bool active)
3140{
3141 unsigned long flags;
3142 struct slgt_info *info = container_of(port, struct slgt_info, port);
3143
3144 spin_lock_irqsave(&info->lock,flags);
3145 if (active)
3146 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3147 else
3148 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3149 set_gtsignals(info);
3150 spin_unlock_irqrestore(&info->lock,flags);
3151}
3152
3153
3154/*
3155 * block current process until the device is ready to open
3156 */
3157static int block_til_ready(struct tty_struct *tty, struct file *filp,
3158 struct slgt_info *info)
3159{
3160 DECLARE_WAITQUEUE(wait, current);
3161 int retval;
3162 bool do_clocal = false;
3163 unsigned long flags;
3164 bool cd;
3165 struct tty_port *port = &info->port;
3166
3167 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3168
3169 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3170 /* nonblock mode is set or port is not enabled */
3171 tty_port_set_active(port, true);
3172 return 0;
3173 }
3174
3175 if (C_CLOCAL(tty))
3176 do_clocal = true;
3177
3178 /* Wait for carrier detect and the line to become
3179 * free (i.e., not in use by the callout). While we are in
3180 * this loop, port->count is dropped by one, so that
3181 * close() knows when to free things. We restore it upon
3182 * exit, either normal or abnormal.
3183 */
3184
3185 retval = 0;
3186 add_wait_queue(&port->open_wait, &wait);
3187
3188 spin_lock_irqsave(&info->lock, flags);
3189 port->count--;
3190 spin_unlock_irqrestore(&info->lock, flags);
3191 port->blocked_open++;
3192
3193 while (1) {
3194 if (C_BAUD(tty) && tty_port_initialized(port))
3195 tty_port_raise_dtr_rts(port);
3196
3197 set_current_state(TASK_INTERRUPTIBLE);
3198
3199 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3200 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3201 -EAGAIN : -ERESTARTSYS;
3202 break;
3203 }
3204
3205 cd = tty_port_carrier_raised(port);
3206 if (do_clocal || cd)
3207 break;
3208
3209 if (signal_pending(current)) {
3210 retval = -ERESTARTSYS;
3211 break;
3212 }
3213
3214 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3215 tty_unlock(tty);
3216 schedule();
3217 tty_lock(tty);
3218 }
3219
3220 set_current_state(TASK_RUNNING);
3221 remove_wait_queue(&port->open_wait, &wait);
3222
3223 if (!tty_hung_up_p(filp))
3224 port->count++;
3225 port->blocked_open--;
3226
3227 if (!retval)
3228 tty_port_set_active(port, true);
3229
3230 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3231 return retval;
3232}
3233
3234/*
3235 * allocate buffers used for calling line discipline receive_buf
3236 * directly in synchronous mode
3237 * note: add 5 bytes to max frame size to allow appending
3238 * 32-bit CRC and status byte when configured to do so
3239 */
3240static int alloc_tmp_rbuf(struct slgt_info *info)
3241{
3242 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3243 if (info->tmp_rbuf == NULL)
3244 return -ENOMEM;
3245
3246 return 0;
3247}
3248
3249static void free_tmp_rbuf(struct slgt_info *info)
3250{
3251 kfree(info->tmp_rbuf);
3252 info->tmp_rbuf = NULL;
3253}
3254
3255/*
3256 * allocate DMA descriptor lists.
3257 */
3258static int alloc_desc(struct slgt_info *info)
3259{
3260 unsigned int i;
3261 unsigned int pbufs;
3262
3263 /* allocate memory to hold descriptor lists */
3264 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3265 &info->bufs_dma_addr, GFP_KERNEL);
3266 if (info->bufs == NULL)
3267 return -ENOMEM;
3268
3269 info->rbufs = (struct slgt_desc*)info->bufs;
3270 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3271
3272 pbufs = (unsigned int)info->bufs_dma_addr;
3273
3274 /*
3275 * Build circular lists of descriptors
3276 */
3277
3278 for (i=0; i < info->rbuf_count; i++) {
3279 /* physical address of this descriptor */
3280 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3281
3282 /* physical address of next descriptor */
3283 if (i == info->rbuf_count - 1)
3284 info->rbufs[i].next = cpu_to_le32(pbufs);
3285 else
3286 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3287 set_desc_count(info->rbufs[i], DMABUFSIZE);
3288 }
3289
3290 for (i=0; i < info->tbuf_count; i++) {
3291 /* physical address of this descriptor */
3292 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3293
3294 /* physical address of next descriptor */
3295 if (i == info->tbuf_count - 1)
3296 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3297 else
3298 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3299 }
3300
3301 return 0;
3302}
3303
3304static void free_desc(struct slgt_info *info)
3305{
3306 if (info->bufs != NULL) {
3307 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3308 info->bufs, info->bufs_dma_addr);
3309 info->bufs = NULL;
3310 info->rbufs = NULL;
3311 info->tbufs = NULL;
3312 }
3313}
3314
3315static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3316{
3317 int i;
3318 for (i=0; i < count; i++) {
3319 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3320 &bufs[i].buf_dma_addr, GFP_KERNEL);
3321 if (!bufs[i].buf)
3322 return -ENOMEM;
3323 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3324 }
3325 return 0;
3326}
3327
3328static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3329{
3330 int i;
3331 for (i=0; i < count; i++) {
3332 if (bufs[i].buf == NULL)
3333 continue;
3334 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3335 bufs[i].buf_dma_addr);
3336 bufs[i].buf = NULL;
3337 }
3338}
3339
3340static int alloc_dma_bufs(struct slgt_info *info)
3341{
3342 info->rbuf_count = 32;
3343 info->tbuf_count = 32;
3344
3345 if (alloc_desc(info) < 0 ||
3346 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3347 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3348 alloc_tmp_rbuf(info) < 0) {
3349 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3350 return -ENOMEM;
3351 }
3352 reset_rbufs(info);
3353 return 0;
3354}
3355
3356static void free_dma_bufs(struct slgt_info *info)
3357{
3358 if (info->bufs) {
3359 free_bufs(info, info->rbufs, info->rbuf_count);
3360 free_bufs(info, info->tbufs, info->tbuf_count);
3361 free_desc(info);
3362 }
3363 free_tmp_rbuf(info);
3364}
3365
3366static int claim_resources(struct slgt_info *info)
3367{
3368 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3369 DBGERR(("%s reg addr conflict, addr=%08X\n",
3370 info->device_name, info->phys_reg_addr));
3371 info->init_error = DiagStatus_AddressConflict;
3372 goto errout;
3373 }
3374 else
3375 info->reg_addr_requested = true;
3376
3377 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3378 if (!info->reg_addr) {
3379 DBGERR(("%s can't map device registers, addr=%08X\n",
3380 info->device_name, info->phys_reg_addr));
3381 info->init_error = DiagStatus_CantAssignPciResources;
3382 goto errout;
3383 }
3384 return 0;
3385
3386errout:
3387 release_resources(info);
3388 return -ENODEV;
3389}
3390
3391static void release_resources(struct slgt_info *info)
3392{
3393 if (info->irq_requested) {
3394 free_irq(info->irq_level, info);
3395 info->irq_requested = false;
3396 }
3397
3398 if (info->reg_addr_requested) {
3399 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3400 info->reg_addr_requested = false;
3401 }
3402
3403 if (info->reg_addr) {
3404 iounmap(info->reg_addr);
3405 info->reg_addr = NULL;
3406 }
3407}
3408
3409/* Add the specified device instance data structure to the
3410 * global linked list of devices and increment the device count.
3411 */
3412static void add_device(struct slgt_info *info)
3413{
3414 char *devstr;
3415
3416 info->next_device = NULL;
3417 info->line = slgt_device_count;
3418 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3419
3420 if (info->line < MAX_DEVICES) {
3421 if (maxframe[info->line])
3422 info->max_frame_size = maxframe[info->line];
3423 }
3424
3425 slgt_device_count++;
3426
3427 if (!slgt_device_list)
3428 slgt_device_list = info;
3429 else {
3430 struct slgt_info *current_dev = slgt_device_list;
3431 while(current_dev->next_device)
3432 current_dev = current_dev->next_device;
3433 current_dev->next_device = info;
3434 }
3435
3436 if (info->max_frame_size < 4096)
3437 info->max_frame_size = 4096;
3438 else if (info->max_frame_size > 65535)
3439 info->max_frame_size = 65535;
3440
3441 switch(info->pdev->device) {
3442 case SYNCLINK_GT_DEVICE_ID:
3443 devstr = "GT";
3444 break;
3445 case SYNCLINK_GT2_DEVICE_ID:
3446 devstr = "GT2";
3447 break;
3448 case SYNCLINK_GT4_DEVICE_ID:
3449 devstr = "GT4";
3450 break;
3451 case SYNCLINK_AC_DEVICE_ID:
3452 devstr = "AC";
3453 info->params.mode = MGSL_MODE_ASYNC;
3454 break;
3455 default:
3456 devstr = "(unknown model)";
3457 }
3458 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3459 devstr, info->device_name, info->phys_reg_addr,
3460 info->irq_level, info->max_frame_size);
3461
3462#if SYNCLINK_GENERIC_HDLC
3463 hdlcdev_init(info);
3464#endif
3465}
3466
3467static const struct tty_port_operations slgt_port_ops = {
3468 .carrier_raised = carrier_raised,
3469 .dtr_rts = dtr_rts,
3470};
3471
3472/*
3473 * allocate device instance structure, return NULL on failure
3474 */
3475static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3476{
3477 struct slgt_info *info;
3478
3479 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3480
3481 if (!info) {
3482 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3483 driver_name, adapter_num, port_num));
3484 } else {
3485 tty_port_init(&info->port);
3486 info->port.ops = &slgt_port_ops;
3487 INIT_WORK(&info->task, bh_handler);
3488 info->max_frame_size = 4096;
3489 info->base_clock = 14745600;
3490 info->rbuf_fill_level = DMABUFSIZE;
3491 init_waitqueue_head(&info->status_event_wait_q);
3492 init_waitqueue_head(&info->event_wait_q);
3493 spin_lock_init(&info->netlock);
3494 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3495 info->idle_mode = HDLC_TXIDLE_FLAGS;
3496 info->adapter_num = adapter_num;
3497 info->port_num = port_num;
3498
3499 timer_setup(&info->tx_timer, tx_timeout, 0);
3500 timer_setup(&info->rx_timer, rx_timeout, 0);
3501
3502 /* Copy configuration info to device instance data */
3503 info->pdev = pdev;
3504 info->irq_level = pdev->irq;
3505 info->phys_reg_addr = pci_resource_start(pdev,0);
3506
3507 info->bus_type = MGSL_BUS_TYPE_PCI;
3508 info->irq_flags = IRQF_SHARED;
3509
3510 info->init_error = -1; /* assume error, set to 0 on successful init */
3511 }
3512
3513 return info;
3514}
3515
3516static void device_init(int adapter_num, struct pci_dev *pdev)
3517{
3518 struct slgt_info *port_array[SLGT_MAX_PORTS];
3519 int i;
3520 int port_count = 1;
3521
3522 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3523 port_count = 2;
3524 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3525 port_count = 4;
3526
3527 /* allocate device instances for all ports */
3528 for (i=0; i < port_count; ++i) {
3529 port_array[i] = alloc_dev(adapter_num, i, pdev);
3530 if (port_array[i] == NULL) {
3531 for (--i; i >= 0; --i) {
3532 tty_port_destroy(&port_array[i]->port);
3533 kfree(port_array[i]);
3534 }
3535 return;
3536 }
3537 }
3538
3539 /* give copy of port_array to all ports and add to device list */
3540 for (i=0; i < port_count; ++i) {
3541 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3542 add_device(port_array[i]);
3543 port_array[i]->port_count = port_count;
3544 spin_lock_init(&port_array[i]->lock);
3545 }
3546
3547 /* Allocate and claim adapter resources */
3548 if (!claim_resources(port_array[0])) {
3549
3550 alloc_dma_bufs(port_array[0]);
3551
3552 /* copy resource information from first port to others */
3553 for (i = 1; i < port_count; ++i) {
3554 port_array[i]->irq_level = port_array[0]->irq_level;
3555 port_array[i]->reg_addr = port_array[0]->reg_addr;
3556 alloc_dma_bufs(port_array[i]);
3557 }
3558
3559 if (request_irq(port_array[0]->irq_level,
3560 slgt_interrupt,
3561 port_array[0]->irq_flags,
3562 port_array[0]->device_name,
3563 port_array[0]) < 0) {
3564 DBGERR(("%s request_irq failed IRQ=%d\n",
3565 port_array[0]->device_name,
3566 port_array[0]->irq_level));
3567 } else {
3568 port_array[0]->irq_requested = true;
3569 adapter_test(port_array[0]);
3570 for (i=1 ; i < port_count ; i++) {
3571 port_array[i]->init_error = port_array[0]->init_error;
3572 port_array[i]->gpio_present = port_array[0]->gpio_present;
3573 }
3574 }
3575 }
3576
3577 for (i = 0; i < port_count; ++i) {
3578 struct slgt_info *info = port_array[i];
3579 tty_port_register_device(&info->port, serial_driver, info->line,
3580 &info->pdev->dev);
3581 }
3582}
3583
3584static int init_one(struct pci_dev *dev,
3585 const struct pci_device_id *ent)
3586{
3587 if (pci_enable_device(dev)) {
3588 printk("error enabling pci device %p\n", dev);
3589 return -EIO;
3590 }
3591 pci_set_master(dev);
3592 device_init(slgt_device_count, dev);
3593 return 0;
3594}
3595
3596static void remove_one(struct pci_dev *dev)
3597{
3598}
3599
3600static const struct tty_operations ops = {
3601 .open = open,
3602 .close = close,
3603 .write = write,
3604 .put_char = put_char,
3605 .flush_chars = flush_chars,
3606 .write_room = write_room,
3607 .chars_in_buffer = chars_in_buffer,
3608 .flush_buffer = flush_buffer,
3609 .ioctl = ioctl,
3610 .compat_ioctl = slgt_compat_ioctl,
3611 .throttle = throttle,
3612 .unthrottle = unthrottle,
3613 .send_xchar = send_xchar,
3614 .break_ctl = set_break,
3615 .wait_until_sent = wait_until_sent,
3616 .set_termios = set_termios,
3617 .stop = tx_hold,
3618 .start = tx_release,
3619 .hangup = hangup,
3620 .tiocmget = tiocmget,
3621 .tiocmset = tiocmset,
3622 .get_icount = get_icount,
3623 .proc_show = synclink_gt_proc_show,
3624};
3625
3626static void slgt_cleanup(void)
3627{
3628 struct slgt_info *info;
3629 struct slgt_info *tmp;
3630
3631 if (serial_driver) {
3632 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3633 tty_unregister_device(serial_driver, info->line);
3634 tty_unregister_driver(serial_driver);
3635 tty_driver_kref_put(serial_driver);
3636 }
3637
3638 /* reset devices */
3639 info = slgt_device_list;
3640 while(info) {
3641 reset_port(info);
3642 info = info->next_device;
3643 }
3644
3645 /* release devices */
3646 info = slgt_device_list;
3647 while(info) {
3648#if SYNCLINK_GENERIC_HDLC
3649 hdlcdev_exit(info);
3650#endif
3651 free_dma_bufs(info);
3652 free_tmp_rbuf(info);
3653 if (info->port_num == 0)
3654 release_resources(info);
3655 tmp = info;
3656 info = info->next_device;
3657 tty_port_destroy(&tmp->port);
3658 kfree(tmp);
3659 }
3660
3661 if (pci_registered)
3662 pci_unregister_driver(&pci_driver);
3663}
3664
3665/*
3666 * Driver initialization entry point.
3667 */
3668static int __init slgt_init(void)
3669{
3670 int rc;
3671
3672 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3673 TTY_DRIVER_DYNAMIC_DEV);
3674 if (IS_ERR(serial_driver)) {
3675 printk("%s can't allocate tty driver\n", driver_name);
3676 return PTR_ERR(serial_driver);
3677 }
3678
3679 /* Initialize the tty_driver structure */
3680
3681 serial_driver->driver_name = "synclink_gt";
3682 serial_driver->name = tty_dev_prefix;
3683 serial_driver->major = ttymajor;
3684 serial_driver->minor_start = 64;
3685 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3686 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3687 serial_driver->init_termios = tty_std_termios;
3688 serial_driver->init_termios.c_cflag =
3689 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3690 serial_driver->init_termios.c_ispeed = 9600;
3691 serial_driver->init_termios.c_ospeed = 9600;
3692 tty_set_operations(serial_driver, &ops);
3693 if ((rc = tty_register_driver(serial_driver)) < 0) {
3694 DBGERR(("%s can't register serial driver\n", driver_name));
3695 tty_driver_kref_put(serial_driver);
3696 serial_driver = NULL;
3697 goto error;
3698 }
3699
3700 slgt_device_count = 0;
3701 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3702 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3703 goto error;
3704 }
3705 pci_registered = true;
3706
3707 return 0;
3708
3709error:
3710 slgt_cleanup();
3711 return rc;
3712}
3713
3714static void __exit slgt_exit(void)
3715{
3716 slgt_cleanup();
3717}
3718
3719module_init(slgt_init);
3720module_exit(slgt_exit);
3721
3722/*
3723 * register access routines
3724 */
3725
3726static inline void __iomem *calc_regaddr(struct slgt_info *info,
3727 unsigned int addr)
3728{
3729 void __iomem *reg_addr = info->reg_addr + addr;
3730
3731 if (addr >= 0x80)
3732 reg_addr += info->port_num * 32;
3733 else if (addr >= 0x40)
3734 reg_addr += info->port_num * 16;
3735
3736 return reg_addr;
3737}
3738
3739static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3740{
3741 return readb(calc_regaddr(info, addr));
3742}
3743
3744static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3745{
3746 writeb(value, calc_regaddr(info, addr));
3747}
3748
3749static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3750{
3751 return readw(calc_regaddr(info, addr));
3752}
3753
3754static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3755{
3756 writew(value, calc_regaddr(info, addr));
3757}
3758
3759static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3760{
3761 return readl(calc_regaddr(info, addr));
3762}
3763
3764static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3765{
3766 writel(value, calc_regaddr(info, addr));
3767}
3768
3769static void rdma_reset(struct slgt_info *info)
3770{
3771 unsigned int i;
3772
3773 /* set reset bit */
3774 wr_reg32(info, RDCSR, BIT1);
3775
3776 /* wait for enable bit cleared */
3777 for(i=0 ; i < 1000 ; i++)
3778 if (!(rd_reg32(info, RDCSR) & BIT0))
3779 break;
3780}
3781
3782static void tdma_reset(struct slgt_info *info)
3783{
3784 unsigned int i;
3785
3786 /* set reset bit */
3787 wr_reg32(info, TDCSR, BIT1);
3788
3789 /* wait for enable bit cleared */
3790 for(i=0 ; i < 1000 ; i++)
3791 if (!(rd_reg32(info, TDCSR) & BIT0))
3792 break;
3793}
3794
3795/*
3796 * enable internal loopback
3797 * TxCLK and RxCLK are generated from BRG
3798 * and TxD is looped back to RxD internally.
3799 */
3800static void enable_loopback(struct slgt_info *info)
3801{
3802 /* SCR (serial control) BIT2=loopback enable */
3803 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3804
3805 if (info->params.mode != MGSL_MODE_ASYNC) {
3806 /* CCR (clock control)
3807 * 07..05 tx clock source (010 = BRG)
3808 * 04..02 rx clock source (010 = BRG)
3809 * 01 auxclk enable (0 = disable)
3810 * 00 BRG enable (1 = enable)
3811 *
3812 * 0100 1001
3813 */
3814 wr_reg8(info, CCR, 0x49);
3815
3816 /* set speed if available, otherwise use default */
3817 if (info->params.clock_speed)
3818 set_rate(info, info->params.clock_speed);
3819 else
3820 set_rate(info, 3686400);
3821 }
3822}
3823
3824/*
3825 * set baud rate generator to specified rate
3826 */
3827static void set_rate(struct slgt_info *info, u32 rate)
3828{
3829 unsigned int div;
3830 unsigned int osc = info->base_clock;
3831
3832 /* div = osc/rate - 1
3833 *
3834 * Round div up if osc/rate is not integer to
3835 * force to next slowest rate.
3836 */
3837
3838 if (rate) {
3839 div = osc/rate;
3840 if (!(osc % rate) && div)
3841 div--;
3842 wr_reg16(info, BDR, (unsigned short)div);
3843 }
3844}
3845
3846static void rx_stop(struct slgt_info *info)
3847{
3848 unsigned short val;
3849
3850 /* disable and reset receiver */
3851 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3852 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3853 wr_reg16(info, RCR, val); /* clear reset bit */
3854
3855 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3856
3857 /* clear pending rx interrupts */
3858 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3859
3860 rdma_reset(info);
3861
3862 info->rx_enabled = false;
3863 info->rx_restart = false;
3864}
3865
3866static void rx_start(struct slgt_info *info)
3867{
3868 unsigned short val;
3869
3870 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3871
3872 /* clear pending rx overrun IRQ */
3873 wr_reg16(info, SSR, IRQ_RXOVER);
3874
3875 /* reset and disable receiver */
3876 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3877 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3878 wr_reg16(info, RCR, val); /* clear reset bit */
3879
3880 rdma_reset(info);
3881 reset_rbufs(info);
3882
3883 if (info->rx_pio) {
3884 /* rx request when rx FIFO not empty */
3885 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3886 slgt_irq_on(info, IRQ_RXDATA);
3887 if (info->params.mode == MGSL_MODE_ASYNC) {
3888 /* enable saving of rx status */
3889 wr_reg32(info, RDCSR, BIT6);
3890 }
3891 } else {
3892 /* rx request when rx FIFO half full */
3893 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3894 /* set 1st descriptor address */
3895 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3896
3897 if (info->params.mode != MGSL_MODE_ASYNC) {
3898 /* enable rx DMA and DMA interrupt */
3899 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3900 } else {
3901 /* enable saving of rx status, rx DMA and DMA interrupt */
3902 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3903 }
3904 }
3905
3906 slgt_irq_on(info, IRQ_RXOVER);
3907
3908 /* enable receiver */
3909 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3910
3911 info->rx_restart = false;
3912 info->rx_enabled = true;
3913}
3914
3915static void tx_start(struct slgt_info *info)
3916{
3917 if (!info->tx_enabled) {
3918 wr_reg16(info, TCR,
3919 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3920 info->tx_enabled = true;
3921 }
3922
3923 if (desc_count(info->tbufs[info->tbuf_start])) {
3924 info->drop_rts_on_tx_done = false;
3925
3926 if (info->params.mode != MGSL_MODE_ASYNC) {
3927 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3928 get_gtsignals(info);
3929 if (!(info->signals & SerialSignal_RTS)) {
3930 info->signals |= SerialSignal_RTS;
3931 set_gtsignals(info);
3932 info->drop_rts_on_tx_done = true;
3933 }
3934 }
3935
3936 slgt_irq_off(info, IRQ_TXDATA);
3937 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3938 /* clear tx idle and underrun status bits */
3939 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3940 } else {
3941 slgt_irq_off(info, IRQ_TXDATA);
3942 slgt_irq_on(info, IRQ_TXIDLE);
3943 /* clear tx idle status bit */
3944 wr_reg16(info, SSR, IRQ_TXIDLE);
3945 }
3946 /* set 1st descriptor address and start DMA */
3947 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3948 wr_reg32(info, TDCSR, BIT2 + BIT0);
3949 info->tx_active = true;
3950 }
3951}
3952
3953static void tx_stop(struct slgt_info *info)
3954{
3955 unsigned short val;
3956
3957 del_timer(&info->tx_timer);
3958
3959 tdma_reset(info);
3960
3961 /* reset and disable transmitter */
3962 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3963 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3964
3965 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3966
3967 /* clear tx idle and underrun status bit */
3968 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3969
3970 reset_tbufs(info);
3971
3972 info->tx_enabled = false;
3973 info->tx_active = false;
3974}
3975
3976static void reset_port(struct slgt_info *info)
3977{
3978 if (!info->reg_addr)
3979 return;
3980
3981 tx_stop(info);
3982 rx_stop(info);
3983
3984 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3985 set_gtsignals(info);
3986
3987 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3988}
3989
3990static void reset_adapter(struct slgt_info *info)
3991{
3992 int i;
3993 for (i=0; i < info->port_count; ++i) {
3994 if (info->port_array[i])
3995 reset_port(info->port_array[i]);
3996 }
3997}
3998
3999static void async_mode(struct slgt_info *info)
4000{
4001 unsigned short val;
4002
4003 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4004 tx_stop(info);
4005 rx_stop(info);
4006
4007 /* TCR (tx control)
4008 *
4009 * 15..13 mode, 010=async
4010 * 12..10 encoding, 000=NRZ
4011 * 09 parity enable
4012 * 08 1=odd parity, 0=even parity
4013 * 07 1=RTS driver control
4014 * 06 1=break enable
4015 * 05..04 character length
4016 * 00=5 bits
4017 * 01=6 bits
4018 * 10=7 bits
4019 * 11=8 bits
4020 * 03 0=1 stop bit, 1=2 stop bits
4021 * 02 reset
4022 * 01 enable
4023 * 00 auto-CTS enable
4024 */
4025 val = 0x4000;
4026
4027 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4028 val |= BIT7;
4029
4030 if (info->params.parity != ASYNC_PARITY_NONE) {
4031 val |= BIT9;
4032 if (info->params.parity == ASYNC_PARITY_ODD)
4033 val |= BIT8;
4034 }
4035
4036 switch (info->params.data_bits)
4037 {
4038 case 6: val |= BIT4; break;
4039 case 7: val |= BIT5; break;
4040 case 8: val |= BIT5 + BIT4; break;
4041 }
4042
4043 if (info->params.stop_bits != 1)
4044 val |= BIT3;
4045
4046 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4047 val |= BIT0;
4048
4049 wr_reg16(info, TCR, val);
4050
4051 /* RCR (rx control)
4052 *
4053 * 15..13 mode, 010=async
4054 * 12..10 encoding, 000=NRZ
4055 * 09 parity enable
4056 * 08 1=odd parity, 0=even parity
4057 * 07..06 reserved, must be 0
4058 * 05..04 character length
4059 * 00=5 bits
4060 * 01=6 bits
4061 * 10=7 bits
4062 * 11=8 bits
4063 * 03 reserved, must be zero
4064 * 02 reset
4065 * 01 enable
4066 * 00 auto-DCD enable
4067 */
4068 val = 0x4000;
4069
4070 if (info->params.parity != ASYNC_PARITY_NONE) {
4071 val |= BIT9;
4072 if (info->params.parity == ASYNC_PARITY_ODD)
4073 val |= BIT8;
4074 }
4075
4076 switch (info->params.data_bits)
4077 {
4078 case 6: val |= BIT4; break;
4079 case 7: val |= BIT5; break;
4080 case 8: val |= BIT5 + BIT4; break;
4081 }
4082
4083 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4084 val |= BIT0;
4085
4086 wr_reg16(info, RCR, val);
4087
4088 /* CCR (clock control)
4089 *
4090 * 07..05 011 = tx clock source is BRG/16
4091 * 04..02 010 = rx clock source is BRG
4092 * 01 0 = auxclk disabled
4093 * 00 1 = BRG enabled
4094 *
4095 * 0110 1001
4096 */
4097 wr_reg8(info, CCR, 0x69);
4098
4099 msc_set_vcr(info);
4100
4101 /* SCR (serial control)
4102 *
4103 * 15 1=tx req on FIFO half empty
4104 * 14 1=rx req on FIFO half full
4105 * 13 tx data IRQ enable
4106 * 12 tx idle IRQ enable
4107 * 11 rx break on IRQ enable
4108 * 10 rx data IRQ enable
4109 * 09 rx break off IRQ enable
4110 * 08 overrun IRQ enable
4111 * 07 DSR IRQ enable
4112 * 06 CTS IRQ enable
4113 * 05 DCD IRQ enable
4114 * 04 RI IRQ enable
4115 * 03 0=16x sampling, 1=8x sampling
4116 * 02 1=txd->rxd internal loopback enable
4117 * 01 reserved, must be zero
4118 * 00 1=master IRQ enable
4119 */
4120 val = BIT15 + BIT14 + BIT0;
4121 /* JCR[8] : 1 = x8 async mode feature available */
4122 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4123 ((info->base_clock < (info->params.data_rate * 16)) ||
4124 (info->base_clock % (info->params.data_rate * 16)))) {
4125 /* use 8x sampling */
4126 val |= BIT3;
4127 set_rate(info, info->params.data_rate * 8);
4128 } else {
4129 /* use 16x sampling */
4130 set_rate(info, info->params.data_rate * 16);
4131 }
4132 wr_reg16(info, SCR, val);
4133
4134 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4135
4136 if (info->params.loopback)
4137 enable_loopback(info);
4138}
4139
4140static void sync_mode(struct slgt_info *info)
4141{
4142 unsigned short val;
4143
4144 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4145 tx_stop(info);
4146 rx_stop(info);
4147
4148 /* TCR (tx control)
4149 *
4150 * 15..13 mode
4151 * 000=HDLC/SDLC
4152 * 001=raw bit synchronous
4153 * 010=asynchronous/isochronous
4154 * 011=monosync byte synchronous
4155 * 100=bisync byte synchronous
4156 * 101=xsync byte synchronous
4157 * 12..10 encoding
4158 * 09 CRC enable
4159 * 08 CRC32
4160 * 07 1=RTS driver control
4161 * 06 preamble enable
4162 * 05..04 preamble length
4163 * 03 share open/close flag
4164 * 02 reset
4165 * 01 enable
4166 * 00 auto-CTS enable
4167 */
4168 val = BIT2;
4169
4170 switch(info->params.mode) {
4171 case MGSL_MODE_XSYNC:
4172 val |= BIT15 + BIT13;
4173 break;
4174 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4175 case MGSL_MODE_BISYNC: val |= BIT15; break;
4176 case MGSL_MODE_RAW: val |= BIT13; break;
4177 }
4178 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4179 val |= BIT7;
4180
4181 switch(info->params.encoding)
4182 {
4183 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4184 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4185 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4186 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4187 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4188 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4189 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4190 }
4191
4192 switch (info->params.crc_type & HDLC_CRC_MASK)
4193 {
4194 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4195 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4196 }
4197
4198 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4199 val |= BIT6;
4200
4201 switch (info->params.preamble_length)
4202 {
4203 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4204 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4205 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4206 }
4207
4208 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4209 val |= BIT0;
4210
4211 wr_reg16(info, TCR, val);
4212
4213 /* TPR (transmit preamble) */
4214
4215 switch (info->params.preamble)
4216 {
4217 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4218 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4219 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4220 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4221 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4222 default: val = 0x7e; break;
4223 }
4224 wr_reg8(info, TPR, (unsigned char)val);
4225
4226 /* RCR (rx control)
4227 *
4228 * 15..13 mode
4229 * 000=HDLC/SDLC
4230 * 001=raw bit synchronous
4231 * 010=asynchronous/isochronous
4232 * 011=monosync byte synchronous
4233 * 100=bisync byte synchronous
4234 * 101=xsync byte synchronous
4235 * 12..10 encoding
4236 * 09 CRC enable
4237 * 08 CRC32
4238 * 07..03 reserved, must be 0
4239 * 02 reset
4240 * 01 enable
4241 * 00 auto-DCD enable
4242 */
4243 val = 0;
4244
4245 switch(info->params.mode) {
4246 case MGSL_MODE_XSYNC:
4247 val |= BIT15 + BIT13;
4248 break;
4249 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4250 case MGSL_MODE_BISYNC: val |= BIT15; break;
4251 case MGSL_MODE_RAW: val |= BIT13; break;
4252 }
4253
4254 switch(info->params.encoding)
4255 {
4256 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4257 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4258 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4259 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4260 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4261 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4262 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4263 }
4264
4265 switch (info->params.crc_type & HDLC_CRC_MASK)
4266 {
4267 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4268 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4269 }
4270
4271 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4272 val |= BIT0;
4273
4274 wr_reg16(info, RCR, val);
4275
4276 /* CCR (clock control)
4277 *
4278 * 07..05 tx clock source
4279 * 04..02 rx clock source
4280 * 01 auxclk enable
4281 * 00 BRG enable
4282 */
4283 val = 0;
4284
4285 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4286 {
4287 // when RxC source is DPLL, BRG generates 16X DPLL
4288 // reference clock, so take TxC from BRG/16 to get
4289 // transmit clock at actual data rate
4290 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4291 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4292 else
4293 val |= BIT6; /* 010, txclk = BRG */
4294 }
4295 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4296 val |= BIT7; /* 100, txclk = DPLL Input */
4297 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4298 val |= BIT5; /* 001, txclk = RXC Input */
4299
4300 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4301 val |= BIT3; /* 010, rxclk = BRG */
4302 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4303 val |= BIT4; /* 100, rxclk = DPLL */
4304 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4305 val |= BIT2; /* 001, rxclk = TXC Input */
4306
4307 if (info->params.clock_speed)
4308 val |= BIT1 + BIT0;
4309
4310 wr_reg8(info, CCR, (unsigned char)val);
4311
4312 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4313 {
4314 // program DPLL mode
4315 switch(info->params.encoding)
4316 {
4317 case HDLC_ENCODING_BIPHASE_MARK:
4318 case HDLC_ENCODING_BIPHASE_SPACE:
4319 val = BIT7; break;
4320 case HDLC_ENCODING_BIPHASE_LEVEL:
4321 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4322 val = BIT7 + BIT6; break;
4323 default: val = BIT6; // NRZ encodings
4324 }
4325 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4326
4327 // DPLL requires a 16X reference clock from BRG
4328 set_rate(info, info->params.clock_speed * 16);
4329 }
4330 else
4331 set_rate(info, info->params.clock_speed);
4332
4333 tx_set_idle(info);
4334
4335 msc_set_vcr(info);
4336
4337 /* SCR (serial control)
4338 *
4339 * 15 1=tx req on FIFO half empty
4340 * 14 1=rx req on FIFO half full
4341 * 13 tx data IRQ enable
4342 * 12 tx idle IRQ enable
4343 * 11 underrun IRQ enable
4344 * 10 rx data IRQ enable
4345 * 09 rx idle IRQ enable
4346 * 08 overrun IRQ enable
4347 * 07 DSR IRQ enable
4348 * 06 CTS IRQ enable
4349 * 05 DCD IRQ enable
4350 * 04 RI IRQ enable
4351 * 03 reserved, must be zero
4352 * 02 1=txd->rxd internal loopback enable
4353 * 01 reserved, must be zero
4354 * 00 1=master IRQ enable
4355 */
4356 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4357
4358 if (info->params.loopback)
4359 enable_loopback(info);
4360}
4361
4362/*
4363 * set transmit idle mode
4364 */
4365static void tx_set_idle(struct slgt_info *info)
4366{
4367 unsigned char val;
4368 unsigned short tcr;
4369
4370 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4371 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4372 */
4373 tcr = rd_reg16(info, TCR);
4374 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4375 /* disable preamble, set idle size to 16 bits */
4376 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4377 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4378 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4379 } else if (!(tcr & BIT6)) {
4380 /* preamble is disabled, set idle size to 8 bits */
4381 tcr &= ~(BIT5 + BIT4);
4382 }
4383 wr_reg16(info, TCR, tcr);
4384
4385 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4386 /* LSB of custom tx idle specified in tx idle register */
4387 val = (unsigned char)(info->idle_mode & 0xff);
4388 } else {
4389 /* standard 8 bit idle patterns */
4390 switch(info->idle_mode)
4391 {
4392 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4393 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4394 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4395 case HDLC_TXIDLE_ZEROS:
4396 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4397 default: val = 0xff;
4398 }
4399 }
4400
4401 wr_reg8(info, TIR, val);
4402}
4403
4404/*
4405 * get state of V24 status (input) signals
4406 */
4407static void get_gtsignals(struct slgt_info *info)
4408{
4409 unsigned short status = rd_reg16(info, SSR);
4410
4411 /* clear all serial signals except RTS and DTR */
4412 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4413
4414 if (status & BIT3)
4415 info->signals |= SerialSignal_DSR;
4416 if (status & BIT2)
4417 info->signals |= SerialSignal_CTS;
4418 if (status & BIT1)
4419 info->signals |= SerialSignal_DCD;
4420 if (status & BIT0)
4421 info->signals |= SerialSignal_RI;
4422}
4423
4424/*
4425 * set V.24 Control Register based on current configuration
4426 */
4427static void msc_set_vcr(struct slgt_info *info)
4428{
4429 unsigned char val = 0;
4430
4431 /* VCR (V.24 control)
4432 *
4433 * 07..04 serial IF select
4434 * 03 DTR
4435 * 02 RTS
4436 * 01 LL
4437 * 00 RL
4438 */
4439
4440 switch(info->if_mode & MGSL_INTERFACE_MASK)
4441 {
4442 case MGSL_INTERFACE_RS232:
4443 val |= BIT5; /* 0010 */
4444 break;
4445 case MGSL_INTERFACE_V35:
4446 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4447 break;
4448 case MGSL_INTERFACE_RS422:
4449 val |= BIT6; /* 0100 */
4450 break;
4451 }
4452
4453 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4454 val |= BIT4;
4455 if (info->signals & SerialSignal_DTR)
4456 val |= BIT3;
4457 if (info->signals & SerialSignal_RTS)
4458 val |= BIT2;
4459 if (info->if_mode & MGSL_INTERFACE_LL)
4460 val |= BIT1;
4461 if (info->if_mode & MGSL_INTERFACE_RL)
4462 val |= BIT0;
4463 wr_reg8(info, VCR, val);
4464}
4465
4466/*
4467 * set state of V24 control (output) signals
4468 */
4469static void set_gtsignals(struct slgt_info *info)
4470{
4471 unsigned char val = rd_reg8(info, VCR);
4472 if (info->signals & SerialSignal_DTR)
4473 val |= BIT3;
4474 else
4475 val &= ~BIT3;
4476 if (info->signals & SerialSignal_RTS)
4477 val |= BIT2;
4478 else
4479 val &= ~BIT2;
4480 wr_reg8(info, VCR, val);
4481}
4482
4483/*
4484 * free range of receive DMA buffers (i to last)
4485 */
4486static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4487{
4488 int done = 0;
4489
4490 while(!done) {
4491 /* reset current buffer for reuse */
4492 info->rbufs[i].status = 0;
4493 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4494 if (i == last)
4495 done = 1;
4496 if (++i == info->rbuf_count)
4497 i = 0;
4498 }
4499 info->rbuf_current = i;
4500}
4501
4502/*
4503 * mark all receive DMA buffers as free
4504 */
4505static void reset_rbufs(struct slgt_info *info)
4506{
4507 free_rbufs(info, 0, info->rbuf_count - 1);
4508 info->rbuf_fill_index = 0;
4509 info->rbuf_fill_count = 0;
4510}
4511
4512/*
4513 * pass receive HDLC frame to upper layer
4514 *
4515 * return true if frame available, otherwise false
4516 */
4517static bool rx_get_frame(struct slgt_info *info)
4518{
4519 unsigned int start, end;
4520 unsigned short status;
4521 unsigned int framesize = 0;
4522 unsigned long flags;
4523 struct tty_struct *tty = info->port.tty;
4524 unsigned char addr_field = 0xff;
4525 unsigned int crc_size = 0;
4526
4527 switch (info->params.crc_type & HDLC_CRC_MASK) {
4528 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4529 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4530 }
4531
4532check_again:
4533
4534 framesize = 0;
4535 addr_field = 0xff;
4536 start = end = info->rbuf_current;
4537
4538 for (;;) {
4539 if (!desc_complete(info->rbufs[end]))
4540 goto cleanup;
4541
4542 if (framesize == 0 && info->params.addr_filter != 0xff)
4543 addr_field = info->rbufs[end].buf[0];
4544
4545 framesize += desc_count(info->rbufs[end]);
4546
4547 if (desc_eof(info->rbufs[end]))
4548 break;
4549
4550 if (++end == info->rbuf_count)
4551 end = 0;
4552
4553 if (end == info->rbuf_current) {
4554 if (info->rx_enabled){
4555 spin_lock_irqsave(&info->lock,flags);
4556 rx_start(info);
4557 spin_unlock_irqrestore(&info->lock,flags);
4558 }
4559 goto cleanup;
4560 }
4561 }
4562
4563 /* status
4564 *
4565 * 15 buffer complete
4566 * 14..06 reserved
4567 * 05..04 residue
4568 * 02 eof (end of frame)
4569 * 01 CRC error
4570 * 00 abort
4571 */
4572 status = desc_status(info->rbufs[end]);
4573
4574 /* ignore CRC bit if not using CRC (bit is undefined) */
4575 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4576 status &= ~BIT1;
4577
4578 if (framesize == 0 ||
4579 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4580 free_rbufs(info, start, end);
4581 goto check_again;
4582 }
4583
4584 if (framesize < (2 + crc_size) || status & BIT0) {
4585 info->icount.rxshort++;
4586 framesize = 0;
4587 } else if (status & BIT1) {
4588 info->icount.rxcrc++;
4589 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4590 framesize = 0;
4591 }
4592
4593#if SYNCLINK_GENERIC_HDLC
4594 if (framesize == 0) {
4595 info->netdev->stats.rx_errors++;
4596 info->netdev->stats.rx_frame_errors++;
4597 }
4598#endif
4599
4600 DBGBH(("%s rx frame status=%04X size=%d\n",
4601 info->device_name, status, framesize));
4602 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4603
4604 if (framesize) {
4605 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4606 framesize -= crc_size;
4607 crc_size = 0;
4608 }
4609
4610 if (framesize > info->max_frame_size + crc_size)
4611 info->icount.rxlong++;
4612 else {
4613 /* copy dma buffer(s) to contiguous temp buffer */
4614 int copy_count = framesize;
4615 int i = start;
4616 unsigned char *p = info->tmp_rbuf;
4617 info->tmp_rbuf_count = framesize;
4618
4619 info->icount.rxok++;
4620
4621 while(copy_count) {
4622 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4623 memcpy(p, info->rbufs[i].buf, partial_count);
4624 p += partial_count;
4625 copy_count -= partial_count;
4626 if (++i == info->rbuf_count)
4627 i = 0;
4628 }
4629
4630 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4631 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4632 framesize++;
4633 }
4634
4635#if SYNCLINK_GENERIC_HDLC
4636 if (info->netcount)
4637 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4638 else
4639#endif
4640 ldisc_receive_buf(tty, info->tmp_rbuf, NULL,
4641 framesize);
4642 }
4643 }
4644 free_rbufs(info, start, end);
4645 return true;
4646
4647cleanup:
4648 return false;
4649}
4650
4651/*
4652 * pass receive buffer (RAW synchronous mode) to tty layer
4653 * return true if buffer available, otherwise false
4654 */
4655static bool rx_get_buf(struct slgt_info *info)
4656{
4657 unsigned int i = info->rbuf_current;
4658 unsigned int count;
4659
4660 if (!desc_complete(info->rbufs[i]))
4661 return false;
4662 count = desc_count(info->rbufs[i]);
4663 switch(info->params.mode) {
4664 case MGSL_MODE_MONOSYNC:
4665 case MGSL_MODE_BISYNC:
4666 case MGSL_MODE_XSYNC:
4667 /* ignore residue in byte synchronous modes */
4668 if (desc_residue(info->rbufs[i]))
4669 count--;
4670 break;
4671 }
4672 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4673 DBGINFO(("rx_get_buf size=%d\n", count));
4674 if (count)
4675 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, NULL,
4676 count);
4677 free_rbufs(info, i, i);
4678 return true;
4679}
4680
4681static void reset_tbufs(struct slgt_info *info)
4682{
4683 unsigned int i;
4684 info->tbuf_current = 0;
4685 for (i=0 ; i < info->tbuf_count ; i++) {
4686 info->tbufs[i].status = 0;
4687 info->tbufs[i].count = 0;
4688 }
4689}
4690
4691/*
4692 * return number of free transmit DMA buffers
4693 */
4694static unsigned int free_tbuf_count(struct slgt_info *info)
4695{
4696 unsigned int count = 0;
4697 unsigned int i = info->tbuf_current;
4698
4699 do
4700 {
4701 if (desc_count(info->tbufs[i]))
4702 break; /* buffer in use */
4703 ++count;
4704 if (++i == info->tbuf_count)
4705 i=0;
4706 } while (i != info->tbuf_current);
4707
4708 /* if tx DMA active, last zero count buffer is in use */
4709 if (count && (rd_reg32(info, TDCSR) & BIT0))
4710 --count;
4711
4712 return count;
4713}
4714
4715/*
4716 * return number of bytes in unsent transmit DMA buffers
4717 * and the serial controller tx FIFO
4718 */
4719static unsigned int tbuf_bytes(struct slgt_info *info)
4720{
4721 unsigned int total_count = 0;
4722 unsigned int i = info->tbuf_current;
4723 unsigned int reg_value;
4724 unsigned int count;
4725 unsigned int active_buf_count = 0;
4726
4727 /*
4728 * Add descriptor counts for all tx DMA buffers.
4729 * If count is zero (cleared by DMA controller after read),
4730 * the buffer is complete or is actively being read from.
4731 *
4732 * Record buf_count of last buffer with zero count starting
4733 * from current ring position. buf_count is mirror
4734 * copy of count and is not cleared by serial controller.
4735 * If DMA controller is active, that buffer is actively
4736 * being read so add to total.
4737 */
4738 do {
4739 count = desc_count(info->tbufs[i]);
4740 if (count)
4741 total_count += count;
4742 else if (!total_count)
4743 active_buf_count = info->tbufs[i].buf_count;
4744 if (++i == info->tbuf_count)
4745 i = 0;
4746 } while (i != info->tbuf_current);
4747
4748 /* read tx DMA status register */
4749 reg_value = rd_reg32(info, TDCSR);
4750
4751 /* if tx DMA active, last zero count buffer is in use */
4752 if (reg_value & BIT0)
4753 total_count += active_buf_count;
4754
4755 /* add tx FIFO count = reg_value[15..8] */
4756 total_count += (reg_value >> 8) & 0xff;
4757
4758 /* if transmitter active add one byte for shift register */
4759 if (info->tx_active)
4760 total_count++;
4761
4762 return total_count;
4763}
4764
4765/*
4766 * load data into transmit DMA buffer ring and start transmitter if needed
4767 * return true if data accepted, otherwise false (buffers full)
4768 */
4769static bool tx_load(struct slgt_info *info, const u8 *buf, unsigned int size)
4770{
4771 unsigned short count;
4772 unsigned int i;
4773 struct slgt_desc *d;
4774
4775 /* check required buffer space */
4776 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4777 return false;
4778
4779 DBGDATA(info, buf, size, "tx");
4780
4781 /*
4782 * copy data to one or more DMA buffers in circular ring
4783 * tbuf_start = first buffer for this data
4784 * tbuf_current = next free buffer
4785 *
4786 * Copy all data before making data visible to DMA controller by
4787 * setting descriptor count of the first buffer.
4788 * This prevents an active DMA controller from reading the first DMA
4789 * buffers of a frame and stopping before the final buffers are filled.
4790 */
4791
4792 info->tbuf_start = i = info->tbuf_current;
4793
4794 while (size) {
4795 d = &info->tbufs[i];
4796
4797 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4798 memcpy(d->buf, buf, count);
4799
4800 size -= count;
4801 buf += count;
4802
4803 /*
4804 * set EOF bit for last buffer of HDLC frame or
4805 * for every buffer in raw mode
4806 */
4807 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4808 info->params.mode == MGSL_MODE_RAW)
4809 set_desc_eof(*d, 1);
4810 else
4811 set_desc_eof(*d, 0);
4812
4813 /* set descriptor count for all but first buffer */
4814 if (i != info->tbuf_start)
4815 set_desc_count(*d, count);
4816 d->buf_count = count;
4817
4818 if (++i == info->tbuf_count)
4819 i = 0;
4820 }
4821
4822 info->tbuf_current = i;
4823
4824 /* set first buffer count to make new data visible to DMA controller */
4825 d = &info->tbufs[info->tbuf_start];
4826 set_desc_count(*d, d->buf_count);
4827
4828 /* start transmitter if needed and update transmit timeout */
4829 if (!info->tx_active)
4830 tx_start(info);
4831 update_tx_timer(info);
4832
4833 return true;
4834}
4835
4836static int register_test(struct slgt_info *info)
4837{
4838 static unsigned short patterns[] =
4839 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4840 static unsigned int count = ARRAY_SIZE(patterns);
4841 unsigned int i;
4842 int rc = 0;
4843
4844 for (i=0 ; i < count ; i++) {
4845 wr_reg16(info, TIR, patterns[i]);
4846 wr_reg16(info, BDR, patterns[(i+1)%count]);
4847 if ((rd_reg16(info, TIR) != patterns[i]) ||
4848 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4849 rc = -ENODEV;
4850 break;
4851 }
4852 }
4853 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4854 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4855 return rc;
4856}
4857
4858static int irq_test(struct slgt_info *info)
4859{
4860 unsigned long timeout;
4861 unsigned long flags;
4862 struct tty_struct *oldtty = info->port.tty;
4863 u32 speed = info->params.data_rate;
4864
4865 info->params.data_rate = 921600;
4866 info->port.tty = NULL;
4867
4868 spin_lock_irqsave(&info->lock, flags);
4869 async_mode(info);
4870 slgt_irq_on(info, IRQ_TXIDLE);
4871
4872 /* enable transmitter */
4873 wr_reg16(info, TCR,
4874 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4875
4876 /* write one byte and wait for tx idle */
4877 wr_reg16(info, TDR, 0);
4878
4879 /* assume failure */
4880 info->init_error = DiagStatus_IrqFailure;
4881 info->irq_occurred = false;
4882
4883 spin_unlock_irqrestore(&info->lock, flags);
4884
4885 timeout=100;
4886 while(timeout-- && !info->irq_occurred)
4887 msleep_interruptible(10);
4888
4889 spin_lock_irqsave(&info->lock,flags);
4890 reset_port(info);
4891 spin_unlock_irqrestore(&info->lock,flags);
4892
4893 info->params.data_rate = speed;
4894 info->port.tty = oldtty;
4895
4896 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4897 return info->irq_occurred ? 0 : -ENODEV;
4898}
4899
4900static int loopback_test_rx(struct slgt_info *info)
4901{
4902 unsigned char *src, *dest;
4903 int count;
4904
4905 if (desc_complete(info->rbufs[0])) {
4906 count = desc_count(info->rbufs[0]);
4907 src = info->rbufs[0].buf;
4908 dest = info->tmp_rbuf;
4909
4910 for( ; count ; count-=2, src+=2) {
4911 /* src=data byte (src+1)=status byte */
4912 if (!(*(src+1) & (BIT9 + BIT8))) {
4913 *dest = *src;
4914 dest++;
4915 info->tmp_rbuf_count++;
4916 }
4917 }
4918 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4919 return 1;
4920 }
4921 return 0;
4922}
4923
4924static int loopback_test(struct slgt_info *info)
4925{
4926#define TESTFRAMESIZE 20
4927
4928 unsigned long timeout;
4929 u16 count;
4930 unsigned char buf[TESTFRAMESIZE];
4931 int rc = -ENODEV;
4932 unsigned long flags;
4933
4934 struct tty_struct *oldtty = info->port.tty;
4935 MGSL_PARAMS params;
4936
4937 memcpy(¶ms, &info->params, sizeof(params));
4938
4939 info->params.mode = MGSL_MODE_ASYNC;
4940 info->params.data_rate = 921600;
4941 info->params.loopback = 1;
4942 info->port.tty = NULL;
4943
4944 /* build and send transmit frame */
4945 for (count = 0; count < TESTFRAMESIZE; ++count)
4946 buf[count] = (unsigned char)count;
4947
4948 info->tmp_rbuf_count = 0;
4949 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4950
4951 /* program hardware for HDLC and enabled receiver */
4952 spin_lock_irqsave(&info->lock,flags);
4953 async_mode(info);
4954 rx_start(info);
4955 tx_load(info, buf, count);
4956 spin_unlock_irqrestore(&info->lock, flags);
4957
4958 /* wait for receive complete */
4959 for (timeout = 100; timeout; --timeout) {
4960 msleep_interruptible(10);
4961 if (loopback_test_rx(info)) {
4962 rc = 0;
4963 break;
4964 }
4965 }
4966
4967 /* verify received frame length and contents */
4968 if (!rc && (info->tmp_rbuf_count != count ||
4969 memcmp(buf, info->tmp_rbuf, count))) {
4970 rc = -ENODEV;
4971 }
4972
4973 spin_lock_irqsave(&info->lock,flags);
4974 reset_adapter(info);
4975 spin_unlock_irqrestore(&info->lock,flags);
4976
4977 memcpy(&info->params, ¶ms, sizeof(info->params));
4978 info->port.tty = oldtty;
4979
4980 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4981 return rc;
4982}
4983
4984static int adapter_test(struct slgt_info *info)
4985{
4986 DBGINFO(("testing %s\n", info->device_name));
4987 if (register_test(info) < 0) {
4988 printk("register test failure %s addr=%08X\n",
4989 info->device_name, info->phys_reg_addr);
4990 } else if (irq_test(info) < 0) {
4991 printk("IRQ test failure %s IRQ=%d\n",
4992 info->device_name, info->irq_level);
4993 } else if (loopback_test(info) < 0) {
4994 printk("loopback test failure %s\n", info->device_name);
4995 }
4996 return info->init_error;
4997}
4998
4999/*
5000 * transmit timeout handler
5001 */
5002static void tx_timeout(struct timer_list *t)
5003{
5004 struct slgt_info *info = from_timer(info, t, tx_timer);
5005 unsigned long flags;
5006
5007 DBGINFO(("%s tx_timeout\n", info->device_name));
5008 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5009 info->icount.txtimeout++;
5010 }
5011 spin_lock_irqsave(&info->lock,flags);
5012 tx_stop(info);
5013 spin_unlock_irqrestore(&info->lock,flags);
5014
5015#if SYNCLINK_GENERIC_HDLC
5016 if (info->netcount)
5017 hdlcdev_tx_done(info);
5018 else
5019#endif
5020 bh_transmit(info);
5021}
5022
5023/*
5024 * receive buffer polling timer
5025 */
5026static void rx_timeout(struct timer_list *t)
5027{
5028 struct slgt_info *info = from_timer(info, t, rx_timer);
5029 unsigned long flags;
5030
5031 DBGINFO(("%s rx_timeout\n", info->device_name));
5032 spin_lock_irqsave(&info->lock, flags);
5033 info->pending_bh |= BH_RECEIVE;
5034 spin_unlock_irqrestore(&info->lock, flags);
5035 bh_handler(&info->task);
5036}
5037
1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static char *driver_name = "SyncLink GT";
91static char *slgt_driver_name = "synclink_gt";
92static char *tty_dev_prefix = "ttySLG";
93MODULE_LICENSE("GPL");
94#define MAX_DEVICES 32
95
96static const struct pci_device_id pci_table[] = {
97 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {0,}, /* terminate list */
102};
103MODULE_DEVICE_TABLE(pci, pci_table);
104
105static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
106static void remove_one(struct pci_dev *dev);
107static struct pci_driver pci_driver = {
108 .name = "synclink_gt",
109 .id_table = pci_table,
110 .probe = init_one,
111 .remove = remove_one,
112};
113
114static bool pci_registered;
115
116/*
117 * module configuration and status
118 */
119static struct slgt_info *slgt_device_list;
120static int slgt_device_count;
121
122static int ttymajor;
123static int debug_level;
124static int maxframe[MAX_DEVICES];
125
126module_param(ttymajor, int, 0);
127module_param(debug_level, int, 0);
128module_param_array(maxframe, int, NULL, 0);
129
130MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
131MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
132MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
133
134/*
135 * tty support and callbacks
136 */
137static struct tty_driver *serial_driver;
138
139static void wait_until_sent(struct tty_struct *tty, int timeout);
140static void flush_buffer(struct tty_struct *tty);
141static void tx_release(struct tty_struct *tty);
142
143/*
144 * generic HDLC support
145 */
146#define dev_to_port(D) (dev_to_hdlc(D)->priv)
147
148
149/*
150 * device specific structures, macros and functions
151 */
152
153#define SLGT_MAX_PORTS 4
154#define SLGT_REG_SIZE 256
155
156/*
157 * conditional wait facility
158 */
159struct cond_wait {
160 struct cond_wait *next;
161 wait_queue_head_t q;
162 wait_queue_entry_t wait;
163 unsigned int data;
164};
165static void flush_cond_wait(struct cond_wait **head);
166
167/*
168 * DMA buffer descriptor and access macros
169 */
170struct slgt_desc
171{
172 __le16 count;
173 __le16 status;
174 __le32 pbuf; /* physical address of data buffer */
175 __le32 next; /* physical address of next descriptor */
176
177 /* driver book keeping */
178 char *buf; /* virtual address of data buffer */
179 unsigned int pdesc; /* physical address of this descriptor */
180 dma_addr_t buf_dma_addr;
181 unsigned short buf_count;
182};
183
184#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
185#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
186#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
187#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
188#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
189#define desc_count(a) (le16_to_cpu((a).count))
190#define desc_status(a) (le16_to_cpu((a).status))
191#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
192#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
193#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
194#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
195#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
196
197struct _input_signal_events {
198 int ri_up;
199 int ri_down;
200 int dsr_up;
201 int dsr_down;
202 int dcd_up;
203 int dcd_down;
204 int cts_up;
205 int cts_down;
206};
207
208/*
209 * device instance data structure
210 */
211struct slgt_info {
212 void *if_ptr; /* General purpose pointer (used by SPPP) */
213 struct tty_port port;
214
215 struct slgt_info *next_device; /* device list link */
216
217 char device_name[25];
218 struct pci_dev *pdev;
219
220 int port_count; /* count of ports on adapter */
221 int adapter_num; /* adapter instance number */
222 int port_num; /* port instance number */
223
224 /* array of pointers to port contexts on this adapter */
225 struct slgt_info *port_array[SLGT_MAX_PORTS];
226
227 int line; /* tty line instance number */
228
229 struct mgsl_icount icount;
230
231 int timeout;
232 int x_char; /* xon/xoff character */
233 unsigned int read_status_mask;
234 unsigned int ignore_status_mask;
235
236 wait_queue_head_t status_event_wait_q;
237 wait_queue_head_t event_wait_q;
238 struct timer_list tx_timer;
239 struct timer_list rx_timer;
240
241 unsigned int gpio_present;
242 struct cond_wait *gpio_wait_q;
243
244 spinlock_t lock; /* spinlock for synchronizing with ISR */
245
246 struct work_struct task;
247 u32 pending_bh;
248 bool bh_requested;
249 bool bh_running;
250
251 int isr_overflow;
252 bool irq_requested; /* true if IRQ requested */
253 bool irq_occurred; /* for diagnostics use */
254
255 /* device configuration */
256
257 unsigned int bus_type;
258 unsigned int irq_level;
259 unsigned long irq_flags;
260
261 unsigned char __iomem * reg_addr; /* memory mapped registers address */
262 u32 phys_reg_addr;
263 bool reg_addr_requested;
264
265 MGSL_PARAMS params; /* communications parameters */
266 u32 idle_mode;
267 u32 max_frame_size; /* as set by device config */
268
269 unsigned int rbuf_fill_level;
270 unsigned int rx_pio;
271 unsigned int if_mode;
272 unsigned int base_clock;
273 unsigned int xsync;
274 unsigned int xctrl;
275
276 /* device status */
277
278 bool rx_enabled;
279 bool rx_restart;
280
281 bool tx_enabled;
282 bool tx_active;
283
284 unsigned char signals; /* serial signal states */
285 int init_error; /* initialization error */
286
287 unsigned char *tx_buf;
288 int tx_count;
289
290 char *flag_buf;
291 bool drop_rts_on_tx_done;
292 struct _input_signal_events input_signal_events;
293
294 int dcd_chkcount; /* check counts to prevent */
295 int cts_chkcount; /* too many IRQs if a signal */
296 int dsr_chkcount; /* is floating */
297 int ri_chkcount;
298
299 char *bufs; /* virtual address of DMA buffer lists */
300 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
301
302 unsigned int rbuf_count;
303 struct slgt_desc *rbufs;
304 unsigned int rbuf_current;
305 unsigned int rbuf_index;
306 unsigned int rbuf_fill_index;
307 unsigned short rbuf_fill_count;
308
309 unsigned int tbuf_count;
310 struct slgt_desc *tbufs;
311 unsigned int tbuf_current;
312 unsigned int tbuf_start;
313
314 unsigned char *tmp_rbuf;
315 unsigned int tmp_rbuf_count;
316
317 /* SPPP/Cisco HDLC device parts */
318
319 int netcount;
320 spinlock_t netlock;
321#if SYNCLINK_GENERIC_HDLC
322 struct net_device *netdev;
323#endif
324
325};
326
327static MGSL_PARAMS default_params = {
328 .mode = MGSL_MODE_HDLC,
329 .loopback = 0,
330 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
331 .encoding = HDLC_ENCODING_NRZI_SPACE,
332 .clock_speed = 0,
333 .addr_filter = 0xff,
334 .crc_type = HDLC_CRC_16_CCITT,
335 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
336 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
337 .data_rate = 9600,
338 .data_bits = 8,
339 .stop_bits = 1,
340 .parity = ASYNC_PARITY_NONE
341};
342
343
344#define BH_RECEIVE 1
345#define BH_TRANSMIT 2
346#define BH_STATUS 4
347#define IO_PIN_SHUTDOWN_LIMIT 100
348
349#define DMABUFSIZE 256
350#define DESC_LIST_SIZE 4096
351
352#define MASK_PARITY BIT1
353#define MASK_FRAMING BIT0
354#define MASK_BREAK BIT14
355#define MASK_OVERRUN BIT4
356
357#define GSR 0x00 /* global status */
358#define JCR 0x04 /* JTAG control */
359#define IODR 0x08 /* GPIO direction */
360#define IOER 0x0c /* GPIO interrupt enable */
361#define IOVR 0x10 /* GPIO value */
362#define IOSR 0x14 /* GPIO interrupt status */
363#define TDR 0x80 /* tx data */
364#define RDR 0x80 /* rx data */
365#define TCR 0x82 /* tx control */
366#define TIR 0x84 /* tx idle */
367#define TPR 0x85 /* tx preamble */
368#define RCR 0x86 /* rx control */
369#define VCR 0x88 /* V.24 control */
370#define CCR 0x89 /* clock control */
371#define BDR 0x8a /* baud divisor */
372#define SCR 0x8c /* serial control */
373#define SSR 0x8e /* serial status */
374#define RDCSR 0x90 /* rx DMA control/status */
375#define TDCSR 0x94 /* tx DMA control/status */
376#define RDDAR 0x98 /* rx DMA descriptor address */
377#define TDDAR 0x9c /* tx DMA descriptor address */
378#define XSR 0x40 /* extended sync pattern */
379#define XCR 0x44 /* extended control */
380
381#define RXIDLE BIT14
382#define RXBREAK BIT14
383#define IRQ_TXDATA BIT13
384#define IRQ_TXIDLE BIT12
385#define IRQ_TXUNDER BIT11 /* HDLC */
386#define IRQ_RXDATA BIT10
387#define IRQ_RXIDLE BIT9 /* HDLC */
388#define IRQ_RXBREAK BIT9 /* async */
389#define IRQ_RXOVER BIT8
390#define IRQ_DSR BIT7
391#define IRQ_CTS BIT6
392#define IRQ_DCD BIT5
393#define IRQ_RI BIT4
394#define IRQ_ALL 0x3ff0
395#define IRQ_MASTER BIT0
396
397#define slgt_irq_on(info, mask) \
398 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
399#define slgt_irq_off(info, mask) \
400 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
401
402static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
403static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
404static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
405static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
406static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
407static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
408
409static void msc_set_vcr(struct slgt_info *info);
410
411static int startup(struct slgt_info *info);
412static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
413static void shutdown(struct slgt_info *info);
414static void program_hw(struct slgt_info *info);
415static void change_params(struct slgt_info *info);
416
417static int adapter_test(struct slgt_info *info);
418
419static void reset_port(struct slgt_info *info);
420static void async_mode(struct slgt_info *info);
421static void sync_mode(struct slgt_info *info);
422
423static void rx_stop(struct slgt_info *info);
424static void rx_start(struct slgt_info *info);
425static void reset_rbufs(struct slgt_info *info);
426static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
427static bool rx_get_frame(struct slgt_info *info);
428static bool rx_get_buf(struct slgt_info *info);
429
430static void tx_start(struct slgt_info *info);
431static void tx_stop(struct slgt_info *info);
432static void tx_set_idle(struct slgt_info *info);
433static unsigned int tbuf_bytes(struct slgt_info *info);
434static void reset_tbufs(struct slgt_info *info);
435static void tdma_reset(struct slgt_info *info);
436static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
437
438static void get_gtsignals(struct slgt_info *info);
439static void set_gtsignals(struct slgt_info *info);
440static void set_rate(struct slgt_info *info, u32 data_rate);
441
442static void bh_transmit(struct slgt_info *info);
443static void isr_txeom(struct slgt_info *info, unsigned short status);
444
445static void tx_timeout(struct timer_list *t);
446static void rx_timeout(struct timer_list *t);
447
448/*
449 * ioctl handlers
450 */
451static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
452static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
453static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
454static int get_txidle(struct slgt_info *info, int __user *idle_mode);
455static int set_txidle(struct slgt_info *info, int idle_mode);
456static int tx_enable(struct slgt_info *info, int enable);
457static int tx_abort(struct slgt_info *info);
458static int rx_enable(struct slgt_info *info, int enable);
459static int modem_input_wait(struct slgt_info *info,int arg);
460static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
461static int get_interface(struct slgt_info *info, int __user *if_mode);
462static int set_interface(struct slgt_info *info, int if_mode);
463static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
464static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
465static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
466static int get_xsync(struct slgt_info *info, int __user *if_mode);
467static int set_xsync(struct slgt_info *info, int if_mode);
468static int get_xctrl(struct slgt_info *info, int __user *if_mode);
469static int set_xctrl(struct slgt_info *info, int if_mode);
470
471/*
472 * driver functions
473 */
474static void release_resources(struct slgt_info *info);
475
476/*
477 * DEBUG OUTPUT CODE
478 */
479#ifndef DBGINFO
480#define DBGINFO(fmt)
481#endif
482#ifndef DBGERR
483#define DBGERR(fmt)
484#endif
485#ifndef DBGBH
486#define DBGBH(fmt)
487#endif
488#ifndef DBGISR
489#define DBGISR(fmt)
490#endif
491
492#ifdef DBGDATA
493static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
494{
495 int i;
496 int linecount;
497 printk("%s %s data:\n",info->device_name, label);
498 while(count) {
499 linecount = (count > 16) ? 16 : count;
500 for(i=0; i < linecount; i++)
501 printk("%02X ",(unsigned char)data[i]);
502 for(;i<17;i++)
503 printk(" ");
504 for(i=0;i<linecount;i++) {
505 if (data[i]>=040 && data[i]<=0176)
506 printk("%c",data[i]);
507 else
508 printk(".");
509 }
510 printk("\n");
511 data += linecount;
512 count -= linecount;
513 }
514}
515#else
516#define DBGDATA(info, buf, size, label)
517#endif
518
519#ifdef DBGTBUF
520static void dump_tbufs(struct slgt_info *info)
521{
522 int i;
523 printk("tbuf_current=%d\n", info->tbuf_current);
524 for (i=0 ; i < info->tbuf_count ; i++) {
525 printk("%d: count=%04X status=%04X\n",
526 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
527 }
528}
529#else
530#define DBGTBUF(info)
531#endif
532
533#ifdef DBGRBUF
534static void dump_rbufs(struct slgt_info *info)
535{
536 int i;
537 printk("rbuf_current=%d\n", info->rbuf_current);
538 for (i=0 ; i < info->rbuf_count ; i++) {
539 printk("%d: count=%04X status=%04X\n",
540 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
541 }
542}
543#else
544#define DBGRBUF(info)
545#endif
546
547static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
548{
549#ifdef SANITY_CHECK
550 if (!info) {
551 printk("null struct slgt_info for (%s) in %s\n", devname, name);
552 return 1;
553 }
554#else
555 if (!info)
556 return 1;
557#endif
558 return 0;
559}
560
561/*
562 * line discipline callback wrappers
563 *
564 * The wrappers maintain line discipline references
565 * while calling into the line discipline.
566 *
567 * ldisc_receive_buf - pass receive data to line discipline
568 */
569static void ldisc_receive_buf(struct tty_struct *tty,
570 const __u8 *data, char *flags, int count)
571{
572 struct tty_ldisc *ld;
573 if (!tty)
574 return;
575 ld = tty_ldisc_ref(tty);
576 if (ld) {
577 if (ld->ops->receive_buf)
578 ld->ops->receive_buf(tty, data, flags, count);
579 tty_ldisc_deref(ld);
580 }
581}
582
583/* tty callbacks */
584
585static int open(struct tty_struct *tty, struct file *filp)
586{
587 struct slgt_info *info;
588 int retval, line;
589 unsigned long flags;
590
591 line = tty->index;
592 if (line >= slgt_device_count) {
593 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
594 return -ENODEV;
595 }
596
597 info = slgt_device_list;
598 while(info && info->line != line)
599 info = info->next_device;
600 if (sanity_check(info, tty->name, "open"))
601 return -ENODEV;
602 if (info->init_error) {
603 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
604 return -ENODEV;
605 }
606
607 tty->driver_data = info;
608 info->port.tty = tty;
609
610 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
611
612 mutex_lock(&info->port.mutex);
613
614 spin_lock_irqsave(&info->netlock, flags);
615 if (info->netcount) {
616 retval = -EBUSY;
617 spin_unlock_irqrestore(&info->netlock, flags);
618 mutex_unlock(&info->port.mutex);
619 goto cleanup;
620 }
621 info->port.count++;
622 spin_unlock_irqrestore(&info->netlock, flags);
623
624 if (info->port.count == 1) {
625 /* 1st open on this device, init hardware */
626 retval = startup(info);
627 if (retval < 0) {
628 mutex_unlock(&info->port.mutex);
629 goto cleanup;
630 }
631 }
632 mutex_unlock(&info->port.mutex);
633 retval = block_til_ready(tty, filp, info);
634 if (retval) {
635 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
636 goto cleanup;
637 }
638
639 retval = 0;
640
641cleanup:
642 if (retval) {
643 if (tty->count == 1)
644 info->port.tty = NULL; /* tty layer will release tty struct */
645 if(info->port.count)
646 info->port.count--;
647 }
648
649 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
650 return retval;
651}
652
653static void close(struct tty_struct *tty, struct file *filp)
654{
655 struct slgt_info *info = tty->driver_data;
656
657 if (sanity_check(info, tty->name, "close"))
658 return;
659 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
660
661 if (tty_port_close_start(&info->port, tty, filp) == 0)
662 goto cleanup;
663
664 mutex_lock(&info->port.mutex);
665 if (tty_port_initialized(&info->port))
666 wait_until_sent(tty, info->timeout);
667 flush_buffer(tty);
668 tty_ldisc_flush(tty);
669
670 shutdown(info);
671 mutex_unlock(&info->port.mutex);
672
673 tty_port_close_end(&info->port, tty);
674 info->port.tty = NULL;
675cleanup:
676 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
677}
678
679static void hangup(struct tty_struct *tty)
680{
681 struct slgt_info *info = tty->driver_data;
682 unsigned long flags;
683
684 if (sanity_check(info, tty->name, "hangup"))
685 return;
686 DBGINFO(("%s hangup\n", info->device_name));
687
688 flush_buffer(tty);
689
690 mutex_lock(&info->port.mutex);
691 shutdown(info);
692
693 spin_lock_irqsave(&info->port.lock, flags);
694 info->port.count = 0;
695 info->port.tty = NULL;
696 spin_unlock_irqrestore(&info->port.lock, flags);
697 tty_port_set_active(&info->port, 0);
698 mutex_unlock(&info->port.mutex);
699
700 wake_up_interruptible(&info->port.open_wait);
701}
702
703static void set_termios(struct tty_struct *tty,
704 const struct ktermios *old_termios)
705{
706 struct slgt_info *info = tty->driver_data;
707 unsigned long flags;
708
709 DBGINFO(("%s set_termios\n", tty->driver->name));
710
711 change_params(info);
712
713 /* Handle transition to B0 status */
714 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
715 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
716 spin_lock_irqsave(&info->lock,flags);
717 set_gtsignals(info);
718 spin_unlock_irqrestore(&info->lock,flags);
719 }
720
721 /* Handle transition away from B0 status */
722 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
723 info->signals |= SerialSignal_DTR;
724 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
725 info->signals |= SerialSignal_RTS;
726 spin_lock_irqsave(&info->lock,flags);
727 set_gtsignals(info);
728 spin_unlock_irqrestore(&info->lock,flags);
729 }
730
731 /* Handle turning off CRTSCTS */
732 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
733 tty->hw_stopped = 0;
734 tx_release(tty);
735 }
736}
737
738static void update_tx_timer(struct slgt_info *info)
739{
740 /*
741 * use worst case speed of 1200bps to calculate transmit timeout
742 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
743 */
744 if (info->params.mode == MGSL_MODE_HDLC) {
745 int timeout = (tbuf_bytes(info) * 7) + 1000;
746 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
747 }
748}
749
750static int write(struct tty_struct *tty,
751 const unsigned char *buf, int count)
752{
753 int ret = 0;
754 struct slgt_info *info = tty->driver_data;
755 unsigned long flags;
756
757 if (sanity_check(info, tty->name, "write"))
758 return -EIO;
759
760 DBGINFO(("%s write count=%d\n", info->device_name, count));
761
762 if (!info->tx_buf || (count > info->max_frame_size))
763 return -EIO;
764
765 if (!count || tty->flow.stopped || tty->hw_stopped)
766 return 0;
767
768 spin_lock_irqsave(&info->lock, flags);
769
770 if (info->tx_count) {
771 /* send accumulated data from send_char() */
772 if (!tx_load(info, info->tx_buf, info->tx_count))
773 goto cleanup;
774 info->tx_count = 0;
775 }
776
777 if (tx_load(info, buf, count))
778 ret = count;
779
780cleanup:
781 spin_unlock_irqrestore(&info->lock, flags);
782 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
783 return ret;
784}
785
786static int put_char(struct tty_struct *tty, unsigned char ch)
787{
788 struct slgt_info *info = tty->driver_data;
789 unsigned long flags;
790 int ret = 0;
791
792 if (sanity_check(info, tty->name, "put_char"))
793 return 0;
794 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
795 if (!info->tx_buf)
796 return 0;
797 spin_lock_irqsave(&info->lock,flags);
798 if (info->tx_count < info->max_frame_size) {
799 info->tx_buf[info->tx_count++] = ch;
800 ret = 1;
801 }
802 spin_unlock_irqrestore(&info->lock,flags);
803 return ret;
804}
805
806static void send_xchar(struct tty_struct *tty, char ch)
807{
808 struct slgt_info *info = tty->driver_data;
809 unsigned long flags;
810
811 if (sanity_check(info, tty->name, "send_xchar"))
812 return;
813 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
814 info->x_char = ch;
815 if (ch) {
816 spin_lock_irqsave(&info->lock,flags);
817 if (!info->tx_enabled)
818 tx_start(info);
819 spin_unlock_irqrestore(&info->lock,flags);
820 }
821}
822
823static void wait_until_sent(struct tty_struct *tty, int timeout)
824{
825 struct slgt_info *info = tty->driver_data;
826 unsigned long orig_jiffies, char_time;
827
828 if (!info )
829 return;
830 if (sanity_check(info, tty->name, "wait_until_sent"))
831 return;
832 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
833 if (!tty_port_initialized(&info->port))
834 goto exit;
835
836 orig_jiffies = jiffies;
837
838 /* Set check interval to 1/5 of estimated time to
839 * send a character, and make it at least 1. The check
840 * interval should also be less than the timeout.
841 * Note: use tight timings here to satisfy the NIST-PCTS.
842 */
843
844 if (info->params.data_rate) {
845 char_time = info->timeout/(32 * 5);
846 if (!char_time)
847 char_time++;
848 } else
849 char_time = 1;
850
851 if (timeout)
852 char_time = min_t(unsigned long, char_time, timeout);
853
854 while (info->tx_active) {
855 msleep_interruptible(jiffies_to_msecs(char_time));
856 if (signal_pending(current))
857 break;
858 if (timeout && time_after(jiffies, orig_jiffies + timeout))
859 break;
860 }
861exit:
862 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
863}
864
865static unsigned int write_room(struct tty_struct *tty)
866{
867 struct slgt_info *info = tty->driver_data;
868 unsigned int ret;
869
870 if (sanity_check(info, tty->name, "write_room"))
871 return 0;
872 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
873 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
874 return ret;
875}
876
877static void flush_chars(struct tty_struct *tty)
878{
879 struct slgt_info *info = tty->driver_data;
880 unsigned long flags;
881
882 if (sanity_check(info, tty->name, "flush_chars"))
883 return;
884 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
885
886 if (info->tx_count <= 0 || tty->flow.stopped ||
887 tty->hw_stopped || !info->tx_buf)
888 return;
889
890 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
891
892 spin_lock_irqsave(&info->lock,flags);
893 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
894 info->tx_count = 0;
895 spin_unlock_irqrestore(&info->lock,flags);
896}
897
898static void flush_buffer(struct tty_struct *tty)
899{
900 struct slgt_info *info = tty->driver_data;
901 unsigned long flags;
902
903 if (sanity_check(info, tty->name, "flush_buffer"))
904 return;
905 DBGINFO(("%s flush_buffer\n", info->device_name));
906
907 spin_lock_irqsave(&info->lock, flags);
908 info->tx_count = 0;
909 spin_unlock_irqrestore(&info->lock, flags);
910
911 tty_wakeup(tty);
912}
913
914/*
915 * throttle (stop) transmitter
916 */
917static void tx_hold(struct tty_struct *tty)
918{
919 struct slgt_info *info = tty->driver_data;
920 unsigned long flags;
921
922 if (sanity_check(info, tty->name, "tx_hold"))
923 return;
924 DBGINFO(("%s tx_hold\n", info->device_name));
925 spin_lock_irqsave(&info->lock,flags);
926 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
927 tx_stop(info);
928 spin_unlock_irqrestore(&info->lock,flags);
929}
930
931/*
932 * release (start) transmitter
933 */
934static void tx_release(struct tty_struct *tty)
935{
936 struct slgt_info *info = tty->driver_data;
937 unsigned long flags;
938
939 if (sanity_check(info, tty->name, "tx_release"))
940 return;
941 DBGINFO(("%s tx_release\n", info->device_name));
942 spin_lock_irqsave(&info->lock, flags);
943 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
944 info->tx_count = 0;
945 spin_unlock_irqrestore(&info->lock, flags);
946}
947
948/*
949 * Service an IOCTL request
950 *
951 * Arguments
952 *
953 * tty pointer to tty instance data
954 * cmd IOCTL command code
955 * arg command argument/context
956 *
957 * Return 0 if success, otherwise error code
958 */
959static int ioctl(struct tty_struct *tty,
960 unsigned int cmd, unsigned long arg)
961{
962 struct slgt_info *info = tty->driver_data;
963 void __user *argp = (void __user *)arg;
964 int ret;
965
966 if (sanity_check(info, tty->name, "ioctl"))
967 return -ENODEV;
968 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
969
970 if (cmd != TIOCMIWAIT) {
971 if (tty_io_error(tty))
972 return -EIO;
973 }
974
975 switch (cmd) {
976 case MGSL_IOCWAITEVENT:
977 return wait_mgsl_event(info, argp);
978 case TIOCMIWAIT:
979 return modem_input_wait(info,(int)arg);
980 case MGSL_IOCSGPIO:
981 return set_gpio(info, argp);
982 case MGSL_IOCGGPIO:
983 return get_gpio(info, argp);
984 case MGSL_IOCWAITGPIO:
985 return wait_gpio(info, argp);
986 case MGSL_IOCGXSYNC:
987 return get_xsync(info, argp);
988 case MGSL_IOCSXSYNC:
989 return set_xsync(info, (int)arg);
990 case MGSL_IOCGXCTRL:
991 return get_xctrl(info, argp);
992 case MGSL_IOCSXCTRL:
993 return set_xctrl(info, (int)arg);
994 }
995 mutex_lock(&info->port.mutex);
996 switch (cmd) {
997 case MGSL_IOCGPARAMS:
998 ret = get_params(info, argp);
999 break;
1000 case MGSL_IOCSPARAMS:
1001 ret = set_params(info, argp);
1002 break;
1003 case MGSL_IOCGTXIDLE:
1004 ret = get_txidle(info, argp);
1005 break;
1006 case MGSL_IOCSTXIDLE:
1007 ret = set_txidle(info, (int)arg);
1008 break;
1009 case MGSL_IOCTXENABLE:
1010 ret = tx_enable(info, (int)arg);
1011 break;
1012 case MGSL_IOCRXENABLE:
1013 ret = rx_enable(info, (int)arg);
1014 break;
1015 case MGSL_IOCTXABORT:
1016 ret = tx_abort(info);
1017 break;
1018 case MGSL_IOCGSTATS:
1019 ret = get_stats(info, argp);
1020 break;
1021 case MGSL_IOCGIF:
1022 ret = get_interface(info, argp);
1023 break;
1024 case MGSL_IOCSIF:
1025 ret = set_interface(info,(int)arg);
1026 break;
1027 default:
1028 ret = -ENOIOCTLCMD;
1029 }
1030 mutex_unlock(&info->port.mutex);
1031 return ret;
1032}
1033
1034static int get_icount(struct tty_struct *tty,
1035 struct serial_icounter_struct *icount)
1036
1037{
1038 struct slgt_info *info = tty->driver_data;
1039 struct mgsl_icount cnow; /* kernel counter temps */
1040 unsigned long flags;
1041
1042 spin_lock_irqsave(&info->lock,flags);
1043 cnow = info->icount;
1044 spin_unlock_irqrestore(&info->lock,flags);
1045
1046 icount->cts = cnow.cts;
1047 icount->dsr = cnow.dsr;
1048 icount->rng = cnow.rng;
1049 icount->dcd = cnow.dcd;
1050 icount->rx = cnow.rx;
1051 icount->tx = cnow.tx;
1052 icount->frame = cnow.frame;
1053 icount->overrun = cnow.overrun;
1054 icount->parity = cnow.parity;
1055 icount->brk = cnow.brk;
1056 icount->buf_overrun = cnow.buf_overrun;
1057
1058 return 0;
1059}
1060
1061/*
1062 * support for 32 bit ioctl calls on 64 bit systems
1063 */
1064#ifdef CONFIG_COMPAT
1065static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1066{
1067 struct MGSL_PARAMS32 tmp_params;
1068
1069 DBGINFO(("%s get_params32\n", info->device_name));
1070 memset(&tmp_params, 0, sizeof(tmp_params));
1071 tmp_params.mode = (compat_ulong_t)info->params.mode;
1072 tmp_params.loopback = info->params.loopback;
1073 tmp_params.flags = info->params.flags;
1074 tmp_params.encoding = info->params.encoding;
1075 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1076 tmp_params.addr_filter = info->params.addr_filter;
1077 tmp_params.crc_type = info->params.crc_type;
1078 tmp_params.preamble_length = info->params.preamble_length;
1079 tmp_params.preamble = info->params.preamble;
1080 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1081 tmp_params.data_bits = info->params.data_bits;
1082 tmp_params.stop_bits = info->params.stop_bits;
1083 tmp_params.parity = info->params.parity;
1084 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1085 return -EFAULT;
1086 return 0;
1087}
1088
1089static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1090{
1091 struct MGSL_PARAMS32 tmp_params;
1092
1093 DBGINFO(("%s set_params32\n", info->device_name));
1094 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1095 return -EFAULT;
1096
1097 spin_lock(&info->lock);
1098 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1099 info->base_clock = tmp_params.clock_speed;
1100 } else {
1101 info->params.mode = tmp_params.mode;
1102 info->params.loopback = tmp_params.loopback;
1103 info->params.flags = tmp_params.flags;
1104 info->params.encoding = tmp_params.encoding;
1105 info->params.clock_speed = tmp_params.clock_speed;
1106 info->params.addr_filter = tmp_params.addr_filter;
1107 info->params.crc_type = tmp_params.crc_type;
1108 info->params.preamble_length = tmp_params.preamble_length;
1109 info->params.preamble = tmp_params.preamble;
1110 info->params.data_rate = tmp_params.data_rate;
1111 info->params.data_bits = tmp_params.data_bits;
1112 info->params.stop_bits = tmp_params.stop_bits;
1113 info->params.parity = tmp_params.parity;
1114 }
1115 spin_unlock(&info->lock);
1116
1117 program_hw(info);
1118
1119 return 0;
1120}
1121
1122static long slgt_compat_ioctl(struct tty_struct *tty,
1123 unsigned int cmd, unsigned long arg)
1124{
1125 struct slgt_info *info = tty->driver_data;
1126 int rc;
1127
1128 if (sanity_check(info, tty->name, "compat_ioctl"))
1129 return -ENODEV;
1130 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1131
1132 switch (cmd) {
1133 case MGSL_IOCSPARAMS32:
1134 rc = set_params32(info, compat_ptr(arg));
1135 break;
1136
1137 case MGSL_IOCGPARAMS32:
1138 rc = get_params32(info, compat_ptr(arg));
1139 break;
1140
1141 case MGSL_IOCGPARAMS:
1142 case MGSL_IOCSPARAMS:
1143 case MGSL_IOCGTXIDLE:
1144 case MGSL_IOCGSTATS:
1145 case MGSL_IOCWAITEVENT:
1146 case MGSL_IOCGIF:
1147 case MGSL_IOCSGPIO:
1148 case MGSL_IOCGGPIO:
1149 case MGSL_IOCWAITGPIO:
1150 case MGSL_IOCGXSYNC:
1151 case MGSL_IOCGXCTRL:
1152 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1153 break;
1154 default:
1155 rc = ioctl(tty, cmd, arg);
1156 }
1157 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1158 return rc;
1159}
1160#else
1161#define slgt_compat_ioctl NULL
1162#endif /* ifdef CONFIG_COMPAT */
1163
1164/*
1165 * proc fs support
1166 */
1167static inline void line_info(struct seq_file *m, struct slgt_info *info)
1168{
1169 char stat_buf[30];
1170 unsigned long flags;
1171
1172 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1173 info->device_name, info->phys_reg_addr,
1174 info->irq_level, info->max_frame_size);
1175
1176 /* output current serial signal states */
1177 spin_lock_irqsave(&info->lock,flags);
1178 get_gtsignals(info);
1179 spin_unlock_irqrestore(&info->lock,flags);
1180
1181 stat_buf[0] = 0;
1182 stat_buf[1] = 0;
1183 if (info->signals & SerialSignal_RTS)
1184 strcat(stat_buf, "|RTS");
1185 if (info->signals & SerialSignal_CTS)
1186 strcat(stat_buf, "|CTS");
1187 if (info->signals & SerialSignal_DTR)
1188 strcat(stat_buf, "|DTR");
1189 if (info->signals & SerialSignal_DSR)
1190 strcat(stat_buf, "|DSR");
1191 if (info->signals & SerialSignal_DCD)
1192 strcat(stat_buf, "|CD");
1193 if (info->signals & SerialSignal_RI)
1194 strcat(stat_buf, "|RI");
1195
1196 if (info->params.mode != MGSL_MODE_ASYNC) {
1197 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1198 info->icount.txok, info->icount.rxok);
1199 if (info->icount.txunder)
1200 seq_printf(m, " txunder:%d", info->icount.txunder);
1201 if (info->icount.txabort)
1202 seq_printf(m, " txabort:%d", info->icount.txabort);
1203 if (info->icount.rxshort)
1204 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1205 if (info->icount.rxlong)
1206 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1207 if (info->icount.rxover)
1208 seq_printf(m, " rxover:%d", info->icount.rxover);
1209 if (info->icount.rxcrc)
1210 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1211 } else {
1212 seq_printf(m, "\tASYNC tx:%d rx:%d",
1213 info->icount.tx, info->icount.rx);
1214 if (info->icount.frame)
1215 seq_printf(m, " fe:%d", info->icount.frame);
1216 if (info->icount.parity)
1217 seq_printf(m, " pe:%d", info->icount.parity);
1218 if (info->icount.brk)
1219 seq_printf(m, " brk:%d", info->icount.brk);
1220 if (info->icount.overrun)
1221 seq_printf(m, " oe:%d", info->icount.overrun);
1222 }
1223
1224 /* Append serial signal status to end */
1225 seq_printf(m, " %s\n", stat_buf+1);
1226
1227 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1228 info->tx_active,info->bh_requested,info->bh_running,
1229 info->pending_bh);
1230}
1231
1232/* Called to print information about devices
1233 */
1234static int synclink_gt_proc_show(struct seq_file *m, void *v)
1235{
1236 struct slgt_info *info;
1237
1238 seq_puts(m, "synclink_gt driver\n");
1239
1240 info = slgt_device_list;
1241 while( info ) {
1242 line_info(m, info);
1243 info = info->next_device;
1244 }
1245 return 0;
1246}
1247
1248/*
1249 * return count of bytes in transmit buffer
1250 */
1251static unsigned int chars_in_buffer(struct tty_struct *tty)
1252{
1253 struct slgt_info *info = tty->driver_data;
1254 unsigned int count;
1255 if (sanity_check(info, tty->name, "chars_in_buffer"))
1256 return 0;
1257 count = tbuf_bytes(info);
1258 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1259 return count;
1260}
1261
1262/*
1263 * signal remote device to throttle send data (our receive data)
1264 */
1265static void throttle(struct tty_struct * tty)
1266{
1267 struct slgt_info *info = tty->driver_data;
1268 unsigned long flags;
1269
1270 if (sanity_check(info, tty->name, "throttle"))
1271 return;
1272 DBGINFO(("%s throttle\n", info->device_name));
1273 if (I_IXOFF(tty))
1274 send_xchar(tty, STOP_CHAR(tty));
1275 if (C_CRTSCTS(tty)) {
1276 spin_lock_irqsave(&info->lock,flags);
1277 info->signals &= ~SerialSignal_RTS;
1278 set_gtsignals(info);
1279 spin_unlock_irqrestore(&info->lock,flags);
1280 }
1281}
1282
1283/*
1284 * signal remote device to stop throttling send data (our receive data)
1285 */
1286static void unthrottle(struct tty_struct * tty)
1287{
1288 struct slgt_info *info = tty->driver_data;
1289 unsigned long flags;
1290
1291 if (sanity_check(info, tty->name, "unthrottle"))
1292 return;
1293 DBGINFO(("%s unthrottle\n", info->device_name));
1294 if (I_IXOFF(tty)) {
1295 if (info->x_char)
1296 info->x_char = 0;
1297 else
1298 send_xchar(tty, START_CHAR(tty));
1299 }
1300 if (C_CRTSCTS(tty)) {
1301 spin_lock_irqsave(&info->lock,flags);
1302 info->signals |= SerialSignal_RTS;
1303 set_gtsignals(info);
1304 spin_unlock_irqrestore(&info->lock,flags);
1305 }
1306}
1307
1308/*
1309 * set or clear transmit break condition
1310 * break_state -1=set break condition, 0=clear
1311 */
1312static int set_break(struct tty_struct *tty, int break_state)
1313{
1314 struct slgt_info *info = tty->driver_data;
1315 unsigned short value;
1316 unsigned long flags;
1317
1318 if (sanity_check(info, tty->name, "set_break"))
1319 return -EINVAL;
1320 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1321
1322 spin_lock_irqsave(&info->lock,flags);
1323 value = rd_reg16(info, TCR);
1324 if (break_state == -1)
1325 value |= BIT6;
1326 else
1327 value &= ~BIT6;
1328 wr_reg16(info, TCR, value);
1329 spin_unlock_irqrestore(&info->lock,flags);
1330 return 0;
1331}
1332
1333#if SYNCLINK_GENERIC_HDLC
1334
1335/**
1336 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1337 * @dev: pointer to network device structure
1338 * @encoding: serial encoding setting
1339 * @parity: FCS setting
1340 *
1341 * Set encoding and frame check sequence (FCS) options.
1342 *
1343 * Return: 0 if success, otherwise error code
1344 */
1345static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1346 unsigned short parity)
1347{
1348 struct slgt_info *info = dev_to_port(dev);
1349 unsigned char new_encoding;
1350 unsigned short new_crctype;
1351
1352 /* return error if TTY interface open */
1353 if (info->port.count)
1354 return -EBUSY;
1355
1356 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1357
1358 switch (encoding)
1359 {
1360 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1361 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1362 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1363 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1364 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1365 default: return -EINVAL;
1366 }
1367
1368 switch (parity)
1369 {
1370 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1371 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1372 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1373 default: return -EINVAL;
1374 }
1375
1376 info->params.encoding = new_encoding;
1377 info->params.crc_type = new_crctype;
1378
1379 /* if network interface up, reprogram hardware */
1380 if (info->netcount)
1381 program_hw(info);
1382
1383 return 0;
1384}
1385
1386/**
1387 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1388 * @skb: socket buffer containing HDLC frame
1389 * @dev: pointer to network device structure
1390 */
1391static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1392 struct net_device *dev)
1393{
1394 struct slgt_info *info = dev_to_port(dev);
1395 unsigned long flags;
1396
1397 DBGINFO(("%s hdlc_xmit\n", dev->name));
1398
1399 if (!skb->len)
1400 return NETDEV_TX_OK;
1401
1402 /* stop sending until this frame completes */
1403 netif_stop_queue(dev);
1404
1405 /* update network statistics */
1406 dev->stats.tx_packets++;
1407 dev->stats.tx_bytes += skb->len;
1408
1409 /* save start time for transmit timeout detection */
1410 netif_trans_update(dev);
1411
1412 spin_lock_irqsave(&info->lock, flags);
1413 tx_load(info, skb->data, skb->len);
1414 spin_unlock_irqrestore(&info->lock, flags);
1415
1416 /* done with socket buffer, so free it */
1417 dev_kfree_skb(skb);
1418
1419 return NETDEV_TX_OK;
1420}
1421
1422/**
1423 * hdlcdev_open - called by network layer when interface enabled
1424 * @dev: pointer to network device structure
1425 *
1426 * Claim resources and initialize hardware.
1427 *
1428 * Return: 0 if success, otherwise error code
1429 */
1430static int hdlcdev_open(struct net_device *dev)
1431{
1432 struct slgt_info *info = dev_to_port(dev);
1433 int rc;
1434 unsigned long flags;
1435
1436 DBGINFO(("%s hdlcdev_open\n", dev->name));
1437
1438 /* arbitrate between network and tty opens */
1439 spin_lock_irqsave(&info->netlock, flags);
1440 if (info->port.count != 0 || info->netcount != 0) {
1441 DBGINFO(("%s hdlc_open busy\n", dev->name));
1442 spin_unlock_irqrestore(&info->netlock, flags);
1443 return -EBUSY;
1444 }
1445 info->netcount=1;
1446 spin_unlock_irqrestore(&info->netlock, flags);
1447
1448 /* claim resources and init adapter */
1449 if ((rc = startup(info)) != 0) {
1450 spin_lock_irqsave(&info->netlock, flags);
1451 info->netcount=0;
1452 spin_unlock_irqrestore(&info->netlock, flags);
1453 return rc;
1454 }
1455
1456 /* generic HDLC layer open processing */
1457 rc = hdlc_open(dev);
1458 if (rc) {
1459 shutdown(info);
1460 spin_lock_irqsave(&info->netlock, flags);
1461 info->netcount = 0;
1462 spin_unlock_irqrestore(&info->netlock, flags);
1463 return rc;
1464 }
1465
1466 /* assert RTS and DTR, apply hardware settings */
1467 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1468 program_hw(info);
1469
1470 /* enable network layer transmit */
1471 netif_trans_update(dev);
1472 netif_start_queue(dev);
1473
1474 /* inform generic HDLC layer of current DCD status */
1475 spin_lock_irqsave(&info->lock, flags);
1476 get_gtsignals(info);
1477 spin_unlock_irqrestore(&info->lock, flags);
1478 if (info->signals & SerialSignal_DCD)
1479 netif_carrier_on(dev);
1480 else
1481 netif_carrier_off(dev);
1482 return 0;
1483}
1484
1485/**
1486 * hdlcdev_close - called by network layer when interface is disabled
1487 * @dev: pointer to network device structure
1488 *
1489 * Shutdown hardware and release resources.
1490 *
1491 * Return: 0 if success, otherwise error code
1492 */
1493static int hdlcdev_close(struct net_device *dev)
1494{
1495 struct slgt_info *info = dev_to_port(dev);
1496 unsigned long flags;
1497
1498 DBGINFO(("%s hdlcdev_close\n", dev->name));
1499
1500 netif_stop_queue(dev);
1501
1502 /* shutdown adapter and release resources */
1503 shutdown(info);
1504
1505 hdlc_close(dev);
1506
1507 spin_lock_irqsave(&info->netlock, flags);
1508 info->netcount=0;
1509 spin_unlock_irqrestore(&info->netlock, flags);
1510
1511 return 0;
1512}
1513
1514/**
1515 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1516 * @dev: pointer to network device structure
1517 * @ifr: pointer to network interface request structure
1518 * @cmd: IOCTL command code
1519 *
1520 * Return: 0 if success, otherwise error code
1521 */
1522static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1523{
1524 const size_t size = sizeof(sync_serial_settings);
1525 sync_serial_settings new_line;
1526 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1527 struct slgt_info *info = dev_to_port(dev);
1528 unsigned int flags;
1529
1530 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1531
1532 /* return error if TTY interface open */
1533 if (info->port.count)
1534 return -EBUSY;
1535
1536 memset(&new_line, 0, sizeof(new_line));
1537
1538 switch (ifs->type) {
1539 case IF_GET_IFACE: /* return current sync_serial_settings */
1540
1541 ifs->type = IF_IFACE_SYNC_SERIAL;
1542 if (ifs->size < size) {
1543 ifs->size = size; /* data size wanted */
1544 return -ENOBUFS;
1545 }
1546
1547 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1548 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1549 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1550 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1551
1552 switch (flags){
1553 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1554 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1555 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1556 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1557 default: new_line.clock_type = CLOCK_DEFAULT;
1558 }
1559
1560 new_line.clock_rate = info->params.clock_speed;
1561 new_line.loopback = info->params.loopback ? 1:0;
1562
1563 if (copy_to_user(line, &new_line, size))
1564 return -EFAULT;
1565 return 0;
1566
1567 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1568
1569 if(!capable(CAP_NET_ADMIN))
1570 return -EPERM;
1571 if (copy_from_user(&new_line, line, size))
1572 return -EFAULT;
1573
1574 switch (new_line.clock_type)
1575 {
1576 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1577 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1578 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1579 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1580 case CLOCK_DEFAULT: flags = info->params.flags &
1581 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1582 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1583 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1584 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1585 default: return -EINVAL;
1586 }
1587
1588 if (new_line.loopback != 0 && new_line.loopback != 1)
1589 return -EINVAL;
1590
1591 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1592 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1593 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1594 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1595 info->params.flags |= flags;
1596
1597 info->params.loopback = new_line.loopback;
1598
1599 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1600 info->params.clock_speed = new_line.clock_rate;
1601 else
1602 info->params.clock_speed = 0;
1603
1604 /* if network interface up, reprogram hardware */
1605 if (info->netcount)
1606 program_hw(info);
1607 return 0;
1608
1609 default:
1610 return hdlc_ioctl(dev, ifs);
1611 }
1612}
1613
1614/**
1615 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1616 * @dev: pointer to network device structure
1617 * @txqueue: unused
1618 */
1619static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1620{
1621 struct slgt_info *info = dev_to_port(dev);
1622 unsigned long flags;
1623
1624 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1625
1626 dev->stats.tx_errors++;
1627 dev->stats.tx_aborted_errors++;
1628
1629 spin_lock_irqsave(&info->lock,flags);
1630 tx_stop(info);
1631 spin_unlock_irqrestore(&info->lock,flags);
1632
1633 netif_wake_queue(dev);
1634}
1635
1636/**
1637 * hdlcdev_tx_done - called by device driver when transmit completes
1638 * @info: pointer to device instance information
1639 *
1640 * Reenable network layer transmit if stopped.
1641 */
1642static void hdlcdev_tx_done(struct slgt_info *info)
1643{
1644 if (netif_queue_stopped(info->netdev))
1645 netif_wake_queue(info->netdev);
1646}
1647
1648/**
1649 * hdlcdev_rx - called by device driver when frame received
1650 * @info: pointer to device instance information
1651 * @buf: pointer to buffer contianing frame data
1652 * @size: count of data bytes in buf
1653 *
1654 * Pass frame to network layer.
1655 */
1656static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1657{
1658 struct sk_buff *skb = dev_alloc_skb(size);
1659 struct net_device *dev = info->netdev;
1660
1661 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1662
1663 if (skb == NULL) {
1664 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1665 dev->stats.rx_dropped++;
1666 return;
1667 }
1668
1669 skb_put_data(skb, buf, size);
1670
1671 skb->protocol = hdlc_type_trans(skb, dev);
1672
1673 dev->stats.rx_packets++;
1674 dev->stats.rx_bytes += size;
1675
1676 netif_rx(skb);
1677}
1678
1679static const struct net_device_ops hdlcdev_ops = {
1680 .ndo_open = hdlcdev_open,
1681 .ndo_stop = hdlcdev_close,
1682 .ndo_start_xmit = hdlc_start_xmit,
1683 .ndo_siocwandev = hdlcdev_ioctl,
1684 .ndo_tx_timeout = hdlcdev_tx_timeout,
1685};
1686
1687/**
1688 * hdlcdev_init - called by device driver when adding device instance
1689 * @info: pointer to device instance information
1690 *
1691 * Do generic HDLC initialization.
1692 *
1693 * Return: 0 if success, otherwise error code
1694 */
1695static int hdlcdev_init(struct slgt_info *info)
1696{
1697 int rc;
1698 struct net_device *dev;
1699 hdlc_device *hdlc;
1700
1701 /* allocate and initialize network and HDLC layer objects */
1702
1703 dev = alloc_hdlcdev(info);
1704 if (!dev) {
1705 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1706 return -ENOMEM;
1707 }
1708
1709 /* for network layer reporting purposes only */
1710 dev->mem_start = info->phys_reg_addr;
1711 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1712 dev->irq = info->irq_level;
1713
1714 /* network layer callbacks and settings */
1715 dev->netdev_ops = &hdlcdev_ops;
1716 dev->watchdog_timeo = 10 * HZ;
1717 dev->tx_queue_len = 50;
1718
1719 /* generic HDLC layer callbacks and settings */
1720 hdlc = dev_to_hdlc(dev);
1721 hdlc->attach = hdlcdev_attach;
1722 hdlc->xmit = hdlcdev_xmit;
1723
1724 /* register objects with HDLC layer */
1725 rc = register_hdlc_device(dev);
1726 if (rc) {
1727 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1728 free_netdev(dev);
1729 return rc;
1730 }
1731
1732 info->netdev = dev;
1733 return 0;
1734}
1735
1736/**
1737 * hdlcdev_exit - called by device driver when removing device instance
1738 * @info: pointer to device instance information
1739 *
1740 * Do generic HDLC cleanup.
1741 */
1742static void hdlcdev_exit(struct slgt_info *info)
1743{
1744 if (!info->netdev)
1745 return;
1746 unregister_hdlc_device(info->netdev);
1747 free_netdev(info->netdev);
1748 info->netdev = NULL;
1749}
1750
1751#endif /* ifdef CONFIG_HDLC */
1752
1753/*
1754 * get async data from rx DMA buffers
1755 */
1756static void rx_async(struct slgt_info *info)
1757{
1758 struct mgsl_icount *icount = &info->icount;
1759 unsigned int start, end;
1760 unsigned char *p;
1761 unsigned char status;
1762 struct slgt_desc *bufs = info->rbufs;
1763 int i, count;
1764 int chars = 0;
1765 int stat;
1766 unsigned char ch;
1767
1768 start = end = info->rbuf_current;
1769
1770 while(desc_complete(bufs[end])) {
1771 count = desc_count(bufs[end]) - info->rbuf_index;
1772 p = bufs[end].buf + info->rbuf_index;
1773
1774 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1775 DBGDATA(info, p, count, "rx");
1776
1777 for(i=0 ; i < count; i+=2, p+=2) {
1778 ch = *p;
1779 icount->rx++;
1780
1781 stat = 0;
1782
1783 status = *(p + 1) & (BIT1 + BIT0);
1784 if (status) {
1785 if (status & BIT1)
1786 icount->parity++;
1787 else if (status & BIT0)
1788 icount->frame++;
1789 /* discard char if tty control flags say so */
1790 if (status & info->ignore_status_mask)
1791 continue;
1792 if (status & BIT1)
1793 stat = TTY_PARITY;
1794 else if (status & BIT0)
1795 stat = TTY_FRAME;
1796 }
1797 tty_insert_flip_char(&info->port, ch, stat);
1798 chars++;
1799 }
1800
1801 if (i < count) {
1802 /* receive buffer not completed */
1803 info->rbuf_index += i;
1804 mod_timer(&info->rx_timer, jiffies + 1);
1805 break;
1806 }
1807
1808 info->rbuf_index = 0;
1809 free_rbufs(info, end, end);
1810
1811 if (++end == info->rbuf_count)
1812 end = 0;
1813
1814 /* if entire list searched then no frame available */
1815 if (end == start)
1816 break;
1817 }
1818
1819 if (chars)
1820 tty_flip_buffer_push(&info->port);
1821}
1822
1823/*
1824 * return next bottom half action to perform
1825 */
1826static int bh_action(struct slgt_info *info)
1827{
1828 unsigned long flags;
1829 int rc;
1830
1831 spin_lock_irqsave(&info->lock,flags);
1832
1833 if (info->pending_bh & BH_RECEIVE) {
1834 info->pending_bh &= ~BH_RECEIVE;
1835 rc = BH_RECEIVE;
1836 } else if (info->pending_bh & BH_TRANSMIT) {
1837 info->pending_bh &= ~BH_TRANSMIT;
1838 rc = BH_TRANSMIT;
1839 } else if (info->pending_bh & BH_STATUS) {
1840 info->pending_bh &= ~BH_STATUS;
1841 rc = BH_STATUS;
1842 } else {
1843 /* Mark BH routine as complete */
1844 info->bh_running = false;
1845 info->bh_requested = false;
1846 rc = 0;
1847 }
1848
1849 spin_unlock_irqrestore(&info->lock,flags);
1850
1851 return rc;
1852}
1853
1854/*
1855 * perform bottom half processing
1856 */
1857static void bh_handler(struct work_struct *work)
1858{
1859 struct slgt_info *info = container_of(work, struct slgt_info, task);
1860 int action;
1861
1862 info->bh_running = true;
1863
1864 while((action = bh_action(info))) {
1865 switch (action) {
1866 case BH_RECEIVE:
1867 DBGBH(("%s bh receive\n", info->device_name));
1868 switch(info->params.mode) {
1869 case MGSL_MODE_ASYNC:
1870 rx_async(info);
1871 break;
1872 case MGSL_MODE_HDLC:
1873 while(rx_get_frame(info));
1874 break;
1875 case MGSL_MODE_RAW:
1876 case MGSL_MODE_MONOSYNC:
1877 case MGSL_MODE_BISYNC:
1878 case MGSL_MODE_XSYNC:
1879 while(rx_get_buf(info));
1880 break;
1881 }
1882 /* restart receiver if rx DMA buffers exhausted */
1883 if (info->rx_restart)
1884 rx_start(info);
1885 break;
1886 case BH_TRANSMIT:
1887 bh_transmit(info);
1888 break;
1889 case BH_STATUS:
1890 DBGBH(("%s bh status\n", info->device_name));
1891 info->ri_chkcount = 0;
1892 info->dsr_chkcount = 0;
1893 info->dcd_chkcount = 0;
1894 info->cts_chkcount = 0;
1895 break;
1896 default:
1897 DBGBH(("%s unknown action\n", info->device_name));
1898 break;
1899 }
1900 }
1901 DBGBH(("%s bh_handler exit\n", info->device_name));
1902}
1903
1904static void bh_transmit(struct slgt_info *info)
1905{
1906 struct tty_struct *tty = info->port.tty;
1907
1908 DBGBH(("%s bh_transmit\n", info->device_name));
1909 if (tty)
1910 tty_wakeup(tty);
1911}
1912
1913static void dsr_change(struct slgt_info *info, unsigned short status)
1914{
1915 if (status & BIT3) {
1916 info->signals |= SerialSignal_DSR;
1917 info->input_signal_events.dsr_up++;
1918 } else {
1919 info->signals &= ~SerialSignal_DSR;
1920 info->input_signal_events.dsr_down++;
1921 }
1922 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1923 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1924 slgt_irq_off(info, IRQ_DSR);
1925 return;
1926 }
1927 info->icount.dsr++;
1928 wake_up_interruptible(&info->status_event_wait_q);
1929 wake_up_interruptible(&info->event_wait_q);
1930 info->pending_bh |= BH_STATUS;
1931}
1932
1933static void cts_change(struct slgt_info *info, unsigned short status)
1934{
1935 if (status & BIT2) {
1936 info->signals |= SerialSignal_CTS;
1937 info->input_signal_events.cts_up++;
1938 } else {
1939 info->signals &= ~SerialSignal_CTS;
1940 info->input_signal_events.cts_down++;
1941 }
1942 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1943 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1944 slgt_irq_off(info, IRQ_CTS);
1945 return;
1946 }
1947 info->icount.cts++;
1948 wake_up_interruptible(&info->status_event_wait_q);
1949 wake_up_interruptible(&info->event_wait_q);
1950 info->pending_bh |= BH_STATUS;
1951
1952 if (tty_port_cts_enabled(&info->port)) {
1953 if (info->port.tty) {
1954 if (info->port.tty->hw_stopped) {
1955 if (info->signals & SerialSignal_CTS) {
1956 info->port.tty->hw_stopped = 0;
1957 info->pending_bh |= BH_TRANSMIT;
1958 return;
1959 }
1960 } else {
1961 if (!(info->signals & SerialSignal_CTS))
1962 info->port.tty->hw_stopped = 1;
1963 }
1964 }
1965 }
1966}
1967
1968static void dcd_change(struct slgt_info *info, unsigned short status)
1969{
1970 if (status & BIT1) {
1971 info->signals |= SerialSignal_DCD;
1972 info->input_signal_events.dcd_up++;
1973 } else {
1974 info->signals &= ~SerialSignal_DCD;
1975 info->input_signal_events.dcd_down++;
1976 }
1977 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1978 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1979 slgt_irq_off(info, IRQ_DCD);
1980 return;
1981 }
1982 info->icount.dcd++;
1983#if SYNCLINK_GENERIC_HDLC
1984 if (info->netcount) {
1985 if (info->signals & SerialSignal_DCD)
1986 netif_carrier_on(info->netdev);
1987 else
1988 netif_carrier_off(info->netdev);
1989 }
1990#endif
1991 wake_up_interruptible(&info->status_event_wait_q);
1992 wake_up_interruptible(&info->event_wait_q);
1993 info->pending_bh |= BH_STATUS;
1994
1995 if (tty_port_check_carrier(&info->port)) {
1996 if (info->signals & SerialSignal_DCD)
1997 wake_up_interruptible(&info->port.open_wait);
1998 else {
1999 if (info->port.tty)
2000 tty_hangup(info->port.tty);
2001 }
2002 }
2003}
2004
2005static void ri_change(struct slgt_info *info, unsigned short status)
2006{
2007 if (status & BIT0) {
2008 info->signals |= SerialSignal_RI;
2009 info->input_signal_events.ri_up++;
2010 } else {
2011 info->signals &= ~SerialSignal_RI;
2012 info->input_signal_events.ri_down++;
2013 }
2014 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2015 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2016 slgt_irq_off(info, IRQ_RI);
2017 return;
2018 }
2019 info->icount.rng++;
2020 wake_up_interruptible(&info->status_event_wait_q);
2021 wake_up_interruptible(&info->event_wait_q);
2022 info->pending_bh |= BH_STATUS;
2023}
2024
2025static void isr_rxdata(struct slgt_info *info)
2026{
2027 unsigned int count = info->rbuf_fill_count;
2028 unsigned int i = info->rbuf_fill_index;
2029 unsigned short reg;
2030
2031 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2032 reg = rd_reg16(info, RDR);
2033 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2034 if (desc_complete(info->rbufs[i])) {
2035 /* all buffers full */
2036 rx_stop(info);
2037 info->rx_restart = true;
2038 continue;
2039 }
2040 info->rbufs[i].buf[count++] = (unsigned char)reg;
2041 /* async mode saves status byte to buffer for each data byte */
2042 if (info->params.mode == MGSL_MODE_ASYNC)
2043 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2044 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2045 /* buffer full or end of frame */
2046 set_desc_count(info->rbufs[i], count);
2047 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2048 info->rbuf_fill_count = count = 0;
2049 if (++i == info->rbuf_count)
2050 i = 0;
2051 info->pending_bh |= BH_RECEIVE;
2052 }
2053 }
2054
2055 info->rbuf_fill_index = i;
2056 info->rbuf_fill_count = count;
2057}
2058
2059static void isr_serial(struct slgt_info *info)
2060{
2061 unsigned short status = rd_reg16(info, SSR);
2062
2063 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2064
2065 wr_reg16(info, SSR, status); /* clear pending */
2066
2067 info->irq_occurred = true;
2068
2069 if (info->params.mode == MGSL_MODE_ASYNC) {
2070 if (status & IRQ_TXIDLE) {
2071 if (info->tx_active)
2072 isr_txeom(info, status);
2073 }
2074 if (info->rx_pio && (status & IRQ_RXDATA))
2075 isr_rxdata(info);
2076 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2077 info->icount.brk++;
2078 /* process break detection if tty control allows */
2079 if (info->port.tty) {
2080 if (!(status & info->ignore_status_mask)) {
2081 if (info->read_status_mask & MASK_BREAK) {
2082 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2083 if (info->port.flags & ASYNC_SAK)
2084 do_SAK(info->port.tty);
2085 }
2086 }
2087 }
2088 }
2089 } else {
2090 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2091 isr_txeom(info, status);
2092 if (info->rx_pio && (status & IRQ_RXDATA))
2093 isr_rxdata(info);
2094 if (status & IRQ_RXIDLE) {
2095 if (status & RXIDLE)
2096 info->icount.rxidle++;
2097 else
2098 info->icount.exithunt++;
2099 wake_up_interruptible(&info->event_wait_q);
2100 }
2101
2102 if (status & IRQ_RXOVER)
2103 rx_start(info);
2104 }
2105
2106 if (status & IRQ_DSR)
2107 dsr_change(info, status);
2108 if (status & IRQ_CTS)
2109 cts_change(info, status);
2110 if (status & IRQ_DCD)
2111 dcd_change(info, status);
2112 if (status & IRQ_RI)
2113 ri_change(info, status);
2114}
2115
2116static void isr_rdma(struct slgt_info *info)
2117{
2118 unsigned int status = rd_reg32(info, RDCSR);
2119
2120 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2121
2122 /* RDCSR (rx DMA control/status)
2123 *
2124 * 31..07 reserved
2125 * 06 save status byte to DMA buffer
2126 * 05 error
2127 * 04 eol (end of list)
2128 * 03 eob (end of buffer)
2129 * 02 IRQ enable
2130 * 01 reset
2131 * 00 enable
2132 */
2133 wr_reg32(info, RDCSR, status); /* clear pending */
2134
2135 if (status & (BIT5 + BIT4)) {
2136 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2137 info->rx_restart = true;
2138 }
2139 info->pending_bh |= BH_RECEIVE;
2140}
2141
2142static void isr_tdma(struct slgt_info *info)
2143{
2144 unsigned int status = rd_reg32(info, TDCSR);
2145
2146 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2147
2148 /* TDCSR (tx DMA control/status)
2149 *
2150 * 31..06 reserved
2151 * 05 error
2152 * 04 eol (end of list)
2153 * 03 eob (end of buffer)
2154 * 02 IRQ enable
2155 * 01 reset
2156 * 00 enable
2157 */
2158 wr_reg32(info, TDCSR, status); /* clear pending */
2159
2160 if (status & (BIT5 + BIT4 + BIT3)) {
2161 // another transmit buffer has completed
2162 // run bottom half to get more send data from user
2163 info->pending_bh |= BH_TRANSMIT;
2164 }
2165}
2166
2167/*
2168 * return true if there are unsent tx DMA buffers, otherwise false
2169 *
2170 * if there are unsent buffers then info->tbuf_start
2171 * is set to index of first unsent buffer
2172 */
2173static bool unsent_tbufs(struct slgt_info *info)
2174{
2175 unsigned int i = info->tbuf_current;
2176 bool rc = false;
2177
2178 /*
2179 * search backwards from last loaded buffer (precedes tbuf_current)
2180 * for first unsent buffer (desc_count > 0)
2181 */
2182
2183 do {
2184 if (i)
2185 i--;
2186 else
2187 i = info->tbuf_count - 1;
2188 if (!desc_count(info->tbufs[i]))
2189 break;
2190 info->tbuf_start = i;
2191 rc = true;
2192 } while (i != info->tbuf_current);
2193
2194 return rc;
2195}
2196
2197static void isr_txeom(struct slgt_info *info, unsigned short status)
2198{
2199 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2200
2201 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2202 tdma_reset(info);
2203 if (status & IRQ_TXUNDER) {
2204 unsigned short val = rd_reg16(info, TCR);
2205 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2206 wr_reg16(info, TCR, val); /* clear reset bit */
2207 }
2208
2209 if (info->tx_active) {
2210 if (info->params.mode != MGSL_MODE_ASYNC) {
2211 if (status & IRQ_TXUNDER)
2212 info->icount.txunder++;
2213 else if (status & IRQ_TXIDLE)
2214 info->icount.txok++;
2215 }
2216
2217 if (unsent_tbufs(info)) {
2218 tx_start(info);
2219 update_tx_timer(info);
2220 return;
2221 }
2222 info->tx_active = false;
2223
2224 del_timer(&info->tx_timer);
2225
2226 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2227 info->signals &= ~SerialSignal_RTS;
2228 info->drop_rts_on_tx_done = false;
2229 set_gtsignals(info);
2230 }
2231
2232#if SYNCLINK_GENERIC_HDLC
2233 if (info->netcount)
2234 hdlcdev_tx_done(info);
2235 else
2236#endif
2237 {
2238 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2239 tx_stop(info);
2240 return;
2241 }
2242 info->pending_bh |= BH_TRANSMIT;
2243 }
2244 }
2245}
2246
2247static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2248{
2249 struct cond_wait *w, *prev;
2250
2251 /* wake processes waiting for specific transitions */
2252 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2253 if (w->data & changed) {
2254 w->data = state;
2255 wake_up_interruptible(&w->q);
2256 if (prev != NULL)
2257 prev->next = w->next;
2258 else
2259 info->gpio_wait_q = w->next;
2260 } else
2261 prev = w;
2262 }
2263}
2264
2265/* interrupt service routine
2266 *
2267 * irq interrupt number
2268 * dev_id device ID supplied during interrupt registration
2269 */
2270static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2271{
2272 struct slgt_info *info = dev_id;
2273 unsigned int gsr;
2274 unsigned int i;
2275
2276 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2277
2278 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2279 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2280 info->irq_occurred = true;
2281 for(i=0; i < info->port_count ; i++) {
2282 if (info->port_array[i] == NULL)
2283 continue;
2284 spin_lock(&info->port_array[i]->lock);
2285 if (gsr & (BIT8 << i))
2286 isr_serial(info->port_array[i]);
2287 if (gsr & (BIT16 << (i*2)))
2288 isr_rdma(info->port_array[i]);
2289 if (gsr & (BIT17 << (i*2)))
2290 isr_tdma(info->port_array[i]);
2291 spin_unlock(&info->port_array[i]->lock);
2292 }
2293 }
2294
2295 if (info->gpio_present) {
2296 unsigned int state;
2297 unsigned int changed;
2298 spin_lock(&info->lock);
2299 while ((changed = rd_reg32(info, IOSR)) != 0) {
2300 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2301 /* read latched state of GPIO signals */
2302 state = rd_reg32(info, IOVR);
2303 /* clear pending GPIO interrupt bits */
2304 wr_reg32(info, IOSR, changed);
2305 for (i=0 ; i < info->port_count ; i++) {
2306 if (info->port_array[i] != NULL)
2307 isr_gpio(info->port_array[i], changed, state);
2308 }
2309 }
2310 spin_unlock(&info->lock);
2311 }
2312
2313 for(i=0; i < info->port_count ; i++) {
2314 struct slgt_info *port = info->port_array[i];
2315 if (port == NULL)
2316 continue;
2317 spin_lock(&port->lock);
2318 if ((port->port.count || port->netcount) &&
2319 port->pending_bh && !port->bh_running &&
2320 !port->bh_requested) {
2321 DBGISR(("%s bh queued\n", port->device_name));
2322 schedule_work(&port->task);
2323 port->bh_requested = true;
2324 }
2325 spin_unlock(&port->lock);
2326 }
2327
2328 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2329 return IRQ_HANDLED;
2330}
2331
2332static int startup(struct slgt_info *info)
2333{
2334 DBGINFO(("%s startup\n", info->device_name));
2335
2336 if (tty_port_initialized(&info->port))
2337 return 0;
2338
2339 if (!info->tx_buf) {
2340 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2341 if (!info->tx_buf) {
2342 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2343 return -ENOMEM;
2344 }
2345 }
2346
2347 info->pending_bh = 0;
2348
2349 memset(&info->icount, 0, sizeof(info->icount));
2350
2351 /* program hardware for current parameters */
2352 change_params(info);
2353
2354 if (info->port.tty)
2355 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2356
2357 tty_port_set_initialized(&info->port, 1);
2358
2359 return 0;
2360}
2361
2362/*
2363 * called by close() and hangup() to shutdown hardware
2364 */
2365static void shutdown(struct slgt_info *info)
2366{
2367 unsigned long flags;
2368
2369 if (!tty_port_initialized(&info->port))
2370 return;
2371
2372 DBGINFO(("%s shutdown\n", info->device_name));
2373
2374 /* clear status wait queue because status changes */
2375 /* can't happen after shutting down the hardware */
2376 wake_up_interruptible(&info->status_event_wait_q);
2377 wake_up_interruptible(&info->event_wait_q);
2378
2379 del_timer_sync(&info->tx_timer);
2380 del_timer_sync(&info->rx_timer);
2381
2382 kfree(info->tx_buf);
2383 info->tx_buf = NULL;
2384
2385 spin_lock_irqsave(&info->lock,flags);
2386
2387 tx_stop(info);
2388 rx_stop(info);
2389
2390 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2391
2392 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2393 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2394 set_gtsignals(info);
2395 }
2396
2397 flush_cond_wait(&info->gpio_wait_q);
2398
2399 spin_unlock_irqrestore(&info->lock,flags);
2400
2401 if (info->port.tty)
2402 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2403
2404 tty_port_set_initialized(&info->port, 0);
2405}
2406
2407static void program_hw(struct slgt_info *info)
2408{
2409 unsigned long flags;
2410
2411 spin_lock_irqsave(&info->lock,flags);
2412
2413 rx_stop(info);
2414 tx_stop(info);
2415
2416 if (info->params.mode != MGSL_MODE_ASYNC ||
2417 info->netcount)
2418 sync_mode(info);
2419 else
2420 async_mode(info);
2421
2422 set_gtsignals(info);
2423
2424 info->dcd_chkcount = 0;
2425 info->cts_chkcount = 0;
2426 info->ri_chkcount = 0;
2427 info->dsr_chkcount = 0;
2428
2429 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2430 get_gtsignals(info);
2431
2432 if (info->netcount ||
2433 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2434 rx_start(info);
2435
2436 spin_unlock_irqrestore(&info->lock,flags);
2437}
2438
2439/*
2440 * reconfigure adapter based on new parameters
2441 */
2442static void change_params(struct slgt_info *info)
2443{
2444 unsigned cflag;
2445 int bits_per_char;
2446
2447 if (!info->port.tty)
2448 return;
2449 DBGINFO(("%s change_params\n", info->device_name));
2450
2451 cflag = info->port.tty->termios.c_cflag;
2452
2453 /* if B0 rate (hangup) specified then negate RTS and DTR */
2454 /* otherwise assert RTS and DTR */
2455 if (cflag & CBAUD)
2456 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2457 else
2458 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2459
2460 /* byte size and parity */
2461
2462 info->params.data_bits = tty_get_char_size(cflag);
2463 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2464
2465 if (cflag & PARENB)
2466 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2467 else
2468 info->params.parity = ASYNC_PARITY_NONE;
2469
2470 /* calculate number of jiffies to transmit a full
2471 * FIFO (32 bytes) at specified data rate
2472 */
2473 bits_per_char = info->params.data_bits +
2474 info->params.stop_bits + 1;
2475
2476 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2477
2478 if (info->params.data_rate) {
2479 info->timeout = (32*HZ*bits_per_char) /
2480 info->params.data_rate;
2481 }
2482 info->timeout += HZ/50; /* Add .02 seconds of slop */
2483
2484 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2485 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2486
2487 /* process tty input control flags */
2488
2489 info->read_status_mask = IRQ_RXOVER;
2490 if (I_INPCK(info->port.tty))
2491 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2492 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2493 info->read_status_mask |= MASK_BREAK;
2494 if (I_IGNPAR(info->port.tty))
2495 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2496 if (I_IGNBRK(info->port.tty)) {
2497 info->ignore_status_mask |= MASK_BREAK;
2498 /* If ignoring parity and break indicators, ignore
2499 * overruns too. (For real raw support).
2500 */
2501 if (I_IGNPAR(info->port.tty))
2502 info->ignore_status_mask |= MASK_OVERRUN;
2503 }
2504
2505 program_hw(info);
2506}
2507
2508static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2509{
2510 DBGINFO(("%s get_stats\n", info->device_name));
2511 if (!user_icount) {
2512 memset(&info->icount, 0, sizeof(info->icount));
2513 } else {
2514 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2515 return -EFAULT;
2516 }
2517 return 0;
2518}
2519
2520static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2521{
2522 DBGINFO(("%s get_params\n", info->device_name));
2523 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2524 return -EFAULT;
2525 return 0;
2526}
2527
2528static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2529{
2530 unsigned long flags;
2531 MGSL_PARAMS tmp_params;
2532
2533 DBGINFO(("%s set_params\n", info->device_name));
2534 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2535 return -EFAULT;
2536
2537 spin_lock_irqsave(&info->lock, flags);
2538 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2539 info->base_clock = tmp_params.clock_speed;
2540 else
2541 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2542 spin_unlock_irqrestore(&info->lock, flags);
2543
2544 program_hw(info);
2545
2546 return 0;
2547}
2548
2549static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2550{
2551 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2552 if (put_user(info->idle_mode, idle_mode))
2553 return -EFAULT;
2554 return 0;
2555}
2556
2557static int set_txidle(struct slgt_info *info, int idle_mode)
2558{
2559 unsigned long flags;
2560 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2561 spin_lock_irqsave(&info->lock,flags);
2562 info->idle_mode = idle_mode;
2563 if (info->params.mode != MGSL_MODE_ASYNC)
2564 tx_set_idle(info);
2565 spin_unlock_irqrestore(&info->lock,flags);
2566 return 0;
2567}
2568
2569static int tx_enable(struct slgt_info *info, int enable)
2570{
2571 unsigned long flags;
2572 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2573 spin_lock_irqsave(&info->lock,flags);
2574 if (enable) {
2575 if (!info->tx_enabled)
2576 tx_start(info);
2577 } else {
2578 if (info->tx_enabled)
2579 tx_stop(info);
2580 }
2581 spin_unlock_irqrestore(&info->lock,flags);
2582 return 0;
2583}
2584
2585/*
2586 * abort transmit HDLC frame
2587 */
2588static int tx_abort(struct slgt_info *info)
2589{
2590 unsigned long flags;
2591 DBGINFO(("%s tx_abort\n", info->device_name));
2592 spin_lock_irqsave(&info->lock,flags);
2593 tdma_reset(info);
2594 spin_unlock_irqrestore(&info->lock,flags);
2595 return 0;
2596}
2597
2598static int rx_enable(struct slgt_info *info, int enable)
2599{
2600 unsigned long flags;
2601 unsigned int rbuf_fill_level;
2602 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2603 spin_lock_irqsave(&info->lock,flags);
2604 /*
2605 * enable[31..16] = receive DMA buffer fill level
2606 * 0 = noop (leave fill level unchanged)
2607 * fill level must be multiple of 4 and <= buffer size
2608 */
2609 rbuf_fill_level = ((unsigned int)enable) >> 16;
2610 if (rbuf_fill_level) {
2611 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2612 spin_unlock_irqrestore(&info->lock, flags);
2613 return -EINVAL;
2614 }
2615 info->rbuf_fill_level = rbuf_fill_level;
2616 if (rbuf_fill_level < 128)
2617 info->rx_pio = 1; /* PIO mode */
2618 else
2619 info->rx_pio = 0; /* DMA mode */
2620 rx_stop(info); /* restart receiver to use new fill level */
2621 }
2622
2623 /*
2624 * enable[1..0] = receiver enable command
2625 * 0 = disable
2626 * 1 = enable
2627 * 2 = enable or force hunt mode if already enabled
2628 */
2629 enable &= 3;
2630 if (enable) {
2631 if (!info->rx_enabled)
2632 rx_start(info);
2633 else if (enable == 2) {
2634 /* force hunt mode (write 1 to RCR[3]) */
2635 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2636 }
2637 } else {
2638 if (info->rx_enabled)
2639 rx_stop(info);
2640 }
2641 spin_unlock_irqrestore(&info->lock,flags);
2642 return 0;
2643}
2644
2645/*
2646 * wait for specified event to occur
2647 */
2648static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2649{
2650 unsigned long flags;
2651 int s;
2652 int rc=0;
2653 struct mgsl_icount cprev, cnow;
2654 int events;
2655 int mask;
2656 struct _input_signal_events oldsigs, newsigs;
2657 DECLARE_WAITQUEUE(wait, current);
2658
2659 if (get_user(mask, mask_ptr))
2660 return -EFAULT;
2661
2662 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2663
2664 spin_lock_irqsave(&info->lock,flags);
2665
2666 /* return immediately if state matches requested events */
2667 get_gtsignals(info);
2668 s = info->signals;
2669
2670 events = mask &
2671 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2672 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2673 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2674 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2675 if (events) {
2676 spin_unlock_irqrestore(&info->lock,flags);
2677 goto exit;
2678 }
2679
2680 /* save current irq counts */
2681 cprev = info->icount;
2682 oldsigs = info->input_signal_events;
2683
2684 /* enable hunt and idle irqs if needed */
2685 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2686 unsigned short val = rd_reg16(info, SCR);
2687 if (!(val & IRQ_RXIDLE))
2688 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2689 }
2690
2691 set_current_state(TASK_INTERRUPTIBLE);
2692 add_wait_queue(&info->event_wait_q, &wait);
2693
2694 spin_unlock_irqrestore(&info->lock,flags);
2695
2696 for(;;) {
2697 schedule();
2698 if (signal_pending(current)) {
2699 rc = -ERESTARTSYS;
2700 break;
2701 }
2702
2703 /* get current irq counts */
2704 spin_lock_irqsave(&info->lock,flags);
2705 cnow = info->icount;
2706 newsigs = info->input_signal_events;
2707 set_current_state(TASK_INTERRUPTIBLE);
2708 spin_unlock_irqrestore(&info->lock,flags);
2709
2710 /* if no change, wait aborted for some reason */
2711 if (newsigs.dsr_up == oldsigs.dsr_up &&
2712 newsigs.dsr_down == oldsigs.dsr_down &&
2713 newsigs.dcd_up == oldsigs.dcd_up &&
2714 newsigs.dcd_down == oldsigs.dcd_down &&
2715 newsigs.cts_up == oldsigs.cts_up &&
2716 newsigs.cts_down == oldsigs.cts_down &&
2717 newsigs.ri_up == oldsigs.ri_up &&
2718 newsigs.ri_down == oldsigs.ri_down &&
2719 cnow.exithunt == cprev.exithunt &&
2720 cnow.rxidle == cprev.rxidle) {
2721 rc = -EIO;
2722 break;
2723 }
2724
2725 events = mask &
2726 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2727 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2728 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2729 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2730 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2731 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2732 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2733 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2734 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2735 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2736 if (events)
2737 break;
2738
2739 cprev = cnow;
2740 oldsigs = newsigs;
2741 }
2742
2743 remove_wait_queue(&info->event_wait_q, &wait);
2744 set_current_state(TASK_RUNNING);
2745
2746
2747 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2748 spin_lock_irqsave(&info->lock,flags);
2749 if (!waitqueue_active(&info->event_wait_q)) {
2750 /* disable enable exit hunt mode/idle rcvd IRQs */
2751 wr_reg16(info, SCR,
2752 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2753 }
2754 spin_unlock_irqrestore(&info->lock,flags);
2755 }
2756exit:
2757 if (rc == 0)
2758 rc = put_user(events, mask_ptr);
2759 return rc;
2760}
2761
2762static int get_interface(struct slgt_info *info, int __user *if_mode)
2763{
2764 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2765 if (put_user(info->if_mode, if_mode))
2766 return -EFAULT;
2767 return 0;
2768}
2769
2770static int set_interface(struct slgt_info *info, int if_mode)
2771{
2772 unsigned long flags;
2773 unsigned short val;
2774
2775 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2776 spin_lock_irqsave(&info->lock,flags);
2777 info->if_mode = if_mode;
2778
2779 msc_set_vcr(info);
2780
2781 /* TCR (tx control) 07 1=RTS driver control */
2782 val = rd_reg16(info, TCR);
2783 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2784 val |= BIT7;
2785 else
2786 val &= ~BIT7;
2787 wr_reg16(info, TCR, val);
2788
2789 spin_unlock_irqrestore(&info->lock,flags);
2790 return 0;
2791}
2792
2793static int get_xsync(struct slgt_info *info, int __user *xsync)
2794{
2795 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2796 if (put_user(info->xsync, xsync))
2797 return -EFAULT;
2798 return 0;
2799}
2800
2801/*
2802 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2803 *
2804 * sync pattern is contained in least significant bytes of value
2805 * most significant byte of sync pattern is oldest (1st sent/detected)
2806 */
2807static int set_xsync(struct slgt_info *info, int xsync)
2808{
2809 unsigned long flags;
2810
2811 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2812 spin_lock_irqsave(&info->lock, flags);
2813 info->xsync = xsync;
2814 wr_reg32(info, XSR, xsync);
2815 spin_unlock_irqrestore(&info->lock, flags);
2816 return 0;
2817}
2818
2819static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2820{
2821 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2822 if (put_user(info->xctrl, xctrl))
2823 return -EFAULT;
2824 return 0;
2825}
2826
2827/*
2828 * set extended control options
2829 *
2830 * xctrl[31:19] reserved, must be zero
2831 * xctrl[18:17] extended sync pattern length in bytes
2832 * 00 = 1 byte in xsr[7:0]
2833 * 01 = 2 bytes in xsr[15:0]
2834 * 10 = 3 bytes in xsr[23:0]
2835 * 11 = 4 bytes in xsr[31:0]
2836 * xctrl[16] 1 = enable terminal count, 0=disabled
2837 * xctrl[15:0] receive terminal count for fixed length packets
2838 * value is count minus one (0 = 1 byte packet)
2839 * when terminal count is reached, receiver
2840 * automatically returns to hunt mode and receive
2841 * FIFO contents are flushed to DMA buffers with
2842 * end of frame (EOF) status
2843 */
2844static int set_xctrl(struct slgt_info *info, int xctrl)
2845{
2846 unsigned long flags;
2847
2848 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2849 spin_lock_irqsave(&info->lock, flags);
2850 info->xctrl = xctrl;
2851 wr_reg32(info, XCR, xctrl);
2852 spin_unlock_irqrestore(&info->lock, flags);
2853 return 0;
2854}
2855
2856/*
2857 * set general purpose IO pin state and direction
2858 *
2859 * user_gpio fields:
2860 * state each bit indicates a pin state
2861 * smask set bit indicates pin state to set
2862 * dir each bit indicates a pin direction (0=input, 1=output)
2863 * dmask set bit indicates pin direction to set
2864 */
2865static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2866{
2867 unsigned long flags;
2868 struct gpio_desc gpio;
2869 __u32 data;
2870
2871 if (!info->gpio_present)
2872 return -EINVAL;
2873 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2874 return -EFAULT;
2875 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2876 info->device_name, gpio.state, gpio.smask,
2877 gpio.dir, gpio.dmask));
2878
2879 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2880 if (gpio.dmask) {
2881 data = rd_reg32(info, IODR);
2882 data |= gpio.dmask & gpio.dir;
2883 data &= ~(gpio.dmask & ~gpio.dir);
2884 wr_reg32(info, IODR, data);
2885 }
2886 if (gpio.smask) {
2887 data = rd_reg32(info, IOVR);
2888 data |= gpio.smask & gpio.state;
2889 data &= ~(gpio.smask & ~gpio.state);
2890 wr_reg32(info, IOVR, data);
2891 }
2892 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2893
2894 return 0;
2895}
2896
2897/*
2898 * get general purpose IO pin state and direction
2899 */
2900static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2901{
2902 struct gpio_desc gpio;
2903 if (!info->gpio_present)
2904 return -EINVAL;
2905 gpio.state = rd_reg32(info, IOVR);
2906 gpio.smask = 0xffffffff;
2907 gpio.dir = rd_reg32(info, IODR);
2908 gpio.dmask = 0xffffffff;
2909 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2910 return -EFAULT;
2911 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2912 info->device_name, gpio.state, gpio.dir));
2913 return 0;
2914}
2915
2916/*
2917 * conditional wait facility
2918 */
2919static void init_cond_wait(struct cond_wait *w, unsigned int data)
2920{
2921 init_waitqueue_head(&w->q);
2922 init_waitqueue_entry(&w->wait, current);
2923 w->data = data;
2924}
2925
2926static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2927{
2928 set_current_state(TASK_INTERRUPTIBLE);
2929 add_wait_queue(&w->q, &w->wait);
2930 w->next = *head;
2931 *head = w;
2932}
2933
2934static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2935{
2936 struct cond_wait *w, *prev;
2937 remove_wait_queue(&cw->q, &cw->wait);
2938 set_current_state(TASK_RUNNING);
2939 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2940 if (w == cw) {
2941 if (prev != NULL)
2942 prev->next = w->next;
2943 else
2944 *head = w->next;
2945 break;
2946 }
2947 }
2948}
2949
2950static void flush_cond_wait(struct cond_wait **head)
2951{
2952 while (*head != NULL) {
2953 wake_up_interruptible(&(*head)->q);
2954 *head = (*head)->next;
2955 }
2956}
2957
2958/*
2959 * wait for general purpose I/O pin(s) to enter specified state
2960 *
2961 * user_gpio fields:
2962 * state - bit indicates target pin state
2963 * smask - set bit indicates watched pin
2964 *
2965 * The wait ends when at least one watched pin enters the specified
2966 * state. When 0 (no error) is returned, user_gpio->state is set to the
2967 * state of all GPIO pins when the wait ends.
2968 *
2969 * Note: Each pin may be a dedicated input, dedicated output, or
2970 * configurable input/output. The number and configuration of pins
2971 * varies with the specific adapter model. Only input pins (dedicated
2972 * or configured) can be monitored with this function.
2973 */
2974static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2975{
2976 unsigned long flags;
2977 int rc = 0;
2978 struct gpio_desc gpio;
2979 struct cond_wait wait;
2980 u32 state;
2981
2982 if (!info->gpio_present)
2983 return -EINVAL;
2984 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2985 return -EFAULT;
2986 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2987 info->device_name, gpio.state, gpio.smask));
2988 /* ignore output pins identified by set IODR bit */
2989 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2990 return -EINVAL;
2991 init_cond_wait(&wait, gpio.smask);
2992
2993 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2994 /* enable interrupts for watched pins */
2995 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2996 /* get current pin states */
2997 state = rd_reg32(info, IOVR);
2998
2999 if (gpio.smask & ~(state ^ gpio.state)) {
3000 /* already in target state */
3001 gpio.state = state;
3002 } else {
3003 /* wait for target state */
3004 add_cond_wait(&info->gpio_wait_q, &wait);
3005 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3006 schedule();
3007 if (signal_pending(current))
3008 rc = -ERESTARTSYS;
3009 else
3010 gpio.state = wait.data;
3011 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3012 remove_cond_wait(&info->gpio_wait_q, &wait);
3013 }
3014
3015 /* disable all GPIO interrupts if no waiting processes */
3016 if (info->gpio_wait_q == NULL)
3017 wr_reg32(info, IOER, 0);
3018 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3019
3020 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3021 rc = -EFAULT;
3022 return rc;
3023}
3024
3025static int modem_input_wait(struct slgt_info *info,int arg)
3026{
3027 unsigned long flags;
3028 int rc;
3029 struct mgsl_icount cprev, cnow;
3030 DECLARE_WAITQUEUE(wait, current);
3031
3032 /* save current irq counts */
3033 spin_lock_irqsave(&info->lock,flags);
3034 cprev = info->icount;
3035 add_wait_queue(&info->status_event_wait_q, &wait);
3036 set_current_state(TASK_INTERRUPTIBLE);
3037 spin_unlock_irqrestore(&info->lock,flags);
3038
3039 for(;;) {
3040 schedule();
3041 if (signal_pending(current)) {
3042 rc = -ERESTARTSYS;
3043 break;
3044 }
3045
3046 /* get new irq counts */
3047 spin_lock_irqsave(&info->lock,flags);
3048 cnow = info->icount;
3049 set_current_state(TASK_INTERRUPTIBLE);
3050 spin_unlock_irqrestore(&info->lock,flags);
3051
3052 /* if no change, wait aborted for some reason */
3053 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3054 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3055 rc = -EIO;
3056 break;
3057 }
3058
3059 /* check for change in caller specified modem input */
3060 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3061 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3062 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3063 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3064 rc = 0;
3065 break;
3066 }
3067
3068 cprev = cnow;
3069 }
3070 remove_wait_queue(&info->status_event_wait_q, &wait);
3071 set_current_state(TASK_RUNNING);
3072 return rc;
3073}
3074
3075/*
3076 * return state of serial control and status signals
3077 */
3078static int tiocmget(struct tty_struct *tty)
3079{
3080 struct slgt_info *info = tty->driver_data;
3081 unsigned int result;
3082 unsigned long flags;
3083
3084 spin_lock_irqsave(&info->lock,flags);
3085 get_gtsignals(info);
3086 spin_unlock_irqrestore(&info->lock,flags);
3087
3088 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3089 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3090 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3091 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3092 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3093 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3094
3095 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3096 return result;
3097}
3098
3099/*
3100 * set modem control signals (DTR/RTS)
3101 *
3102 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3103 * TIOCMSET = set/clear signal values
3104 * value bit mask for command
3105 */
3106static int tiocmset(struct tty_struct *tty,
3107 unsigned int set, unsigned int clear)
3108{
3109 struct slgt_info *info = tty->driver_data;
3110 unsigned long flags;
3111
3112 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3113
3114 if (set & TIOCM_RTS)
3115 info->signals |= SerialSignal_RTS;
3116 if (set & TIOCM_DTR)
3117 info->signals |= SerialSignal_DTR;
3118 if (clear & TIOCM_RTS)
3119 info->signals &= ~SerialSignal_RTS;
3120 if (clear & TIOCM_DTR)
3121 info->signals &= ~SerialSignal_DTR;
3122
3123 spin_lock_irqsave(&info->lock,flags);
3124 set_gtsignals(info);
3125 spin_unlock_irqrestore(&info->lock,flags);
3126 return 0;
3127}
3128
3129static int carrier_raised(struct tty_port *port)
3130{
3131 unsigned long flags;
3132 struct slgt_info *info = container_of(port, struct slgt_info, port);
3133
3134 spin_lock_irqsave(&info->lock,flags);
3135 get_gtsignals(info);
3136 spin_unlock_irqrestore(&info->lock,flags);
3137 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3138}
3139
3140static void dtr_rts(struct tty_port *port, int on)
3141{
3142 unsigned long flags;
3143 struct slgt_info *info = container_of(port, struct slgt_info, port);
3144
3145 spin_lock_irqsave(&info->lock,flags);
3146 if (on)
3147 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3148 else
3149 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3150 set_gtsignals(info);
3151 spin_unlock_irqrestore(&info->lock,flags);
3152}
3153
3154
3155/*
3156 * block current process until the device is ready to open
3157 */
3158static int block_til_ready(struct tty_struct *tty, struct file *filp,
3159 struct slgt_info *info)
3160{
3161 DECLARE_WAITQUEUE(wait, current);
3162 int retval;
3163 bool do_clocal = false;
3164 unsigned long flags;
3165 int cd;
3166 struct tty_port *port = &info->port;
3167
3168 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3169
3170 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3171 /* nonblock mode is set or port is not enabled */
3172 tty_port_set_active(port, 1);
3173 return 0;
3174 }
3175
3176 if (C_CLOCAL(tty))
3177 do_clocal = true;
3178
3179 /* Wait for carrier detect and the line to become
3180 * free (i.e., not in use by the callout). While we are in
3181 * this loop, port->count is dropped by one, so that
3182 * close() knows when to free things. We restore it upon
3183 * exit, either normal or abnormal.
3184 */
3185
3186 retval = 0;
3187 add_wait_queue(&port->open_wait, &wait);
3188
3189 spin_lock_irqsave(&info->lock, flags);
3190 port->count--;
3191 spin_unlock_irqrestore(&info->lock, flags);
3192 port->blocked_open++;
3193
3194 while (1) {
3195 if (C_BAUD(tty) && tty_port_initialized(port))
3196 tty_port_raise_dtr_rts(port);
3197
3198 set_current_state(TASK_INTERRUPTIBLE);
3199
3200 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3201 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3202 -EAGAIN : -ERESTARTSYS;
3203 break;
3204 }
3205
3206 cd = tty_port_carrier_raised(port);
3207 if (do_clocal || cd)
3208 break;
3209
3210 if (signal_pending(current)) {
3211 retval = -ERESTARTSYS;
3212 break;
3213 }
3214
3215 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3216 tty_unlock(tty);
3217 schedule();
3218 tty_lock(tty);
3219 }
3220
3221 set_current_state(TASK_RUNNING);
3222 remove_wait_queue(&port->open_wait, &wait);
3223
3224 if (!tty_hung_up_p(filp))
3225 port->count++;
3226 port->blocked_open--;
3227
3228 if (!retval)
3229 tty_port_set_active(port, 1);
3230
3231 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3232 return retval;
3233}
3234
3235/*
3236 * allocate buffers used for calling line discipline receive_buf
3237 * directly in synchronous mode
3238 * note: add 5 bytes to max frame size to allow appending
3239 * 32-bit CRC and status byte when configured to do so
3240 */
3241static int alloc_tmp_rbuf(struct slgt_info *info)
3242{
3243 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3244 if (info->tmp_rbuf == NULL)
3245 return -ENOMEM;
3246 /* unused flag buffer to satisfy receive_buf calling interface */
3247 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3248 if (!info->flag_buf) {
3249 kfree(info->tmp_rbuf);
3250 info->tmp_rbuf = NULL;
3251 return -ENOMEM;
3252 }
3253 return 0;
3254}
3255
3256static void free_tmp_rbuf(struct slgt_info *info)
3257{
3258 kfree(info->tmp_rbuf);
3259 info->tmp_rbuf = NULL;
3260 kfree(info->flag_buf);
3261 info->flag_buf = NULL;
3262}
3263
3264/*
3265 * allocate DMA descriptor lists.
3266 */
3267static int alloc_desc(struct slgt_info *info)
3268{
3269 unsigned int i;
3270 unsigned int pbufs;
3271
3272 /* allocate memory to hold descriptor lists */
3273 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3274 &info->bufs_dma_addr, GFP_KERNEL);
3275 if (info->bufs == NULL)
3276 return -ENOMEM;
3277
3278 info->rbufs = (struct slgt_desc*)info->bufs;
3279 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3280
3281 pbufs = (unsigned int)info->bufs_dma_addr;
3282
3283 /*
3284 * Build circular lists of descriptors
3285 */
3286
3287 for (i=0; i < info->rbuf_count; i++) {
3288 /* physical address of this descriptor */
3289 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3290
3291 /* physical address of next descriptor */
3292 if (i == info->rbuf_count - 1)
3293 info->rbufs[i].next = cpu_to_le32(pbufs);
3294 else
3295 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3296 set_desc_count(info->rbufs[i], DMABUFSIZE);
3297 }
3298
3299 for (i=0; i < info->tbuf_count; i++) {
3300 /* physical address of this descriptor */
3301 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3302
3303 /* physical address of next descriptor */
3304 if (i == info->tbuf_count - 1)
3305 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3306 else
3307 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3308 }
3309
3310 return 0;
3311}
3312
3313static void free_desc(struct slgt_info *info)
3314{
3315 if (info->bufs != NULL) {
3316 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3317 info->bufs, info->bufs_dma_addr);
3318 info->bufs = NULL;
3319 info->rbufs = NULL;
3320 info->tbufs = NULL;
3321 }
3322}
3323
3324static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3325{
3326 int i;
3327 for (i=0; i < count; i++) {
3328 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3329 &bufs[i].buf_dma_addr, GFP_KERNEL);
3330 if (!bufs[i].buf)
3331 return -ENOMEM;
3332 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3333 }
3334 return 0;
3335}
3336
3337static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3338{
3339 int i;
3340 for (i=0; i < count; i++) {
3341 if (bufs[i].buf == NULL)
3342 continue;
3343 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3344 bufs[i].buf_dma_addr);
3345 bufs[i].buf = NULL;
3346 }
3347}
3348
3349static int alloc_dma_bufs(struct slgt_info *info)
3350{
3351 info->rbuf_count = 32;
3352 info->tbuf_count = 32;
3353
3354 if (alloc_desc(info) < 0 ||
3355 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3356 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3357 alloc_tmp_rbuf(info) < 0) {
3358 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3359 return -ENOMEM;
3360 }
3361 reset_rbufs(info);
3362 return 0;
3363}
3364
3365static void free_dma_bufs(struct slgt_info *info)
3366{
3367 if (info->bufs) {
3368 free_bufs(info, info->rbufs, info->rbuf_count);
3369 free_bufs(info, info->tbufs, info->tbuf_count);
3370 free_desc(info);
3371 }
3372 free_tmp_rbuf(info);
3373}
3374
3375static int claim_resources(struct slgt_info *info)
3376{
3377 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3378 DBGERR(("%s reg addr conflict, addr=%08X\n",
3379 info->device_name, info->phys_reg_addr));
3380 info->init_error = DiagStatus_AddressConflict;
3381 goto errout;
3382 }
3383 else
3384 info->reg_addr_requested = true;
3385
3386 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3387 if (!info->reg_addr) {
3388 DBGERR(("%s can't map device registers, addr=%08X\n",
3389 info->device_name, info->phys_reg_addr));
3390 info->init_error = DiagStatus_CantAssignPciResources;
3391 goto errout;
3392 }
3393 return 0;
3394
3395errout:
3396 release_resources(info);
3397 return -ENODEV;
3398}
3399
3400static void release_resources(struct slgt_info *info)
3401{
3402 if (info->irq_requested) {
3403 free_irq(info->irq_level, info);
3404 info->irq_requested = false;
3405 }
3406
3407 if (info->reg_addr_requested) {
3408 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3409 info->reg_addr_requested = false;
3410 }
3411
3412 if (info->reg_addr) {
3413 iounmap(info->reg_addr);
3414 info->reg_addr = NULL;
3415 }
3416}
3417
3418/* Add the specified device instance data structure to the
3419 * global linked list of devices and increment the device count.
3420 */
3421static void add_device(struct slgt_info *info)
3422{
3423 char *devstr;
3424
3425 info->next_device = NULL;
3426 info->line = slgt_device_count;
3427 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3428
3429 if (info->line < MAX_DEVICES) {
3430 if (maxframe[info->line])
3431 info->max_frame_size = maxframe[info->line];
3432 }
3433
3434 slgt_device_count++;
3435
3436 if (!slgt_device_list)
3437 slgt_device_list = info;
3438 else {
3439 struct slgt_info *current_dev = slgt_device_list;
3440 while(current_dev->next_device)
3441 current_dev = current_dev->next_device;
3442 current_dev->next_device = info;
3443 }
3444
3445 if (info->max_frame_size < 4096)
3446 info->max_frame_size = 4096;
3447 else if (info->max_frame_size > 65535)
3448 info->max_frame_size = 65535;
3449
3450 switch(info->pdev->device) {
3451 case SYNCLINK_GT_DEVICE_ID:
3452 devstr = "GT";
3453 break;
3454 case SYNCLINK_GT2_DEVICE_ID:
3455 devstr = "GT2";
3456 break;
3457 case SYNCLINK_GT4_DEVICE_ID:
3458 devstr = "GT4";
3459 break;
3460 case SYNCLINK_AC_DEVICE_ID:
3461 devstr = "AC";
3462 info->params.mode = MGSL_MODE_ASYNC;
3463 break;
3464 default:
3465 devstr = "(unknown model)";
3466 }
3467 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3468 devstr, info->device_name, info->phys_reg_addr,
3469 info->irq_level, info->max_frame_size);
3470
3471#if SYNCLINK_GENERIC_HDLC
3472 hdlcdev_init(info);
3473#endif
3474}
3475
3476static const struct tty_port_operations slgt_port_ops = {
3477 .carrier_raised = carrier_raised,
3478 .dtr_rts = dtr_rts,
3479};
3480
3481/*
3482 * allocate device instance structure, return NULL on failure
3483 */
3484static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3485{
3486 struct slgt_info *info;
3487
3488 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3489
3490 if (!info) {
3491 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3492 driver_name, adapter_num, port_num));
3493 } else {
3494 tty_port_init(&info->port);
3495 info->port.ops = &slgt_port_ops;
3496 INIT_WORK(&info->task, bh_handler);
3497 info->max_frame_size = 4096;
3498 info->base_clock = 14745600;
3499 info->rbuf_fill_level = DMABUFSIZE;
3500 init_waitqueue_head(&info->status_event_wait_q);
3501 init_waitqueue_head(&info->event_wait_q);
3502 spin_lock_init(&info->netlock);
3503 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3504 info->idle_mode = HDLC_TXIDLE_FLAGS;
3505 info->adapter_num = adapter_num;
3506 info->port_num = port_num;
3507
3508 timer_setup(&info->tx_timer, tx_timeout, 0);
3509 timer_setup(&info->rx_timer, rx_timeout, 0);
3510
3511 /* Copy configuration info to device instance data */
3512 info->pdev = pdev;
3513 info->irq_level = pdev->irq;
3514 info->phys_reg_addr = pci_resource_start(pdev,0);
3515
3516 info->bus_type = MGSL_BUS_TYPE_PCI;
3517 info->irq_flags = IRQF_SHARED;
3518
3519 info->init_error = -1; /* assume error, set to 0 on successful init */
3520 }
3521
3522 return info;
3523}
3524
3525static void device_init(int adapter_num, struct pci_dev *pdev)
3526{
3527 struct slgt_info *port_array[SLGT_MAX_PORTS];
3528 int i;
3529 int port_count = 1;
3530
3531 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3532 port_count = 2;
3533 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3534 port_count = 4;
3535
3536 /* allocate device instances for all ports */
3537 for (i=0; i < port_count; ++i) {
3538 port_array[i] = alloc_dev(adapter_num, i, pdev);
3539 if (port_array[i] == NULL) {
3540 for (--i; i >= 0; --i) {
3541 tty_port_destroy(&port_array[i]->port);
3542 kfree(port_array[i]);
3543 }
3544 return;
3545 }
3546 }
3547
3548 /* give copy of port_array to all ports and add to device list */
3549 for (i=0; i < port_count; ++i) {
3550 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3551 add_device(port_array[i]);
3552 port_array[i]->port_count = port_count;
3553 spin_lock_init(&port_array[i]->lock);
3554 }
3555
3556 /* Allocate and claim adapter resources */
3557 if (!claim_resources(port_array[0])) {
3558
3559 alloc_dma_bufs(port_array[0]);
3560
3561 /* copy resource information from first port to others */
3562 for (i = 1; i < port_count; ++i) {
3563 port_array[i]->irq_level = port_array[0]->irq_level;
3564 port_array[i]->reg_addr = port_array[0]->reg_addr;
3565 alloc_dma_bufs(port_array[i]);
3566 }
3567
3568 if (request_irq(port_array[0]->irq_level,
3569 slgt_interrupt,
3570 port_array[0]->irq_flags,
3571 port_array[0]->device_name,
3572 port_array[0]) < 0) {
3573 DBGERR(("%s request_irq failed IRQ=%d\n",
3574 port_array[0]->device_name,
3575 port_array[0]->irq_level));
3576 } else {
3577 port_array[0]->irq_requested = true;
3578 adapter_test(port_array[0]);
3579 for (i=1 ; i < port_count ; i++) {
3580 port_array[i]->init_error = port_array[0]->init_error;
3581 port_array[i]->gpio_present = port_array[0]->gpio_present;
3582 }
3583 }
3584 }
3585
3586 for (i = 0; i < port_count; ++i) {
3587 struct slgt_info *info = port_array[i];
3588 tty_port_register_device(&info->port, serial_driver, info->line,
3589 &info->pdev->dev);
3590 }
3591}
3592
3593static int init_one(struct pci_dev *dev,
3594 const struct pci_device_id *ent)
3595{
3596 if (pci_enable_device(dev)) {
3597 printk("error enabling pci device %p\n", dev);
3598 return -EIO;
3599 }
3600 pci_set_master(dev);
3601 device_init(slgt_device_count, dev);
3602 return 0;
3603}
3604
3605static void remove_one(struct pci_dev *dev)
3606{
3607}
3608
3609static const struct tty_operations ops = {
3610 .open = open,
3611 .close = close,
3612 .write = write,
3613 .put_char = put_char,
3614 .flush_chars = flush_chars,
3615 .write_room = write_room,
3616 .chars_in_buffer = chars_in_buffer,
3617 .flush_buffer = flush_buffer,
3618 .ioctl = ioctl,
3619 .compat_ioctl = slgt_compat_ioctl,
3620 .throttle = throttle,
3621 .unthrottle = unthrottle,
3622 .send_xchar = send_xchar,
3623 .break_ctl = set_break,
3624 .wait_until_sent = wait_until_sent,
3625 .set_termios = set_termios,
3626 .stop = tx_hold,
3627 .start = tx_release,
3628 .hangup = hangup,
3629 .tiocmget = tiocmget,
3630 .tiocmset = tiocmset,
3631 .get_icount = get_icount,
3632 .proc_show = synclink_gt_proc_show,
3633};
3634
3635static void slgt_cleanup(void)
3636{
3637 struct slgt_info *info;
3638 struct slgt_info *tmp;
3639
3640 printk(KERN_INFO "unload %s\n", driver_name);
3641
3642 if (serial_driver) {
3643 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3644 tty_unregister_device(serial_driver, info->line);
3645 tty_unregister_driver(serial_driver);
3646 tty_driver_kref_put(serial_driver);
3647 }
3648
3649 /* reset devices */
3650 info = slgt_device_list;
3651 while(info) {
3652 reset_port(info);
3653 info = info->next_device;
3654 }
3655
3656 /* release devices */
3657 info = slgt_device_list;
3658 while(info) {
3659#if SYNCLINK_GENERIC_HDLC
3660 hdlcdev_exit(info);
3661#endif
3662 free_dma_bufs(info);
3663 free_tmp_rbuf(info);
3664 if (info->port_num == 0)
3665 release_resources(info);
3666 tmp = info;
3667 info = info->next_device;
3668 tty_port_destroy(&tmp->port);
3669 kfree(tmp);
3670 }
3671
3672 if (pci_registered)
3673 pci_unregister_driver(&pci_driver);
3674}
3675
3676/*
3677 * Driver initialization entry point.
3678 */
3679static int __init slgt_init(void)
3680{
3681 int rc;
3682
3683 printk(KERN_INFO "%s\n", driver_name);
3684
3685 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3686 TTY_DRIVER_DYNAMIC_DEV);
3687 if (IS_ERR(serial_driver)) {
3688 printk("%s can't allocate tty driver\n", driver_name);
3689 return PTR_ERR(serial_driver);
3690 }
3691
3692 /* Initialize the tty_driver structure */
3693
3694 serial_driver->driver_name = slgt_driver_name;
3695 serial_driver->name = tty_dev_prefix;
3696 serial_driver->major = ttymajor;
3697 serial_driver->minor_start = 64;
3698 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3699 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3700 serial_driver->init_termios = tty_std_termios;
3701 serial_driver->init_termios.c_cflag =
3702 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3703 serial_driver->init_termios.c_ispeed = 9600;
3704 serial_driver->init_termios.c_ospeed = 9600;
3705 tty_set_operations(serial_driver, &ops);
3706 if ((rc = tty_register_driver(serial_driver)) < 0) {
3707 DBGERR(("%s can't register serial driver\n", driver_name));
3708 tty_driver_kref_put(serial_driver);
3709 serial_driver = NULL;
3710 goto error;
3711 }
3712
3713 printk(KERN_INFO "%s, tty major#%d\n",
3714 driver_name, serial_driver->major);
3715
3716 slgt_device_count = 0;
3717 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3718 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3719 goto error;
3720 }
3721 pci_registered = true;
3722
3723 if (!slgt_device_list)
3724 printk("%s no devices found\n",driver_name);
3725
3726 return 0;
3727
3728error:
3729 slgt_cleanup();
3730 return rc;
3731}
3732
3733static void __exit slgt_exit(void)
3734{
3735 slgt_cleanup();
3736}
3737
3738module_init(slgt_init);
3739module_exit(slgt_exit);
3740
3741/*
3742 * register access routines
3743 */
3744
3745#define CALC_REGADDR() \
3746 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3747 if (addr >= 0x80) \
3748 reg_addr += (info->port_num) * 32; \
3749 else if (addr >= 0x40) \
3750 reg_addr += (info->port_num) * 16;
3751
3752static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3753{
3754 CALC_REGADDR();
3755 return readb((void __iomem *)reg_addr);
3756}
3757
3758static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3759{
3760 CALC_REGADDR();
3761 writeb(value, (void __iomem *)reg_addr);
3762}
3763
3764static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3765{
3766 CALC_REGADDR();
3767 return readw((void __iomem *)reg_addr);
3768}
3769
3770static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3771{
3772 CALC_REGADDR();
3773 writew(value, (void __iomem *)reg_addr);
3774}
3775
3776static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3777{
3778 CALC_REGADDR();
3779 return readl((void __iomem *)reg_addr);
3780}
3781
3782static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3783{
3784 CALC_REGADDR();
3785 writel(value, (void __iomem *)reg_addr);
3786}
3787
3788static void rdma_reset(struct slgt_info *info)
3789{
3790 unsigned int i;
3791
3792 /* set reset bit */
3793 wr_reg32(info, RDCSR, BIT1);
3794
3795 /* wait for enable bit cleared */
3796 for(i=0 ; i < 1000 ; i++)
3797 if (!(rd_reg32(info, RDCSR) & BIT0))
3798 break;
3799}
3800
3801static void tdma_reset(struct slgt_info *info)
3802{
3803 unsigned int i;
3804
3805 /* set reset bit */
3806 wr_reg32(info, TDCSR, BIT1);
3807
3808 /* wait for enable bit cleared */
3809 for(i=0 ; i < 1000 ; i++)
3810 if (!(rd_reg32(info, TDCSR) & BIT0))
3811 break;
3812}
3813
3814/*
3815 * enable internal loopback
3816 * TxCLK and RxCLK are generated from BRG
3817 * and TxD is looped back to RxD internally.
3818 */
3819static void enable_loopback(struct slgt_info *info)
3820{
3821 /* SCR (serial control) BIT2=loopback enable */
3822 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3823
3824 if (info->params.mode != MGSL_MODE_ASYNC) {
3825 /* CCR (clock control)
3826 * 07..05 tx clock source (010 = BRG)
3827 * 04..02 rx clock source (010 = BRG)
3828 * 01 auxclk enable (0 = disable)
3829 * 00 BRG enable (1 = enable)
3830 *
3831 * 0100 1001
3832 */
3833 wr_reg8(info, CCR, 0x49);
3834
3835 /* set speed if available, otherwise use default */
3836 if (info->params.clock_speed)
3837 set_rate(info, info->params.clock_speed);
3838 else
3839 set_rate(info, 3686400);
3840 }
3841}
3842
3843/*
3844 * set baud rate generator to specified rate
3845 */
3846static void set_rate(struct slgt_info *info, u32 rate)
3847{
3848 unsigned int div;
3849 unsigned int osc = info->base_clock;
3850
3851 /* div = osc/rate - 1
3852 *
3853 * Round div up if osc/rate is not integer to
3854 * force to next slowest rate.
3855 */
3856
3857 if (rate) {
3858 div = osc/rate;
3859 if (!(osc % rate) && div)
3860 div--;
3861 wr_reg16(info, BDR, (unsigned short)div);
3862 }
3863}
3864
3865static void rx_stop(struct slgt_info *info)
3866{
3867 unsigned short val;
3868
3869 /* disable and reset receiver */
3870 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3871 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3872 wr_reg16(info, RCR, val); /* clear reset bit */
3873
3874 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3875
3876 /* clear pending rx interrupts */
3877 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3878
3879 rdma_reset(info);
3880
3881 info->rx_enabled = false;
3882 info->rx_restart = false;
3883}
3884
3885static void rx_start(struct slgt_info *info)
3886{
3887 unsigned short val;
3888
3889 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3890
3891 /* clear pending rx overrun IRQ */
3892 wr_reg16(info, SSR, IRQ_RXOVER);
3893
3894 /* reset and disable receiver */
3895 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3896 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3897 wr_reg16(info, RCR, val); /* clear reset bit */
3898
3899 rdma_reset(info);
3900 reset_rbufs(info);
3901
3902 if (info->rx_pio) {
3903 /* rx request when rx FIFO not empty */
3904 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3905 slgt_irq_on(info, IRQ_RXDATA);
3906 if (info->params.mode == MGSL_MODE_ASYNC) {
3907 /* enable saving of rx status */
3908 wr_reg32(info, RDCSR, BIT6);
3909 }
3910 } else {
3911 /* rx request when rx FIFO half full */
3912 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3913 /* set 1st descriptor address */
3914 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3915
3916 if (info->params.mode != MGSL_MODE_ASYNC) {
3917 /* enable rx DMA and DMA interrupt */
3918 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3919 } else {
3920 /* enable saving of rx status, rx DMA and DMA interrupt */
3921 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3922 }
3923 }
3924
3925 slgt_irq_on(info, IRQ_RXOVER);
3926
3927 /* enable receiver */
3928 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3929
3930 info->rx_restart = false;
3931 info->rx_enabled = true;
3932}
3933
3934static void tx_start(struct slgt_info *info)
3935{
3936 if (!info->tx_enabled) {
3937 wr_reg16(info, TCR,
3938 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3939 info->tx_enabled = true;
3940 }
3941
3942 if (desc_count(info->tbufs[info->tbuf_start])) {
3943 info->drop_rts_on_tx_done = false;
3944
3945 if (info->params.mode != MGSL_MODE_ASYNC) {
3946 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3947 get_gtsignals(info);
3948 if (!(info->signals & SerialSignal_RTS)) {
3949 info->signals |= SerialSignal_RTS;
3950 set_gtsignals(info);
3951 info->drop_rts_on_tx_done = true;
3952 }
3953 }
3954
3955 slgt_irq_off(info, IRQ_TXDATA);
3956 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3957 /* clear tx idle and underrun status bits */
3958 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3959 } else {
3960 slgt_irq_off(info, IRQ_TXDATA);
3961 slgt_irq_on(info, IRQ_TXIDLE);
3962 /* clear tx idle status bit */
3963 wr_reg16(info, SSR, IRQ_TXIDLE);
3964 }
3965 /* set 1st descriptor address and start DMA */
3966 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3967 wr_reg32(info, TDCSR, BIT2 + BIT0);
3968 info->tx_active = true;
3969 }
3970}
3971
3972static void tx_stop(struct slgt_info *info)
3973{
3974 unsigned short val;
3975
3976 del_timer(&info->tx_timer);
3977
3978 tdma_reset(info);
3979
3980 /* reset and disable transmitter */
3981 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3982 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3983
3984 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3985
3986 /* clear tx idle and underrun status bit */
3987 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3988
3989 reset_tbufs(info);
3990
3991 info->tx_enabled = false;
3992 info->tx_active = false;
3993}
3994
3995static void reset_port(struct slgt_info *info)
3996{
3997 if (!info->reg_addr)
3998 return;
3999
4000 tx_stop(info);
4001 rx_stop(info);
4002
4003 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4004 set_gtsignals(info);
4005
4006 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4007}
4008
4009static void reset_adapter(struct slgt_info *info)
4010{
4011 int i;
4012 for (i=0; i < info->port_count; ++i) {
4013 if (info->port_array[i])
4014 reset_port(info->port_array[i]);
4015 }
4016}
4017
4018static void async_mode(struct slgt_info *info)
4019{
4020 unsigned short val;
4021
4022 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4023 tx_stop(info);
4024 rx_stop(info);
4025
4026 /* TCR (tx control)
4027 *
4028 * 15..13 mode, 010=async
4029 * 12..10 encoding, 000=NRZ
4030 * 09 parity enable
4031 * 08 1=odd parity, 0=even parity
4032 * 07 1=RTS driver control
4033 * 06 1=break enable
4034 * 05..04 character length
4035 * 00=5 bits
4036 * 01=6 bits
4037 * 10=7 bits
4038 * 11=8 bits
4039 * 03 0=1 stop bit, 1=2 stop bits
4040 * 02 reset
4041 * 01 enable
4042 * 00 auto-CTS enable
4043 */
4044 val = 0x4000;
4045
4046 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4047 val |= BIT7;
4048
4049 if (info->params.parity != ASYNC_PARITY_NONE) {
4050 val |= BIT9;
4051 if (info->params.parity == ASYNC_PARITY_ODD)
4052 val |= BIT8;
4053 }
4054
4055 switch (info->params.data_bits)
4056 {
4057 case 6: val |= BIT4; break;
4058 case 7: val |= BIT5; break;
4059 case 8: val |= BIT5 + BIT4; break;
4060 }
4061
4062 if (info->params.stop_bits != 1)
4063 val |= BIT3;
4064
4065 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4066 val |= BIT0;
4067
4068 wr_reg16(info, TCR, val);
4069
4070 /* RCR (rx control)
4071 *
4072 * 15..13 mode, 010=async
4073 * 12..10 encoding, 000=NRZ
4074 * 09 parity enable
4075 * 08 1=odd parity, 0=even parity
4076 * 07..06 reserved, must be 0
4077 * 05..04 character length
4078 * 00=5 bits
4079 * 01=6 bits
4080 * 10=7 bits
4081 * 11=8 bits
4082 * 03 reserved, must be zero
4083 * 02 reset
4084 * 01 enable
4085 * 00 auto-DCD enable
4086 */
4087 val = 0x4000;
4088
4089 if (info->params.parity != ASYNC_PARITY_NONE) {
4090 val |= BIT9;
4091 if (info->params.parity == ASYNC_PARITY_ODD)
4092 val |= BIT8;
4093 }
4094
4095 switch (info->params.data_bits)
4096 {
4097 case 6: val |= BIT4; break;
4098 case 7: val |= BIT5; break;
4099 case 8: val |= BIT5 + BIT4; break;
4100 }
4101
4102 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4103 val |= BIT0;
4104
4105 wr_reg16(info, RCR, val);
4106
4107 /* CCR (clock control)
4108 *
4109 * 07..05 011 = tx clock source is BRG/16
4110 * 04..02 010 = rx clock source is BRG
4111 * 01 0 = auxclk disabled
4112 * 00 1 = BRG enabled
4113 *
4114 * 0110 1001
4115 */
4116 wr_reg8(info, CCR, 0x69);
4117
4118 msc_set_vcr(info);
4119
4120 /* SCR (serial control)
4121 *
4122 * 15 1=tx req on FIFO half empty
4123 * 14 1=rx req on FIFO half full
4124 * 13 tx data IRQ enable
4125 * 12 tx idle IRQ enable
4126 * 11 rx break on IRQ enable
4127 * 10 rx data IRQ enable
4128 * 09 rx break off IRQ enable
4129 * 08 overrun IRQ enable
4130 * 07 DSR IRQ enable
4131 * 06 CTS IRQ enable
4132 * 05 DCD IRQ enable
4133 * 04 RI IRQ enable
4134 * 03 0=16x sampling, 1=8x sampling
4135 * 02 1=txd->rxd internal loopback enable
4136 * 01 reserved, must be zero
4137 * 00 1=master IRQ enable
4138 */
4139 val = BIT15 + BIT14 + BIT0;
4140 /* JCR[8] : 1 = x8 async mode feature available */
4141 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4142 ((info->base_clock < (info->params.data_rate * 16)) ||
4143 (info->base_clock % (info->params.data_rate * 16)))) {
4144 /* use 8x sampling */
4145 val |= BIT3;
4146 set_rate(info, info->params.data_rate * 8);
4147 } else {
4148 /* use 16x sampling */
4149 set_rate(info, info->params.data_rate * 16);
4150 }
4151 wr_reg16(info, SCR, val);
4152
4153 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4154
4155 if (info->params.loopback)
4156 enable_loopback(info);
4157}
4158
4159static void sync_mode(struct slgt_info *info)
4160{
4161 unsigned short val;
4162
4163 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4164 tx_stop(info);
4165 rx_stop(info);
4166
4167 /* TCR (tx control)
4168 *
4169 * 15..13 mode
4170 * 000=HDLC/SDLC
4171 * 001=raw bit synchronous
4172 * 010=asynchronous/isochronous
4173 * 011=monosync byte synchronous
4174 * 100=bisync byte synchronous
4175 * 101=xsync byte synchronous
4176 * 12..10 encoding
4177 * 09 CRC enable
4178 * 08 CRC32
4179 * 07 1=RTS driver control
4180 * 06 preamble enable
4181 * 05..04 preamble length
4182 * 03 share open/close flag
4183 * 02 reset
4184 * 01 enable
4185 * 00 auto-CTS enable
4186 */
4187 val = BIT2;
4188
4189 switch(info->params.mode) {
4190 case MGSL_MODE_XSYNC:
4191 val |= BIT15 + BIT13;
4192 break;
4193 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4194 case MGSL_MODE_BISYNC: val |= BIT15; break;
4195 case MGSL_MODE_RAW: val |= BIT13; break;
4196 }
4197 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4198 val |= BIT7;
4199
4200 switch(info->params.encoding)
4201 {
4202 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4203 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4204 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4205 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4206 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4207 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4208 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4209 }
4210
4211 switch (info->params.crc_type & HDLC_CRC_MASK)
4212 {
4213 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4214 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4215 }
4216
4217 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4218 val |= BIT6;
4219
4220 switch (info->params.preamble_length)
4221 {
4222 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4223 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4224 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4225 }
4226
4227 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4228 val |= BIT0;
4229
4230 wr_reg16(info, TCR, val);
4231
4232 /* TPR (transmit preamble) */
4233
4234 switch (info->params.preamble)
4235 {
4236 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4237 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4238 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4239 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4240 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4241 default: val = 0x7e; break;
4242 }
4243 wr_reg8(info, TPR, (unsigned char)val);
4244
4245 /* RCR (rx control)
4246 *
4247 * 15..13 mode
4248 * 000=HDLC/SDLC
4249 * 001=raw bit synchronous
4250 * 010=asynchronous/isochronous
4251 * 011=monosync byte synchronous
4252 * 100=bisync byte synchronous
4253 * 101=xsync byte synchronous
4254 * 12..10 encoding
4255 * 09 CRC enable
4256 * 08 CRC32
4257 * 07..03 reserved, must be 0
4258 * 02 reset
4259 * 01 enable
4260 * 00 auto-DCD enable
4261 */
4262 val = 0;
4263
4264 switch(info->params.mode) {
4265 case MGSL_MODE_XSYNC:
4266 val |= BIT15 + BIT13;
4267 break;
4268 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4269 case MGSL_MODE_BISYNC: val |= BIT15; break;
4270 case MGSL_MODE_RAW: val |= BIT13; break;
4271 }
4272
4273 switch(info->params.encoding)
4274 {
4275 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4276 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4277 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4278 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4279 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4280 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4281 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4282 }
4283
4284 switch (info->params.crc_type & HDLC_CRC_MASK)
4285 {
4286 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4287 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4288 }
4289
4290 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4291 val |= BIT0;
4292
4293 wr_reg16(info, RCR, val);
4294
4295 /* CCR (clock control)
4296 *
4297 * 07..05 tx clock source
4298 * 04..02 rx clock source
4299 * 01 auxclk enable
4300 * 00 BRG enable
4301 */
4302 val = 0;
4303
4304 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4305 {
4306 // when RxC source is DPLL, BRG generates 16X DPLL
4307 // reference clock, so take TxC from BRG/16 to get
4308 // transmit clock at actual data rate
4309 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4310 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4311 else
4312 val |= BIT6; /* 010, txclk = BRG */
4313 }
4314 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4315 val |= BIT7; /* 100, txclk = DPLL Input */
4316 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4317 val |= BIT5; /* 001, txclk = RXC Input */
4318
4319 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4320 val |= BIT3; /* 010, rxclk = BRG */
4321 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4322 val |= BIT4; /* 100, rxclk = DPLL */
4323 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4324 val |= BIT2; /* 001, rxclk = TXC Input */
4325
4326 if (info->params.clock_speed)
4327 val |= BIT1 + BIT0;
4328
4329 wr_reg8(info, CCR, (unsigned char)val);
4330
4331 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4332 {
4333 // program DPLL mode
4334 switch(info->params.encoding)
4335 {
4336 case HDLC_ENCODING_BIPHASE_MARK:
4337 case HDLC_ENCODING_BIPHASE_SPACE:
4338 val = BIT7; break;
4339 case HDLC_ENCODING_BIPHASE_LEVEL:
4340 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4341 val = BIT7 + BIT6; break;
4342 default: val = BIT6; // NRZ encodings
4343 }
4344 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4345
4346 // DPLL requires a 16X reference clock from BRG
4347 set_rate(info, info->params.clock_speed * 16);
4348 }
4349 else
4350 set_rate(info, info->params.clock_speed);
4351
4352 tx_set_idle(info);
4353
4354 msc_set_vcr(info);
4355
4356 /* SCR (serial control)
4357 *
4358 * 15 1=tx req on FIFO half empty
4359 * 14 1=rx req on FIFO half full
4360 * 13 tx data IRQ enable
4361 * 12 tx idle IRQ enable
4362 * 11 underrun IRQ enable
4363 * 10 rx data IRQ enable
4364 * 09 rx idle IRQ enable
4365 * 08 overrun IRQ enable
4366 * 07 DSR IRQ enable
4367 * 06 CTS IRQ enable
4368 * 05 DCD IRQ enable
4369 * 04 RI IRQ enable
4370 * 03 reserved, must be zero
4371 * 02 1=txd->rxd internal loopback enable
4372 * 01 reserved, must be zero
4373 * 00 1=master IRQ enable
4374 */
4375 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4376
4377 if (info->params.loopback)
4378 enable_loopback(info);
4379}
4380
4381/*
4382 * set transmit idle mode
4383 */
4384static void tx_set_idle(struct slgt_info *info)
4385{
4386 unsigned char val;
4387 unsigned short tcr;
4388
4389 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4390 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4391 */
4392 tcr = rd_reg16(info, TCR);
4393 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4394 /* disable preamble, set idle size to 16 bits */
4395 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4396 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4397 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4398 } else if (!(tcr & BIT6)) {
4399 /* preamble is disabled, set idle size to 8 bits */
4400 tcr &= ~(BIT5 + BIT4);
4401 }
4402 wr_reg16(info, TCR, tcr);
4403
4404 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4405 /* LSB of custom tx idle specified in tx idle register */
4406 val = (unsigned char)(info->idle_mode & 0xff);
4407 } else {
4408 /* standard 8 bit idle patterns */
4409 switch(info->idle_mode)
4410 {
4411 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4412 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4413 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4414 case HDLC_TXIDLE_ZEROS:
4415 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4416 default: val = 0xff;
4417 }
4418 }
4419
4420 wr_reg8(info, TIR, val);
4421}
4422
4423/*
4424 * get state of V24 status (input) signals
4425 */
4426static void get_gtsignals(struct slgt_info *info)
4427{
4428 unsigned short status = rd_reg16(info, SSR);
4429
4430 /* clear all serial signals except RTS and DTR */
4431 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4432
4433 if (status & BIT3)
4434 info->signals |= SerialSignal_DSR;
4435 if (status & BIT2)
4436 info->signals |= SerialSignal_CTS;
4437 if (status & BIT1)
4438 info->signals |= SerialSignal_DCD;
4439 if (status & BIT0)
4440 info->signals |= SerialSignal_RI;
4441}
4442
4443/*
4444 * set V.24 Control Register based on current configuration
4445 */
4446static void msc_set_vcr(struct slgt_info *info)
4447{
4448 unsigned char val = 0;
4449
4450 /* VCR (V.24 control)
4451 *
4452 * 07..04 serial IF select
4453 * 03 DTR
4454 * 02 RTS
4455 * 01 LL
4456 * 00 RL
4457 */
4458
4459 switch(info->if_mode & MGSL_INTERFACE_MASK)
4460 {
4461 case MGSL_INTERFACE_RS232:
4462 val |= BIT5; /* 0010 */
4463 break;
4464 case MGSL_INTERFACE_V35:
4465 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4466 break;
4467 case MGSL_INTERFACE_RS422:
4468 val |= BIT6; /* 0100 */
4469 break;
4470 }
4471
4472 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4473 val |= BIT4;
4474 if (info->signals & SerialSignal_DTR)
4475 val |= BIT3;
4476 if (info->signals & SerialSignal_RTS)
4477 val |= BIT2;
4478 if (info->if_mode & MGSL_INTERFACE_LL)
4479 val |= BIT1;
4480 if (info->if_mode & MGSL_INTERFACE_RL)
4481 val |= BIT0;
4482 wr_reg8(info, VCR, val);
4483}
4484
4485/*
4486 * set state of V24 control (output) signals
4487 */
4488static void set_gtsignals(struct slgt_info *info)
4489{
4490 unsigned char val = rd_reg8(info, VCR);
4491 if (info->signals & SerialSignal_DTR)
4492 val |= BIT3;
4493 else
4494 val &= ~BIT3;
4495 if (info->signals & SerialSignal_RTS)
4496 val |= BIT2;
4497 else
4498 val &= ~BIT2;
4499 wr_reg8(info, VCR, val);
4500}
4501
4502/*
4503 * free range of receive DMA buffers (i to last)
4504 */
4505static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4506{
4507 int done = 0;
4508
4509 while(!done) {
4510 /* reset current buffer for reuse */
4511 info->rbufs[i].status = 0;
4512 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4513 if (i == last)
4514 done = 1;
4515 if (++i == info->rbuf_count)
4516 i = 0;
4517 }
4518 info->rbuf_current = i;
4519}
4520
4521/*
4522 * mark all receive DMA buffers as free
4523 */
4524static void reset_rbufs(struct slgt_info *info)
4525{
4526 free_rbufs(info, 0, info->rbuf_count - 1);
4527 info->rbuf_fill_index = 0;
4528 info->rbuf_fill_count = 0;
4529}
4530
4531/*
4532 * pass receive HDLC frame to upper layer
4533 *
4534 * return true if frame available, otherwise false
4535 */
4536static bool rx_get_frame(struct slgt_info *info)
4537{
4538 unsigned int start, end;
4539 unsigned short status;
4540 unsigned int framesize = 0;
4541 unsigned long flags;
4542 struct tty_struct *tty = info->port.tty;
4543 unsigned char addr_field = 0xff;
4544 unsigned int crc_size = 0;
4545
4546 switch (info->params.crc_type & HDLC_CRC_MASK) {
4547 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4548 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4549 }
4550
4551check_again:
4552
4553 framesize = 0;
4554 addr_field = 0xff;
4555 start = end = info->rbuf_current;
4556
4557 for (;;) {
4558 if (!desc_complete(info->rbufs[end]))
4559 goto cleanup;
4560
4561 if (framesize == 0 && info->params.addr_filter != 0xff)
4562 addr_field = info->rbufs[end].buf[0];
4563
4564 framesize += desc_count(info->rbufs[end]);
4565
4566 if (desc_eof(info->rbufs[end]))
4567 break;
4568
4569 if (++end == info->rbuf_count)
4570 end = 0;
4571
4572 if (end == info->rbuf_current) {
4573 if (info->rx_enabled){
4574 spin_lock_irqsave(&info->lock,flags);
4575 rx_start(info);
4576 spin_unlock_irqrestore(&info->lock,flags);
4577 }
4578 goto cleanup;
4579 }
4580 }
4581
4582 /* status
4583 *
4584 * 15 buffer complete
4585 * 14..06 reserved
4586 * 05..04 residue
4587 * 02 eof (end of frame)
4588 * 01 CRC error
4589 * 00 abort
4590 */
4591 status = desc_status(info->rbufs[end]);
4592
4593 /* ignore CRC bit if not using CRC (bit is undefined) */
4594 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4595 status &= ~BIT1;
4596
4597 if (framesize == 0 ||
4598 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4599 free_rbufs(info, start, end);
4600 goto check_again;
4601 }
4602
4603 if (framesize < (2 + crc_size) || status & BIT0) {
4604 info->icount.rxshort++;
4605 framesize = 0;
4606 } else if (status & BIT1) {
4607 info->icount.rxcrc++;
4608 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4609 framesize = 0;
4610 }
4611
4612#if SYNCLINK_GENERIC_HDLC
4613 if (framesize == 0) {
4614 info->netdev->stats.rx_errors++;
4615 info->netdev->stats.rx_frame_errors++;
4616 }
4617#endif
4618
4619 DBGBH(("%s rx frame status=%04X size=%d\n",
4620 info->device_name, status, framesize));
4621 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4622
4623 if (framesize) {
4624 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4625 framesize -= crc_size;
4626 crc_size = 0;
4627 }
4628
4629 if (framesize > info->max_frame_size + crc_size)
4630 info->icount.rxlong++;
4631 else {
4632 /* copy dma buffer(s) to contiguous temp buffer */
4633 int copy_count = framesize;
4634 int i = start;
4635 unsigned char *p = info->tmp_rbuf;
4636 info->tmp_rbuf_count = framesize;
4637
4638 info->icount.rxok++;
4639
4640 while(copy_count) {
4641 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4642 memcpy(p, info->rbufs[i].buf, partial_count);
4643 p += partial_count;
4644 copy_count -= partial_count;
4645 if (++i == info->rbuf_count)
4646 i = 0;
4647 }
4648
4649 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4650 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4651 framesize++;
4652 }
4653
4654#if SYNCLINK_GENERIC_HDLC
4655 if (info->netcount)
4656 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4657 else
4658#endif
4659 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4660 }
4661 }
4662 free_rbufs(info, start, end);
4663 return true;
4664
4665cleanup:
4666 return false;
4667}
4668
4669/*
4670 * pass receive buffer (RAW synchronous mode) to tty layer
4671 * return true if buffer available, otherwise false
4672 */
4673static bool rx_get_buf(struct slgt_info *info)
4674{
4675 unsigned int i = info->rbuf_current;
4676 unsigned int count;
4677
4678 if (!desc_complete(info->rbufs[i]))
4679 return false;
4680 count = desc_count(info->rbufs[i]);
4681 switch(info->params.mode) {
4682 case MGSL_MODE_MONOSYNC:
4683 case MGSL_MODE_BISYNC:
4684 case MGSL_MODE_XSYNC:
4685 /* ignore residue in byte synchronous modes */
4686 if (desc_residue(info->rbufs[i]))
4687 count--;
4688 break;
4689 }
4690 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4691 DBGINFO(("rx_get_buf size=%d\n", count));
4692 if (count)
4693 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4694 info->flag_buf, count);
4695 free_rbufs(info, i, i);
4696 return true;
4697}
4698
4699static void reset_tbufs(struct slgt_info *info)
4700{
4701 unsigned int i;
4702 info->tbuf_current = 0;
4703 for (i=0 ; i < info->tbuf_count ; i++) {
4704 info->tbufs[i].status = 0;
4705 info->tbufs[i].count = 0;
4706 }
4707}
4708
4709/*
4710 * return number of free transmit DMA buffers
4711 */
4712static unsigned int free_tbuf_count(struct slgt_info *info)
4713{
4714 unsigned int count = 0;
4715 unsigned int i = info->tbuf_current;
4716
4717 do
4718 {
4719 if (desc_count(info->tbufs[i]))
4720 break; /* buffer in use */
4721 ++count;
4722 if (++i == info->tbuf_count)
4723 i=0;
4724 } while (i != info->tbuf_current);
4725
4726 /* if tx DMA active, last zero count buffer is in use */
4727 if (count && (rd_reg32(info, TDCSR) & BIT0))
4728 --count;
4729
4730 return count;
4731}
4732
4733/*
4734 * return number of bytes in unsent transmit DMA buffers
4735 * and the serial controller tx FIFO
4736 */
4737static unsigned int tbuf_bytes(struct slgt_info *info)
4738{
4739 unsigned int total_count = 0;
4740 unsigned int i = info->tbuf_current;
4741 unsigned int reg_value;
4742 unsigned int count;
4743 unsigned int active_buf_count = 0;
4744
4745 /*
4746 * Add descriptor counts for all tx DMA buffers.
4747 * If count is zero (cleared by DMA controller after read),
4748 * the buffer is complete or is actively being read from.
4749 *
4750 * Record buf_count of last buffer with zero count starting
4751 * from current ring position. buf_count is mirror
4752 * copy of count and is not cleared by serial controller.
4753 * If DMA controller is active, that buffer is actively
4754 * being read so add to total.
4755 */
4756 do {
4757 count = desc_count(info->tbufs[i]);
4758 if (count)
4759 total_count += count;
4760 else if (!total_count)
4761 active_buf_count = info->tbufs[i].buf_count;
4762 if (++i == info->tbuf_count)
4763 i = 0;
4764 } while (i != info->tbuf_current);
4765
4766 /* read tx DMA status register */
4767 reg_value = rd_reg32(info, TDCSR);
4768
4769 /* if tx DMA active, last zero count buffer is in use */
4770 if (reg_value & BIT0)
4771 total_count += active_buf_count;
4772
4773 /* add tx FIFO count = reg_value[15..8] */
4774 total_count += (reg_value >> 8) & 0xff;
4775
4776 /* if transmitter active add one byte for shift register */
4777 if (info->tx_active)
4778 total_count++;
4779
4780 return total_count;
4781}
4782
4783/*
4784 * load data into transmit DMA buffer ring and start transmitter if needed
4785 * return true if data accepted, otherwise false (buffers full)
4786 */
4787static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4788{
4789 unsigned short count;
4790 unsigned int i;
4791 struct slgt_desc *d;
4792
4793 /* check required buffer space */
4794 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4795 return false;
4796
4797 DBGDATA(info, buf, size, "tx");
4798
4799 /*
4800 * copy data to one or more DMA buffers in circular ring
4801 * tbuf_start = first buffer for this data
4802 * tbuf_current = next free buffer
4803 *
4804 * Copy all data before making data visible to DMA controller by
4805 * setting descriptor count of the first buffer.
4806 * This prevents an active DMA controller from reading the first DMA
4807 * buffers of a frame and stopping before the final buffers are filled.
4808 */
4809
4810 info->tbuf_start = i = info->tbuf_current;
4811
4812 while (size) {
4813 d = &info->tbufs[i];
4814
4815 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4816 memcpy(d->buf, buf, count);
4817
4818 size -= count;
4819 buf += count;
4820
4821 /*
4822 * set EOF bit for last buffer of HDLC frame or
4823 * for every buffer in raw mode
4824 */
4825 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4826 info->params.mode == MGSL_MODE_RAW)
4827 set_desc_eof(*d, 1);
4828 else
4829 set_desc_eof(*d, 0);
4830
4831 /* set descriptor count for all but first buffer */
4832 if (i != info->tbuf_start)
4833 set_desc_count(*d, count);
4834 d->buf_count = count;
4835
4836 if (++i == info->tbuf_count)
4837 i = 0;
4838 }
4839
4840 info->tbuf_current = i;
4841
4842 /* set first buffer count to make new data visible to DMA controller */
4843 d = &info->tbufs[info->tbuf_start];
4844 set_desc_count(*d, d->buf_count);
4845
4846 /* start transmitter if needed and update transmit timeout */
4847 if (!info->tx_active)
4848 tx_start(info);
4849 update_tx_timer(info);
4850
4851 return true;
4852}
4853
4854static int register_test(struct slgt_info *info)
4855{
4856 static unsigned short patterns[] =
4857 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4858 static unsigned int count = ARRAY_SIZE(patterns);
4859 unsigned int i;
4860 int rc = 0;
4861
4862 for (i=0 ; i < count ; i++) {
4863 wr_reg16(info, TIR, patterns[i]);
4864 wr_reg16(info, BDR, patterns[(i+1)%count]);
4865 if ((rd_reg16(info, TIR) != patterns[i]) ||
4866 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4867 rc = -ENODEV;
4868 break;
4869 }
4870 }
4871 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4872 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4873 return rc;
4874}
4875
4876static int irq_test(struct slgt_info *info)
4877{
4878 unsigned long timeout;
4879 unsigned long flags;
4880 struct tty_struct *oldtty = info->port.tty;
4881 u32 speed = info->params.data_rate;
4882
4883 info->params.data_rate = 921600;
4884 info->port.tty = NULL;
4885
4886 spin_lock_irqsave(&info->lock, flags);
4887 async_mode(info);
4888 slgt_irq_on(info, IRQ_TXIDLE);
4889
4890 /* enable transmitter */
4891 wr_reg16(info, TCR,
4892 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4893
4894 /* write one byte and wait for tx idle */
4895 wr_reg16(info, TDR, 0);
4896
4897 /* assume failure */
4898 info->init_error = DiagStatus_IrqFailure;
4899 info->irq_occurred = false;
4900
4901 spin_unlock_irqrestore(&info->lock, flags);
4902
4903 timeout=100;
4904 while(timeout-- && !info->irq_occurred)
4905 msleep_interruptible(10);
4906
4907 spin_lock_irqsave(&info->lock,flags);
4908 reset_port(info);
4909 spin_unlock_irqrestore(&info->lock,flags);
4910
4911 info->params.data_rate = speed;
4912 info->port.tty = oldtty;
4913
4914 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4915 return info->irq_occurred ? 0 : -ENODEV;
4916}
4917
4918static int loopback_test_rx(struct slgt_info *info)
4919{
4920 unsigned char *src, *dest;
4921 int count;
4922
4923 if (desc_complete(info->rbufs[0])) {
4924 count = desc_count(info->rbufs[0]);
4925 src = info->rbufs[0].buf;
4926 dest = info->tmp_rbuf;
4927
4928 for( ; count ; count-=2, src+=2) {
4929 /* src=data byte (src+1)=status byte */
4930 if (!(*(src+1) & (BIT9 + BIT8))) {
4931 *dest = *src;
4932 dest++;
4933 info->tmp_rbuf_count++;
4934 }
4935 }
4936 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4937 return 1;
4938 }
4939 return 0;
4940}
4941
4942static int loopback_test(struct slgt_info *info)
4943{
4944#define TESTFRAMESIZE 20
4945
4946 unsigned long timeout;
4947 u16 count;
4948 unsigned char buf[TESTFRAMESIZE];
4949 int rc = -ENODEV;
4950 unsigned long flags;
4951
4952 struct tty_struct *oldtty = info->port.tty;
4953 MGSL_PARAMS params;
4954
4955 memcpy(¶ms, &info->params, sizeof(params));
4956
4957 info->params.mode = MGSL_MODE_ASYNC;
4958 info->params.data_rate = 921600;
4959 info->params.loopback = 1;
4960 info->port.tty = NULL;
4961
4962 /* build and send transmit frame */
4963 for (count = 0; count < TESTFRAMESIZE; ++count)
4964 buf[count] = (unsigned char)count;
4965
4966 info->tmp_rbuf_count = 0;
4967 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4968
4969 /* program hardware for HDLC and enabled receiver */
4970 spin_lock_irqsave(&info->lock,flags);
4971 async_mode(info);
4972 rx_start(info);
4973 tx_load(info, buf, count);
4974 spin_unlock_irqrestore(&info->lock, flags);
4975
4976 /* wait for receive complete */
4977 for (timeout = 100; timeout; --timeout) {
4978 msleep_interruptible(10);
4979 if (loopback_test_rx(info)) {
4980 rc = 0;
4981 break;
4982 }
4983 }
4984
4985 /* verify received frame length and contents */
4986 if (!rc && (info->tmp_rbuf_count != count ||
4987 memcmp(buf, info->tmp_rbuf, count))) {
4988 rc = -ENODEV;
4989 }
4990
4991 spin_lock_irqsave(&info->lock,flags);
4992 reset_adapter(info);
4993 spin_unlock_irqrestore(&info->lock,flags);
4994
4995 memcpy(&info->params, ¶ms, sizeof(info->params));
4996 info->port.tty = oldtty;
4997
4998 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4999 return rc;
5000}
5001
5002static int adapter_test(struct slgt_info *info)
5003{
5004 DBGINFO(("testing %s\n", info->device_name));
5005 if (register_test(info) < 0) {
5006 printk("register test failure %s addr=%08X\n",
5007 info->device_name, info->phys_reg_addr);
5008 } else if (irq_test(info) < 0) {
5009 printk("IRQ test failure %s IRQ=%d\n",
5010 info->device_name, info->irq_level);
5011 } else if (loopback_test(info) < 0) {
5012 printk("loopback test failure %s\n", info->device_name);
5013 }
5014 return info->init_error;
5015}
5016
5017/*
5018 * transmit timeout handler
5019 */
5020static void tx_timeout(struct timer_list *t)
5021{
5022 struct slgt_info *info = from_timer(info, t, tx_timer);
5023 unsigned long flags;
5024
5025 DBGINFO(("%s tx_timeout\n", info->device_name));
5026 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5027 info->icount.txtimeout++;
5028 }
5029 spin_lock_irqsave(&info->lock,flags);
5030 tx_stop(info);
5031 spin_unlock_irqrestore(&info->lock,flags);
5032
5033#if SYNCLINK_GENERIC_HDLC
5034 if (info->netcount)
5035 hdlcdev_tx_done(info);
5036 else
5037#endif
5038 bh_transmit(info);
5039}
5040
5041/*
5042 * receive buffer polling timer
5043 */
5044static void rx_timeout(struct timer_list *t)
5045{
5046 struct slgt_info *info = from_timer(info, t, rx_timer);
5047 unsigned long flags;
5048
5049 DBGINFO(("%s rx_timeout\n", info->device_name));
5050 spin_lock_irqsave(&info->lock, flags);
5051 info->pending_bh |= BH_RECEIVE;
5052 spin_unlock_irqrestore(&info->lock, flags);
5053 bh_handler(&info->task);
5054}
5055