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1/*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/slab.h>
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/io.h>
37#include <linux/platform_device.h>
38#include <linux/init.h>
39#include <linux/sysrq.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/serial.h>
45#include <linux/serial_s3c.h>
46#include <linux/delay.h>
47#include <linux/clk.h>
48#include <linux/cpufreq.h>
49#include <linux/of.h>
50
51#include <asm/irq.h>
52
53#include "samsung.h"
54
55#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 !defined(MODULE)
57
58extern void printascii(const char *);
59
60__printf(1, 2)
61static void dbg(const char *fmt, ...)
62{
63 va_list va;
64 char buff[256];
65
66 va_start(va, fmt);
67 vscnprintf(buff, sizeof(buff), fmt, va);
68 va_end(va);
69
70 printascii(buff);
71}
72
73#else
74#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
75#endif
76
77/* UART name and device definitions */
78
79#define S3C24XX_SERIAL_NAME "ttySAC"
80#define S3C24XX_SERIAL_MAJOR 204
81#define S3C24XX_SERIAL_MINOR 64
82
83#define S3C24XX_TX_PIO 1
84#define S3C24XX_TX_DMA 2
85#define S3C24XX_RX_PIO 1
86#define S3C24XX_RX_DMA 2
87/* macros to change one thing to another */
88
89#define tx_enabled(port) ((port)->unused[0])
90#define rx_enabled(port) ((port)->unused[1])
91
92/* flag to ignore all characters coming in */
93#define RXSTAT_DUMMY_READ (0x10000000)
94
95static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
96{
97 return container_of(port, struct s3c24xx_uart_port, port);
98}
99
100/* translate a port to the device name */
101
102static inline const char *s3c24xx_serial_portname(struct uart_port *port)
103{
104 return to_platform_device(port->dev)->name;
105}
106
107static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
108{
109 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
110}
111
112/*
113 * s3c64xx and later SoC's include the interrupt mask and status registers in
114 * the controller itself, unlike the s3c24xx SoC's which have these registers
115 * in the interrupt controller. Check if the port type is s3c64xx or higher.
116 */
117static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
118{
119 return to_ourport(port)->info->type == PORT_S3C6400;
120}
121
122static void s3c24xx_serial_rx_enable(struct uart_port *port)
123{
124 unsigned long flags;
125 unsigned int ucon, ufcon;
126 int count = 10000;
127
128 spin_lock_irqsave(&port->lock, flags);
129
130 while (--count && !s3c24xx_serial_txempty_nofifo(port))
131 udelay(100);
132
133 ufcon = rd_regl(port, S3C2410_UFCON);
134 ufcon |= S3C2410_UFCON_RESETRX;
135 wr_regl(port, S3C2410_UFCON, ufcon);
136
137 ucon = rd_regl(port, S3C2410_UCON);
138 ucon |= S3C2410_UCON_RXIRQMODE;
139 wr_regl(port, S3C2410_UCON, ucon);
140
141 rx_enabled(port) = 1;
142 spin_unlock_irqrestore(&port->lock, flags);
143}
144
145static void s3c24xx_serial_rx_disable(struct uart_port *port)
146{
147 unsigned long flags;
148 unsigned int ucon;
149
150 spin_lock_irqsave(&port->lock, flags);
151
152 ucon = rd_regl(port, S3C2410_UCON);
153 ucon &= ~S3C2410_UCON_RXIRQMODE;
154 wr_regl(port, S3C2410_UCON, ucon);
155
156 rx_enabled(port) = 0;
157 spin_unlock_irqrestore(&port->lock, flags);
158}
159
160static void s3c24xx_serial_stop_tx(struct uart_port *port)
161{
162 struct s3c24xx_uart_port *ourport = to_ourport(port);
163 struct s3c24xx_uart_dma *dma = ourport->dma;
164 struct circ_buf *xmit = &port->state->xmit;
165 struct dma_tx_state state;
166 int count;
167
168 if (!tx_enabled(port))
169 return;
170
171 if (s3c24xx_serial_has_interrupt_mask(port))
172 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
173 else
174 disable_irq_nosync(ourport->tx_irq);
175
176 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
177 dmaengine_pause(dma->tx_chan);
178 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
179 dmaengine_terminate_all(dma->tx_chan);
180 dma_sync_single_for_cpu(ourport->port.dev,
181 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
182 async_tx_ack(dma->tx_desc);
183 count = dma->tx_bytes_requested - state.residue;
184 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
185 port->icount.tx += count;
186 }
187
188 tx_enabled(port) = 0;
189 ourport->tx_in_progress = 0;
190
191 if (port->flags & UPF_CONS_FLOW)
192 s3c24xx_serial_rx_enable(port);
193
194 ourport->tx_mode = 0;
195}
196
197static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
198
199static void s3c24xx_serial_tx_dma_complete(void *args)
200{
201 struct s3c24xx_uart_port *ourport = args;
202 struct uart_port *port = &ourport->port;
203 struct circ_buf *xmit = &port->state->xmit;
204 struct s3c24xx_uart_dma *dma = ourport->dma;
205 struct dma_tx_state state;
206 unsigned long flags;
207 int count;
208
209
210 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
211 count = dma->tx_bytes_requested - state.residue;
212 async_tx_ack(dma->tx_desc);
213
214 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
215 dma->tx_size, DMA_TO_DEVICE);
216
217 spin_lock_irqsave(&port->lock, flags);
218
219 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
220 port->icount.tx += count;
221 ourport->tx_in_progress = 0;
222
223 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
224 uart_write_wakeup(port);
225
226 s3c24xx_serial_start_next_tx(ourport);
227 spin_unlock_irqrestore(&port->lock, flags);
228}
229
230static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
231{
232 struct uart_port *port = &ourport->port;
233 u32 ucon;
234
235 /* Mask Tx interrupt */
236 if (s3c24xx_serial_has_interrupt_mask(port))
237 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
238 else
239 disable_irq_nosync(ourport->tx_irq);
240
241 /* Enable tx dma mode */
242 ucon = rd_regl(port, S3C2410_UCON);
243 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
244 ucon |= (dma_get_cache_alignment() >= 16) ?
245 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
246 ucon |= S3C64XX_UCON_TXMODE_DMA;
247 wr_regl(port, S3C2410_UCON, ucon);
248
249 ourport->tx_mode = S3C24XX_TX_DMA;
250}
251
252static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
253{
254 struct uart_port *port = &ourport->port;
255 u32 ucon, ufcon;
256
257 /* Set ufcon txtrig */
258 ourport->tx_in_progress = S3C24XX_TX_PIO;
259 ufcon = rd_regl(port, S3C2410_UFCON);
260 wr_regl(port, S3C2410_UFCON, ufcon);
261
262 /* Enable tx pio mode */
263 ucon = rd_regl(port, S3C2410_UCON);
264 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
265 ucon |= S3C64XX_UCON_TXMODE_CPU;
266 wr_regl(port, S3C2410_UCON, ucon);
267
268 /* Unmask Tx interrupt */
269 if (s3c24xx_serial_has_interrupt_mask(port))
270 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
271 S3C64XX_UINTM);
272 else
273 enable_irq(ourport->tx_irq);
274
275 ourport->tx_mode = S3C24XX_TX_PIO;
276}
277
278static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
279{
280 if (ourport->tx_mode != S3C24XX_TX_PIO)
281 enable_tx_pio(ourport);
282}
283
284static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
285 unsigned int count)
286{
287 struct uart_port *port = &ourport->port;
288 struct circ_buf *xmit = &port->state->xmit;
289 struct s3c24xx_uart_dma *dma = ourport->dma;
290
291
292 if (ourport->tx_mode != S3C24XX_TX_DMA)
293 enable_tx_dma(ourport);
294
295 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
296 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
297
298 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
299 dma->tx_size, DMA_TO_DEVICE);
300
301 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
302 dma->tx_transfer_addr, dma->tx_size,
303 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
304 if (!dma->tx_desc) {
305 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
306 return -EIO;
307 }
308
309 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
310 dma->tx_desc->callback_param = ourport;
311 dma->tx_bytes_requested = dma->tx_size;
312
313 ourport->tx_in_progress = S3C24XX_TX_DMA;
314 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
315 dma_async_issue_pending(dma->tx_chan);
316 return 0;
317}
318
319static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
320{
321 struct uart_port *port = &ourport->port;
322 struct circ_buf *xmit = &port->state->xmit;
323 unsigned long count;
324
325 /* Get data size up to the end of buffer */
326 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
327
328 if (!count) {
329 s3c24xx_serial_stop_tx(port);
330 return;
331 }
332
333 if (!ourport->dma || !ourport->dma->tx_chan ||
334 count < ourport->min_dma_size ||
335 xmit->tail & (dma_get_cache_alignment() - 1))
336 s3c24xx_serial_start_tx_pio(ourport);
337 else
338 s3c24xx_serial_start_tx_dma(ourport, count);
339}
340
341static void s3c24xx_serial_start_tx(struct uart_port *port)
342{
343 struct s3c24xx_uart_port *ourport = to_ourport(port);
344 struct circ_buf *xmit = &port->state->xmit;
345
346 if (!tx_enabled(port)) {
347 if (port->flags & UPF_CONS_FLOW)
348 s3c24xx_serial_rx_disable(port);
349
350 tx_enabled(port) = 1;
351 if (!ourport->dma || !ourport->dma->tx_chan)
352 s3c24xx_serial_start_tx_pio(ourport);
353 }
354
355 if (ourport->dma && ourport->dma->tx_chan) {
356 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
357 s3c24xx_serial_start_next_tx(ourport);
358 }
359}
360
361static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
362 struct tty_port *tty, int count)
363{
364 struct s3c24xx_uart_dma *dma = ourport->dma;
365 int copied;
366
367 if (!count)
368 return;
369
370 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
371 dma->rx_size, DMA_FROM_DEVICE);
372
373 ourport->port.icount.rx += count;
374 if (!tty) {
375 dev_err(ourport->port.dev, "No tty port\n");
376 return;
377 }
378 copied = tty_insert_flip_string(tty,
379 ((unsigned char *)(ourport->dma->rx_buf)), count);
380 if (copied != count) {
381 WARN_ON(1);
382 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
383 }
384}
385
386static void s3c24xx_serial_stop_rx(struct uart_port *port)
387{
388 struct s3c24xx_uart_port *ourport = to_ourport(port);
389 struct s3c24xx_uart_dma *dma = ourport->dma;
390 struct tty_port *t = &port->state->port;
391 struct dma_tx_state state;
392 enum dma_status dma_status;
393 unsigned int received;
394
395 if (rx_enabled(port)) {
396 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
397 if (s3c24xx_serial_has_interrupt_mask(port))
398 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
399 S3C64XX_UINTM);
400 else
401 disable_irq_nosync(ourport->rx_irq);
402 rx_enabled(port) = 0;
403 }
404 if (dma && dma->rx_chan) {
405 dmaengine_pause(dma->tx_chan);
406 dma_status = dmaengine_tx_status(dma->rx_chan,
407 dma->rx_cookie, &state);
408 if (dma_status == DMA_IN_PROGRESS ||
409 dma_status == DMA_PAUSED) {
410 received = dma->rx_bytes_requested - state.residue;
411 dmaengine_terminate_all(dma->rx_chan);
412 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
413 }
414 }
415}
416
417static inline struct s3c24xx_uart_info
418 *s3c24xx_port_to_info(struct uart_port *port)
419{
420 return to_ourport(port)->info;
421}
422
423static inline struct s3c2410_uartcfg
424 *s3c24xx_port_to_cfg(struct uart_port *port)
425{
426 struct s3c24xx_uart_port *ourport;
427
428 if (port->dev == NULL)
429 return NULL;
430
431 ourport = container_of(port, struct s3c24xx_uart_port, port);
432 return ourport->cfg;
433}
434
435static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
436 unsigned long ufstat)
437{
438 struct s3c24xx_uart_info *info = ourport->info;
439
440 if (ufstat & info->rx_fifofull)
441 return ourport->port.fifosize;
442
443 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
444}
445
446static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
447static void s3c24xx_serial_rx_dma_complete(void *args)
448{
449 struct s3c24xx_uart_port *ourport = args;
450 struct uart_port *port = &ourport->port;
451
452 struct s3c24xx_uart_dma *dma = ourport->dma;
453 struct tty_port *t = &port->state->port;
454 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
455
456 struct dma_tx_state state;
457 unsigned long flags;
458 int received;
459
460 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
461 received = dma->rx_bytes_requested - state.residue;
462 async_tx_ack(dma->rx_desc);
463
464 spin_lock_irqsave(&port->lock, flags);
465
466 if (received)
467 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
468
469 if (tty) {
470 tty_flip_buffer_push(t);
471 tty_kref_put(tty);
472 }
473
474 s3c64xx_start_rx_dma(ourport);
475
476 spin_unlock_irqrestore(&port->lock, flags);
477}
478
479static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
480{
481 struct s3c24xx_uart_dma *dma = ourport->dma;
482
483 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
484 dma->rx_size, DMA_FROM_DEVICE);
485
486 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
487 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
488 DMA_PREP_INTERRUPT);
489 if (!dma->rx_desc) {
490 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
491 return;
492 }
493
494 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
495 dma->rx_desc->callback_param = ourport;
496 dma->rx_bytes_requested = dma->rx_size;
497
498 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
499 dma_async_issue_pending(dma->rx_chan);
500}
501
502/* ? - where has parity gone?? */
503#define S3C2410_UERSTAT_PARITY (0x1000)
504
505static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
506{
507 struct uart_port *port = &ourport->port;
508 unsigned int ucon;
509
510 /* set Rx mode to DMA mode */
511 ucon = rd_regl(port, S3C2410_UCON);
512 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
513 S3C64XX_UCON_TIMEOUT_MASK |
514 S3C64XX_UCON_EMPTYINT_EN |
515 S3C64XX_UCON_DMASUS_EN |
516 S3C64XX_UCON_TIMEOUT_EN |
517 S3C64XX_UCON_RXMODE_MASK);
518 ucon |= S3C64XX_UCON_RXBURST_16 |
519 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
520 S3C64XX_UCON_EMPTYINT_EN |
521 S3C64XX_UCON_TIMEOUT_EN |
522 S3C64XX_UCON_RXMODE_DMA;
523 wr_regl(port, S3C2410_UCON, ucon);
524
525 ourport->rx_mode = S3C24XX_RX_DMA;
526}
527
528static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
529{
530 struct uart_port *port = &ourport->port;
531 unsigned int ucon;
532
533 /* set Rx mode to DMA mode */
534 ucon = rd_regl(port, S3C2410_UCON);
535 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
536 S3C64XX_UCON_EMPTYINT_EN |
537 S3C64XX_UCON_DMASUS_EN |
538 S3C64XX_UCON_TIMEOUT_EN |
539 S3C64XX_UCON_RXMODE_MASK);
540 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
541 S3C64XX_UCON_TIMEOUT_EN |
542 S3C64XX_UCON_RXMODE_CPU;
543 wr_regl(port, S3C2410_UCON, ucon);
544
545 ourport->rx_mode = S3C24XX_RX_PIO;
546}
547
548static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
549
550static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
551{
552 unsigned int utrstat, ufstat, received;
553 struct s3c24xx_uart_port *ourport = dev_id;
554 struct uart_port *port = &ourport->port;
555 struct s3c24xx_uart_dma *dma = ourport->dma;
556 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
557 struct tty_port *t = &port->state->port;
558 unsigned long flags;
559 struct dma_tx_state state;
560
561 utrstat = rd_regl(port, S3C2410_UTRSTAT);
562 ufstat = rd_regl(port, S3C2410_UFSTAT);
563
564 spin_lock_irqsave(&port->lock, flags);
565
566 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
567 s3c64xx_start_rx_dma(ourport);
568 if (ourport->rx_mode == S3C24XX_RX_PIO)
569 enable_rx_dma(ourport);
570 goto finish;
571 }
572
573 if (ourport->rx_mode == S3C24XX_RX_DMA) {
574 dmaengine_pause(dma->rx_chan);
575 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
576 dmaengine_terminate_all(dma->rx_chan);
577 received = dma->rx_bytes_requested - state.residue;
578 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
579
580 enable_rx_pio(ourport);
581 }
582
583 s3c24xx_serial_rx_drain_fifo(ourport);
584
585 if (tty) {
586 tty_flip_buffer_push(t);
587 tty_kref_put(tty);
588 }
589
590 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
591
592finish:
593 spin_unlock_irqrestore(&port->lock, flags);
594
595 return IRQ_HANDLED;
596}
597
598static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
599{
600 struct uart_port *port = &ourport->port;
601 unsigned int ufcon, ch, flag, ufstat, uerstat;
602 unsigned int fifocnt = 0;
603 int max_count = port->fifosize;
604
605 while (max_count-- > 0) {
606 /*
607 * Receive all characters known to be in FIFO
608 * before reading FIFO level again
609 */
610 if (fifocnt == 0) {
611 ufstat = rd_regl(port, S3C2410_UFSTAT);
612 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
613 if (fifocnt == 0)
614 break;
615 }
616 fifocnt--;
617
618 uerstat = rd_regl(port, S3C2410_UERSTAT);
619 ch = rd_regb(port, S3C2410_URXH);
620
621 if (port->flags & UPF_CONS_FLOW) {
622 int txe = s3c24xx_serial_txempty_nofifo(port);
623
624 if (rx_enabled(port)) {
625 if (!txe) {
626 rx_enabled(port) = 0;
627 continue;
628 }
629 } else {
630 if (txe) {
631 ufcon = rd_regl(port, S3C2410_UFCON);
632 ufcon |= S3C2410_UFCON_RESETRX;
633 wr_regl(port, S3C2410_UFCON, ufcon);
634 rx_enabled(port) = 1;
635 return;
636 }
637 continue;
638 }
639 }
640
641 /* insert the character into the buffer */
642
643 flag = TTY_NORMAL;
644 port->icount.rx++;
645
646 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
647 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
648 ch, uerstat);
649
650 /* check for break */
651 if (uerstat & S3C2410_UERSTAT_BREAK) {
652 dbg("break!\n");
653 port->icount.brk++;
654 if (uart_handle_break(port))
655 continue; /* Ignore character */
656 }
657
658 if (uerstat & S3C2410_UERSTAT_FRAME)
659 port->icount.frame++;
660 if (uerstat & S3C2410_UERSTAT_OVERRUN)
661 port->icount.overrun++;
662
663 uerstat &= port->read_status_mask;
664
665 if (uerstat & S3C2410_UERSTAT_BREAK)
666 flag = TTY_BREAK;
667 else if (uerstat & S3C2410_UERSTAT_PARITY)
668 flag = TTY_PARITY;
669 else if (uerstat & (S3C2410_UERSTAT_FRAME |
670 S3C2410_UERSTAT_OVERRUN))
671 flag = TTY_FRAME;
672 }
673
674 if (uart_handle_sysrq_char(port, ch))
675 continue; /* Ignore character */
676
677 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
678 ch, flag);
679 }
680
681 tty_flip_buffer_push(&port->state->port);
682}
683
684static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
685{
686 struct s3c24xx_uart_port *ourport = dev_id;
687 struct uart_port *port = &ourport->port;
688 unsigned long flags;
689
690 spin_lock_irqsave(&port->lock, flags);
691 s3c24xx_serial_rx_drain_fifo(ourport);
692 spin_unlock_irqrestore(&port->lock, flags);
693
694 return IRQ_HANDLED;
695}
696
697
698static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
699{
700 struct s3c24xx_uart_port *ourport = dev_id;
701
702 if (ourport->dma && ourport->dma->rx_chan)
703 return s3c24xx_serial_rx_chars_dma(dev_id);
704 return s3c24xx_serial_rx_chars_pio(dev_id);
705}
706
707static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
708{
709 struct s3c24xx_uart_port *ourport = id;
710 struct uart_port *port = &ourport->port;
711 struct circ_buf *xmit = &port->state->xmit;
712 unsigned long flags;
713 int count, dma_count = 0;
714
715 spin_lock_irqsave(&port->lock, flags);
716
717 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
718
719 if (ourport->dma && ourport->dma->tx_chan &&
720 count >= ourport->min_dma_size) {
721 int align = dma_get_cache_alignment() -
722 (xmit->tail & (dma_get_cache_alignment() - 1));
723 if (count-align >= ourport->min_dma_size) {
724 dma_count = count-align;
725 count = align;
726 }
727 }
728
729 if (port->x_char) {
730 wr_regb(port, S3C2410_UTXH, port->x_char);
731 port->icount.tx++;
732 port->x_char = 0;
733 goto out;
734 }
735
736 /* if there isn't anything more to transmit, or the uart is now
737 * stopped, disable the uart and exit
738 */
739
740 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
741 s3c24xx_serial_stop_tx(port);
742 goto out;
743 }
744
745 /* try and drain the buffer... */
746
747 if (count > port->fifosize) {
748 count = port->fifosize;
749 dma_count = 0;
750 }
751
752 while (!uart_circ_empty(xmit) && count > 0) {
753 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
754 break;
755
756 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
757 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
758 port->icount.tx++;
759 count--;
760 }
761
762 if (!count && dma_count) {
763 s3c24xx_serial_start_tx_dma(ourport, dma_count);
764 goto out;
765 }
766
767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
768 spin_unlock(&port->lock);
769 uart_write_wakeup(port);
770 spin_lock(&port->lock);
771 }
772
773 if (uart_circ_empty(xmit))
774 s3c24xx_serial_stop_tx(port);
775
776out:
777 spin_unlock_irqrestore(&port->lock, flags);
778 return IRQ_HANDLED;
779}
780
781/* interrupt handler for s3c64xx and later SoC's.*/
782static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
783{
784 struct s3c24xx_uart_port *ourport = id;
785 struct uart_port *port = &ourport->port;
786 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
787 irqreturn_t ret = IRQ_HANDLED;
788
789 if (pend & S3C64XX_UINTM_RXD_MSK) {
790 ret = s3c24xx_serial_rx_chars(irq, id);
791 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
792 }
793 if (pend & S3C64XX_UINTM_TXD_MSK) {
794 ret = s3c24xx_serial_tx_chars(irq, id);
795 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
796 }
797 return ret;
798}
799
800static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
801{
802 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
803 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
804 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
805
806 if (ufcon & S3C2410_UFCON_FIFOMODE) {
807 if ((ufstat & info->tx_fifomask) != 0 ||
808 (ufstat & info->tx_fifofull))
809 return 0;
810
811 return 1;
812 }
813
814 return s3c24xx_serial_txempty_nofifo(port);
815}
816
817/* no modem control lines */
818static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
819{
820 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
821
822 if (umstat & S3C2410_UMSTAT_CTS)
823 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
824 else
825 return TIOCM_CAR | TIOCM_DSR;
826}
827
828static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
829{
830 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
831
832 if (mctrl & TIOCM_RTS)
833 umcon |= S3C2410_UMCOM_RTS_LOW;
834 else
835 umcon &= ~S3C2410_UMCOM_RTS_LOW;
836
837 wr_regl(port, S3C2410_UMCON, umcon);
838}
839
840static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
841{
842 unsigned long flags;
843 unsigned int ucon;
844
845 spin_lock_irqsave(&port->lock, flags);
846
847 ucon = rd_regl(port, S3C2410_UCON);
848
849 if (break_state)
850 ucon |= S3C2410_UCON_SBREAK;
851 else
852 ucon &= ~S3C2410_UCON_SBREAK;
853
854 wr_regl(port, S3C2410_UCON, ucon);
855
856 spin_unlock_irqrestore(&port->lock, flags);
857}
858
859static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
860{
861 struct s3c24xx_uart_dma *dma = p->dma;
862 dma_cap_mask_t mask;
863 unsigned long flags;
864
865 /* Default slave configuration parameters */
866 dma->rx_conf.direction = DMA_DEV_TO_MEM;
867 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
868 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
869 dma->rx_conf.src_maxburst = 16;
870
871 dma->tx_conf.direction = DMA_MEM_TO_DEV;
872 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
873 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
874 if (dma_get_cache_alignment() >= 16)
875 dma->tx_conf.dst_maxburst = 16;
876 else
877 dma->tx_conf.dst_maxburst = 1;
878
879 dma_cap_zero(mask);
880 dma_cap_set(DMA_SLAVE, mask);
881
882 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
883 dma->rx_param, p->port.dev, "rx");
884 if (!dma->rx_chan)
885 return -ENODEV;
886
887 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
888
889 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
890 dma->tx_param, p->port.dev, "tx");
891 if (!dma->tx_chan) {
892 dma_release_channel(dma->rx_chan);
893 return -ENODEV;
894 }
895
896 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
897
898 /* RX buffer */
899 dma->rx_size = PAGE_SIZE;
900
901 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
902
903 if (!dma->rx_buf) {
904 dma_release_channel(dma->rx_chan);
905 dma_release_channel(dma->tx_chan);
906 return -ENOMEM;
907 }
908
909 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
910 dma->rx_size, DMA_FROM_DEVICE);
911
912 spin_lock_irqsave(&p->port.lock, flags);
913
914 /* TX buffer */
915 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
916 p->port.state->xmit.buf,
917 UART_XMIT_SIZE, DMA_TO_DEVICE);
918
919 spin_unlock_irqrestore(&p->port.lock, flags);
920
921 return 0;
922}
923
924static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
925{
926 struct s3c24xx_uart_dma *dma = p->dma;
927
928 if (dma->rx_chan) {
929 dmaengine_terminate_all(dma->rx_chan);
930 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
931 dma->rx_size, DMA_FROM_DEVICE);
932 kfree(dma->rx_buf);
933 dma_release_channel(dma->rx_chan);
934 dma->rx_chan = NULL;
935 }
936
937 if (dma->tx_chan) {
938 dmaengine_terminate_all(dma->tx_chan);
939 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
940 UART_XMIT_SIZE, DMA_TO_DEVICE);
941 dma_release_channel(dma->tx_chan);
942 dma->tx_chan = NULL;
943 }
944}
945
946static void s3c24xx_serial_shutdown(struct uart_port *port)
947{
948 struct s3c24xx_uart_port *ourport = to_ourport(port);
949
950 if (ourport->tx_claimed) {
951 if (!s3c24xx_serial_has_interrupt_mask(port))
952 free_irq(ourport->tx_irq, ourport);
953 tx_enabled(port) = 0;
954 ourport->tx_claimed = 0;
955 ourport->tx_mode = 0;
956 }
957
958 if (ourport->rx_claimed) {
959 if (!s3c24xx_serial_has_interrupt_mask(port))
960 free_irq(ourport->rx_irq, ourport);
961 ourport->rx_claimed = 0;
962 rx_enabled(port) = 0;
963 }
964
965 /* Clear pending interrupts and mask all interrupts */
966 if (s3c24xx_serial_has_interrupt_mask(port)) {
967 free_irq(port->irq, ourport);
968
969 wr_regl(port, S3C64XX_UINTP, 0xf);
970 wr_regl(port, S3C64XX_UINTM, 0xf);
971 }
972
973 if (ourport->dma)
974 s3c24xx_serial_release_dma(ourport);
975
976 ourport->tx_in_progress = 0;
977}
978
979static int s3c24xx_serial_startup(struct uart_port *port)
980{
981 struct s3c24xx_uart_port *ourport = to_ourport(port);
982 int ret;
983
984 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
985 port, (unsigned long long)port->mapbase, port->membase);
986
987 rx_enabled(port) = 1;
988
989 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
990 s3c24xx_serial_portname(port), ourport);
991
992 if (ret != 0) {
993 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
994 return ret;
995 }
996
997 ourport->rx_claimed = 1;
998
999 dbg("requesting tx irq...\n");
1000
1001 tx_enabled(port) = 1;
1002
1003 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1004 s3c24xx_serial_portname(port), ourport);
1005
1006 if (ret) {
1007 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1008 goto err;
1009 }
1010
1011 ourport->tx_claimed = 1;
1012
1013 dbg("s3c24xx_serial_startup ok\n");
1014
1015 /* the port reset code should have done the correct
1016 * register setup for the port controls */
1017
1018 return ret;
1019
1020err:
1021 s3c24xx_serial_shutdown(port);
1022 return ret;
1023}
1024
1025static int s3c64xx_serial_startup(struct uart_port *port)
1026{
1027 struct s3c24xx_uart_port *ourport = to_ourport(port);
1028 unsigned long flags;
1029 unsigned int ufcon;
1030 int ret;
1031
1032 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1033 port, (unsigned long long)port->mapbase, port->membase);
1034
1035 wr_regl(port, S3C64XX_UINTM, 0xf);
1036 if (ourport->dma) {
1037 ret = s3c24xx_serial_request_dma(ourport);
1038 if (ret < 0) {
1039 dev_warn(port->dev,
1040 "DMA request failed, DMA will not be used\n");
1041 devm_kfree(port->dev, ourport->dma);
1042 ourport->dma = NULL;
1043 }
1044 }
1045
1046 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1047 s3c24xx_serial_portname(port), ourport);
1048 if (ret) {
1049 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1050 return ret;
1051 }
1052
1053 /* For compatibility with s3c24xx Soc's */
1054 rx_enabled(port) = 1;
1055 ourport->rx_claimed = 1;
1056 tx_enabled(port) = 0;
1057 ourport->tx_claimed = 1;
1058
1059 spin_lock_irqsave(&port->lock, flags);
1060
1061 ufcon = rd_regl(port, S3C2410_UFCON);
1062 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1063 if (!uart_console(port))
1064 ufcon |= S3C2410_UFCON_RESETTX;
1065 wr_regl(port, S3C2410_UFCON, ufcon);
1066
1067 enable_rx_pio(ourport);
1068
1069 spin_unlock_irqrestore(&port->lock, flags);
1070
1071 /* Enable Rx Interrupt */
1072 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1073
1074 dbg("s3c64xx_serial_startup ok\n");
1075 return ret;
1076}
1077
1078/* power power management control */
1079
1080static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1081 unsigned int old)
1082{
1083 struct s3c24xx_uart_port *ourport = to_ourport(port);
1084 int timeout = 10000;
1085
1086 ourport->pm_level = level;
1087
1088 switch (level) {
1089 case 3:
1090 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1091 udelay(100);
1092
1093 if (!IS_ERR(ourport->baudclk))
1094 clk_disable_unprepare(ourport->baudclk);
1095
1096 clk_disable_unprepare(ourport->clk);
1097 break;
1098
1099 case 0:
1100 clk_prepare_enable(ourport->clk);
1101
1102 if (!IS_ERR(ourport->baudclk))
1103 clk_prepare_enable(ourport->baudclk);
1104
1105 break;
1106 default:
1107 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1108 }
1109}
1110
1111/* baud rate calculation
1112 *
1113 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1114 * of different sources, including the peripheral clock ("pclk") and an
1115 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1116 * with a programmable extra divisor.
1117 *
1118 * The following code goes through the clock sources, and calculates the
1119 * baud clocks (and the resultant actual baud rates) and then tries to
1120 * pick the closest one and select that.
1121 *
1122*/
1123
1124#define MAX_CLK_NAME_LENGTH 15
1125
1126static inline int s3c24xx_serial_getsource(struct uart_port *port)
1127{
1128 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1129 unsigned int ucon;
1130
1131 if (info->num_clks == 1)
1132 return 0;
1133
1134 ucon = rd_regl(port, S3C2410_UCON);
1135 ucon &= info->clksel_mask;
1136 return ucon >> info->clksel_shift;
1137}
1138
1139static void s3c24xx_serial_setsource(struct uart_port *port,
1140 unsigned int clk_sel)
1141{
1142 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1143 unsigned int ucon;
1144
1145 if (info->num_clks == 1)
1146 return;
1147
1148 ucon = rd_regl(port, S3C2410_UCON);
1149 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1150 return;
1151
1152 ucon &= ~info->clksel_mask;
1153 ucon |= clk_sel << info->clksel_shift;
1154 wr_regl(port, S3C2410_UCON, ucon);
1155}
1156
1157static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1158 unsigned int req_baud, struct clk **best_clk,
1159 unsigned int *clk_num)
1160{
1161 struct s3c24xx_uart_info *info = ourport->info;
1162 struct clk *clk;
1163 unsigned long rate;
1164 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1165 char clkname[MAX_CLK_NAME_LENGTH];
1166 int calc_deviation, deviation = (1 << 30) - 1;
1167
1168 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1169 ourport->info->def_clk_sel;
1170 for (cnt = 0; cnt < info->num_clks; cnt++) {
1171 if (!(clk_sel & (1 << cnt)))
1172 continue;
1173
1174 sprintf(clkname, "clk_uart_baud%d", cnt);
1175 clk = clk_get(ourport->port.dev, clkname);
1176 if (IS_ERR(clk))
1177 continue;
1178
1179 rate = clk_get_rate(clk);
1180 if (!rate)
1181 continue;
1182
1183 if (ourport->info->has_divslot) {
1184 unsigned long div = rate / req_baud;
1185
1186 /* The UDIVSLOT register on the newer UARTs allows us to
1187 * get a divisor adjustment of 1/16th on the baud clock.
1188 *
1189 * We don't keep the UDIVSLOT value (the 16ths we
1190 * calculated by not multiplying the baud by 16) as it
1191 * is easy enough to recalculate.
1192 */
1193
1194 quot = div / 16;
1195 baud = rate / div;
1196 } else {
1197 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1198 baud = rate / (quot * 16);
1199 }
1200 quot--;
1201
1202 calc_deviation = req_baud - baud;
1203 if (calc_deviation < 0)
1204 calc_deviation = -calc_deviation;
1205
1206 if (calc_deviation < deviation) {
1207 *best_clk = clk;
1208 best_quot = quot;
1209 *clk_num = cnt;
1210 deviation = calc_deviation;
1211 }
1212 }
1213
1214 return best_quot;
1215}
1216
1217/* udivslot_table[]
1218 *
1219 * This table takes the fractional value of the baud divisor and gives
1220 * the recommended setting for the UDIVSLOT register.
1221 */
1222static u16 udivslot_table[16] = {
1223 [0] = 0x0000,
1224 [1] = 0x0080,
1225 [2] = 0x0808,
1226 [3] = 0x0888,
1227 [4] = 0x2222,
1228 [5] = 0x4924,
1229 [6] = 0x4A52,
1230 [7] = 0x54AA,
1231 [8] = 0x5555,
1232 [9] = 0xD555,
1233 [10] = 0xD5D5,
1234 [11] = 0xDDD5,
1235 [12] = 0xDDDD,
1236 [13] = 0xDFDD,
1237 [14] = 0xDFDF,
1238 [15] = 0xFFDF,
1239};
1240
1241static void s3c24xx_serial_set_termios(struct uart_port *port,
1242 struct ktermios *termios,
1243 struct ktermios *old)
1244{
1245 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1246 struct s3c24xx_uart_port *ourport = to_ourport(port);
1247 struct clk *clk = ERR_PTR(-EINVAL);
1248 unsigned long flags;
1249 unsigned int baud, quot, clk_sel = 0;
1250 unsigned int ulcon;
1251 unsigned int umcon;
1252 unsigned int udivslot = 0;
1253
1254 /*
1255 * We don't support modem control lines.
1256 */
1257 termios->c_cflag &= ~(HUPCL | CMSPAR);
1258 termios->c_cflag |= CLOCAL;
1259
1260 /*
1261 * Ask the core to calculate the divisor for us.
1262 */
1263
1264 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1265 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1266 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1267 quot = port->custom_divisor;
1268 if (IS_ERR(clk))
1269 return;
1270
1271 /* check to see if we need to change clock source */
1272
1273 if (ourport->baudclk != clk) {
1274 clk_prepare_enable(clk);
1275
1276 s3c24xx_serial_setsource(port, clk_sel);
1277
1278 if (!IS_ERR(ourport->baudclk)) {
1279 clk_disable_unprepare(ourport->baudclk);
1280 ourport->baudclk = ERR_PTR(-EINVAL);
1281 }
1282
1283 ourport->baudclk = clk;
1284 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1285 }
1286
1287 if (ourport->info->has_divslot) {
1288 unsigned int div = ourport->baudclk_rate / baud;
1289
1290 if (cfg->has_fracval) {
1291 udivslot = (div & 15);
1292 dbg("fracval = %04x\n", udivslot);
1293 } else {
1294 udivslot = udivslot_table[div & 15];
1295 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1296 }
1297 }
1298
1299 switch (termios->c_cflag & CSIZE) {
1300 case CS5:
1301 dbg("config: 5bits/char\n");
1302 ulcon = S3C2410_LCON_CS5;
1303 break;
1304 case CS6:
1305 dbg("config: 6bits/char\n");
1306 ulcon = S3C2410_LCON_CS6;
1307 break;
1308 case CS7:
1309 dbg("config: 7bits/char\n");
1310 ulcon = S3C2410_LCON_CS7;
1311 break;
1312 case CS8:
1313 default:
1314 dbg("config: 8bits/char\n");
1315 ulcon = S3C2410_LCON_CS8;
1316 break;
1317 }
1318
1319 /* preserve original lcon IR settings */
1320 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1321
1322 if (termios->c_cflag & CSTOPB)
1323 ulcon |= S3C2410_LCON_STOPB;
1324
1325 if (termios->c_cflag & PARENB) {
1326 if (termios->c_cflag & PARODD)
1327 ulcon |= S3C2410_LCON_PODD;
1328 else
1329 ulcon |= S3C2410_LCON_PEVEN;
1330 } else {
1331 ulcon |= S3C2410_LCON_PNONE;
1332 }
1333
1334 spin_lock_irqsave(&port->lock, flags);
1335
1336 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1337 ulcon, quot, udivslot);
1338
1339 wr_regl(port, S3C2410_ULCON, ulcon);
1340 wr_regl(port, S3C2410_UBRDIV, quot);
1341
1342 umcon = rd_regl(port, S3C2410_UMCON);
1343 if (termios->c_cflag & CRTSCTS) {
1344 umcon |= S3C2410_UMCOM_AFC;
1345 /* Disable RTS when RX FIFO contains 63 bytes */
1346 umcon &= ~S3C2412_UMCON_AFC_8;
1347 } else {
1348 umcon &= ~S3C2410_UMCOM_AFC;
1349 }
1350 wr_regl(port, S3C2410_UMCON, umcon);
1351
1352 if (ourport->info->has_divslot)
1353 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1354
1355 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1356 rd_regl(port, S3C2410_ULCON),
1357 rd_regl(port, S3C2410_UCON),
1358 rd_regl(port, S3C2410_UFCON));
1359
1360 /*
1361 * Update the per-port timeout.
1362 */
1363 uart_update_timeout(port, termios->c_cflag, baud);
1364
1365 /*
1366 * Which character status flags are we interested in?
1367 */
1368 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1369 if (termios->c_iflag & INPCK)
1370 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1371 S3C2410_UERSTAT_PARITY;
1372 /*
1373 * Which character status flags should we ignore?
1374 */
1375 port->ignore_status_mask = 0;
1376 if (termios->c_iflag & IGNPAR)
1377 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1378 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1379 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1380
1381 /*
1382 * Ignore all characters if CREAD is not set.
1383 */
1384 if ((termios->c_cflag & CREAD) == 0)
1385 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1386
1387 spin_unlock_irqrestore(&port->lock, flags);
1388}
1389
1390static const char *s3c24xx_serial_type(struct uart_port *port)
1391{
1392 switch (port->type) {
1393 case PORT_S3C2410:
1394 return "S3C2410";
1395 case PORT_S3C2440:
1396 return "S3C2440";
1397 case PORT_S3C2412:
1398 return "S3C2412";
1399 case PORT_S3C6400:
1400 return "S3C6400/10";
1401 default:
1402 return NULL;
1403 }
1404}
1405
1406#define MAP_SIZE (0x100)
1407
1408static void s3c24xx_serial_release_port(struct uart_port *port)
1409{
1410 release_mem_region(port->mapbase, MAP_SIZE);
1411}
1412
1413static int s3c24xx_serial_request_port(struct uart_port *port)
1414{
1415 const char *name = s3c24xx_serial_portname(port);
1416 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1417}
1418
1419static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1420{
1421 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1422
1423 if (flags & UART_CONFIG_TYPE &&
1424 s3c24xx_serial_request_port(port) == 0)
1425 port->type = info->type;
1426}
1427
1428/*
1429 * verify the new serial_struct (for TIOCSSERIAL).
1430 */
1431static int
1432s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1433{
1434 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1435
1436 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1437 return -EINVAL;
1438
1439 return 0;
1440}
1441
1442
1443#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1444
1445static struct console s3c24xx_serial_console;
1446
1447static int __init s3c24xx_serial_console_init(void)
1448{
1449 register_console(&s3c24xx_serial_console);
1450 return 0;
1451}
1452console_initcall(s3c24xx_serial_console_init);
1453
1454#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1455#else
1456#define S3C24XX_SERIAL_CONSOLE NULL
1457#endif
1458
1459#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1460static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1461static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1462 unsigned char c);
1463#endif
1464
1465static struct uart_ops s3c24xx_serial_ops = {
1466 .pm = s3c24xx_serial_pm,
1467 .tx_empty = s3c24xx_serial_tx_empty,
1468 .get_mctrl = s3c24xx_serial_get_mctrl,
1469 .set_mctrl = s3c24xx_serial_set_mctrl,
1470 .stop_tx = s3c24xx_serial_stop_tx,
1471 .start_tx = s3c24xx_serial_start_tx,
1472 .stop_rx = s3c24xx_serial_stop_rx,
1473 .break_ctl = s3c24xx_serial_break_ctl,
1474 .startup = s3c24xx_serial_startup,
1475 .shutdown = s3c24xx_serial_shutdown,
1476 .set_termios = s3c24xx_serial_set_termios,
1477 .type = s3c24xx_serial_type,
1478 .release_port = s3c24xx_serial_release_port,
1479 .request_port = s3c24xx_serial_request_port,
1480 .config_port = s3c24xx_serial_config_port,
1481 .verify_port = s3c24xx_serial_verify_port,
1482#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1483 .poll_get_char = s3c24xx_serial_get_poll_char,
1484 .poll_put_char = s3c24xx_serial_put_poll_char,
1485#endif
1486};
1487
1488static struct uart_driver s3c24xx_uart_drv = {
1489 .owner = THIS_MODULE,
1490 .driver_name = "s3c2410_serial",
1491 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1492 .cons = S3C24XX_SERIAL_CONSOLE,
1493 .dev_name = S3C24XX_SERIAL_NAME,
1494 .major = S3C24XX_SERIAL_MAJOR,
1495 .minor = S3C24XX_SERIAL_MINOR,
1496};
1497
1498#define __PORT_LOCK_UNLOCKED(i) \
1499 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1500static struct s3c24xx_uart_port
1501s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1502 [0] = {
1503 .port = {
1504 .lock = __PORT_LOCK_UNLOCKED(0),
1505 .iotype = UPIO_MEM,
1506 .uartclk = 0,
1507 .fifosize = 16,
1508 .ops = &s3c24xx_serial_ops,
1509 .flags = UPF_BOOT_AUTOCONF,
1510 .line = 0,
1511 }
1512 },
1513 [1] = {
1514 .port = {
1515 .lock = __PORT_LOCK_UNLOCKED(1),
1516 .iotype = UPIO_MEM,
1517 .uartclk = 0,
1518 .fifosize = 16,
1519 .ops = &s3c24xx_serial_ops,
1520 .flags = UPF_BOOT_AUTOCONF,
1521 .line = 1,
1522 }
1523 },
1524#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1525
1526 [2] = {
1527 .port = {
1528 .lock = __PORT_LOCK_UNLOCKED(2),
1529 .iotype = UPIO_MEM,
1530 .uartclk = 0,
1531 .fifosize = 16,
1532 .ops = &s3c24xx_serial_ops,
1533 .flags = UPF_BOOT_AUTOCONF,
1534 .line = 2,
1535 }
1536 },
1537#endif
1538#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1539 [3] = {
1540 .port = {
1541 .lock = __PORT_LOCK_UNLOCKED(3),
1542 .iotype = UPIO_MEM,
1543 .uartclk = 0,
1544 .fifosize = 16,
1545 .ops = &s3c24xx_serial_ops,
1546 .flags = UPF_BOOT_AUTOCONF,
1547 .line = 3,
1548 }
1549 }
1550#endif
1551};
1552#undef __PORT_LOCK_UNLOCKED
1553
1554/* s3c24xx_serial_resetport
1555 *
1556 * reset the fifos and other the settings.
1557*/
1558
1559static void s3c24xx_serial_resetport(struct uart_port *port,
1560 struct s3c2410_uartcfg *cfg)
1561{
1562 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1563 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1564 unsigned int ucon_mask;
1565
1566 ucon_mask = info->clksel_mask;
1567 if (info->type == PORT_S3C2440)
1568 ucon_mask |= S3C2440_UCON0_DIVMASK;
1569
1570 ucon &= ucon_mask;
1571 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1572
1573 /* reset both fifos */
1574 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1575 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1576
1577 /* some delay is required after fifo reset */
1578 udelay(1);
1579}
1580
1581
1582#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1583
1584static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1585 unsigned long val, void *data)
1586{
1587 struct s3c24xx_uart_port *port;
1588 struct uart_port *uport;
1589
1590 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1591 uport = &port->port;
1592
1593 /* check to see if port is enabled */
1594
1595 if (port->pm_level != 0)
1596 return 0;
1597
1598 /* try and work out if the baudrate is changing, we can detect
1599 * a change in rate, but we do not have support for detecting
1600 * a disturbance in the clock-rate over the change.
1601 */
1602
1603 if (IS_ERR(port->baudclk))
1604 goto exit;
1605
1606 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1607 goto exit;
1608
1609 if (val == CPUFREQ_PRECHANGE) {
1610 /* we should really shut the port down whilst the
1611 * frequency change is in progress. */
1612
1613 } else if (val == CPUFREQ_POSTCHANGE) {
1614 struct ktermios *termios;
1615 struct tty_struct *tty;
1616
1617 if (uport->state == NULL)
1618 goto exit;
1619
1620 tty = uport->state->port.tty;
1621
1622 if (tty == NULL)
1623 goto exit;
1624
1625 termios = &tty->termios;
1626
1627 if (termios == NULL) {
1628 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1629 goto exit;
1630 }
1631
1632 s3c24xx_serial_set_termios(uport, termios, NULL);
1633 }
1634
1635exit:
1636 return 0;
1637}
1638
1639static inline int
1640s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1641{
1642 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1643
1644 return cpufreq_register_notifier(&port->freq_transition,
1645 CPUFREQ_TRANSITION_NOTIFIER);
1646}
1647
1648static inline void
1649s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1650{
1651 cpufreq_unregister_notifier(&port->freq_transition,
1652 CPUFREQ_TRANSITION_NOTIFIER);
1653}
1654
1655#else
1656static inline int
1657s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1658{
1659 return 0;
1660}
1661
1662static inline void
1663s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1664{
1665}
1666#endif
1667
1668/* s3c24xx_serial_init_port
1669 *
1670 * initialise a single serial port from the platform device given
1671 */
1672
1673static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1674 struct platform_device *platdev)
1675{
1676 struct uart_port *port = &ourport->port;
1677 struct s3c2410_uartcfg *cfg = ourport->cfg;
1678 struct resource *res;
1679 int ret;
1680
1681 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1682
1683 if (platdev == NULL)
1684 return -ENODEV;
1685
1686 if (port->mapbase != 0)
1687 return -EINVAL;
1688
1689 /* setup info for port */
1690 port->dev = &platdev->dev;
1691
1692 /* Startup sequence is different for s3c64xx and higher SoC's */
1693 if (s3c24xx_serial_has_interrupt_mask(port))
1694 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1695
1696 port->uartclk = 1;
1697
1698 if (cfg->uart_flags & UPF_CONS_FLOW) {
1699 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1700 port->flags |= UPF_CONS_FLOW;
1701 }
1702
1703 /* sort our the physical and virtual addresses for each UART */
1704
1705 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1706 if (res == NULL) {
1707 dev_err(port->dev, "failed to find memory resource for uart\n");
1708 return -EINVAL;
1709 }
1710
1711 dbg("resource %pR)\n", res);
1712
1713 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1714 if (!port->membase) {
1715 dev_err(port->dev, "failed to remap controller address\n");
1716 return -EBUSY;
1717 }
1718
1719 port->mapbase = res->start;
1720 ret = platform_get_irq(platdev, 0);
1721 if (ret < 0)
1722 port->irq = 0;
1723 else {
1724 port->irq = ret;
1725 ourport->rx_irq = ret;
1726 ourport->tx_irq = ret + 1;
1727 }
1728
1729 ret = platform_get_irq(platdev, 1);
1730 if (ret > 0)
1731 ourport->tx_irq = ret;
1732 /*
1733 * DMA is currently supported only on DT platforms, if DMA properties
1734 * are specified.
1735 */
1736 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1737 "dmas", NULL)) {
1738 ourport->dma = devm_kzalloc(port->dev,
1739 sizeof(*ourport->dma),
1740 GFP_KERNEL);
1741 if (!ourport->dma) {
1742 ret = -ENOMEM;
1743 goto err;
1744 }
1745 }
1746
1747 ourport->clk = clk_get(&platdev->dev, "uart");
1748 if (IS_ERR(ourport->clk)) {
1749 pr_err("%s: Controller clock not found\n",
1750 dev_name(&platdev->dev));
1751 ret = PTR_ERR(ourport->clk);
1752 goto err;
1753 }
1754
1755 ret = clk_prepare_enable(ourport->clk);
1756 if (ret) {
1757 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1758 clk_put(ourport->clk);
1759 goto err;
1760 }
1761
1762 /* Keep all interrupts masked and cleared */
1763 if (s3c24xx_serial_has_interrupt_mask(port)) {
1764 wr_regl(port, S3C64XX_UINTM, 0xf);
1765 wr_regl(port, S3C64XX_UINTP, 0xf);
1766 wr_regl(port, S3C64XX_UINTSP, 0xf);
1767 }
1768
1769 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1770 &port->mapbase, port->membase, port->irq,
1771 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1772
1773 /* reset the fifos (and setup the uart) */
1774 s3c24xx_serial_resetport(port, cfg);
1775
1776 return 0;
1777
1778err:
1779 port->mapbase = 0;
1780 return ret;
1781}
1782
1783/* Device driver serial port probe */
1784
1785static const struct of_device_id s3c24xx_uart_dt_match[];
1786static int probe_index;
1787
1788static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1789 struct platform_device *pdev)
1790{
1791#ifdef CONFIG_OF
1792 if (pdev->dev.of_node) {
1793 const struct of_device_id *match;
1794 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1795 return (struct s3c24xx_serial_drv_data *)match->data;
1796 }
1797#endif
1798 return (struct s3c24xx_serial_drv_data *)
1799 platform_get_device_id(pdev)->driver_data;
1800}
1801
1802static int s3c24xx_serial_probe(struct platform_device *pdev)
1803{
1804 struct device_node *np = pdev->dev.of_node;
1805 struct s3c24xx_uart_port *ourport;
1806 int index = probe_index;
1807 int ret;
1808
1809 if (np) {
1810 ret = of_alias_get_id(np, "serial");
1811 if (ret >= 0)
1812 index = ret;
1813 }
1814
1815 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1816
1817 ourport = &s3c24xx_serial_ports[index];
1818
1819 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1820 if (!ourport->drv_data) {
1821 dev_err(&pdev->dev, "could not find driver data\n");
1822 return -ENODEV;
1823 }
1824
1825 ourport->baudclk = ERR_PTR(-EINVAL);
1826 ourport->info = ourport->drv_data->info;
1827 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1828 dev_get_platdata(&pdev->dev) :
1829 ourport->drv_data->def_cfg;
1830
1831 if (np)
1832 of_property_read_u32(np,
1833 "samsung,uart-fifosize", &ourport->port.fifosize);
1834
1835 if (ourport->drv_data->fifosize[index])
1836 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1837 else if (ourport->info->fifosize)
1838 ourport->port.fifosize = ourport->info->fifosize;
1839
1840 /*
1841 * DMA transfers must be aligned at least to cache line size,
1842 * so find minimal transfer size suitable for DMA mode
1843 */
1844 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1845 dma_get_cache_alignment());
1846
1847 dbg("%s: initialising port %p...\n", __func__, ourport);
1848
1849 ret = s3c24xx_serial_init_port(ourport, pdev);
1850 if (ret < 0)
1851 return ret;
1852
1853 if (!s3c24xx_uart_drv.state) {
1854 ret = uart_register_driver(&s3c24xx_uart_drv);
1855 if (ret < 0) {
1856 pr_err("Failed to register Samsung UART driver\n");
1857 return ret;
1858 }
1859 }
1860
1861 dbg("%s: adding port\n", __func__);
1862 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1863 platform_set_drvdata(pdev, &ourport->port);
1864
1865 /*
1866 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1867 * so that a potential re-enablement through the pm-callback overlaps
1868 * and keeps the clock enabled in this case.
1869 */
1870 clk_disable_unprepare(ourport->clk);
1871
1872 ret = s3c24xx_serial_cpufreq_register(ourport);
1873 if (ret < 0)
1874 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1875
1876 probe_index++;
1877
1878 return 0;
1879}
1880
1881static int s3c24xx_serial_remove(struct platform_device *dev)
1882{
1883 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1884
1885 if (port) {
1886 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1887 uart_remove_one_port(&s3c24xx_uart_drv, port);
1888 }
1889
1890 uart_unregister_driver(&s3c24xx_uart_drv);
1891
1892 return 0;
1893}
1894
1895/* UART power management code */
1896#ifdef CONFIG_PM_SLEEP
1897static int s3c24xx_serial_suspend(struct device *dev)
1898{
1899 struct uart_port *port = s3c24xx_dev_to_port(dev);
1900
1901 if (port)
1902 uart_suspend_port(&s3c24xx_uart_drv, port);
1903
1904 return 0;
1905}
1906
1907static int s3c24xx_serial_resume(struct device *dev)
1908{
1909 struct uart_port *port = s3c24xx_dev_to_port(dev);
1910 struct s3c24xx_uart_port *ourport = to_ourport(port);
1911
1912 if (port) {
1913 clk_prepare_enable(ourport->clk);
1914 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1915 clk_disable_unprepare(ourport->clk);
1916
1917 uart_resume_port(&s3c24xx_uart_drv, port);
1918 }
1919
1920 return 0;
1921}
1922
1923static int s3c24xx_serial_resume_noirq(struct device *dev)
1924{
1925 struct uart_port *port = s3c24xx_dev_to_port(dev);
1926
1927 if (port) {
1928 /* restore IRQ mask */
1929 if (s3c24xx_serial_has_interrupt_mask(port)) {
1930 unsigned int uintm = 0xf;
1931 if (tx_enabled(port))
1932 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1933 if (rx_enabled(port))
1934 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1935 wr_regl(port, S3C64XX_UINTM, uintm);
1936 }
1937 }
1938
1939 return 0;
1940}
1941
1942static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1943 .suspend = s3c24xx_serial_suspend,
1944 .resume = s3c24xx_serial_resume,
1945 .resume_noirq = s3c24xx_serial_resume_noirq,
1946};
1947#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1948
1949#else /* !CONFIG_PM_SLEEP */
1950
1951#define SERIAL_SAMSUNG_PM_OPS NULL
1952#endif /* CONFIG_PM_SLEEP */
1953
1954/* Console code */
1955
1956#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1957
1958static struct uart_port *cons_uart;
1959
1960static int
1961s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1962{
1963 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1964 unsigned long ufstat, utrstat;
1965
1966 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1967 /* fifo mode - check amount of data in fifo registers... */
1968
1969 ufstat = rd_regl(port, S3C2410_UFSTAT);
1970 return (ufstat & info->tx_fifofull) ? 0 : 1;
1971 }
1972
1973 /* in non-fifo mode, we go and use the tx buffer empty */
1974
1975 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1976 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1977}
1978
1979static bool
1980s3c24xx_port_configured(unsigned int ucon)
1981{
1982 /* consider the serial port configured if the tx/rx mode set */
1983 return (ucon & 0xf) != 0;
1984}
1985
1986#ifdef CONFIG_CONSOLE_POLL
1987/*
1988 * Console polling routines for writing and reading from the uart while
1989 * in an interrupt or debug context.
1990 */
1991
1992static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1993{
1994 struct s3c24xx_uart_port *ourport = to_ourport(port);
1995 unsigned int ufstat;
1996
1997 ufstat = rd_regl(port, S3C2410_UFSTAT);
1998 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1999 return NO_POLL_CHAR;
2000
2001 return rd_regb(port, S3C2410_URXH);
2002}
2003
2004static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2005 unsigned char c)
2006{
2007 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2008 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2009
2010 /* not possible to xmit on unconfigured port */
2011 if (!s3c24xx_port_configured(ucon))
2012 return;
2013
2014 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2015 cpu_relax();
2016 wr_regb(port, S3C2410_UTXH, c);
2017}
2018
2019#endif /* CONFIG_CONSOLE_POLL */
2020
2021static void
2022s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2023{
2024 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2025
2026 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2027 cpu_relax();
2028 wr_regb(port, S3C2410_UTXH, ch);
2029}
2030
2031static void
2032s3c24xx_serial_console_write(struct console *co, const char *s,
2033 unsigned int count)
2034{
2035 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2036
2037 /* not possible to xmit on unconfigured port */
2038 if (!s3c24xx_port_configured(ucon))
2039 return;
2040
2041 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2042}
2043
2044static void __init
2045s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2046 int *parity, int *bits)
2047{
2048 struct clk *clk;
2049 unsigned int ulcon;
2050 unsigned int ucon;
2051 unsigned int ubrdiv;
2052 unsigned long rate;
2053 unsigned int clk_sel;
2054 char clk_name[MAX_CLK_NAME_LENGTH];
2055
2056 ulcon = rd_regl(port, S3C2410_ULCON);
2057 ucon = rd_regl(port, S3C2410_UCON);
2058 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2059
2060 dbg("s3c24xx_serial_get_options: port=%p\n"
2061 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2062 port, ulcon, ucon, ubrdiv);
2063
2064 if (s3c24xx_port_configured(ucon)) {
2065 switch (ulcon & S3C2410_LCON_CSMASK) {
2066 case S3C2410_LCON_CS5:
2067 *bits = 5;
2068 break;
2069 case S3C2410_LCON_CS6:
2070 *bits = 6;
2071 break;
2072 case S3C2410_LCON_CS7:
2073 *bits = 7;
2074 break;
2075 case S3C2410_LCON_CS8:
2076 default:
2077 *bits = 8;
2078 break;
2079 }
2080
2081 switch (ulcon & S3C2410_LCON_PMASK) {
2082 case S3C2410_LCON_PEVEN:
2083 *parity = 'e';
2084 break;
2085
2086 case S3C2410_LCON_PODD:
2087 *parity = 'o';
2088 break;
2089
2090 case S3C2410_LCON_PNONE:
2091 default:
2092 *parity = 'n';
2093 }
2094
2095 /* now calculate the baud rate */
2096
2097 clk_sel = s3c24xx_serial_getsource(port);
2098 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2099
2100 clk = clk_get(port->dev, clk_name);
2101 if (!IS_ERR(clk))
2102 rate = clk_get_rate(clk);
2103 else
2104 rate = 1;
2105
2106 *baud = rate / (16 * (ubrdiv + 1));
2107 dbg("calculated baud %d\n", *baud);
2108 }
2109
2110}
2111
2112static int __init
2113s3c24xx_serial_console_setup(struct console *co, char *options)
2114{
2115 struct uart_port *port;
2116 int baud = 9600;
2117 int bits = 8;
2118 int parity = 'n';
2119 int flow = 'n';
2120
2121 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2122 co, co->index, options);
2123
2124 /* is this a valid port */
2125
2126 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2127 co->index = 0;
2128
2129 port = &s3c24xx_serial_ports[co->index].port;
2130
2131 /* is the port configured? */
2132
2133 if (port->mapbase == 0x0)
2134 return -ENODEV;
2135
2136 cons_uart = port;
2137
2138 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2139
2140 /*
2141 * Check whether an invalid uart number has been specified, and
2142 * if so, search for the first available port that does have
2143 * console support.
2144 */
2145 if (options)
2146 uart_parse_options(options, &baud, &parity, &bits, &flow);
2147 else
2148 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2149
2150 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2151
2152 return uart_set_options(port, co, baud, parity, bits, flow);
2153}
2154
2155static struct console s3c24xx_serial_console = {
2156 .name = S3C24XX_SERIAL_NAME,
2157 .device = uart_console_device,
2158 .flags = CON_PRINTBUFFER,
2159 .index = -1,
2160 .write = s3c24xx_serial_console_write,
2161 .setup = s3c24xx_serial_console_setup,
2162 .data = &s3c24xx_uart_drv,
2163};
2164#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2165
2166#ifdef CONFIG_CPU_S3C2410
2167static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2168 .info = &(struct s3c24xx_uart_info) {
2169 .name = "Samsung S3C2410 UART",
2170 .type = PORT_S3C2410,
2171 .fifosize = 16,
2172 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2173 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2174 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2175 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2176 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2177 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2178 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2179 .num_clks = 2,
2180 .clksel_mask = S3C2410_UCON_CLKMASK,
2181 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2182 },
2183 .def_cfg = &(struct s3c2410_uartcfg) {
2184 .ucon = S3C2410_UCON_DEFAULT,
2185 .ufcon = S3C2410_UFCON_DEFAULT,
2186 },
2187};
2188#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2189#else
2190#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2191#endif
2192
2193#ifdef CONFIG_CPU_S3C2412
2194static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2195 .info = &(struct s3c24xx_uart_info) {
2196 .name = "Samsung S3C2412 UART",
2197 .type = PORT_S3C2412,
2198 .fifosize = 64,
2199 .has_divslot = 1,
2200 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2201 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2202 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2203 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2204 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2205 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2206 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2207 .num_clks = 4,
2208 .clksel_mask = S3C2412_UCON_CLKMASK,
2209 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2210 },
2211 .def_cfg = &(struct s3c2410_uartcfg) {
2212 .ucon = S3C2410_UCON_DEFAULT,
2213 .ufcon = S3C2410_UFCON_DEFAULT,
2214 },
2215};
2216#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2217#else
2218#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2219#endif
2220
2221#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2222 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2223static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2224 .info = &(struct s3c24xx_uart_info) {
2225 .name = "Samsung S3C2440 UART",
2226 .type = PORT_S3C2440,
2227 .fifosize = 64,
2228 .has_divslot = 1,
2229 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2230 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2231 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2232 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2233 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2234 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2235 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2236 .num_clks = 4,
2237 .clksel_mask = S3C2412_UCON_CLKMASK,
2238 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2239 },
2240 .def_cfg = &(struct s3c2410_uartcfg) {
2241 .ucon = S3C2410_UCON_DEFAULT,
2242 .ufcon = S3C2410_UFCON_DEFAULT,
2243 },
2244};
2245#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2246#else
2247#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2248#endif
2249
2250#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2251static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2252 .info = &(struct s3c24xx_uart_info) {
2253 .name = "Samsung S3C6400 UART",
2254 .type = PORT_S3C6400,
2255 .fifosize = 64,
2256 .has_divslot = 1,
2257 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2258 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2259 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2260 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2261 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2262 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2263 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2264 .num_clks = 4,
2265 .clksel_mask = S3C6400_UCON_CLKMASK,
2266 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2267 },
2268 .def_cfg = &(struct s3c2410_uartcfg) {
2269 .ucon = S3C2410_UCON_DEFAULT,
2270 .ufcon = S3C2410_UFCON_DEFAULT,
2271 },
2272};
2273#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2274#else
2275#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2276#endif
2277
2278#ifdef CONFIG_CPU_S5PV210
2279static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2280 .info = &(struct s3c24xx_uart_info) {
2281 .name = "Samsung S5PV210 UART",
2282 .type = PORT_S3C6400,
2283 .has_divslot = 1,
2284 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2285 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2286 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2287 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2288 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2289 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2290 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2291 .num_clks = 2,
2292 .clksel_mask = S5PV210_UCON_CLKMASK,
2293 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2294 },
2295 .def_cfg = &(struct s3c2410_uartcfg) {
2296 .ucon = S5PV210_UCON_DEFAULT,
2297 .ufcon = S5PV210_UFCON_DEFAULT,
2298 },
2299 .fifosize = { 256, 64, 16, 16 },
2300};
2301#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2302#else
2303#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2304#endif
2305
2306#if defined(CONFIG_ARCH_EXYNOS)
2307#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2308 .info = &(struct s3c24xx_uart_info) { \
2309 .name = "Samsung Exynos UART", \
2310 .type = PORT_S3C6400, \
2311 .has_divslot = 1, \
2312 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2313 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2314 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2315 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2316 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2317 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2318 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2319 .num_clks = 1, \
2320 .clksel_mask = 0, \
2321 .clksel_shift = 0, \
2322 }, \
2323 .def_cfg = &(struct s3c2410_uartcfg) { \
2324 .ucon = S5PV210_UCON_DEFAULT, \
2325 .ufcon = S5PV210_UFCON_DEFAULT, \
2326 .has_fracval = 1, \
2327 } \
2328
2329static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2330 EXYNOS_COMMON_SERIAL_DRV_DATA,
2331 .fifosize = { 256, 64, 16, 16 },
2332};
2333
2334static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2335 EXYNOS_COMMON_SERIAL_DRV_DATA,
2336 .fifosize = { 64, 256, 16, 256 },
2337};
2338
2339#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2340#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2341#else
2342#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2343#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2344#endif
2345
2346static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2347 {
2348 .name = "s3c2410-uart",
2349 .driver_data = S3C2410_SERIAL_DRV_DATA,
2350 }, {
2351 .name = "s3c2412-uart",
2352 .driver_data = S3C2412_SERIAL_DRV_DATA,
2353 }, {
2354 .name = "s3c2440-uart",
2355 .driver_data = S3C2440_SERIAL_DRV_DATA,
2356 }, {
2357 .name = "s3c6400-uart",
2358 .driver_data = S3C6400_SERIAL_DRV_DATA,
2359 }, {
2360 .name = "s5pv210-uart",
2361 .driver_data = S5PV210_SERIAL_DRV_DATA,
2362 }, {
2363 .name = "exynos4210-uart",
2364 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2365 }, {
2366 .name = "exynos5433-uart",
2367 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2368 },
2369 { },
2370};
2371MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2372
2373#ifdef CONFIG_OF
2374static const struct of_device_id s3c24xx_uart_dt_match[] = {
2375 { .compatible = "samsung,s3c2410-uart",
2376 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2377 { .compatible = "samsung,s3c2412-uart",
2378 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2379 { .compatible = "samsung,s3c2440-uart",
2380 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2381 { .compatible = "samsung,s3c6400-uart",
2382 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2383 { .compatible = "samsung,s5pv210-uart",
2384 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2385 { .compatible = "samsung,exynos4210-uart",
2386 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2387 { .compatible = "samsung,exynos5433-uart",
2388 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2389 {},
2390};
2391MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2392#endif
2393
2394static struct platform_driver samsung_serial_driver = {
2395 .probe = s3c24xx_serial_probe,
2396 .remove = s3c24xx_serial_remove,
2397 .id_table = s3c24xx_serial_driver_ids,
2398 .driver = {
2399 .name = "samsung-uart",
2400 .pm = SERIAL_SAMSUNG_PM_OPS,
2401 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2402 },
2403};
2404
2405module_platform_driver(samsung_serial_driver);
2406
2407#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2408/*
2409 * Early console.
2410 */
2411
2412struct samsung_early_console_data {
2413 u32 txfull_mask;
2414};
2415
2416static void samsung_early_busyuart(struct uart_port *port)
2417{
2418 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2419 ;
2420}
2421
2422static void samsung_early_busyuart_fifo(struct uart_port *port)
2423{
2424 struct samsung_early_console_data *data = port->private_data;
2425
2426 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2427 ;
2428}
2429
2430static void samsung_early_putc(struct uart_port *port, int c)
2431{
2432 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2433 samsung_early_busyuart_fifo(port);
2434 else
2435 samsung_early_busyuart(port);
2436
2437 writeb(c, port->membase + S3C2410_UTXH);
2438}
2439
2440static void samsung_early_write(struct console *con, const char *s, unsigned n)
2441{
2442 struct earlycon_device *dev = con->data;
2443
2444 uart_console_write(&dev->port, s, n, samsung_early_putc);
2445}
2446
2447static int __init samsung_early_console_setup(struct earlycon_device *device,
2448 const char *opt)
2449{
2450 if (!device->port.membase)
2451 return -ENODEV;
2452
2453 device->con->write = samsung_early_write;
2454 return 0;
2455}
2456
2457/* S3C2410 */
2458static struct samsung_early_console_data s3c2410_early_console_data = {
2459 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2460};
2461
2462static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2463 const char *opt)
2464{
2465 device->port.private_data = &s3c2410_early_console_data;
2466 return samsung_early_console_setup(device, opt);
2467}
2468OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2469 s3c2410_early_console_setup);
2470
2471/* S3C2412, S3C2440, S3C64xx */
2472static struct samsung_early_console_data s3c2440_early_console_data = {
2473 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2474};
2475
2476static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2477 const char *opt)
2478{
2479 device->port.private_data = &s3c2440_early_console_data;
2480 return samsung_early_console_setup(device, opt);
2481}
2482OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2483 s3c2440_early_console_setup);
2484OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2485 s3c2440_early_console_setup);
2486OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2487 s3c2440_early_console_setup);
2488
2489/* S5PV210, EXYNOS */
2490static struct samsung_early_console_data s5pv210_early_console_data = {
2491 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2492};
2493
2494static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2495 const char *opt)
2496{
2497 device->port.private_data = &s5pv210_early_console_data;
2498 return samsung_early_console_setup(device, opt);
2499}
2500OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2501 s5pv210_early_console_setup);
2502OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2503 s5pv210_early_console_setup);
2504#endif
2505
2506MODULE_ALIAS("platform:samsung-uart");
2507MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2508MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2509MODULE_LICENSE("GPL v2");