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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver core for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7*/
8
9/* Hote on 2410 error handling
10 *
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
16 *
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
20 *
21 * BJD, 04-Nov-2004
22*/
23
24#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/dmaengine.h>
29#include <linux/dma-mapping.h>
30#include <linux/slab.h>
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_s3c.h>
43#include <linux/delay.h>
44#include <linux/clk.h>
45#include <linux/cpufreq.h>
46#include <linux/of.h>
47
48#include <asm/irq.h>
49
50#include "samsung.h"
51
52#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
53 !defined(MODULE)
54
55extern void printascii(const char *);
56
57__printf(1, 2)
58static void dbg(const char *fmt, ...)
59{
60 va_list va;
61 char buff[256];
62
63 va_start(va, fmt);
64 vscnprintf(buff, sizeof(buff), fmt, va);
65 va_end(va);
66
67 printascii(buff);
68}
69
70#else
71#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
72#endif
73
74/* UART name and device definitions */
75
76#define S3C24XX_SERIAL_NAME "ttySAC"
77#define S3C24XX_SERIAL_MAJOR 204
78#define S3C24XX_SERIAL_MINOR 64
79
80#define S3C24XX_TX_PIO 1
81#define S3C24XX_TX_DMA 2
82#define S3C24XX_RX_PIO 1
83#define S3C24XX_RX_DMA 2
84/* macros to change one thing to another */
85
86#define tx_enabled(port) ((port)->unused[0])
87#define rx_enabled(port) ((port)->unused[1])
88
89/* flag to ignore all characters coming in */
90#define RXSTAT_DUMMY_READ (0x10000000)
91
92static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
93{
94 return container_of(port, struct s3c24xx_uart_port, port);
95}
96
97/* translate a port to the device name */
98
99static inline const char *s3c24xx_serial_portname(struct uart_port *port)
100{
101 return to_platform_device(port->dev)->name;
102}
103
104static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
105{
106 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
107}
108
109/*
110 * s3c64xx and later SoC's include the interrupt mask and status registers in
111 * the controller itself, unlike the s3c24xx SoC's which have these registers
112 * in the interrupt controller. Check if the port type is s3c64xx or higher.
113 */
114static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
115{
116 return to_ourport(port)->info->type == PORT_S3C6400;
117}
118
119static void s3c24xx_serial_rx_enable(struct uart_port *port)
120{
121 unsigned long flags;
122 unsigned int ucon, ufcon;
123 int count = 10000;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 while (--count && !s3c24xx_serial_txempty_nofifo(port))
128 udelay(100);
129
130 ufcon = rd_regl(port, S3C2410_UFCON);
131 ufcon |= S3C2410_UFCON_RESETRX;
132 wr_regl(port, S3C2410_UFCON, ufcon);
133
134 ucon = rd_regl(port, S3C2410_UCON);
135 ucon |= S3C2410_UCON_RXIRQMODE;
136 wr_regl(port, S3C2410_UCON, ucon);
137
138 rx_enabled(port) = 1;
139 spin_unlock_irqrestore(&port->lock, flags);
140}
141
142static void s3c24xx_serial_rx_disable(struct uart_port *port)
143{
144 unsigned long flags;
145 unsigned int ucon;
146
147 spin_lock_irqsave(&port->lock, flags);
148
149 ucon = rd_regl(port, S3C2410_UCON);
150 ucon &= ~S3C2410_UCON_RXIRQMODE;
151 wr_regl(port, S3C2410_UCON, ucon);
152
153 rx_enabled(port) = 0;
154 spin_unlock_irqrestore(&port->lock, flags);
155}
156
157static void s3c24xx_serial_stop_tx(struct uart_port *port)
158{
159 struct s3c24xx_uart_port *ourport = to_ourport(port);
160 struct s3c24xx_uart_dma *dma = ourport->dma;
161 struct circ_buf *xmit = &port->state->xmit;
162 struct dma_tx_state state;
163 int count;
164
165 if (!tx_enabled(port))
166 return;
167
168 if (s3c24xx_serial_has_interrupt_mask(port))
169 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
170 else
171 disable_irq_nosync(ourport->tx_irq);
172
173 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
174 dmaengine_pause(dma->tx_chan);
175 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
176 dmaengine_terminate_all(dma->tx_chan);
177 dma_sync_single_for_cpu(ourport->port.dev,
178 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
179 async_tx_ack(dma->tx_desc);
180 count = dma->tx_bytes_requested - state.residue;
181 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
182 port->icount.tx += count;
183 }
184
185 tx_enabled(port) = 0;
186 ourport->tx_in_progress = 0;
187
188 if (port->flags & UPF_CONS_FLOW)
189 s3c24xx_serial_rx_enable(port);
190
191 ourport->tx_mode = 0;
192}
193
194static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
195
196static void s3c24xx_serial_tx_dma_complete(void *args)
197{
198 struct s3c24xx_uart_port *ourport = args;
199 struct uart_port *port = &ourport->port;
200 struct circ_buf *xmit = &port->state->xmit;
201 struct s3c24xx_uart_dma *dma = ourport->dma;
202 struct dma_tx_state state;
203 unsigned long flags;
204 int count;
205
206
207 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
208 count = dma->tx_bytes_requested - state.residue;
209 async_tx_ack(dma->tx_desc);
210
211 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
212 dma->tx_size, DMA_TO_DEVICE);
213
214 spin_lock_irqsave(&port->lock, flags);
215
216 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
217 port->icount.tx += count;
218 ourport->tx_in_progress = 0;
219
220 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
221 uart_write_wakeup(port);
222
223 s3c24xx_serial_start_next_tx(ourport);
224 spin_unlock_irqrestore(&port->lock, flags);
225}
226
227static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
228{
229 struct uart_port *port = &ourport->port;
230 u32 ucon;
231
232 /* Mask Tx interrupt */
233 if (s3c24xx_serial_has_interrupt_mask(port))
234 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
235 else
236 disable_irq_nosync(ourport->tx_irq);
237
238 /* Enable tx dma mode */
239 ucon = rd_regl(port, S3C2410_UCON);
240 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
241 ucon |= (dma_get_cache_alignment() >= 16) ?
242 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
243 ucon |= S3C64XX_UCON_TXMODE_DMA;
244 wr_regl(port, S3C2410_UCON, ucon);
245
246 ourport->tx_mode = S3C24XX_TX_DMA;
247}
248
249static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
250{
251 struct uart_port *port = &ourport->port;
252 u32 ucon, ufcon;
253
254 /* Set ufcon txtrig */
255 ourport->tx_in_progress = S3C24XX_TX_PIO;
256 ufcon = rd_regl(port, S3C2410_UFCON);
257 wr_regl(port, S3C2410_UFCON, ufcon);
258
259 /* Enable tx pio mode */
260 ucon = rd_regl(port, S3C2410_UCON);
261 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
262 ucon |= S3C64XX_UCON_TXMODE_CPU;
263 wr_regl(port, S3C2410_UCON, ucon);
264
265 /* Unmask Tx interrupt */
266 if (s3c24xx_serial_has_interrupt_mask(port))
267 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
268 S3C64XX_UINTM);
269 else
270 enable_irq(ourport->tx_irq);
271
272 ourport->tx_mode = S3C24XX_TX_PIO;
273}
274
275static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
276{
277 if (ourport->tx_mode != S3C24XX_TX_PIO)
278 enable_tx_pio(ourport);
279}
280
281static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
282 unsigned int count)
283{
284 struct uart_port *port = &ourport->port;
285 struct circ_buf *xmit = &port->state->xmit;
286 struct s3c24xx_uart_dma *dma = ourport->dma;
287
288
289 if (ourport->tx_mode != S3C24XX_TX_DMA)
290 enable_tx_dma(ourport);
291
292 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
293 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
294
295 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
296 dma->tx_size, DMA_TO_DEVICE);
297
298 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
299 dma->tx_transfer_addr, dma->tx_size,
300 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
301 if (!dma->tx_desc) {
302 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
303 return -EIO;
304 }
305
306 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
307 dma->tx_desc->callback_param = ourport;
308 dma->tx_bytes_requested = dma->tx_size;
309
310 ourport->tx_in_progress = S3C24XX_TX_DMA;
311 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
312 dma_async_issue_pending(dma->tx_chan);
313 return 0;
314}
315
316static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
317{
318 struct uart_port *port = &ourport->port;
319 struct circ_buf *xmit = &port->state->xmit;
320 unsigned long count;
321
322 /* Get data size up to the end of buffer */
323 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
324
325 if (!count) {
326 s3c24xx_serial_stop_tx(port);
327 return;
328 }
329
330 if (!ourport->dma || !ourport->dma->tx_chan ||
331 count < ourport->min_dma_size ||
332 xmit->tail & (dma_get_cache_alignment() - 1))
333 s3c24xx_serial_start_tx_pio(ourport);
334 else
335 s3c24xx_serial_start_tx_dma(ourport, count);
336}
337
338static void s3c24xx_serial_start_tx(struct uart_port *port)
339{
340 struct s3c24xx_uart_port *ourport = to_ourport(port);
341 struct circ_buf *xmit = &port->state->xmit;
342
343 if (!tx_enabled(port)) {
344 if (port->flags & UPF_CONS_FLOW)
345 s3c24xx_serial_rx_disable(port);
346
347 tx_enabled(port) = 1;
348 if (!ourport->dma || !ourport->dma->tx_chan)
349 s3c24xx_serial_start_tx_pio(ourport);
350 }
351
352 if (ourport->dma && ourport->dma->tx_chan) {
353 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
354 s3c24xx_serial_start_next_tx(ourport);
355 }
356}
357
358static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
359 struct tty_port *tty, int count)
360{
361 struct s3c24xx_uart_dma *dma = ourport->dma;
362 int copied;
363
364 if (!count)
365 return;
366
367 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
368 dma->rx_size, DMA_FROM_DEVICE);
369
370 ourport->port.icount.rx += count;
371 if (!tty) {
372 dev_err(ourport->port.dev, "No tty port\n");
373 return;
374 }
375 copied = tty_insert_flip_string(tty,
376 ((unsigned char *)(ourport->dma->rx_buf)), count);
377 if (copied != count) {
378 WARN_ON(1);
379 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
380 }
381}
382
383static void s3c24xx_serial_stop_rx(struct uart_port *port)
384{
385 struct s3c24xx_uart_port *ourport = to_ourport(port);
386 struct s3c24xx_uart_dma *dma = ourport->dma;
387 struct tty_port *t = &port->state->port;
388 struct dma_tx_state state;
389 enum dma_status dma_status;
390 unsigned int received;
391
392 if (rx_enabled(port)) {
393 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
394 if (s3c24xx_serial_has_interrupt_mask(port))
395 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
396 S3C64XX_UINTM);
397 else
398 disable_irq_nosync(ourport->rx_irq);
399 rx_enabled(port) = 0;
400 }
401 if (dma && dma->rx_chan) {
402 dmaengine_pause(dma->tx_chan);
403 dma_status = dmaengine_tx_status(dma->rx_chan,
404 dma->rx_cookie, &state);
405 if (dma_status == DMA_IN_PROGRESS ||
406 dma_status == DMA_PAUSED) {
407 received = dma->rx_bytes_requested - state.residue;
408 dmaengine_terminate_all(dma->rx_chan);
409 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
410 }
411 }
412}
413
414static inline struct s3c24xx_uart_info
415 *s3c24xx_port_to_info(struct uart_port *port)
416{
417 return to_ourport(port)->info;
418}
419
420static inline struct s3c2410_uartcfg
421 *s3c24xx_port_to_cfg(struct uart_port *port)
422{
423 struct s3c24xx_uart_port *ourport;
424
425 if (port->dev == NULL)
426 return NULL;
427
428 ourport = container_of(port, struct s3c24xx_uart_port, port);
429 return ourport->cfg;
430}
431
432static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
433 unsigned long ufstat)
434{
435 struct s3c24xx_uart_info *info = ourport->info;
436
437 if (ufstat & info->rx_fifofull)
438 return ourport->port.fifosize;
439
440 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
441}
442
443static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
444static void s3c24xx_serial_rx_dma_complete(void *args)
445{
446 struct s3c24xx_uart_port *ourport = args;
447 struct uart_port *port = &ourport->port;
448
449 struct s3c24xx_uart_dma *dma = ourport->dma;
450 struct tty_port *t = &port->state->port;
451 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
452
453 struct dma_tx_state state;
454 unsigned long flags;
455 int received;
456
457 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
458 received = dma->rx_bytes_requested - state.residue;
459 async_tx_ack(dma->rx_desc);
460
461 spin_lock_irqsave(&port->lock, flags);
462
463 if (received)
464 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
465
466 if (tty) {
467 tty_flip_buffer_push(t);
468 tty_kref_put(tty);
469 }
470
471 s3c64xx_start_rx_dma(ourport);
472
473 spin_unlock_irqrestore(&port->lock, flags);
474}
475
476static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
477{
478 struct s3c24xx_uart_dma *dma = ourport->dma;
479
480 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
481 dma->rx_size, DMA_FROM_DEVICE);
482
483 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
484 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
485 DMA_PREP_INTERRUPT);
486 if (!dma->rx_desc) {
487 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
488 return;
489 }
490
491 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
492 dma->rx_desc->callback_param = ourport;
493 dma->rx_bytes_requested = dma->rx_size;
494
495 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
496 dma_async_issue_pending(dma->rx_chan);
497}
498
499/* ? - where has parity gone?? */
500#define S3C2410_UERSTAT_PARITY (0x1000)
501
502static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
503{
504 struct uart_port *port = &ourport->port;
505 unsigned int ucon;
506
507 /* set Rx mode to DMA mode */
508 ucon = rd_regl(port, S3C2410_UCON);
509 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
510 S3C64XX_UCON_TIMEOUT_MASK |
511 S3C64XX_UCON_EMPTYINT_EN |
512 S3C64XX_UCON_DMASUS_EN |
513 S3C64XX_UCON_TIMEOUT_EN |
514 S3C64XX_UCON_RXMODE_MASK);
515 ucon |= S3C64XX_UCON_RXBURST_16 |
516 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
517 S3C64XX_UCON_EMPTYINT_EN |
518 S3C64XX_UCON_TIMEOUT_EN |
519 S3C64XX_UCON_RXMODE_DMA;
520 wr_regl(port, S3C2410_UCON, ucon);
521
522 ourport->rx_mode = S3C24XX_RX_DMA;
523}
524
525static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
526{
527 struct uart_port *port = &ourport->port;
528 unsigned int ucon;
529
530 /* set Rx mode to DMA mode */
531 ucon = rd_regl(port, S3C2410_UCON);
532 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
533 S3C64XX_UCON_EMPTYINT_EN |
534 S3C64XX_UCON_DMASUS_EN |
535 S3C64XX_UCON_TIMEOUT_EN |
536 S3C64XX_UCON_RXMODE_MASK);
537 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
538 S3C64XX_UCON_TIMEOUT_EN |
539 S3C64XX_UCON_RXMODE_CPU;
540 wr_regl(port, S3C2410_UCON, ucon);
541
542 ourport->rx_mode = S3C24XX_RX_PIO;
543}
544
545static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
546
547static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
548{
549 unsigned int utrstat, ufstat, received;
550 struct s3c24xx_uart_port *ourport = dev_id;
551 struct uart_port *port = &ourport->port;
552 struct s3c24xx_uart_dma *dma = ourport->dma;
553 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
554 struct tty_port *t = &port->state->port;
555 unsigned long flags;
556 struct dma_tx_state state;
557
558 utrstat = rd_regl(port, S3C2410_UTRSTAT);
559 ufstat = rd_regl(port, S3C2410_UFSTAT);
560
561 spin_lock_irqsave(&port->lock, flags);
562
563 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
564 s3c64xx_start_rx_dma(ourport);
565 if (ourport->rx_mode == S3C24XX_RX_PIO)
566 enable_rx_dma(ourport);
567 goto finish;
568 }
569
570 if (ourport->rx_mode == S3C24XX_RX_DMA) {
571 dmaengine_pause(dma->rx_chan);
572 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
573 dmaengine_terminate_all(dma->rx_chan);
574 received = dma->rx_bytes_requested - state.residue;
575 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
576
577 enable_rx_pio(ourport);
578 }
579
580 s3c24xx_serial_rx_drain_fifo(ourport);
581
582 if (tty) {
583 tty_flip_buffer_push(t);
584 tty_kref_put(tty);
585 }
586
587 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
588
589finish:
590 spin_unlock_irqrestore(&port->lock, flags);
591
592 return IRQ_HANDLED;
593}
594
595static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
596{
597 struct uart_port *port = &ourport->port;
598 unsigned int ufcon, ch, flag, ufstat, uerstat;
599 unsigned int fifocnt = 0;
600 int max_count = port->fifosize;
601
602 while (max_count-- > 0) {
603 /*
604 * Receive all characters known to be in FIFO
605 * before reading FIFO level again
606 */
607 if (fifocnt == 0) {
608 ufstat = rd_regl(port, S3C2410_UFSTAT);
609 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
610 if (fifocnt == 0)
611 break;
612 }
613 fifocnt--;
614
615 uerstat = rd_regl(port, S3C2410_UERSTAT);
616 ch = rd_regb(port, S3C2410_URXH);
617
618 if (port->flags & UPF_CONS_FLOW) {
619 int txe = s3c24xx_serial_txempty_nofifo(port);
620
621 if (rx_enabled(port)) {
622 if (!txe) {
623 rx_enabled(port) = 0;
624 continue;
625 }
626 } else {
627 if (txe) {
628 ufcon = rd_regl(port, S3C2410_UFCON);
629 ufcon |= S3C2410_UFCON_RESETRX;
630 wr_regl(port, S3C2410_UFCON, ufcon);
631 rx_enabled(port) = 1;
632 return;
633 }
634 continue;
635 }
636 }
637
638 /* insert the character into the buffer */
639
640 flag = TTY_NORMAL;
641 port->icount.rx++;
642
643 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
644 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
645 ch, uerstat);
646
647 /* check for break */
648 if (uerstat & S3C2410_UERSTAT_BREAK) {
649 dbg("break!\n");
650 port->icount.brk++;
651 if (uart_handle_break(port))
652 continue; /* Ignore character */
653 }
654
655 if (uerstat & S3C2410_UERSTAT_FRAME)
656 port->icount.frame++;
657 if (uerstat & S3C2410_UERSTAT_OVERRUN)
658 port->icount.overrun++;
659
660 uerstat &= port->read_status_mask;
661
662 if (uerstat & S3C2410_UERSTAT_BREAK)
663 flag = TTY_BREAK;
664 else if (uerstat & S3C2410_UERSTAT_PARITY)
665 flag = TTY_PARITY;
666 else if (uerstat & (S3C2410_UERSTAT_FRAME |
667 S3C2410_UERSTAT_OVERRUN))
668 flag = TTY_FRAME;
669 }
670
671 if (uart_handle_sysrq_char(port, ch))
672 continue; /* Ignore character */
673
674 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
675 ch, flag);
676 }
677
678 tty_flip_buffer_push(&port->state->port);
679}
680
681static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
682{
683 struct s3c24xx_uart_port *ourport = dev_id;
684 struct uart_port *port = &ourport->port;
685 unsigned long flags;
686
687 spin_lock_irqsave(&port->lock, flags);
688 s3c24xx_serial_rx_drain_fifo(ourport);
689 spin_unlock_irqrestore(&port->lock, flags);
690
691 return IRQ_HANDLED;
692}
693
694
695static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
696{
697 struct s3c24xx_uart_port *ourport = dev_id;
698
699 if (ourport->dma && ourport->dma->rx_chan)
700 return s3c24xx_serial_rx_chars_dma(dev_id);
701 return s3c24xx_serial_rx_chars_pio(dev_id);
702}
703
704static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
705{
706 struct s3c24xx_uart_port *ourport = id;
707 struct uart_port *port = &ourport->port;
708 struct circ_buf *xmit = &port->state->xmit;
709 unsigned long flags;
710 int count, dma_count = 0;
711
712 spin_lock_irqsave(&port->lock, flags);
713
714 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
715
716 if (ourport->dma && ourport->dma->tx_chan &&
717 count >= ourport->min_dma_size) {
718 int align = dma_get_cache_alignment() -
719 (xmit->tail & (dma_get_cache_alignment() - 1));
720 if (count-align >= ourport->min_dma_size) {
721 dma_count = count-align;
722 count = align;
723 }
724 }
725
726 if (port->x_char) {
727 wr_regb(port, S3C2410_UTXH, port->x_char);
728 port->icount.tx++;
729 port->x_char = 0;
730 goto out;
731 }
732
733 /* if there isn't anything more to transmit, or the uart is now
734 * stopped, disable the uart and exit
735 */
736
737 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
738 s3c24xx_serial_stop_tx(port);
739 goto out;
740 }
741
742 /* try and drain the buffer... */
743
744 if (count > port->fifosize) {
745 count = port->fifosize;
746 dma_count = 0;
747 }
748
749 while (!uart_circ_empty(xmit) && count > 0) {
750 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
751 break;
752
753 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
754 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
755 port->icount.tx++;
756 count--;
757 }
758
759 if (!count && dma_count) {
760 s3c24xx_serial_start_tx_dma(ourport, dma_count);
761 goto out;
762 }
763
764 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
765 spin_unlock(&port->lock);
766 uart_write_wakeup(port);
767 spin_lock(&port->lock);
768 }
769
770 if (uart_circ_empty(xmit))
771 s3c24xx_serial_stop_tx(port);
772
773out:
774 spin_unlock_irqrestore(&port->lock, flags);
775 return IRQ_HANDLED;
776}
777
778/* interrupt handler for s3c64xx and later SoC's.*/
779static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
780{
781 struct s3c24xx_uart_port *ourport = id;
782 struct uart_port *port = &ourport->port;
783 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
784 irqreturn_t ret = IRQ_HANDLED;
785
786 if (pend & S3C64XX_UINTM_RXD_MSK) {
787 ret = s3c24xx_serial_rx_chars(irq, id);
788 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
789 }
790 if (pend & S3C64XX_UINTM_TXD_MSK) {
791 ret = s3c24xx_serial_tx_chars(irq, id);
792 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
793 }
794 return ret;
795}
796
797static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
798{
799 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
800 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
801 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
802
803 if (ufcon & S3C2410_UFCON_FIFOMODE) {
804 if ((ufstat & info->tx_fifomask) != 0 ||
805 (ufstat & info->tx_fifofull))
806 return 0;
807
808 return 1;
809 }
810
811 return s3c24xx_serial_txempty_nofifo(port);
812}
813
814/* no modem control lines */
815static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
816{
817 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
818
819 if (umstat & S3C2410_UMSTAT_CTS)
820 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
821 else
822 return TIOCM_CAR | TIOCM_DSR;
823}
824
825static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
826{
827 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
828
829 if (mctrl & TIOCM_RTS)
830 umcon |= S3C2410_UMCOM_RTS_LOW;
831 else
832 umcon &= ~S3C2410_UMCOM_RTS_LOW;
833
834 wr_regl(port, S3C2410_UMCON, umcon);
835}
836
837static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
838{
839 unsigned long flags;
840 unsigned int ucon;
841
842 spin_lock_irqsave(&port->lock, flags);
843
844 ucon = rd_regl(port, S3C2410_UCON);
845
846 if (break_state)
847 ucon |= S3C2410_UCON_SBREAK;
848 else
849 ucon &= ~S3C2410_UCON_SBREAK;
850
851 wr_regl(port, S3C2410_UCON, ucon);
852
853 spin_unlock_irqrestore(&port->lock, flags);
854}
855
856static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
857{
858 struct s3c24xx_uart_dma *dma = p->dma;
859 struct dma_slave_caps dma_caps;
860 const char *reason = NULL;
861 int ret;
862
863 /* Default slave configuration parameters */
864 dma->rx_conf.direction = DMA_DEV_TO_MEM;
865 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
866 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
867 dma->rx_conf.src_maxburst = 1;
868
869 dma->tx_conf.direction = DMA_MEM_TO_DEV;
870 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
871 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
872 dma->tx_conf.dst_maxburst = 1;
873
874 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
875
876 if (IS_ERR(dma->rx_chan)) {
877 reason = "DMA RX channel request failed";
878 ret = PTR_ERR(dma->rx_chan);
879 goto err_warn;
880 }
881
882 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
883 if (ret < 0 ||
884 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
885 reason = "insufficient DMA RX engine capabilities";
886 ret = -EOPNOTSUPP;
887 goto err_release_rx;
888 }
889
890 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
891
892 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
893 if (IS_ERR(dma->tx_chan)) {
894 reason = "DMA TX channel request failed";
895 ret = PTR_ERR(dma->tx_chan);
896 goto err_release_rx;
897 }
898
899 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
900 if (ret < 0 ||
901 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
902 reason = "insufficient DMA TX engine capabilities";
903 ret = -EOPNOTSUPP;
904 goto err_release_tx;
905 }
906
907 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
908
909 /* RX buffer */
910 dma->rx_size = PAGE_SIZE;
911
912 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
913 if (!dma->rx_buf) {
914 ret = -ENOMEM;
915 goto err_release_tx;
916 }
917
918 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
919 dma->rx_size, DMA_FROM_DEVICE);
920 if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
921 reason = "DMA mapping error for RX buffer";
922 ret = -EIO;
923 goto err_free_rx;
924 }
925
926 /* TX buffer */
927 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
928 UART_XMIT_SIZE, DMA_TO_DEVICE);
929 if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
930 reason = "DMA mapping error for TX buffer";
931 ret = -EIO;
932 goto err_unmap_rx;
933 }
934
935 return 0;
936
937err_unmap_rx:
938 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
939 DMA_FROM_DEVICE);
940err_free_rx:
941 kfree(dma->rx_buf);
942err_release_tx:
943 dma_release_channel(dma->tx_chan);
944err_release_rx:
945 dma_release_channel(dma->rx_chan);
946err_warn:
947 if (reason)
948 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
949 return ret;
950}
951
952static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
953{
954 struct s3c24xx_uart_dma *dma = p->dma;
955
956 if (dma->rx_chan) {
957 dmaengine_terminate_all(dma->rx_chan);
958 dma_unmap_single(p->port.dev, dma->rx_addr,
959 dma->rx_size, DMA_FROM_DEVICE);
960 kfree(dma->rx_buf);
961 dma_release_channel(dma->rx_chan);
962 dma->rx_chan = NULL;
963 }
964
965 if (dma->tx_chan) {
966 dmaengine_terminate_all(dma->tx_chan);
967 dma_unmap_single(p->port.dev, dma->tx_addr,
968 UART_XMIT_SIZE, DMA_TO_DEVICE);
969 dma_release_channel(dma->tx_chan);
970 dma->tx_chan = NULL;
971 }
972}
973
974static void s3c24xx_serial_shutdown(struct uart_port *port)
975{
976 struct s3c24xx_uart_port *ourport = to_ourport(port);
977
978 if (ourport->tx_claimed) {
979 if (!s3c24xx_serial_has_interrupt_mask(port))
980 free_irq(ourport->tx_irq, ourport);
981 tx_enabled(port) = 0;
982 ourport->tx_claimed = 0;
983 ourport->tx_mode = 0;
984 }
985
986 if (ourport->rx_claimed) {
987 if (!s3c24xx_serial_has_interrupt_mask(port))
988 free_irq(ourport->rx_irq, ourport);
989 ourport->rx_claimed = 0;
990 rx_enabled(port) = 0;
991 }
992
993 /* Clear pending interrupts and mask all interrupts */
994 if (s3c24xx_serial_has_interrupt_mask(port)) {
995 free_irq(port->irq, ourport);
996
997 wr_regl(port, S3C64XX_UINTP, 0xf);
998 wr_regl(port, S3C64XX_UINTM, 0xf);
999 }
1000
1001 if (ourport->dma)
1002 s3c24xx_serial_release_dma(ourport);
1003
1004 ourport->tx_in_progress = 0;
1005}
1006
1007static int s3c24xx_serial_startup(struct uart_port *port)
1008{
1009 struct s3c24xx_uart_port *ourport = to_ourport(port);
1010 int ret;
1011
1012 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1013 port, (unsigned long long)port->mapbase, port->membase);
1014
1015 rx_enabled(port) = 1;
1016
1017 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1018 s3c24xx_serial_portname(port), ourport);
1019
1020 if (ret != 0) {
1021 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1022 return ret;
1023 }
1024
1025 ourport->rx_claimed = 1;
1026
1027 dbg("requesting tx irq...\n");
1028
1029 tx_enabled(port) = 1;
1030
1031 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1032 s3c24xx_serial_portname(port), ourport);
1033
1034 if (ret) {
1035 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1036 goto err;
1037 }
1038
1039 ourport->tx_claimed = 1;
1040
1041 dbg("s3c24xx_serial_startup ok\n");
1042
1043 /* the port reset code should have done the correct
1044 * register setup for the port controls */
1045
1046 return ret;
1047
1048err:
1049 s3c24xx_serial_shutdown(port);
1050 return ret;
1051}
1052
1053static int s3c64xx_serial_startup(struct uart_port *port)
1054{
1055 struct s3c24xx_uart_port *ourport = to_ourport(port);
1056 unsigned long flags;
1057 unsigned int ufcon;
1058 int ret;
1059
1060 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1061 port, (unsigned long long)port->mapbase, port->membase);
1062
1063 wr_regl(port, S3C64XX_UINTM, 0xf);
1064 if (ourport->dma) {
1065 ret = s3c24xx_serial_request_dma(ourport);
1066 if (ret < 0) {
1067 devm_kfree(port->dev, ourport->dma);
1068 ourport->dma = NULL;
1069 }
1070 }
1071
1072 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1073 s3c24xx_serial_portname(port), ourport);
1074 if (ret) {
1075 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1076 return ret;
1077 }
1078
1079 /* For compatibility with s3c24xx Soc's */
1080 rx_enabled(port) = 1;
1081 ourport->rx_claimed = 1;
1082 tx_enabled(port) = 0;
1083 ourport->tx_claimed = 1;
1084
1085 spin_lock_irqsave(&port->lock, flags);
1086
1087 ufcon = rd_regl(port, S3C2410_UFCON);
1088 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1089 if (!uart_console(port))
1090 ufcon |= S3C2410_UFCON_RESETTX;
1091 wr_regl(port, S3C2410_UFCON, ufcon);
1092
1093 enable_rx_pio(ourport);
1094
1095 spin_unlock_irqrestore(&port->lock, flags);
1096
1097 /* Enable Rx Interrupt */
1098 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1099
1100 dbg("s3c64xx_serial_startup ok\n");
1101 return ret;
1102}
1103
1104/* power power management control */
1105
1106static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1107 unsigned int old)
1108{
1109 struct s3c24xx_uart_port *ourport = to_ourport(port);
1110 int timeout = 10000;
1111
1112 ourport->pm_level = level;
1113
1114 switch (level) {
1115 case 3:
1116 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1117 udelay(100);
1118
1119 if (!IS_ERR(ourport->baudclk))
1120 clk_disable_unprepare(ourport->baudclk);
1121
1122 clk_disable_unprepare(ourport->clk);
1123 break;
1124
1125 case 0:
1126 clk_prepare_enable(ourport->clk);
1127
1128 if (!IS_ERR(ourport->baudclk))
1129 clk_prepare_enable(ourport->baudclk);
1130
1131 break;
1132 default:
1133 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1134 }
1135}
1136
1137/* baud rate calculation
1138 *
1139 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1140 * of different sources, including the peripheral clock ("pclk") and an
1141 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1142 * with a programmable extra divisor.
1143 *
1144 * The following code goes through the clock sources, and calculates the
1145 * baud clocks (and the resultant actual baud rates) and then tries to
1146 * pick the closest one and select that.
1147 *
1148*/
1149
1150#define MAX_CLK_NAME_LENGTH 15
1151
1152static inline int s3c24xx_serial_getsource(struct uart_port *port)
1153{
1154 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1155 unsigned int ucon;
1156
1157 if (info->num_clks == 1)
1158 return 0;
1159
1160 ucon = rd_regl(port, S3C2410_UCON);
1161 ucon &= info->clksel_mask;
1162 return ucon >> info->clksel_shift;
1163}
1164
1165static void s3c24xx_serial_setsource(struct uart_port *port,
1166 unsigned int clk_sel)
1167{
1168 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1169 unsigned int ucon;
1170
1171 if (info->num_clks == 1)
1172 return;
1173
1174 ucon = rd_regl(port, S3C2410_UCON);
1175 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1176 return;
1177
1178 ucon &= ~info->clksel_mask;
1179 ucon |= clk_sel << info->clksel_shift;
1180 wr_regl(port, S3C2410_UCON, ucon);
1181}
1182
1183static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1184 unsigned int req_baud, struct clk **best_clk,
1185 unsigned int *clk_num)
1186{
1187 struct s3c24xx_uart_info *info = ourport->info;
1188 struct clk *clk;
1189 unsigned long rate;
1190 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1191 char clkname[MAX_CLK_NAME_LENGTH];
1192 int calc_deviation, deviation = (1 << 30) - 1;
1193
1194 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1195 ourport->info->def_clk_sel;
1196 for (cnt = 0; cnt < info->num_clks; cnt++) {
1197 if (!(clk_sel & (1 << cnt)))
1198 continue;
1199
1200 sprintf(clkname, "clk_uart_baud%d", cnt);
1201 clk = clk_get(ourport->port.dev, clkname);
1202 if (IS_ERR(clk))
1203 continue;
1204
1205 rate = clk_get_rate(clk);
1206 if (!rate)
1207 continue;
1208
1209 if (ourport->info->has_divslot) {
1210 unsigned long div = rate / req_baud;
1211
1212 /* The UDIVSLOT register on the newer UARTs allows us to
1213 * get a divisor adjustment of 1/16th on the baud clock.
1214 *
1215 * We don't keep the UDIVSLOT value (the 16ths we
1216 * calculated by not multiplying the baud by 16) as it
1217 * is easy enough to recalculate.
1218 */
1219
1220 quot = div / 16;
1221 baud = rate / div;
1222 } else {
1223 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1224 baud = rate / (quot * 16);
1225 }
1226 quot--;
1227
1228 calc_deviation = req_baud - baud;
1229 if (calc_deviation < 0)
1230 calc_deviation = -calc_deviation;
1231
1232 if (calc_deviation < deviation) {
1233 *best_clk = clk;
1234 best_quot = quot;
1235 *clk_num = cnt;
1236 deviation = calc_deviation;
1237 }
1238 }
1239
1240 return best_quot;
1241}
1242
1243/* udivslot_table[]
1244 *
1245 * This table takes the fractional value of the baud divisor and gives
1246 * the recommended setting for the UDIVSLOT register.
1247 */
1248static u16 udivslot_table[16] = {
1249 [0] = 0x0000,
1250 [1] = 0x0080,
1251 [2] = 0x0808,
1252 [3] = 0x0888,
1253 [4] = 0x2222,
1254 [5] = 0x4924,
1255 [6] = 0x4A52,
1256 [7] = 0x54AA,
1257 [8] = 0x5555,
1258 [9] = 0xD555,
1259 [10] = 0xD5D5,
1260 [11] = 0xDDD5,
1261 [12] = 0xDDDD,
1262 [13] = 0xDFDD,
1263 [14] = 0xDFDF,
1264 [15] = 0xFFDF,
1265};
1266
1267static void s3c24xx_serial_set_termios(struct uart_port *port,
1268 struct ktermios *termios,
1269 struct ktermios *old)
1270{
1271 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1272 struct s3c24xx_uart_port *ourport = to_ourport(port);
1273 struct clk *clk = ERR_PTR(-EINVAL);
1274 unsigned long flags;
1275 unsigned int baud, quot, clk_sel = 0;
1276 unsigned int ulcon;
1277 unsigned int umcon;
1278 unsigned int udivslot = 0;
1279
1280 /*
1281 * We don't support modem control lines.
1282 */
1283 termios->c_cflag &= ~(HUPCL | CMSPAR);
1284 termios->c_cflag |= CLOCAL;
1285
1286 /*
1287 * Ask the core to calculate the divisor for us.
1288 */
1289
1290 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1291 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1292 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1293 quot = port->custom_divisor;
1294 if (IS_ERR(clk))
1295 return;
1296
1297 /* check to see if we need to change clock source */
1298
1299 if (ourport->baudclk != clk) {
1300 clk_prepare_enable(clk);
1301
1302 s3c24xx_serial_setsource(port, clk_sel);
1303
1304 if (!IS_ERR(ourport->baudclk)) {
1305 clk_disable_unprepare(ourport->baudclk);
1306 ourport->baudclk = ERR_PTR(-EINVAL);
1307 }
1308
1309 ourport->baudclk = clk;
1310 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1311 }
1312
1313 if (ourport->info->has_divslot) {
1314 unsigned int div = ourport->baudclk_rate / baud;
1315
1316 if (cfg->has_fracval) {
1317 udivslot = (div & 15);
1318 dbg("fracval = %04x\n", udivslot);
1319 } else {
1320 udivslot = udivslot_table[div & 15];
1321 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1322 }
1323 }
1324
1325 switch (termios->c_cflag & CSIZE) {
1326 case CS5:
1327 dbg("config: 5bits/char\n");
1328 ulcon = S3C2410_LCON_CS5;
1329 break;
1330 case CS6:
1331 dbg("config: 6bits/char\n");
1332 ulcon = S3C2410_LCON_CS6;
1333 break;
1334 case CS7:
1335 dbg("config: 7bits/char\n");
1336 ulcon = S3C2410_LCON_CS7;
1337 break;
1338 case CS8:
1339 default:
1340 dbg("config: 8bits/char\n");
1341 ulcon = S3C2410_LCON_CS8;
1342 break;
1343 }
1344
1345 /* preserve original lcon IR settings */
1346 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1347
1348 if (termios->c_cflag & CSTOPB)
1349 ulcon |= S3C2410_LCON_STOPB;
1350
1351 if (termios->c_cflag & PARENB) {
1352 if (termios->c_cflag & PARODD)
1353 ulcon |= S3C2410_LCON_PODD;
1354 else
1355 ulcon |= S3C2410_LCON_PEVEN;
1356 } else {
1357 ulcon |= S3C2410_LCON_PNONE;
1358 }
1359
1360 spin_lock_irqsave(&port->lock, flags);
1361
1362 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1363 ulcon, quot, udivslot);
1364
1365 wr_regl(port, S3C2410_ULCON, ulcon);
1366 wr_regl(port, S3C2410_UBRDIV, quot);
1367
1368 port->status &= ~UPSTAT_AUTOCTS;
1369
1370 umcon = rd_regl(port, S3C2410_UMCON);
1371 if (termios->c_cflag & CRTSCTS) {
1372 umcon |= S3C2410_UMCOM_AFC;
1373 /* Disable RTS when RX FIFO contains 63 bytes */
1374 umcon &= ~S3C2412_UMCON_AFC_8;
1375 port->status = UPSTAT_AUTOCTS;
1376 } else {
1377 umcon &= ~S3C2410_UMCOM_AFC;
1378 }
1379 wr_regl(port, S3C2410_UMCON, umcon);
1380
1381 if (ourport->info->has_divslot)
1382 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1383
1384 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1385 rd_regl(port, S3C2410_ULCON),
1386 rd_regl(port, S3C2410_UCON),
1387 rd_regl(port, S3C2410_UFCON));
1388
1389 /*
1390 * Update the per-port timeout.
1391 */
1392 uart_update_timeout(port, termios->c_cflag, baud);
1393
1394 /*
1395 * Which character status flags are we interested in?
1396 */
1397 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1398 if (termios->c_iflag & INPCK)
1399 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1400 S3C2410_UERSTAT_PARITY;
1401 /*
1402 * Which character status flags should we ignore?
1403 */
1404 port->ignore_status_mask = 0;
1405 if (termios->c_iflag & IGNPAR)
1406 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1407 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1408 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1409
1410 /*
1411 * Ignore all characters if CREAD is not set.
1412 */
1413 if ((termios->c_cflag & CREAD) == 0)
1414 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1415
1416 spin_unlock_irqrestore(&port->lock, flags);
1417}
1418
1419static const char *s3c24xx_serial_type(struct uart_port *port)
1420{
1421 switch (port->type) {
1422 case PORT_S3C2410:
1423 return "S3C2410";
1424 case PORT_S3C2440:
1425 return "S3C2440";
1426 case PORT_S3C2412:
1427 return "S3C2412";
1428 case PORT_S3C6400:
1429 return "S3C6400/10";
1430 default:
1431 return NULL;
1432 }
1433}
1434
1435#define MAP_SIZE (0x100)
1436
1437static void s3c24xx_serial_release_port(struct uart_port *port)
1438{
1439 release_mem_region(port->mapbase, MAP_SIZE);
1440}
1441
1442static int s3c24xx_serial_request_port(struct uart_port *port)
1443{
1444 const char *name = s3c24xx_serial_portname(port);
1445 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1446}
1447
1448static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1449{
1450 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1451
1452 if (flags & UART_CONFIG_TYPE &&
1453 s3c24xx_serial_request_port(port) == 0)
1454 port->type = info->type;
1455}
1456
1457/*
1458 * verify the new serial_struct (for TIOCSSERIAL).
1459 */
1460static int
1461s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1462{
1463 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1464
1465 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1466 return -EINVAL;
1467
1468 return 0;
1469}
1470
1471
1472#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1473
1474static struct console s3c24xx_serial_console;
1475
1476static int __init s3c24xx_serial_console_init(void)
1477{
1478 register_console(&s3c24xx_serial_console);
1479 return 0;
1480}
1481console_initcall(s3c24xx_serial_console_init);
1482
1483#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1484#else
1485#define S3C24XX_SERIAL_CONSOLE NULL
1486#endif
1487
1488#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1489static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1490static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1491 unsigned char c);
1492#endif
1493
1494static struct uart_ops s3c24xx_serial_ops = {
1495 .pm = s3c24xx_serial_pm,
1496 .tx_empty = s3c24xx_serial_tx_empty,
1497 .get_mctrl = s3c24xx_serial_get_mctrl,
1498 .set_mctrl = s3c24xx_serial_set_mctrl,
1499 .stop_tx = s3c24xx_serial_stop_tx,
1500 .start_tx = s3c24xx_serial_start_tx,
1501 .stop_rx = s3c24xx_serial_stop_rx,
1502 .break_ctl = s3c24xx_serial_break_ctl,
1503 .startup = s3c24xx_serial_startup,
1504 .shutdown = s3c24xx_serial_shutdown,
1505 .set_termios = s3c24xx_serial_set_termios,
1506 .type = s3c24xx_serial_type,
1507 .release_port = s3c24xx_serial_release_port,
1508 .request_port = s3c24xx_serial_request_port,
1509 .config_port = s3c24xx_serial_config_port,
1510 .verify_port = s3c24xx_serial_verify_port,
1511#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1512 .poll_get_char = s3c24xx_serial_get_poll_char,
1513 .poll_put_char = s3c24xx_serial_put_poll_char,
1514#endif
1515};
1516
1517static struct uart_driver s3c24xx_uart_drv = {
1518 .owner = THIS_MODULE,
1519 .driver_name = "s3c2410_serial",
1520 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1521 .cons = S3C24XX_SERIAL_CONSOLE,
1522 .dev_name = S3C24XX_SERIAL_NAME,
1523 .major = S3C24XX_SERIAL_MAJOR,
1524 .minor = S3C24XX_SERIAL_MINOR,
1525};
1526
1527#define __PORT_LOCK_UNLOCKED(i) \
1528 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1529static struct s3c24xx_uart_port
1530s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1531 [0] = {
1532 .port = {
1533 .lock = __PORT_LOCK_UNLOCKED(0),
1534 .iotype = UPIO_MEM,
1535 .uartclk = 0,
1536 .fifosize = 16,
1537 .ops = &s3c24xx_serial_ops,
1538 .flags = UPF_BOOT_AUTOCONF,
1539 .line = 0,
1540 }
1541 },
1542 [1] = {
1543 .port = {
1544 .lock = __PORT_LOCK_UNLOCKED(1),
1545 .iotype = UPIO_MEM,
1546 .uartclk = 0,
1547 .fifosize = 16,
1548 .ops = &s3c24xx_serial_ops,
1549 .flags = UPF_BOOT_AUTOCONF,
1550 .line = 1,
1551 }
1552 },
1553#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1554
1555 [2] = {
1556 .port = {
1557 .lock = __PORT_LOCK_UNLOCKED(2),
1558 .iotype = UPIO_MEM,
1559 .uartclk = 0,
1560 .fifosize = 16,
1561 .ops = &s3c24xx_serial_ops,
1562 .flags = UPF_BOOT_AUTOCONF,
1563 .line = 2,
1564 }
1565 },
1566#endif
1567#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1568 [3] = {
1569 .port = {
1570 .lock = __PORT_LOCK_UNLOCKED(3),
1571 .iotype = UPIO_MEM,
1572 .uartclk = 0,
1573 .fifosize = 16,
1574 .ops = &s3c24xx_serial_ops,
1575 .flags = UPF_BOOT_AUTOCONF,
1576 .line = 3,
1577 }
1578 }
1579#endif
1580};
1581#undef __PORT_LOCK_UNLOCKED
1582
1583/* s3c24xx_serial_resetport
1584 *
1585 * reset the fifos and other the settings.
1586*/
1587
1588static void s3c24xx_serial_resetport(struct uart_port *port,
1589 struct s3c2410_uartcfg *cfg)
1590{
1591 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1592 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1593 unsigned int ucon_mask;
1594
1595 ucon_mask = info->clksel_mask;
1596 if (info->type == PORT_S3C2440)
1597 ucon_mask |= S3C2440_UCON0_DIVMASK;
1598
1599 ucon &= ucon_mask;
1600 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1601
1602 /* reset both fifos */
1603 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1604 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1605
1606 /* some delay is required after fifo reset */
1607 udelay(1);
1608}
1609
1610
1611#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1612
1613static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1614 unsigned long val, void *data)
1615{
1616 struct s3c24xx_uart_port *port;
1617 struct uart_port *uport;
1618
1619 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1620 uport = &port->port;
1621
1622 /* check to see if port is enabled */
1623
1624 if (port->pm_level != 0)
1625 return 0;
1626
1627 /* try and work out if the baudrate is changing, we can detect
1628 * a change in rate, but we do not have support for detecting
1629 * a disturbance in the clock-rate over the change.
1630 */
1631
1632 if (IS_ERR(port->baudclk))
1633 goto exit;
1634
1635 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1636 goto exit;
1637
1638 if (val == CPUFREQ_PRECHANGE) {
1639 /* we should really shut the port down whilst the
1640 * frequency change is in progress. */
1641
1642 } else if (val == CPUFREQ_POSTCHANGE) {
1643 struct ktermios *termios;
1644 struct tty_struct *tty;
1645
1646 if (uport->state == NULL)
1647 goto exit;
1648
1649 tty = uport->state->port.tty;
1650
1651 if (tty == NULL)
1652 goto exit;
1653
1654 termios = &tty->termios;
1655
1656 if (termios == NULL) {
1657 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1658 goto exit;
1659 }
1660
1661 s3c24xx_serial_set_termios(uport, termios, NULL);
1662 }
1663
1664exit:
1665 return 0;
1666}
1667
1668static inline int
1669s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1670{
1671 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1672
1673 return cpufreq_register_notifier(&port->freq_transition,
1674 CPUFREQ_TRANSITION_NOTIFIER);
1675}
1676
1677static inline void
1678s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1679{
1680 cpufreq_unregister_notifier(&port->freq_transition,
1681 CPUFREQ_TRANSITION_NOTIFIER);
1682}
1683
1684#else
1685static inline int
1686s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1687{
1688 return 0;
1689}
1690
1691static inline void
1692s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1693{
1694}
1695#endif
1696
1697static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1698{
1699 struct device *dev = ourport->port.dev;
1700 struct s3c24xx_uart_info *info = ourport->info;
1701 char clk_name[MAX_CLK_NAME_LENGTH];
1702 unsigned int clk_sel;
1703 struct clk *clk;
1704 int clk_num;
1705 int ret;
1706
1707 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1708 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1709 if (!(clk_sel & (1 << clk_num)))
1710 continue;
1711
1712 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1713 clk = clk_get(dev, clk_name);
1714 if (IS_ERR(clk))
1715 continue;
1716
1717 ret = clk_prepare_enable(clk);
1718 if (ret) {
1719 clk_put(clk);
1720 continue;
1721 }
1722
1723 ourport->baudclk = clk;
1724 ourport->baudclk_rate = clk_get_rate(clk);
1725 s3c24xx_serial_setsource(&ourport->port, clk_num);
1726
1727 return 0;
1728 }
1729
1730 return -EINVAL;
1731}
1732
1733/* s3c24xx_serial_init_port
1734 *
1735 * initialise a single serial port from the platform device given
1736 */
1737
1738static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1739 struct platform_device *platdev)
1740{
1741 struct uart_port *port = &ourport->port;
1742 struct s3c2410_uartcfg *cfg = ourport->cfg;
1743 struct resource *res;
1744 int ret;
1745
1746 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1747
1748 if (platdev == NULL)
1749 return -ENODEV;
1750
1751 if (port->mapbase != 0)
1752 return -EINVAL;
1753
1754 /* setup info for port */
1755 port->dev = &platdev->dev;
1756
1757 /* Startup sequence is different for s3c64xx and higher SoC's */
1758 if (s3c24xx_serial_has_interrupt_mask(port))
1759 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1760
1761 port->uartclk = 1;
1762
1763 if (cfg->uart_flags & UPF_CONS_FLOW) {
1764 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1765 port->flags |= UPF_CONS_FLOW;
1766 }
1767
1768 /* sort our the physical and virtual addresses for each UART */
1769
1770 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1771 if (res == NULL) {
1772 dev_err(port->dev, "failed to find memory resource for uart\n");
1773 return -EINVAL;
1774 }
1775
1776 dbg("resource %pR)\n", res);
1777
1778 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1779 if (!port->membase) {
1780 dev_err(port->dev, "failed to remap controller address\n");
1781 return -EBUSY;
1782 }
1783
1784 port->mapbase = res->start;
1785 ret = platform_get_irq(platdev, 0);
1786 if (ret < 0)
1787 port->irq = 0;
1788 else {
1789 port->irq = ret;
1790 ourport->rx_irq = ret;
1791 ourport->tx_irq = ret + 1;
1792 }
1793
1794 ret = platform_get_irq(platdev, 1);
1795 if (ret > 0)
1796 ourport->tx_irq = ret;
1797 /*
1798 * DMA is currently supported only on DT platforms, if DMA properties
1799 * are specified.
1800 */
1801 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1802 "dmas", NULL)) {
1803 ourport->dma = devm_kzalloc(port->dev,
1804 sizeof(*ourport->dma),
1805 GFP_KERNEL);
1806 if (!ourport->dma) {
1807 ret = -ENOMEM;
1808 goto err;
1809 }
1810 }
1811
1812 ourport->clk = clk_get(&platdev->dev, "uart");
1813 if (IS_ERR(ourport->clk)) {
1814 pr_err("%s: Controller clock not found\n",
1815 dev_name(&platdev->dev));
1816 ret = PTR_ERR(ourport->clk);
1817 goto err;
1818 }
1819
1820 ret = clk_prepare_enable(ourport->clk);
1821 if (ret) {
1822 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1823 clk_put(ourport->clk);
1824 goto err;
1825 }
1826
1827 ret = s3c24xx_serial_enable_baudclk(ourport);
1828 if (ret)
1829 pr_warn("uart: failed to enable baudclk\n");
1830
1831 /* Keep all interrupts masked and cleared */
1832 if (s3c24xx_serial_has_interrupt_mask(port)) {
1833 wr_regl(port, S3C64XX_UINTM, 0xf);
1834 wr_regl(port, S3C64XX_UINTP, 0xf);
1835 wr_regl(port, S3C64XX_UINTSP, 0xf);
1836 }
1837
1838 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1839 &port->mapbase, port->membase, port->irq,
1840 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1841
1842 /* reset the fifos (and setup the uart) */
1843 s3c24xx_serial_resetport(port, cfg);
1844
1845 return 0;
1846
1847err:
1848 port->mapbase = 0;
1849 return ret;
1850}
1851
1852/* Device driver serial port probe */
1853
1854static const struct of_device_id s3c24xx_uart_dt_match[];
1855static int probe_index;
1856
1857static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1858 struct platform_device *pdev)
1859{
1860#ifdef CONFIG_OF
1861 if (pdev->dev.of_node) {
1862 const struct of_device_id *match;
1863 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1864 return (struct s3c24xx_serial_drv_data *)match->data;
1865 }
1866#endif
1867 return (struct s3c24xx_serial_drv_data *)
1868 platform_get_device_id(pdev)->driver_data;
1869}
1870
1871static int s3c24xx_serial_probe(struct platform_device *pdev)
1872{
1873 struct device_node *np = pdev->dev.of_node;
1874 struct s3c24xx_uart_port *ourport;
1875 int index = probe_index;
1876 int ret;
1877
1878 if (np) {
1879 ret = of_alias_get_id(np, "serial");
1880 if (ret >= 0)
1881 index = ret;
1882 }
1883
1884 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1885
1886 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1887 dev_err(&pdev->dev, "serial%d out of range\n", index);
1888 return -EINVAL;
1889 }
1890 ourport = &s3c24xx_serial_ports[index];
1891
1892 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1893 if (!ourport->drv_data) {
1894 dev_err(&pdev->dev, "could not find driver data\n");
1895 return -ENODEV;
1896 }
1897
1898 ourport->baudclk = ERR_PTR(-EINVAL);
1899 ourport->info = ourport->drv_data->info;
1900 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1901 dev_get_platdata(&pdev->dev) :
1902 ourport->drv_data->def_cfg;
1903
1904 if (np)
1905 of_property_read_u32(np,
1906 "samsung,uart-fifosize", &ourport->port.fifosize);
1907
1908 if (ourport->drv_data->fifosize[index])
1909 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1910 else if (ourport->info->fifosize)
1911 ourport->port.fifosize = ourport->info->fifosize;
1912
1913 /*
1914 * DMA transfers must be aligned at least to cache line size,
1915 * so find minimal transfer size suitable for DMA mode
1916 */
1917 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1918 dma_get_cache_alignment());
1919
1920 dbg("%s: initialising port %p...\n", __func__, ourport);
1921
1922 ret = s3c24xx_serial_init_port(ourport, pdev);
1923 if (ret < 0)
1924 return ret;
1925
1926 if (!s3c24xx_uart_drv.state) {
1927 ret = uart_register_driver(&s3c24xx_uart_drv);
1928 if (ret < 0) {
1929 pr_err("Failed to register Samsung UART driver\n");
1930 return ret;
1931 }
1932 }
1933
1934 dbg("%s: adding port\n", __func__);
1935 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1936 platform_set_drvdata(pdev, &ourport->port);
1937
1938 /*
1939 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1940 * so that a potential re-enablement through the pm-callback overlaps
1941 * and keeps the clock enabled in this case.
1942 */
1943 clk_disable_unprepare(ourport->clk);
1944 if (!IS_ERR(ourport->baudclk))
1945 clk_disable_unprepare(ourport->baudclk);
1946
1947 ret = s3c24xx_serial_cpufreq_register(ourport);
1948 if (ret < 0)
1949 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1950
1951 probe_index++;
1952
1953 return 0;
1954}
1955
1956static int s3c24xx_serial_remove(struct platform_device *dev)
1957{
1958 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1959
1960 if (port) {
1961 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1962 uart_remove_one_port(&s3c24xx_uart_drv, port);
1963 }
1964
1965 uart_unregister_driver(&s3c24xx_uart_drv);
1966
1967 return 0;
1968}
1969
1970/* UART power management code */
1971#ifdef CONFIG_PM_SLEEP
1972static int s3c24xx_serial_suspend(struct device *dev)
1973{
1974 struct uart_port *port = s3c24xx_dev_to_port(dev);
1975
1976 if (port)
1977 uart_suspend_port(&s3c24xx_uart_drv, port);
1978
1979 return 0;
1980}
1981
1982static int s3c24xx_serial_resume(struct device *dev)
1983{
1984 struct uart_port *port = s3c24xx_dev_to_port(dev);
1985 struct s3c24xx_uart_port *ourport = to_ourport(port);
1986
1987 if (port) {
1988 clk_prepare_enable(ourport->clk);
1989 if (!IS_ERR(ourport->baudclk))
1990 clk_prepare_enable(ourport->baudclk);
1991 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1992 if (!IS_ERR(ourport->baudclk))
1993 clk_disable_unprepare(ourport->baudclk);
1994 clk_disable_unprepare(ourport->clk);
1995
1996 uart_resume_port(&s3c24xx_uart_drv, port);
1997 }
1998
1999 return 0;
2000}
2001
2002static int s3c24xx_serial_resume_noirq(struct device *dev)
2003{
2004 struct uart_port *port = s3c24xx_dev_to_port(dev);
2005 struct s3c24xx_uart_port *ourport = to_ourport(port);
2006
2007 if (port) {
2008 /* restore IRQ mask */
2009 if (s3c24xx_serial_has_interrupt_mask(port)) {
2010 unsigned int uintm = 0xf;
2011 if (tx_enabled(port))
2012 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2013 if (rx_enabled(port))
2014 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2015 clk_prepare_enable(ourport->clk);
2016 if (!IS_ERR(ourport->baudclk))
2017 clk_prepare_enable(ourport->baudclk);
2018 wr_regl(port, S3C64XX_UINTM, uintm);
2019 if (!IS_ERR(ourport->baudclk))
2020 clk_disable_unprepare(ourport->baudclk);
2021 clk_disable_unprepare(ourport->clk);
2022 }
2023 }
2024
2025 return 0;
2026}
2027
2028static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2029 .suspend = s3c24xx_serial_suspend,
2030 .resume = s3c24xx_serial_resume,
2031 .resume_noirq = s3c24xx_serial_resume_noirq,
2032};
2033#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2034
2035#else /* !CONFIG_PM_SLEEP */
2036
2037#define SERIAL_SAMSUNG_PM_OPS NULL
2038#endif /* CONFIG_PM_SLEEP */
2039
2040/* Console code */
2041
2042#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2043
2044static struct uart_port *cons_uart;
2045
2046static int
2047s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2048{
2049 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2050 unsigned long ufstat, utrstat;
2051
2052 if (ufcon & S3C2410_UFCON_FIFOMODE) {
2053 /* fifo mode - check amount of data in fifo registers... */
2054
2055 ufstat = rd_regl(port, S3C2410_UFSTAT);
2056 return (ufstat & info->tx_fifofull) ? 0 : 1;
2057 }
2058
2059 /* in non-fifo mode, we go and use the tx buffer empty */
2060
2061 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2062 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2063}
2064
2065static bool
2066s3c24xx_port_configured(unsigned int ucon)
2067{
2068 /* consider the serial port configured if the tx/rx mode set */
2069 return (ucon & 0xf) != 0;
2070}
2071
2072#ifdef CONFIG_CONSOLE_POLL
2073/*
2074 * Console polling routines for writing and reading from the uart while
2075 * in an interrupt or debug context.
2076 */
2077
2078static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2079{
2080 struct s3c24xx_uart_port *ourport = to_ourport(port);
2081 unsigned int ufstat;
2082
2083 ufstat = rd_regl(port, S3C2410_UFSTAT);
2084 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2085 return NO_POLL_CHAR;
2086
2087 return rd_regb(port, S3C2410_URXH);
2088}
2089
2090static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2091 unsigned char c)
2092{
2093 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2094 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2095
2096 /* not possible to xmit on unconfigured port */
2097 if (!s3c24xx_port_configured(ucon))
2098 return;
2099
2100 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2101 cpu_relax();
2102 wr_regb(port, S3C2410_UTXH, c);
2103}
2104
2105#endif /* CONFIG_CONSOLE_POLL */
2106
2107static void
2108s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2109{
2110 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2111
2112 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2113 cpu_relax();
2114 wr_regb(port, S3C2410_UTXH, ch);
2115}
2116
2117static void
2118s3c24xx_serial_console_write(struct console *co, const char *s,
2119 unsigned int count)
2120{
2121 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2122
2123 /* not possible to xmit on unconfigured port */
2124 if (!s3c24xx_port_configured(ucon))
2125 return;
2126
2127 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2128}
2129
2130static void __init
2131s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2132 int *parity, int *bits)
2133{
2134 struct clk *clk;
2135 unsigned int ulcon;
2136 unsigned int ucon;
2137 unsigned int ubrdiv;
2138 unsigned long rate;
2139 unsigned int clk_sel;
2140 char clk_name[MAX_CLK_NAME_LENGTH];
2141
2142 ulcon = rd_regl(port, S3C2410_ULCON);
2143 ucon = rd_regl(port, S3C2410_UCON);
2144 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2145
2146 dbg("s3c24xx_serial_get_options: port=%p\n"
2147 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2148 port, ulcon, ucon, ubrdiv);
2149
2150 if (s3c24xx_port_configured(ucon)) {
2151 switch (ulcon & S3C2410_LCON_CSMASK) {
2152 case S3C2410_LCON_CS5:
2153 *bits = 5;
2154 break;
2155 case S3C2410_LCON_CS6:
2156 *bits = 6;
2157 break;
2158 case S3C2410_LCON_CS7:
2159 *bits = 7;
2160 break;
2161 case S3C2410_LCON_CS8:
2162 default:
2163 *bits = 8;
2164 break;
2165 }
2166
2167 switch (ulcon & S3C2410_LCON_PMASK) {
2168 case S3C2410_LCON_PEVEN:
2169 *parity = 'e';
2170 break;
2171
2172 case S3C2410_LCON_PODD:
2173 *parity = 'o';
2174 break;
2175
2176 case S3C2410_LCON_PNONE:
2177 default:
2178 *parity = 'n';
2179 }
2180
2181 /* now calculate the baud rate */
2182
2183 clk_sel = s3c24xx_serial_getsource(port);
2184 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2185
2186 clk = clk_get(port->dev, clk_name);
2187 if (!IS_ERR(clk))
2188 rate = clk_get_rate(clk);
2189 else
2190 rate = 1;
2191
2192 *baud = rate / (16 * (ubrdiv + 1));
2193 dbg("calculated baud %d\n", *baud);
2194 }
2195
2196}
2197
2198static int __init
2199s3c24xx_serial_console_setup(struct console *co, char *options)
2200{
2201 struct uart_port *port;
2202 int baud = 9600;
2203 int bits = 8;
2204 int parity = 'n';
2205 int flow = 'n';
2206
2207 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2208 co, co->index, options);
2209
2210 /* is this a valid port */
2211
2212 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2213 co->index = 0;
2214
2215 port = &s3c24xx_serial_ports[co->index].port;
2216
2217 /* is the port configured? */
2218
2219 if (port->mapbase == 0x0)
2220 return -ENODEV;
2221
2222 cons_uart = port;
2223
2224 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2225
2226 /*
2227 * Check whether an invalid uart number has been specified, and
2228 * if so, search for the first available port that does have
2229 * console support.
2230 */
2231 if (options)
2232 uart_parse_options(options, &baud, &parity, &bits, &flow);
2233 else
2234 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2235
2236 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2237
2238 return uart_set_options(port, co, baud, parity, bits, flow);
2239}
2240
2241static struct console s3c24xx_serial_console = {
2242 .name = S3C24XX_SERIAL_NAME,
2243 .device = uart_console_device,
2244 .flags = CON_PRINTBUFFER,
2245 .index = -1,
2246 .write = s3c24xx_serial_console_write,
2247 .setup = s3c24xx_serial_console_setup,
2248 .data = &s3c24xx_uart_drv,
2249};
2250#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2251
2252#ifdef CONFIG_CPU_S3C2410
2253static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2254 .info = &(struct s3c24xx_uart_info) {
2255 .name = "Samsung S3C2410 UART",
2256 .type = PORT_S3C2410,
2257 .fifosize = 16,
2258 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2259 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2260 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2261 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2262 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2263 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2264 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2265 .num_clks = 2,
2266 .clksel_mask = S3C2410_UCON_CLKMASK,
2267 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2268 },
2269 .def_cfg = &(struct s3c2410_uartcfg) {
2270 .ucon = S3C2410_UCON_DEFAULT,
2271 .ufcon = S3C2410_UFCON_DEFAULT,
2272 },
2273};
2274#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2275#else
2276#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2277#endif
2278
2279#ifdef CONFIG_CPU_S3C2412
2280static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2281 .info = &(struct s3c24xx_uart_info) {
2282 .name = "Samsung S3C2412 UART",
2283 .type = PORT_S3C2412,
2284 .fifosize = 64,
2285 .has_divslot = 1,
2286 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2287 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2288 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2289 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2290 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2291 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2292 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2293 .num_clks = 4,
2294 .clksel_mask = S3C2412_UCON_CLKMASK,
2295 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2296 },
2297 .def_cfg = &(struct s3c2410_uartcfg) {
2298 .ucon = S3C2410_UCON_DEFAULT,
2299 .ufcon = S3C2410_UFCON_DEFAULT,
2300 },
2301};
2302#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2303#else
2304#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2305#endif
2306
2307#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2308 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2309static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2310 .info = &(struct s3c24xx_uart_info) {
2311 .name = "Samsung S3C2440 UART",
2312 .type = PORT_S3C2440,
2313 .fifosize = 64,
2314 .has_divslot = 1,
2315 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2316 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2317 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2318 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2319 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2320 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2321 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2322 .num_clks = 4,
2323 .clksel_mask = S3C2412_UCON_CLKMASK,
2324 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2325 },
2326 .def_cfg = &(struct s3c2410_uartcfg) {
2327 .ucon = S3C2410_UCON_DEFAULT,
2328 .ufcon = S3C2410_UFCON_DEFAULT,
2329 },
2330};
2331#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2332#else
2333#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2334#endif
2335
2336#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2337static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2338 .info = &(struct s3c24xx_uart_info) {
2339 .name = "Samsung S3C6400 UART",
2340 .type = PORT_S3C6400,
2341 .fifosize = 64,
2342 .has_divslot = 1,
2343 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2344 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2345 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2346 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2347 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2348 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2349 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2350 .num_clks = 4,
2351 .clksel_mask = S3C6400_UCON_CLKMASK,
2352 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2353 },
2354 .def_cfg = &(struct s3c2410_uartcfg) {
2355 .ucon = S3C2410_UCON_DEFAULT,
2356 .ufcon = S3C2410_UFCON_DEFAULT,
2357 },
2358};
2359#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2360#else
2361#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2362#endif
2363
2364#ifdef CONFIG_CPU_S5PV210
2365static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2366 .info = &(struct s3c24xx_uart_info) {
2367 .name = "Samsung S5PV210 UART",
2368 .type = PORT_S3C6400,
2369 .has_divslot = 1,
2370 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2371 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2372 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2373 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2374 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2375 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2376 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2377 .num_clks = 2,
2378 .clksel_mask = S5PV210_UCON_CLKMASK,
2379 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2380 },
2381 .def_cfg = &(struct s3c2410_uartcfg) {
2382 .ucon = S5PV210_UCON_DEFAULT,
2383 .ufcon = S5PV210_UFCON_DEFAULT,
2384 },
2385 .fifosize = { 256, 64, 16, 16 },
2386};
2387#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2388#else
2389#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2390#endif
2391
2392#if defined(CONFIG_ARCH_EXYNOS)
2393#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2394 .info = &(struct s3c24xx_uart_info) { \
2395 .name = "Samsung Exynos UART", \
2396 .type = PORT_S3C6400, \
2397 .has_divslot = 1, \
2398 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2399 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2400 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2401 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2402 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2403 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2404 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2405 .num_clks = 1, \
2406 .clksel_mask = 0, \
2407 .clksel_shift = 0, \
2408 }, \
2409 .def_cfg = &(struct s3c2410_uartcfg) { \
2410 .ucon = S5PV210_UCON_DEFAULT, \
2411 .ufcon = S5PV210_UFCON_DEFAULT, \
2412 .has_fracval = 1, \
2413 } \
2414
2415static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2416 EXYNOS_COMMON_SERIAL_DRV_DATA,
2417 .fifosize = { 256, 64, 16, 16 },
2418};
2419
2420static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2421 EXYNOS_COMMON_SERIAL_DRV_DATA,
2422 .fifosize = { 64, 256, 16, 256 },
2423};
2424
2425#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2426#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2427#else
2428#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2429#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2430#endif
2431
2432static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2433 {
2434 .name = "s3c2410-uart",
2435 .driver_data = S3C2410_SERIAL_DRV_DATA,
2436 }, {
2437 .name = "s3c2412-uart",
2438 .driver_data = S3C2412_SERIAL_DRV_DATA,
2439 }, {
2440 .name = "s3c2440-uart",
2441 .driver_data = S3C2440_SERIAL_DRV_DATA,
2442 }, {
2443 .name = "s3c6400-uart",
2444 .driver_data = S3C6400_SERIAL_DRV_DATA,
2445 }, {
2446 .name = "s5pv210-uart",
2447 .driver_data = S5PV210_SERIAL_DRV_DATA,
2448 }, {
2449 .name = "exynos4210-uart",
2450 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2451 }, {
2452 .name = "exynos5433-uart",
2453 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2454 },
2455 { },
2456};
2457MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2458
2459#ifdef CONFIG_OF
2460static const struct of_device_id s3c24xx_uart_dt_match[] = {
2461 { .compatible = "samsung,s3c2410-uart",
2462 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2463 { .compatible = "samsung,s3c2412-uart",
2464 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2465 { .compatible = "samsung,s3c2440-uart",
2466 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2467 { .compatible = "samsung,s3c6400-uart",
2468 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2469 { .compatible = "samsung,s5pv210-uart",
2470 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2471 { .compatible = "samsung,exynos4210-uart",
2472 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2473 { .compatible = "samsung,exynos5433-uart",
2474 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2475 {},
2476};
2477MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2478#endif
2479
2480static struct platform_driver samsung_serial_driver = {
2481 .probe = s3c24xx_serial_probe,
2482 .remove = s3c24xx_serial_remove,
2483 .id_table = s3c24xx_serial_driver_ids,
2484 .driver = {
2485 .name = "samsung-uart",
2486 .pm = SERIAL_SAMSUNG_PM_OPS,
2487 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2488 },
2489};
2490
2491module_platform_driver(samsung_serial_driver);
2492
2493#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2494/*
2495 * Early console.
2496 */
2497
2498struct samsung_early_console_data {
2499 u32 txfull_mask;
2500};
2501
2502static void samsung_early_busyuart(struct uart_port *port)
2503{
2504 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2505 ;
2506}
2507
2508static void samsung_early_busyuart_fifo(struct uart_port *port)
2509{
2510 struct samsung_early_console_data *data = port->private_data;
2511
2512 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2513 ;
2514}
2515
2516static void samsung_early_putc(struct uart_port *port, int c)
2517{
2518 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2519 samsung_early_busyuart_fifo(port);
2520 else
2521 samsung_early_busyuart(port);
2522
2523 writeb(c, port->membase + S3C2410_UTXH);
2524}
2525
2526static void samsung_early_write(struct console *con, const char *s, unsigned n)
2527{
2528 struct earlycon_device *dev = con->data;
2529
2530 uart_console_write(&dev->port, s, n, samsung_early_putc);
2531}
2532
2533static int __init samsung_early_console_setup(struct earlycon_device *device,
2534 const char *opt)
2535{
2536 if (!device->port.membase)
2537 return -ENODEV;
2538
2539 device->con->write = samsung_early_write;
2540 return 0;
2541}
2542
2543/* S3C2410 */
2544static struct samsung_early_console_data s3c2410_early_console_data = {
2545 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2546};
2547
2548static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2549 const char *opt)
2550{
2551 device->port.private_data = &s3c2410_early_console_data;
2552 return samsung_early_console_setup(device, opt);
2553}
2554OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2555 s3c2410_early_console_setup);
2556
2557/* S3C2412, S3C2440, S3C64xx */
2558static struct samsung_early_console_data s3c2440_early_console_data = {
2559 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2560};
2561
2562static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2563 const char *opt)
2564{
2565 device->port.private_data = &s3c2440_early_console_data;
2566 return samsung_early_console_setup(device, opt);
2567}
2568OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2569 s3c2440_early_console_setup);
2570OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2571 s3c2440_early_console_setup);
2572OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2573 s3c2440_early_console_setup);
2574
2575/* S5PV210, EXYNOS */
2576static struct samsung_early_console_data s5pv210_early_console_data = {
2577 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2578};
2579
2580static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2581 const char *opt)
2582{
2583 device->port.private_data = &s5pv210_early_console_data;
2584 return samsung_early_console_setup(device, opt);
2585}
2586OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2587 s5pv210_early_console_setup);
2588OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2589 s5pv210_early_console_setup);
2590#endif
2591
2592MODULE_ALIAS("platform:samsung-uart");
2593MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2594MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2595MODULE_LICENSE("GPL v2");