Loading...
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11#include <linux/circ_buf.h>
12#include <linux/tty.h>
13#include <linux/ioport.h>
14#include <linux/slab.h>
15#include <linux/init.h>
16#include <linux/serial.h>
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/console.h>
20#include <linux/sysrq.h>
21#include <linux/tty_flip.h>
22#include <linux/platform_device.h>
23#include <linux/of.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/atmel_pdc.h>
27#include <linux/uaccess.h>
28#include <linux/platform_data/atmel.h>
29#include <linux/timer.h>
30#include <linux/err.h>
31#include <linux/irq.h>
32#include <linux/suspend.h>
33#include <linux/mm.h>
34#include <linux/io.h>
35
36#include <asm/div64.h>
37#include <asm/ioctls.h>
38
39#define PDC_BUFFER_SIZE 512
40/* Revisit: We should calculate this based on the actual port settings */
41#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
42
43/* The minium number of data FIFOs should be able to contain */
44#define ATMEL_MIN_FIFO_SIZE 8
45/*
46 * These two offsets are substracted from the RX FIFO size to define the RTS
47 * high and low thresholds
48 */
49#define ATMEL_RTS_HIGH_OFFSET 16
50#define ATMEL_RTS_LOW_OFFSET 20
51
52#include <linux/serial_core.h>
53
54#include "serial_mctrl_gpio.h"
55#include "atmel_serial.h"
56
57static void atmel_start_rx(struct uart_port *port);
58static void atmel_stop_rx(struct uart_port *port);
59
60#ifdef CONFIG_SERIAL_ATMEL_TTYAT
61
62/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
63 * should coexist with the 8250 driver, such as if we have an external 16C550
64 * UART. */
65#define SERIAL_ATMEL_MAJOR 204
66#define MINOR_START 154
67#define ATMEL_DEVICENAME "ttyAT"
68
69#else
70
71/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
72 * name, but it is legally reserved for the 8250 driver. */
73#define SERIAL_ATMEL_MAJOR TTY_MAJOR
74#define MINOR_START 64
75#define ATMEL_DEVICENAME "ttyS"
76
77#endif
78
79#define ATMEL_ISR_PASS_LIMIT 256
80
81struct atmel_dma_buffer {
82 unsigned char *buf;
83 dma_addr_t dma_addr;
84 unsigned int dma_size;
85 unsigned int ofs;
86};
87
88struct atmel_uart_char {
89 u16 status;
90 u16 ch;
91};
92
93/*
94 * Be careful, the real size of the ring buffer is
95 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
96 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
97 * DMA mode.
98 */
99#define ATMEL_SERIAL_RINGSIZE 1024
100
101/*
102 * at91: 6 USARTs and one DBGU port (SAM9260)
103 * samx7: 3 USARTs and 5 UARTs
104 */
105#define ATMEL_MAX_UART 8
106
107/*
108 * We wrap our port structure around the generic uart_port.
109 */
110struct atmel_uart_port {
111 struct uart_port uart; /* uart */
112 struct clk *clk; /* uart clock */
113 struct clk *gclk; /* uart generic clock */
114 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
115 u32 backup_imr; /* IMR saved during suspend */
116 int break_active; /* break being received */
117
118 bool use_dma_rx; /* enable DMA receiver */
119 bool use_pdc_rx; /* enable PDC receiver */
120 short pdc_rx_idx; /* current PDC RX buffer */
121 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
122
123 bool use_dma_tx; /* enable DMA transmitter */
124 bool use_pdc_tx; /* enable PDC transmitter */
125 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
126
127 spinlock_t lock_tx; /* port lock */
128 spinlock_t lock_rx; /* port lock */
129 struct dma_chan *chan_tx;
130 struct dma_chan *chan_rx;
131 struct dma_async_tx_descriptor *desc_tx;
132 struct dma_async_tx_descriptor *desc_rx;
133 dma_cookie_t cookie_tx;
134 dma_cookie_t cookie_rx;
135 struct scatterlist sg_tx;
136 struct scatterlist sg_rx;
137 struct tasklet_struct tasklet_rx;
138 struct tasklet_struct tasklet_tx;
139 atomic_t tasklet_shutdown;
140 unsigned int irq_status_prev;
141 unsigned int tx_len;
142
143 struct circ_buf rx_ring;
144
145 struct mctrl_gpios *gpios;
146 u32 backup_mode; /* MR saved during iso7816 operations */
147 u32 backup_brgr; /* BRGR saved during iso7816 operations */
148 unsigned int tx_done_mask;
149 u32 fifo_size;
150 u32 rts_high;
151 u32 rts_low;
152 bool ms_irq_enabled;
153 u32 rtor; /* address of receiver timeout register if it exists */
154 bool is_usart;
155 bool has_frac_baudrate;
156 bool has_hw_timer;
157 struct timer_list uart_timer;
158
159 bool tx_stopped;
160 bool suspended;
161 unsigned int pending;
162 unsigned int pending_status;
163 spinlock_t lock_suspended;
164
165 bool hd_start_rx; /* can start RX during half-duplex operation */
166
167 /* ISO7816 */
168 unsigned int fidi_min;
169 unsigned int fidi_max;
170
171 struct {
172 u32 cr;
173 u32 mr;
174 u32 imr;
175 u32 brgr;
176 u32 rtor;
177 u32 ttgr;
178 u32 fmr;
179 u32 fimr;
180 } cache;
181
182 int (*prepare_rx)(struct uart_port *port);
183 int (*prepare_tx)(struct uart_port *port);
184 void (*schedule_rx)(struct uart_port *port);
185 void (*schedule_tx)(struct uart_port *port);
186 void (*release_rx)(struct uart_port *port);
187 void (*release_tx)(struct uart_port *port);
188};
189
190static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
191static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
192
193#if defined(CONFIG_OF)
194static const struct of_device_id atmel_serial_dt_ids[] = {
195 { .compatible = "atmel,at91rm9200-usart-serial" },
196 { /* sentinel */ }
197};
198#endif
199
200static inline struct atmel_uart_port *
201to_atmel_uart_port(struct uart_port *uart)
202{
203 return container_of(uart, struct atmel_uart_port, uart);
204}
205
206static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
207{
208 return __raw_readl(port->membase + reg);
209}
210
211static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
212{
213 __raw_writel(value, port->membase + reg);
214}
215
216static inline u8 atmel_uart_read_char(struct uart_port *port)
217{
218 return __raw_readb(port->membase + ATMEL_US_RHR);
219}
220
221static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
222{
223 __raw_writeb(value, port->membase + ATMEL_US_THR);
224}
225
226static inline int atmel_uart_is_half_duplex(struct uart_port *port)
227{
228 return ((port->rs485.flags & SER_RS485_ENABLED) &&
229 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
230 (port->iso7816.flags & SER_ISO7816_ENABLED);
231}
232
233static inline int atmel_error_rate(int desired_value, int actual_value)
234{
235 return 100 - (desired_value * 100) / actual_value;
236}
237
238#ifdef CONFIG_SERIAL_ATMEL_PDC
239static bool atmel_use_pdc_rx(struct uart_port *port)
240{
241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
242
243 return atmel_port->use_pdc_rx;
244}
245
246static bool atmel_use_pdc_tx(struct uart_port *port)
247{
248 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
249
250 return atmel_port->use_pdc_tx;
251}
252#else
253static bool atmel_use_pdc_rx(struct uart_port *port)
254{
255 return false;
256}
257
258static bool atmel_use_pdc_tx(struct uart_port *port)
259{
260 return false;
261}
262#endif
263
264static bool atmel_use_dma_tx(struct uart_port *port)
265{
266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
267
268 return atmel_port->use_dma_tx;
269}
270
271static bool atmel_use_dma_rx(struct uart_port *port)
272{
273 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
274
275 return atmel_port->use_dma_rx;
276}
277
278static bool atmel_use_fifo(struct uart_port *port)
279{
280 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
281
282 return atmel_port->fifo_size;
283}
284
285static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
286 struct tasklet_struct *t)
287{
288 if (!atomic_read(&atmel_port->tasklet_shutdown))
289 tasklet_schedule(t);
290}
291
292/* Enable or disable the rs485 support */
293static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
294 struct serial_rs485 *rs485conf)
295{
296 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
297 unsigned int mode;
298
299 /* Disable interrupts */
300 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
301
302 mode = atmel_uart_readl(port, ATMEL_US_MR);
303
304 if (rs485conf->flags & SER_RS485_ENABLED) {
305 dev_dbg(port->dev, "Setting UART to RS485\n");
306 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
307 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
308 else
309 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
310
311 atmel_uart_writel(port, ATMEL_US_TTGR,
312 rs485conf->delay_rts_after_send);
313 mode &= ~ATMEL_US_USMODE;
314 mode |= ATMEL_US_USMODE_RS485;
315 } else {
316 dev_dbg(port->dev, "Setting UART to RS232\n");
317 if (atmel_use_pdc_tx(port))
318 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
319 ATMEL_US_TXBUFE;
320 else
321 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
322 }
323 atmel_uart_writel(port, ATMEL_US_MR, mode);
324
325 /* Enable interrupts */
326 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
327
328 return 0;
329}
330
331static unsigned int atmel_calc_cd(struct uart_port *port,
332 struct serial_iso7816 *iso7816conf)
333{
334 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
335 unsigned int cd;
336 u64 mck_rate;
337
338 mck_rate = (u64)clk_get_rate(atmel_port->clk);
339 do_div(mck_rate, iso7816conf->clk);
340 cd = mck_rate;
341 return cd;
342}
343
344static unsigned int atmel_calc_fidi(struct uart_port *port,
345 struct serial_iso7816 *iso7816conf)
346{
347 u64 fidi = 0;
348
349 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
350 fidi = (u64)iso7816conf->sc_fi;
351 do_div(fidi, iso7816conf->sc_di);
352 }
353 return (u32)fidi;
354}
355
356/* Enable or disable the iso7816 support */
357/* Called with interrupts disabled */
358static int atmel_config_iso7816(struct uart_port *port,
359 struct serial_iso7816 *iso7816conf)
360{
361 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
362 unsigned int mode;
363 unsigned int cd, fidi;
364 int ret = 0;
365
366 /* Disable interrupts */
367 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
368
369 mode = atmel_uart_readl(port, ATMEL_US_MR);
370
371 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
372 mode &= ~ATMEL_US_USMODE;
373
374 if (iso7816conf->tg > 255) {
375 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
376 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
377 ret = -EINVAL;
378 goto err_out;
379 }
380
381 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
382 == SER_ISO7816_T(0)) {
383 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
384 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
385 == SER_ISO7816_T(1)) {
386 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
387 } else {
388 dev_err(port->dev, "ISO7816: Type not supported\n");
389 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
390 ret = -EINVAL;
391 goto err_out;
392 }
393
394 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
395
396 /* select mck clock, and output */
397 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
398 /* set parity for normal/inverse mode + max iterations */
399 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
400
401 cd = atmel_calc_cd(port, iso7816conf);
402 fidi = atmel_calc_fidi(port, iso7816conf);
403 if (fidi == 0) {
404 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
405 } else if (fidi < atmel_port->fidi_min
406 || fidi > atmel_port->fidi_max) {
407 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
408 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
409 ret = -EINVAL;
410 goto err_out;
411 }
412
413 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
414 /* port not yet in iso7816 mode: store configuration */
415 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
416 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
417 }
418
419 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
420 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
421 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
422
423 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
424 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
425 } else {
426 dev_dbg(port->dev, "Setting UART back to RS232\n");
427 /* back to last RS232 settings */
428 mode = atmel_port->backup_mode;
429 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
430 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
431 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
432 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
433
434 if (atmel_use_pdc_tx(port))
435 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
436 ATMEL_US_TXBUFE;
437 else
438 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
439 }
440
441 port->iso7816 = *iso7816conf;
442
443 atmel_uart_writel(port, ATMEL_US_MR, mode);
444
445err_out:
446 /* Enable interrupts */
447 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
448
449 return ret;
450}
451
452/*
453 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
454 */
455static u_int atmel_tx_empty(struct uart_port *port)
456{
457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
458
459 if (atmel_port->tx_stopped)
460 return TIOCSER_TEMT;
461 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
462 TIOCSER_TEMT :
463 0;
464}
465
466/*
467 * Set state of the modem control output lines
468 */
469static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
470{
471 unsigned int control = 0;
472 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
473 unsigned int rts_paused, rts_ready;
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
475
476 /* override mode to RS485 if needed, otherwise keep the current mode */
477 if (port->rs485.flags & SER_RS485_ENABLED) {
478 atmel_uart_writel(port, ATMEL_US_TTGR,
479 port->rs485.delay_rts_after_send);
480 mode &= ~ATMEL_US_USMODE;
481 mode |= ATMEL_US_USMODE_RS485;
482 }
483
484 /* set the RTS line state according to the mode */
485 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
486 /* force RTS line to high level */
487 rts_paused = ATMEL_US_RTSEN;
488
489 /* give the control of the RTS line back to the hardware */
490 rts_ready = ATMEL_US_RTSDIS;
491 } else {
492 /* force RTS line to high level */
493 rts_paused = ATMEL_US_RTSDIS;
494
495 /* force RTS line to low level */
496 rts_ready = ATMEL_US_RTSEN;
497 }
498
499 if (mctrl & TIOCM_RTS)
500 control |= rts_ready;
501 else
502 control |= rts_paused;
503
504 if (mctrl & TIOCM_DTR)
505 control |= ATMEL_US_DTREN;
506 else
507 control |= ATMEL_US_DTRDIS;
508
509 atmel_uart_writel(port, ATMEL_US_CR, control);
510
511 mctrl_gpio_set(atmel_port->gpios, mctrl);
512
513 /* Local loopback mode? */
514 mode &= ~ATMEL_US_CHMODE;
515 if (mctrl & TIOCM_LOOP)
516 mode |= ATMEL_US_CHMODE_LOC_LOOP;
517 else
518 mode |= ATMEL_US_CHMODE_NORMAL;
519
520 atmel_uart_writel(port, ATMEL_US_MR, mode);
521}
522
523/*
524 * Get state of the modem control input lines
525 */
526static u_int atmel_get_mctrl(struct uart_port *port)
527{
528 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
529 unsigned int ret = 0, status;
530
531 status = atmel_uart_readl(port, ATMEL_US_CSR);
532
533 /*
534 * The control signals are active low.
535 */
536 if (!(status & ATMEL_US_DCD))
537 ret |= TIOCM_CD;
538 if (!(status & ATMEL_US_CTS))
539 ret |= TIOCM_CTS;
540 if (!(status & ATMEL_US_DSR))
541 ret |= TIOCM_DSR;
542 if (!(status & ATMEL_US_RI))
543 ret |= TIOCM_RI;
544
545 return mctrl_gpio_get(atmel_port->gpios, &ret);
546}
547
548/*
549 * Stop transmitting.
550 */
551static void atmel_stop_tx(struct uart_port *port)
552{
553 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
554 bool is_pdc = atmel_use_pdc_tx(port);
555 bool is_dma = is_pdc || atmel_use_dma_tx(port);
556
557 if (is_pdc) {
558 /* disable PDC transmit */
559 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
560 }
561
562 if (is_dma) {
563 /*
564 * Disable the transmitter.
565 * This is mandatory when DMA is used, otherwise the DMA buffer
566 * is fully transmitted.
567 */
568 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
569 atmel_port->tx_stopped = true;
570 }
571
572 /* Disable interrupts */
573 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
574
575 if (atmel_uart_is_half_duplex(port))
576 if (!atomic_read(&atmel_port->tasklet_shutdown))
577 atmel_start_rx(port);
578}
579
580/*
581 * Start transmitting.
582 */
583static void atmel_start_tx(struct uart_port *port)
584{
585 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
586 bool is_pdc = atmel_use_pdc_tx(port);
587 bool is_dma = is_pdc || atmel_use_dma_tx(port);
588
589 if (is_pdc && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
590 & ATMEL_PDC_TXTEN))
591 /* The transmitter is already running. Yes, we
592 really need this.*/
593 return;
594
595 if (is_dma && atmel_uart_is_half_duplex(port))
596 atmel_stop_rx(port);
597
598 if (is_pdc) {
599 /* re-enable PDC transmit */
600 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
601 }
602
603 /* Enable interrupts */
604 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
605
606 if (is_dma) {
607 /* re-enable the transmitter */
608 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
609 atmel_port->tx_stopped = false;
610 }
611}
612
613/*
614 * start receiving - port is in process of being opened.
615 */
616static void atmel_start_rx(struct uart_port *port)
617{
618 /* reset status and receiver */
619 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
620
621 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
622
623 if (atmel_use_pdc_rx(port)) {
624 /* enable PDC controller */
625 atmel_uart_writel(port, ATMEL_US_IER,
626 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
627 port->read_status_mask);
628 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
629 } else {
630 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
631 }
632}
633
634/*
635 * Stop receiving - port is in process of being closed.
636 */
637static void atmel_stop_rx(struct uart_port *port)
638{
639 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
640
641 if (atmel_use_pdc_rx(port)) {
642 /* disable PDC receive */
643 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
644 atmel_uart_writel(port, ATMEL_US_IDR,
645 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
646 port->read_status_mask);
647 } else {
648 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
649 }
650}
651
652/*
653 * Enable modem status interrupts
654 */
655static void atmel_enable_ms(struct uart_port *port)
656{
657 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
658 uint32_t ier = 0;
659
660 /*
661 * Interrupt should not be enabled twice
662 */
663 if (atmel_port->ms_irq_enabled)
664 return;
665
666 atmel_port->ms_irq_enabled = true;
667
668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
669 ier |= ATMEL_US_CTSIC;
670
671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
672 ier |= ATMEL_US_DSRIC;
673
674 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
675 ier |= ATMEL_US_RIIC;
676
677 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
678 ier |= ATMEL_US_DCDIC;
679
680 atmel_uart_writel(port, ATMEL_US_IER, ier);
681
682 mctrl_gpio_enable_ms(atmel_port->gpios);
683}
684
685/*
686 * Disable modem status interrupts
687 */
688static void atmel_disable_ms(struct uart_port *port)
689{
690 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
691 uint32_t idr = 0;
692
693 /*
694 * Interrupt should not be disabled twice
695 */
696 if (!atmel_port->ms_irq_enabled)
697 return;
698
699 atmel_port->ms_irq_enabled = false;
700
701 mctrl_gpio_disable_ms(atmel_port->gpios);
702
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
704 idr |= ATMEL_US_CTSIC;
705
706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
707 idr |= ATMEL_US_DSRIC;
708
709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
710 idr |= ATMEL_US_RIIC;
711
712 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
713 idr |= ATMEL_US_DCDIC;
714
715 atmel_uart_writel(port, ATMEL_US_IDR, idr);
716}
717
718/*
719 * Control the transmission of a break signal
720 */
721static void atmel_break_ctl(struct uart_port *port, int break_state)
722{
723 if (break_state != 0)
724 /* start break */
725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
726 else
727 /* stop break */
728 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
729}
730
731/*
732 * Stores the incoming character in the ring buffer
733 */
734static void
735atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
736 unsigned int ch)
737{
738 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
739 struct circ_buf *ring = &atmel_port->rx_ring;
740 struct atmel_uart_char *c;
741
742 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
743 /* Buffer overflow, ignore char */
744 return;
745
746 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
747 c->status = status;
748 c->ch = ch;
749
750 /* Make sure the character is stored before we update head. */
751 smp_wmb();
752
753 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
754}
755
756/*
757 * Deal with parity, framing and overrun errors.
758 */
759static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
760{
761 /* clear error */
762 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
763
764 if (status & ATMEL_US_RXBRK) {
765 /* ignore side-effect */
766 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
767 port->icount.brk++;
768 }
769 if (status & ATMEL_US_PARE)
770 port->icount.parity++;
771 if (status & ATMEL_US_FRAME)
772 port->icount.frame++;
773 if (status & ATMEL_US_OVRE)
774 port->icount.overrun++;
775}
776
777/*
778 * Characters received (called from interrupt handler)
779 */
780static void atmel_rx_chars(struct uart_port *port)
781{
782 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
783 unsigned int status, ch;
784
785 status = atmel_uart_readl(port, ATMEL_US_CSR);
786 while (status & ATMEL_US_RXRDY) {
787 ch = atmel_uart_read_char(port);
788
789 /*
790 * note that the error handling code is
791 * out of the main execution path
792 */
793 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
794 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
795 || atmel_port->break_active)) {
796
797 /* clear error */
798 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
799
800 if (status & ATMEL_US_RXBRK
801 && !atmel_port->break_active) {
802 atmel_port->break_active = 1;
803 atmel_uart_writel(port, ATMEL_US_IER,
804 ATMEL_US_RXBRK);
805 } else {
806 /*
807 * This is either the end-of-break
808 * condition or we've received at
809 * least one character without RXBRK
810 * being set. In both cases, the next
811 * RXBRK will indicate start-of-break.
812 */
813 atmel_uart_writel(port, ATMEL_US_IDR,
814 ATMEL_US_RXBRK);
815 status &= ~ATMEL_US_RXBRK;
816 atmel_port->break_active = 0;
817 }
818 }
819
820 atmel_buffer_rx_char(port, status, ch);
821 status = atmel_uart_readl(port, ATMEL_US_CSR);
822 }
823
824 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
825}
826
827/*
828 * Transmit characters (called from tasklet with TXRDY interrupt
829 * disabled)
830 */
831static void atmel_tx_chars(struct uart_port *port)
832{
833 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
834 bool pending;
835 u8 ch;
836
837 pending = uart_port_tx(port, ch,
838 atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY,
839 atmel_uart_write_char(port, ch));
840 if (pending) {
841 /* we still have characters to transmit, so we should continue
842 * transmitting them when TX is ready, regardless of
843 * mode or duplexity
844 */
845 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
846
847 /* Enable interrupts */
848 atmel_uart_writel(port, ATMEL_US_IER,
849 atmel_port->tx_done_mask);
850 } else {
851 if (atmel_uart_is_half_duplex(port))
852 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
853 }
854}
855
856static void atmel_complete_tx_dma(void *arg)
857{
858 struct atmel_uart_port *atmel_port = arg;
859 struct uart_port *port = &atmel_port->uart;
860 struct circ_buf *xmit = &port->state->xmit;
861 struct dma_chan *chan = atmel_port->chan_tx;
862 unsigned long flags;
863
864 uart_port_lock_irqsave(port, &flags);
865
866 if (chan)
867 dmaengine_terminate_all(chan);
868 uart_xmit_advance(port, atmel_port->tx_len);
869
870 spin_lock(&atmel_port->lock_tx);
871 async_tx_ack(atmel_port->desc_tx);
872 atmel_port->cookie_tx = -EINVAL;
873 atmel_port->desc_tx = NULL;
874 spin_unlock(&atmel_port->lock_tx);
875
876 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
877 uart_write_wakeup(port);
878
879 /*
880 * xmit is a circular buffer so, if we have just send data from
881 * xmit->tail to the end of xmit->buf, now we have to transmit the
882 * remaining data from the beginning of xmit->buf to xmit->head.
883 */
884 if (!uart_circ_empty(xmit))
885 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
886 else if (atmel_uart_is_half_duplex(port)) {
887 /*
888 * DMA done, re-enable TXEMPTY and signal that we can stop
889 * TX and start RX for RS485
890 */
891 atmel_port->hd_start_rx = true;
892 atmel_uart_writel(port, ATMEL_US_IER,
893 atmel_port->tx_done_mask);
894 }
895
896 uart_port_unlock_irqrestore(port, flags);
897}
898
899static void atmel_release_tx_dma(struct uart_port *port)
900{
901 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
902 struct dma_chan *chan = atmel_port->chan_tx;
903
904 if (chan) {
905 dmaengine_terminate_all(chan);
906 dma_release_channel(chan);
907 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
908 DMA_TO_DEVICE);
909 }
910
911 atmel_port->desc_tx = NULL;
912 atmel_port->chan_tx = NULL;
913 atmel_port->cookie_tx = -EINVAL;
914}
915
916/*
917 * Called from tasklet with TXRDY interrupt is disabled.
918 */
919static void atmel_tx_dma(struct uart_port *port)
920{
921 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
922 struct circ_buf *xmit = &port->state->xmit;
923 struct dma_chan *chan = atmel_port->chan_tx;
924 struct dma_async_tx_descriptor *desc;
925 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
926 unsigned int tx_len, part1_len, part2_len, sg_len;
927 dma_addr_t phys_addr;
928
929 /* Make sure we have an idle channel */
930 if (atmel_port->desc_tx != NULL)
931 return;
932
933 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
934 /*
935 * DMA is idle now.
936 * Port xmit buffer is already mapped,
937 * and it is one page... Just adjust
938 * offsets and lengths. Since it is a circular buffer,
939 * we have to transmit till the end, and then the rest.
940 * Take the port lock to get a
941 * consistent xmit buffer state.
942 */
943 tx_len = CIRC_CNT_TO_END(xmit->head,
944 xmit->tail,
945 UART_XMIT_SIZE);
946
947 if (atmel_port->fifo_size) {
948 /* multi data mode */
949 part1_len = (tx_len & ~0x3); /* DWORD access */
950 part2_len = (tx_len & 0x3); /* BYTE access */
951 } else {
952 /* single data (legacy) mode */
953 part1_len = 0;
954 part2_len = tx_len; /* BYTE access only */
955 }
956
957 sg_init_table(sgl, 2);
958 sg_len = 0;
959 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
960 if (part1_len) {
961 sg = &sgl[sg_len++];
962 sg_dma_address(sg) = phys_addr;
963 sg_dma_len(sg) = part1_len;
964
965 phys_addr += part1_len;
966 }
967
968 if (part2_len) {
969 sg = &sgl[sg_len++];
970 sg_dma_address(sg) = phys_addr;
971 sg_dma_len(sg) = part2_len;
972 }
973
974 /*
975 * save tx_len so atmel_complete_tx_dma() will increase
976 * xmit->tail correctly
977 */
978 atmel_port->tx_len = tx_len;
979
980 desc = dmaengine_prep_slave_sg(chan,
981 sgl,
982 sg_len,
983 DMA_MEM_TO_DEV,
984 DMA_PREP_INTERRUPT |
985 DMA_CTRL_ACK);
986 if (!desc) {
987 dev_err(port->dev, "Failed to send via dma!\n");
988 return;
989 }
990
991 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
992
993 atmel_port->desc_tx = desc;
994 desc->callback = atmel_complete_tx_dma;
995 desc->callback_param = atmel_port;
996 atmel_port->cookie_tx = dmaengine_submit(desc);
997 if (dma_submit_error(atmel_port->cookie_tx)) {
998 dev_err(port->dev, "dma_submit_error %d\n",
999 atmel_port->cookie_tx);
1000 return;
1001 }
1002
1003 dma_async_issue_pending(chan);
1004 }
1005
1006 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1007 uart_write_wakeup(port);
1008}
1009
1010static int atmel_prepare_tx_dma(struct uart_port *port)
1011{
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1013 struct device *mfd_dev = port->dev->parent;
1014 dma_cap_mask_t mask;
1015 struct dma_slave_config config;
1016 struct dma_chan *chan;
1017 int ret, nent;
1018
1019 dma_cap_zero(mask);
1020 dma_cap_set(DMA_SLAVE, mask);
1021
1022 chan = dma_request_chan(mfd_dev, "tx");
1023 if (IS_ERR(chan)) {
1024 atmel_port->chan_tx = NULL;
1025 goto chan_err;
1026 }
1027 atmel_port->chan_tx = chan;
1028 dev_info(port->dev, "using %s for tx DMA transfers\n",
1029 dma_chan_name(atmel_port->chan_tx));
1030
1031 spin_lock_init(&atmel_port->lock_tx);
1032 sg_init_table(&atmel_port->sg_tx, 1);
1033 /* UART circular tx buffer is an aligned page. */
1034 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1035 sg_set_page(&atmel_port->sg_tx,
1036 virt_to_page(port->state->xmit.buf),
1037 UART_XMIT_SIZE,
1038 offset_in_page(port->state->xmit.buf));
1039 nent = dma_map_sg(port->dev,
1040 &atmel_port->sg_tx,
1041 1,
1042 DMA_TO_DEVICE);
1043
1044 if (!nent) {
1045 dev_dbg(port->dev, "need to release resource of dma\n");
1046 goto chan_err;
1047 } else {
1048 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1049 sg_dma_len(&atmel_port->sg_tx),
1050 port->state->xmit.buf,
1051 &sg_dma_address(&atmel_port->sg_tx));
1052 }
1053
1054 /* Configure the slave DMA */
1055 memset(&config, 0, sizeof(config));
1056 config.direction = DMA_MEM_TO_DEV;
1057 config.dst_addr_width = (atmel_port->fifo_size) ?
1058 DMA_SLAVE_BUSWIDTH_4_BYTES :
1059 DMA_SLAVE_BUSWIDTH_1_BYTE;
1060 config.dst_addr = port->mapbase + ATMEL_US_THR;
1061 config.dst_maxburst = 1;
1062
1063 ret = dmaengine_slave_config(atmel_port->chan_tx,
1064 &config);
1065 if (ret) {
1066 dev_err(port->dev, "DMA tx slave configuration failed\n");
1067 goto chan_err;
1068 }
1069
1070 return 0;
1071
1072chan_err:
1073 dev_err(port->dev, "TX channel not available, switch to pio\n");
1074 atmel_port->use_dma_tx = false;
1075 if (atmel_port->chan_tx)
1076 atmel_release_tx_dma(port);
1077 return -EINVAL;
1078}
1079
1080static void atmel_complete_rx_dma(void *arg)
1081{
1082 struct uart_port *port = arg;
1083 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1084
1085 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1086}
1087
1088static void atmel_release_rx_dma(struct uart_port *port)
1089{
1090 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1091 struct dma_chan *chan = atmel_port->chan_rx;
1092
1093 if (chan) {
1094 dmaengine_terminate_all(chan);
1095 dma_release_channel(chan);
1096 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1097 DMA_FROM_DEVICE);
1098 }
1099
1100 atmel_port->desc_rx = NULL;
1101 atmel_port->chan_rx = NULL;
1102 atmel_port->cookie_rx = -EINVAL;
1103}
1104
1105static void atmel_rx_from_dma(struct uart_port *port)
1106{
1107 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1108 struct tty_port *tport = &port->state->port;
1109 struct circ_buf *ring = &atmel_port->rx_ring;
1110 struct dma_chan *chan = atmel_port->chan_rx;
1111 struct dma_tx_state state;
1112 enum dma_status dmastat;
1113 size_t count;
1114
1115
1116 /* Reset the UART timeout early so that we don't miss one */
1117 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1118 dmastat = dmaengine_tx_status(chan,
1119 atmel_port->cookie_rx,
1120 &state);
1121 /* Restart a new tasklet if DMA status is error */
1122 if (dmastat == DMA_ERROR) {
1123 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1124 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1125 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1126 return;
1127 }
1128
1129 /* CPU claims ownership of RX DMA buffer */
1130 dma_sync_sg_for_cpu(port->dev,
1131 &atmel_port->sg_rx,
1132 1,
1133 DMA_FROM_DEVICE);
1134
1135 /*
1136 * ring->head points to the end of data already written by the DMA.
1137 * ring->tail points to the beginning of data to be read by the
1138 * framework.
1139 * The current transfer size should not be larger than the dma buffer
1140 * length.
1141 */
1142 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1143 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1144 /*
1145 * At this point ring->head may point to the first byte right after the
1146 * last byte of the dma buffer:
1147 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1148 *
1149 * However ring->tail must always points inside the dma buffer:
1150 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1151 *
1152 * Since we use a ring buffer, we have to handle the case
1153 * where head is lower than tail. In such a case, we first read from
1154 * tail to the end of the buffer then reset tail.
1155 */
1156 if (ring->head < ring->tail) {
1157 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1158
1159 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1160 ring->tail = 0;
1161 port->icount.rx += count;
1162 }
1163
1164 /* Finally we read data from tail to head */
1165 if (ring->tail < ring->head) {
1166 count = ring->head - ring->tail;
1167
1168 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1169 /* Wrap ring->head if needed */
1170 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1171 ring->head = 0;
1172 ring->tail = ring->head;
1173 port->icount.rx += count;
1174 }
1175
1176 /* USART retreives ownership of RX DMA buffer */
1177 dma_sync_sg_for_device(port->dev,
1178 &atmel_port->sg_rx,
1179 1,
1180 DMA_FROM_DEVICE);
1181
1182 tty_flip_buffer_push(tport);
1183
1184 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1185}
1186
1187static int atmel_prepare_rx_dma(struct uart_port *port)
1188{
1189 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1190 struct device *mfd_dev = port->dev->parent;
1191 struct dma_async_tx_descriptor *desc;
1192 dma_cap_mask_t mask;
1193 struct dma_slave_config config;
1194 struct circ_buf *ring;
1195 struct dma_chan *chan;
1196 int ret, nent;
1197
1198 ring = &atmel_port->rx_ring;
1199
1200 dma_cap_zero(mask);
1201 dma_cap_set(DMA_CYCLIC, mask);
1202
1203 chan = dma_request_chan(mfd_dev, "rx");
1204 if (IS_ERR(chan)) {
1205 atmel_port->chan_rx = NULL;
1206 goto chan_err;
1207 }
1208 atmel_port->chan_rx = chan;
1209 dev_info(port->dev, "using %s for rx DMA transfers\n",
1210 dma_chan_name(atmel_port->chan_rx));
1211
1212 spin_lock_init(&atmel_port->lock_rx);
1213 sg_init_table(&atmel_port->sg_rx, 1);
1214 /* UART circular rx buffer is an aligned page. */
1215 BUG_ON(!PAGE_ALIGNED(ring->buf));
1216 sg_set_page(&atmel_port->sg_rx,
1217 virt_to_page(ring->buf),
1218 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1219 offset_in_page(ring->buf));
1220 nent = dma_map_sg(port->dev,
1221 &atmel_port->sg_rx,
1222 1,
1223 DMA_FROM_DEVICE);
1224
1225 if (!nent) {
1226 dev_dbg(port->dev, "need to release resource of dma\n");
1227 goto chan_err;
1228 } else {
1229 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1230 sg_dma_len(&atmel_port->sg_rx),
1231 ring->buf,
1232 &sg_dma_address(&atmel_port->sg_rx));
1233 }
1234
1235 /* Configure the slave DMA */
1236 memset(&config, 0, sizeof(config));
1237 config.direction = DMA_DEV_TO_MEM;
1238 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1239 config.src_addr = port->mapbase + ATMEL_US_RHR;
1240 config.src_maxburst = 1;
1241
1242 ret = dmaengine_slave_config(atmel_port->chan_rx,
1243 &config);
1244 if (ret) {
1245 dev_err(port->dev, "DMA rx slave configuration failed\n");
1246 goto chan_err;
1247 }
1248 /*
1249 * Prepare a cyclic dma transfer, assign 2 descriptors,
1250 * each one is half ring buffer size
1251 */
1252 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1253 sg_dma_address(&atmel_port->sg_rx),
1254 sg_dma_len(&atmel_port->sg_rx),
1255 sg_dma_len(&atmel_port->sg_rx)/2,
1256 DMA_DEV_TO_MEM,
1257 DMA_PREP_INTERRUPT);
1258 if (!desc) {
1259 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1260 goto chan_err;
1261 }
1262 desc->callback = atmel_complete_rx_dma;
1263 desc->callback_param = port;
1264 atmel_port->desc_rx = desc;
1265 atmel_port->cookie_rx = dmaengine_submit(desc);
1266 if (dma_submit_error(atmel_port->cookie_rx)) {
1267 dev_err(port->dev, "dma_submit_error %d\n",
1268 atmel_port->cookie_rx);
1269 goto chan_err;
1270 }
1271
1272 dma_async_issue_pending(atmel_port->chan_rx);
1273
1274 return 0;
1275
1276chan_err:
1277 dev_err(port->dev, "RX channel not available, switch to pio\n");
1278 atmel_port->use_dma_rx = false;
1279 if (atmel_port->chan_rx)
1280 atmel_release_rx_dma(port);
1281 return -EINVAL;
1282}
1283
1284static void atmel_uart_timer_callback(struct timer_list *t)
1285{
1286 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1287 uart_timer);
1288 struct uart_port *port = &atmel_port->uart;
1289
1290 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1291 tasklet_schedule(&atmel_port->tasklet_rx);
1292 mod_timer(&atmel_port->uart_timer,
1293 jiffies + uart_poll_timeout(port));
1294 }
1295}
1296
1297/*
1298 * receive interrupt handler.
1299 */
1300static void
1301atmel_handle_receive(struct uart_port *port, unsigned int pending)
1302{
1303 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1304
1305 if (atmel_use_pdc_rx(port)) {
1306 /*
1307 * PDC receive. Just schedule the tasklet and let it
1308 * figure out the details.
1309 *
1310 * TODO: We're not handling error flags correctly at
1311 * the moment.
1312 */
1313 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1314 atmel_uart_writel(port, ATMEL_US_IDR,
1315 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1316 atmel_tasklet_schedule(atmel_port,
1317 &atmel_port->tasklet_rx);
1318 }
1319
1320 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1321 ATMEL_US_FRAME | ATMEL_US_PARE))
1322 atmel_pdc_rxerr(port, pending);
1323 }
1324
1325 if (atmel_use_dma_rx(port)) {
1326 if (pending & ATMEL_US_TIMEOUT) {
1327 atmel_uart_writel(port, ATMEL_US_IDR,
1328 ATMEL_US_TIMEOUT);
1329 atmel_tasklet_schedule(atmel_port,
1330 &atmel_port->tasklet_rx);
1331 }
1332 }
1333
1334 /* Interrupt receive */
1335 if (pending & ATMEL_US_RXRDY)
1336 atmel_rx_chars(port);
1337 else if (pending & ATMEL_US_RXBRK) {
1338 /*
1339 * End of break detected. If it came along with a
1340 * character, atmel_rx_chars will handle it.
1341 */
1342 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1343 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1344 atmel_port->break_active = 0;
1345 }
1346}
1347
1348/*
1349 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1350 */
1351static void
1352atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1353{
1354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1355
1356 if (pending & atmel_port->tx_done_mask) {
1357 atmel_uart_writel(port, ATMEL_US_IDR,
1358 atmel_port->tx_done_mask);
1359
1360 /* Start RX if flag was set and FIFO is empty */
1361 if (atmel_port->hd_start_rx) {
1362 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1363 & ATMEL_US_TXEMPTY))
1364 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1365
1366 atmel_port->hd_start_rx = false;
1367 atmel_start_rx(port);
1368 }
1369
1370 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1371 }
1372}
1373
1374/*
1375 * status flags interrupt handler.
1376 */
1377static void
1378atmel_handle_status(struct uart_port *port, unsigned int pending,
1379 unsigned int status)
1380{
1381 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1382 unsigned int status_change;
1383
1384 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1385 | ATMEL_US_CTSIC)) {
1386 status_change = status ^ atmel_port->irq_status_prev;
1387 atmel_port->irq_status_prev = status;
1388
1389 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1390 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1391 /* TODO: All reads to CSR will clear these interrupts! */
1392 if (status_change & ATMEL_US_RI)
1393 port->icount.rng++;
1394 if (status_change & ATMEL_US_DSR)
1395 port->icount.dsr++;
1396 if (status_change & ATMEL_US_DCD)
1397 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1398 if (status_change & ATMEL_US_CTS)
1399 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1400
1401 wake_up_interruptible(&port->state->port.delta_msr_wait);
1402 }
1403 }
1404
1405 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1406 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1407}
1408
1409/*
1410 * Interrupt handler
1411 */
1412static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1413{
1414 struct uart_port *port = dev_id;
1415 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1416 unsigned int status, pending, mask, pass_counter = 0;
1417
1418 spin_lock(&atmel_port->lock_suspended);
1419
1420 do {
1421 status = atmel_uart_readl(port, ATMEL_US_CSR);
1422 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1423 pending = status & mask;
1424 if (!pending)
1425 break;
1426
1427 if (atmel_port->suspended) {
1428 atmel_port->pending |= pending;
1429 atmel_port->pending_status = status;
1430 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1431 pm_system_wakeup();
1432 break;
1433 }
1434
1435 atmel_handle_receive(port, pending);
1436 atmel_handle_status(port, pending, status);
1437 atmel_handle_transmit(port, pending);
1438 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1439
1440 spin_unlock(&atmel_port->lock_suspended);
1441
1442 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1443}
1444
1445static void atmel_release_tx_pdc(struct uart_port *port)
1446{
1447 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1448 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1449
1450 dma_unmap_single(port->dev,
1451 pdc->dma_addr,
1452 pdc->dma_size,
1453 DMA_TO_DEVICE);
1454}
1455
1456/*
1457 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1458 */
1459static void atmel_tx_pdc(struct uart_port *port)
1460{
1461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1462 struct circ_buf *xmit = &port->state->xmit;
1463 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1464 int count;
1465
1466 /* nothing left to transmit? */
1467 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1468 return;
1469 uart_xmit_advance(port, pdc->ofs);
1470 pdc->ofs = 0;
1471
1472 /* more to transmit - setup next transfer */
1473
1474 /* disable PDC transmit */
1475 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1476
1477 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1478 dma_sync_single_for_device(port->dev,
1479 pdc->dma_addr,
1480 pdc->dma_size,
1481 DMA_TO_DEVICE);
1482
1483 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1484 pdc->ofs = count;
1485
1486 atmel_uart_writel(port, ATMEL_PDC_TPR,
1487 pdc->dma_addr + xmit->tail);
1488 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1489 /* re-enable PDC transmit */
1490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1491 /* Enable interrupts */
1492 atmel_uart_writel(port, ATMEL_US_IER,
1493 atmel_port->tx_done_mask);
1494 } else {
1495 if (atmel_uart_is_half_duplex(port)) {
1496 /* DMA done, stop TX, start RX for RS485 */
1497 atmel_start_rx(port);
1498 }
1499 }
1500
1501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1502 uart_write_wakeup(port);
1503}
1504
1505static int atmel_prepare_tx_pdc(struct uart_port *port)
1506{
1507 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1508 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1509 struct circ_buf *xmit = &port->state->xmit;
1510
1511 pdc->buf = xmit->buf;
1512 pdc->dma_addr = dma_map_single(port->dev,
1513 pdc->buf,
1514 UART_XMIT_SIZE,
1515 DMA_TO_DEVICE);
1516 pdc->dma_size = UART_XMIT_SIZE;
1517 pdc->ofs = 0;
1518
1519 return 0;
1520}
1521
1522static void atmel_rx_from_ring(struct uart_port *port)
1523{
1524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1525 struct circ_buf *ring = &atmel_port->rx_ring;
1526 unsigned int status;
1527 u8 flg;
1528
1529 while (ring->head != ring->tail) {
1530 struct atmel_uart_char c;
1531
1532 /* Make sure c is loaded after head. */
1533 smp_rmb();
1534
1535 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1536
1537 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1538
1539 port->icount.rx++;
1540 status = c.status;
1541 flg = TTY_NORMAL;
1542
1543 /*
1544 * note that the error handling code is
1545 * out of the main execution path
1546 */
1547 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1548 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1549 if (status & ATMEL_US_RXBRK) {
1550 /* ignore side-effect */
1551 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1552
1553 port->icount.brk++;
1554 if (uart_handle_break(port))
1555 continue;
1556 }
1557 if (status & ATMEL_US_PARE)
1558 port->icount.parity++;
1559 if (status & ATMEL_US_FRAME)
1560 port->icount.frame++;
1561 if (status & ATMEL_US_OVRE)
1562 port->icount.overrun++;
1563
1564 status &= port->read_status_mask;
1565
1566 if (status & ATMEL_US_RXBRK)
1567 flg = TTY_BREAK;
1568 else if (status & ATMEL_US_PARE)
1569 flg = TTY_PARITY;
1570 else if (status & ATMEL_US_FRAME)
1571 flg = TTY_FRAME;
1572 }
1573
1574
1575 if (uart_handle_sysrq_char(port, c.ch))
1576 continue;
1577
1578 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1579 }
1580
1581 tty_flip_buffer_push(&port->state->port);
1582}
1583
1584static void atmel_release_rx_pdc(struct uart_port *port)
1585{
1586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1587 int i;
1588
1589 for (i = 0; i < 2; i++) {
1590 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1591
1592 dma_unmap_single(port->dev,
1593 pdc->dma_addr,
1594 pdc->dma_size,
1595 DMA_FROM_DEVICE);
1596 kfree(pdc->buf);
1597 }
1598}
1599
1600static void atmel_rx_from_pdc(struct uart_port *port)
1601{
1602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1603 struct tty_port *tport = &port->state->port;
1604 struct atmel_dma_buffer *pdc;
1605 int rx_idx = atmel_port->pdc_rx_idx;
1606 unsigned int head;
1607 unsigned int tail;
1608 unsigned int count;
1609
1610 do {
1611 /* Reset the UART timeout early so that we don't miss one */
1612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1613
1614 pdc = &atmel_port->pdc_rx[rx_idx];
1615 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1616 tail = pdc->ofs;
1617
1618 /* If the PDC has switched buffers, RPR won't contain
1619 * any address within the current buffer. Since head
1620 * is unsigned, we just need a one-way comparison to
1621 * find out.
1622 *
1623 * In this case, we just need to consume the entire
1624 * buffer and resubmit it for DMA. This will clear the
1625 * ENDRX bit as well, so that we can safely re-enable
1626 * all interrupts below.
1627 */
1628 head = min(head, pdc->dma_size);
1629
1630 if (likely(head != tail)) {
1631 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1632 pdc->dma_size, DMA_FROM_DEVICE);
1633
1634 /*
1635 * head will only wrap around when we recycle
1636 * the DMA buffer, and when that happens, we
1637 * explicitly set tail to 0. So head will
1638 * always be greater than tail.
1639 */
1640 count = head - tail;
1641
1642 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1643 count);
1644
1645 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1646 pdc->dma_size, DMA_FROM_DEVICE);
1647
1648 port->icount.rx += count;
1649 pdc->ofs = head;
1650 }
1651
1652 /*
1653 * If the current buffer is full, we need to check if
1654 * the next one contains any additional data.
1655 */
1656 if (head >= pdc->dma_size) {
1657 pdc->ofs = 0;
1658 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1659 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1660
1661 rx_idx = !rx_idx;
1662 atmel_port->pdc_rx_idx = rx_idx;
1663 }
1664 } while (head >= pdc->dma_size);
1665
1666 tty_flip_buffer_push(tport);
1667
1668 atmel_uart_writel(port, ATMEL_US_IER,
1669 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1670}
1671
1672static int atmel_prepare_rx_pdc(struct uart_port *port)
1673{
1674 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1675 int i;
1676
1677 for (i = 0; i < 2; i++) {
1678 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1679
1680 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1681 if (pdc->buf == NULL) {
1682 if (i != 0) {
1683 dma_unmap_single(port->dev,
1684 atmel_port->pdc_rx[0].dma_addr,
1685 PDC_BUFFER_SIZE,
1686 DMA_FROM_DEVICE);
1687 kfree(atmel_port->pdc_rx[0].buf);
1688 }
1689 atmel_port->use_pdc_rx = false;
1690 return -ENOMEM;
1691 }
1692 pdc->dma_addr = dma_map_single(port->dev,
1693 pdc->buf,
1694 PDC_BUFFER_SIZE,
1695 DMA_FROM_DEVICE);
1696 pdc->dma_size = PDC_BUFFER_SIZE;
1697 pdc->ofs = 0;
1698 }
1699
1700 atmel_port->pdc_rx_idx = 0;
1701
1702 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1703 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1704
1705 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1706 atmel_port->pdc_rx[1].dma_addr);
1707 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1708
1709 return 0;
1710}
1711
1712/*
1713 * tasklet handling tty stuff outside the interrupt handler.
1714 */
1715static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1716{
1717 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1718 tasklet_rx);
1719 struct uart_port *port = &atmel_port->uart;
1720
1721 /* The interrupt handler does not take the lock */
1722 uart_port_lock(port);
1723 atmel_port->schedule_rx(port);
1724 uart_port_unlock(port);
1725}
1726
1727static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1728{
1729 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1730 tasklet_tx);
1731 struct uart_port *port = &atmel_port->uart;
1732
1733 /* The interrupt handler does not take the lock */
1734 uart_port_lock(port);
1735 atmel_port->schedule_tx(port);
1736 uart_port_unlock(port);
1737}
1738
1739static void atmel_init_property(struct atmel_uart_port *atmel_port,
1740 struct platform_device *pdev)
1741{
1742 struct device_node *np = pdev->dev.of_node;
1743
1744 /* DMA/PDC usage specification */
1745 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1746 if (of_property_read_bool(np, "dmas")) {
1747 atmel_port->use_dma_rx = true;
1748 atmel_port->use_pdc_rx = false;
1749 } else {
1750 atmel_port->use_dma_rx = false;
1751 atmel_port->use_pdc_rx = true;
1752 }
1753 } else {
1754 atmel_port->use_dma_rx = false;
1755 atmel_port->use_pdc_rx = false;
1756 }
1757
1758 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1759 if (of_property_read_bool(np, "dmas")) {
1760 atmel_port->use_dma_tx = true;
1761 atmel_port->use_pdc_tx = false;
1762 } else {
1763 atmel_port->use_dma_tx = false;
1764 atmel_port->use_pdc_tx = true;
1765 }
1766 } else {
1767 atmel_port->use_dma_tx = false;
1768 atmel_port->use_pdc_tx = false;
1769 }
1770}
1771
1772static void atmel_set_ops(struct uart_port *port)
1773{
1774 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1775
1776 if (atmel_use_dma_rx(port)) {
1777 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1778 atmel_port->schedule_rx = &atmel_rx_from_dma;
1779 atmel_port->release_rx = &atmel_release_rx_dma;
1780 } else if (atmel_use_pdc_rx(port)) {
1781 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1782 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1783 atmel_port->release_rx = &atmel_release_rx_pdc;
1784 } else {
1785 atmel_port->prepare_rx = NULL;
1786 atmel_port->schedule_rx = &atmel_rx_from_ring;
1787 atmel_port->release_rx = NULL;
1788 }
1789
1790 if (atmel_use_dma_tx(port)) {
1791 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1792 atmel_port->schedule_tx = &atmel_tx_dma;
1793 atmel_port->release_tx = &atmel_release_tx_dma;
1794 } else if (atmel_use_pdc_tx(port)) {
1795 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1796 atmel_port->schedule_tx = &atmel_tx_pdc;
1797 atmel_port->release_tx = &atmel_release_tx_pdc;
1798 } else {
1799 atmel_port->prepare_tx = NULL;
1800 atmel_port->schedule_tx = &atmel_tx_chars;
1801 atmel_port->release_tx = NULL;
1802 }
1803}
1804
1805/*
1806 * Get ip name usart or uart
1807 */
1808static void atmel_get_ip_name(struct uart_port *port)
1809{
1810 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1811 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1812 u32 version;
1813 u32 usart, dbgu_uart, new_uart;
1814 /* ASCII decoding for IP version */
1815 usart = 0x55534152; /* USAR(T) */
1816 dbgu_uart = 0x44424755; /* DBGU */
1817 new_uart = 0x55415254; /* UART */
1818
1819 /*
1820 * Only USART devices from at91sam9260 SOC implement fractional
1821 * baudrate. It is available for all asynchronous modes, with the
1822 * following restriction: the sampling clock's duty cycle is not
1823 * constant.
1824 */
1825 atmel_port->has_frac_baudrate = false;
1826 atmel_port->has_hw_timer = false;
1827 atmel_port->is_usart = false;
1828
1829 if (name == new_uart) {
1830 dev_dbg(port->dev, "Uart with hw timer");
1831 atmel_port->has_hw_timer = true;
1832 atmel_port->rtor = ATMEL_UA_RTOR;
1833 } else if (name == usart) {
1834 dev_dbg(port->dev, "Usart\n");
1835 atmel_port->has_frac_baudrate = true;
1836 atmel_port->has_hw_timer = true;
1837 atmel_port->is_usart = true;
1838 atmel_port->rtor = ATMEL_US_RTOR;
1839 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1840 switch (version) {
1841 case 0x814: /* sama5d2 */
1842 fallthrough;
1843 case 0x701: /* sama5d4 */
1844 atmel_port->fidi_min = 3;
1845 atmel_port->fidi_max = 65535;
1846 break;
1847 case 0x502: /* sam9x5, sama5d3 */
1848 atmel_port->fidi_min = 3;
1849 atmel_port->fidi_max = 2047;
1850 break;
1851 default:
1852 atmel_port->fidi_min = 1;
1853 atmel_port->fidi_max = 2047;
1854 }
1855 } else if (name == dbgu_uart) {
1856 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1857 } else {
1858 /* fallback for older SoCs: use version field */
1859 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1860 switch (version) {
1861 case 0x302:
1862 case 0x10213:
1863 case 0x10302:
1864 dev_dbg(port->dev, "This version is usart\n");
1865 atmel_port->has_frac_baudrate = true;
1866 atmel_port->has_hw_timer = true;
1867 atmel_port->is_usart = true;
1868 atmel_port->rtor = ATMEL_US_RTOR;
1869 break;
1870 case 0x203:
1871 case 0x10202:
1872 dev_dbg(port->dev, "This version is uart\n");
1873 break;
1874 default:
1875 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1876 }
1877 }
1878}
1879
1880/*
1881 * Perform initialization and enable port for reception
1882 */
1883static int atmel_startup(struct uart_port *port)
1884{
1885 struct platform_device *pdev = to_platform_device(port->dev);
1886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1887 int retval;
1888
1889 /*
1890 * Ensure that no interrupts are enabled otherwise when
1891 * request_irq() is called we could get stuck trying to
1892 * handle an unexpected interrupt
1893 */
1894 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1895 atmel_port->ms_irq_enabled = false;
1896
1897 /*
1898 * Allocate the IRQ
1899 */
1900 retval = request_irq(port->irq, atmel_interrupt,
1901 IRQF_SHARED | IRQF_COND_SUSPEND,
1902 dev_name(&pdev->dev), port);
1903 if (retval) {
1904 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1905 return retval;
1906 }
1907
1908 atomic_set(&atmel_port->tasklet_shutdown, 0);
1909 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1910 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1911
1912 /*
1913 * Initialize DMA (if necessary)
1914 */
1915 atmel_init_property(atmel_port, pdev);
1916 atmel_set_ops(port);
1917
1918 if (atmel_port->prepare_rx) {
1919 retval = atmel_port->prepare_rx(port);
1920 if (retval < 0)
1921 atmel_set_ops(port);
1922 }
1923
1924 if (atmel_port->prepare_tx) {
1925 retval = atmel_port->prepare_tx(port);
1926 if (retval < 0)
1927 atmel_set_ops(port);
1928 }
1929
1930 /*
1931 * Enable FIFO when available
1932 */
1933 if (atmel_port->fifo_size) {
1934 unsigned int txrdym = ATMEL_US_ONE_DATA;
1935 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1936 unsigned int fmr;
1937
1938 atmel_uart_writel(port, ATMEL_US_CR,
1939 ATMEL_US_FIFOEN |
1940 ATMEL_US_RXFCLR |
1941 ATMEL_US_TXFLCLR);
1942
1943 if (atmel_use_dma_tx(port))
1944 txrdym = ATMEL_US_FOUR_DATA;
1945
1946 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1947 if (atmel_port->rts_high &&
1948 atmel_port->rts_low)
1949 fmr |= ATMEL_US_FRTSC |
1950 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1951 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1952
1953 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1954 }
1955
1956 /* Save current CSR for comparison in atmel_tasklet_func() */
1957 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1958
1959 /*
1960 * Finally, enable the serial port
1961 */
1962 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1963 /* enable xmit & rcvr */
1964 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1965 atmel_port->tx_stopped = false;
1966
1967 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1968
1969 if (atmel_use_pdc_rx(port)) {
1970 /* set UART timeout */
1971 if (!atmel_port->has_hw_timer) {
1972 mod_timer(&atmel_port->uart_timer,
1973 jiffies + uart_poll_timeout(port));
1974 /* set USART timeout */
1975 } else {
1976 atmel_uart_writel(port, atmel_port->rtor,
1977 PDC_RX_TIMEOUT);
1978 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1979
1980 atmel_uart_writel(port, ATMEL_US_IER,
1981 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1982 }
1983 /* enable PDC controller */
1984 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1985 } else if (atmel_use_dma_rx(port)) {
1986 /* set UART timeout */
1987 if (!atmel_port->has_hw_timer) {
1988 mod_timer(&atmel_port->uart_timer,
1989 jiffies + uart_poll_timeout(port));
1990 /* set USART timeout */
1991 } else {
1992 atmel_uart_writel(port, atmel_port->rtor,
1993 PDC_RX_TIMEOUT);
1994 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1995
1996 atmel_uart_writel(port, ATMEL_US_IER,
1997 ATMEL_US_TIMEOUT);
1998 }
1999 } else {
2000 /* enable receive only */
2001 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2002 }
2003
2004 return 0;
2005}
2006
2007/*
2008 * Flush any TX data submitted for DMA. Called when the TX circular
2009 * buffer is reset.
2010 */
2011static void atmel_flush_buffer(struct uart_port *port)
2012{
2013 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2014
2015 if (atmel_use_pdc_tx(port)) {
2016 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2017 atmel_port->pdc_tx.ofs = 0;
2018 }
2019 /*
2020 * in uart_flush_buffer(), the xmit circular buffer has just
2021 * been cleared, so we have to reset tx_len accordingly.
2022 */
2023 atmel_port->tx_len = 0;
2024}
2025
2026/*
2027 * Disable the port
2028 */
2029static void atmel_shutdown(struct uart_port *port)
2030{
2031 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2032
2033 /* Disable modem control lines interrupts */
2034 atmel_disable_ms(port);
2035
2036 /* Disable interrupts at device level */
2037 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2038
2039 /* Prevent spurious interrupts from scheduling the tasklet */
2040 atomic_inc(&atmel_port->tasklet_shutdown);
2041
2042 /*
2043 * Prevent any tasklets being scheduled during
2044 * cleanup
2045 */
2046 del_timer_sync(&atmel_port->uart_timer);
2047
2048 /* Make sure that no interrupt is on the fly */
2049 synchronize_irq(port->irq);
2050
2051 /*
2052 * Clear out any scheduled tasklets before
2053 * we destroy the buffers
2054 */
2055 tasklet_kill(&atmel_port->tasklet_rx);
2056 tasklet_kill(&atmel_port->tasklet_tx);
2057
2058 /*
2059 * Ensure everything is stopped and
2060 * disable port and break condition.
2061 */
2062 atmel_stop_rx(port);
2063 atmel_stop_tx(port);
2064
2065 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2066
2067 /*
2068 * Shut-down the DMA.
2069 */
2070 if (atmel_port->release_rx)
2071 atmel_port->release_rx(port);
2072 if (atmel_port->release_tx)
2073 atmel_port->release_tx(port);
2074
2075 /*
2076 * Reset ring buffer pointers
2077 */
2078 atmel_port->rx_ring.head = 0;
2079 atmel_port->rx_ring.tail = 0;
2080
2081 /*
2082 * Free the interrupts
2083 */
2084 free_irq(port->irq, port);
2085
2086 atmel_flush_buffer(port);
2087}
2088
2089/*
2090 * Power / Clock management.
2091 */
2092static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2093 unsigned int oldstate)
2094{
2095 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2096
2097 switch (state) {
2098 case UART_PM_STATE_ON:
2099 /*
2100 * Enable the peripheral clock for this serial port.
2101 * This is called on uart_open() or a resume event.
2102 */
2103 clk_prepare_enable(atmel_port->clk);
2104
2105 /* re-enable interrupts if we disabled some on suspend */
2106 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2107 break;
2108 case UART_PM_STATE_OFF:
2109 /* Back up the interrupt mask and disable all interrupts */
2110 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2111 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2112
2113 /*
2114 * Disable the peripheral clock for this serial port.
2115 * This is called on uart_close() or a suspend event.
2116 */
2117 clk_disable_unprepare(atmel_port->clk);
2118 if (__clk_is_enabled(atmel_port->gclk))
2119 clk_disable_unprepare(atmel_port->gclk);
2120 break;
2121 default:
2122 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2123 }
2124}
2125
2126/*
2127 * Change the port parameters
2128 */
2129static void atmel_set_termios(struct uart_port *port,
2130 struct ktermios *termios,
2131 const struct ktermios *old)
2132{
2133 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2134 unsigned long flags;
2135 unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
2136 unsigned int baud, actual_baud, gclk_rate;
2137 int ret;
2138
2139 /* save the current mode register */
2140 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2141
2142 /* reset the mode, clock divisor, parity, stop bits and data size */
2143 if (atmel_port->is_usart)
2144 mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
2145 ATMEL_US_USCLKS | ATMEL_US_USMODE);
2146 else
2147 mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
2148
2149 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2150
2151 /* byte size */
2152 switch (termios->c_cflag & CSIZE) {
2153 case CS5:
2154 mode |= ATMEL_US_CHRL_5;
2155 break;
2156 case CS6:
2157 mode |= ATMEL_US_CHRL_6;
2158 break;
2159 case CS7:
2160 mode |= ATMEL_US_CHRL_7;
2161 break;
2162 default:
2163 mode |= ATMEL_US_CHRL_8;
2164 break;
2165 }
2166
2167 /* stop bits */
2168 if (termios->c_cflag & CSTOPB)
2169 mode |= ATMEL_US_NBSTOP_2;
2170
2171 /* parity */
2172 if (termios->c_cflag & PARENB) {
2173 /* Mark or Space parity */
2174 if (termios->c_cflag & CMSPAR) {
2175 if (termios->c_cflag & PARODD)
2176 mode |= ATMEL_US_PAR_MARK;
2177 else
2178 mode |= ATMEL_US_PAR_SPACE;
2179 } else if (termios->c_cflag & PARODD)
2180 mode |= ATMEL_US_PAR_ODD;
2181 else
2182 mode |= ATMEL_US_PAR_EVEN;
2183 } else
2184 mode |= ATMEL_US_PAR_NONE;
2185
2186 uart_port_lock_irqsave(port, &flags);
2187
2188 port->read_status_mask = ATMEL_US_OVRE;
2189 if (termios->c_iflag & INPCK)
2190 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2191 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2192 port->read_status_mask |= ATMEL_US_RXBRK;
2193
2194 if (atmel_use_pdc_rx(port))
2195 /* need to enable error interrupts */
2196 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2197
2198 /*
2199 * Characters to ignore
2200 */
2201 port->ignore_status_mask = 0;
2202 if (termios->c_iflag & IGNPAR)
2203 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2204 if (termios->c_iflag & IGNBRK) {
2205 port->ignore_status_mask |= ATMEL_US_RXBRK;
2206 /*
2207 * If we're ignoring parity and break indicators,
2208 * ignore overruns too (for real raw support).
2209 */
2210 if (termios->c_iflag & IGNPAR)
2211 port->ignore_status_mask |= ATMEL_US_OVRE;
2212 }
2213 /* TODO: Ignore all characters if CREAD is set.*/
2214
2215 /* update the per-port timeout */
2216 uart_update_timeout(port, termios->c_cflag, baud);
2217
2218 /*
2219 * save/disable interrupts. The tty layer will ensure that the
2220 * transmitter is empty if requested by the caller, so there's
2221 * no need to wait for it here.
2222 */
2223 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2224 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2225
2226 /* disable receiver and transmitter */
2227 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2228 atmel_port->tx_stopped = true;
2229
2230 /* mode */
2231 if (port->rs485.flags & SER_RS485_ENABLED) {
2232 atmel_uart_writel(port, ATMEL_US_TTGR,
2233 port->rs485.delay_rts_after_send);
2234 mode |= ATMEL_US_USMODE_RS485;
2235 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2236 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2237 /* select mck clock, and output */
2238 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2239 /* set max iterations */
2240 mode |= ATMEL_US_MAX_ITER(3);
2241 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2242 == SER_ISO7816_T(0))
2243 mode |= ATMEL_US_USMODE_ISO7816_T0;
2244 else
2245 mode |= ATMEL_US_USMODE_ISO7816_T1;
2246 } else if (termios->c_cflag & CRTSCTS) {
2247 /* RS232 with hardware handshake (RTS/CTS) */
2248 if (atmel_use_fifo(port) &&
2249 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2250 /*
2251 * with ATMEL_US_USMODE_HWHS set, the controller will
2252 * be able to drive the RTS pin high/low when the RX
2253 * FIFO is above RXFTHRES/below RXFTHRES2.
2254 * It will also disable the transmitter when the CTS
2255 * pin is high.
2256 * This mode is not activated if CTS pin is a GPIO
2257 * because in this case, the transmitter is always
2258 * disabled (there must be an internal pull-up
2259 * responsible for this behaviour).
2260 * If the RTS pin is a GPIO, the controller won't be
2261 * able to drive it according to the FIFO thresholds,
2262 * but it will be handled by the driver.
2263 */
2264 mode |= ATMEL_US_USMODE_HWHS;
2265 } else {
2266 /*
2267 * For platforms without FIFO, the flow control is
2268 * handled by the driver.
2269 */
2270 mode |= ATMEL_US_USMODE_NORMAL;
2271 }
2272 } else {
2273 /* RS232 without hadware handshake */
2274 mode |= ATMEL_US_USMODE_NORMAL;
2275 }
2276
2277 /*
2278 * Set the baud rate:
2279 * Fractional baudrate allows to setup output frequency more
2280 * accurately. This feature is enabled only when using normal mode.
2281 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2282 * Currently, OVER is always set to 0 so we get
2283 * baudrate = selected clock / (16 * (CD + FP / 8))
2284 * then
2285 * 8 CD + FP = selected clock / (2 * baudrate)
2286 */
2287 if (atmel_port->has_frac_baudrate) {
2288 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2289 cd = div >> 3;
2290 fp = div & ATMEL_US_FP_MASK;
2291 } else {
2292 cd = uart_get_divisor(port, baud);
2293 }
2294
2295 /*
2296 * If the current value of the Clock Divisor surpasses the 16 bit
2297 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
2298 * Clock implicitly divided by 8.
2299 * If the IP is UART however, keep the highest possible value for
2300 * the CD and avoid needless division of CD, since UART IP's do not
2301 * support implicit division of the Peripheral Clock.
2302 */
2303 if (atmel_port->is_usart && cd > ATMEL_US_CD) {
2304 cd /= 8;
2305 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2306 } else {
2307 cd = min_t(unsigned int, cd, ATMEL_US_CD);
2308 }
2309
2310 /*
2311 * If there is no Fractional Part, there is a high chance that
2312 * we may be able to generate a baudrate closer to the desired one
2313 * if we use the GCLK as the clock source driving the baudrate
2314 * generator.
2315 */
2316 if (!atmel_port->has_frac_baudrate) {
2317 if (__clk_is_enabled(atmel_port->gclk))
2318 clk_disable_unprepare(atmel_port->gclk);
2319 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
2320 actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
2321 if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
2322 abs(atmel_error_rate(baud, gclk_rate / 16))) {
2323 clk_set_rate(atmel_port->gclk, 16 * baud);
2324 ret = clk_prepare_enable(atmel_port->gclk);
2325 if (ret)
2326 goto gclk_fail;
2327
2328 if (atmel_port->is_usart) {
2329 mode &= ~ATMEL_US_USCLKS;
2330 mode |= ATMEL_US_USCLKS_GCLK;
2331 } else {
2332 mode |= ATMEL_UA_BRSRCCK;
2333 }
2334
2335 /*
2336 * Set the Clock Divisor for GCLK to 1.
2337 * Since we were able to generate the smallest
2338 * multiple of the desired baudrate times 16,
2339 * then we surely can generate a bigger multiple
2340 * with the exact error rate for an equally increased
2341 * CD. Thus no need to take into account
2342 * a higher value for CD.
2343 */
2344 cd = 1;
2345 }
2346 }
2347
2348gclk_fail:
2349 quot = cd | fp << ATMEL_US_FP_OFFSET;
2350
2351 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2352 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2353
2354 /* set the mode, clock divisor, parity, stop bits and data size */
2355 atmel_uart_writel(port, ATMEL_US_MR, mode);
2356
2357 /*
2358 * when switching the mode, set the RTS line state according to the
2359 * new mode, otherwise keep the former state
2360 */
2361 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2362 unsigned int rts_state;
2363
2364 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2365 /* let the hardware control the RTS line */
2366 rts_state = ATMEL_US_RTSDIS;
2367 } else {
2368 /* force RTS line to low level */
2369 rts_state = ATMEL_US_RTSEN;
2370 }
2371
2372 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2373 }
2374
2375 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2376 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2377 atmel_port->tx_stopped = false;
2378
2379 /* restore interrupts */
2380 atmel_uart_writel(port, ATMEL_US_IER, imr);
2381
2382 /* CTS flow-control and modem-status interrupts */
2383 if (UART_ENABLE_MS(port, termios->c_cflag))
2384 atmel_enable_ms(port);
2385 else
2386 atmel_disable_ms(port);
2387
2388 uart_port_unlock_irqrestore(port, flags);
2389}
2390
2391static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2392{
2393 if (termios->c_line == N_PPS) {
2394 port->flags |= UPF_HARDPPS_CD;
2395 uart_port_lock_irq(port);
2396 atmel_enable_ms(port);
2397 uart_port_unlock_irq(port);
2398 } else {
2399 port->flags &= ~UPF_HARDPPS_CD;
2400 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2401 uart_port_lock_irq(port);
2402 atmel_disable_ms(port);
2403 uart_port_unlock_irq(port);
2404 }
2405 }
2406}
2407
2408/*
2409 * Return string describing the specified port
2410 */
2411static const char *atmel_type(struct uart_port *port)
2412{
2413 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2414}
2415
2416/*
2417 * Release the memory region(s) being used by 'port'.
2418 */
2419static void atmel_release_port(struct uart_port *port)
2420{
2421 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2422 int size = resource_size(mpdev->resource);
2423
2424 release_mem_region(port->mapbase, size);
2425
2426 if (port->flags & UPF_IOREMAP) {
2427 iounmap(port->membase);
2428 port->membase = NULL;
2429 }
2430}
2431
2432/*
2433 * Request the memory region(s) being used by 'port'.
2434 */
2435static int atmel_request_port(struct uart_port *port)
2436{
2437 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2438 int size = resource_size(mpdev->resource);
2439
2440 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2441 return -EBUSY;
2442
2443 if (port->flags & UPF_IOREMAP) {
2444 port->membase = ioremap(port->mapbase, size);
2445 if (port->membase == NULL) {
2446 release_mem_region(port->mapbase, size);
2447 return -ENOMEM;
2448 }
2449 }
2450
2451 return 0;
2452}
2453
2454/*
2455 * Configure/autoconfigure the port.
2456 */
2457static void atmel_config_port(struct uart_port *port, int flags)
2458{
2459 if (flags & UART_CONFIG_TYPE) {
2460 port->type = PORT_ATMEL;
2461 atmel_request_port(port);
2462 }
2463}
2464
2465/*
2466 * Verify the new serial_struct (for TIOCSSERIAL).
2467 */
2468static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2469{
2470 int ret = 0;
2471 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2472 ret = -EINVAL;
2473 if (port->irq != ser->irq)
2474 ret = -EINVAL;
2475 if (ser->io_type != SERIAL_IO_MEM)
2476 ret = -EINVAL;
2477 if (port->uartclk / 16 != ser->baud_base)
2478 ret = -EINVAL;
2479 if (port->mapbase != (unsigned long)ser->iomem_base)
2480 ret = -EINVAL;
2481 if (port->iobase != ser->port)
2482 ret = -EINVAL;
2483 if (ser->hub6 != 0)
2484 ret = -EINVAL;
2485 return ret;
2486}
2487
2488#ifdef CONFIG_CONSOLE_POLL
2489static int atmel_poll_get_char(struct uart_port *port)
2490{
2491 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2492 cpu_relax();
2493
2494 return atmel_uart_read_char(port);
2495}
2496
2497static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2498{
2499 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2500 cpu_relax();
2501
2502 atmel_uart_write_char(port, ch);
2503}
2504#endif
2505
2506static const struct uart_ops atmel_pops = {
2507 .tx_empty = atmel_tx_empty,
2508 .set_mctrl = atmel_set_mctrl,
2509 .get_mctrl = atmel_get_mctrl,
2510 .stop_tx = atmel_stop_tx,
2511 .start_tx = atmel_start_tx,
2512 .stop_rx = atmel_stop_rx,
2513 .enable_ms = atmel_enable_ms,
2514 .break_ctl = atmel_break_ctl,
2515 .startup = atmel_startup,
2516 .shutdown = atmel_shutdown,
2517 .flush_buffer = atmel_flush_buffer,
2518 .set_termios = atmel_set_termios,
2519 .set_ldisc = atmel_set_ldisc,
2520 .type = atmel_type,
2521 .release_port = atmel_release_port,
2522 .request_port = atmel_request_port,
2523 .config_port = atmel_config_port,
2524 .verify_port = atmel_verify_port,
2525 .pm = atmel_serial_pm,
2526#ifdef CONFIG_CONSOLE_POLL
2527 .poll_get_char = atmel_poll_get_char,
2528 .poll_put_char = atmel_poll_put_char,
2529#endif
2530};
2531
2532static const struct serial_rs485 atmel_rs485_supported = {
2533 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
2534 .delay_rts_before_send = 1,
2535 .delay_rts_after_send = 1,
2536};
2537
2538/*
2539 * Configure the port from the platform device resource info.
2540 */
2541static int atmel_init_port(struct atmel_uart_port *atmel_port,
2542 struct platform_device *pdev)
2543{
2544 int ret;
2545 struct uart_port *port = &atmel_port->uart;
2546 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2547
2548 atmel_init_property(atmel_port, pdev);
2549 atmel_set_ops(port);
2550
2551 port->iotype = UPIO_MEM;
2552 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2553 port->ops = &atmel_pops;
2554 port->fifosize = 1;
2555 port->dev = &pdev->dev;
2556 port->mapbase = mpdev->resource[0].start;
2557 port->irq = platform_get_irq(mpdev, 0);
2558 port->rs485_config = atmel_config_rs485;
2559 port->rs485_supported = atmel_rs485_supported;
2560 port->iso7816_config = atmel_config_iso7816;
2561 port->membase = NULL;
2562
2563 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2564
2565 ret = uart_get_rs485_mode(port);
2566 if (ret)
2567 return ret;
2568
2569 port->uartclk = clk_get_rate(atmel_port->clk);
2570
2571 /*
2572 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2573 * ENDTX|TXBUFE
2574 */
2575 if (atmel_uart_is_half_duplex(port))
2576 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2577 else if (atmel_use_pdc_tx(port)) {
2578 port->fifosize = PDC_BUFFER_SIZE;
2579 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2580 } else {
2581 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2582 }
2583
2584 return 0;
2585}
2586
2587#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2588static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
2589{
2590 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2591 cpu_relax();
2592 atmel_uart_write_char(port, ch);
2593}
2594
2595/*
2596 * Interrupts are disabled on entering
2597 */
2598static void atmel_console_write(struct console *co, const char *s, u_int count)
2599{
2600 struct uart_port *port = &atmel_ports[co->index].uart;
2601 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2602 unsigned int status, imr;
2603 unsigned int pdc_tx;
2604
2605 /*
2606 * First, save IMR and then disable interrupts
2607 */
2608 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2609 atmel_uart_writel(port, ATMEL_US_IDR,
2610 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2611
2612 /* Store PDC transmit status and disable it */
2613 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2614 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2615
2616 /* Make sure that tx path is actually able to send characters */
2617 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2618 atmel_port->tx_stopped = false;
2619
2620 uart_console_write(port, s, count, atmel_console_putchar);
2621
2622 /*
2623 * Finally, wait for transmitter to become empty
2624 * and restore IMR
2625 */
2626 do {
2627 status = atmel_uart_readl(port, ATMEL_US_CSR);
2628 } while (!(status & ATMEL_US_TXRDY));
2629
2630 /* Restore PDC transmit status */
2631 if (pdc_tx)
2632 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2633
2634 /* set interrupts back the way they were */
2635 atmel_uart_writel(port, ATMEL_US_IER, imr);
2636}
2637
2638/*
2639 * If the port was already initialised (eg, by a boot loader),
2640 * try to determine the current setup.
2641 */
2642static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2643 int *parity, int *bits)
2644{
2645 unsigned int mr, quot;
2646
2647 /*
2648 * If the baud rate generator isn't running, the port wasn't
2649 * initialized by the boot loader.
2650 */
2651 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2652 if (!quot)
2653 return;
2654
2655 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2656 if (mr == ATMEL_US_CHRL_8)
2657 *bits = 8;
2658 else
2659 *bits = 7;
2660
2661 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2662 if (mr == ATMEL_US_PAR_EVEN)
2663 *parity = 'e';
2664 else if (mr == ATMEL_US_PAR_ODD)
2665 *parity = 'o';
2666
2667 *baud = port->uartclk / (16 * quot);
2668}
2669
2670static int __init atmel_console_setup(struct console *co, char *options)
2671{
2672 struct uart_port *port = &atmel_ports[co->index].uart;
2673 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2674 int baud = 115200;
2675 int bits = 8;
2676 int parity = 'n';
2677 int flow = 'n';
2678
2679 if (port->membase == NULL) {
2680 /* Port not initialized yet - delay setup */
2681 return -ENODEV;
2682 }
2683
2684 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2685 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2686 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2687 atmel_port->tx_stopped = false;
2688
2689 if (options)
2690 uart_parse_options(options, &baud, &parity, &bits, &flow);
2691 else
2692 atmel_console_get_options(port, &baud, &parity, &bits);
2693
2694 return uart_set_options(port, co, baud, parity, bits, flow);
2695}
2696
2697static struct uart_driver atmel_uart;
2698
2699static struct console atmel_console = {
2700 .name = ATMEL_DEVICENAME,
2701 .write = atmel_console_write,
2702 .device = uart_console_device,
2703 .setup = atmel_console_setup,
2704 .flags = CON_PRINTBUFFER,
2705 .index = -1,
2706 .data = &atmel_uart,
2707};
2708
2709static void atmel_serial_early_write(struct console *con, const char *s,
2710 unsigned int n)
2711{
2712 struct earlycon_device *dev = con->data;
2713
2714 uart_console_write(&dev->port, s, n, atmel_console_putchar);
2715}
2716
2717static int __init atmel_early_console_setup(struct earlycon_device *device,
2718 const char *options)
2719{
2720 if (!device->port.membase)
2721 return -ENODEV;
2722
2723 device->con->write = atmel_serial_early_write;
2724
2725 return 0;
2726}
2727
2728OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2729 atmel_early_console_setup);
2730OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2731 atmel_early_console_setup);
2732
2733#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2734
2735#else
2736#define ATMEL_CONSOLE_DEVICE NULL
2737#endif
2738
2739static struct uart_driver atmel_uart = {
2740 .owner = THIS_MODULE,
2741 .driver_name = "atmel_serial",
2742 .dev_name = ATMEL_DEVICENAME,
2743 .major = SERIAL_ATMEL_MAJOR,
2744 .minor = MINOR_START,
2745 .nr = ATMEL_MAX_UART,
2746 .cons = ATMEL_CONSOLE_DEVICE,
2747};
2748
2749static bool atmel_serial_clk_will_stop(void)
2750{
2751#ifdef CONFIG_ARCH_AT91
2752 return at91_suspend_entering_slow_clock();
2753#else
2754 return false;
2755#endif
2756}
2757
2758static int __maybe_unused atmel_serial_suspend(struct device *dev)
2759{
2760 struct uart_port *port = dev_get_drvdata(dev);
2761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2762
2763 if (uart_console(port) && console_suspend_enabled) {
2764 /* Drain the TX shifter */
2765 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2766 ATMEL_US_TXEMPTY))
2767 cpu_relax();
2768 }
2769
2770 if (uart_console(port) && !console_suspend_enabled) {
2771 /* Cache register values as we won't get a full shutdown/startup
2772 * cycle
2773 */
2774 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2775 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2776 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2777 atmel_port->cache.rtor = atmel_uart_readl(port,
2778 atmel_port->rtor);
2779 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2780 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2781 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2782 }
2783
2784 /* we can not wake up if we're running on slow clock */
2785 atmel_port->may_wakeup = device_may_wakeup(dev);
2786 if (atmel_serial_clk_will_stop()) {
2787 unsigned long flags;
2788
2789 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2790 atmel_port->suspended = true;
2791 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2792 device_set_wakeup_enable(dev, 0);
2793 }
2794
2795 uart_suspend_port(&atmel_uart, port);
2796
2797 return 0;
2798}
2799
2800static int __maybe_unused atmel_serial_resume(struct device *dev)
2801{
2802 struct uart_port *port = dev_get_drvdata(dev);
2803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2804 unsigned long flags;
2805
2806 if (uart_console(port) && !console_suspend_enabled) {
2807 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2808 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2809 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2810 atmel_uart_writel(port, atmel_port->rtor,
2811 atmel_port->cache.rtor);
2812 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2813
2814 if (atmel_port->fifo_size) {
2815 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2816 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2817 atmel_uart_writel(port, ATMEL_US_FMR,
2818 atmel_port->cache.fmr);
2819 atmel_uart_writel(port, ATMEL_US_FIER,
2820 atmel_port->cache.fimr);
2821 }
2822 atmel_start_rx(port);
2823 }
2824
2825 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2826 if (atmel_port->pending) {
2827 atmel_handle_receive(port, atmel_port->pending);
2828 atmel_handle_status(port, atmel_port->pending,
2829 atmel_port->pending_status);
2830 atmel_handle_transmit(port, atmel_port->pending);
2831 atmel_port->pending = 0;
2832 }
2833 atmel_port->suspended = false;
2834 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2835
2836 uart_resume_port(&atmel_uart, port);
2837 device_set_wakeup_enable(dev, atmel_port->may_wakeup);
2838
2839 return 0;
2840}
2841
2842static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2843 struct platform_device *pdev)
2844{
2845 atmel_port->fifo_size = 0;
2846 atmel_port->rts_low = 0;
2847 atmel_port->rts_high = 0;
2848
2849 if (of_property_read_u32(pdev->dev.of_node,
2850 "atmel,fifo-size",
2851 &atmel_port->fifo_size))
2852 return;
2853
2854 if (!atmel_port->fifo_size)
2855 return;
2856
2857 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2858 atmel_port->fifo_size = 0;
2859 dev_err(&pdev->dev, "Invalid FIFO size\n");
2860 return;
2861 }
2862
2863 /*
2864 * 0 <= rts_low <= rts_high <= fifo_size
2865 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2866 * to flush their internal TX FIFO, commonly up to 16 data, before
2867 * actually stopping to send new data. So we try to set the RTS High
2868 * Threshold to a reasonably high value respecting this 16 data
2869 * empirical rule when possible.
2870 */
2871 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2872 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2873 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2874 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2875
2876 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2877 atmel_port->fifo_size);
2878 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2879 atmel_port->rts_high);
2880 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2881 atmel_port->rts_low);
2882}
2883
2884static int atmel_serial_probe(struct platform_device *pdev)
2885{
2886 struct atmel_uart_port *atmel_port;
2887 struct device_node *np = pdev->dev.parent->of_node;
2888 void *data;
2889 int ret;
2890 bool rs485_enabled;
2891
2892 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2893
2894 /*
2895 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2896 * as compatible string. This driver is probed by at91-usart mfd driver
2897 * which is just a wrapper over the atmel_serial driver and
2898 * spi-at91-usart driver. All attributes needed by this driver are
2899 * found in of_node of parent.
2900 */
2901 pdev->dev.of_node = np;
2902
2903 ret = of_alias_get_id(np, "serial");
2904 if (ret < 0)
2905 /* port id not found in platform data nor device-tree aliases:
2906 * auto-enumerate it */
2907 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2908
2909 if (ret >= ATMEL_MAX_UART) {
2910 ret = -ENODEV;
2911 goto err;
2912 }
2913
2914 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2915 /* port already in use */
2916 ret = -EBUSY;
2917 goto err;
2918 }
2919
2920 atmel_port = &atmel_ports[ret];
2921 atmel_port->backup_imr = 0;
2922 atmel_port->uart.line = ret;
2923 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2924 atmel_serial_probe_fifos(atmel_port, pdev);
2925
2926 atomic_set(&atmel_port->tasklet_shutdown, 0);
2927 spin_lock_init(&atmel_port->lock_suspended);
2928
2929 atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2930 if (IS_ERR(atmel_port->clk)) {
2931 ret = PTR_ERR(atmel_port->clk);
2932 goto err;
2933 }
2934 ret = clk_prepare_enable(atmel_port->clk);
2935 if (ret)
2936 goto err;
2937
2938 atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
2939 if (IS_ERR(atmel_port->gclk)) {
2940 ret = PTR_ERR(atmel_port->gclk);
2941 goto err_clk_disable_unprepare;
2942 }
2943
2944 ret = atmel_init_port(atmel_port, pdev);
2945 if (ret)
2946 goto err_clk_disable_unprepare;
2947
2948 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2949 if (IS_ERR(atmel_port->gpios)) {
2950 ret = PTR_ERR(atmel_port->gpios);
2951 goto err_clk_disable_unprepare;
2952 }
2953
2954 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2955 ret = -ENOMEM;
2956 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2957 sizeof(struct atmel_uart_char),
2958 GFP_KERNEL);
2959 if (!data)
2960 goto err_clk_disable_unprepare;
2961 atmel_port->rx_ring.buf = data;
2962 }
2963
2964 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2965
2966 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2967 if (ret)
2968 goto err_add_port;
2969
2970 device_init_wakeup(&pdev->dev, 1);
2971 platform_set_drvdata(pdev, atmel_port);
2972
2973 if (rs485_enabled) {
2974 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2975 ATMEL_US_USMODE_NORMAL);
2976 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2977 ATMEL_US_RTSEN);
2978 }
2979
2980 /*
2981 * Get port name of usart or uart
2982 */
2983 atmel_get_ip_name(&atmel_port->uart);
2984
2985 /*
2986 * The peripheral clock can now safely be disabled till the port
2987 * is used
2988 */
2989 clk_disable_unprepare(atmel_port->clk);
2990
2991 return 0;
2992
2993err_add_port:
2994 kfree(atmel_port->rx_ring.buf);
2995 atmel_port->rx_ring.buf = NULL;
2996err_clk_disable_unprepare:
2997 clk_disable_unprepare(atmel_port->clk);
2998 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2999err:
3000 return ret;
3001}
3002
3003/*
3004 * Even if the driver is not modular, it makes sense to be able to
3005 * unbind a device: there can be many bound devices, and there are
3006 * situations where dynamic binding and unbinding can be useful.
3007 *
3008 * For example, a connected device can require a specific firmware update
3009 * protocol that needs bitbanging on IO lines, but use the regular serial
3010 * port in the normal case.
3011 */
3012static void atmel_serial_remove(struct platform_device *pdev)
3013{
3014 struct uart_port *port = platform_get_drvdata(pdev);
3015 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
3016
3017 tasklet_kill(&atmel_port->tasklet_rx);
3018 tasklet_kill(&atmel_port->tasklet_tx);
3019
3020 device_init_wakeup(&pdev->dev, 0);
3021
3022 uart_remove_one_port(&atmel_uart, port);
3023
3024 kfree(atmel_port->rx_ring.buf);
3025
3026 /* "port" is allocated statically, so we shouldn't free it */
3027
3028 clear_bit(port->line, atmel_ports_in_use);
3029
3030 pdev->dev.of_node = NULL;
3031}
3032
3033static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
3034 atmel_serial_resume);
3035
3036static struct platform_driver atmel_serial_driver = {
3037 .probe = atmel_serial_probe,
3038 .remove_new = atmel_serial_remove,
3039 .driver = {
3040 .name = "atmel_usart_serial",
3041 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3042 .pm = pm_ptr(&atmel_serial_pm_ops),
3043 },
3044};
3045
3046static int __init atmel_serial_init(void)
3047{
3048 int ret;
3049
3050 ret = uart_register_driver(&atmel_uart);
3051 if (ret)
3052 return ret;
3053
3054 ret = platform_driver_register(&atmel_serial_driver);
3055 if (ret)
3056 uart_unregister_driver(&atmel_uart);
3057
3058 return ret;
3059}
3060device_initcall(atmel_serial_init);
1/*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#include <linux/tty.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/serial.h>
30#include <linux/clk.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
33#include <linux/tty_flip.h>
34#include <linux/platform_device.h>
35#include <linux/of.h>
36#include <linux/of_device.h>
37#include <linux/of_gpio.h>
38#include <linux/dma-mapping.h>
39#include <linux/dmaengine.h>
40#include <linux/atmel_pdc.h>
41#include <linux/atmel_serial.h>
42#include <linux/uaccess.h>
43#include <linux/platform_data/atmel.h>
44#include <linux/timer.h>
45#include <linux/gpio.h>
46#include <linux/gpio/consumer.h>
47#include <linux/err.h>
48#include <linux/irq.h>
49#include <linux/suspend.h>
50
51#include <asm/io.h>
52#include <asm/ioctls.h>
53
54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
58/* The minium number of data FIFOs should be able to contain */
59#define ATMEL_MIN_FIFO_SIZE 8
60/*
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
63 */
64#define ATMEL_RTS_HIGH_OFFSET 16
65#define ATMEL_RTS_LOW_OFFSET 20
66
67#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
68#define SUPPORT_SYSRQ
69#endif
70
71#include <linux/serial_core.h>
72
73#include "serial_mctrl_gpio.h"
74
75static void atmel_start_rx(struct uart_port *port);
76static void atmel_stop_rx(struct uart_port *port);
77
78#ifdef CONFIG_SERIAL_ATMEL_TTYAT
79
80/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
82 * UART. */
83#define SERIAL_ATMEL_MAJOR 204
84#define MINOR_START 154
85#define ATMEL_DEVICENAME "ttyAT"
86
87#else
88
89/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91#define SERIAL_ATMEL_MAJOR TTY_MAJOR
92#define MINOR_START 64
93#define ATMEL_DEVICENAME "ttyS"
94
95#endif
96
97#define ATMEL_ISR_PASS_LIMIT 256
98
99struct atmel_dma_buffer {
100 unsigned char *buf;
101 dma_addr_t dma_addr;
102 unsigned int dma_size;
103 unsigned int ofs;
104};
105
106struct atmel_uart_char {
107 u16 status;
108 u16 ch;
109};
110
111/*
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
115 * DMA mode.
116 */
117#define ATMEL_SERIAL_RINGSIZE 1024
118
119/*
120 * at91: 6 USARTs and one DBGU port (SAM9260)
121 * avr32: 4
122 */
123#define ATMEL_MAX_UART 7
124
125/*
126 * We wrap our port structure around the generic uart_port.
127 */
128struct atmel_uart_port {
129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
133 int break_active; /* break being received */
134
135 bool use_dma_rx; /* enable DMA receiver */
136 bool use_pdc_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
139
140 bool use_dma_tx; /* enable DMA transmitter */
141 bool use_pdc_tx; /* enable PDC transmitter */
142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
143
144 spinlock_t lock_tx; /* port lock */
145 spinlock_t lock_rx; /* port lock */
146 struct dma_chan *chan_tx;
147 struct dma_chan *chan_rx;
148 struct dma_async_tx_descriptor *desc_tx;
149 struct dma_async_tx_descriptor *desc_rx;
150 dma_cookie_t cookie_tx;
151 dma_cookie_t cookie_rx;
152 struct scatterlist sg_tx;
153 struct scatterlist sg_rx;
154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
156 atomic_t tasklet_shutdown;
157 unsigned int irq_status_prev;
158 unsigned int tx_len;
159
160 struct circ_buf rx_ring;
161
162 struct mctrl_gpios *gpios;
163 unsigned int tx_done_mask;
164 u32 fifo_size;
165 u32 rts_high;
166 u32 rts_low;
167 bool ms_irq_enabled;
168 u32 rtor; /* address of receiver timeout register if it exists */
169 bool has_frac_baudrate;
170 bool has_hw_timer;
171 struct timer_list uart_timer;
172
173 bool suspended;
174 unsigned int pending;
175 unsigned int pending_status;
176 spinlock_t lock_suspended;
177
178 int (*prepare_rx)(struct uart_port *port);
179 int (*prepare_tx)(struct uart_port *port);
180 void (*schedule_rx)(struct uart_port *port);
181 void (*schedule_tx)(struct uart_port *port);
182 void (*release_rx)(struct uart_port *port);
183 void (*release_tx)(struct uart_port *port);
184};
185
186static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
187static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
188
189#ifdef SUPPORT_SYSRQ
190static struct console atmel_console;
191#endif
192
193#if defined(CONFIG_OF)
194static const struct of_device_id atmel_serial_dt_ids[] = {
195 { .compatible = "atmel,at91rm9200-usart" },
196 { .compatible = "atmel,at91sam9260-usart" },
197 { /* sentinel */ }
198};
199#endif
200
201static inline struct atmel_uart_port *
202to_atmel_uart_port(struct uart_port *uart)
203{
204 return container_of(uart, struct atmel_uart_port, uart);
205}
206
207static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
208{
209 return __raw_readl(port->membase + reg);
210}
211
212static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
213{
214 __raw_writel(value, port->membase + reg);
215}
216
217#ifdef CONFIG_AVR32
218
219/* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
220static inline u8 atmel_uart_read_char(struct uart_port *port)
221{
222 return __raw_readl(port->membase + ATMEL_US_RHR);
223}
224
225static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
226{
227 __raw_writel(value, port->membase + ATMEL_US_THR);
228}
229
230#else
231
232static inline u8 atmel_uart_read_char(struct uart_port *port)
233{
234 return __raw_readb(port->membase + ATMEL_US_RHR);
235}
236
237static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
238{
239 __raw_writeb(value, port->membase + ATMEL_US_THR);
240}
241
242#endif
243
244#ifdef CONFIG_SERIAL_ATMEL_PDC
245static bool atmel_use_pdc_rx(struct uart_port *port)
246{
247 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
248
249 return atmel_port->use_pdc_rx;
250}
251
252static bool atmel_use_pdc_tx(struct uart_port *port)
253{
254 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
255
256 return atmel_port->use_pdc_tx;
257}
258#else
259static bool atmel_use_pdc_rx(struct uart_port *port)
260{
261 return false;
262}
263
264static bool atmel_use_pdc_tx(struct uart_port *port)
265{
266 return false;
267}
268#endif
269
270static bool atmel_use_dma_tx(struct uart_port *port)
271{
272 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
273
274 return atmel_port->use_dma_tx;
275}
276
277static bool atmel_use_dma_rx(struct uart_port *port)
278{
279 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
280
281 return atmel_port->use_dma_rx;
282}
283
284static bool atmel_use_fifo(struct uart_port *port)
285{
286 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
287
288 return atmel_port->fifo_size;
289}
290
291static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
292 struct tasklet_struct *t)
293{
294 if (!atomic_read(&atmel_port->tasklet_shutdown))
295 tasklet_schedule(t);
296}
297
298static unsigned int atmel_get_lines_status(struct uart_port *port)
299{
300 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
301 unsigned int status, ret = 0;
302
303 status = atmel_uart_readl(port, ATMEL_US_CSR);
304
305 mctrl_gpio_get(atmel_port->gpios, &ret);
306
307 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
308 UART_GPIO_CTS))) {
309 if (ret & TIOCM_CTS)
310 status &= ~ATMEL_US_CTS;
311 else
312 status |= ATMEL_US_CTS;
313 }
314
315 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
316 UART_GPIO_DSR))) {
317 if (ret & TIOCM_DSR)
318 status &= ~ATMEL_US_DSR;
319 else
320 status |= ATMEL_US_DSR;
321 }
322
323 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
324 UART_GPIO_RI))) {
325 if (ret & TIOCM_RI)
326 status &= ~ATMEL_US_RI;
327 else
328 status |= ATMEL_US_RI;
329 }
330
331 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
332 UART_GPIO_DCD))) {
333 if (ret & TIOCM_CD)
334 status &= ~ATMEL_US_DCD;
335 else
336 status |= ATMEL_US_DCD;
337 }
338
339 return status;
340}
341
342/* Enable or disable the rs485 support */
343static int atmel_config_rs485(struct uart_port *port,
344 struct serial_rs485 *rs485conf)
345{
346 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
347 unsigned int mode;
348
349 /* Disable interrupts */
350 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
351
352 mode = atmel_uart_readl(port, ATMEL_US_MR);
353
354 /* Resetting serial mode to RS232 (0x0) */
355 mode &= ~ATMEL_US_USMODE;
356
357 port->rs485 = *rs485conf;
358
359 if (rs485conf->flags & SER_RS485_ENABLED) {
360 dev_dbg(port->dev, "Setting UART to RS485\n");
361 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
362 atmel_uart_writel(port, ATMEL_US_TTGR,
363 rs485conf->delay_rts_after_send);
364 mode |= ATMEL_US_USMODE_RS485;
365 } else {
366 dev_dbg(port->dev, "Setting UART to RS232\n");
367 if (atmel_use_pdc_tx(port))
368 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
369 ATMEL_US_TXBUFE;
370 else
371 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
372 }
373 atmel_uart_writel(port, ATMEL_US_MR, mode);
374
375 /* Enable interrupts */
376 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
377
378 return 0;
379}
380
381/*
382 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
383 */
384static u_int atmel_tx_empty(struct uart_port *port)
385{
386 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
387 TIOCSER_TEMT :
388 0;
389}
390
391/*
392 * Set state of the modem control output lines
393 */
394static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
395{
396 unsigned int control = 0;
397 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
398 unsigned int rts_paused, rts_ready;
399 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
400
401 /* override mode to RS485 if needed, otherwise keep the current mode */
402 if (port->rs485.flags & SER_RS485_ENABLED) {
403 atmel_uart_writel(port, ATMEL_US_TTGR,
404 port->rs485.delay_rts_after_send);
405 mode &= ~ATMEL_US_USMODE;
406 mode |= ATMEL_US_USMODE_RS485;
407 }
408
409 /* set the RTS line state according to the mode */
410 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
411 /* force RTS line to high level */
412 rts_paused = ATMEL_US_RTSEN;
413
414 /* give the control of the RTS line back to the hardware */
415 rts_ready = ATMEL_US_RTSDIS;
416 } else {
417 /* force RTS line to high level */
418 rts_paused = ATMEL_US_RTSDIS;
419
420 /* force RTS line to low level */
421 rts_ready = ATMEL_US_RTSEN;
422 }
423
424 if (mctrl & TIOCM_RTS)
425 control |= rts_ready;
426 else
427 control |= rts_paused;
428
429 if (mctrl & TIOCM_DTR)
430 control |= ATMEL_US_DTREN;
431 else
432 control |= ATMEL_US_DTRDIS;
433
434 atmel_uart_writel(port, ATMEL_US_CR, control);
435
436 mctrl_gpio_set(atmel_port->gpios, mctrl);
437
438 /* Local loopback mode? */
439 mode &= ~ATMEL_US_CHMODE;
440 if (mctrl & TIOCM_LOOP)
441 mode |= ATMEL_US_CHMODE_LOC_LOOP;
442 else
443 mode |= ATMEL_US_CHMODE_NORMAL;
444
445 atmel_uart_writel(port, ATMEL_US_MR, mode);
446}
447
448/*
449 * Get state of the modem control input lines
450 */
451static u_int atmel_get_mctrl(struct uart_port *port)
452{
453 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
454 unsigned int ret = 0, status;
455
456 status = atmel_uart_readl(port, ATMEL_US_CSR);
457
458 /*
459 * The control signals are active low.
460 */
461 if (!(status & ATMEL_US_DCD))
462 ret |= TIOCM_CD;
463 if (!(status & ATMEL_US_CTS))
464 ret |= TIOCM_CTS;
465 if (!(status & ATMEL_US_DSR))
466 ret |= TIOCM_DSR;
467 if (!(status & ATMEL_US_RI))
468 ret |= TIOCM_RI;
469
470 return mctrl_gpio_get(atmel_port->gpios, &ret);
471}
472
473/*
474 * Stop transmitting.
475 */
476static void atmel_stop_tx(struct uart_port *port)
477{
478 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
479
480 if (atmel_use_pdc_tx(port)) {
481 /* disable PDC transmit */
482 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
483 }
484
485 /*
486 * Disable the transmitter.
487 * This is mandatory when DMA is used, otherwise the DMA buffer
488 * is fully transmitted.
489 */
490 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
491
492 /* Disable interrupts */
493 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
494
495 if ((port->rs485.flags & SER_RS485_ENABLED) &&
496 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
497 atmel_start_rx(port);
498}
499
500/*
501 * Start transmitting.
502 */
503static void atmel_start_tx(struct uart_port *port)
504{
505 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
506
507 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
508 & ATMEL_PDC_TXTEN))
509 /* The transmitter is already running. Yes, we
510 really need this.*/
511 return;
512
513 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
514 if ((port->rs485.flags & SER_RS485_ENABLED) &&
515 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
516 atmel_stop_rx(port);
517
518 if (atmel_use_pdc_tx(port))
519 /* re-enable PDC transmit */
520 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
521
522 /* Enable interrupts */
523 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
524
525 /* re-enable the transmitter */
526 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
527}
528
529/*
530 * start receiving - port is in process of being opened.
531 */
532static void atmel_start_rx(struct uart_port *port)
533{
534 /* reset status and receiver */
535 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
536
537 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
538
539 if (atmel_use_pdc_rx(port)) {
540 /* enable PDC controller */
541 atmel_uart_writel(port, ATMEL_US_IER,
542 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
543 port->read_status_mask);
544 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
545 } else {
546 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
547 }
548}
549
550/*
551 * Stop receiving - port is in process of being closed.
552 */
553static void atmel_stop_rx(struct uart_port *port)
554{
555 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
556
557 if (atmel_use_pdc_rx(port)) {
558 /* disable PDC receive */
559 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
560 atmel_uart_writel(port, ATMEL_US_IDR,
561 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
562 port->read_status_mask);
563 } else {
564 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
565 }
566}
567
568/*
569 * Enable modem status interrupts
570 */
571static void atmel_enable_ms(struct uart_port *port)
572{
573 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
574 uint32_t ier = 0;
575
576 /*
577 * Interrupt should not be enabled twice
578 */
579 if (atmel_port->ms_irq_enabled)
580 return;
581
582 atmel_port->ms_irq_enabled = true;
583
584 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
585 ier |= ATMEL_US_CTSIC;
586
587 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
588 ier |= ATMEL_US_DSRIC;
589
590 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
591 ier |= ATMEL_US_RIIC;
592
593 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
594 ier |= ATMEL_US_DCDIC;
595
596 atmel_uart_writel(port, ATMEL_US_IER, ier);
597
598 mctrl_gpio_enable_ms(atmel_port->gpios);
599}
600
601/*
602 * Disable modem status interrupts
603 */
604static void atmel_disable_ms(struct uart_port *port)
605{
606 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
607 uint32_t idr = 0;
608
609 /*
610 * Interrupt should not be disabled twice
611 */
612 if (!atmel_port->ms_irq_enabled)
613 return;
614
615 atmel_port->ms_irq_enabled = false;
616
617 mctrl_gpio_disable_ms(atmel_port->gpios);
618
619 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
620 idr |= ATMEL_US_CTSIC;
621
622 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
623 idr |= ATMEL_US_DSRIC;
624
625 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
626 idr |= ATMEL_US_RIIC;
627
628 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
629 idr |= ATMEL_US_DCDIC;
630
631 atmel_uart_writel(port, ATMEL_US_IDR, idr);
632}
633
634/*
635 * Control the transmission of a break signal
636 */
637static void atmel_break_ctl(struct uart_port *port, int break_state)
638{
639 if (break_state != 0)
640 /* start break */
641 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
642 else
643 /* stop break */
644 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
645}
646
647/*
648 * Stores the incoming character in the ring buffer
649 */
650static void
651atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
652 unsigned int ch)
653{
654 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
655 struct circ_buf *ring = &atmel_port->rx_ring;
656 struct atmel_uart_char *c;
657
658 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
659 /* Buffer overflow, ignore char */
660 return;
661
662 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
663 c->status = status;
664 c->ch = ch;
665
666 /* Make sure the character is stored before we update head. */
667 smp_wmb();
668
669 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
670}
671
672/*
673 * Deal with parity, framing and overrun errors.
674 */
675static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
676{
677 /* clear error */
678 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
679
680 if (status & ATMEL_US_RXBRK) {
681 /* ignore side-effect */
682 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
683 port->icount.brk++;
684 }
685 if (status & ATMEL_US_PARE)
686 port->icount.parity++;
687 if (status & ATMEL_US_FRAME)
688 port->icount.frame++;
689 if (status & ATMEL_US_OVRE)
690 port->icount.overrun++;
691}
692
693/*
694 * Characters received (called from interrupt handler)
695 */
696static void atmel_rx_chars(struct uart_port *port)
697{
698 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
699 unsigned int status, ch;
700
701 status = atmel_uart_readl(port, ATMEL_US_CSR);
702 while (status & ATMEL_US_RXRDY) {
703 ch = atmel_uart_read_char(port);
704
705 /*
706 * note that the error handling code is
707 * out of the main execution path
708 */
709 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
710 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
711 || atmel_port->break_active)) {
712
713 /* clear error */
714 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
715
716 if (status & ATMEL_US_RXBRK
717 && !atmel_port->break_active) {
718 atmel_port->break_active = 1;
719 atmel_uart_writel(port, ATMEL_US_IER,
720 ATMEL_US_RXBRK);
721 } else {
722 /*
723 * This is either the end-of-break
724 * condition or we've received at
725 * least one character without RXBRK
726 * being set. In both cases, the next
727 * RXBRK will indicate start-of-break.
728 */
729 atmel_uart_writel(port, ATMEL_US_IDR,
730 ATMEL_US_RXBRK);
731 status &= ~ATMEL_US_RXBRK;
732 atmel_port->break_active = 0;
733 }
734 }
735
736 atmel_buffer_rx_char(port, status, ch);
737 status = atmel_uart_readl(port, ATMEL_US_CSR);
738 }
739
740 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
741}
742
743/*
744 * Transmit characters (called from tasklet with TXRDY interrupt
745 * disabled)
746 */
747static void atmel_tx_chars(struct uart_port *port)
748{
749 struct circ_buf *xmit = &port->state->xmit;
750 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
751
752 if (port->x_char &&
753 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
754 atmel_uart_write_char(port, port->x_char);
755 port->icount.tx++;
756 port->x_char = 0;
757 }
758 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
759 return;
760
761 while (atmel_uart_readl(port, ATMEL_US_CSR) &
762 atmel_port->tx_done_mask) {
763 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
764 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
765 port->icount.tx++;
766 if (uart_circ_empty(xmit))
767 break;
768 }
769
770 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
771 uart_write_wakeup(port);
772
773 if (!uart_circ_empty(xmit))
774 /* Enable interrupts */
775 atmel_uart_writel(port, ATMEL_US_IER,
776 atmel_port->tx_done_mask);
777}
778
779static void atmel_complete_tx_dma(void *arg)
780{
781 struct atmel_uart_port *atmel_port = arg;
782 struct uart_port *port = &atmel_port->uart;
783 struct circ_buf *xmit = &port->state->xmit;
784 struct dma_chan *chan = atmel_port->chan_tx;
785 unsigned long flags;
786
787 spin_lock_irqsave(&port->lock, flags);
788
789 if (chan)
790 dmaengine_terminate_all(chan);
791 xmit->tail += atmel_port->tx_len;
792 xmit->tail &= UART_XMIT_SIZE - 1;
793
794 port->icount.tx += atmel_port->tx_len;
795
796 spin_lock_irq(&atmel_port->lock_tx);
797 async_tx_ack(atmel_port->desc_tx);
798 atmel_port->cookie_tx = -EINVAL;
799 atmel_port->desc_tx = NULL;
800 spin_unlock_irq(&atmel_port->lock_tx);
801
802 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
803 uart_write_wakeup(port);
804
805 /*
806 * xmit is a circular buffer so, if we have just send data from
807 * xmit->tail to the end of xmit->buf, now we have to transmit the
808 * remaining data from the beginning of xmit->buf to xmit->head.
809 */
810 if (!uart_circ_empty(xmit))
811 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
812 else if ((port->rs485.flags & SER_RS485_ENABLED) &&
813 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
814 /* DMA done, stop TX, start RX for RS485 */
815 atmel_start_rx(port);
816 }
817
818 spin_unlock_irqrestore(&port->lock, flags);
819}
820
821static void atmel_release_tx_dma(struct uart_port *port)
822{
823 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
824 struct dma_chan *chan = atmel_port->chan_tx;
825
826 if (chan) {
827 dmaengine_terminate_all(chan);
828 dma_release_channel(chan);
829 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
830 DMA_TO_DEVICE);
831 }
832
833 atmel_port->desc_tx = NULL;
834 atmel_port->chan_tx = NULL;
835 atmel_port->cookie_tx = -EINVAL;
836}
837
838/*
839 * Called from tasklet with TXRDY interrupt is disabled.
840 */
841static void atmel_tx_dma(struct uart_port *port)
842{
843 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
844 struct circ_buf *xmit = &port->state->xmit;
845 struct dma_chan *chan = atmel_port->chan_tx;
846 struct dma_async_tx_descriptor *desc;
847 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
848 unsigned int tx_len, part1_len, part2_len, sg_len;
849 dma_addr_t phys_addr;
850
851 /* Make sure we have an idle channel */
852 if (atmel_port->desc_tx != NULL)
853 return;
854
855 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
856 /*
857 * DMA is idle now.
858 * Port xmit buffer is already mapped,
859 * and it is one page... Just adjust
860 * offsets and lengths. Since it is a circular buffer,
861 * we have to transmit till the end, and then the rest.
862 * Take the port lock to get a
863 * consistent xmit buffer state.
864 */
865 tx_len = CIRC_CNT_TO_END(xmit->head,
866 xmit->tail,
867 UART_XMIT_SIZE);
868
869 if (atmel_port->fifo_size) {
870 /* multi data mode */
871 part1_len = (tx_len & ~0x3); /* DWORD access */
872 part2_len = (tx_len & 0x3); /* BYTE access */
873 } else {
874 /* single data (legacy) mode */
875 part1_len = 0;
876 part2_len = tx_len; /* BYTE access only */
877 }
878
879 sg_init_table(sgl, 2);
880 sg_len = 0;
881 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
882 if (part1_len) {
883 sg = &sgl[sg_len++];
884 sg_dma_address(sg) = phys_addr;
885 sg_dma_len(sg) = part1_len;
886
887 phys_addr += part1_len;
888 }
889
890 if (part2_len) {
891 sg = &sgl[sg_len++];
892 sg_dma_address(sg) = phys_addr;
893 sg_dma_len(sg) = part2_len;
894 }
895
896 /*
897 * save tx_len so atmel_complete_tx_dma() will increase
898 * xmit->tail correctly
899 */
900 atmel_port->tx_len = tx_len;
901
902 desc = dmaengine_prep_slave_sg(chan,
903 sgl,
904 sg_len,
905 DMA_MEM_TO_DEV,
906 DMA_PREP_INTERRUPT |
907 DMA_CTRL_ACK);
908 if (!desc) {
909 dev_err(port->dev, "Failed to send via dma!\n");
910 return;
911 }
912
913 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
914
915 atmel_port->desc_tx = desc;
916 desc->callback = atmel_complete_tx_dma;
917 desc->callback_param = atmel_port;
918 atmel_port->cookie_tx = dmaengine_submit(desc);
919 }
920
921 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
922 uart_write_wakeup(port);
923}
924
925static int atmel_prepare_tx_dma(struct uart_port *port)
926{
927 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
928 dma_cap_mask_t mask;
929 struct dma_slave_config config;
930 int ret, nent;
931
932 dma_cap_zero(mask);
933 dma_cap_set(DMA_SLAVE, mask);
934
935 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
936 if (atmel_port->chan_tx == NULL)
937 goto chan_err;
938 dev_info(port->dev, "using %s for tx DMA transfers\n",
939 dma_chan_name(atmel_port->chan_tx));
940
941 spin_lock_init(&atmel_port->lock_tx);
942 sg_init_table(&atmel_port->sg_tx, 1);
943 /* UART circular tx buffer is an aligned page. */
944 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
945 sg_set_page(&atmel_port->sg_tx,
946 virt_to_page(port->state->xmit.buf),
947 UART_XMIT_SIZE,
948 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
949 nent = dma_map_sg(port->dev,
950 &atmel_port->sg_tx,
951 1,
952 DMA_TO_DEVICE);
953
954 if (!nent) {
955 dev_dbg(port->dev, "need to release resource of dma\n");
956 goto chan_err;
957 } else {
958 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
959 sg_dma_len(&atmel_port->sg_tx),
960 port->state->xmit.buf,
961 &sg_dma_address(&atmel_port->sg_tx));
962 }
963
964 /* Configure the slave DMA */
965 memset(&config, 0, sizeof(config));
966 config.direction = DMA_MEM_TO_DEV;
967 config.dst_addr_width = (atmel_port->fifo_size) ?
968 DMA_SLAVE_BUSWIDTH_4_BYTES :
969 DMA_SLAVE_BUSWIDTH_1_BYTE;
970 config.dst_addr = port->mapbase + ATMEL_US_THR;
971 config.dst_maxburst = 1;
972
973 ret = dmaengine_slave_config(atmel_port->chan_tx,
974 &config);
975 if (ret) {
976 dev_err(port->dev, "DMA tx slave configuration failed\n");
977 goto chan_err;
978 }
979
980 return 0;
981
982chan_err:
983 dev_err(port->dev, "TX channel not available, switch to pio\n");
984 atmel_port->use_dma_tx = 0;
985 if (atmel_port->chan_tx)
986 atmel_release_tx_dma(port);
987 return -EINVAL;
988}
989
990static void atmel_complete_rx_dma(void *arg)
991{
992 struct uart_port *port = arg;
993 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
994
995 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
996}
997
998static void atmel_release_rx_dma(struct uart_port *port)
999{
1000 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1001 struct dma_chan *chan = atmel_port->chan_rx;
1002
1003 if (chan) {
1004 dmaengine_terminate_all(chan);
1005 dma_release_channel(chan);
1006 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1007 DMA_FROM_DEVICE);
1008 }
1009
1010 atmel_port->desc_rx = NULL;
1011 atmel_port->chan_rx = NULL;
1012 atmel_port->cookie_rx = -EINVAL;
1013}
1014
1015static void atmel_rx_from_dma(struct uart_port *port)
1016{
1017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1018 struct tty_port *tport = &port->state->port;
1019 struct circ_buf *ring = &atmel_port->rx_ring;
1020 struct dma_chan *chan = atmel_port->chan_rx;
1021 struct dma_tx_state state;
1022 enum dma_status dmastat;
1023 size_t count;
1024
1025
1026 /* Reset the UART timeout early so that we don't miss one */
1027 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1028 dmastat = dmaengine_tx_status(chan,
1029 atmel_port->cookie_rx,
1030 &state);
1031 /* Restart a new tasklet if DMA status is error */
1032 if (dmastat == DMA_ERROR) {
1033 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1034 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1035 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1036 return;
1037 }
1038
1039 /* CPU claims ownership of RX DMA buffer */
1040 dma_sync_sg_for_cpu(port->dev,
1041 &atmel_port->sg_rx,
1042 1,
1043 DMA_FROM_DEVICE);
1044
1045 /*
1046 * ring->head points to the end of data already written by the DMA.
1047 * ring->tail points to the beginning of data to be read by the
1048 * framework.
1049 * The current transfer size should not be larger than the dma buffer
1050 * length.
1051 */
1052 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1053 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1054 /*
1055 * At this point ring->head may point to the first byte right after the
1056 * last byte of the dma buffer:
1057 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1058 *
1059 * However ring->tail must always points inside the dma buffer:
1060 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1061 *
1062 * Since we use a ring buffer, we have to handle the case
1063 * where head is lower than tail. In such a case, we first read from
1064 * tail to the end of the buffer then reset tail.
1065 */
1066 if (ring->head < ring->tail) {
1067 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1068
1069 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1070 ring->tail = 0;
1071 port->icount.rx += count;
1072 }
1073
1074 /* Finally we read data from tail to head */
1075 if (ring->tail < ring->head) {
1076 count = ring->head - ring->tail;
1077
1078 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1079 /* Wrap ring->head if needed */
1080 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1081 ring->head = 0;
1082 ring->tail = ring->head;
1083 port->icount.rx += count;
1084 }
1085
1086 /* USART retreives ownership of RX DMA buffer */
1087 dma_sync_sg_for_device(port->dev,
1088 &atmel_port->sg_rx,
1089 1,
1090 DMA_FROM_DEVICE);
1091
1092 /*
1093 * Drop the lock here since it might end up calling
1094 * uart_start(), which takes the lock.
1095 */
1096 spin_unlock(&port->lock);
1097 tty_flip_buffer_push(tport);
1098 spin_lock(&port->lock);
1099
1100 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1101}
1102
1103static int atmel_prepare_rx_dma(struct uart_port *port)
1104{
1105 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1106 struct dma_async_tx_descriptor *desc;
1107 dma_cap_mask_t mask;
1108 struct dma_slave_config config;
1109 struct circ_buf *ring;
1110 int ret, nent;
1111
1112 ring = &atmel_port->rx_ring;
1113
1114 dma_cap_zero(mask);
1115 dma_cap_set(DMA_CYCLIC, mask);
1116
1117 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1118 if (atmel_port->chan_rx == NULL)
1119 goto chan_err;
1120 dev_info(port->dev, "using %s for rx DMA transfers\n",
1121 dma_chan_name(atmel_port->chan_rx));
1122
1123 spin_lock_init(&atmel_port->lock_rx);
1124 sg_init_table(&atmel_port->sg_rx, 1);
1125 /* UART circular rx buffer is an aligned page. */
1126 BUG_ON(!PAGE_ALIGNED(ring->buf));
1127 sg_set_page(&atmel_port->sg_rx,
1128 virt_to_page(ring->buf),
1129 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1130 (unsigned long)ring->buf & ~PAGE_MASK);
1131 nent = dma_map_sg(port->dev,
1132 &atmel_port->sg_rx,
1133 1,
1134 DMA_FROM_DEVICE);
1135
1136 if (!nent) {
1137 dev_dbg(port->dev, "need to release resource of dma\n");
1138 goto chan_err;
1139 } else {
1140 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1141 sg_dma_len(&atmel_port->sg_rx),
1142 ring->buf,
1143 &sg_dma_address(&atmel_port->sg_rx));
1144 }
1145
1146 /* Configure the slave DMA */
1147 memset(&config, 0, sizeof(config));
1148 config.direction = DMA_DEV_TO_MEM;
1149 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1150 config.src_addr = port->mapbase + ATMEL_US_RHR;
1151 config.src_maxburst = 1;
1152
1153 ret = dmaengine_slave_config(atmel_port->chan_rx,
1154 &config);
1155 if (ret) {
1156 dev_err(port->dev, "DMA rx slave configuration failed\n");
1157 goto chan_err;
1158 }
1159 /*
1160 * Prepare a cyclic dma transfer, assign 2 descriptors,
1161 * each one is half ring buffer size
1162 */
1163 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1164 sg_dma_address(&atmel_port->sg_rx),
1165 sg_dma_len(&atmel_port->sg_rx),
1166 sg_dma_len(&atmel_port->sg_rx)/2,
1167 DMA_DEV_TO_MEM,
1168 DMA_PREP_INTERRUPT);
1169 desc->callback = atmel_complete_rx_dma;
1170 desc->callback_param = port;
1171 atmel_port->desc_rx = desc;
1172 atmel_port->cookie_rx = dmaengine_submit(desc);
1173
1174 return 0;
1175
1176chan_err:
1177 dev_err(port->dev, "RX channel not available, switch to pio\n");
1178 atmel_port->use_dma_rx = 0;
1179 if (atmel_port->chan_rx)
1180 atmel_release_rx_dma(port);
1181 return -EINVAL;
1182}
1183
1184static void atmel_uart_timer_callback(unsigned long data)
1185{
1186 struct uart_port *port = (void *)data;
1187 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1188
1189 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1190 tasklet_schedule(&atmel_port->tasklet_rx);
1191 mod_timer(&atmel_port->uart_timer,
1192 jiffies + uart_poll_timeout(port));
1193 }
1194}
1195
1196/*
1197 * receive interrupt handler.
1198 */
1199static void
1200atmel_handle_receive(struct uart_port *port, unsigned int pending)
1201{
1202 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1203
1204 if (atmel_use_pdc_rx(port)) {
1205 /*
1206 * PDC receive. Just schedule the tasklet and let it
1207 * figure out the details.
1208 *
1209 * TODO: We're not handling error flags correctly at
1210 * the moment.
1211 */
1212 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1213 atmel_uart_writel(port, ATMEL_US_IDR,
1214 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1215 atmel_tasklet_schedule(atmel_port,
1216 &atmel_port->tasklet_rx);
1217 }
1218
1219 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1220 ATMEL_US_FRAME | ATMEL_US_PARE))
1221 atmel_pdc_rxerr(port, pending);
1222 }
1223
1224 if (atmel_use_dma_rx(port)) {
1225 if (pending & ATMEL_US_TIMEOUT) {
1226 atmel_uart_writel(port, ATMEL_US_IDR,
1227 ATMEL_US_TIMEOUT);
1228 atmel_tasklet_schedule(atmel_port,
1229 &atmel_port->tasklet_rx);
1230 }
1231 }
1232
1233 /* Interrupt receive */
1234 if (pending & ATMEL_US_RXRDY)
1235 atmel_rx_chars(port);
1236 else if (pending & ATMEL_US_RXBRK) {
1237 /*
1238 * End of break detected. If it came along with a
1239 * character, atmel_rx_chars will handle it.
1240 */
1241 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1242 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1243 atmel_port->break_active = 0;
1244 }
1245}
1246
1247/*
1248 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1249 */
1250static void
1251atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1252{
1253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1254
1255 if (pending & atmel_port->tx_done_mask) {
1256 /* Either PDC or interrupt transmission */
1257 atmel_uart_writel(port, ATMEL_US_IDR,
1258 atmel_port->tx_done_mask);
1259 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1260 }
1261}
1262
1263/*
1264 * status flags interrupt handler.
1265 */
1266static void
1267atmel_handle_status(struct uart_port *port, unsigned int pending,
1268 unsigned int status)
1269{
1270 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1271 unsigned int status_change;
1272
1273 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1274 | ATMEL_US_CTSIC)) {
1275 status_change = status ^ atmel_port->irq_status_prev;
1276 atmel_port->irq_status_prev = status;
1277
1278 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1279 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1280 /* TODO: All reads to CSR will clear these interrupts! */
1281 if (status_change & ATMEL_US_RI)
1282 port->icount.rng++;
1283 if (status_change & ATMEL_US_DSR)
1284 port->icount.dsr++;
1285 if (status_change & ATMEL_US_DCD)
1286 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1287 if (status_change & ATMEL_US_CTS)
1288 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1289
1290 wake_up_interruptible(&port->state->port.delta_msr_wait);
1291 }
1292 }
1293}
1294
1295/*
1296 * Interrupt handler
1297 */
1298static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1299{
1300 struct uart_port *port = dev_id;
1301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1302 unsigned int status, pending, mask, pass_counter = 0;
1303
1304 spin_lock(&atmel_port->lock_suspended);
1305
1306 do {
1307 status = atmel_get_lines_status(port);
1308 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1309 pending = status & mask;
1310 if (!pending)
1311 break;
1312
1313 if (atmel_port->suspended) {
1314 atmel_port->pending |= pending;
1315 atmel_port->pending_status = status;
1316 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1317 pm_system_wakeup();
1318 break;
1319 }
1320
1321 atmel_handle_receive(port, pending);
1322 atmel_handle_status(port, pending, status);
1323 atmel_handle_transmit(port, pending);
1324 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1325
1326 spin_unlock(&atmel_port->lock_suspended);
1327
1328 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1329}
1330
1331static void atmel_release_tx_pdc(struct uart_port *port)
1332{
1333 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1334 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1335
1336 dma_unmap_single(port->dev,
1337 pdc->dma_addr,
1338 pdc->dma_size,
1339 DMA_TO_DEVICE);
1340}
1341
1342/*
1343 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1344 */
1345static void atmel_tx_pdc(struct uart_port *port)
1346{
1347 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1348 struct circ_buf *xmit = &port->state->xmit;
1349 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1350 int count;
1351
1352 /* nothing left to transmit? */
1353 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1354 return;
1355
1356 xmit->tail += pdc->ofs;
1357 xmit->tail &= UART_XMIT_SIZE - 1;
1358
1359 port->icount.tx += pdc->ofs;
1360 pdc->ofs = 0;
1361
1362 /* more to transmit - setup next transfer */
1363
1364 /* disable PDC transmit */
1365 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1366
1367 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1368 dma_sync_single_for_device(port->dev,
1369 pdc->dma_addr,
1370 pdc->dma_size,
1371 DMA_TO_DEVICE);
1372
1373 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1374 pdc->ofs = count;
1375
1376 atmel_uart_writel(port, ATMEL_PDC_TPR,
1377 pdc->dma_addr + xmit->tail);
1378 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1379 /* re-enable PDC transmit */
1380 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1381 /* Enable interrupts */
1382 atmel_uart_writel(port, ATMEL_US_IER,
1383 atmel_port->tx_done_mask);
1384 } else {
1385 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1386 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1387 /* DMA done, stop TX, start RX for RS485 */
1388 atmel_start_rx(port);
1389 }
1390 }
1391
1392 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1393 uart_write_wakeup(port);
1394}
1395
1396static int atmel_prepare_tx_pdc(struct uart_port *port)
1397{
1398 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1399 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1400 struct circ_buf *xmit = &port->state->xmit;
1401
1402 pdc->buf = xmit->buf;
1403 pdc->dma_addr = dma_map_single(port->dev,
1404 pdc->buf,
1405 UART_XMIT_SIZE,
1406 DMA_TO_DEVICE);
1407 pdc->dma_size = UART_XMIT_SIZE;
1408 pdc->ofs = 0;
1409
1410 return 0;
1411}
1412
1413static void atmel_rx_from_ring(struct uart_port *port)
1414{
1415 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1416 struct circ_buf *ring = &atmel_port->rx_ring;
1417 unsigned int flg;
1418 unsigned int status;
1419
1420 while (ring->head != ring->tail) {
1421 struct atmel_uart_char c;
1422
1423 /* Make sure c is loaded after head. */
1424 smp_rmb();
1425
1426 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1427
1428 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1429
1430 port->icount.rx++;
1431 status = c.status;
1432 flg = TTY_NORMAL;
1433
1434 /*
1435 * note that the error handling code is
1436 * out of the main execution path
1437 */
1438 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1439 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1440 if (status & ATMEL_US_RXBRK) {
1441 /* ignore side-effect */
1442 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1443
1444 port->icount.brk++;
1445 if (uart_handle_break(port))
1446 continue;
1447 }
1448 if (status & ATMEL_US_PARE)
1449 port->icount.parity++;
1450 if (status & ATMEL_US_FRAME)
1451 port->icount.frame++;
1452 if (status & ATMEL_US_OVRE)
1453 port->icount.overrun++;
1454
1455 status &= port->read_status_mask;
1456
1457 if (status & ATMEL_US_RXBRK)
1458 flg = TTY_BREAK;
1459 else if (status & ATMEL_US_PARE)
1460 flg = TTY_PARITY;
1461 else if (status & ATMEL_US_FRAME)
1462 flg = TTY_FRAME;
1463 }
1464
1465
1466 if (uart_handle_sysrq_char(port, c.ch))
1467 continue;
1468
1469 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1470 }
1471
1472 /*
1473 * Drop the lock here since it might end up calling
1474 * uart_start(), which takes the lock.
1475 */
1476 spin_unlock(&port->lock);
1477 tty_flip_buffer_push(&port->state->port);
1478 spin_lock(&port->lock);
1479}
1480
1481static void atmel_release_rx_pdc(struct uart_port *port)
1482{
1483 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1484 int i;
1485
1486 for (i = 0; i < 2; i++) {
1487 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1488
1489 dma_unmap_single(port->dev,
1490 pdc->dma_addr,
1491 pdc->dma_size,
1492 DMA_FROM_DEVICE);
1493 kfree(pdc->buf);
1494 }
1495}
1496
1497static void atmel_rx_from_pdc(struct uart_port *port)
1498{
1499 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1500 struct tty_port *tport = &port->state->port;
1501 struct atmel_dma_buffer *pdc;
1502 int rx_idx = atmel_port->pdc_rx_idx;
1503 unsigned int head;
1504 unsigned int tail;
1505 unsigned int count;
1506
1507 do {
1508 /* Reset the UART timeout early so that we don't miss one */
1509 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1510
1511 pdc = &atmel_port->pdc_rx[rx_idx];
1512 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1513 tail = pdc->ofs;
1514
1515 /* If the PDC has switched buffers, RPR won't contain
1516 * any address within the current buffer. Since head
1517 * is unsigned, we just need a one-way comparison to
1518 * find out.
1519 *
1520 * In this case, we just need to consume the entire
1521 * buffer and resubmit it for DMA. This will clear the
1522 * ENDRX bit as well, so that we can safely re-enable
1523 * all interrupts below.
1524 */
1525 head = min(head, pdc->dma_size);
1526
1527 if (likely(head != tail)) {
1528 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1529 pdc->dma_size, DMA_FROM_DEVICE);
1530
1531 /*
1532 * head will only wrap around when we recycle
1533 * the DMA buffer, and when that happens, we
1534 * explicitly set tail to 0. So head will
1535 * always be greater than tail.
1536 */
1537 count = head - tail;
1538
1539 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1540 count);
1541
1542 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1543 pdc->dma_size, DMA_FROM_DEVICE);
1544
1545 port->icount.rx += count;
1546 pdc->ofs = head;
1547 }
1548
1549 /*
1550 * If the current buffer is full, we need to check if
1551 * the next one contains any additional data.
1552 */
1553 if (head >= pdc->dma_size) {
1554 pdc->ofs = 0;
1555 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1556 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1557
1558 rx_idx = !rx_idx;
1559 atmel_port->pdc_rx_idx = rx_idx;
1560 }
1561 } while (head >= pdc->dma_size);
1562
1563 /*
1564 * Drop the lock here since it might end up calling
1565 * uart_start(), which takes the lock.
1566 */
1567 spin_unlock(&port->lock);
1568 tty_flip_buffer_push(tport);
1569 spin_lock(&port->lock);
1570
1571 atmel_uart_writel(port, ATMEL_US_IER,
1572 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1573}
1574
1575static int atmel_prepare_rx_pdc(struct uart_port *port)
1576{
1577 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1578 int i;
1579
1580 for (i = 0; i < 2; i++) {
1581 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1582
1583 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1584 if (pdc->buf == NULL) {
1585 if (i != 0) {
1586 dma_unmap_single(port->dev,
1587 atmel_port->pdc_rx[0].dma_addr,
1588 PDC_BUFFER_SIZE,
1589 DMA_FROM_DEVICE);
1590 kfree(atmel_port->pdc_rx[0].buf);
1591 }
1592 atmel_port->use_pdc_rx = 0;
1593 return -ENOMEM;
1594 }
1595 pdc->dma_addr = dma_map_single(port->dev,
1596 pdc->buf,
1597 PDC_BUFFER_SIZE,
1598 DMA_FROM_DEVICE);
1599 pdc->dma_size = PDC_BUFFER_SIZE;
1600 pdc->ofs = 0;
1601 }
1602
1603 atmel_port->pdc_rx_idx = 0;
1604
1605 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1606 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1607
1608 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1609 atmel_port->pdc_rx[1].dma_addr);
1610 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1611
1612 return 0;
1613}
1614
1615/*
1616 * tasklet handling tty stuff outside the interrupt handler.
1617 */
1618static void atmel_tasklet_rx_func(unsigned long data)
1619{
1620 struct uart_port *port = (struct uart_port *)data;
1621 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1622
1623 /* The interrupt handler does not take the lock */
1624 spin_lock(&port->lock);
1625 atmel_port->schedule_rx(port);
1626 spin_unlock(&port->lock);
1627}
1628
1629static void atmel_tasklet_tx_func(unsigned long data)
1630{
1631 struct uart_port *port = (struct uart_port *)data;
1632 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1633
1634 /* The interrupt handler does not take the lock */
1635 spin_lock(&port->lock);
1636 atmel_port->schedule_tx(port);
1637 spin_unlock(&port->lock);
1638}
1639
1640static void atmel_init_property(struct atmel_uart_port *atmel_port,
1641 struct platform_device *pdev)
1642{
1643 struct device_node *np = pdev->dev.of_node;
1644 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1645
1646 if (np) {
1647 /* DMA/PDC usage specification */
1648 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1649 if (of_property_read_bool(np, "dmas")) {
1650 atmel_port->use_dma_rx = true;
1651 atmel_port->use_pdc_rx = false;
1652 } else {
1653 atmel_port->use_dma_rx = false;
1654 atmel_port->use_pdc_rx = true;
1655 }
1656 } else {
1657 atmel_port->use_dma_rx = false;
1658 atmel_port->use_pdc_rx = false;
1659 }
1660
1661 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1662 if (of_property_read_bool(np, "dmas")) {
1663 atmel_port->use_dma_tx = true;
1664 atmel_port->use_pdc_tx = false;
1665 } else {
1666 atmel_port->use_dma_tx = false;
1667 atmel_port->use_pdc_tx = true;
1668 }
1669 } else {
1670 atmel_port->use_dma_tx = false;
1671 atmel_port->use_pdc_tx = false;
1672 }
1673
1674 } else {
1675 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1676 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1677 atmel_port->use_dma_rx = false;
1678 atmel_port->use_dma_tx = false;
1679 }
1680
1681}
1682
1683static void atmel_init_rs485(struct uart_port *port,
1684 struct platform_device *pdev)
1685{
1686 struct device_node *np = pdev->dev.of_node;
1687 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1688
1689 if (np) {
1690 struct serial_rs485 *rs485conf = &port->rs485;
1691 u32 rs485_delay[2];
1692 /* rs485 properties */
1693 if (of_property_read_u32_array(np, "rs485-rts-delay",
1694 rs485_delay, 2) == 0) {
1695 rs485conf->delay_rts_before_send = rs485_delay[0];
1696 rs485conf->delay_rts_after_send = rs485_delay[1];
1697 rs485conf->flags = 0;
1698 }
1699
1700 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1701 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1702
1703 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1704 NULL))
1705 rs485conf->flags |= SER_RS485_ENABLED;
1706 } else {
1707 port->rs485 = pdata->rs485;
1708 }
1709
1710}
1711
1712static void atmel_set_ops(struct uart_port *port)
1713{
1714 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1715
1716 if (atmel_use_dma_rx(port)) {
1717 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1718 atmel_port->schedule_rx = &atmel_rx_from_dma;
1719 atmel_port->release_rx = &atmel_release_rx_dma;
1720 } else if (atmel_use_pdc_rx(port)) {
1721 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1722 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1723 atmel_port->release_rx = &atmel_release_rx_pdc;
1724 } else {
1725 atmel_port->prepare_rx = NULL;
1726 atmel_port->schedule_rx = &atmel_rx_from_ring;
1727 atmel_port->release_rx = NULL;
1728 }
1729
1730 if (atmel_use_dma_tx(port)) {
1731 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1732 atmel_port->schedule_tx = &atmel_tx_dma;
1733 atmel_port->release_tx = &atmel_release_tx_dma;
1734 } else if (atmel_use_pdc_tx(port)) {
1735 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1736 atmel_port->schedule_tx = &atmel_tx_pdc;
1737 atmel_port->release_tx = &atmel_release_tx_pdc;
1738 } else {
1739 atmel_port->prepare_tx = NULL;
1740 atmel_port->schedule_tx = &atmel_tx_chars;
1741 atmel_port->release_tx = NULL;
1742 }
1743}
1744
1745/*
1746 * Get ip name usart or uart
1747 */
1748static void atmel_get_ip_name(struct uart_port *port)
1749{
1750 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1751 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1752 u32 version;
1753 u32 usart, dbgu_uart, new_uart;
1754 /* ASCII decoding for IP version */
1755 usart = 0x55534152; /* USAR(T) */
1756 dbgu_uart = 0x44424755; /* DBGU */
1757 new_uart = 0x55415254; /* UART */
1758
1759 /*
1760 * Only USART devices from at91sam9260 SOC implement fractional
1761 * baudrate.
1762 */
1763 atmel_port->has_frac_baudrate = false;
1764 atmel_port->has_hw_timer = false;
1765
1766 if (name == new_uart) {
1767 dev_dbg(port->dev, "Uart with hw timer");
1768 atmel_port->has_hw_timer = true;
1769 atmel_port->rtor = ATMEL_UA_RTOR;
1770 } else if (name == usart) {
1771 dev_dbg(port->dev, "Usart\n");
1772 atmel_port->has_frac_baudrate = true;
1773 atmel_port->has_hw_timer = true;
1774 atmel_port->rtor = ATMEL_US_RTOR;
1775 } else if (name == dbgu_uart) {
1776 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1777 } else {
1778 /* fallback for older SoCs: use version field */
1779 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1780 switch (version) {
1781 case 0x302:
1782 case 0x10213:
1783 dev_dbg(port->dev, "This version is usart\n");
1784 atmel_port->has_frac_baudrate = true;
1785 atmel_port->has_hw_timer = true;
1786 atmel_port->rtor = ATMEL_US_RTOR;
1787 break;
1788 case 0x203:
1789 case 0x10202:
1790 dev_dbg(port->dev, "This version is uart\n");
1791 break;
1792 default:
1793 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1794 }
1795 }
1796}
1797
1798/*
1799 * Perform initialization and enable port for reception
1800 */
1801static int atmel_startup(struct uart_port *port)
1802{
1803 struct platform_device *pdev = to_platform_device(port->dev);
1804 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1805 struct tty_struct *tty = port->state->port.tty;
1806 int retval;
1807
1808 /*
1809 * Ensure that no interrupts are enabled otherwise when
1810 * request_irq() is called we could get stuck trying to
1811 * handle an unexpected interrupt
1812 */
1813 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1814 atmel_port->ms_irq_enabled = false;
1815
1816 /*
1817 * Allocate the IRQ
1818 */
1819 retval = request_irq(port->irq, atmel_interrupt,
1820 IRQF_SHARED | IRQF_COND_SUSPEND,
1821 tty ? tty->name : "atmel_serial", port);
1822 if (retval) {
1823 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1824 return retval;
1825 }
1826
1827 atomic_set(&atmel_port->tasklet_shutdown, 0);
1828 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1829 (unsigned long)port);
1830 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1831 (unsigned long)port);
1832
1833 /*
1834 * Initialize DMA (if necessary)
1835 */
1836 atmel_init_property(atmel_port, pdev);
1837 atmel_set_ops(port);
1838
1839 if (atmel_port->prepare_rx) {
1840 retval = atmel_port->prepare_rx(port);
1841 if (retval < 0)
1842 atmel_set_ops(port);
1843 }
1844
1845 if (atmel_port->prepare_tx) {
1846 retval = atmel_port->prepare_tx(port);
1847 if (retval < 0)
1848 atmel_set_ops(port);
1849 }
1850
1851 /*
1852 * Enable FIFO when available
1853 */
1854 if (atmel_port->fifo_size) {
1855 unsigned int txrdym = ATMEL_US_ONE_DATA;
1856 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1857 unsigned int fmr;
1858
1859 atmel_uart_writel(port, ATMEL_US_CR,
1860 ATMEL_US_FIFOEN |
1861 ATMEL_US_RXFCLR |
1862 ATMEL_US_TXFLCLR);
1863
1864 if (atmel_use_dma_tx(port))
1865 txrdym = ATMEL_US_FOUR_DATA;
1866
1867 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1868 if (atmel_port->rts_high &&
1869 atmel_port->rts_low)
1870 fmr |= ATMEL_US_FRTSC |
1871 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1872 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1873
1874 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1875 }
1876
1877 /* Save current CSR for comparison in atmel_tasklet_func() */
1878 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1879
1880 /*
1881 * Finally, enable the serial port
1882 */
1883 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1884 /* enable xmit & rcvr */
1885 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1886
1887 setup_timer(&atmel_port->uart_timer,
1888 atmel_uart_timer_callback,
1889 (unsigned long)port);
1890
1891 if (atmel_use_pdc_rx(port)) {
1892 /* set UART timeout */
1893 if (!atmel_port->has_hw_timer) {
1894 mod_timer(&atmel_port->uart_timer,
1895 jiffies + uart_poll_timeout(port));
1896 /* set USART timeout */
1897 } else {
1898 atmel_uart_writel(port, atmel_port->rtor,
1899 PDC_RX_TIMEOUT);
1900 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1901
1902 atmel_uart_writel(port, ATMEL_US_IER,
1903 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1904 }
1905 /* enable PDC controller */
1906 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1907 } else if (atmel_use_dma_rx(port)) {
1908 /* set UART timeout */
1909 if (!atmel_port->has_hw_timer) {
1910 mod_timer(&atmel_port->uart_timer,
1911 jiffies + uart_poll_timeout(port));
1912 /* set USART timeout */
1913 } else {
1914 atmel_uart_writel(port, atmel_port->rtor,
1915 PDC_RX_TIMEOUT);
1916 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1917
1918 atmel_uart_writel(port, ATMEL_US_IER,
1919 ATMEL_US_TIMEOUT);
1920 }
1921 } else {
1922 /* enable receive only */
1923 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1924 }
1925
1926 return 0;
1927}
1928
1929/*
1930 * Flush any TX data submitted for DMA. Called when the TX circular
1931 * buffer is reset.
1932 */
1933static void atmel_flush_buffer(struct uart_port *port)
1934{
1935 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1936
1937 if (atmel_use_pdc_tx(port)) {
1938 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1939 atmel_port->pdc_tx.ofs = 0;
1940 }
1941 /*
1942 * in uart_flush_buffer(), the xmit circular buffer has just
1943 * been cleared, so we have to reset tx_len accordingly.
1944 */
1945 atmel_port->tx_len = 0;
1946}
1947
1948/*
1949 * Disable the port
1950 */
1951static void atmel_shutdown(struct uart_port *port)
1952{
1953 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1954
1955 /* Disable modem control lines interrupts */
1956 atmel_disable_ms(port);
1957
1958 /* Disable interrupts at device level */
1959 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1960
1961 /* Prevent spurious interrupts from scheduling the tasklet */
1962 atomic_inc(&atmel_port->tasklet_shutdown);
1963
1964 /*
1965 * Prevent any tasklets being scheduled during
1966 * cleanup
1967 */
1968 del_timer_sync(&atmel_port->uart_timer);
1969
1970 /* Make sure that no interrupt is on the fly */
1971 synchronize_irq(port->irq);
1972
1973 /*
1974 * Clear out any scheduled tasklets before
1975 * we destroy the buffers
1976 */
1977 tasklet_kill(&atmel_port->tasklet_rx);
1978 tasklet_kill(&atmel_port->tasklet_tx);
1979
1980 /*
1981 * Ensure everything is stopped and
1982 * disable port and break condition.
1983 */
1984 atmel_stop_rx(port);
1985 atmel_stop_tx(port);
1986
1987 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1988
1989 /*
1990 * Shut-down the DMA.
1991 */
1992 if (atmel_port->release_rx)
1993 atmel_port->release_rx(port);
1994 if (atmel_port->release_tx)
1995 atmel_port->release_tx(port);
1996
1997 /*
1998 * Reset ring buffer pointers
1999 */
2000 atmel_port->rx_ring.head = 0;
2001 atmel_port->rx_ring.tail = 0;
2002
2003 /*
2004 * Free the interrupts
2005 */
2006 free_irq(port->irq, port);
2007
2008 atmel_flush_buffer(port);
2009}
2010
2011/*
2012 * Power / Clock management.
2013 */
2014static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2015 unsigned int oldstate)
2016{
2017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2018
2019 switch (state) {
2020 case 0:
2021 /*
2022 * Enable the peripheral clock for this serial port.
2023 * This is called on uart_open() or a resume event.
2024 */
2025 clk_prepare_enable(atmel_port->clk);
2026
2027 /* re-enable interrupts if we disabled some on suspend */
2028 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2029 break;
2030 case 3:
2031 /* Back up the interrupt mask and disable all interrupts */
2032 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2033 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2034
2035 /*
2036 * Disable the peripheral clock for this serial port.
2037 * This is called on uart_close() or a suspend event.
2038 */
2039 clk_disable_unprepare(atmel_port->clk);
2040 break;
2041 default:
2042 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2043 }
2044}
2045
2046/*
2047 * Change the port parameters
2048 */
2049static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2050 struct ktermios *old)
2051{
2052 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2053 unsigned long flags;
2054 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2055
2056 /* save the current mode register */
2057 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2058
2059 /* reset the mode, clock divisor, parity, stop bits and data size */
2060 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2061 ATMEL_US_PAR | ATMEL_US_USMODE);
2062
2063 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2064
2065 /* byte size */
2066 switch (termios->c_cflag & CSIZE) {
2067 case CS5:
2068 mode |= ATMEL_US_CHRL_5;
2069 break;
2070 case CS6:
2071 mode |= ATMEL_US_CHRL_6;
2072 break;
2073 case CS7:
2074 mode |= ATMEL_US_CHRL_7;
2075 break;
2076 default:
2077 mode |= ATMEL_US_CHRL_8;
2078 break;
2079 }
2080
2081 /* stop bits */
2082 if (termios->c_cflag & CSTOPB)
2083 mode |= ATMEL_US_NBSTOP_2;
2084
2085 /* parity */
2086 if (termios->c_cflag & PARENB) {
2087 /* Mark or Space parity */
2088 if (termios->c_cflag & CMSPAR) {
2089 if (termios->c_cflag & PARODD)
2090 mode |= ATMEL_US_PAR_MARK;
2091 else
2092 mode |= ATMEL_US_PAR_SPACE;
2093 } else if (termios->c_cflag & PARODD)
2094 mode |= ATMEL_US_PAR_ODD;
2095 else
2096 mode |= ATMEL_US_PAR_EVEN;
2097 } else
2098 mode |= ATMEL_US_PAR_NONE;
2099
2100 spin_lock_irqsave(&port->lock, flags);
2101
2102 port->read_status_mask = ATMEL_US_OVRE;
2103 if (termios->c_iflag & INPCK)
2104 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2105 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2106 port->read_status_mask |= ATMEL_US_RXBRK;
2107
2108 if (atmel_use_pdc_rx(port))
2109 /* need to enable error interrupts */
2110 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2111
2112 /*
2113 * Characters to ignore
2114 */
2115 port->ignore_status_mask = 0;
2116 if (termios->c_iflag & IGNPAR)
2117 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2118 if (termios->c_iflag & IGNBRK) {
2119 port->ignore_status_mask |= ATMEL_US_RXBRK;
2120 /*
2121 * If we're ignoring parity and break indicators,
2122 * ignore overruns too (for real raw support).
2123 */
2124 if (termios->c_iflag & IGNPAR)
2125 port->ignore_status_mask |= ATMEL_US_OVRE;
2126 }
2127 /* TODO: Ignore all characters if CREAD is set.*/
2128
2129 /* update the per-port timeout */
2130 uart_update_timeout(port, termios->c_cflag, baud);
2131
2132 /*
2133 * save/disable interrupts. The tty layer will ensure that the
2134 * transmitter is empty if requested by the caller, so there's
2135 * no need to wait for it here.
2136 */
2137 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2138 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2139
2140 /* disable receiver and transmitter */
2141 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2142
2143 /* mode */
2144 if (port->rs485.flags & SER_RS485_ENABLED) {
2145 atmel_uart_writel(port, ATMEL_US_TTGR,
2146 port->rs485.delay_rts_after_send);
2147 mode |= ATMEL_US_USMODE_RS485;
2148 } else if (termios->c_cflag & CRTSCTS) {
2149 /* RS232 with hardware handshake (RTS/CTS) */
2150 if (atmel_use_fifo(port) &&
2151 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2152 /*
2153 * with ATMEL_US_USMODE_HWHS set, the controller will
2154 * be able to drive the RTS pin high/low when the RX
2155 * FIFO is above RXFTHRES/below RXFTHRES2.
2156 * It will also disable the transmitter when the CTS
2157 * pin is high.
2158 * This mode is not activated if CTS pin is a GPIO
2159 * because in this case, the transmitter is always
2160 * disabled (there must be an internal pull-up
2161 * responsible for this behaviour).
2162 * If the RTS pin is a GPIO, the controller won't be
2163 * able to drive it according to the FIFO thresholds,
2164 * but it will be handled by the driver.
2165 */
2166 mode |= ATMEL_US_USMODE_HWHS;
2167 } else {
2168 /*
2169 * For platforms without FIFO, the flow control is
2170 * handled by the driver.
2171 */
2172 mode |= ATMEL_US_USMODE_NORMAL;
2173 }
2174 } else {
2175 /* RS232 without hadware handshake */
2176 mode |= ATMEL_US_USMODE_NORMAL;
2177 }
2178
2179 /* set the mode, clock divisor, parity, stop bits and data size */
2180 atmel_uart_writel(port, ATMEL_US_MR, mode);
2181
2182 /*
2183 * when switching the mode, set the RTS line state according to the
2184 * new mode, otherwise keep the former state
2185 */
2186 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2187 unsigned int rts_state;
2188
2189 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2190 /* let the hardware control the RTS line */
2191 rts_state = ATMEL_US_RTSDIS;
2192 } else {
2193 /* force RTS line to low level */
2194 rts_state = ATMEL_US_RTSEN;
2195 }
2196
2197 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2198 }
2199
2200 /*
2201 * Set the baud rate:
2202 * Fractional baudrate allows to setup output frequency more
2203 * accurately. This feature is enabled only when using normal mode.
2204 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2205 * Currently, OVER is always set to 0 so we get
2206 * baudrate = selected clock / (16 * (CD + FP / 8))
2207 * then
2208 * 8 CD + FP = selected clock / (2 * baudrate)
2209 */
2210 if (atmel_port->has_frac_baudrate &&
2211 (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) {
2212 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2213 cd = div >> 3;
2214 fp = div & ATMEL_US_FP_MASK;
2215 } else {
2216 cd = uart_get_divisor(port, baud);
2217 }
2218
2219 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2220 cd /= 8;
2221 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2222 }
2223 quot = cd | fp << ATMEL_US_FP_OFFSET;
2224
2225 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2226 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2227 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2228
2229 /* restore interrupts */
2230 atmel_uart_writel(port, ATMEL_US_IER, imr);
2231
2232 /* CTS flow-control and modem-status interrupts */
2233 if (UART_ENABLE_MS(port, termios->c_cflag))
2234 atmel_enable_ms(port);
2235 else
2236 atmel_disable_ms(port);
2237
2238 spin_unlock_irqrestore(&port->lock, flags);
2239}
2240
2241static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2242{
2243 if (termios->c_line == N_PPS) {
2244 port->flags |= UPF_HARDPPS_CD;
2245 spin_lock_irq(&port->lock);
2246 atmel_enable_ms(port);
2247 spin_unlock_irq(&port->lock);
2248 } else {
2249 port->flags &= ~UPF_HARDPPS_CD;
2250 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2251 spin_lock_irq(&port->lock);
2252 atmel_disable_ms(port);
2253 spin_unlock_irq(&port->lock);
2254 }
2255 }
2256}
2257
2258/*
2259 * Return string describing the specified port
2260 */
2261static const char *atmel_type(struct uart_port *port)
2262{
2263 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2264}
2265
2266/*
2267 * Release the memory region(s) being used by 'port'.
2268 */
2269static void atmel_release_port(struct uart_port *port)
2270{
2271 struct platform_device *pdev = to_platform_device(port->dev);
2272 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2273
2274 release_mem_region(port->mapbase, size);
2275
2276 if (port->flags & UPF_IOREMAP) {
2277 iounmap(port->membase);
2278 port->membase = NULL;
2279 }
2280}
2281
2282/*
2283 * Request the memory region(s) being used by 'port'.
2284 */
2285static int atmel_request_port(struct uart_port *port)
2286{
2287 struct platform_device *pdev = to_platform_device(port->dev);
2288 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2289
2290 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2291 return -EBUSY;
2292
2293 if (port->flags & UPF_IOREMAP) {
2294 port->membase = ioremap(port->mapbase, size);
2295 if (port->membase == NULL) {
2296 release_mem_region(port->mapbase, size);
2297 return -ENOMEM;
2298 }
2299 }
2300
2301 return 0;
2302}
2303
2304/*
2305 * Configure/autoconfigure the port.
2306 */
2307static void atmel_config_port(struct uart_port *port, int flags)
2308{
2309 if (flags & UART_CONFIG_TYPE) {
2310 port->type = PORT_ATMEL;
2311 atmel_request_port(port);
2312 }
2313}
2314
2315/*
2316 * Verify the new serial_struct (for TIOCSSERIAL).
2317 */
2318static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2319{
2320 int ret = 0;
2321 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2322 ret = -EINVAL;
2323 if (port->irq != ser->irq)
2324 ret = -EINVAL;
2325 if (ser->io_type != SERIAL_IO_MEM)
2326 ret = -EINVAL;
2327 if (port->uartclk / 16 != ser->baud_base)
2328 ret = -EINVAL;
2329 if (port->mapbase != (unsigned long)ser->iomem_base)
2330 ret = -EINVAL;
2331 if (port->iobase != ser->port)
2332 ret = -EINVAL;
2333 if (ser->hub6 != 0)
2334 ret = -EINVAL;
2335 return ret;
2336}
2337
2338#ifdef CONFIG_CONSOLE_POLL
2339static int atmel_poll_get_char(struct uart_port *port)
2340{
2341 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2342 cpu_relax();
2343
2344 return atmel_uart_read_char(port);
2345}
2346
2347static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2348{
2349 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2350 cpu_relax();
2351
2352 atmel_uart_write_char(port, ch);
2353}
2354#endif
2355
2356static const struct uart_ops atmel_pops = {
2357 .tx_empty = atmel_tx_empty,
2358 .set_mctrl = atmel_set_mctrl,
2359 .get_mctrl = atmel_get_mctrl,
2360 .stop_tx = atmel_stop_tx,
2361 .start_tx = atmel_start_tx,
2362 .stop_rx = atmel_stop_rx,
2363 .enable_ms = atmel_enable_ms,
2364 .break_ctl = atmel_break_ctl,
2365 .startup = atmel_startup,
2366 .shutdown = atmel_shutdown,
2367 .flush_buffer = atmel_flush_buffer,
2368 .set_termios = atmel_set_termios,
2369 .set_ldisc = atmel_set_ldisc,
2370 .type = atmel_type,
2371 .release_port = atmel_release_port,
2372 .request_port = atmel_request_port,
2373 .config_port = atmel_config_port,
2374 .verify_port = atmel_verify_port,
2375 .pm = atmel_serial_pm,
2376#ifdef CONFIG_CONSOLE_POLL
2377 .poll_get_char = atmel_poll_get_char,
2378 .poll_put_char = atmel_poll_put_char,
2379#endif
2380};
2381
2382/*
2383 * Configure the port from the platform device resource info.
2384 */
2385static int atmel_init_port(struct atmel_uart_port *atmel_port,
2386 struct platform_device *pdev)
2387{
2388 int ret;
2389 struct uart_port *port = &atmel_port->uart;
2390 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2391
2392 atmel_init_property(atmel_port, pdev);
2393 atmel_set_ops(port);
2394
2395 atmel_init_rs485(port, pdev);
2396
2397 port->iotype = UPIO_MEM;
2398 port->flags = UPF_BOOT_AUTOCONF;
2399 port->ops = &atmel_pops;
2400 port->fifosize = 1;
2401 port->dev = &pdev->dev;
2402 port->mapbase = pdev->resource[0].start;
2403 port->irq = pdev->resource[1].start;
2404 port->rs485_config = atmel_config_rs485;
2405
2406 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2407
2408 if (pdata && pdata->regs) {
2409 /* Already mapped by setup code */
2410 port->membase = pdata->regs;
2411 } else {
2412 port->flags |= UPF_IOREMAP;
2413 port->membase = NULL;
2414 }
2415
2416 /* for console, the clock could already be configured */
2417 if (!atmel_port->clk) {
2418 atmel_port->clk = clk_get(&pdev->dev, "usart");
2419 if (IS_ERR(atmel_port->clk)) {
2420 ret = PTR_ERR(atmel_port->clk);
2421 atmel_port->clk = NULL;
2422 return ret;
2423 }
2424 ret = clk_prepare_enable(atmel_port->clk);
2425 if (ret) {
2426 clk_put(atmel_port->clk);
2427 atmel_port->clk = NULL;
2428 return ret;
2429 }
2430 port->uartclk = clk_get_rate(atmel_port->clk);
2431 clk_disable_unprepare(atmel_port->clk);
2432 /* only enable clock when USART is in use */
2433 }
2434
2435 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2436 if (port->rs485.flags & SER_RS485_ENABLED)
2437 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2438 else if (atmel_use_pdc_tx(port)) {
2439 port->fifosize = PDC_BUFFER_SIZE;
2440 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2441 } else {
2442 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2443 }
2444
2445 return 0;
2446}
2447
2448struct platform_device *atmel_default_console_device; /* the serial console device */
2449
2450#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2451static void atmel_console_putchar(struct uart_port *port, int ch)
2452{
2453 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2454 cpu_relax();
2455 atmel_uart_write_char(port, ch);
2456}
2457
2458/*
2459 * Interrupts are disabled on entering
2460 */
2461static void atmel_console_write(struct console *co, const char *s, u_int count)
2462{
2463 struct uart_port *port = &atmel_ports[co->index].uart;
2464 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2465 unsigned int status, imr;
2466 unsigned int pdc_tx;
2467
2468 /*
2469 * First, save IMR and then disable interrupts
2470 */
2471 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2472 atmel_uart_writel(port, ATMEL_US_IDR,
2473 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2474
2475 /* Store PDC transmit status and disable it */
2476 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2477 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2478
2479 /* Make sure that tx path is actually able to send characters */
2480 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2481
2482 uart_console_write(port, s, count, atmel_console_putchar);
2483
2484 /*
2485 * Finally, wait for transmitter to become empty
2486 * and restore IMR
2487 */
2488 do {
2489 status = atmel_uart_readl(port, ATMEL_US_CSR);
2490 } while (!(status & ATMEL_US_TXRDY));
2491
2492 /* Restore PDC transmit status */
2493 if (pdc_tx)
2494 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2495
2496 /* set interrupts back the way they were */
2497 atmel_uart_writel(port, ATMEL_US_IER, imr);
2498}
2499
2500/*
2501 * If the port was already initialised (eg, by a boot loader),
2502 * try to determine the current setup.
2503 */
2504static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2505 int *parity, int *bits)
2506{
2507 unsigned int mr, quot;
2508
2509 /*
2510 * If the baud rate generator isn't running, the port wasn't
2511 * initialized by the boot loader.
2512 */
2513 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2514 if (!quot)
2515 return;
2516
2517 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2518 if (mr == ATMEL_US_CHRL_8)
2519 *bits = 8;
2520 else
2521 *bits = 7;
2522
2523 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2524 if (mr == ATMEL_US_PAR_EVEN)
2525 *parity = 'e';
2526 else if (mr == ATMEL_US_PAR_ODD)
2527 *parity = 'o';
2528
2529 /*
2530 * The serial core only rounds down when matching this to a
2531 * supported baud rate. Make sure we don't end up slightly
2532 * lower than one of those, as it would make us fall through
2533 * to a much lower baud rate than we really want.
2534 */
2535 *baud = port->uartclk / (16 * (quot - 1));
2536}
2537
2538static int __init atmel_console_setup(struct console *co, char *options)
2539{
2540 int ret;
2541 struct uart_port *port = &atmel_ports[co->index].uart;
2542 int baud = 115200;
2543 int bits = 8;
2544 int parity = 'n';
2545 int flow = 'n';
2546
2547 if (port->membase == NULL) {
2548 /* Port not initialized yet - delay setup */
2549 return -ENODEV;
2550 }
2551
2552 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2553 if (ret)
2554 return ret;
2555
2556 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2557 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2558 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2559
2560 if (options)
2561 uart_parse_options(options, &baud, &parity, &bits, &flow);
2562 else
2563 atmel_console_get_options(port, &baud, &parity, &bits);
2564
2565 return uart_set_options(port, co, baud, parity, bits, flow);
2566}
2567
2568static struct uart_driver atmel_uart;
2569
2570static struct console atmel_console = {
2571 .name = ATMEL_DEVICENAME,
2572 .write = atmel_console_write,
2573 .device = uart_console_device,
2574 .setup = atmel_console_setup,
2575 .flags = CON_PRINTBUFFER,
2576 .index = -1,
2577 .data = &atmel_uart,
2578};
2579
2580#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2581
2582/*
2583 * Early console initialization (before VM subsystem initialized).
2584 */
2585static int __init atmel_console_init(void)
2586{
2587 int ret;
2588 if (atmel_default_console_device) {
2589 struct atmel_uart_data *pdata =
2590 dev_get_platdata(&atmel_default_console_device->dev);
2591 int id = pdata->num;
2592 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2593
2594 atmel_port->backup_imr = 0;
2595 atmel_port->uart.line = id;
2596
2597 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2598 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2599 if (ret)
2600 return ret;
2601 register_console(&atmel_console);
2602 }
2603
2604 return 0;
2605}
2606
2607console_initcall(atmel_console_init);
2608
2609/*
2610 * Late console initialization.
2611 */
2612static int __init atmel_late_console_init(void)
2613{
2614 if (atmel_default_console_device
2615 && !(atmel_console.flags & CON_ENABLED))
2616 register_console(&atmel_console);
2617
2618 return 0;
2619}
2620
2621core_initcall(atmel_late_console_init);
2622
2623static inline bool atmel_is_console_port(struct uart_port *port)
2624{
2625 return port->cons && port->cons->index == port->line;
2626}
2627
2628#else
2629#define ATMEL_CONSOLE_DEVICE NULL
2630
2631static inline bool atmel_is_console_port(struct uart_port *port)
2632{
2633 return false;
2634}
2635#endif
2636
2637static struct uart_driver atmel_uart = {
2638 .owner = THIS_MODULE,
2639 .driver_name = "atmel_serial",
2640 .dev_name = ATMEL_DEVICENAME,
2641 .major = SERIAL_ATMEL_MAJOR,
2642 .minor = MINOR_START,
2643 .nr = ATMEL_MAX_UART,
2644 .cons = ATMEL_CONSOLE_DEVICE,
2645};
2646
2647#ifdef CONFIG_PM
2648static bool atmel_serial_clk_will_stop(void)
2649{
2650#ifdef CONFIG_ARCH_AT91
2651 return at91_suspend_entering_slow_clock();
2652#else
2653 return false;
2654#endif
2655}
2656
2657static int atmel_serial_suspend(struct platform_device *pdev,
2658 pm_message_t state)
2659{
2660 struct uart_port *port = platform_get_drvdata(pdev);
2661 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2662
2663 if (atmel_is_console_port(port) && console_suspend_enabled) {
2664 /* Drain the TX shifter */
2665 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2666 ATMEL_US_TXEMPTY))
2667 cpu_relax();
2668 }
2669
2670 /* we can not wake up if we're running on slow clock */
2671 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2672 if (atmel_serial_clk_will_stop()) {
2673 unsigned long flags;
2674
2675 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2676 atmel_port->suspended = true;
2677 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2678 device_set_wakeup_enable(&pdev->dev, 0);
2679 }
2680
2681 uart_suspend_port(&atmel_uart, port);
2682
2683 return 0;
2684}
2685
2686static int atmel_serial_resume(struct platform_device *pdev)
2687{
2688 struct uart_port *port = platform_get_drvdata(pdev);
2689 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2690 unsigned long flags;
2691
2692 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2693 if (atmel_port->pending) {
2694 atmel_handle_receive(port, atmel_port->pending);
2695 atmel_handle_status(port, atmel_port->pending,
2696 atmel_port->pending_status);
2697 atmel_handle_transmit(port, atmel_port->pending);
2698 atmel_port->pending = 0;
2699 }
2700 atmel_port->suspended = false;
2701 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2702
2703 uart_resume_port(&atmel_uart, port);
2704 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2705
2706 return 0;
2707}
2708#else
2709#define atmel_serial_suspend NULL
2710#define atmel_serial_resume NULL
2711#endif
2712
2713static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2714 struct platform_device *pdev)
2715{
2716 atmel_port->fifo_size = 0;
2717 atmel_port->rts_low = 0;
2718 atmel_port->rts_high = 0;
2719
2720 if (of_property_read_u32(pdev->dev.of_node,
2721 "atmel,fifo-size",
2722 &atmel_port->fifo_size))
2723 return;
2724
2725 if (!atmel_port->fifo_size)
2726 return;
2727
2728 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2729 atmel_port->fifo_size = 0;
2730 dev_err(&pdev->dev, "Invalid FIFO size\n");
2731 return;
2732 }
2733
2734 /*
2735 * 0 <= rts_low <= rts_high <= fifo_size
2736 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2737 * to flush their internal TX FIFO, commonly up to 16 data, before
2738 * actually stopping to send new data. So we try to set the RTS High
2739 * Threshold to a reasonably high value respecting this 16 data
2740 * empirical rule when possible.
2741 */
2742 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2743 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2744 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2745 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2746
2747 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2748 atmel_port->fifo_size);
2749 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2750 atmel_port->rts_high);
2751 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2752 atmel_port->rts_low);
2753}
2754
2755static int atmel_serial_probe(struct platform_device *pdev)
2756{
2757 struct atmel_uart_port *atmel_port;
2758 struct device_node *np = pdev->dev.of_node;
2759 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2760 void *data;
2761 int ret = -ENODEV;
2762 bool rs485_enabled;
2763
2764 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2765
2766 if (np)
2767 ret = of_alias_get_id(np, "serial");
2768 else
2769 if (pdata)
2770 ret = pdata->num;
2771
2772 if (ret < 0)
2773 /* port id not found in platform data nor device-tree aliases:
2774 * auto-enumerate it */
2775 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2776
2777 if (ret >= ATMEL_MAX_UART) {
2778 ret = -ENODEV;
2779 goto err;
2780 }
2781
2782 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2783 /* port already in use */
2784 ret = -EBUSY;
2785 goto err;
2786 }
2787
2788 atmel_port = &atmel_ports[ret];
2789 atmel_port->backup_imr = 0;
2790 atmel_port->uart.line = ret;
2791 atmel_serial_probe_fifos(atmel_port, pdev);
2792
2793 atomic_set(&atmel_port->tasklet_shutdown, 0);
2794 spin_lock_init(&atmel_port->lock_suspended);
2795
2796 ret = atmel_init_port(atmel_port, pdev);
2797 if (ret)
2798 goto err_clear_bit;
2799
2800 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2801 if (IS_ERR(atmel_port->gpios)) {
2802 ret = PTR_ERR(atmel_port->gpios);
2803 goto err_clear_bit;
2804 }
2805
2806 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2807 ret = -ENOMEM;
2808 data = kmalloc(sizeof(struct atmel_uart_char)
2809 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2810 if (!data)
2811 goto err_alloc_ring;
2812 atmel_port->rx_ring.buf = data;
2813 }
2814
2815 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2816
2817 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2818 if (ret)
2819 goto err_add_port;
2820
2821#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2822 if (atmel_is_console_port(&atmel_port->uart)
2823 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2824 /*
2825 * The serial core enabled the clock for us, so undo
2826 * the clk_prepare_enable() in atmel_console_setup()
2827 */
2828 clk_disable_unprepare(atmel_port->clk);
2829 }
2830#endif
2831
2832 device_init_wakeup(&pdev->dev, 1);
2833 platform_set_drvdata(pdev, atmel_port);
2834
2835 /*
2836 * The peripheral clock has been disabled by atmel_init_port():
2837 * enable it before accessing I/O registers
2838 */
2839 clk_prepare_enable(atmel_port->clk);
2840
2841 if (rs485_enabled) {
2842 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2843 ATMEL_US_USMODE_NORMAL);
2844 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2845 ATMEL_US_RTSEN);
2846 }
2847
2848 /*
2849 * Get port name of usart or uart
2850 */
2851 atmel_get_ip_name(&atmel_port->uart);
2852
2853 /*
2854 * The peripheral clock can now safely be disabled till the port
2855 * is used
2856 */
2857 clk_disable_unprepare(atmel_port->clk);
2858
2859 return 0;
2860
2861err_add_port:
2862 kfree(atmel_port->rx_ring.buf);
2863 atmel_port->rx_ring.buf = NULL;
2864err_alloc_ring:
2865 if (!atmel_is_console_port(&atmel_port->uart)) {
2866 clk_put(atmel_port->clk);
2867 atmel_port->clk = NULL;
2868 }
2869err_clear_bit:
2870 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2871err:
2872 return ret;
2873}
2874
2875/*
2876 * Even if the driver is not modular, it makes sense to be able to
2877 * unbind a device: there can be many bound devices, and there are
2878 * situations where dynamic binding and unbinding can be useful.
2879 *
2880 * For example, a connected device can require a specific firmware update
2881 * protocol that needs bitbanging on IO lines, but use the regular serial
2882 * port in the normal case.
2883 */
2884static int atmel_serial_remove(struct platform_device *pdev)
2885{
2886 struct uart_port *port = platform_get_drvdata(pdev);
2887 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2888 int ret = 0;
2889
2890 tasklet_kill(&atmel_port->tasklet_rx);
2891 tasklet_kill(&atmel_port->tasklet_tx);
2892
2893 device_init_wakeup(&pdev->dev, 0);
2894
2895 ret = uart_remove_one_port(&atmel_uart, port);
2896
2897 kfree(atmel_port->rx_ring.buf);
2898
2899 /* "port" is allocated statically, so we shouldn't free it */
2900
2901 clear_bit(port->line, atmel_ports_in_use);
2902
2903 clk_put(atmel_port->clk);
2904 atmel_port->clk = NULL;
2905
2906 return ret;
2907}
2908
2909static struct platform_driver atmel_serial_driver = {
2910 .probe = atmel_serial_probe,
2911 .remove = atmel_serial_remove,
2912 .suspend = atmel_serial_suspend,
2913 .resume = atmel_serial_resume,
2914 .driver = {
2915 .name = "atmel_usart",
2916 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2917 },
2918};
2919
2920static int __init atmel_serial_init(void)
2921{
2922 int ret;
2923
2924 ret = uart_register_driver(&atmel_uart);
2925 if (ret)
2926 return ret;
2927
2928 ret = platform_driver_register(&atmel_serial_driver);
2929 if (ret)
2930 uart_unregister_driver(&atmel_uart);
2931
2932 return ret;
2933}
2934device_initcall(atmel_serial_init);