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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11#include <linux/circ_buf.h>
12#include <linux/tty.h>
13#include <linux/ioport.h>
14#include <linux/slab.h>
15#include <linux/init.h>
16#include <linux/serial.h>
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/console.h>
20#include <linux/sysrq.h>
21#include <linux/tty_flip.h>
22#include <linux/platform_device.h>
23#include <linux/of.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/atmel_pdc.h>
27#include <linux/uaccess.h>
28#include <linux/platform_data/atmel.h>
29#include <linux/timer.h>
30#include <linux/err.h>
31#include <linux/irq.h>
32#include <linux/suspend.h>
33#include <linux/mm.h>
34#include <linux/io.h>
35
36#include <asm/div64.h>
37#include <asm/ioctls.h>
38
39#define PDC_BUFFER_SIZE 512
40/* Revisit: We should calculate this based on the actual port settings */
41#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
42
43/* The minium number of data FIFOs should be able to contain */
44#define ATMEL_MIN_FIFO_SIZE 8
45/*
46 * These two offsets are substracted from the RX FIFO size to define the RTS
47 * high and low thresholds
48 */
49#define ATMEL_RTS_HIGH_OFFSET 16
50#define ATMEL_RTS_LOW_OFFSET 20
51
52#include <linux/serial_core.h>
53
54#include "serial_mctrl_gpio.h"
55#include "atmel_serial.h"
56
57static void atmel_start_rx(struct uart_port *port);
58static void atmel_stop_rx(struct uart_port *port);
59
60#ifdef CONFIG_SERIAL_ATMEL_TTYAT
61
62/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
63 * should coexist with the 8250 driver, such as if we have an external 16C550
64 * UART. */
65#define SERIAL_ATMEL_MAJOR 204
66#define MINOR_START 154
67#define ATMEL_DEVICENAME "ttyAT"
68
69#else
70
71/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
72 * name, but it is legally reserved for the 8250 driver. */
73#define SERIAL_ATMEL_MAJOR TTY_MAJOR
74#define MINOR_START 64
75#define ATMEL_DEVICENAME "ttyS"
76
77#endif
78
79#define ATMEL_ISR_PASS_LIMIT 256
80
81struct atmel_dma_buffer {
82 unsigned char *buf;
83 dma_addr_t dma_addr;
84 unsigned int dma_size;
85 unsigned int ofs;
86};
87
88struct atmel_uart_char {
89 u16 status;
90 u16 ch;
91};
92
93/*
94 * Be careful, the real size of the ring buffer is
95 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
96 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
97 * DMA mode.
98 */
99#define ATMEL_SERIAL_RINGSIZE 1024
100
101/*
102 * at91: 6 USARTs and one DBGU port (SAM9260)
103 * samx7: 3 USARTs and 5 UARTs
104 */
105#define ATMEL_MAX_UART 8
106
107/*
108 * We wrap our port structure around the generic uart_port.
109 */
110struct atmel_uart_port {
111 struct uart_port uart; /* uart */
112 struct clk *clk; /* uart clock */
113 struct clk *gclk; /* uart generic clock */
114 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
115 u32 backup_imr; /* IMR saved during suspend */
116 int break_active; /* break being received */
117
118 bool use_dma_rx; /* enable DMA receiver */
119 bool use_pdc_rx; /* enable PDC receiver */
120 short pdc_rx_idx; /* current PDC RX buffer */
121 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
122
123 bool use_dma_tx; /* enable DMA transmitter */
124 bool use_pdc_tx; /* enable PDC transmitter */
125 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
126
127 spinlock_t lock_tx; /* port lock */
128 spinlock_t lock_rx; /* port lock */
129 struct dma_chan *chan_tx;
130 struct dma_chan *chan_rx;
131 struct dma_async_tx_descriptor *desc_tx;
132 struct dma_async_tx_descriptor *desc_rx;
133 dma_cookie_t cookie_tx;
134 dma_cookie_t cookie_rx;
135 struct scatterlist sg_tx;
136 struct scatterlist sg_rx;
137 struct tasklet_struct tasklet_rx;
138 struct tasklet_struct tasklet_tx;
139 atomic_t tasklet_shutdown;
140 unsigned int irq_status_prev;
141 unsigned int tx_len;
142
143 struct circ_buf rx_ring;
144
145 struct mctrl_gpios *gpios;
146 u32 backup_mode; /* MR saved during iso7816 operations */
147 u32 backup_brgr; /* BRGR saved during iso7816 operations */
148 unsigned int tx_done_mask;
149 u32 fifo_size;
150 u32 rts_high;
151 u32 rts_low;
152 bool ms_irq_enabled;
153 u32 rtor; /* address of receiver timeout register if it exists */
154 bool is_usart;
155 bool has_frac_baudrate;
156 bool has_hw_timer;
157 struct timer_list uart_timer;
158
159 bool tx_stopped;
160 bool suspended;
161 unsigned int pending;
162 unsigned int pending_status;
163 spinlock_t lock_suspended;
164
165 bool hd_start_rx; /* can start RX during half-duplex operation */
166
167 /* ISO7816 */
168 unsigned int fidi_min;
169 unsigned int fidi_max;
170
171 struct {
172 u32 cr;
173 u32 mr;
174 u32 imr;
175 u32 brgr;
176 u32 rtor;
177 u32 ttgr;
178 u32 fmr;
179 u32 fimr;
180 } cache;
181
182 int (*prepare_rx)(struct uart_port *port);
183 int (*prepare_tx)(struct uart_port *port);
184 void (*schedule_rx)(struct uart_port *port);
185 void (*schedule_tx)(struct uart_port *port);
186 void (*release_rx)(struct uart_port *port);
187 void (*release_tx)(struct uart_port *port);
188};
189
190static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
191static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
192
193#if defined(CONFIG_OF)
194static const struct of_device_id atmel_serial_dt_ids[] = {
195 { .compatible = "atmel,at91rm9200-usart-serial" },
196 { /* sentinel */ }
197};
198#endif
199
200static inline struct atmel_uart_port *
201to_atmel_uart_port(struct uart_port *uart)
202{
203 return container_of(uart, struct atmel_uart_port, uart);
204}
205
206static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
207{
208 return __raw_readl(port->membase + reg);
209}
210
211static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
212{
213 __raw_writel(value, port->membase + reg);
214}
215
216static inline u8 atmel_uart_read_char(struct uart_port *port)
217{
218 return __raw_readb(port->membase + ATMEL_US_RHR);
219}
220
221static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
222{
223 __raw_writeb(value, port->membase + ATMEL_US_THR);
224}
225
226static inline int atmel_uart_is_half_duplex(struct uart_port *port)
227{
228 return ((port->rs485.flags & SER_RS485_ENABLED) &&
229 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
230 (port->iso7816.flags & SER_ISO7816_ENABLED);
231}
232
233static inline int atmel_error_rate(int desired_value, int actual_value)
234{
235 return 100 - (desired_value * 100) / actual_value;
236}
237
238#ifdef CONFIG_SERIAL_ATMEL_PDC
239static bool atmel_use_pdc_rx(struct uart_port *port)
240{
241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
242
243 return atmel_port->use_pdc_rx;
244}
245
246static bool atmel_use_pdc_tx(struct uart_port *port)
247{
248 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
249
250 return atmel_port->use_pdc_tx;
251}
252#else
253static bool atmel_use_pdc_rx(struct uart_port *port)
254{
255 return false;
256}
257
258static bool atmel_use_pdc_tx(struct uart_port *port)
259{
260 return false;
261}
262#endif
263
264static bool atmel_use_dma_tx(struct uart_port *port)
265{
266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
267
268 return atmel_port->use_dma_tx;
269}
270
271static bool atmel_use_dma_rx(struct uart_port *port)
272{
273 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
274
275 return atmel_port->use_dma_rx;
276}
277
278static bool atmel_use_fifo(struct uart_port *port)
279{
280 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
281
282 return atmel_port->fifo_size;
283}
284
285static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
286 struct tasklet_struct *t)
287{
288 if (!atomic_read(&atmel_port->tasklet_shutdown))
289 tasklet_schedule(t);
290}
291
292/* Enable or disable the rs485 support */
293static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
294 struct serial_rs485 *rs485conf)
295{
296 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
297 unsigned int mode;
298
299 /* Disable interrupts */
300 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
301
302 mode = atmel_uart_readl(port, ATMEL_US_MR);
303
304 if (rs485conf->flags & SER_RS485_ENABLED) {
305 dev_dbg(port->dev, "Setting UART to RS485\n");
306 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
307 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
308 else
309 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
310
311 atmel_uart_writel(port, ATMEL_US_TTGR,
312 rs485conf->delay_rts_after_send);
313 mode &= ~ATMEL_US_USMODE;
314 mode |= ATMEL_US_USMODE_RS485;
315 } else {
316 dev_dbg(port->dev, "Setting UART to RS232\n");
317 if (atmel_use_pdc_tx(port))
318 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
319 ATMEL_US_TXBUFE;
320 else
321 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
322 }
323 atmel_uart_writel(port, ATMEL_US_MR, mode);
324
325 /* Enable interrupts */
326 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
327
328 return 0;
329}
330
331static unsigned int atmel_calc_cd(struct uart_port *port,
332 struct serial_iso7816 *iso7816conf)
333{
334 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
335 unsigned int cd;
336 u64 mck_rate;
337
338 mck_rate = (u64)clk_get_rate(atmel_port->clk);
339 do_div(mck_rate, iso7816conf->clk);
340 cd = mck_rate;
341 return cd;
342}
343
344static unsigned int atmel_calc_fidi(struct uart_port *port,
345 struct serial_iso7816 *iso7816conf)
346{
347 u64 fidi = 0;
348
349 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
350 fidi = (u64)iso7816conf->sc_fi;
351 do_div(fidi, iso7816conf->sc_di);
352 }
353 return (u32)fidi;
354}
355
356/* Enable or disable the iso7816 support */
357/* Called with interrupts disabled */
358static int atmel_config_iso7816(struct uart_port *port,
359 struct serial_iso7816 *iso7816conf)
360{
361 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
362 unsigned int mode;
363 unsigned int cd, fidi;
364 int ret = 0;
365
366 /* Disable interrupts */
367 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
368
369 mode = atmel_uart_readl(port, ATMEL_US_MR);
370
371 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
372 mode &= ~ATMEL_US_USMODE;
373
374 if (iso7816conf->tg > 255) {
375 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
376 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
377 ret = -EINVAL;
378 goto err_out;
379 }
380
381 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
382 == SER_ISO7816_T(0)) {
383 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
384 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
385 == SER_ISO7816_T(1)) {
386 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
387 } else {
388 dev_err(port->dev, "ISO7816: Type not supported\n");
389 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
390 ret = -EINVAL;
391 goto err_out;
392 }
393
394 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
395
396 /* select mck clock, and output */
397 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
398 /* set parity for normal/inverse mode + max iterations */
399 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
400
401 cd = atmel_calc_cd(port, iso7816conf);
402 fidi = atmel_calc_fidi(port, iso7816conf);
403 if (fidi == 0) {
404 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
405 } else if (fidi < atmel_port->fidi_min
406 || fidi > atmel_port->fidi_max) {
407 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
408 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
409 ret = -EINVAL;
410 goto err_out;
411 }
412
413 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
414 /* port not yet in iso7816 mode: store configuration */
415 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
416 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
417 }
418
419 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
420 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
421 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
422
423 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
424 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
425 } else {
426 dev_dbg(port->dev, "Setting UART back to RS232\n");
427 /* back to last RS232 settings */
428 mode = atmel_port->backup_mode;
429 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
430 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
431 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
432 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
433
434 if (atmel_use_pdc_tx(port))
435 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
436 ATMEL_US_TXBUFE;
437 else
438 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
439 }
440
441 port->iso7816 = *iso7816conf;
442
443 atmel_uart_writel(port, ATMEL_US_MR, mode);
444
445err_out:
446 /* Enable interrupts */
447 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
448
449 return ret;
450}
451
452/*
453 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
454 */
455static u_int atmel_tx_empty(struct uart_port *port)
456{
457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
458
459 if (atmel_port->tx_stopped)
460 return TIOCSER_TEMT;
461 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
462 TIOCSER_TEMT :
463 0;
464}
465
466/*
467 * Set state of the modem control output lines
468 */
469static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
470{
471 unsigned int control = 0;
472 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
473 unsigned int rts_paused, rts_ready;
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
475
476 /* override mode to RS485 if needed, otherwise keep the current mode */
477 if (port->rs485.flags & SER_RS485_ENABLED) {
478 atmel_uart_writel(port, ATMEL_US_TTGR,
479 port->rs485.delay_rts_after_send);
480 mode &= ~ATMEL_US_USMODE;
481 mode |= ATMEL_US_USMODE_RS485;
482 }
483
484 /* set the RTS line state according to the mode */
485 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
486 /* force RTS line to high level */
487 rts_paused = ATMEL_US_RTSEN;
488
489 /* give the control of the RTS line back to the hardware */
490 rts_ready = ATMEL_US_RTSDIS;
491 } else {
492 /* force RTS line to high level */
493 rts_paused = ATMEL_US_RTSDIS;
494
495 /* force RTS line to low level */
496 rts_ready = ATMEL_US_RTSEN;
497 }
498
499 if (mctrl & TIOCM_RTS)
500 control |= rts_ready;
501 else
502 control |= rts_paused;
503
504 if (mctrl & TIOCM_DTR)
505 control |= ATMEL_US_DTREN;
506 else
507 control |= ATMEL_US_DTRDIS;
508
509 atmel_uart_writel(port, ATMEL_US_CR, control);
510
511 mctrl_gpio_set(atmel_port->gpios, mctrl);
512
513 /* Local loopback mode? */
514 mode &= ~ATMEL_US_CHMODE;
515 if (mctrl & TIOCM_LOOP)
516 mode |= ATMEL_US_CHMODE_LOC_LOOP;
517 else
518 mode |= ATMEL_US_CHMODE_NORMAL;
519
520 atmel_uart_writel(port, ATMEL_US_MR, mode);
521}
522
523/*
524 * Get state of the modem control input lines
525 */
526static u_int atmel_get_mctrl(struct uart_port *port)
527{
528 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
529 unsigned int ret = 0, status;
530
531 status = atmel_uart_readl(port, ATMEL_US_CSR);
532
533 /*
534 * The control signals are active low.
535 */
536 if (!(status & ATMEL_US_DCD))
537 ret |= TIOCM_CD;
538 if (!(status & ATMEL_US_CTS))
539 ret |= TIOCM_CTS;
540 if (!(status & ATMEL_US_DSR))
541 ret |= TIOCM_DSR;
542 if (!(status & ATMEL_US_RI))
543 ret |= TIOCM_RI;
544
545 return mctrl_gpio_get(atmel_port->gpios, &ret);
546}
547
548/*
549 * Stop transmitting.
550 */
551static void atmel_stop_tx(struct uart_port *port)
552{
553 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
554 bool is_pdc = atmel_use_pdc_tx(port);
555 bool is_dma = is_pdc || atmel_use_dma_tx(port);
556
557 if (is_pdc) {
558 /* disable PDC transmit */
559 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
560 }
561
562 if (is_dma) {
563 /*
564 * Disable the transmitter.
565 * This is mandatory when DMA is used, otherwise the DMA buffer
566 * is fully transmitted.
567 */
568 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
569 atmel_port->tx_stopped = true;
570 }
571
572 /* Disable interrupts */
573 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
574
575 if (atmel_uart_is_half_duplex(port))
576 if (!atomic_read(&atmel_port->tasklet_shutdown))
577 atmel_start_rx(port);
578}
579
580/*
581 * Start transmitting.
582 */
583static void atmel_start_tx(struct uart_port *port)
584{
585 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
586 bool is_pdc = atmel_use_pdc_tx(port);
587 bool is_dma = is_pdc || atmel_use_dma_tx(port);
588
589 if (is_pdc && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
590 & ATMEL_PDC_TXTEN))
591 /* The transmitter is already running. Yes, we
592 really need this.*/
593 return;
594
595 if (is_dma && atmel_uart_is_half_duplex(port))
596 atmel_stop_rx(port);
597
598 if (is_pdc) {
599 /* re-enable PDC transmit */
600 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
601 }
602
603 /* Enable interrupts */
604 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
605
606 if (is_dma) {
607 /* re-enable the transmitter */
608 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
609 atmel_port->tx_stopped = false;
610 }
611}
612
613/*
614 * start receiving - port is in process of being opened.
615 */
616static void atmel_start_rx(struct uart_port *port)
617{
618 /* reset status and receiver */
619 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
620
621 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
622
623 if (atmel_use_pdc_rx(port)) {
624 /* enable PDC controller */
625 atmel_uart_writel(port, ATMEL_US_IER,
626 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
627 port->read_status_mask);
628 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
629 } else {
630 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
631 }
632}
633
634/*
635 * Stop receiving - port is in process of being closed.
636 */
637static void atmel_stop_rx(struct uart_port *port)
638{
639 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
640
641 if (atmel_use_pdc_rx(port)) {
642 /* disable PDC receive */
643 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
644 atmel_uart_writel(port, ATMEL_US_IDR,
645 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
646 port->read_status_mask);
647 } else {
648 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
649 }
650}
651
652/*
653 * Enable modem status interrupts
654 */
655static void atmel_enable_ms(struct uart_port *port)
656{
657 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
658 uint32_t ier = 0;
659
660 /*
661 * Interrupt should not be enabled twice
662 */
663 if (atmel_port->ms_irq_enabled)
664 return;
665
666 atmel_port->ms_irq_enabled = true;
667
668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
669 ier |= ATMEL_US_CTSIC;
670
671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
672 ier |= ATMEL_US_DSRIC;
673
674 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
675 ier |= ATMEL_US_RIIC;
676
677 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
678 ier |= ATMEL_US_DCDIC;
679
680 atmel_uart_writel(port, ATMEL_US_IER, ier);
681
682 mctrl_gpio_enable_ms(atmel_port->gpios);
683}
684
685/*
686 * Disable modem status interrupts
687 */
688static void atmel_disable_ms(struct uart_port *port)
689{
690 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
691 uint32_t idr = 0;
692
693 /*
694 * Interrupt should not be disabled twice
695 */
696 if (!atmel_port->ms_irq_enabled)
697 return;
698
699 atmel_port->ms_irq_enabled = false;
700
701 mctrl_gpio_disable_ms(atmel_port->gpios);
702
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
704 idr |= ATMEL_US_CTSIC;
705
706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
707 idr |= ATMEL_US_DSRIC;
708
709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
710 idr |= ATMEL_US_RIIC;
711
712 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
713 idr |= ATMEL_US_DCDIC;
714
715 atmel_uart_writel(port, ATMEL_US_IDR, idr);
716}
717
718/*
719 * Control the transmission of a break signal
720 */
721static void atmel_break_ctl(struct uart_port *port, int break_state)
722{
723 if (break_state != 0)
724 /* start break */
725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
726 else
727 /* stop break */
728 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
729}
730
731/*
732 * Stores the incoming character in the ring buffer
733 */
734static void
735atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
736 unsigned int ch)
737{
738 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
739 struct circ_buf *ring = &atmel_port->rx_ring;
740 struct atmel_uart_char *c;
741
742 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
743 /* Buffer overflow, ignore char */
744 return;
745
746 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
747 c->status = status;
748 c->ch = ch;
749
750 /* Make sure the character is stored before we update head. */
751 smp_wmb();
752
753 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
754}
755
756/*
757 * Deal with parity, framing and overrun errors.
758 */
759static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
760{
761 /* clear error */
762 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
763
764 if (status & ATMEL_US_RXBRK) {
765 /* ignore side-effect */
766 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
767 port->icount.brk++;
768 }
769 if (status & ATMEL_US_PARE)
770 port->icount.parity++;
771 if (status & ATMEL_US_FRAME)
772 port->icount.frame++;
773 if (status & ATMEL_US_OVRE)
774 port->icount.overrun++;
775}
776
777/*
778 * Characters received (called from interrupt handler)
779 */
780static void atmel_rx_chars(struct uart_port *port)
781{
782 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
783 unsigned int status, ch;
784
785 status = atmel_uart_readl(port, ATMEL_US_CSR);
786 while (status & ATMEL_US_RXRDY) {
787 ch = atmel_uart_read_char(port);
788
789 /*
790 * note that the error handling code is
791 * out of the main execution path
792 */
793 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
794 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
795 || atmel_port->break_active)) {
796
797 /* clear error */
798 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
799
800 if (status & ATMEL_US_RXBRK
801 && !atmel_port->break_active) {
802 atmel_port->break_active = 1;
803 atmel_uart_writel(port, ATMEL_US_IER,
804 ATMEL_US_RXBRK);
805 } else {
806 /*
807 * This is either the end-of-break
808 * condition or we've received at
809 * least one character without RXBRK
810 * being set. In both cases, the next
811 * RXBRK will indicate start-of-break.
812 */
813 atmel_uart_writel(port, ATMEL_US_IDR,
814 ATMEL_US_RXBRK);
815 status &= ~ATMEL_US_RXBRK;
816 atmel_port->break_active = 0;
817 }
818 }
819
820 atmel_buffer_rx_char(port, status, ch);
821 status = atmel_uart_readl(port, ATMEL_US_CSR);
822 }
823
824 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
825}
826
827/*
828 * Transmit characters (called from tasklet with TXRDY interrupt
829 * disabled)
830 */
831static void atmel_tx_chars(struct uart_port *port)
832{
833 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
834 bool pending;
835 u8 ch;
836
837 pending = uart_port_tx(port, ch,
838 atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY,
839 atmel_uart_write_char(port, ch));
840 if (pending) {
841 /* we still have characters to transmit, so we should continue
842 * transmitting them when TX is ready, regardless of
843 * mode or duplexity
844 */
845 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
846
847 /* Enable interrupts */
848 atmel_uart_writel(port, ATMEL_US_IER,
849 atmel_port->tx_done_mask);
850 } else {
851 if (atmel_uart_is_half_duplex(port))
852 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
853 }
854}
855
856static void atmel_complete_tx_dma(void *arg)
857{
858 struct atmel_uart_port *atmel_port = arg;
859 struct uart_port *port = &atmel_port->uart;
860 struct circ_buf *xmit = &port->state->xmit;
861 struct dma_chan *chan = atmel_port->chan_tx;
862 unsigned long flags;
863
864 uart_port_lock_irqsave(port, &flags);
865
866 if (chan)
867 dmaengine_terminate_all(chan);
868 uart_xmit_advance(port, atmel_port->tx_len);
869
870 spin_lock(&atmel_port->lock_tx);
871 async_tx_ack(atmel_port->desc_tx);
872 atmel_port->cookie_tx = -EINVAL;
873 atmel_port->desc_tx = NULL;
874 spin_unlock(&atmel_port->lock_tx);
875
876 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
877 uart_write_wakeup(port);
878
879 /*
880 * xmit is a circular buffer so, if we have just send data from
881 * xmit->tail to the end of xmit->buf, now we have to transmit the
882 * remaining data from the beginning of xmit->buf to xmit->head.
883 */
884 if (!uart_circ_empty(xmit))
885 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
886 else if (atmel_uart_is_half_duplex(port)) {
887 /*
888 * DMA done, re-enable TXEMPTY and signal that we can stop
889 * TX and start RX for RS485
890 */
891 atmel_port->hd_start_rx = true;
892 atmel_uart_writel(port, ATMEL_US_IER,
893 atmel_port->tx_done_mask);
894 }
895
896 uart_port_unlock_irqrestore(port, flags);
897}
898
899static void atmel_release_tx_dma(struct uart_port *port)
900{
901 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
902 struct dma_chan *chan = atmel_port->chan_tx;
903
904 if (chan) {
905 dmaengine_terminate_all(chan);
906 dma_release_channel(chan);
907 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
908 DMA_TO_DEVICE);
909 }
910
911 atmel_port->desc_tx = NULL;
912 atmel_port->chan_tx = NULL;
913 atmel_port->cookie_tx = -EINVAL;
914}
915
916/*
917 * Called from tasklet with TXRDY interrupt is disabled.
918 */
919static void atmel_tx_dma(struct uart_port *port)
920{
921 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
922 struct circ_buf *xmit = &port->state->xmit;
923 struct dma_chan *chan = atmel_port->chan_tx;
924 struct dma_async_tx_descriptor *desc;
925 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
926 unsigned int tx_len, part1_len, part2_len, sg_len;
927 dma_addr_t phys_addr;
928
929 /* Make sure we have an idle channel */
930 if (atmel_port->desc_tx != NULL)
931 return;
932
933 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
934 /*
935 * DMA is idle now.
936 * Port xmit buffer is already mapped,
937 * and it is one page... Just adjust
938 * offsets and lengths. Since it is a circular buffer,
939 * we have to transmit till the end, and then the rest.
940 * Take the port lock to get a
941 * consistent xmit buffer state.
942 */
943 tx_len = CIRC_CNT_TO_END(xmit->head,
944 xmit->tail,
945 UART_XMIT_SIZE);
946
947 if (atmel_port->fifo_size) {
948 /* multi data mode */
949 part1_len = (tx_len & ~0x3); /* DWORD access */
950 part2_len = (tx_len & 0x3); /* BYTE access */
951 } else {
952 /* single data (legacy) mode */
953 part1_len = 0;
954 part2_len = tx_len; /* BYTE access only */
955 }
956
957 sg_init_table(sgl, 2);
958 sg_len = 0;
959 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
960 if (part1_len) {
961 sg = &sgl[sg_len++];
962 sg_dma_address(sg) = phys_addr;
963 sg_dma_len(sg) = part1_len;
964
965 phys_addr += part1_len;
966 }
967
968 if (part2_len) {
969 sg = &sgl[sg_len++];
970 sg_dma_address(sg) = phys_addr;
971 sg_dma_len(sg) = part2_len;
972 }
973
974 /*
975 * save tx_len so atmel_complete_tx_dma() will increase
976 * xmit->tail correctly
977 */
978 atmel_port->tx_len = tx_len;
979
980 desc = dmaengine_prep_slave_sg(chan,
981 sgl,
982 sg_len,
983 DMA_MEM_TO_DEV,
984 DMA_PREP_INTERRUPT |
985 DMA_CTRL_ACK);
986 if (!desc) {
987 dev_err(port->dev, "Failed to send via dma!\n");
988 return;
989 }
990
991 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
992
993 atmel_port->desc_tx = desc;
994 desc->callback = atmel_complete_tx_dma;
995 desc->callback_param = atmel_port;
996 atmel_port->cookie_tx = dmaengine_submit(desc);
997 if (dma_submit_error(atmel_port->cookie_tx)) {
998 dev_err(port->dev, "dma_submit_error %d\n",
999 atmel_port->cookie_tx);
1000 return;
1001 }
1002
1003 dma_async_issue_pending(chan);
1004 }
1005
1006 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1007 uart_write_wakeup(port);
1008}
1009
1010static int atmel_prepare_tx_dma(struct uart_port *port)
1011{
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1013 struct device *mfd_dev = port->dev->parent;
1014 dma_cap_mask_t mask;
1015 struct dma_slave_config config;
1016 struct dma_chan *chan;
1017 int ret, nent;
1018
1019 dma_cap_zero(mask);
1020 dma_cap_set(DMA_SLAVE, mask);
1021
1022 chan = dma_request_chan(mfd_dev, "tx");
1023 if (IS_ERR(chan)) {
1024 atmel_port->chan_tx = NULL;
1025 goto chan_err;
1026 }
1027 atmel_port->chan_tx = chan;
1028 dev_info(port->dev, "using %s for tx DMA transfers\n",
1029 dma_chan_name(atmel_port->chan_tx));
1030
1031 spin_lock_init(&atmel_port->lock_tx);
1032 sg_init_table(&atmel_port->sg_tx, 1);
1033 /* UART circular tx buffer is an aligned page. */
1034 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1035 sg_set_page(&atmel_port->sg_tx,
1036 virt_to_page(port->state->xmit.buf),
1037 UART_XMIT_SIZE,
1038 offset_in_page(port->state->xmit.buf));
1039 nent = dma_map_sg(port->dev,
1040 &atmel_port->sg_tx,
1041 1,
1042 DMA_TO_DEVICE);
1043
1044 if (!nent) {
1045 dev_dbg(port->dev, "need to release resource of dma\n");
1046 goto chan_err;
1047 } else {
1048 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1049 sg_dma_len(&atmel_port->sg_tx),
1050 port->state->xmit.buf,
1051 &sg_dma_address(&atmel_port->sg_tx));
1052 }
1053
1054 /* Configure the slave DMA */
1055 memset(&config, 0, sizeof(config));
1056 config.direction = DMA_MEM_TO_DEV;
1057 config.dst_addr_width = (atmel_port->fifo_size) ?
1058 DMA_SLAVE_BUSWIDTH_4_BYTES :
1059 DMA_SLAVE_BUSWIDTH_1_BYTE;
1060 config.dst_addr = port->mapbase + ATMEL_US_THR;
1061 config.dst_maxburst = 1;
1062
1063 ret = dmaengine_slave_config(atmel_port->chan_tx,
1064 &config);
1065 if (ret) {
1066 dev_err(port->dev, "DMA tx slave configuration failed\n");
1067 goto chan_err;
1068 }
1069
1070 return 0;
1071
1072chan_err:
1073 dev_err(port->dev, "TX channel not available, switch to pio\n");
1074 atmel_port->use_dma_tx = false;
1075 if (atmel_port->chan_tx)
1076 atmel_release_tx_dma(port);
1077 return -EINVAL;
1078}
1079
1080static void atmel_complete_rx_dma(void *arg)
1081{
1082 struct uart_port *port = arg;
1083 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1084
1085 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1086}
1087
1088static void atmel_release_rx_dma(struct uart_port *port)
1089{
1090 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1091 struct dma_chan *chan = atmel_port->chan_rx;
1092
1093 if (chan) {
1094 dmaengine_terminate_all(chan);
1095 dma_release_channel(chan);
1096 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1097 DMA_FROM_DEVICE);
1098 }
1099
1100 atmel_port->desc_rx = NULL;
1101 atmel_port->chan_rx = NULL;
1102 atmel_port->cookie_rx = -EINVAL;
1103}
1104
1105static void atmel_rx_from_dma(struct uart_port *port)
1106{
1107 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1108 struct tty_port *tport = &port->state->port;
1109 struct circ_buf *ring = &atmel_port->rx_ring;
1110 struct dma_chan *chan = atmel_port->chan_rx;
1111 struct dma_tx_state state;
1112 enum dma_status dmastat;
1113 size_t count;
1114
1115
1116 /* Reset the UART timeout early so that we don't miss one */
1117 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1118 dmastat = dmaengine_tx_status(chan,
1119 atmel_port->cookie_rx,
1120 &state);
1121 /* Restart a new tasklet if DMA status is error */
1122 if (dmastat == DMA_ERROR) {
1123 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1124 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1125 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1126 return;
1127 }
1128
1129 /* CPU claims ownership of RX DMA buffer */
1130 dma_sync_sg_for_cpu(port->dev,
1131 &atmel_port->sg_rx,
1132 1,
1133 DMA_FROM_DEVICE);
1134
1135 /*
1136 * ring->head points to the end of data already written by the DMA.
1137 * ring->tail points to the beginning of data to be read by the
1138 * framework.
1139 * The current transfer size should not be larger than the dma buffer
1140 * length.
1141 */
1142 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1143 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1144 /*
1145 * At this point ring->head may point to the first byte right after the
1146 * last byte of the dma buffer:
1147 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1148 *
1149 * However ring->tail must always points inside the dma buffer:
1150 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1151 *
1152 * Since we use a ring buffer, we have to handle the case
1153 * where head is lower than tail. In such a case, we first read from
1154 * tail to the end of the buffer then reset tail.
1155 */
1156 if (ring->head < ring->tail) {
1157 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1158
1159 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1160 ring->tail = 0;
1161 port->icount.rx += count;
1162 }
1163
1164 /* Finally we read data from tail to head */
1165 if (ring->tail < ring->head) {
1166 count = ring->head - ring->tail;
1167
1168 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1169 /* Wrap ring->head if needed */
1170 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1171 ring->head = 0;
1172 ring->tail = ring->head;
1173 port->icount.rx += count;
1174 }
1175
1176 /* USART retreives ownership of RX DMA buffer */
1177 dma_sync_sg_for_device(port->dev,
1178 &atmel_port->sg_rx,
1179 1,
1180 DMA_FROM_DEVICE);
1181
1182 tty_flip_buffer_push(tport);
1183
1184 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1185}
1186
1187static int atmel_prepare_rx_dma(struct uart_port *port)
1188{
1189 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1190 struct device *mfd_dev = port->dev->parent;
1191 struct dma_async_tx_descriptor *desc;
1192 dma_cap_mask_t mask;
1193 struct dma_slave_config config;
1194 struct circ_buf *ring;
1195 struct dma_chan *chan;
1196 int ret, nent;
1197
1198 ring = &atmel_port->rx_ring;
1199
1200 dma_cap_zero(mask);
1201 dma_cap_set(DMA_CYCLIC, mask);
1202
1203 chan = dma_request_chan(mfd_dev, "rx");
1204 if (IS_ERR(chan)) {
1205 atmel_port->chan_rx = NULL;
1206 goto chan_err;
1207 }
1208 atmel_port->chan_rx = chan;
1209 dev_info(port->dev, "using %s for rx DMA transfers\n",
1210 dma_chan_name(atmel_port->chan_rx));
1211
1212 spin_lock_init(&atmel_port->lock_rx);
1213 sg_init_table(&atmel_port->sg_rx, 1);
1214 /* UART circular rx buffer is an aligned page. */
1215 BUG_ON(!PAGE_ALIGNED(ring->buf));
1216 sg_set_page(&atmel_port->sg_rx,
1217 virt_to_page(ring->buf),
1218 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1219 offset_in_page(ring->buf));
1220 nent = dma_map_sg(port->dev,
1221 &atmel_port->sg_rx,
1222 1,
1223 DMA_FROM_DEVICE);
1224
1225 if (!nent) {
1226 dev_dbg(port->dev, "need to release resource of dma\n");
1227 goto chan_err;
1228 } else {
1229 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1230 sg_dma_len(&atmel_port->sg_rx),
1231 ring->buf,
1232 &sg_dma_address(&atmel_port->sg_rx));
1233 }
1234
1235 /* Configure the slave DMA */
1236 memset(&config, 0, sizeof(config));
1237 config.direction = DMA_DEV_TO_MEM;
1238 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1239 config.src_addr = port->mapbase + ATMEL_US_RHR;
1240 config.src_maxburst = 1;
1241
1242 ret = dmaengine_slave_config(atmel_port->chan_rx,
1243 &config);
1244 if (ret) {
1245 dev_err(port->dev, "DMA rx slave configuration failed\n");
1246 goto chan_err;
1247 }
1248 /*
1249 * Prepare a cyclic dma transfer, assign 2 descriptors,
1250 * each one is half ring buffer size
1251 */
1252 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1253 sg_dma_address(&atmel_port->sg_rx),
1254 sg_dma_len(&atmel_port->sg_rx),
1255 sg_dma_len(&atmel_port->sg_rx)/2,
1256 DMA_DEV_TO_MEM,
1257 DMA_PREP_INTERRUPT);
1258 if (!desc) {
1259 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1260 goto chan_err;
1261 }
1262 desc->callback = atmel_complete_rx_dma;
1263 desc->callback_param = port;
1264 atmel_port->desc_rx = desc;
1265 atmel_port->cookie_rx = dmaengine_submit(desc);
1266 if (dma_submit_error(atmel_port->cookie_rx)) {
1267 dev_err(port->dev, "dma_submit_error %d\n",
1268 atmel_port->cookie_rx);
1269 goto chan_err;
1270 }
1271
1272 dma_async_issue_pending(atmel_port->chan_rx);
1273
1274 return 0;
1275
1276chan_err:
1277 dev_err(port->dev, "RX channel not available, switch to pio\n");
1278 atmel_port->use_dma_rx = false;
1279 if (atmel_port->chan_rx)
1280 atmel_release_rx_dma(port);
1281 return -EINVAL;
1282}
1283
1284static void atmel_uart_timer_callback(struct timer_list *t)
1285{
1286 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1287 uart_timer);
1288 struct uart_port *port = &atmel_port->uart;
1289
1290 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1291 tasklet_schedule(&atmel_port->tasklet_rx);
1292 mod_timer(&atmel_port->uart_timer,
1293 jiffies + uart_poll_timeout(port));
1294 }
1295}
1296
1297/*
1298 * receive interrupt handler.
1299 */
1300static void
1301atmel_handle_receive(struct uart_port *port, unsigned int pending)
1302{
1303 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1304
1305 if (atmel_use_pdc_rx(port)) {
1306 /*
1307 * PDC receive. Just schedule the tasklet and let it
1308 * figure out the details.
1309 *
1310 * TODO: We're not handling error flags correctly at
1311 * the moment.
1312 */
1313 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1314 atmel_uart_writel(port, ATMEL_US_IDR,
1315 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1316 atmel_tasklet_schedule(atmel_port,
1317 &atmel_port->tasklet_rx);
1318 }
1319
1320 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1321 ATMEL_US_FRAME | ATMEL_US_PARE))
1322 atmel_pdc_rxerr(port, pending);
1323 }
1324
1325 if (atmel_use_dma_rx(port)) {
1326 if (pending & ATMEL_US_TIMEOUT) {
1327 atmel_uart_writel(port, ATMEL_US_IDR,
1328 ATMEL_US_TIMEOUT);
1329 atmel_tasklet_schedule(atmel_port,
1330 &atmel_port->tasklet_rx);
1331 }
1332 }
1333
1334 /* Interrupt receive */
1335 if (pending & ATMEL_US_RXRDY)
1336 atmel_rx_chars(port);
1337 else if (pending & ATMEL_US_RXBRK) {
1338 /*
1339 * End of break detected. If it came along with a
1340 * character, atmel_rx_chars will handle it.
1341 */
1342 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1343 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1344 atmel_port->break_active = 0;
1345 }
1346}
1347
1348/*
1349 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1350 */
1351static void
1352atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1353{
1354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1355
1356 if (pending & atmel_port->tx_done_mask) {
1357 atmel_uart_writel(port, ATMEL_US_IDR,
1358 atmel_port->tx_done_mask);
1359
1360 /* Start RX if flag was set and FIFO is empty */
1361 if (atmel_port->hd_start_rx) {
1362 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1363 & ATMEL_US_TXEMPTY))
1364 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1365
1366 atmel_port->hd_start_rx = false;
1367 atmel_start_rx(port);
1368 }
1369
1370 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1371 }
1372}
1373
1374/*
1375 * status flags interrupt handler.
1376 */
1377static void
1378atmel_handle_status(struct uart_port *port, unsigned int pending,
1379 unsigned int status)
1380{
1381 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1382 unsigned int status_change;
1383
1384 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1385 | ATMEL_US_CTSIC)) {
1386 status_change = status ^ atmel_port->irq_status_prev;
1387 atmel_port->irq_status_prev = status;
1388
1389 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1390 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1391 /* TODO: All reads to CSR will clear these interrupts! */
1392 if (status_change & ATMEL_US_RI)
1393 port->icount.rng++;
1394 if (status_change & ATMEL_US_DSR)
1395 port->icount.dsr++;
1396 if (status_change & ATMEL_US_DCD)
1397 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1398 if (status_change & ATMEL_US_CTS)
1399 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1400
1401 wake_up_interruptible(&port->state->port.delta_msr_wait);
1402 }
1403 }
1404
1405 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1406 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1407}
1408
1409/*
1410 * Interrupt handler
1411 */
1412static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1413{
1414 struct uart_port *port = dev_id;
1415 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1416 unsigned int status, pending, mask, pass_counter = 0;
1417
1418 spin_lock(&atmel_port->lock_suspended);
1419
1420 do {
1421 status = atmel_uart_readl(port, ATMEL_US_CSR);
1422 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1423 pending = status & mask;
1424 if (!pending)
1425 break;
1426
1427 if (atmel_port->suspended) {
1428 atmel_port->pending |= pending;
1429 atmel_port->pending_status = status;
1430 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1431 pm_system_wakeup();
1432 break;
1433 }
1434
1435 atmel_handle_receive(port, pending);
1436 atmel_handle_status(port, pending, status);
1437 atmel_handle_transmit(port, pending);
1438 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1439
1440 spin_unlock(&atmel_port->lock_suspended);
1441
1442 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1443}
1444
1445static void atmel_release_tx_pdc(struct uart_port *port)
1446{
1447 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1448 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1449
1450 dma_unmap_single(port->dev,
1451 pdc->dma_addr,
1452 pdc->dma_size,
1453 DMA_TO_DEVICE);
1454}
1455
1456/*
1457 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1458 */
1459static void atmel_tx_pdc(struct uart_port *port)
1460{
1461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1462 struct circ_buf *xmit = &port->state->xmit;
1463 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1464 int count;
1465
1466 /* nothing left to transmit? */
1467 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1468 return;
1469 uart_xmit_advance(port, pdc->ofs);
1470 pdc->ofs = 0;
1471
1472 /* more to transmit - setup next transfer */
1473
1474 /* disable PDC transmit */
1475 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1476
1477 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1478 dma_sync_single_for_device(port->dev,
1479 pdc->dma_addr,
1480 pdc->dma_size,
1481 DMA_TO_DEVICE);
1482
1483 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1484 pdc->ofs = count;
1485
1486 atmel_uart_writel(port, ATMEL_PDC_TPR,
1487 pdc->dma_addr + xmit->tail);
1488 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1489 /* re-enable PDC transmit */
1490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1491 /* Enable interrupts */
1492 atmel_uart_writel(port, ATMEL_US_IER,
1493 atmel_port->tx_done_mask);
1494 } else {
1495 if (atmel_uart_is_half_duplex(port)) {
1496 /* DMA done, stop TX, start RX for RS485 */
1497 atmel_start_rx(port);
1498 }
1499 }
1500
1501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1502 uart_write_wakeup(port);
1503}
1504
1505static int atmel_prepare_tx_pdc(struct uart_port *port)
1506{
1507 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1508 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1509 struct circ_buf *xmit = &port->state->xmit;
1510
1511 pdc->buf = xmit->buf;
1512 pdc->dma_addr = dma_map_single(port->dev,
1513 pdc->buf,
1514 UART_XMIT_SIZE,
1515 DMA_TO_DEVICE);
1516 pdc->dma_size = UART_XMIT_SIZE;
1517 pdc->ofs = 0;
1518
1519 return 0;
1520}
1521
1522static void atmel_rx_from_ring(struct uart_port *port)
1523{
1524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1525 struct circ_buf *ring = &atmel_port->rx_ring;
1526 unsigned int status;
1527 u8 flg;
1528
1529 while (ring->head != ring->tail) {
1530 struct atmel_uart_char c;
1531
1532 /* Make sure c is loaded after head. */
1533 smp_rmb();
1534
1535 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1536
1537 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1538
1539 port->icount.rx++;
1540 status = c.status;
1541 flg = TTY_NORMAL;
1542
1543 /*
1544 * note that the error handling code is
1545 * out of the main execution path
1546 */
1547 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1548 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1549 if (status & ATMEL_US_RXBRK) {
1550 /* ignore side-effect */
1551 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1552
1553 port->icount.brk++;
1554 if (uart_handle_break(port))
1555 continue;
1556 }
1557 if (status & ATMEL_US_PARE)
1558 port->icount.parity++;
1559 if (status & ATMEL_US_FRAME)
1560 port->icount.frame++;
1561 if (status & ATMEL_US_OVRE)
1562 port->icount.overrun++;
1563
1564 status &= port->read_status_mask;
1565
1566 if (status & ATMEL_US_RXBRK)
1567 flg = TTY_BREAK;
1568 else if (status & ATMEL_US_PARE)
1569 flg = TTY_PARITY;
1570 else if (status & ATMEL_US_FRAME)
1571 flg = TTY_FRAME;
1572 }
1573
1574
1575 if (uart_handle_sysrq_char(port, c.ch))
1576 continue;
1577
1578 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1579 }
1580
1581 tty_flip_buffer_push(&port->state->port);
1582}
1583
1584static void atmel_release_rx_pdc(struct uart_port *port)
1585{
1586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1587 int i;
1588
1589 for (i = 0; i < 2; i++) {
1590 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1591
1592 dma_unmap_single(port->dev,
1593 pdc->dma_addr,
1594 pdc->dma_size,
1595 DMA_FROM_DEVICE);
1596 kfree(pdc->buf);
1597 }
1598}
1599
1600static void atmel_rx_from_pdc(struct uart_port *port)
1601{
1602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1603 struct tty_port *tport = &port->state->port;
1604 struct atmel_dma_buffer *pdc;
1605 int rx_idx = atmel_port->pdc_rx_idx;
1606 unsigned int head;
1607 unsigned int tail;
1608 unsigned int count;
1609
1610 do {
1611 /* Reset the UART timeout early so that we don't miss one */
1612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1613
1614 pdc = &atmel_port->pdc_rx[rx_idx];
1615 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1616 tail = pdc->ofs;
1617
1618 /* If the PDC has switched buffers, RPR won't contain
1619 * any address within the current buffer. Since head
1620 * is unsigned, we just need a one-way comparison to
1621 * find out.
1622 *
1623 * In this case, we just need to consume the entire
1624 * buffer and resubmit it for DMA. This will clear the
1625 * ENDRX bit as well, so that we can safely re-enable
1626 * all interrupts below.
1627 */
1628 head = min(head, pdc->dma_size);
1629
1630 if (likely(head != tail)) {
1631 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1632 pdc->dma_size, DMA_FROM_DEVICE);
1633
1634 /*
1635 * head will only wrap around when we recycle
1636 * the DMA buffer, and when that happens, we
1637 * explicitly set tail to 0. So head will
1638 * always be greater than tail.
1639 */
1640 count = head - tail;
1641
1642 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1643 count);
1644
1645 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1646 pdc->dma_size, DMA_FROM_DEVICE);
1647
1648 port->icount.rx += count;
1649 pdc->ofs = head;
1650 }
1651
1652 /*
1653 * If the current buffer is full, we need to check if
1654 * the next one contains any additional data.
1655 */
1656 if (head >= pdc->dma_size) {
1657 pdc->ofs = 0;
1658 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1659 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1660
1661 rx_idx = !rx_idx;
1662 atmel_port->pdc_rx_idx = rx_idx;
1663 }
1664 } while (head >= pdc->dma_size);
1665
1666 tty_flip_buffer_push(tport);
1667
1668 atmel_uart_writel(port, ATMEL_US_IER,
1669 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1670}
1671
1672static int atmel_prepare_rx_pdc(struct uart_port *port)
1673{
1674 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1675 int i;
1676
1677 for (i = 0; i < 2; i++) {
1678 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1679
1680 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1681 if (pdc->buf == NULL) {
1682 if (i != 0) {
1683 dma_unmap_single(port->dev,
1684 atmel_port->pdc_rx[0].dma_addr,
1685 PDC_BUFFER_SIZE,
1686 DMA_FROM_DEVICE);
1687 kfree(atmel_port->pdc_rx[0].buf);
1688 }
1689 atmel_port->use_pdc_rx = false;
1690 return -ENOMEM;
1691 }
1692 pdc->dma_addr = dma_map_single(port->dev,
1693 pdc->buf,
1694 PDC_BUFFER_SIZE,
1695 DMA_FROM_DEVICE);
1696 pdc->dma_size = PDC_BUFFER_SIZE;
1697 pdc->ofs = 0;
1698 }
1699
1700 atmel_port->pdc_rx_idx = 0;
1701
1702 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1703 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1704
1705 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1706 atmel_port->pdc_rx[1].dma_addr);
1707 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1708
1709 return 0;
1710}
1711
1712/*
1713 * tasklet handling tty stuff outside the interrupt handler.
1714 */
1715static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1716{
1717 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1718 tasklet_rx);
1719 struct uart_port *port = &atmel_port->uart;
1720
1721 /* The interrupt handler does not take the lock */
1722 uart_port_lock(port);
1723 atmel_port->schedule_rx(port);
1724 uart_port_unlock(port);
1725}
1726
1727static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1728{
1729 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1730 tasklet_tx);
1731 struct uart_port *port = &atmel_port->uart;
1732
1733 /* The interrupt handler does not take the lock */
1734 uart_port_lock(port);
1735 atmel_port->schedule_tx(port);
1736 uart_port_unlock(port);
1737}
1738
1739static void atmel_init_property(struct atmel_uart_port *atmel_port,
1740 struct platform_device *pdev)
1741{
1742 struct device_node *np = pdev->dev.of_node;
1743
1744 /* DMA/PDC usage specification */
1745 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1746 if (of_property_read_bool(np, "dmas")) {
1747 atmel_port->use_dma_rx = true;
1748 atmel_port->use_pdc_rx = false;
1749 } else {
1750 atmel_port->use_dma_rx = false;
1751 atmel_port->use_pdc_rx = true;
1752 }
1753 } else {
1754 atmel_port->use_dma_rx = false;
1755 atmel_port->use_pdc_rx = false;
1756 }
1757
1758 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1759 if (of_property_read_bool(np, "dmas")) {
1760 atmel_port->use_dma_tx = true;
1761 atmel_port->use_pdc_tx = false;
1762 } else {
1763 atmel_port->use_dma_tx = false;
1764 atmel_port->use_pdc_tx = true;
1765 }
1766 } else {
1767 atmel_port->use_dma_tx = false;
1768 atmel_port->use_pdc_tx = false;
1769 }
1770}
1771
1772static void atmel_set_ops(struct uart_port *port)
1773{
1774 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1775
1776 if (atmel_use_dma_rx(port)) {
1777 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1778 atmel_port->schedule_rx = &atmel_rx_from_dma;
1779 atmel_port->release_rx = &atmel_release_rx_dma;
1780 } else if (atmel_use_pdc_rx(port)) {
1781 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1782 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1783 atmel_port->release_rx = &atmel_release_rx_pdc;
1784 } else {
1785 atmel_port->prepare_rx = NULL;
1786 atmel_port->schedule_rx = &atmel_rx_from_ring;
1787 atmel_port->release_rx = NULL;
1788 }
1789
1790 if (atmel_use_dma_tx(port)) {
1791 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1792 atmel_port->schedule_tx = &atmel_tx_dma;
1793 atmel_port->release_tx = &atmel_release_tx_dma;
1794 } else if (atmel_use_pdc_tx(port)) {
1795 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1796 atmel_port->schedule_tx = &atmel_tx_pdc;
1797 atmel_port->release_tx = &atmel_release_tx_pdc;
1798 } else {
1799 atmel_port->prepare_tx = NULL;
1800 atmel_port->schedule_tx = &atmel_tx_chars;
1801 atmel_port->release_tx = NULL;
1802 }
1803}
1804
1805/*
1806 * Get ip name usart or uart
1807 */
1808static void atmel_get_ip_name(struct uart_port *port)
1809{
1810 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1811 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1812 u32 version;
1813 u32 usart, dbgu_uart, new_uart;
1814 /* ASCII decoding for IP version */
1815 usart = 0x55534152; /* USAR(T) */
1816 dbgu_uart = 0x44424755; /* DBGU */
1817 new_uart = 0x55415254; /* UART */
1818
1819 /*
1820 * Only USART devices from at91sam9260 SOC implement fractional
1821 * baudrate. It is available for all asynchronous modes, with the
1822 * following restriction: the sampling clock's duty cycle is not
1823 * constant.
1824 */
1825 atmel_port->has_frac_baudrate = false;
1826 atmel_port->has_hw_timer = false;
1827 atmel_port->is_usart = false;
1828
1829 if (name == new_uart) {
1830 dev_dbg(port->dev, "Uart with hw timer");
1831 atmel_port->has_hw_timer = true;
1832 atmel_port->rtor = ATMEL_UA_RTOR;
1833 } else if (name == usart) {
1834 dev_dbg(port->dev, "Usart\n");
1835 atmel_port->has_frac_baudrate = true;
1836 atmel_port->has_hw_timer = true;
1837 atmel_port->is_usart = true;
1838 atmel_port->rtor = ATMEL_US_RTOR;
1839 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1840 switch (version) {
1841 case 0x814: /* sama5d2 */
1842 fallthrough;
1843 case 0x701: /* sama5d4 */
1844 atmel_port->fidi_min = 3;
1845 atmel_port->fidi_max = 65535;
1846 break;
1847 case 0x502: /* sam9x5, sama5d3 */
1848 atmel_port->fidi_min = 3;
1849 atmel_port->fidi_max = 2047;
1850 break;
1851 default:
1852 atmel_port->fidi_min = 1;
1853 atmel_port->fidi_max = 2047;
1854 }
1855 } else if (name == dbgu_uart) {
1856 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1857 } else {
1858 /* fallback for older SoCs: use version field */
1859 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1860 switch (version) {
1861 case 0x302:
1862 case 0x10213:
1863 case 0x10302:
1864 dev_dbg(port->dev, "This version is usart\n");
1865 atmel_port->has_frac_baudrate = true;
1866 atmel_port->has_hw_timer = true;
1867 atmel_port->is_usart = true;
1868 atmel_port->rtor = ATMEL_US_RTOR;
1869 break;
1870 case 0x203:
1871 case 0x10202:
1872 dev_dbg(port->dev, "This version is uart\n");
1873 break;
1874 default:
1875 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1876 }
1877 }
1878}
1879
1880/*
1881 * Perform initialization and enable port for reception
1882 */
1883static int atmel_startup(struct uart_port *port)
1884{
1885 struct platform_device *pdev = to_platform_device(port->dev);
1886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1887 int retval;
1888
1889 /*
1890 * Ensure that no interrupts are enabled otherwise when
1891 * request_irq() is called we could get stuck trying to
1892 * handle an unexpected interrupt
1893 */
1894 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1895 atmel_port->ms_irq_enabled = false;
1896
1897 /*
1898 * Allocate the IRQ
1899 */
1900 retval = request_irq(port->irq, atmel_interrupt,
1901 IRQF_SHARED | IRQF_COND_SUSPEND,
1902 dev_name(&pdev->dev), port);
1903 if (retval) {
1904 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1905 return retval;
1906 }
1907
1908 atomic_set(&atmel_port->tasklet_shutdown, 0);
1909 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1910 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1911
1912 /*
1913 * Initialize DMA (if necessary)
1914 */
1915 atmel_init_property(atmel_port, pdev);
1916 atmel_set_ops(port);
1917
1918 if (atmel_port->prepare_rx) {
1919 retval = atmel_port->prepare_rx(port);
1920 if (retval < 0)
1921 atmel_set_ops(port);
1922 }
1923
1924 if (atmel_port->prepare_tx) {
1925 retval = atmel_port->prepare_tx(port);
1926 if (retval < 0)
1927 atmel_set_ops(port);
1928 }
1929
1930 /*
1931 * Enable FIFO when available
1932 */
1933 if (atmel_port->fifo_size) {
1934 unsigned int txrdym = ATMEL_US_ONE_DATA;
1935 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1936 unsigned int fmr;
1937
1938 atmel_uart_writel(port, ATMEL_US_CR,
1939 ATMEL_US_FIFOEN |
1940 ATMEL_US_RXFCLR |
1941 ATMEL_US_TXFLCLR);
1942
1943 if (atmel_use_dma_tx(port))
1944 txrdym = ATMEL_US_FOUR_DATA;
1945
1946 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1947 if (atmel_port->rts_high &&
1948 atmel_port->rts_low)
1949 fmr |= ATMEL_US_FRTSC |
1950 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1951 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1952
1953 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1954 }
1955
1956 /* Save current CSR for comparison in atmel_tasklet_func() */
1957 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1958
1959 /*
1960 * Finally, enable the serial port
1961 */
1962 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1963 /* enable xmit & rcvr */
1964 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1965 atmel_port->tx_stopped = false;
1966
1967 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1968
1969 if (atmel_use_pdc_rx(port)) {
1970 /* set UART timeout */
1971 if (!atmel_port->has_hw_timer) {
1972 mod_timer(&atmel_port->uart_timer,
1973 jiffies + uart_poll_timeout(port));
1974 /* set USART timeout */
1975 } else {
1976 atmel_uart_writel(port, atmel_port->rtor,
1977 PDC_RX_TIMEOUT);
1978 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1979
1980 atmel_uart_writel(port, ATMEL_US_IER,
1981 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1982 }
1983 /* enable PDC controller */
1984 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1985 } else if (atmel_use_dma_rx(port)) {
1986 /* set UART timeout */
1987 if (!atmel_port->has_hw_timer) {
1988 mod_timer(&atmel_port->uart_timer,
1989 jiffies + uart_poll_timeout(port));
1990 /* set USART timeout */
1991 } else {
1992 atmel_uart_writel(port, atmel_port->rtor,
1993 PDC_RX_TIMEOUT);
1994 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1995
1996 atmel_uart_writel(port, ATMEL_US_IER,
1997 ATMEL_US_TIMEOUT);
1998 }
1999 } else {
2000 /* enable receive only */
2001 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2002 }
2003
2004 return 0;
2005}
2006
2007/*
2008 * Flush any TX data submitted for DMA. Called when the TX circular
2009 * buffer is reset.
2010 */
2011static void atmel_flush_buffer(struct uart_port *port)
2012{
2013 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2014
2015 if (atmel_use_pdc_tx(port)) {
2016 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2017 atmel_port->pdc_tx.ofs = 0;
2018 }
2019 /*
2020 * in uart_flush_buffer(), the xmit circular buffer has just
2021 * been cleared, so we have to reset tx_len accordingly.
2022 */
2023 atmel_port->tx_len = 0;
2024}
2025
2026/*
2027 * Disable the port
2028 */
2029static void atmel_shutdown(struct uart_port *port)
2030{
2031 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2032
2033 /* Disable modem control lines interrupts */
2034 atmel_disable_ms(port);
2035
2036 /* Disable interrupts at device level */
2037 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2038
2039 /* Prevent spurious interrupts from scheduling the tasklet */
2040 atomic_inc(&atmel_port->tasklet_shutdown);
2041
2042 /*
2043 * Prevent any tasklets being scheduled during
2044 * cleanup
2045 */
2046 del_timer_sync(&atmel_port->uart_timer);
2047
2048 /* Make sure that no interrupt is on the fly */
2049 synchronize_irq(port->irq);
2050
2051 /*
2052 * Clear out any scheduled tasklets before
2053 * we destroy the buffers
2054 */
2055 tasklet_kill(&atmel_port->tasklet_rx);
2056 tasklet_kill(&atmel_port->tasklet_tx);
2057
2058 /*
2059 * Ensure everything is stopped and
2060 * disable port and break condition.
2061 */
2062 atmel_stop_rx(port);
2063 atmel_stop_tx(port);
2064
2065 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2066
2067 /*
2068 * Shut-down the DMA.
2069 */
2070 if (atmel_port->release_rx)
2071 atmel_port->release_rx(port);
2072 if (atmel_port->release_tx)
2073 atmel_port->release_tx(port);
2074
2075 /*
2076 * Reset ring buffer pointers
2077 */
2078 atmel_port->rx_ring.head = 0;
2079 atmel_port->rx_ring.tail = 0;
2080
2081 /*
2082 * Free the interrupts
2083 */
2084 free_irq(port->irq, port);
2085
2086 atmel_flush_buffer(port);
2087}
2088
2089/*
2090 * Power / Clock management.
2091 */
2092static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2093 unsigned int oldstate)
2094{
2095 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2096
2097 switch (state) {
2098 case UART_PM_STATE_ON:
2099 /*
2100 * Enable the peripheral clock for this serial port.
2101 * This is called on uart_open() or a resume event.
2102 */
2103 clk_prepare_enable(atmel_port->clk);
2104
2105 /* re-enable interrupts if we disabled some on suspend */
2106 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2107 break;
2108 case UART_PM_STATE_OFF:
2109 /* Back up the interrupt mask and disable all interrupts */
2110 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2111 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2112
2113 /*
2114 * Disable the peripheral clock for this serial port.
2115 * This is called on uart_close() or a suspend event.
2116 */
2117 clk_disable_unprepare(atmel_port->clk);
2118 if (__clk_is_enabled(atmel_port->gclk))
2119 clk_disable_unprepare(atmel_port->gclk);
2120 break;
2121 default:
2122 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2123 }
2124}
2125
2126/*
2127 * Change the port parameters
2128 */
2129static void atmel_set_termios(struct uart_port *port,
2130 struct ktermios *termios,
2131 const struct ktermios *old)
2132{
2133 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2134 unsigned long flags;
2135 unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
2136 unsigned int baud, actual_baud, gclk_rate;
2137 int ret;
2138
2139 /* save the current mode register */
2140 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2141
2142 /* reset the mode, clock divisor, parity, stop bits and data size */
2143 if (atmel_port->is_usart)
2144 mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
2145 ATMEL_US_USCLKS | ATMEL_US_USMODE);
2146 else
2147 mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
2148
2149 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2150
2151 /* byte size */
2152 switch (termios->c_cflag & CSIZE) {
2153 case CS5:
2154 mode |= ATMEL_US_CHRL_5;
2155 break;
2156 case CS6:
2157 mode |= ATMEL_US_CHRL_6;
2158 break;
2159 case CS7:
2160 mode |= ATMEL_US_CHRL_7;
2161 break;
2162 default:
2163 mode |= ATMEL_US_CHRL_8;
2164 break;
2165 }
2166
2167 /* stop bits */
2168 if (termios->c_cflag & CSTOPB)
2169 mode |= ATMEL_US_NBSTOP_2;
2170
2171 /* parity */
2172 if (termios->c_cflag & PARENB) {
2173 /* Mark or Space parity */
2174 if (termios->c_cflag & CMSPAR) {
2175 if (termios->c_cflag & PARODD)
2176 mode |= ATMEL_US_PAR_MARK;
2177 else
2178 mode |= ATMEL_US_PAR_SPACE;
2179 } else if (termios->c_cflag & PARODD)
2180 mode |= ATMEL_US_PAR_ODD;
2181 else
2182 mode |= ATMEL_US_PAR_EVEN;
2183 } else
2184 mode |= ATMEL_US_PAR_NONE;
2185
2186 uart_port_lock_irqsave(port, &flags);
2187
2188 port->read_status_mask = ATMEL_US_OVRE;
2189 if (termios->c_iflag & INPCK)
2190 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2191 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2192 port->read_status_mask |= ATMEL_US_RXBRK;
2193
2194 if (atmel_use_pdc_rx(port))
2195 /* need to enable error interrupts */
2196 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2197
2198 /*
2199 * Characters to ignore
2200 */
2201 port->ignore_status_mask = 0;
2202 if (termios->c_iflag & IGNPAR)
2203 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2204 if (termios->c_iflag & IGNBRK) {
2205 port->ignore_status_mask |= ATMEL_US_RXBRK;
2206 /*
2207 * If we're ignoring parity and break indicators,
2208 * ignore overruns too (for real raw support).
2209 */
2210 if (termios->c_iflag & IGNPAR)
2211 port->ignore_status_mask |= ATMEL_US_OVRE;
2212 }
2213 /* TODO: Ignore all characters if CREAD is set.*/
2214
2215 /* update the per-port timeout */
2216 uart_update_timeout(port, termios->c_cflag, baud);
2217
2218 /*
2219 * save/disable interrupts. The tty layer will ensure that the
2220 * transmitter is empty if requested by the caller, so there's
2221 * no need to wait for it here.
2222 */
2223 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2224 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2225
2226 /* disable receiver and transmitter */
2227 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2228 atmel_port->tx_stopped = true;
2229
2230 /* mode */
2231 if (port->rs485.flags & SER_RS485_ENABLED) {
2232 atmel_uart_writel(port, ATMEL_US_TTGR,
2233 port->rs485.delay_rts_after_send);
2234 mode |= ATMEL_US_USMODE_RS485;
2235 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2236 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2237 /* select mck clock, and output */
2238 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2239 /* set max iterations */
2240 mode |= ATMEL_US_MAX_ITER(3);
2241 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2242 == SER_ISO7816_T(0))
2243 mode |= ATMEL_US_USMODE_ISO7816_T0;
2244 else
2245 mode |= ATMEL_US_USMODE_ISO7816_T1;
2246 } else if (termios->c_cflag & CRTSCTS) {
2247 /* RS232 with hardware handshake (RTS/CTS) */
2248 if (atmel_use_fifo(port) &&
2249 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2250 /*
2251 * with ATMEL_US_USMODE_HWHS set, the controller will
2252 * be able to drive the RTS pin high/low when the RX
2253 * FIFO is above RXFTHRES/below RXFTHRES2.
2254 * It will also disable the transmitter when the CTS
2255 * pin is high.
2256 * This mode is not activated if CTS pin is a GPIO
2257 * because in this case, the transmitter is always
2258 * disabled (there must be an internal pull-up
2259 * responsible for this behaviour).
2260 * If the RTS pin is a GPIO, the controller won't be
2261 * able to drive it according to the FIFO thresholds,
2262 * but it will be handled by the driver.
2263 */
2264 mode |= ATMEL_US_USMODE_HWHS;
2265 } else {
2266 /*
2267 * For platforms without FIFO, the flow control is
2268 * handled by the driver.
2269 */
2270 mode |= ATMEL_US_USMODE_NORMAL;
2271 }
2272 } else {
2273 /* RS232 without hadware handshake */
2274 mode |= ATMEL_US_USMODE_NORMAL;
2275 }
2276
2277 /*
2278 * Set the baud rate:
2279 * Fractional baudrate allows to setup output frequency more
2280 * accurately. This feature is enabled only when using normal mode.
2281 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2282 * Currently, OVER is always set to 0 so we get
2283 * baudrate = selected clock / (16 * (CD + FP / 8))
2284 * then
2285 * 8 CD + FP = selected clock / (2 * baudrate)
2286 */
2287 if (atmel_port->has_frac_baudrate) {
2288 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2289 cd = div >> 3;
2290 fp = div & ATMEL_US_FP_MASK;
2291 } else {
2292 cd = uart_get_divisor(port, baud);
2293 }
2294
2295 /*
2296 * If the current value of the Clock Divisor surpasses the 16 bit
2297 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
2298 * Clock implicitly divided by 8.
2299 * If the IP is UART however, keep the highest possible value for
2300 * the CD and avoid needless division of CD, since UART IP's do not
2301 * support implicit division of the Peripheral Clock.
2302 */
2303 if (atmel_port->is_usart && cd > ATMEL_US_CD) {
2304 cd /= 8;
2305 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2306 } else {
2307 cd = min_t(unsigned int, cd, ATMEL_US_CD);
2308 }
2309
2310 /*
2311 * If there is no Fractional Part, there is a high chance that
2312 * we may be able to generate a baudrate closer to the desired one
2313 * if we use the GCLK as the clock source driving the baudrate
2314 * generator.
2315 */
2316 if (!atmel_port->has_frac_baudrate) {
2317 if (__clk_is_enabled(atmel_port->gclk))
2318 clk_disable_unprepare(atmel_port->gclk);
2319 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
2320 actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
2321 if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
2322 abs(atmel_error_rate(baud, gclk_rate / 16))) {
2323 clk_set_rate(atmel_port->gclk, 16 * baud);
2324 ret = clk_prepare_enable(atmel_port->gclk);
2325 if (ret)
2326 goto gclk_fail;
2327
2328 if (atmel_port->is_usart) {
2329 mode &= ~ATMEL_US_USCLKS;
2330 mode |= ATMEL_US_USCLKS_GCLK;
2331 } else {
2332 mode |= ATMEL_UA_BRSRCCK;
2333 }
2334
2335 /*
2336 * Set the Clock Divisor for GCLK to 1.
2337 * Since we were able to generate the smallest
2338 * multiple of the desired baudrate times 16,
2339 * then we surely can generate a bigger multiple
2340 * with the exact error rate for an equally increased
2341 * CD. Thus no need to take into account
2342 * a higher value for CD.
2343 */
2344 cd = 1;
2345 }
2346 }
2347
2348gclk_fail:
2349 quot = cd | fp << ATMEL_US_FP_OFFSET;
2350
2351 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2352 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2353
2354 /* set the mode, clock divisor, parity, stop bits and data size */
2355 atmel_uart_writel(port, ATMEL_US_MR, mode);
2356
2357 /*
2358 * when switching the mode, set the RTS line state according to the
2359 * new mode, otherwise keep the former state
2360 */
2361 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2362 unsigned int rts_state;
2363
2364 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2365 /* let the hardware control the RTS line */
2366 rts_state = ATMEL_US_RTSDIS;
2367 } else {
2368 /* force RTS line to low level */
2369 rts_state = ATMEL_US_RTSEN;
2370 }
2371
2372 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2373 }
2374
2375 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2376 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2377 atmel_port->tx_stopped = false;
2378
2379 /* restore interrupts */
2380 atmel_uart_writel(port, ATMEL_US_IER, imr);
2381
2382 /* CTS flow-control and modem-status interrupts */
2383 if (UART_ENABLE_MS(port, termios->c_cflag))
2384 atmel_enable_ms(port);
2385 else
2386 atmel_disable_ms(port);
2387
2388 uart_port_unlock_irqrestore(port, flags);
2389}
2390
2391static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2392{
2393 if (termios->c_line == N_PPS) {
2394 port->flags |= UPF_HARDPPS_CD;
2395 uart_port_lock_irq(port);
2396 atmel_enable_ms(port);
2397 uart_port_unlock_irq(port);
2398 } else {
2399 port->flags &= ~UPF_HARDPPS_CD;
2400 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2401 uart_port_lock_irq(port);
2402 atmel_disable_ms(port);
2403 uart_port_unlock_irq(port);
2404 }
2405 }
2406}
2407
2408/*
2409 * Return string describing the specified port
2410 */
2411static const char *atmel_type(struct uart_port *port)
2412{
2413 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2414}
2415
2416/*
2417 * Release the memory region(s) being used by 'port'.
2418 */
2419static void atmel_release_port(struct uart_port *port)
2420{
2421 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2422 int size = resource_size(mpdev->resource);
2423
2424 release_mem_region(port->mapbase, size);
2425
2426 if (port->flags & UPF_IOREMAP) {
2427 iounmap(port->membase);
2428 port->membase = NULL;
2429 }
2430}
2431
2432/*
2433 * Request the memory region(s) being used by 'port'.
2434 */
2435static int atmel_request_port(struct uart_port *port)
2436{
2437 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2438 int size = resource_size(mpdev->resource);
2439
2440 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2441 return -EBUSY;
2442
2443 if (port->flags & UPF_IOREMAP) {
2444 port->membase = ioremap(port->mapbase, size);
2445 if (port->membase == NULL) {
2446 release_mem_region(port->mapbase, size);
2447 return -ENOMEM;
2448 }
2449 }
2450
2451 return 0;
2452}
2453
2454/*
2455 * Configure/autoconfigure the port.
2456 */
2457static void atmel_config_port(struct uart_port *port, int flags)
2458{
2459 if (flags & UART_CONFIG_TYPE) {
2460 port->type = PORT_ATMEL;
2461 atmel_request_port(port);
2462 }
2463}
2464
2465/*
2466 * Verify the new serial_struct (for TIOCSSERIAL).
2467 */
2468static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2469{
2470 int ret = 0;
2471 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2472 ret = -EINVAL;
2473 if (port->irq != ser->irq)
2474 ret = -EINVAL;
2475 if (ser->io_type != SERIAL_IO_MEM)
2476 ret = -EINVAL;
2477 if (port->uartclk / 16 != ser->baud_base)
2478 ret = -EINVAL;
2479 if (port->mapbase != (unsigned long)ser->iomem_base)
2480 ret = -EINVAL;
2481 if (port->iobase != ser->port)
2482 ret = -EINVAL;
2483 if (ser->hub6 != 0)
2484 ret = -EINVAL;
2485 return ret;
2486}
2487
2488#ifdef CONFIG_CONSOLE_POLL
2489static int atmel_poll_get_char(struct uart_port *port)
2490{
2491 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2492 cpu_relax();
2493
2494 return atmel_uart_read_char(port);
2495}
2496
2497static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2498{
2499 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2500 cpu_relax();
2501
2502 atmel_uart_write_char(port, ch);
2503}
2504#endif
2505
2506static const struct uart_ops atmel_pops = {
2507 .tx_empty = atmel_tx_empty,
2508 .set_mctrl = atmel_set_mctrl,
2509 .get_mctrl = atmel_get_mctrl,
2510 .stop_tx = atmel_stop_tx,
2511 .start_tx = atmel_start_tx,
2512 .stop_rx = atmel_stop_rx,
2513 .enable_ms = atmel_enable_ms,
2514 .break_ctl = atmel_break_ctl,
2515 .startup = atmel_startup,
2516 .shutdown = atmel_shutdown,
2517 .flush_buffer = atmel_flush_buffer,
2518 .set_termios = atmel_set_termios,
2519 .set_ldisc = atmel_set_ldisc,
2520 .type = atmel_type,
2521 .release_port = atmel_release_port,
2522 .request_port = atmel_request_port,
2523 .config_port = atmel_config_port,
2524 .verify_port = atmel_verify_port,
2525 .pm = atmel_serial_pm,
2526#ifdef CONFIG_CONSOLE_POLL
2527 .poll_get_char = atmel_poll_get_char,
2528 .poll_put_char = atmel_poll_put_char,
2529#endif
2530};
2531
2532static const struct serial_rs485 atmel_rs485_supported = {
2533 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
2534 .delay_rts_before_send = 1,
2535 .delay_rts_after_send = 1,
2536};
2537
2538/*
2539 * Configure the port from the platform device resource info.
2540 */
2541static int atmel_init_port(struct atmel_uart_port *atmel_port,
2542 struct platform_device *pdev)
2543{
2544 int ret;
2545 struct uart_port *port = &atmel_port->uart;
2546 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2547
2548 atmel_init_property(atmel_port, pdev);
2549 atmel_set_ops(port);
2550
2551 port->iotype = UPIO_MEM;
2552 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2553 port->ops = &atmel_pops;
2554 port->fifosize = 1;
2555 port->dev = &pdev->dev;
2556 port->mapbase = mpdev->resource[0].start;
2557 port->irq = platform_get_irq(mpdev, 0);
2558 port->rs485_config = atmel_config_rs485;
2559 port->rs485_supported = atmel_rs485_supported;
2560 port->iso7816_config = atmel_config_iso7816;
2561 port->membase = NULL;
2562
2563 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2564
2565 ret = uart_get_rs485_mode(port);
2566 if (ret)
2567 return ret;
2568
2569 port->uartclk = clk_get_rate(atmel_port->clk);
2570
2571 /*
2572 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2573 * ENDTX|TXBUFE
2574 */
2575 if (atmel_uart_is_half_duplex(port))
2576 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2577 else if (atmel_use_pdc_tx(port)) {
2578 port->fifosize = PDC_BUFFER_SIZE;
2579 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2580 } else {
2581 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2582 }
2583
2584 return 0;
2585}
2586
2587#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2588static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
2589{
2590 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2591 cpu_relax();
2592 atmel_uart_write_char(port, ch);
2593}
2594
2595/*
2596 * Interrupts are disabled on entering
2597 */
2598static void atmel_console_write(struct console *co, const char *s, u_int count)
2599{
2600 struct uart_port *port = &atmel_ports[co->index].uart;
2601 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2602 unsigned int status, imr;
2603 unsigned int pdc_tx;
2604
2605 /*
2606 * First, save IMR and then disable interrupts
2607 */
2608 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2609 atmel_uart_writel(port, ATMEL_US_IDR,
2610 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2611
2612 /* Store PDC transmit status and disable it */
2613 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2614 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2615
2616 /* Make sure that tx path is actually able to send characters */
2617 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2618 atmel_port->tx_stopped = false;
2619
2620 uart_console_write(port, s, count, atmel_console_putchar);
2621
2622 /*
2623 * Finally, wait for transmitter to become empty
2624 * and restore IMR
2625 */
2626 do {
2627 status = atmel_uart_readl(port, ATMEL_US_CSR);
2628 } while (!(status & ATMEL_US_TXRDY));
2629
2630 /* Restore PDC transmit status */
2631 if (pdc_tx)
2632 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2633
2634 /* set interrupts back the way they were */
2635 atmel_uart_writel(port, ATMEL_US_IER, imr);
2636}
2637
2638/*
2639 * If the port was already initialised (eg, by a boot loader),
2640 * try to determine the current setup.
2641 */
2642static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2643 int *parity, int *bits)
2644{
2645 unsigned int mr, quot;
2646
2647 /*
2648 * If the baud rate generator isn't running, the port wasn't
2649 * initialized by the boot loader.
2650 */
2651 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2652 if (!quot)
2653 return;
2654
2655 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2656 if (mr == ATMEL_US_CHRL_8)
2657 *bits = 8;
2658 else
2659 *bits = 7;
2660
2661 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2662 if (mr == ATMEL_US_PAR_EVEN)
2663 *parity = 'e';
2664 else if (mr == ATMEL_US_PAR_ODD)
2665 *parity = 'o';
2666
2667 *baud = port->uartclk / (16 * quot);
2668}
2669
2670static int __init atmel_console_setup(struct console *co, char *options)
2671{
2672 struct uart_port *port = &atmel_ports[co->index].uart;
2673 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2674 int baud = 115200;
2675 int bits = 8;
2676 int parity = 'n';
2677 int flow = 'n';
2678
2679 if (port->membase == NULL) {
2680 /* Port not initialized yet - delay setup */
2681 return -ENODEV;
2682 }
2683
2684 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2685 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2686 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2687 atmel_port->tx_stopped = false;
2688
2689 if (options)
2690 uart_parse_options(options, &baud, &parity, &bits, &flow);
2691 else
2692 atmel_console_get_options(port, &baud, &parity, &bits);
2693
2694 return uart_set_options(port, co, baud, parity, bits, flow);
2695}
2696
2697static struct uart_driver atmel_uart;
2698
2699static struct console atmel_console = {
2700 .name = ATMEL_DEVICENAME,
2701 .write = atmel_console_write,
2702 .device = uart_console_device,
2703 .setup = atmel_console_setup,
2704 .flags = CON_PRINTBUFFER,
2705 .index = -1,
2706 .data = &atmel_uart,
2707};
2708
2709static void atmel_serial_early_write(struct console *con, const char *s,
2710 unsigned int n)
2711{
2712 struct earlycon_device *dev = con->data;
2713
2714 uart_console_write(&dev->port, s, n, atmel_console_putchar);
2715}
2716
2717static int __init atmel_early_console_setup(struct earlycon_device *device,
2718 const char *options)
2719{
2720 if (!device->port.membase)
2721 return -ENODEV;
2722
2723 device->con->write = atmel_serial_early_write;
2724
2725 return 0;
2726}
2727
2728OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2729 atmel_early_console_setup);
2730OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2731 atmel_early_console_setup);
2732
2733#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2734
2735#else
2736#define ATMEL_CONSOLE_DEVICE NULL
2737#endif
2738
2739static struct uart_driver atmel_uart = {
2740 .owner = THIS_MODULE,
2741 .driver_name = "atmel_serial",
2742 .dev_name = ATMEL_DEVICENAME,
2743 .major = SERIAL_ATMEL_MAJOR,
2744 .minor = MINOR_START,
2745 .nr = ATMEL_MAX_UART,
2746 .cons = ATMEL_CONSOLE_DEVICE,
2747};
2748
2749static bool atmel_serial_clk_will_stop(void)
2750{
2751#ifdef CONFIG_ARCH_AT91
2752 return at91_suspend_entering_slow_clock();
2753#else
2754 return false;
2755#endif
2756}
2757
2758static int __maybe_unused atmel_serial_suspend(struct device *dev)
2759{
2760 struct uart_port *port = dev_get_drvdata(dev);
2761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2762
2763 if (uart_console(port) && console_suspend_enabled) {
2764 /* Drain the TX shifter */
2765 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2766 ATMEL_US_TXEMPTY))
2767 cpu_relax();
2768 }
2769
2770 if (uart_console(port) && !console_suspend_enabled) {
2771 /* Cache register values as we won't get a full shutdown/startup
2772 * cycle
2773 */
2774 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2775 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2776 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2777 atmel_port->cache.rtor = atmel_uart_readl(port,
2778 atmel_port->rtor);
2779 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2780 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2781 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2782 }
2783
2784 /* we can not wake up if we're running on slow clock */
2785 atmel_port->may_wakeup = device_may_wakeup(dev);
2786 if (atmel_serial_clk_will_stop()) {
2787 unsigned long flags;
2788
2789 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2790 atmel_port->suspended = true;
2791 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2792 device_set_wakeup_enable(dev, 0);
2793 }
2794
2795 uart_suspend_port(&atmel_uart, port);
2796
2797 return 0;
2798}
2799
2800static int __maybe_unused atmel_serial_resume(struct device *dev)
2801{
2802 struct uart_port *port = dev_get_drvdata(dev);
2803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2804 unsigned long flags;
2805
2806 if (uart_console(port) && !console_suspend_enabled) {
2807 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2808 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2809 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2810 atmel_uart_writel(port, atmel_port->rtor,
2811 atmel_port->cache.rtor);
2812 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2813
2814 if (atmel_port->fifo_size) {
2815 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2816 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2817 atmel_uart_writel(port, ATMEL_US_FMR,
2818 atmel_port->cache.fmr);
2819 atmel_uart_writel(port, ATMEL_US_FIER,
2820 atmel_port->cache.fimr);
2821 }
2822 atmel_start_rx(port);
2823 }
2824
2825 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2826 if (atmel_port->pending) {
2827 atmel_handle_receive(port, atmel_port->pending);
2828 atmel_handle_status(port, atmel_port->pending,
2829 atmel_port->pending_status);
2830 atmel_handle_transmit(port, atmel_port->pending);
2831 atmel_port->pending = 0;
2832 }
2833 atmel_port->suspended = false;
2834 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2835
2836 uart_resume_port(&atmel_uart, port);
2837 device_set_wakeup_enable(dev, atmel_port->may_wakeup);
2838
2839 return 0;
2840}
2841
2842static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2843 struct platform_device *pdev)
2844{
2845 atmel_port->fifo_size = 0;
2846 atmel_port->rts_low = 0;
2847 atmel_port->rts_high = 0;
2848
2849 if (of_property_read_u32(pdev->dev.of_node,
2850 "atmel,fifo-size",
2851 &atmel_port->fifo_size))
2852 return;
2853
2854 if (!atmel_port->fifo_size)
2855 return;
2856
2857 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2858 atmel_port->fifo_size = 0;
2859 dev_err(&pdev->dev, "Invalid FIFO size\n");
2860 return;
2861 }
2862
2863 /*
2864 * 0 <= rts_low <= rts_high <= fifo_size
2865 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2866 * to flush their internal TX FIFO, commonly up to 16 data, before
2867 * actually stopping to send new data. So we try to set the RTS High
2868 * Threshold to a reasonably high value respecting this 16 data
2869 * empirical rule when possible.
2870 */
2871 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2872 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2873 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2874 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2875
2876 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2877 atmel_port->fifo_size);
2878 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2879 atmel_port->rts_high);
2880 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2881 atmel_port->rts_low);
2882}
2883
2884static int atmel_serial_probe(struct platform_device *pdev)
2885{
2886 struct atmel_uart_port *atmel_port;
2887 struct device_node *np = pdev->dev.parent->of_node;
2888 void *data;
2889 int ret;
2890 bool rs485_enabled;
2891
2892 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2893
2894 /*
2895 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2896 * as compatible string. This driver is probed by at91-usart mfd driver
2897 * which is just a wrapper over the atmel_serial driver and
2898 * spi-at91-usart driver. All attributes needed by this driver are
2899 * found in of_node of parent.
2900 */
2901 pdev->dev.of_node = np;
2902
2903 ret = of_alias_get_id(np, "serial");
2904 if (ret < 0)
2905 /* port id not found in platform data nor device-tree aliases:
2906 * auto-enumerate it */
2907 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2908
2909 if (ret >= ATMEL_MAX_UART) {
2910 ret = -ENODEV;
2911 goto err;
2912 }
2913
2914 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2915 /* port already in use */
2916 ret = -EBUSY;
2917 goto err;
2918 }
2919
2920 atmel_port = &atmel_ports[ret];
2921 atmel_port->backup_imr = 0;
2922 atmel_port->uart.line = ret;
2923 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2924 atmel_serial_probe_fifos(atmel_port, pdev);
2925
2926 atomic_set(&atmel_port->tasklet_shutdown, 0);
2927 spin_lock_init(&atmel_port->lock_suspended);
2928
2929 atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2930 if (IS_ERR(atmel_port->clk)) {
2931 ret = PTR_ERR(atmel_port->clk);
2932 goto err;
2933 }
2934 ret = clk_prepare_enable(atmel_port->clk);
2935 if (ret)
2936 goto err;
2937
2938 atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
2939 if (IS_ERR(atmel_port->gclk)) {
2940 ret = PTR_ERR(atmel_port->gclk);
2941 goto err_clk_disable_unprepare;
2942 }
2943
2944 ret = atmel_init_port(atmel_port, pdev);
2945 if (ret)
2946 goto err_clk_disable_unprepare;
2947
2948 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2949 if (IS_ERR(atmel_port->gpios)) {
2950 ret = PTR_ERR(atmel_port->gpios);
2951 goto err_clk_disable_unprepare;
2952 }
2953
2954 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2955 ret = -ENOMEM;
2956 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2957 sizeof(struct atmel_uart_char),
2958 GFP_KERNEL);
2959 if (!data)
2960 goto err_clk_disable_unprepare;
2961 atmel_port->rx_ring.buf = data;
2962 }
2963
2964 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2965
2966 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2967 if (ret)
2968 goto err_add_port;
2969
2970 device_init_wakeup(&pdev->dev, 1);
2971 platform_set_drvdata(pdev, atmel_port);
2972
2973 if (rs485_enabled) {
2974 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2975 ATMEL_US_USMODE_NORMAL);
2976 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2977 ATMEL_US_RTSEN);
2978 }
2979
2980 /*
2981 * Get port name of usart or uart
2982 */
2983 atmel_get_ip_name(&atmel_port->uart);
2984
2985 /*
2986 * The peripheral clock can now safely be disabled till the port
2987 * is used
2988 */
2989 clk_disable_unprepare(atmel_port->clk);
2990
2991 return 0;
2992
2993err_add_port:
2994 kfree(atmel_port->rx_ring.buf);
2995 atmel_port->rx_ring.buf = NULL;
2996err_clk_disable_unprepare:
2997 clk_disable_unprepare(atmel_port->clk);
2998 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2999err:
3000 return ret;
3001}
3002
3003/*
3004 * Even if the driver is not modular, it makes sense to be able to
3005 * unbind a device: there can be many bound devices, and there are
3006 * situations where dynamic binding and unbinding can be useful.
3007 *
3008 * For example, a connected device can require a specific firmware update
3009 * protocol that needs bitbanging on IO lines, but use the regular serial
3010 * port in the normal case.
3011 */
3012static void atmel_serial_remove(struct platform_device *pdev)
3013{
3014 struct uart_port *port = platform_get_drvdata(pdev);
3015 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
3016
3017 tasklet_kill(&atmel_port->tasklet_rx);
3018 tasklet_kill(&atmel_port->tasklet_tx);
3019
3020 device_init_wakeup(&pdev->dev, 0);
3021
3022 uart_remove_one_port(&atmel_uart, port);
3023
3024 kfree(atmel_port->rx_ring.buf);
3025
3026 /* "port" is allocated statically, so we shouldn't free it */
3027
3028 clear_bit(port->line, atmel_ports_in_use);
3029
3030 pdev->dev.of_node = NULL;
3031}
3032
3033static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
3034 atmel_serial_resume);
3035
3036static struct platform_driver atmel_serial_driver = {
3037 .probe = atmel_serial_probe,
3038 .remove_new = atmel_serial_remove,
3039 .driver = {
3040 .name = "atmel_usart_serial",
3041 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3042 .pm = pm_ptr(&atmel_serial_pm_ops),
3043 },
3044};
3045
3046static int __init atmel_serial_init(void)
3047{
3048 int ret;
3049
3050 ret = uart_register_driver(&atmel_uart);
3051 if (ret)
3052 return ret;
3053
3054 ret = platform_driver_register(&atmel_serial_driver);
3055 if (ret)
3056 uart_unregister_driver(&atmel_uart);
3057
3058 return ret;
3059}
3060device_initcall(atmel_serial_init);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11#include <linux/tty.h>
12#include <linux/ioport.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/serial.h>
16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/sysrq.h>
19#include <linux/tty_flip.h>
20#include <linux/platform_device.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_gpio.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/atmel_pdc.h>
27#include <linux/uaccess.h>
28#include <linux/platform_data/atmel.h>
29#include <linux/timer.h>
30#include <linux/gpio.h>
31#include <linux/gpio/consumer.h>
32#include <linux/err.h>
33#include <linux/irq.h>
34#include <linux/suspend.h>
35#include <linux/mm.h>
36
37#include <asm/div64.h>
38#include <asm/io.h>
39#include <asm/ioctls.h>
40
41#define PDC_BUFFER_SIZE 512
42/* Revisit: We should calculate this based on the actual port settings */
43#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
44
45/* The minium number of data FIFOs should be able to contain */
46#define ATMEL_MIN_FIFO_SIZE 8
47/*
48 * These two offsets are substracted from the RX FIFO size to define the RTS
49 * high and low thresholds
50 */
51#define ATMEL_RTS_HIGH_OFFSET 16
52#define ATMEL_RTS_LOW_OFFSET 20
53
54#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
55#define SUPPORT_SYSRQ
56#endif
57
58#include <linux/serial_core.h>
59
60#include "serial_mctrl_gpio.h"
61#include "atmel_serial.h"
62
63static void atmel_start_rx(struct uart_port *port);
64static void atmel_stop_rx(struct uart_port *port);
65
66#ifdef CONFIG_SERIAL_ATMEL_TTYAT
67
68/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
69 * should coexist with the 8250 driver, such as if we have an external 16C550
70 * UART. */
71#define SERIAL_ATMEL_MAJOR 204
72#define MINOR_START 154
73#define ATMEL_DEVICENAME "ttyAT"
74
75#else
76
77/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
78 * name, but it is legally reserved for the 8250 driver. */
79#define SERIAL_ATMEL_MAJOR TTY_MAJOR
80#define MINOR_START 64
81#define ATMEL_DEVICENAME "ttyS"
82
83#endif
84
85#define ATMEL_ISR_PASS_LIMIT 256
86
87struct atmel_dma_buffer {
88 unsigned char *buf;
89 dma_addr_t dma_addr;
90 unsigned int dma_size;
91 unsigned int ofs;
92};
93
94struct atmel_uart_char {
95 u16 status;
96 u16 ch;
97};
98
99/*
100 * Be careful, the real size of the ring buffer is
101 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
102 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
103 * DMA mode.
104 */
105#define ATMEL_SERIAL_RINGSIZE 1024
106
107/*
108 * at91: 6 USARTs and one DBGU port (SAM9260)
109 * samx7: 3 USARTs and 5 UARTs
110 */
111#define ATMEL_MAX_UART 8
112
113/*
114 * We wrap our port structure around the generic uart_port.
115 */
116struct atmel_uart_port {
117 struct uart_port uart; /* uart */
118 struct clk *clk; /* uart clock */
119 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
120 u32 backup_imr; /* IMR saved during suspend */
121 int break_active; /* break being received */
122
123 bool use_dma_rx; /* enable DMA receiver */
124 bool use_pdc_rx; /* enable PDC receiver */
125 short pdc_rx_idx; /* current PDC RX buffer */
126 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
127
128 bool use_dma_tx; /* enable DMA transmitter */
129 bool use_pdc_tx; /* enable PDC transmitter */
130 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
131
132 spinlock_t lock_tx; /* port lock */
133 spinlock_t lock_rx; /* port lock */
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136 struct dma_async_tx_descriptor *desc_tx;
137 struct dma_async_tx_descriptor *desc_rx;
138 dma_cookie_t cookie_tx;
139 dma_cookie_t cookie_rx;
140 struct scatterlist sg_tx;
141 struct scatterlist sg_rx;
142 struct tasklet_struct tasklet_rx;
143 struct tasklet_struct tasklet_tx;
144 atomic_t tasklet_shutdown;
145 unsigned int irq_status_prev;
146 unsigned int tx_len;
147
148 struct circ_buf rx_ring;
149
150 struct mctrl_gpios *gpios;
151 u32 backup_mode; /* MR saved during iso7816 operations */
152 u32 backup_brgr; /* BRGR saved during iso7816 operations */
153 unsigned int tx_done_mask;
154 u32 fifo_size;
155 u32 rts_high;
156 u32 rts_low;
157 bool ms_irq_enabled;
158 u32 rtor; /* address of receiver timeout register if it exists */
159 bool has_frac_baudrate;
160 bool has_hw_timer;
161 struct timer_list uart_timer;
162
163 bool tx_stopped;
164 bool suspended;
165 unsigned int pending;
166 unsigned int pending_status;
167 spinlock_t lock_suspended;
168
169 bool hd_start_rx; /* can start RX during half-duplex operation */
170
171 /* ISO7816 */
172 unsigned int fidi_min;
173 unsigned int fidi_max;
174
175#ifdef CONFIG_PM
176 struct {
177 u32 cr;
178 u32 mr;
179 u32 imr;
180 u32 brgr;
181 u32 rtor;
182 u32 ttgr;
183 u32 fmr;
184 u32 fimr;
185 } cache;
186#endif
187
188 int (*prepare_rx)(struct uart_port *port);
189 int (*prepare_tx)(struct uart_port *port);
190 void (*schedule_rx)(struct uart_port *port);
191 void (*schedule_tx)(struct uart_port *port);
192 void (*release_rx)(struct uart_port *port);
193 void (*release_tx)(struct uart_port *port);
194};
195
196static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
197static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
198
199#ifdef SUPPORT_SYSRQ
200static struct console atmel_console;
201#endif
202
203#if defined(CONFIG_OF)
204static const struct of_device_id atmel_serial_dt_ids[] = {
205 { .compatible = "atmel,at91rm9200-usart-serial" },
206 { /* sentinel */ }
207};
208#endif
209
210static inline struct atmel_uart_port *
211to_atmel_uart_port(struct uart_port *uart)
212{
213 return container_of(uart, struct atmel_uart_port, uart);
214}
215
216static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
217{
218 return __raw_readl(port->membase + reg);
219}
220
221static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
222{
223 __raw_writel(value, port->membase + reg);
224}
225
226static inline u8 atmel_uart_read_char(struct uart_port *port)
227{
228 return __raw_readb(port->membase + ATMEL_US_RHR);
229}
230
231static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
232{
233 __raw_writeb(value, port->membase + ATMEL_US_THR);
234}
235
236static inline int atmel_uart_is_half_duplex(struct uart_port *port)
237{
238 return ((port->rs485.flags & SER_RS485_ENABLED) &&
239 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
240 (port->iso7816.flags & SER_ISO7816_ENABLED);
241}
242
243#ifdef CONFIG_SERIAL_ATMEL_PDC
244static bool atmel_use_pdc_rx(struct uart_port *port)
245{
246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
247
248 return atmel_port->use_pdc_rx;
249}
250
251static bool atmel_use_pdc_tx(struct uart_port *port)
252{
253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
254
255 return atmel_port->use_pdc_tx;
256}
257#else
258static bool atmel_use_pdc_rx(struct uart_port *port)
259{
260 return false;
261}
262
263static bool atmel_use_pdc_tx(struct uart_port *port)
264{
265 return false;
266}
267#endif
268
269static bool atmel_use_dma_tx(struct uart_port *port)
270{
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
272
273 return atmel_port->use_dma_tx;
274}
275
276static bool atmel_use_dma_rx(struct uart_port *port)
277{
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279
280 return atmel_port->use_dma_rx;
281}
282
283static bool atmel_use_fifo(struct uart_port *port)
284{
285 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
286
287 return atmel_port->fifo_size;
288}
289
290static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
291 struct tasklet_struct *t)
292{
293 if (!atomic_read(&atmel_port->tasklet_shutdown))
294 tasklet_schedule(t);
295}
296
297/* Enable or disable the rs485 support */
298static int atmel_config_rs485(struct uart_port *port,
299 struct serial_rs485 *rs485conf)
300{
301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
302 unsigned int mode;
303
304 /* Disable interrupts */
305 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
306
307 mode = atmel_uart_readl(port, ATMEL_US_MR);
308
309 /* Resetting serial mode to RS232 (0x0) */
310 mode &= ~ATMEL_US_USMODE;
311
312 port->rs485 = *rs485conf;
313
314 if (rs485conf->flags & SER_RS485_ENABLED) {
315 dev_dbg(port->dev, "Setting UART to RS485\n");
316 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
317 atmel_uart_writel(port, ATMEL_US_TTGR,
318 rs485conf->delay_rts_after_send);
319 mode |= ATMEL_US_USMODE_RS485;
320 } else {
321 dev_dbg(port->dev, "Setting UART to RS232\n");
322 if (atmel_use_pdc_tx(port))
323 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
324 ATMEL_US_TXBUFE;
325 else
326 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
327 }
328 atmel_uart_writel(port, ATMEL_US_MR, mode);
329
330 /* Enable interrupts */
331 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
332
333 return 0;
334}
335
336static unsigned int atmel_calc_cd(struct uart_port *port,
337 struct serial_iso7816 *iso7816conf)
338{
339 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
340 unsigned int cd;
341 u64 mck_rate;
342
343 mck_rate = (u64)clk_get_rate(atmel_port->clk);
344 do_div(mck_rate, iso7816conf->clk);
345 cd = mck_rate;
346 return cd;
347}
348
349static unsigned int atmel_calc_fidi(struct uart_port *port,
350 struct serial_iso7816 *iso7816conf)
351{
352 u64 fidi = 0;
353
354 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
355 fidi = (u64)iso7816conf->sc_fi;
356 do_div(fidi, iso7816conf->sc_di);
357 }
358 return (u32)fidi;
359}
360
361/* Enable or disable the iso7816 support */
362/* Called with interrupts disabled */
363static int atmel_config_iso7816(struct uart_port *port,
364 struct serial_iso7816 *iso7816conf)
365{
366 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
367 unsigned int mode;
368 unsigned int cd, fidi;
369 int ret = 0;
370
371 /* Disable interrupts */
372 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
373
374 mode = atmel_uart_readl(port, ATMEL_US_MR);
375
376 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
377 mode &= ~ATMEL_US_USMODE;
378
379 if (iso7816conf->tg > 255) {
380 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
381 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
382 ret = -EINVAL;
383 goto err_out;
384 }
385
386 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
387 == SER_ISO7816_T(0)) {
388 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
389 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
390 == SER_ISO7816_T(1)) {
391 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
392 } else {
393 dev_err(port->dev, "ISO7816: Type not supported\n");
394 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
395 ret = -EINVAL;
396 goto err_out;
397 }
398
399 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
400
401 /* select mck clock, and output */
402 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
403 /* set parity for normal/inverse mode + max iterations */
404 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
405
406 cd = atmel_calc_cd(port, iso7816conf);
407 fidi = atmel_calc_fidi(port, iso7816conf);
408 if (fidi == 0) {
409 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
410 } else if (fidi < atmel_port->fidi_min
411 || fidi > atmel_port->fidi_max) {
412 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
413 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
414 ret = -EINVAL;
415 goto err_out;
416 }
417
418 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
419 /* port not yet in iso7816 mode: store configuration */
420 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
421 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
422 }
423
424 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
425 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
426 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
427
428 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
429 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
430 } else {
431 dev_dbg(port->dev, "Setting UART back to RS232\n");
432 /* back to last RS232 settings */
433 mode = atmel_port->backup_mode;
434 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
435 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
436 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
437 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
438
439 if (atmel_use_pdc_tx(port))
440 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
441 ATMEL_US_TXBUFE;
442 else
443 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
444 }
445
446 port->iso7816 = *iso7816conf;
447
448 atmel_uart_writel(port, ATMEL_US_MR, mode);
449
450err_out:
451 /* Enable interrupts */
452 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
453
454 return ret;
455}
456
457/*
458 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
459 */
460static u_int atmel_tx_empty(struct uart_port *port)
461{
462 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
463
464 if (atmel_port->tx_stopped)
465 return TIOCSER_TEMT;
466 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
467 TIOCSER_TEMT :
468 0;
469}
470
471/*
472 * Set state of the modem control output lines
473 */
474static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
475{
476 unsigned int control = 0;
477 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
478 unsigned int rts_paused, rts_ready;
479 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
480
481 /* override mode to RS485 if needed, otherwise keep the current mode */
482 if (port->rs485.flags & SER_RS485_ENABLED) {
483 atmel_uart_writel(port, ATMEL_US_TTGR,
484 port->rs485.delay_rts_after_send);
485 mode &= ~ATMEL_US_USMODE;
486 mode |= ATMEL_US_USMODE_RS485;
487 }
488
489 /* set the RTS line state according to the mode */
490 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
491 /* force RTS line to high level */
492 rts_paused = ATMEL_US_RTSEN;
493
494 /* give the control of the RTS line back to the hardware */
495 rts_ready = ATMEL_US_RTSDIS;
496 } else {
497 /* force RTS line to high level */
498 rts_paused = ATMEL_US_RTSDIS;
499
500 /* force RTS line to low level */
501 rts_ready = ATMEL_US_RTSEN;
502 }
503
504 if (mctrl & TIOCM_RTS)
505 control |= rts_ready;
506 else
507 control |= rts_paused;
508
509 if (mctrl & TIOCM_DTR)
510 control |= ATMEL_US_DTREN;
511 else
512 control |= ATMEL_US_DTRDIS;
513
514 atmel_uart_writel(port, ATMEL_US_CR, control);
515
516 mctrl_gpio_set(atmel_port->gpios, mctrl);
517
518 /* Local loopback mode? */
519 mode &= ~ATMEL_US_CHMODE;
520 if (mctrl & TIOCM_LOOP)
521 mode |= ATMEL_US_CHMODE_LOC_LOOP;
522 else
523 mode |= ATMEL_US_CHMODE_NORMAL;
524
525 atmel_uart_writel(port, ATMEL_US_MR, mode);
526}
527
528/*
529 * Get state of the modem control input lines
530 */
531static u_int atmel_get_mctrl(struct uart_port *port)
532{
533 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
534 unsigned int ret = 0, status;
535
536 status = atmel_uart_readl(port, ATMEL_US_CSR);
537
538 /*
539 * The control signals are active low.
540 */
541 if (!(status & ATMEL_US_DCD))
542 ret |= TIOCM_CD;
543 if (!(status & ATMEL_US_CTS))
544 ret |= TIOCM_CTS;
545 if (!(status & ATMEL_US_DSR))
546 ret |= TIOCM_DSR;
547 if (!(status & ATMEL_US_RI))
548 ret |= TIOCM_RI;
549
550 return mctrl_gpio_get(atmel_port->gpios, &ret);
551}
552
553/*
554 * Stop transmitting.
555 */
556static void atmel_stop_tx(struct uart_port *port)
557{
558 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
559
560 if (atmel_use_pdc_tx(port)) {
561 /* disable PDC transmit */
562 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
563 }
564
565 /*
566 * Disable the transmitter.
567 * This is mandatory when DMA is used, otherwise the DMA buffer
568 * is fully transmitted.
569 */
570 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
571 atmel_port->tx_stopped = true;
572
573 /* Disable interrupts */
574 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
575
576 if (atmel_uart_is_half_duplex(port))
577 atmel_start_rx(port);
578
579}
580
581/*
582 * Start transmitting.
583 */
584static void atmel_start_tx(struct uart_port *port)
585{
586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
587
588 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
589 & ATMEL_PDC_TXTEN))
590 /* The transmitter is already running. Yes, we
591 really need this.*/
592 return;
593
594 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
595 if (atmel_uart_is_half_duplex(port))
596 atmel_stop_rx(port);
597
598 if (atmel_use_pdc_tx(port))
599 /* re-enable PDC transmit */
600 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
601
602 /* Enable interrupts */
603 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
604
605 /* re-enable the transmitter */
606 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
607 atmel_port->tx_stopped = false;
608}
609
610/*
611 * start receiving - port is in process of being opened.
612 */
613static void atmel_start_rx(struct uart_port *port)
614{
615 /* reset status and receiver */
616 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
617
618 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
619
620 if (atmel_use_pdc_rx(port)) {
621 /* enable PDC controller */
622 atmel_uart_writel(port, ATMEL_US_IER,
623 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
624 port->read_status_mask);
625 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
626 } else {
627 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
628 }
629}
630
631/*
632 * Stop receiving - port is in process of being closed.
633 */
634static void atmel_stop_rx(struct uart_port *port)
635{
636 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
637
638 if (atmel_use_pdc_rx(port)) {
639 /* disable PDC receive */
640 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
641 atmel_uart_writel(port, ATMEL_US_IDR,
642 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
643 port->read_status_mask);
644 } else {
645 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
646 }
647}
648
649/*
650 * Enable modem status interrupts
651 */
652static void atmel_enable_ms(struct uart_port *port)
653{
654 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
655 uint32_t ier = 0;
656
657 /*
658 * Interrupt should not be enabled twice
659 */
660 if (atmel_port->ms_irq_enabled)
661 return;
662
663 atmel_port->ms_irq_enabled = true;
664
665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
666 ier |= ATMEL_US_CTSIC;
667
668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
669 ier |= ATMEL_US_DSRIC;
670
671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
672 ier |= ATMEL_US_RIIC;
673
674 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
675 ier |= ATMEL_US_DCDIC;
676
677 atmel_uart_writel(port, ATMEL_US_IER, ier);
678
679 mctrl_gpio_enable_ms(atmel_port->gpios);
680}
681
682/*
683 * Disable modem status interrupts
684 */
685static void atmel_disable_ms(struct uart_port *port)
686{
687 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
688 uint32_t idr = 0;
689
690 /*
691 * Interrupt should not be disabled twice
692 */
693 if (!atmel_port->ms_irq_enabled)
694 return;
695
696 atmel_port->ms_irq_enabled = false;
697
698 mctrl_gpio_disable_ms(atmel_port->gpios);
699
700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
701 idr |= ATMEL_US_CTSIC;
702
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
704 idr |= ATMEL_US_DSRIC;
705
706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
707 idr |= ATMEL_US_RIIC;
708
709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
710 idr |= ATMEL_US_DCDIC;
711
712 atmel_uart_writel(port, ATMEL_US_IDR, idr);
713}
714
715/*
716 * Control the transmission of a break signal
717 */
718static void atmel_break_ctl(struct uart_port *port, int break_state)
719{
720 if (break_state != 0)
721 /* start break */
722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
723 else
724 /* stop break */
725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
726}
727
728/*
729 * Stores the incoming character in the ring buffer
730 */
731static void
732atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
733 unsigned int ch)
734{
735 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
736 struct circ_buf *ring = &atmel_port->rx_ring;
737 struct atmel_uart_char *c;
738
739 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
740 /* Buffer overflow, ignore char */
741 return;
742
743 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
744 c->status = status;
745 c->ch = ch;
746
747 /* Make sure the character is stored before we update head. */
748 smp_wmb();
749
750 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
751}
752
753/*
754 * Deal with parity, framing and overrun errors.
755 */
756static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
757{
758 /* clear error */
759 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
760
761 if (status & ATMEL_US_RXBRK) {
762 /* ignore side-effect */
763 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
764 port->icount.brk++;
765 }
766 if (status & ATMEL_US_PARE)
767 port->icount.parity++;
768 if (status & ATMEL_US_FRAME)
769 port->icount.frame++;
770 if (status & ATMEL_US_OVRE)
771 port->icount.overrun++;
772}
773
774/*
775 * Characters received (called from interrupt handler)
776 */
777static void atmel_rx_chars(struct uart_port *port)
778{
779 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
780 unsigned int status, ch;
781
782 status = atmel_uart_readl(port, ATMEL_US_CSR);
783 while (status & ATMEL_US_RXRDY) {
784 ch = atmel_uart_read_char(port);
785
786 /*
787 * note that the error handling code is
788 * out of the main execution path
789 */
790 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
791 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
792 || atmel_port->break_active)) {
793
794 /* clear error */
795 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
796
797 if (status & ATMEL_US_RXBRK
798 && !atmel_port->break_active) {
799 atmel_port->break_active = 1;
800 atmel_uart_writel(port, ATMEL_US_IER,
801 ATMEL_US_RXBRK);
802 } else {
803 /*
804 * This is either the end-of-break
805 * condition or we've received at
806 * least one character without RXBRK
807 * being set. In both cases, the next
808 * RXBRK will indicate start-of-break.
809 */
810 atmel_uart_writel(port, ATMEL_US_IDR,
811 ATMEL_US_RXBRK);
812 status &= ~ATMEL_US_RXBRK;
813 atmel_port->break_active = 0;
814 }
815 }
816
817 atmel_buffer_rx_char(port, status, ch);
818 status = atmel_uart_readl(port, ATMEL_US_CSR);
819 }
820
821 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
822}
823
824/*
825 * Transmit characters (called from tasklet with TXRDY interrupt
826 * disabled)
827 */
828static void atmel_tx_chars(struct uart_port *port)
829{
830 struct circ_buf *xmit = &port->state->xmit;
831 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
832
833 if (port->x_char &&
834 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
835 atmel_uart_write_char(port, port->x_char);
836 port->icount.tx++;
837 port->x_char = 0;
838 }
839 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
840 return;
841
842 while (atmel_uart_readl(port, ATMEL_US_CSR) &
843 atmel_port->tx_done_mask) {
844 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
845 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
846 port->icount.tx++;
847 if (uart_circ_empty(xmit))
848 break;
849 }
850
851 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
852 uart_write_wakeup(port);
853
854 if (!uart_circ_empty(xmit))
855 /* Enable interrupts */
856 atmel_uart_writel(port, ATMEL_US_IER,
857 atmel_port->tx_done_mask);
858}
859
860static void atmel_complete_tx_dma(void *arg)
861{
862 struct atmel_uart_port *atmel_port = arg;
863 struct uart_port *port = &atmel_port->uart;
864 struct circ_buf *xmit = &port->state->xmit;
865 struct dma_chan *chan = atmel_port->chan_tx;
866 unsigned long flags;
867
868 spin_lock_irqsave(&port->lock, flags);
869
870 if (chan)
871 dmaengine_terminate_all(chan);
872 xmit->tail += atmel_port->tx_len;
873 xmit->tail &= UART_XMIT_SIZE - 1;
874
875 port->icount.tx += atmel_port->tx_len;
876
877 spin_lock_irq(&atmel_port->lock_tx);
878 async_tx_ack(atmel_port->desc_tx);
879 atmel_port->cookie_tx = -EINVAL;
880 atmel_port->desc_tx = NULL;
881 spin_unlock_irq(&atmel_port->lock_tx);
882
883 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
884 uart_write_wakeup(port);
885
886 /*
887 * xmit is a circular buffer so, if we have just send data from
888 * xmit->tail to the end of xmit->buf, now we have to transmit the
889 * remaining data from the beginning of xmit->buf to xmit->head.
890 */
891 if (!uart_circ_empty(xmit))
892 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
893 else if (atmel_uart_is_half_duplex(port)) {
894 /*
895 * DMA done, re-enable TXEMPTY and signal that we can stop
896 * TX and start RX for RS485
897 */
898 atmel_port->hd_start_rx = true;
899 atmel_uart_writel(port, ATMEL_US_IER,
900 atmel_port->tx_done_mask);
901 }
902
903 spin_unlock_irqrestore(&port->lock, flags);
904}
905
906static void atmel_release_tx_dma(struct uart_port *port)
907{
908 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
909 struct dma_chan *chan = atmel_port->chan_tx;
910
911 if (chan) {
912 dmaengine_terminate_all(chan);
913 dma_release_channel(chan);
914 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
915 DMA_TO_DEVICE);
916 }
917
918 atmel_port->desc_tx = NULL;
919 atmel_port->chan_tx = NULL;
920 atmel_port->cookie_tx = -EINVAL;
921}
922
923/*
924 * Called from tasklet with TXRDY interrupt is disabled.
925 */
926static void atmel_tx_dma(struct uart_port *port)
927{
928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
929 struct circ_buf *xmit = &port->state->xmit;
930 struct dma_chan *chan = atmel_port->chan_tx;
931 struct dma_async_tx_descriptor *desc;
932 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
933 unsigned int tx_len, part1_len, part2_len, sg_len;
934 dma_addr_t phys_addr;
935
936 /* Make sure we have an idle channel */
937 if (atmel_port->desc_tx != NULL)
938 return;
939
940 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
941 /*
942 * DMA is idle now.
943 * Port xmit buffer is already mapped,
944 * and it is one page... Just adjust
945 * offsets and lengths. Since it is a circular buffer,
946 * we have to transmit till the end, and then the rest.
947 * Take the port lock to get a
948 * consistent xmit buffer state.
949 */
950 tx_len = CIRC_CNT_TO_END(xmit->head,
951 xmit->tail,
952 UART_XMIT_SIZE);
953
954 if (atmel_port->fifo_size) {
955 /* multi data mode */
956 part1_len = (tx_len & ~0x3); /* DWORD access */
957 part2_len = (tx_len & 0x3); /* BYTE access */
958 } else {
959 /* single data (legacy) mode */
960 part1_len = 0;
961 part2_len = tx_len; /* BYTE access only */
962 }
963
964 sg_init_table(sgl, 2);
965 sg_len = 0;
966 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
967 if (part1_len) {
968 sg = &sgl[sg_len++];
969 sg_dma_address(sg) = phys_addr;
970 sg_dma_len(sg) = part1_len;
971
972 phys_addr += part1_len;
973 }
974
975 if (part2_len) {
976 sg = &sgl[sg_len++];
977 sg_dma_address(sg) = phys_addr;
978 sg_dma_len(sg) = part2_len;
979 }
980
981 /*
982 * save tx_len so atmel_complete_tx_dma() will increase
983 * xmit->tail correctly
984 */
985 atmel_port->tx_len = tx_len;
986
987 desc = dmaengine_prep_slave_sg(chan,
988 sgl,
989 sg_len,
990 DMA_MEM_TO_DEV,
991 DMA_PREP_INTERRUPT |
992 DMA_CTRL_ACK);
993 if (!desc) {
994 dev_err(port->dev, "Failed to send via dma!\n");
995 return;
996 }
997
998 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
999
1000 atmel_port->desc_tx = desc;
1001 desc->callback = atmel_complete_tx_dma;
1002 desc->callback_param = atmel_port;
1003 atmel_port->cookie_tx = dmaengine_submit(desc);
1004 }
1005
1006 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1007 uart_write_wakeup(port);
1008}
1009
1010static int atmel_prepare_tx_dma(struct uart_port *port)
1011{
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1013 struct device *mfd_dev = port->dev->parent;
1014 dma_cap_mask_t mask;
1015 struct dma_slave_config config;
1016 int ret, nent;
1017
1018 dma_cap_zero(mask);
1019 dma_cap_set(DMA_SLAVE, mask);
1020
1021 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1022 if (atmel_port->chan_tx == NULL)
1023 goto chan_err;
1024 dev_info(port->dev, "using %s for tx DMA transfers\n",
1025 dma_chan_name(atmel_port->chan_tx));
1026
1027 spin_lock_init(&atmel_port->lock_tx);
1028 sg_init_table(&atmel_port->sg_tx, 1);
1029 /* UART circular tx buffer is an aligned page. */
1030 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1031 sg_set_page(&atmel_port->sg_tx,
1032 virt_to_page(port->state->xmit.buf),
1033 UART_XMIT_SIZE,
1034 offset_in_page(port->state->xmit.buf));
1035 nent = dma_map_sg(port->dev,
1036 &atmel_port->sg_tx,
1037 1,
1038 DMA_TO_DEVICE);
1039
1040 if (!nent) {
1041 dev_dbg(port->dev, "need to release resource of dma\n");
1042 goto chan_err;
1043 } else {
1044 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1045 sg_dma_len(&atmel_port->sg_tx),
1046 port->state->xmit.buf,
1047 &sg_dma_address(&atmel_port->sg_tx));
1048 }
1049
1050 /* Configure the slave DMA */
1051 memset(&config, 0, sizeof(config));
1052 config.direction = DMA_MEM_TO_DEV;
1053 config.dst_addr_width = (atmel_port->fifo_size) ?
1054 DMA_SLAVE_BUSWIDTH_4_BYTES :
1055 DMA_SLAVE_BUSWIDTH_1_BYTE;
1056 config.dst_addr = port->mapbase + ATMEL_US_THR;
1057 config.dst_maxburst = 1;
1058
1059 ret = dmaengine_slave_config(atmel_port->chan_tx,
1060 &config);
1061 if (ret) {
1062 dev_err(port->dev, "DMA tx slave configuration failed\n");
1063 goto chan_err;
1064 }
1065
1066 return 0;
1067
1068chan_err:
1069 dev_err(port->dev, "TX channel not available, switch to pio\n");
1070 atmel_port->use_dma_tx = 0;
1071 if (atmel_port->chan_tx)
1072 atmel_release_tx_dma(port);
1073 return -EINVAL;
1074}
1075
1076static void atmel_complete_rx_dma(void *arg)
1077{
1078 struct uart_port *port = arg;
1079 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1080
1081 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1082}
1083
1084static void atmel_release_rx_dma(struct uart_port *port)
1085{
1086 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1087 struct dma_chan *chan = atmel_port->chan_rx;
1088
1089 if (chan) {
1090 dmaengine_terminate_all(chan);
1091 dma_release_channel(chan);
1092 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1093 DMA_FROM_DEVICE);
1094 }
1095
1096 atmel_port->desc_rx = NULL;
1097 atmel_port->chan_rx = NULL;
1098 atmel_port->cookie_rx = -EINVAL;
1099}
1100
1101static void atmel_rx_from_dma(struct uart_port *port)
1102{
1103 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1104 struct tty_port *tport = &port->state->port;
1105 struct circ_buf *ring = &atmel_port->rx_ring;
1106 struct dma_chan *chan = atmel_port->chan_rx;
1107 struct dma_tx_state state;
1108 enum dma_status dmastat;
1109 size_t count;
1110
1111
1112 /* Reset the UART timeout early so that we don't miss one */
1113 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1114 dmastat = dmaengine_tx_status(chan,
1115 atmel_port->cookie_rx,
1116 &state);
1117 /* Restart a new tasklet if DMA status is error */
1118 if (dmastat == DMA_ERROR) {
1119 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1120 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1121 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1122 return;
1123 }
1124
1125 /* CPU claims ownership of RX DMA buffer */
1126 dma_sync_sg_for_cpu(port->dev,
1127 &atmel_port->sg_rx,
1128 1,
1129 DMA_FROM_DEVICE);
1130
1131 /*
1132 * ring->head points to the end of data already written by the DMA.
1133 * ring->tail points to the beginning of data to be read by the
1134 * framework.
1135 * The current transfer size should not be larger than the dma buffer
1136 * length.
1137 */
1138 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1139 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1140 /*
1141 * At this point ring->head may point to the first byte right after the
1142 * last byte of the dma buffer:
1143 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1144 *
1145 * However ring->tail must always points inside the dma buffer:
1146 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1147 *
1148 * Since we use a ring buffer, we have to handle the case
1149 * where head is lower than tail. In such a case, we first read from
1150 * tail to the end of the buffer then reset tail.
1151 */
1152 if (ring->head < ring->tail) {
1153 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1154
1155 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1156 ring->tail = 0;
1157 port->icount.rx += count;
1158 }
1159
1160 /* Finally we read data from tail to head */
1161 if (ring->tail < ring->head) {
1162 count = ring->head - ring->tail;
1163
1164 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1165 /* Wrap ring->head if needed */
1166 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1167 ring->head = 0;
1168 ring->tail = ring->head;
1169 port->icount.rx += count;
1170 }
1171
1172 /* USART retreives ownership of RX DMA buffer */
1173 dma_sync_sg_for_device(port->dev,
1174 &atmel_port->sg_rx,
1175 1,
1176 DMA_FROM_DEVICE);
1177
1178 /*
1179 * Drop the lock here since it might end up calling
1180 * uart_start(), which takes the lock.
1181 */
1182 spin_unlock(&port->lock);
1183 tty_flip_buffer_push(tport);
1184 spin_lock(&port->lock);
1185
1186 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1187}
1188
1189static int atmel_prepare_rx_dma(struct uart_port *port)
1190{
1191 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1192 struct device *mfd_dev = port->dev->parent;
1193 struct dma_async_tx_descriptor *desc;
1194 dma_cap_mask_t mask;
1195 struct dma_slave_config config;
1196 struct circ_buf *ring;
1197 int ret, nent;
1198
1199 ring = &atmel_port->rx_ring;
1200
1201 dma_cap_zero(mask);
1202 dma_cap_set(DMA_CYCLIC, mask);
1203
1204 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1205 if (atmel_port->chan_rx == NULL)
1206 goto chan_err;
1207 dev_info(port->dev, "using %s for rx DMA transfers\n",
1208 dma_chan_name(atmel_port->chan_rx));
1209
1210 spin_lock_init(&atmel_port->lock_rx);
1211 sg_init_table(&atmel_port->sg_rx, 1);
1212 /* UART circular rx buffer is an aligned page. */
1213 BUG_ON(!PAGE_ALIGNED(ring->buf));
1214 sg_set_page(&atmel_port->sg_rx,
1215 virt_to_page(ring->buf),
1216 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1217 offset_in_page(ring->buf));
1218 nent = dma_map_sg(port->dev,
1219 &atmel_port->sg_rx,
1220 1,
1221 DMA_FROM_DEVICE);
1222
1223 if (!nent) {
1224 dev_dbg(port->dev, "need to release resource of dma\n");
1225 goto chan_err;
1226 } else {
1227 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1228 sg_dma_len(&atmel_port->sg_rx),
1229 ring->buf,
1230 &sg_dma_address(&atmel_port->sg_rx));
1231 }
1232
1233 /* Configure the slave DMA */
1234 memset(&config, 0, sizeof(config));
1235 config.direction = DMA_DEV_TO_MEM;
1236 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1237 config.src_addr = port->mapbase + ATMEL_US_RHR;
1238 config.src_maxburst = 1;
1239
1240 ret = dmaengine_slave_config(atmel_port->chan_rx,
1241 &config);
1242 if (ret) {
1243 dev_err(port->dev, "DMA rx slave configuration failed\n");
1244 goto chan_err;
1245 }
1246 /*
1247 * Prepare a cyclic dma transfer, assign 2 descriptors,
1248 * each one is half ring buffer size
1249 */
1250 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1251 sg_dma_address(&atmel_port->sg_rx),
1252 sg_dma_len(&atmel_port->sg_rx),
1253 sg_dma_len(&atmel_port->sg_rx)/2,
1254 DMA_DEV_TO_MEM,
1255 DMA_PREP_INTERRUPT);
1256 if (!desc) {
1257 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1258 goto chan_err;
1259 }
1260 desc->callback = atmel_complete_rx_dma;
1261 desc->callback_param = port;
1262 atmel_port->desc_rx = desc;
1263 atmel_port->cookie_rx = dmaengine_submit(desc);
1264
1265 return 0;
1266
1267chan_err:
1268 dev_err(port->dev, "RX channel not available, switch to pio\n");
1269 atmel_port->use_dma_rx = 0;
1270 if (atmel_port->chan_rx)
1271 atmel_release_rx_dma(port);
1272 return -EINVAL;
1273}
1274
1275static void atmel_uart_timer_callback(struct timer_list *t)
1276{
1277 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1278 uart_timer);
1279 struct uart_port *port = &atmel_port->uart;
1280
1281 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1282 tasklet_schedule(&atmel_port->tasklet_rx);
1283 mod_timer(&atmel_port->uart_timer,
1284 jiffies + uart_poll_timeout(port));
1285 }
1286}
1287
1288/*
1289 * receive interrupt handler.
1290 */
1291static void
1292atmel_handle_receive(struct uart_port *port, unsigned int pending)
1293{
1294 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1295
1296 if (atmel_use_pdc_rx(port)) {
1297 /*
1298 * PDC receive. Just schedule the tasklet and let it
1299 * figure out the details.
1300 *
1301 * TODO: We're not handling error flags correctly at
1302 * the moment.
1303 */
1304 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1305 atmel_uart_writel(port, ATMEL_US_IDR,
1306 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1307 atmel_tasklet_schedule(atmel_port,
1308 &atmel_port->tasklet_rx);
1309 }
1310
1311 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1312 ATMEL_US_FRAME | ATMEL_US_PARE))
1313 atmel_pdc_rxerr(port, pending);
1314 }
1315
1316 if (atmel_use_dma_rx(port)) {
1317 if (pending & ATMEL_US_TIMEOUT) {
1318 atmel_uart_writel(port, ATMEL_US_IDR,
1319 ATMEL_US_TIMEOUT);
1320 atmel_tasklet_schedule(atmel_port,
1321 &atmel_port->tasklet_rx);
1322 }
1323 }
1324
1325 /* Interrupt receive */
1326 if (pending & ATMEL_US_RXRDY)
1327 atmel_rx_chars(port);
1328 else if (pending & ATMEL_US_RXBRK) {
1329 /*
1330 * End of break detected. If it came along with a
1331 * character, atmel_rx_chars will handle it.
1332 */
1333 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1334 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1335 atmel_port->break_active = 0;
1336 }
1337}
1338
1339/*
1340 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1341 */
1342static void
1343atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1344{
1345 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1346
1347 if (pending & atmel_port->tx_done_mask) {
1348 atmel_uart_writel(port, ATMEL_US_IDR,
1349 atmel_port->tx_done_mask);
1350
1351 /* Start RX if flag was set and FIFO is empty */
1352 if (atmel_port->hd_start_rx) {
1353 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1354 & ATMEL_US_TXEMPTY))
1355 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1356
1357 atmel_port->hd_start_rx = false;
1358 atmel_start_rx(port);
1359 }
1360
1361 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1362 }
1363}
1364
1365/*
1366 * status flags interrupt handler.
1367 */
1368static void
1369atmel_handle_status(struct uart_port *port, unsigned int pending,
1370 unsigned int status)
1371{
1372 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1373 unsigned int status_change;
1374
1375 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1376 | ATMEL_US_CTSIC)) {
1377 status_change = status ^ atmel_port->irq_status_prev;
1378 atmel_port->irq_status_prev = status;
1379
1380 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1381 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1382 /* TODO: All reads to CSR will clear these interrupts! */
1383 if (status_change & ATMEL_US_RI)
1384 port->icount.rng++;
1385 if (status_change & ATMEL_US_DSR)
1386 port->icount.dsr++;
1387 if (status_change & ATMEL_US_DCD)
1388 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1389 if (status_change & ATMEL_US_CTS)
1390 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1391
1392 wake_up_interruptible(&port->state->port.delta_msr_wait);
1393 }
1394 }
1395
1396 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1397 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1398}
1399
1400/*
1401 * Interrupt handler
1402 */
1403static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1404{
1405 struct uart_port *port = dev_id;
1406 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1407 unsigned int status, pending, mask, pass_counter = 0;
1408
1409 spin_lock(&atmel_port->lock_suspended);
1410
1411 do {
1412 status = atmel_uart_readl(port, ATMEL_US_CSR);
1413 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1414 pending = status & mask;
1415 if (!pending)
1416 break;
1417
1418 if (atmel_port->suspended) {
1419 atmel_port->pending |= pending;
1420 atmel_port->pending_status = status;
1421 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1422 pm_system_wakeup();
1423 break;
1424 }
1425
1426 atmel_handle_receive(port, pending);
1427 atmel_handle_status(port, pending, status);
1428 atmel_handle_transmit(port, pending);
1429 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1430
1431 spin_unlock(&atmel_port->lock_suspended);
1432
1433 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1434}
1435
1436static void atmel_release_tx_pdc(struct uart_port *port)
1437{
1438 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1439 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1440
1441 dma_unmap_single(port->dev,
1442 pdc->dma_addr,
1443 pdc->dma_size,
1444 DMA_TO_DEVICE);
1445}
1446
1447/*
1448 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1449 */
1450static void atmel_tx_pdc(struct uart_port *port)
1451{
1452 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1453 struct circ_buf *xmit = &port->state->xmit;
1454 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1455 int count;
1456
1457 /* nothing left to transmit? */
1458 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1459 return;
1460
1461 xmit->tail += pdc->ofs;
1462 xmit->tail &= UART_XMIT_SIZE - 1;
1463
1464 port->icount.tx += pdc->ofs;
1465 pdc->ofs = 0;
1466
1467 /* more to transmit - setup next transfer */
1468
1469 /* disable PDC transmit */
1470 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1471
1472 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1473 dma_sync_single_for_device(port->dev,
1474 pdc->dma_addr,
1475 pdc->dma_size,
1476 DMA_TO_DEVICE);
1477
1478 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1479 pdc->ofs = count;
1480
1481 atmel_uart_writel(port, ATMEL_PDC_TPR,
1482 pdc->dma_addr + xmit->tail);
1483 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1484 /* re-enable PDC transmit */
1485 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1486 /* Enable interrupts */
1487 atmel_uart_writel(port, ATMEL_US_IER,
1488 atmel_port->tx_done_mask);
1489 } else {
1490 if (atmel_uart_is_half_duplex(port)) {
1491 /* DMA done, stop TX, start RX for RS485 */
1492 atmel_start_rx(port);
1493 }
1494 }
1495
1496 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1497 uart_write_wakeup(port);
1498}
1499
1500static int atmel_prepare_tx_pdc(struct uart_port *port)
1501{
1502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1503 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1504 struct circ_buf *xmit = &port->state->xmit;
1505
1506 pdc->buf = xmit->buf;
1507 pdc->dma_addr = dma_map_single(port->dev,
1508 pdc->buf,
1509 UART_XMIT_SIZE,
1510 DMA_TO_DEVICE);
1511 pdc->dma_size = UART_XMIT_SIZE;
1512 pdc->ofs = 0;
1513
1514 return 0;
1515}
1516
1517static void atmel_rx_from_ring(struct uart_port *port)
1518{
1519 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1520 struct circ_buf *ring = &atmel_port->rx_ring;
1521 unsigned int flg;
1522 unsigned int status;
1523
1524 while (ring->head != ring->tail) {
1525 struct atmel_uart_char c;
1526
1527 /* Make sure c is loaded after head. */
1528 smp_rmb();
1529
1530 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1531
1532 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1533
1534 port->icount.rx++;
1535 status = c.status;
1536 flg = TTY_NORMAL;
1537
1538 /*
1539 * note that the error handling code is
1540 * out of the main execution path
1541 */
1542 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1543 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1544 if (status & ATMEL_US_RXBRK) {
1545 /* ignore side-effect */
1546 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1547
1548 port->icount.brk++;
1549 if (uart_handle_break(port))
1550 continue;
1551 }
1552 if (status & ATMEL_US_PARE)
1553 port->icount.parity++;
1554 if (status & ATMEL_US_FRAME)
1555 port->icount.frame++;
1556 if (status & ATMEL_US_OVRE)
1557 port->icount.overrun++;
1558
1559 status &= port->read_status_mask;
1560
1561 if (status & ATMEL_US_RXBRK)
1562 flg = TTY_BREAK;
1563 else if (status & ATMEL_US_PARE)
1564 flg = TTY_PARITY;
1565 else if (status & ATMEL_US_FRAME)
1566 flg = TTY_FRAME;
1567 }
1568
1569
1570 if (uart_handle_sysrq_char(port, c.ch))
1571 continue;
1572
1573 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1574 }
1575
1576 /*
1577 * Drop the lock here since it might end up calling
1578 * uart_start(), which takes the lock.
1579 */
1580 spin_unlock(&port->lock);
1581 tty_flip_buffer_push(&port->state->port);
1582 spin_lock(&port->lock);
1583}
1584
1585static void atmel_release_rx_pdc(struct uart_port *port)
1586{
1587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1588 int i;
1589
1590 for (i = 0; i < 2; i++) {
1591 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1592
1593 dma_unmap_single(port->dev,
1594 pdc->dma_addr,
1595 pdc->dma_size,
1596 DMA_FROM_DEVICE);
1597 kfree(pdc->buf);
1598 }
1599}
1600
1601static void atmel_rx_from_pdc(struct uart_port *port)
1602{
1603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1604 struct tty_port *tport = &port->state->port;
1605 struct atmel_dma_buffer *pdc;
1606 int rx_idx = atmel_port->pdc_rx_idx;
1607 unsigned int head;
1608 unsigned int tail;
1609 unsigned int count;
1610
1611 do {
1612 /* Reset the UART timeout early so that we don't miss one */
1613 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1614
1615 pdc = &atmel_port->pdc_rx[rx_idx];
1616 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1617 tail = pdc->ofs;
1618
1619 /* If the PDC has switched buffers, RPR won't contain
1620 * any address within the current buffer. Since head
1621 * is unsigned, we just need a one-way comparison to
1622 * find out.
1623 *
1624 * In this case, we just need to consume the entire
1625 * buffer and resubmit it for DMA. This will clear the
1626 * ENDRX bit as well, so that we can safely re-enable
1627 * all interrupts below.
1628 */
1629 head = min(head, pdc->dma_size);
1630
1631 if (likely(head != tail)) {
1632 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1633 pdc->dma_size, DMA_FROM_DEVICE);
1634
1635 /*
1636 * head will only wrap around when we recycle
1637 * the DMA buffer, and when that happens, we
1638 * explicitly set tail to 0. So head will
1639 * always be greater than tail.
1640 */
1641 count = head - tail;
1642
1643 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1644 count);
1645
1646 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1647 pdc->dma_size, DMA_FROM_DEVICE);
1648
1649 port->icount.rx += count;
1650 pdc->ofs = head;
1651 }
1652
1653 /*
1654 * If the current buffer is full, we need to check if
1655 * the next one contains any additional data.
1656 */
1657 if (head >= pdc->dma_size) {
1658 pdc->ofs = 0;
1659 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1660 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1661
1662 rx_idx = !rx_idx;
1663 atmel_port->pdc_rx_idx = rx_idx;
1664 }
1665 } while (head >= pdc->dma_size);
1666
1667 /*
1668 * Drop the lock here since it might end up calling
1669 * uart_start(), which takes the lock.
1670 */
1671 spin_unlock(&port->lock);
1672 tty_flip_buffer_push(tport);
1673 spin_lock(&port->lock);
1674
1675 atmel_uart_writel(port, ATMEL_US_IER,
1676 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1677}
1678
1679static int atmel_prepare_rx_pdc(struct uart_port *port)
1680{
1681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1682 int i;
1683
1684 for (i = 0; i < 2; i++) {
1685 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1686
1687 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1688 if (pdc->buf == NULL) {
1689 if (i != 0) {
1690 dma_unmap_single(port->dev,
1691 atmel_port->pdc_rx[0].dma_addr,
1692 PDC_BUFFER_SIZE,
1693 DMA_FROM_DEVICE);
1694 kfree(atmel_port->pdc_rx[0].buf);
1695 }
1696 atmel_port->use_pdc_rx = 0;
1697 return -ENOMEM;
1698 }
1699 pdc->dma_addr = dma_map_single(port->dev,
1700 pdc->buf,
1701 PDC_BUFFER_SIZE,
1702 DMA_FROM_DEVICE);
1703 pdc->dma_size = PDC_BUFFER_SIZE;
1704 pdc->ofs = 0;
1705 }
1706
1707 atmel_port->pdc_rx_idx = 0;
1708
1709 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1710 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1711
1712 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1713 atmel_port->pdc_rx[1].dma_addr);
1714 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1715
1716 return 0;
1717}
1718
1719/*
1720 * tasklet handling tty stuff outside the interrupt handler.
1721 */
1722static void atmel_tasklet_rx_func(unsigned long data)
1723{
1724 struct uart_port *port = (struct uart_port *)data;
1725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1726
1727 /* The interrupt handler does not take the lock */
1728 spin_lock(&port->lock);
1729 atmel_port->schedule_rx(port);
1730 spin_unlock(&port->lock);
1731}
1732
1733static void atmel_tasklet_tx_func(unsigned long data)
1734{
1735 struct uart_port *port = (struct uart_port *)data;
1736 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1737
1738 /* The interrupt handler does not take the lock */
1739 spin_lock(&port->lock);
1740 atmel_port->schedule_tx(port);
1741 spin_unlock(&port->lock);
1742}
1743
1744static void atmel_init_property(struct atmel_uart_port *atmel_port,
1745 struct platform_device *pdev)
1746{
1747 struct device_node *np = pdev->dev.of_node;
1748
1749 /* DMA/PDC usage specification */
1750 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1751 if (of_property_read_bool(np, "dmas")) {
1752 atmel_port->use_dma_rx = true;
1753 atmel_port->use_pdc_rx = false;
1754 } else {
1755 atmel_port->use_dma_rx = false;
1756 atmel_port->use_pdc_rx = true;
1757 }
1758 } else {
1759 atmel_port->use_dma_rx = false;
1760 atmel_port->use_pdc_rx = false;
1761 }
1762
1763 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1764 if (of_property_read_bool(np, "dmas")) {
1765 atmel_port->use_dma_tx = true;
1766 atmel_port->use_pdc_tx = false;
1767 } else {
1768 atmel_port->use_dma_tx = false;
1769 atmel_port->use_pdc_tx = true;
1770 }
1771 } else {
1772 atmel_port->use_dma_tx = false;
1773 atmel_port->use_pdc_tx = false;
1774 }
1775}
1776
1777static void atmel_set_ops(struct uart_port *port)
1778{
1779 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1780
1781 if (atmel_use_dma_rx(port)) {
1782 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1783 atmel_port->schedule_rx = &atmel_rx_from_dma;
1784 atmel_port->release_rx = &atmel_release_rx_dma;
1785 } else if (atmel_use_pdc_rx(port)) {
1786 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1787 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1788 atmel_port->release_rx = &atmel_release_rx_pdc;
1789 } else {
1790 atmel_port->prepare_rx = NULL;
1791 atmel_port->schedule_rx = &atmel_rx_from_ring;
1792 atmel_port->release_rx = NULL;
1793 }
1794
1795 if (atmel_use_dma_tx(port)) {
1796 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1797 atmel_port->schedule_tx = &atmel_tx_dma;
1798 atmel_port->release_tx = &atmel_release_tx_dma;
1799 } else if (atmel_use_pdc_tx(port)) {
1800 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1801 atmel_port->schedule_tx = &atmel_tx_pdc;
1802 atmel_port->release_tx = &atmel_release_tx_pdc;
1803 } else {
1804 atmel_port->prepare_tx = NULL;
1805 atmel_port->schedule_tx = &atmel_tx_chars;
1806 atmel_port->release_tx = NULL;
1807 }
1808}
1809
1810/*
1811 * Get ip name usart or uart
1812 */
1813static void atmel_get_ip_name(struct uart_port *port)
1814{
1815 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1816 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1817 u32 version;
1818 u32 usart, dbgu_uart, new_uart;
1819 /* ASCII decoding for IP version */
1820 usart = 0x55534152; /* USAR(T) */
1821 dbgu_uart = 0x44424755; /* DBGU */
1822 new_uart = 0x55415254; /* UART */
1823
1824 /*
1825 * Only USART devices from at91sam9260 SOC implement fractional
1826 * baudrate. It is available for all asynchronous modes, with the
1827 * following restriction: the sampling clock's duty cycle is not
1828 * constant.
1829 */
1830 atmel_port->has_frac_baudrate = false;
1831 atmel_port->has_hw_timer = false;
1832
1833 if (name == new_uart) {
1834 dev_dbg(port->dev, "Uart with hw timer");
1835 atmel_port->has_hw_timer = true;
1836 atmel_port->rtor = ATMEL_UA_RTOR;
1837 } else if (name == usart) {
1838 dev_dbg(port->dev, "Usart\n");
1839 atmel_port->has_frac_baudrate = true;
1840 atmel_port->has_hw_timer = true;
1841 atmel_port->rtor = ATMEL_US_RTOR;
1842 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1843 switch (version) {
1844 case 0x814: /* sama5d2 */
1845 /* fall through */
1846 case 0x701: /* sama5d4 */
1847 atmel_port->fidi_min = 3;
1848 atmel_port->fidi_max = 65535;
1849 break;
1850 case 0x502: /* sam9x5, sama5d3 */
1851 atmel_port->fidi_min = 3;
1852 atmel_port->fidi_max = 2047;
1853 break;
1854 default:
1855 atmel_port->fidi_min = 1;
1856 atmel_port->fidi_max = 2047;
1857 }
1858 } else if (name == dbgu_uart) {
1859 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1860 } else {
1861 /* fallback for older SoCs: use version field */
1862 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1863 switch (version) {
1864 case 0x302:
1865 case 0x10213:
1866 case 0x10302:
1867 dev_dbg(port->dev, "This version is usart\n");
1868 atmel_port->has_frac_baudrate = true;
1869 atmel_port->has_hw_timer = true;
1870 atmel_port->rtor = ATMEL_US_RTOR;
1871 break;
1872 case 0x203:
1873 case 0x10202:
1874 dev_dbg(port->dev, "This version is uart\n");
1875 break;
1876 default:
1877 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1878 }
1879 }
1880}
1881
1882/*
1883 * Perform initialization and enable port for reception
1884 */
1885static int atmel_startup(struct uart_port *port)
1886{
1887 struct platform_device *pdev = to_platform_device(port->dev);
1888 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1889 int retval;
1890
1891 /*
1892 * Ensure that no interrupts are enabled otherwise when
1893 * request_irq() is called we could get stuck trying to
1894 * handle an unexpected interrupt
1895 */
1896 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1897 atmel_port->ms_irq_enabled = false;
1898
1899 /*
1900 * Allocate the IRQ
1901 */
1902 retval = request_irq(port->irq, atmel_interrupt,
1903 IRQF_SHARED | IRQF_COND_SUSPEND,
1904 dev_name(&pdev->dev), port);
1905 if (retval) {
1906 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1907 return retval;
1908 }
1909
1910 atomic_set(&atmel_port->tasklet_shutdown, 0);
1911 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1912 (unsigned long)port);
1913 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1914 (unsigned long)port);
1915
1916 /*
1917 * Initialize DMA (if necessary)
1918 */
1919 atmel_init_property(atmel_port, pdev);
1920 atmel_set_ops(port);
1921
1922 if (atmel_port->prepare_rx) {
1923 retval = atmel_port->prepare_rx(port);
1924 if (retval < 0)
1925 atmel_set_ops(port);
1926 }
1927
1928 if (atmel_port->prepare_tx) {
1929 retval = atmel_port->prepare_tx(port);
1930 if (retval < 0)
1931 atmel_set_ops(port);
1932 }
1933
1934 /*
1935 * Enable FIFO when available
1936 */
1937 if (atmel_port->fifo_size) {
1938 unsigned int txrdym = ATMEL_US_ONE_DATA;
1939 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1940 unsigned int fmr;
1941
1942 atmel_uart_writel(port, ATMEL_US_CR,
1943 ATMEL_US_FIFOEN |
1944 ATMEL_US_RXFCLR |
1945 ATMEL_US_TXFLCLR);
1946
1947 if (atmel_use_dma_tx(port))
1948 txrdym = ATMEL_US_FOUR_DATA;
1949
1950 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1951 if (atmel_port->rts_high &&
1952 atmel_port->rts_low)
1953 fmr |= ATMEL_US_FRTSC |
1954 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1955 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1956
1957 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1958 }
1959
1960 /* Save current CSR for comparison in atmel_tasklet_func() */
1961 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1962
1963 /*
1964 * Finally, enable the serial port
1965 */
1966 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1967 /* enable xmit & rcvr */
1968 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1969 atmel_port->tx_stopped = false;
1970
1971 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1972
1973 if (atmel_use_pdc_rx(port)) {
1974 /* set UART timeout */
1975 if (!atmel_port->has_hw_timer) {
1976 mod_timer(&atmel_port->uart_timer,
1977 jiffies + uart_poll_timeout(port));
1978 /* set USART timeout */
1979 } else {
1980 atmel_uart_writel(port, atmel_port->rtor,
1981 PDC_RX_TIMEOUT);
1982 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1983
1984 atmel_uart_writel(port, ATMEL_US_IER,
1985 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1986 }
1987 /* enable PDC controller */
1988 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1989 } else if (atmel_use_dma_rx(port)) {
1990 /* set UART timeout */
1991 if (!atmel_port->has_hw_timer) {
1992 mod_timer(&atmel_port->uart_timer,
1993 jiffies + uart_poll_timeout(port));
1994 /* set USART timeout */
1995 } else {
1996 atmel_uart_writel(port, atmel_port->rtor,
1997 PDC_RX_TIMEOUT);
1998 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1999
2000 atmel_uart_writel(port, ATMEL_US_IER,
2001 ATMEL_US_TIMEOUT);
2002 }
2003 } else {
2004 /* enable receive only */
2005 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2006 }
2007
2008 return 0;
2009}
2010
2011/*
2012 * Flush any TX data submitted for DMA. Called when the TX circular
2013 * buffer is reset.
2014 */
2015static void atmel_flush_buffer(struct uart_port *port)
2016{
2017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2018
2019 if (atmel_use_pdc_tx(port)) {
2020 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2021 atmel_port->pdc_tx.ofs = 0;
2022 }
2023 /*
2024 * in uart_flush_buffer(), the xmit circular buffer has just
2025 * been cleared, so we have to reset tx_len accordingly.
2026 */
2027 atmel_port->tx_len = 0;
2028}
2029
2030/*
2031 * Disable the port
2032 */
2033static void atmel_shutdown(struct uart_port *port)
2034{
2035 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2036
2037 /* Disable modem control lines interrupts */
2038 atmel_disable_ms(port);
2039
2040 /* Disable interrupts at device level */
2041 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2042
2043 /* Prevent spurious interrupts from scheduling the tasklet */
2044 atomic_inc(&atmel_port->tasklet_shutdown);
2045
2046 /*
2047 * Prevent any tasklets being scheduled during
2048 * cleanup
2049 */
2050 del_timer_sync(&atmel_port->uart_timer);
2051
2052 /* Make sure that no interrupt is on the fly */
2053 synchronize_irq(port->irq);
2054
2055 /*
2056 * Clear out any scheduled tasklets before
2057 * we destroy the buffers
2058 */
2059 tasklet_kill(&atmel_port->tasklet_rx);
2060 tasklet_kill(&atmel_port->tasklet_tx);
2061
2062 /*
2063 * Ensure everything is stopped and
2064 * disable port and break condition.
2065 */
2066 atmel_stop_rx(port);
2067 atmel_stop_tx(port);
2068
2069 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2070
2071 /*
2072 * Shut-down the DMA.
2073 */
2074 if (atmel_port->release_rx)
2075 atmel_port->release_rx(port);
2076 if (atmel_port->release_tx)
2077 atmel_port->release_tx(port);
2078
2079 /*
2080 * Reset ring buffer pointers
2081 */
2082 atmel_port->rx_ring.head = 0;
2083 atmel_port->rx_ring.tail = 0;
2084
2085 /*
2086 * Free the interrupts
2087 */
2088 free_irq(port->irq, port);
2089
2090 atmel_flush_buffer(port);
2091}
2092
2093/*
2094 * Power / Clock management.
2095 */
2096static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2097 unsigned int oldstate)
2098{
2099 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2100
2101 switch (state) {
2102 case 0:
2103 /*
2104 * Enable the peripheral clock for this serial port.
2105 * This is called on uart_open() or a resume event.
2106 */
2107 clk_prepare_enable(atmel_port->clk);
2108
2109 /* re-enable interrupts if we disabled some on suspend */
2110 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2111 break;
2112 case 3:
2113 /* Back up the interrupt mask and disable all interrupts */
2114 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2115 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2116
2117 /*
2118 * Disable the peripheral clock for this serial port.
2119 * This is called on uart_close() or a suspend event.
2120 */
2121 clk_disable_unprepare(atmel_port->clk);
2122 break;
2123 default:
2124 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2125 }
2126}
2127
2128/*
2129 * Change the port parameters
2130 */
2131static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2132 struct ktermios *old)
2133{
2134 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2135 unsigned long flags;
2136 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2137
2138 /* save the current mode register */
2139 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2140
2141 /* reset the mode, clock divisor, parity, stop bits and data size */
2142 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2143 ATMEL_US_PAR | ATMEL_US_USMODE);
2144
2145 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2146
2147 /* byte size */
2148 switch (termios->c_cflag & CSIZE) {
2149 case CS5:
2150 mode |= ATMEL_US_CHRL_5;
2151 break;
2152 case CS6:
2153 mode |= ATMEL_US_CHRL_6;
2154 break;
2155 case CS7:
2156 mode |= ATMEL_US_CHRL_7;
2157 break;
2158 default:
2159 mode |= ATMEL_US_CHRL_8;
2160 break;
2161 }
2162
2163 /* stop bits */
2164 if (termios->c_cflag & CSTOPB)
2165 mode |= ATMEL_US_NBSTOP_2;
2166
2167 /* parity */
2168 if (termios->c_cflag & PARENB) {
2169 /* Mark or Space parity */
2170 if (termios->c_cflag & CMSPAR) {
2171 if (termios->c_cflag & PARODD)
2172 mode |= ATMEL_US_PAR_MARK;
2173 else
2174 mode |= ATMEL_US_PAR_SPACE;
2175 } else if (termios->c_cflag & PARODD)
2176 mode |= ATMEL_US_PAR_ODD;
2177 else
2178 mode |= ATMEL_US_PAR_EVEN;
2179 } else
2180 mode |= ATMEL_US_PAR_NONE;
2181
2182 spin_lock_irqsave(&port->lock, flags);
2183
2184 port->read_status_mask = ATMEL_US_OVRE;
2185 if (termios->c_iflag & INPCK)
2186 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2187 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2188 port->read_status_mask |= ATMEL_US_RXBRK;
2189
2190 if (atmel_use_pdc_rx(port))
2191 /* need to enable error interrupts */
2192 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2193
2194 /*
2195 * Characters to ignore
2196 */
2197 port->ignore_status_mask = 0;
2198 if (termios->c_iflag & IGNPAR)
2199 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2200 if (termios->c_iflag & IGNBRK) {
2201 port->ignore_status_mask |= ATMEL_US_RXBRK;
2202 /*
2203 * If we're ignoring parity and break indicators,
2204 * ignore overruns too (for real raw support).
2205 */
2206 if (termios->c_iflag & IGNPAR)
2207 port->ignore_status_mask |= ATMEL_US_OVRE;
2208 }
2209 /* TODO: Ignore all characters if CREAD is set.*/
2210
2211 /* update the per-port timeout */
2212 uart_update_timeout(port, termios->c_cflag, baud);
2213
2214 /*
2215 * save/disable interrupts. The tty layer will ensure that the
2216 * transmitter is empty if requested by the caller, so there's
2217 * no need to wait for it here.
2218 */
2219 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2220 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2221
2222 /* disable receiver and transmitter */
2223 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2224 atmel_port->tx_stopped = true;
2225
2226 /* mode */
2227 if (port->rs485.flags & SER_RS485_ENABLED) {
2228 atmel_uart_writel(port, ATMEL_US_TTGR,
2229 port->rs485.delay_rts_after_send);
2230 mode |= ATMEL_US_USMODE_RS485;
2231 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2232 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2233 /* select mck clock, and output */
2234 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2235 /* set max iterations */
2236 mode |= ATMEL_US_MAX_ITER(3);
2237 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2238 == SER_ISO7816_T(0))
2239 mode |= ATMEL_US_USMODE_ISO7816_T0;
2240 else
2241 mode |= ATMEL_US_USMODE_ISO7816_T1;
2242 } else if (termios->c_cflag & CRTSCTS) {
2243 /* RS232 with hardware handshake (RTS/CTS) */
2244 if (atmel_use_fifo(port) &&
2245 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2246 /*
2247 * with ATMEL_US_USMODE_HWHS set, the controller will
2248 * be able to drive the RTS pin high/low when the RX
2249 * FIFO is above RXFTHRES/below RXFTHRES2.
2250 * It will also disable the transmitter when the CTS
2251 * pin is high.
2252 * This mode is not activated if CTS pin is a GPIO
2253 * because in this case, the transmitter is always
2254 * disabled (there must be an internal pull-up
2255 * responsible for this behaviour).
2256 * If the RTS pin is a GPIO, the controller won't be
2257 * able to drive it according to the FIFO thresholds,
2258 * but it will be handled by the driver.
2259 */
2260 mode |= ATMEL_US_USMODE_HWHS;
2261 } else {
2262 /*
2263 * For platforms without FIFO, the flow control is
2264 * handled by the driver.
2265 */
2266 mode |= ATMEL_US_USMODE_NORMAL;
2267 }
2268 } else {
2269 /* RS232 without hadware handshake */
2270 mode |= ATMEL_US_USMODE_NORMAL;
2271 }
2272
2273 /* set the mode, clock divisor, parity, stop bits and data size */
2274 atmel_uart_writel(port, ATMEL_US_MR, mode);
2275
2276 /*
2277 * when switching the mode, set the RTS line state according to the
2278 * new mode, otherwise keep the former state
2279 */
2280 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2281 unsigned int rts_state;
2282
2283 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2284 /* let the hardware control the RTS line */
2285 rts_state = ATMEL_US_RTSDIS;
2286 } else {
2287 /* force RTS line to low level */
2288 rts_state = ATMEL_US_RTSEN;
2289 }
2290
2291 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2292 }
2293
2294 /*
2295 * Set the baud rate:
2296 * Fractional baudrate allows to setup output frequency more
2297 * accurately. This feature is enabled only when using normal mode.
2298 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2299 * Currently, OVER is always set to 0 so we get
2300 * baudrate = selected clock / (16 * (CD + FP / 8))
2301 * then
2302 * 8 CD + FP = selected clock / (2 * baudrate)
2303 */
2304 if (atmel_port->has_frac_baudrate) {
2305 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2306 cd = div >> 3;
2307 fp = div & ATMEL_US_FP_MASK;
2308 } else {
2309 cd = uart_get_divisor(port, baud);
2310 }
2311
2312 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2313 cd /= 8;
2314 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2315 }
2316 quot = cd | fp << ATMEL_US_FP_OFFSET;
2317
2318 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2319 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2320 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2321 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2322 atmel_port->tx_stopped = false;
2323
2324 /* restore interrupts */
2325 atmel_uart_writel(port, ATMEL_US_IER, imr);
2326
2327 /* CTS flow-control and modem-status interrupts */
2328 if (UART_ENABLE_MS(port, termios->c_cflag))
2329 atmel_enable_ms(port);
2330 else
2331 atmel_disable_ms(port);
2332
2333 spin_unlock_irqrestore(&port->lock, flags);
2334}
2335
2336static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2337{
2338 if (termios->c_line == N_PPS) {
2339 port->flags |= UPF_HARDPPS_CD;
2340 spin_lock_irq(&port->lock);
2341 atmel_enable_ms(port);
2342 spin_unlock_irq(&port->lock);
2343 } else {
2344 port->flags &= ~UPF_HARDPPS_CD;
2345 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2346 spin_lock_irq(&port->lock);
2347 atmel_disable_ms(port);
2348 spin_unlock_irq(&port->lock);
2349 }
2350 }
2351}
2352
2353/*
2354 * Return string describing the specified port
2355 */
2356static const char *atmel_type(struct uart_port *port)
2357{
2358 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2359}
2360
2361/*
2362 * Release the memory region(s) being used by 'port'.
2363 */
2364static void atmel_release_port(struct uart_port *port)
2365{
2366 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2367 int size = resource_size(mpdev->resource);
2368
2369 release_mem_region(port->mapbase, size);
2370
2371 if (port->flags & UPF_IOREMAP) {
2372 iounmap(port->membase);
2373 port->membase = NULL;
2374 }
2375}
2376
2377/*
2378 * Request the memory region(s) being used by 'port'.
2379 */
2380static int atmel_request_port(struct uart_port *port)
2381{
2382 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2383 int size = resource_size(mpdev->resource);
2384
2385 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2386 return -EBUSY;
2387
2388 if (port->flags & UPF_IOREMAP) {
2389 port->membase = ioremap(port->mapbase, size);
2390 if (port->membase == NULL) {
2391 release_mem_region(port->mapbase, size);
2392 return -ENOMEM;
2393 }
2394 }
2395
2396 return 0;
2397}
2398
2399/*
2400 * Configure/autoconfigure the port.
2401 */
2402static void atmel_config_port(struct uart_port *port, int flags)
2403{
2404 if (flags & UART_CONFIG_TYPE) {
2405 port->type = PORT_ATMEL;
2406 atmel_request_port(port);
2407 }
2408}
2409
2410/*
2411 * Verify the new serial_struct (for TIOCSSERIAL).
2412 */
2413static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2414{
2415 int ret = 0;
2416 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2417 ret = -EINVAL;
2418 if (port->irq != ser->irq)
2419 ret = -EINVAL;
2420 if (ser->io_type != SERIAL_IO_MEM)
2421 ret = -EINVAL;
2422 if (port->uartclk / 16 != ser->baud_base)
2423 ret = -EINVAL;
2424 if (port->mapbase != (unsigned long)ser->iomem_base)
2425 ret = -EINVAL;
2426 if (port->iobase != ser->port)
2427 ret = -EINVAL;
2428 if (ser->hub6 != 0)
2429 ret = -EINVAL;
2430 return ret;
2431}
2432
2433#ifdef CONFIG_CONSOLE_POLL
2434static int atmel_poll_get_char(struct uart_port *port)
2435{
2436 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2437 cpu_relax();
2438
2439 return atmel_uart_read_char(port);
2440}
2441
2442static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2443{
2444 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2445 cpu_relax();
2446
2447 atmel_uart_write_char(port, ch);
2448}
2449#endif
2450
2451static const struct uart_ops atmel_pops = {
2452 .tx_empty = atmel_tx_empty,
2453 .set_mctrl = atmel_set_mctrl,
2454 .get_mctrl = atmel_get_mctrl,
2455 .stop_tx = atmel_stop_tx,
2456 .start_tx = atmel_start_tx,
2457 .stop_rx = atmel_stop_rx,
2458 .enable_ms = atmel_enable_ms,
2459 .break_ctl = atmel_break_ctl,
2460 .startup = atmel_startup,
2461 .shutdown = atmel_shutdown,
2462 .flush_buffer = atmel_flush_buffer,
2463 .set_termios = atmel_set_termios,
2464 .set_ldisc = atmel_set_ldisc,
2465 .type = atmel_type,
2466 .release_port = atmel_release_port,
2467 .request_port = atmel_request_port,
2468 .config_port = atmel_config_port,
2469 .verify_port = atmel_verify_port,
2470 .pm = atmel_serial_pm,
2471#ifdef CONFIG_CONSOLE_POLL
2472 .poll_get_char = atmel_poll_get_char,
2473 .poll_put_char = atmel_poll_put_char,
2474#endif
2475};
2476
2477/*
2478 * Configure the port from the platform device resource info.
2479 */
2480static int atmel_init_port(struct atmel_uart_port *atmel_port,
2481 struct platform_device *pdev)
2482{
2483 int ret;
2484 struct uart_port *port = &atmel_port->uart;
2485 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2486
2487 atmel_init_property(atmel_port, pdev);
2488 atmel_set_ops(port);
2489
2490 uart_get_rs485_mode(&mpdev->dev, &port->rs485);
2491
2492 port->iotype = UPIO_MEM;
2493 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2494 port->ops = &atmel_pops;
2495 port->fifosize = 1;
2496 port->dev = &pdev->dev;
2497 port->mapbase = mpdev->resource[0].start;
2498 port->irq = mpdev->resource[1].start;
2499 port->rs485_config = atmel_config_rs485;
2500 port->iso7816_config = atmel_config_iso7816;
2501 port->membase = NULL;
2502
2503 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2504
2505 /* for console, the clock could already be configured */
2506 if (!atmel_port->clk) {
2507 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2508 if (IS_ERR(atmel_port->clk)) {
2509 ret = PTR_ERR(atmel_port->clk);
2510 atmel_port->clk = NULL;
2511 return ret;
2512 }
2513 ret = clk_prepare_enable(atmel_port->clk);
2514 if (ret) {
2515 clk_put(atmel_port->clk);
2516 atmel_port->clk = NULL;
2517 return ret;
2518 }
2519 port->uartclk = clk_get_rate(atmel_port->clk);
2520 clk_disable_unprepare(atmel_port->clk);
2521 /* only enable clock when USART is in use */
2522 }
2523
2524 /*
2525 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2526 * ENDTX|TXBUFE
2527 */
2528 if (port->rs485.flags & SER_RS485_ENABLED ||
2529 port->iso7816.flags & SER_ISO7816_ENABLED)
2530 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2531 else if (atmel_use_pdc_tx(port)) {
2532 port->fifosize = PDC_BUFFER_SIZE;
2533 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2534 } else {
2535 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2536 }
2537
2538 return 0;
2539}
2540
2541#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2542static void atmel_console_putchar(struct uart_port *port, int ch)
2543{
2544 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2545 cpu_relax();
2546 atmel_uart_write_char(port, ch);
2547}
2548
2549/*
2550 * Interrupts are disabled on entering
2551 */
2552static void atmel_console_write(struct console *co, const char *s, u_int count)
2553{
2554 struct uart_port *port = &atmel_ports[co->index].uart;
2555 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2556 unsigned int status, imr;
2557 unsigned int pdc_tx;
2558
2559 /*
2560 * First, save IMR and then disable interrupts
2561 */
2562 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2563 atmel_uart_writel(port, ATMEL_US_IDR,
2564 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2565
2566 /* Store PDC transmit status and disable it */
2567 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2568 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2569
2570 /* Make sure that tx path is actually able to send characters */
2571 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2572 atmel_port->tx_stopped = false;
2573
2574 uart_console_write(port, s, count, atmel_console_putchar);
2575
2576 /*
2577 * Finally, wait for transmitter to become empty
2578 * and restore IMR
2579 */
2580 do {
2581 status = atmel_uart_readl(port, ATMEL_US_CSR);
2582 } while (!(status & ATMEL_US_TXRDY));
2583
2584 /* Restore PDC transmit status */
2585 if (pdc_tx)
2586 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2587
2588 /* set interrupts back the way they were */
2589 atmel_uart_writel(port, ATMEL_US_IER, imr);
2590}
2591
2592/*
2593 * If the port was already initialised (eg, by a boot loader),
2594 * try to determine the current setup.
2595 */
2596static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2597 int *parity, int *bits)
2598{
2599 unsigned int mr, quot;
2600
2601 /*
2602 * If the baud rate generator isn't running, the port wasn't
2603 * initialized by the boot loader.
2604 */
2605 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2606 if (!quot)
2607 return;
2608
2609 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2610 if (mr == ATMEL_US_CHRL_8)
2611 *bits = 8;
2612 else
2613 *bits = 7;
2614
2615 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2616 if (mr == ATMEL_US_PAR_EVEN)
2617 *parity = 'e';
2618 else if (mr == ATMEL_US_PAR_ODD)
2619 *parity = 'o';
2620
2621 /*
2622 * The serial core only rounds down when matching this to a
2623 * supported baud rate. Make sure we don't end up slightly
2624 * lower than one of those, as it would make us fall through
2625 * to a much lower baud rate than we really want.
2626 */
2627 *baud = port->uartclk / (16 * (quot - 1));
2628}
2629
2630static int __init atmel_console_setup(struct console *co, char *options)
2631{
2632 int ret;
2633 struct uart_port *port = &atmel_ports[co->index].uart;
2634 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2635 int baud = 115200;
2636 int bits = 8;
2637 int parity = 'n';
2638 int flow = 'n';
2639
2640 if (port->membase == NULL) {
2641 /* Port not initialized yet - delay setup */
2642 return -ENODEV;
2643 }
2644
2645 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2646 if (ret)
2647 return ret;
2648
2649 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2650 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2651 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2652 atmel_port->tx_stopped = false;
2653
2654 if (options)
2655 uart_parse_options(options, &baud, &parity, &bits, &flow);
2656 else
2657 atmel_console_get_options(port, &baud, &parity, &bits);
2658
2659 return uart_set_options(port, co, baud, parity, bits, flow);
2660}
2661
2662static struct uart_driver atmel_uart;
2663
2664static struct console atmel_console = {
2665 .name = ATMEL_DEVICENAME,
2666 .write = atmel_console_write,
2667 .device = uart_console_device,
2668 .setup = atmel_console_setup,
2669 .flags = CON_PRINTBUFFER,
2670 .index = -1,
2671 .data = &atmel_uart,
2672};
2673
2674#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2675
2676static inline bool atmel_is_console_port(struct uart_port *port)
2677{
2678 return port->cons && port->cons->index == port->line;
2679}
2680
2681#else
2682#define ATMEL_CONSOLE_DEVICE NULL
2683
2684static inline bool atmel_is_console_port(struct uart_port *port)
2685{
2686 return false;
2687}
2688#endif
2689
2690static struct uart_driver atmel_uart = {
2691 .owner = THIS_MODULE,
2692 .driver_name = "atmel_serial",
2693 .dev_name = ATMEL_DEVICENAME,
2694 .major = SERIAL_ATMEL_MAJOR,
2695 .minor = MINOR_START,
2696 .nr = ATMEL_MAX_UART,
2697 .cons = ATMEL_CONSOLE_DEVICE,
2698};
2699
2700#ifdef CONFIG_PM
2701static bool atmel_serial_clk_will_stop(void)
2702{
2703#ifdef CONFIG_ARCH_AT91
2704 return at91_suspend_entering_slow_clock();
2705#else
2706 return false;
2707#endif
2708}
2709
2710static int atmel_serial_suspend(struct platform_device *pdev,
2711 pm_message_t state)
2712{
2713 struct uart_port *port = platform_get_drvdata(pdev);
2714 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2715
2716 if (atmel_is_console_port(port) && console_suspend_enabled) {
2717 /* Drain the TX shifter */
2718 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2719 ATMEL_US_TXEMPTY))
2720 cpu_relax();
2721 }
2722
2723 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2724 /* Cache register values as we won't get a full shutdown/startup
2725 * cycle
2726 */
2727 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2728 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2729 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2730 atmel_port->cache.rtor = atmel_uart_readl(port,
2731 atmel_port->rtor);
2732 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2733 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2734 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2735 }
2736
2737 /* we can not wake up if we're running on slow clock */
2738 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2739 if (atmel_serial_clk_will_stop()) {
2740 unsigned long flags;
2741
2742 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2743 atmel_port->suspended = true;
2744 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2745 device_set_wakeup_enable(&pdev->dev, 0);
2746 }
2747
2748 uart_suspend_port(&atmel_uart, port);
2749
2750 return 0;
2751}
2752
2753static int atmel_serial_resume(struct platform_device *pdev)
2754{
2755 struct uart_port *port = platform_get_drvdata(pdev);
2756 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2757 unsigned long flags;
2758
2759 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2760 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2761 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2762 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2763 atmel_uart_writel(port, atmel_port->rtor,
2764 atmel_port->cache.rtor);
2765 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2766
2767 if (atmel_port->fifo_size) {
2768 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2769 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2770 atmel_uart_writel(port, ATMEL_US_FMR,
2771 atmel_port->cache.fmr);
2772 atmel_uart_writel(port, ATMEL_US_FIER,
2773 atmel_port->cache.fimr);
2774 }
2775 atmel_start_rx(port);
2776 }
2777
2778 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2779 if (atmel_port->pending) {
2780 atmel_handle_receive(port, atmel_port->pending);
2781 atmel_handle_status(port, atmel_port->pending,
2782 atmel_port->pending_status);
2783 atmel_handle_transmit(port, atmel_port->pending);
2784 atmel_port->pending = 0;
2785 }
2786 atmel_port->suspended = false;
2787 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2788
2789 uart_resume_port(&atmel_uart, port);
2790 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2791
2792 return 0;
2793}
2794#else
2795#define atmel_serial_suspend NULL
2796#define atmel_serial_resume NULL
2797#endif
2798
2799static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2800 struct platform_device *pdev)
2801{
2802 atmel_port->fifo_size = 0;
2803 atmel_port->rts_low = 0;
2804 atmel_port->rts_high = 0;
2805
2806 if (of_property_read_u32(pdev->dev.of_node,
2807 "atmel,fifo-size",
2808 &atmel_port->fifo_size))
2809 return;
2810
2811 if (!atmel_port->fifo_size)
2812 return;
2813
2814 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2815 atmel_port->fifo_size = 0;
2816 dev_err(&pdev->dev, "Invalid FIFO size\n");
2817 return;
2818 }
2819
2820 /*
2821 * 0 <= rts_low <= rts_high <= fifo_size
2822 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2823 * to flush their internal TX FIFO, commonly up to 16 data, before
2824 * actually stopping to send new data. So we try to set the RTS High
2825 * Threshold to a reasonably high value respecting this 16 data
2826 * empirical rule when possible.
2827 */
2828 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2829 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2830 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2831 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2832
2833 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2834 atmel_port->fifo_size);
2835 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2836 atmel_port->rts_high);
2837 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2838 atmel_port->rts_low);
2839}
2840
2841static int atmel_serial_probe(struct platform_device *pdev)
2842{
2843 struct atmel_uart_port *atmel_port;
2844 struct device_node *np = pdev->dev.parent->of_node;
2845 void *data;
2846 int ret;
2847 bool rs485_enabled;
2848
2849 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2850
2851 /*
2852 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2853 * as compatible string. This driver is probed by at91-usart mfd driver
2854 * which is just a wrapper over the atmel_serial driver and
2855 * spi-at91-usart driver. All attributes needed by this driver are
2856 * found in of_node of parent.
2857 */
2858 pdev->dev.of_node = np;
2859
2860 ret = of_alias_get_id(np, "serial");
2861 if (ret < 0)
2862 /* port id not found in platform data nor device-tree aliases:
2863 * auto-enumerate it */
2864 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2865
2866 if (ret >= ATMEL_MAX_UART) {
2867 ret = -ENODEV;
2868 goto err;
2869 }
2870
2871 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2872 /* port already in use */
2873 ret = -EBUSY;
2874 goto err;
2875 }
2876
2877 atmel_port = &atmel_ports[ret];
2878 atmel_port->backup_imr = 0;
2879 atmel_port->uart.line = ret;
2880 atmel_serial_probe_fifos(atmel_port, pdev);
2881
2882 atomic_set(&atmel_port->tasklet_shutdown, 0);
2883 spin_lock_init(&atmel_port->lock_suspended);
2884
2885 ret = atmel_init_port(atmel_port, pdev);
2886 if (ret)
2887 goto err_clear_bit;
2888
2889 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2890 if (IS_ERR(atmel_port->gpios)) {
2891 ret = PTR_ERR(atmel_port->gpios);
2892 goto err_clear_bit;
2893 }
2894
2895 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2896 ret = -ENOMEM;
2897 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2898 sizeof(struct atmel_uart_char),
2899 GFP_KERNEL);
2900 if (!data)
2901 goto err_alloc_ring;
2902 atmel_port->rx_ring.buf = data;
2903 }
2904
2905 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2906
2907 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2908 if (ret)
2909 goto err_add_port;
2910
2911#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2912 if (atmel_is_console_port(&atmel_port->uart)
2913 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2914 /*
2915 * The serial core enabled the clock for us, so undo
2916 * the clk_prepare_enable() in atmel_console_setup()
2917 */
2918 clk_disable_unprepare(atmel_port->clk);
2919 }
2920#endif
2921
2922 device_init_wakeup(&pdev->dev, 1);
2923 platform_set_drvdata(pdev, atmel_port);
2924
2925 /*
2926 * The peripheral clock has been disabled by atmel_init_port():
2927 * enable it before accessing I/O registers
2928 */
2929 clk_prepare_enable(atmel_port->clk);
2930
2931 if (rs485_enabled) {
2932 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2933 ATMEL_US_USMODE_NORMAL);
2934 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2935 ATMEL_US_RTSEN);
2936 }
2937
2938 /*
2939 * Get port name of usart or uart
2940 */
2941 atmel_get_ip_name(&atmel_port->uart);
2942
2943 /*
2944 * The peripheral clock can now safely be disabled till the port
2945 * is used
2946 */
2947 clk_disable_unprepare(atmel_port->clk);
2948
2949 return 0;
2950
2951err_add_port:
2952 kfree(atmel_port->rx_ring.buf);
2953 atmel_port->rx_ring.buf = NULL;
2954err_alloc_ring:
2955 if (!atmel_is_console_port(&atmel_port->uart)) {
2956 clk_put(atmel_port->clk);
2957 atmel_port->clk = NULL;
2958 }
2959err_clear_bit:
2960 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2961err:
2962 return ret;
2963}
2964
2965/*
2966 * Even if the driver is not modular, it makes sense to be able to
2967 * unbind a device: there can be many bound devices, and there are
2968 * situations where dynamic binding and unbinding can be useful.
2969 *
2970 * For example, a connected device can require a specific firmware update
2971 * protocol that needs bitbanging on IO lines, but use the regular serial
2972 * port in the normal case.
2973 */
2974static int atmel_serial_remove(struct platform_device *pdev)
2975{
2976 struct uart_port *port = platform_get_drvdata(pdev);
2977 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2978 int ret = 0;
2979
2980 tasklet_kill(&atmel_port->tasklet_rx);
2981 tasklet_kill(&atmel_port->tasklet_tx);
2982
2983 device_init_wakeup(&pdev->dev, 0);
2984
2985 ret = uart_remove_one_port(&atmel_uart, port);
2986
2987 kfree(atmel_port->rx_ring.buf);
2988
2989 /* "port" is allocated statically, so we shouldn't free it */
2990
2991 clear_bit(port->line, atmel_ports_in_use);
2992
2993 clk_put(atmel_port->clk);
2994 atmel_port->clk = NULL;
2995 pdev->dev.of_node = NULL;
2996
2997 return ret;
2998}
2999
3000static struct platform_driver atmel_serial_driver = {
3001 .probe = atmel_serial_probe,
3002 .remove = atmel_serial_remove,
3003 .suspend = atmel_serial_suspend,
3004 .resume = atmel_serial_resume,
3005 .driver = {
3006 .name = "atmel_usart_serial",
3007 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3008 },
3009};
3010
3011static int __init atmel_serial_init(void)
3012{
3013 int ret;
3014
3015 ret = uart_register_driver(&atmel_uart);
3016 if (ret)
3017 return ret;
3018
3019 ret = platform_driver_register(&atmel_serial_driver);
3020 if (ret)
3021 uart_unregister_driver(&atmel_uart);
3022
3023 return ret;
3024}
3025device_initcall(atmel_serial_init);