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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
4 * Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
5 *
6 * This driver is a port from stlc45xx:
7 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
8 */
9
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/interrupt.h>
13#include <linux/firmware.h>
14#include <linux/delay.h>
15#include <linux/irq.h>
16#include <linux/spi/spi.h>
17#include <linux/etherdevice.h>
18#include <linux/gpio.h>
19#include <linux/slab.h>
20
21#include "p54spi.h"
22#include "p54.h"
23
24#include "lmac.h"
25
26#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
27#include "p54spi_eeprom.h"
28#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
29
30MODULE_FIRMWARE("3826.arm");
31MODULE_FIRMWARE("3826.eeprom");
32
33/* gpios should be handled in board files and provided via platform data,
34 * but because it's currently impossible for p54spi to have a header file
35 * in include/linux, let's use module paramaters for now
36 */
37
38static int p54spi_gpio_power = 97;
39module_param(p54spi_gpio_power, int, 0444);
40MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
41
42static int p54spi_gpio_irq = 87;
43module_param(p54spi_gpio_irq, int, 0444);
44MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
45
46static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
47 void *buf, size_t len)
48{
49 struct spi_transfer t[2];
50 struct spi_message m;
51 __le16 addr;
52
53 /* We first push the address */
54 addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
55
56 spi_message_init(&m);
57 memset(t, 0, sizeof(t));
58
59 t[0].tx_buf = &addr;
60 t[0].len = sizeof(addr);
61 spi_message_add_tail(&t[0], &m);
62
63 t[1].rx_buf = buf;
64 t[1].len = len;
65 spi_message_add_tail(&t[1], &m);
66
67 spi_sync(priv->spi, &m);
68}
69
70
71static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
72 const void *buf, size_t len)
73{
74 struct spi_transfer t[3];
75 struct spi_message m;
76 __le16 addr;
77
78 /* We first push the address */
79 addr = cpu_to_le16(address << 8);
80
81 spi_message_init(&m);
82 memset(t, 0, sizeof(t));
83
84 t[0].tx_buf = &addr;
85 t[0].len = sizeof(addr);
86 spi_message_add_tail(&t[0], &m);
87
88 t[1].tx_buf = buf;
89 t[1].len = len & ~1;
90 spi_message_add_tail(&t[1], &m);
91
92 if (len % 2) {
93 __le16 last_word;
94 last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
95
96 t[2].tx_buf = &last_word;
97 t[2].len = sizeof(last_word);
98 spi_message_add_tail(&t[2], &m);
99 }
100
101 spi_sync(priv->spi, &m);
102}
103
104static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
105{
106 __le32 val;
107
108 p54spi_spi_read(priv, addr, &val, sizeof(val));
109
110 return le32_to_cpu(val);
111}
112
113static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
114{
115 p54spi_spi_write(priv, addr, &val, sizeof(val));
116}
117
118static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
119{
120 p54spi_spi_write(priv, addr, &val, sizeof(val));
121}
122
123static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
124{
125 int i;
126
127 for (i = 0; i < 2000; i++) {
128 u32 buffer = p54spi_read32(priv, reg);
129 if ((buffer & bits) == bits)
130 return 1;
131 }
132 return 0;
133}
134
135static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
136 const void *buf, size_t len)
137{
138 if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
139 dev_err(&priv->spi->dev, "spi_write_dma not allowed "
140 "to DMA write.\n");
141 return -EAGAIN;
142 }
143
144 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
145 cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
146
147 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
148 p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
149 p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
150 return 0;
151}
152
153static int p54spi_request_firmware(struct ieee80211_hw *dev)
154{
155 struct p54s_priv *priv = dev->priv;
156 int ret;
157
158 /* FIXME: should driver use it's own struct device? */
159 ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
160
161 if (ret < 0) {
162 dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
163 return ret;
164 }
165
166 ret = p54_parse_firmware(dev, priv->firmware);
167 if (ret) {
168 /* the firmware is released by the caller */
169 return ret;
170 }
171
172 return 0;
173}
174
175static int p54spi_request_eeprom(struct ieee80211_hw *dev)
176{
177 struct p54s_priv *priv = dev->priv;
178 const struct firmware *eeprom;
179 int ret;
180
181 /* allow users to customize their eeprom.
182 */
183
184 ret = request_firmware_direct(&eeprom, "3826.eeprom", &priv->spi->dev);
185 if (ret < 0) {
186#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
187 dev_info(&priv->spi->dev, "loading default eeprom...\n");
188 ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
189 sizeof(p54spi_eeprom));
190#else
191 dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
192#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
193 } else {
194 dev_info(&priv->spi->dev, "loading user eeprom...\n");
195 ret = p54_parse_eeprom(dev, (void *) eeprom->data,
196 (int)eeprom->size);
197 release_firmware(eeprom);
198 }
199 return ret;
200}
201
202static int p54spi_upload_firmware(struct ieee80211_hw *dev)
203{
204 struct p54s_priv *priv = dev->priv;
205 unsigned long fw_len, _fw_len;
206 unsigned int offset = 0;
207 int err = 0;
208 u8 *fw;
209
210 fw_len = priv->firmware->size;
211 fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
212 if (!fw)
213 return -ENOMEM;
214
215 /* stop the device */
216 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
217 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
218 SPI_CTRL_STAT_START_HALTED));
219
220 msleep(TARGET_BOOT_SLEEP);
221
222 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
223 SPI_CTRL_STAT_HOST_OVERRIDE |
224 SPI_CTRL_STAT_START_HALTED));
225
226 msleep(TARGET_BOOT_SLEEP);
227
228 while (fw_len > 0) {
229 _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
230
231 err = p54spi_spi_write_dma(priv, cpu_to_le32(
232 ISL38XX_DEV_FIRMWARE_ADDR + offset),
233 (fw + offset), _fw_len);
234 if (err < 0)
235 goto out;
236
237 fw_len -= _fw_len;
238 offset += _fw_len;
239 }
240
241 BUG_ON(fw_len != 0);
242
243 /* enable host interrupts */
244 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
245 cpu_to_le32(SPI_HOST_INTS_DEFAULT));
246
247 /* boot the device */
248 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
249 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
250 SPI_CTRL_STAT_RAM_BOOT));
251
252 msleep(TARGET_BOOT_SLEEP);
253
254 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
255 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
256 msleep(TARGET_BOOT_SLEEP);
257
258out:
259 kfree(fw);
260 return err;
261}
262
263static void p54spi_power_off(struct p54s_priv *priv)
264{
265 disable_irq(gpio_to_irq(p54spi_gpio_irq));
266 gpio_set_value(p54spi_gpio_power, 0);
267}
268
269static void p54spi_power_on(struct p54s_priv *priv)
270{
271 gpio_set_value(p54spi_gpio_power, 1);
272 enable_irq(gpio_to_irq(p54spi_gpio_irq));
273
274 /* need to wait a while before device can be accessed, the length
275 * is just a guess
276 */
277 msleep(10);
278}
279
280static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
281{
282 p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
283}
284
285static int p54spi_wakeup(struct p54s_priv *priv)
286{
287 /* wake the chip */
288 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
289 cpu_to_le32(SPI_TARGET_INT_WAKEUP));
290
291 /* And wait for the READY interrupt */
292 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
293 SPI_HOST_INT_READY)) {
294 dev_err(&priv->spi->dev, "INT_READY timeout\n");
295 return -EBUSY;
296 }
297
298 p54spi_int_ack(priv, SPI_HOST_INT_READY);
299 return 0;
300}
301
302static inline void p54spi_sleep(struct p54s_priv *priv)
303{
304 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
305 cpu_to_le32(SPI_TARGET_INT_SLEEP));
306}
307
308static void p54spi_int_ready(struct p54s_priv *priv)
309{
310 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
311 SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
312
313 switch (priv->fw_state) {
314 case FW_STATE_BOOTING:
315 priv->fw_state = FW_STATE_READY;
316 complete(&priv->fw_comp);
317 break;
318 case FW_STATE_RESETTING:
319 priv->fw_state = FW_STATE_READY;
320 /* TODO: reinitialize state */
321 break;
322 default:
323 break;
324 }
325}
326
327static int p54spi_rx(struct p54s_priv *priv)
328{
329 struct sk_buff *skb;
330 u16 len;
331 u16 rx_head[2];
332#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
333
334 if (p54spi_wakeup(priv) < 0)
335 return -EBUSY;
336
337 /* Read data size and first data word in one SPI transaction
338 * This is workaround for firmware/DMA bug,
339 * when first data word gets lost under high load.
340 */
341 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
342 len = rx_head[0];
343
344 if (len == 0) {
345 p54spi_sleep(priv);
346 dev_err(&priv->spi->dev, "rx request of zero bytes\n");
347 return 0;
348 }
349
350 /* Firmware may insert up to 4 padding bytes after the lmac header,
351 * but it does not amend the size of SPI data transfer.
352 * Such packets has correct data size in header, thus referencing
353 * past the end of allocated skb. Reserve extra 4 bytes for this case
354 */
355 skb = dev_alloc_skb(len + 4);
356 if (!skb) {
357 p54spi_sleep(priv);
358 dev_err(&priv->spi->dev, "could not alloc skb");
359 return -ENOMEM;
360 }
361
362 if (len <= READAHEAD_SZ) {
363 skb_put_data(skb, rx_head + 1, len);
364 } else {
365 skb_put_data(skb, rx_head + 1, READAHEAD_SZ);
366 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
367 skb_put(skb, len - READAHEAD_SZ),
368 len - READAHEAD_SZ);
369 }
370 p54spi_sleep(priv);
371 /* Put additional bytes to compensate for the possible
372 * alignment-caused truncation
373 */
374 skb_put(skb, 4);
375
376 if (p54_rx(priv->hw, skb) == 0)
377 dev_kfree_skb(skb);
378
379 return 0;
380}
381
382
383static irqreturn_t p54spi_interrupt(int irq, void *config)
384{
385 struct spi_device *spi = config;
386 struct p54s_priv *priv = spi_get_drvdata(spi);
387
388 ieee80211_queue_work(priv->hw, &priv->work);
389
390 return IRQ_HANDLED;
391}
392
393static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
394{
395 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
396 int ret = 0;
397
398 if (p54spi_wakeup(priv) < 0)
399 return -EBUSY;
400
401 ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
402 if (ret < 0)
403 goto out;
404
405 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
406 SPI_HOST_INT_WR_READY)) {
407 dev_err(&priv->spi->dev, "WR_READY timeout\n");
408 ret = -EAGAIN;
409 goto out;
410 }
411
412 p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
413
414 if (FREE_AFTER_TX(skb))
415 p54_free_skb(priv->hw, skb);
416out:
417 p54spi_sleep(priv);
418 return ret;
419}
420
421static int p54spi_wq_tx(struct p54s_priv *priv)
422{
423 struct p54s_tx_info *entry;
424 struct sk_buff *skb;
425 struct ieee80211_tx_info *info;
426 struct p54_tx_info *minfo;
427 struct p54s_tx_info *dinfo;
428 unsigned long flags;
429 int ret = 0;
430
431 spin_lock_irqsave(&priv->tx_lock, flags);
432
433 while (!list_empty(&priv->tx_pending)) {
434 entry = list_entry(priv->tx_pending.next,
435 struct p54s_tx_info, tx_list);
436
437 list_del_init(&entry->tx_list);
438
439 spin_unlock_irqrestore(&priv->tx_lock, flags);
440
441 dinfo = container_of((void *) entry, struct p54s_tx_info,
442 tx_list);
443 minfo = container_of((void *) dinfo, struct p54_tx_info,
444 data);
445 info = container_of((void *) minfo, struct ieee80211_tx_info,
446 rate_driver_data);
447 skb = container_of((void *) info, struct sk_buff, cb);
448
449 ret = p54spi_tx_frame(priv, skb);
450
451 if (ret < 0) {
452 p54_free_skb(priv->hw, skb);
453 return ret;
454 }
455
456 spin_lock_irqsave(&priv->tx_lock, flags);
457 }
458 spin_unlock_irqrestore(&priv->tx_lock, flags);
459 return ret;
460}
461
462static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
463{
464 struct p54s_priv *priv = dev->priv;
465 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
466 struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
467 struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
468 unsigned long flags;
469
470 BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
471
472 spin_lock_irqsave(&priv->tx_lock, flags);
473 list_add_tail(&di->tx_list, &priv->tx_pending);
474 spin_unlock_irqrestore(&priv->tx_lock, flags);
475
476 ieee80211_queue_work(priv->hw, &priv->work);
477}
478
479static void p54spi_work(struct work_struct *work)
480{
481 struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
482 u32 ints;
483 int ret;
484
485 mutex_lock(&priv->mutex);
486
487 if (priv->fw_state == FW_STATE_OFF)
488 goto out;
489
490 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
491
492 if (ints & SPI_HOST_INT_READY) {
493 p54spi_int_ready(priv);
494 p54spi_int_ack(priv, SPI_HOST_INT_READY);
495 }
496
497 if (priv->fw_state != FW_STATE_READY)
498 goto out;
499
500 if (ints & SPI_HOST_INT_UPDATE) {
501 p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
502 ret = p54spi_rx(priv);
503 if (ret < 0)
504 goto out;
505 }
506 if (ints & SPI_HOST_INT_SW_UPDATE) {
507 p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
508 ret = p54spi_rx(priv);
509 if (ret < 0)
510 goto out;
511 }
512
513 ret = p54spi_wq_tx(priv);
514out:
515 mutex_unlock(&priv->mutex);
516}
517
518static int p54spi_op_start(struct ieee80211_hw *dev)
519{
520 struct p54s_priv *priv = dev->priv;
521 unsigned long timeout;
522 int ret = 0;
523
524 if (mutex_lock_interruptible(&priv->mutex)) {
525 ret = -EINTR;
526 goto out;
527 }
528
529 priv->fw_state = FW_STATE_BOOTING;
530
531 p54spi_power_on(priv);
532
533 ret = p54spi_upload_firmware(dev);
534 if (ret < 0) {
535 p54spi_power_off(priv);
536 goto out_unlock;
537 }
538
539 mutex_unlock(&priv->mutex);
540
541 timeout = msecs_to_jiffies(2000);
542 timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
543 timeout);
544 if (!timeout) {
545 dev_err(&priv->spi->dev, "firmware boot failed");
546 p54spi_power_off(priv);
547 ret = -1;
548 goto out;
549 }
550
551 if (mutex_lock_interruptible(&priv->mutex)) {
552 ret = -EINTR;
553 p54spi_power_off(priv);
554 goto out;
555 }
556
557 WARN_ON(priv->fw_state != FW_STATE_READY);
558
559out_unlock:
560 mutex_unlock(&priv->mutex);
561
562out:
563 return ret;
564}
565
566static void p54spi_op_stop(struct ieee80211_hw *dev)
567{
568 struct p54s_priv *priv = dev->priv;
569 unsigned long flags;
570
571 mutex_lock(&priv->mutex);
572 WARN_ON(priv->fw_state != FW_STATE_READY);
573
574 p54spi_power_off(priv);
575 spin_lock_irqsave(&priv->tx_lock, flags);
576 INIT_LIST_HEAD(&priv->tx_pending);
577 spin_unlock_irqrestore(&priv->tx_lock, flags);
578
579 priv->fw_state = FW_STATE_OFF;
580 mutex_unlock(&priv->mutex);
581
582 cancel_work_sync(&priv->work);
583}
584
585static int p54spi_probe(struct spi_device *spi)
586{
587 struct p54s_priv *priv = NULL;
588 struct ieee80211_hw *hw;
589 int ret = -EINVAL;
590
591 hw = p54_init_common(sizeof(*priv));
592 if (!hw) {
593 dev_err(&spi->dev, "could not alloc ieee80211_hw");
594 return -ENOMEM;
595 }
596
597 priv = hw->priv;
598 priv->hw = hw;
599 spi_set_drvdata(spi, priv);
600 priv->spi = spi;
601
602 spi->bits_per_word = 16;
603 spi->max_speed_hz = 24000000;
604
605 ret = spi_setup(spi);
606 if (ret < 0) {
607 dev_err(&priv->spi->dev, "spi_setup failed");
608 goto err_free;
609 }
610
611 ret = gpio_request(p54spi_gpio_power, "p54spi power");
612 if (ret < 0) {
613 dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
614 goto err_free;
615 }
616
617 ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
618 if (ret < 0) {
619 dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
620 goto err_free_gpio_power;
621 }
622
623 gpio_direction_output(p54spi_gpio_power, 0);
624 gpio_direction_input(p54spi_gpio_irq);
625
626 ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
627 p54spi_interrupt, 0, "p54spi",
628 priv->spi);
629 if (ret < 0) {
630 dev_err(&priv->spi->dev, "request_irq() failed");
631 goto err_free_gpio_irq;
632 }
633
634 irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);
635
636 disable_irq(gpio_to_irq(p54spi_gpio_irq));
637
638 INIT_WORK(&priv->work, p54spi_work);
639 init_completion(&priv->fw_comp);
640 INIT_LIST_HEAD(&priv->tx_pending);
641 mutex_init(&priv->mutex);
642 spin_lock_init(&priv->tx_lock);
643 SET_IEEE80211_DEV(hw, &spi->dev);
644 priv->common.open = p54spi_op_start;
645 priv->common.stop = p54spi_op_stop;
646 priv->common.tx = p54spi_op_tx;
647
648 ret = p54spi_request_firmware(hw);
649 if (ret < 0)
650 goto err_free_common;
651
652 ret = p54spi_request_eeprom(hw);
653 if (ret)
654 goto err_free_common;
655
656 ret = p54_register_common(hw, &priv->spi->dev);
657 if (ret)
658 goto err_free_common;
659
660 return 0;
661
662err_free_common:
663 release_firmware(priv->firmware);
664 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
665err_free_gpio_irq:
666 gpio_free(p54spi_gpio_irq);
667err_free_gpio_power:
668 gpio_free(p54spi_gpio_power);
669err_free:
670 p54_free_common(priv->hw);
671 return ret;
672}
673
674static void p54spi_remove(struct spi_device *spi)
675{
676 struct p54s_priv *priv = spi_get_drvdata(spi);
677
678 p54_unregister_common(priv->hw);
679
680 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
681
682 gpio_free(p54spi_gpio_power);
683 gpio_free(p54spi_gpio_irq);
684 release_firmware(priv->firmware);
685
686 mutex_destroy(&priv->mutex);
687
688 p54_free_common(priv->hw);
689}
690
691
692static struct spi_driver p54spi_driver = {
693 .driver = {
694 .name = "p54spi",
695 },
696
697 .probe = p54spi_probe,
698 .remove = p54spi_remove,
699};
700
701module_spi_driver(p54spi_driver);
702
703MODULE_DESCRIPTION("Prism54 SPI wireless driver");
704MODULE_LICENSE("GPL");
705MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
706MODULE_ALIAS("spi:cx3110x");
707MODULE_ALIAS("spi:p54spi");
708MODULE_ALIAS("spi:stlc45xx");
1/*
2 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
3 * Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
4 *
5 * This driver is a port from stlc45xx:
6 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 */
22
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/interrupt.h>
26#include <linux/firmware.h>
27#include <linux/delay.h>
28#include <linux/irq.h>
29#include <linux/spi/spi.h>
30#include <linux/etherdevice.h>
31#include <linux/gpio.h>
32#include <linux/slab.h>
33
34#include "p54spi.h"
35#include "p54.h"
36
37#include "lmac.h"
38
39#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
40#include "p54spi_eeprom.h"
41#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
42
43MODULE_FIRMWARE("3826.arm");
44
45/* gpios should be handled in board files and provided via platform data,
46 * but because it's currently impossible for p54spi to have a header file
47 * in include/linux, let's use module paramaters for now
48 */
49
50static int p54spi_gpio_power = 97;
51module_param(p54spi_gpio_power, int, 0444);
52MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
53
54static int p54spi_gpio_irq = 87;
55module_param(p54spi_gpio_irq, int, 0444);
56MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
57
58static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
59 void *buf, size_t len)
60{
61 struct spi_transfer t[2];
62 struct spi_message m;
63 __le16 addr;
64
65 /* We first push the address */
66 addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
67
68 spi_message_init(&m);
69 memset(t, 0, sizeof(t));
70
71 t[0].tx_buf = &addr;
72 t[0].len = sizeof(addr);
73 spi_message_add_tail(&t[0], &m);
74
75 t[1].rx_buf = buf;
76 t[1].len = len;
77 spi_message_add_tail(&t[1], &m);
78
79 spi_sync(priv->spi, &m);
80}
81
82
83static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
84 const void *buf, size_t len)
85{
86 struct spi_transfer t[3];
87 struct spi_message m;
88 __le16 addr;
89
90 /* We first push the address */
91 addr = cpu_to_le16(address << 8);
92
93 spi_message_init(&m);
94 memset(t, 0, sizeof(t));
95
96 t[0].tx_buf = &addr;
97 t[0].len = sizeof(addr);
98 spi_message_add_tail(&t[0], &m);
99
100 t[1].tx_buf = buf;
101 t[1].len = len & ~1;
102 spi_message_add_tail(&t[1], &m);
103
104 if (len % 2) {
105 __le16 last_word;
106 last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
107
108 t[2].tx_buf = &last_word;
109 t[2].len = sizeof(last_word);
110 spi_message_add_tail(&t[2], &m);
111 }
112
113 spi_sync(priv->spi, &m);
114}
115
116static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
117{
118 __le32 val;
119
120 p54spi_spi_read(priv, addr, &val, sizeof(val));
121
122 return le32_to_cpu(val);
123}
124
125static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
126{
127 p54spi_spi_write(priv, addr, &val, sizeof(val));
128}
129
130static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
131{
132 p54spi_spi_write(priv, addr, &val, sizeof(val));
133}
134
135static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
136{
137 int i;
138
139 for (i = 0; i < 2000; i++) {
140 u32 buffer = p54spi_read32(priv, reg);
141 if ((buffer & bits) == bits)
142 return 1;
143 }
144 return 0;
145}
146
147static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
148 const void *buf, size_t len)
149{
150 if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
151 dev_err(&priv->spi->dev, "spi_write_dma not allowed "
152 "to DMA write.\n");
153 return -EAGAIN;
154 }
155
156 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
157 cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
158
159 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
160 p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
161 p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
162 return 0;
163}
164
165static int p54spi_request_firmware(struct ieee80211_hw *dev)
166{
167 struct p54s_priv *priv = dev->priv;
168 int ret;
169
170 /* FIXME: should driver use it's own struct device? */
171 ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
172
173 if (ret < 0) {
174 dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
175 return ret;
176 }
177
178 ret = p54_parse_firmware(dev, priv->firmware);
179 if (ret) {
180 release_firmware(priv->firmware);
181 return ret;
182 }
183
184 return 0;
185}
186
187static int p54spi_request_eeprom(struct ieee80211_hw *dev)
188{
189 struct p54s_priv *priv = dev->priv;
190 const struct firmware *eeprom;
191 int ret;
192
193 /* allow users to customize their eeprom.
194 */
195
196 ret = request_firmware_direct(&eeprom, "3826.eeprom", &priv->spi->dev);
197 if (ret < 0) {
198#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
199 dev_info(&priv->spi->dev, "loading default eeprom...\n");
200 ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
201 sizeof(p54spi_eeprom));
202#else
203 dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
204#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
205 } else {
206 dev_info(&priv->spi->dev, "loading user eeprom...\n");
207 ret = p54_parse_eeprom(dev, (void *) eeprom->data,
208 (int)eeprom->size);
209 release_firmware(eeprom);
210 }
211 return ret;
212}
213
214static int p54spi_upload_firmware(struct ieee80211_hw *dev)
215{
216 struct p54s_priv *priv = dev->priv;
217 unsigned long fw_len, _fw_len;
218 unsigned int offset = 0;
219 int err = 0;
220 u8 *fw;
221
222 fw_len = priv->firmware->size;
223 fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
224 if (!fw)
225 return -ENOMEM;
226
227 /* stop the device */
228 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
229 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
230 SPI_CTRL_STAT_START_HALTED));
231
232 msleep(TARGET_BOOT_SLEEP);
233
234 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
235 SPI_CTRL_STAT_HOST_OVERRIDE |
236 SPI_CTRL_STAT_START_HALTED));
237
238 msleep(TARGET_BOOT_SLEEP);
239
240 while (fw_len > 0) {
241 _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
242
243 err = p54spi_spi_write_dma(priv, cpu_to_le32(
244 ISL38XX_DEV_FIRMWARE_ADDR + offset),
245 (fw + offset), _fw_len);
246 if (err < 0)
247 goto out;
248
249 fw_len -= _fw_len;
250 offset += _fw_len;
251 }
252
253 BUG_ON(fw_len != 0);
254
255 /* enable host interrupts */
256 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
257 cpu_to_le32(SPI_HOST_INTS_DEFAULT));
258
259 /* boot the device */
260 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
261 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
262 SPI_CTRL_STAT_RAM_BOOT));
263
264 msleep(TARGET_BOOT_SLEEP);
265
266 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
267 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
268 msleep(TARGET_BOOT_SLEEP);
269
270out:
271 kfree(fw);
272 return err;
273}
274
275static void p54spi_power_off(struct p54s_priv *priv)
276{
277 disable_irq(gpio_to_irq(p54spi_gpio_irq));
278 gpio_set_value(p54spi_gpio_power, 0);
279}
280
281static void p54spi_power_on(struct p54s_priv *priv)
282{
283 gpio_set_value(p54spi_gpio_power, 1);
284 enable_irq(gpio_to_irq(p54spi_gpio_irq));
285
286 /* need to wait a while before device can be accessed, the length
287 * is just a guess
288 */
289 msleep(10);
290}
291
292static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
293{
294 p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
295}
296
297static int p54spi_wakeup(struct p54s_priv *priv)
298{
299 /* wake the chip */
300 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
301 cpu_to_le32(SPI_TARGET_INT_WAKEUP));
302
303 /* And wait for the READY interrupt */
304 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
305 SPI_HOST_INT_READY)) {
306 dev_err(&priv->spi->dev, "INT_READY timeout\n");
307 return -EBUSY;
308 }
309
310 p54spi_int_ack(priv, SPI_HOST_INT_READY);
311 return 0;
312}
313
314static inline void p54spi_sleep(struct p54s_priv *priv)
315{
316 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
317 cpu_to_le32(SPI_TARGET_INT_SLEEP));
318}
319
320static void p54spi_int_ready(struct p54s_priv *priv)
321{
322 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
323 SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
324
325 switch (priv->fw_state) {
326 case FW_STATE_BOOTING:
327 priv->fw_state = FW_STATE_READY;
328 complete(&priv->fw_comp);
329 break;
330 case FW_STATE_RESETTING:
331 priv->fw_state = FW_STATE_READY;
332 /* TODO: reinitialize state */
333 break;
334 default:
335 break;
336 }
337}
338
339static int p54spi_rx(struct p54s_priv *priv)
340{
341 struct sk_buff *skb;
342 u16 len;
343 u16 rx_head[2];
344#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
345
346 if (p54spi_wakeup(priv) < 0)
347 return -EBUSY;
348
349 /* Read data size and first data word in one SPI transaction
350 * This is workaround for firmware/DMA bug,
351 * when first data word gets lost under high load.
352 */
353 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
354 len = rx_head[0];
355
356 if (len == 0) {
357 p54spi_sleep(priv);
358 dev_err(&priv->spi->dev, "rx request of zero bytes\n");
359 return 0;
360 }
361
362 /* Firmware may insert up to 4 padding bytes after the lmac header,
363 * but it does not amend the size of SPI data transfer.
364 * Such packets has correct data size in header, thus referencing
365 * past the end of allocated skb. Reserve extra 4 bytes for this case
366 */
367 skb = dev_alloc_skb(len + 4);
368 if (!skb) {
369 p54spi_sleep(priv);
370 dev_err(&priv->spi->dev, "could not alloc skb");
371 return -ENOMEM;
372 }
373
374 if (len <= READAHEAD_SZ) {
375 memcpy(skb_put(skb, len), rx_head + 1, len);
376 } else {
377 memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
378 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
379 skb_put(skb, len - READAHEAD_SZ),
380 len - READAHEAD_SZ);
381 }
382 p54spi_sleep(priv);
383 /* Put additional bytes to compensate for the possible
384 * alignment-caused truncation
385 */
386 skb_put(skb, 4);
387
388 if (p54_rx(priv->hw, skb) == 0)
389 dev_kfree_skb(skb);
390
391 return 0;
392}
393
394
395static irqreturn_t p54spi_interrupt(int irq, void *config)
396{
397 struct spi_device *spi = config;
398 struct p54s_priv *priv = spi_get_drvdata(spi);
399
400 ieee80211_queue_work(priv->hw, &priv->work);
401
402 return IRQ_HANDLED;
403}
404
405static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
406{
407 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
408 int ret = 0;
409
410 if (p54spi_wakeup(priv) < 0)
411 return -EBUSY;
412
413 ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
414 if (ret < 0)
415 goto out;
416
417 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
418 SPI_HOST_INT_WR_READY)) {
419 dev_err(&priv->spi->dev, "WR_READY timeout\n");
420 ret = -EAGAIN;
421 goto out;
422 }
423
424 p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
425
426 if (FREE_AFTER_TX(skb))
427 p54_free_skb(priv->hw, skb);
428out:
429 p54spi_sleep(priv);
430 return ret;
431}
432
433static int p54spi_wq_tx(struct p54s_priv *priv)
434{
435 struct p54s_tx_info *entry;
436 struct sk_buff *skb;
437 struct ieee80211_tx_info *info;
438 struct p54_tx_info *minfo;
439 struct p54s_tx_info *dinfo;
440 unsigned long flags;
441 int ret = 0;
442
443 spin_lock_irqsave(&priv->tx_lock, flags);
444
445 while (!list_empty(&priv->tx_pending)) {
446 entry = list_entry(priv->tx_pending.next,
447 struct p54s_tx_info, tx_list);
448
449 list_del_init(&entry->tx_list);
450
451 spin_unlock_irqrestore(&priv->tx_lock, flags);
452
453 dinfo = container_of((void *) entry, struct p54s_tx_info,
454 tx_list);
455 minfo = container_of((void *) dinfo, struct p54_tx_info,
456 data);
457 info = container_of((void *) minfo, struct ieee80211_tx_info,
458 rate_driver_data);
459 skb = container_of((void *) info, struct sk_buff, cb);
460
461 ret = p54spi_tx_frame(priv, skb);
462
463 if (ret < 0) {
464 p54_free_skb(priv->hw, skb);
465 return ret;
466 }
467
468 spin_lock_irqsave(&priv->tx_lock, flags);
469 }
470 spin_unlock_irqrestore(&priv->tx_lock, flags);
471 return ret;
472}
473
474static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
475{
476 struct p54s_priv *priv = dev->priv;
477 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
478 struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
479 struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
480 unsigned long flags;
481
482 BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
483
484 spin_lock_irqsave(&priv->tx_lock, flags);
485 list_add_tail(&di->tx_list, &priv->tx_pending);
486 spin_unlock_irqrestore(&priv->tx_lock, flags);
487
488 ieee80211_queue_work(priv->hw, &priv->work);
489}
490
491static void p54spi_work(struct work_struct *work)
492{
493 struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
494 u32 ints;
495 int ret;
496
497 mutex_lock(&priv->mutex);
498
499 if (priv->fw_state == FW_STATE_OFF)
500 goto out;
501
502 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
503
504 if (ints & SPI_HOST_INT_READY) {
505 p54spi_int_ready(priv);
506 p54spi_int_ack(priv, SPI_HOST_INT_READY);
507 }
508
509 if (priv->fw_state != FW_STATE_READY)
510 goto out;
511
512 if (ints & SPI_HOST_INT_UPDATE) {
513 p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
514 ret = p54spi_rx(priv);
515 if (ret < 0)
516 goto out;
517 }
518 if (ints & SPI_HOST_INT_SW_UPDATE) {
519 p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
520 ret = p54spi_rx(priv);
521 if (ret < 0)
522 goto out;
523 }
524
525 ret = p54spi_wq_tx(priv);
526out:
527 mutex_unlock(&priv->mutex);
528}
529
530static int p54spi_op_start(struct ieee80211_hw *dev)
531{
532 struct p54s_priv *priv = dev->priv;
533 unsigned long timeout;
534 int ret = 0;
535
536 if (mutex_lock_interruptible(&priv->mutex)) {
537 ret = -EINTR;
538 goto out;
539 }
540
541 priv->fw_state = FW_STATE_BOOTING;
542
543 p54spi_power_on(priv);
544
545 ret = p54spi_upload_firmware(dev);
546 if (ret < 0) {
547 p54spi_power_off(priv);
548 goto out_unlock;
549 }
550
551 mutex_unlock(&priv->mutex);
552
553 timeout = msecs_to_jiffies(2000);
554 timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
555 timeout);
556 if (!timeout) {
557 dev_err(&priv->spi->dev, "firmware boot failed");
558 p54spi_power_off(priv);
559 ret = -1;
560 goto out;
561 }
562
563 if (mutex_lock_interruptible(&priv->mutex)) {
564 ret = -EINTR;
565 p54spi_power_off(priv);
566 goto out;
567 }
568
569 WARN_ON(priv->fw_state != FW_STATE_READY);
570
571out_unlock:
572 mutex_unlock(&priv->mutex);
573
574out:
575 return ret;
576}
577
578static void p54spi_op_stop(struct ieee80211_hw *dev)
579{
580 struct p54s_priv *priv = dev->priv;
581 unsigned long flags;
582
583 mutex_lock(&priv->mutex);
584 WARN_ON(priv->fw_state != FW_STATE_READY);
585
586 p54spi_power_off(priv);
587 spin_lock_irqsave(&priv->tx_lock, flags);
588 INIT_LIST_HEAD(&priv->tx_pending);
589 spin_unlock_irqrestore(&priv->tx_lock, flags);
590
591 priv->fw_state = FW_STATE_OFF;
592 mutex_unlock(&priv->mutex);
593
594 cancel_work_sync(&priv->work);
595}
596
597static int p54spi_probe(struct spi_device *spi)
598{
599 struct p54s_priv *priv = NULL;
600 struct ieee80211_hw *hw;
601 int ret = -EINVAL;
602
603 hw = p54_init_common(sizeof(*priv));
604 if (!hw) {
605 dev_err(&spi->dev, "could not alloc ieee80211_hw");
606 return -ENOMEM;
607 }
608
609 priv = hw->priv;
610 priv->hw = hw;
611 spi_set_drvdata(spi, priv);
612 priv->spi = spi;
613
614 spi->bits_per_word = 16;
615 spi->max_speed_hz = 24000000;
616
617 ret = spi_setup(spi);
618 if (ret < 0) {
619 dev_err(&priv->spi->dev, "spi_setup failed");
620 goto err_free;
621 }
622
623 ret = gpio_request(p54spi_gpio_power, "p54spi power");
624 if (ret < 0) {
625 dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
626 goto err_free;
627 }
628
629 ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
630 if (ret < 0) {
631 dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
632 goto err_free_gpio_power;
633 }
634
635 gpio_direction_output(p54spi_gpio_power, 0);
636 gpio_direction_input(p54spi_gpio_irq);
637
638 ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
639 p54spi_interrupt, 0, "p54spi",
640 priv->spi);
641 if (ret < 0) {
642 dev_err(&priv->spi->dev, "request_irq() failed");
643 goto err_free_gpio_irq;
644 }
645
646 irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);
647
648 disable_irq(gpio_to_irq(p54spi_gpio_irq));
649
650 INIT_WORK(&priv->work, p54spi_work);
651 init_completion(&priv->fw_comp);
652 INIT_LIST_HEAD(&priv->tx_pending);
653 mutex_init(&priv->mutex);
654 spin_lock_init(&priv->tx_lock);
655 SET_IEEE80211_DEV(hw, &spi->dev);
656 priv->common.open = p54spi_op_start;
657 priv->common.stop = p54spi_op_stop;
658 priv->common.tx = p54spi_op_tx;
659
660 ret = p54spi_request_firmware(hw);
661 if (ret < 0)
662 goto err_free_common;
663
664 ret = p54spi_request_eeprom(hw);
665 if (ret)
666 goto err_free_common;
667
668 ret = p54_register_common(hw, &priv->spi->dev);
669 if (ret)
670 goto err_free_common;
671
672 return 0;
673
674err_free_common:
675 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
676err_free_gpio_irq:
677 gpio_free(p54spi_gpio_irq);
678err_free_gpio_power:
679 gpio_free(p54spi_gpio_power);
680err_free:
681 p54_free_common(priv->hw);
682 return ret;
683}
684
685static int p54spi_remove(struct spi_device *spi)
686{
687 struct p54s_priv *priv = spi_get_drvdata(spi);
688
689 p54_unregister_common(priv->hw);
690
691 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
692
693 gpio_free(p54spi_gpio_power);
694 gpio_free(p54spi_gpio_irq);
695 release_firmware(priv->firmware);
696
697 mutex_destroy(&priv->mutex);
698
699 p54_free_common(priv->hw);
700
701 return 0;
702}
703
704
705static struct spi_driver p54spi_driver = {
706 .driver = {
707 .name = "p54spi",
708 },
709
710 .probe = p54spi_probe,
711 .remove = p54spi_remove,
712};
713
714module_spi_driver(p54spi_driver);
715
716MODULE_LICENSE("GPL");
717MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
718MODULE_ALIAS("spi:cx3110x");
719MODULE_ALIAS("spi:p54spi");
720MODULE_ALIAS("spi:stlc45xx");