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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
4 * Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
5 *
6 * This driver is a port from stlc45xx:
7 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
8 */
9
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/interrupt.h>
13#include <linux/firmware.h>
14#include <linux/delay.h>
15#include <linux/irq.h>
16#include <linux/spi/spi.h>
17#include <linux/etherdevice.h>
18#include <linux/gpio.h>
19#include <linux/slab.h>
20
21#include "p54spi.h"
22#include "p54.h"
23
24#include "lmac.h"
25
26#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
27#include "p54spi_eeprom.h"
28#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
29
30MODULE_FIRMWARE("3826.arm");
31MODULE_FIRMWARE("3826.eeprom");
32
33/* gpios should be handled in board files and provided via platform data,
34 * but because it's currently impossible for p54spi to have a header file
35 * in include/linux, let's use module paramaters for now
36 */
37
38static int p54spi_gpio_power = 97;
39module_param(p54spi_gpio_power, int, 0444);
40MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
41
42static int p54spi_gpio_irq = 87;
43module_param(p54spi_gpio_irq, int, 0444);
44MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
45
46static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
47 void *buf, size_t len)
48{
49 struct spi_transfer t[2];
50 struct spi_message m;
51 __le16 addr;
52
53 /* We first push the address */
54 addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
55
56 spi_message_init(&m);
57 memset(t, 0, sizeof(t));
58
59 t[0].tx_buf = &addr;
60 t[0].len = sizeof(addr);
61 spi_message_add_tail(&t[0], &m);
62
63 t[1].rx_buf = buf;
64 t[1].len = len;
65 spi_message_add_tail(&t[1], &m);
66
67 spi_sync(priv->spi, &m);
68}
69
70
71static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
72 const void *buf, size_t len)
73{
74 struct spi_transfer t[3];
75 struct spi_message m;
76 __le16 addr;
77
78 /* We first push the address */
79 addr = cpu_to_le16(address << 8);
80
81 spi_message_init(&m);
82 memset(t, 0, sizeof(t));
83
84 t[0].tx_buf = &addr;
85 t[0].len = sizeof(addr);
86 spi_message_add_tail(&t[0], &m);
87
88 t[1].tx_buf = buf;
89 t[1].len = len & ~1;
90 spi_message_add_tail(&t[1], &m);
91
92 if (len % 2) {
93 __le16 last_word;
94 last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
95
96 t[2].tx_buf = &last_word;
97 t[2].len = sizeof(last_word);
98 spi_message_add_tail(&t[2], &m);
99 }
100
101 spi_sync(priv->spi, &m);
102}
103
104static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
105{
106 __le32 val;
107
108 p54spi_spi_read(priv, addr, &val, sizeof(val));
109
110 return le32_to_cpu(val);
111}
112
113static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
114{
115 p54spi_spi_write(priv, addr, &val, sizeof(val));
116}
117
118static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
119{
120 p54spi_spi_write(priv, addr, &val, sizeof(val));
121}
122
123static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
124{
125 int i;
126
127 for (i = 0; i < 2000; i++) {
128 u32 buffer = p54spi_read32(priv, reg);
129 if ((buffer & bits) == bits)
130 return 1;
131 }
132 return 0;
133}
134
135static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
136 const void *buf, size_t len)
137{
138 if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
139 dev_err(&priv->spi->dev, "spi_write_dma not allowed "
140 "to DMA write.\n");
141 return -EAGAIN;
142 }
143
144 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
145 cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
146
147 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
148 p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
149 p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
150 return 0;
151}
152
153static int p54spi_request_firmware(struct ieee80211_hw *dev)
154{
155 struct p54s_priv *priv = dev->priv;
156 int ret;
157
158 /* FIXME: should driver use it's own struct device? */
159 ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
160
161 if (ret < 0) {
162 dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
163 return ret;
164 }
165
166 ret = p54_parse_firmware(dev, priv->firmware);
167 if (ret) {
168 /* the firmware is released by the caller */
169 return ret;
170 }
171
172 return 0;
173}
174
175static int p54spi_request_eeprom(struct ieee80211_hw *dev)
176{
177 struct p54s_priv *priv = dev->priv;
178 const struct firmware *eeprom;
179 int ret;
180
181 /* allow users to customize their eeprom.
182 */
183
184 ret = request_firmware_direct(&eeprom, "3826.eeprom", &priv->spi->dev);
185 if (ret < 0) {
186#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
187 dev_info(&priv->spi->dev, "loading default eeprom...\n");
188 ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
189 sizeof(p54spi_eeprom));
190#else
191 dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
192#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
193 } else {
194 dev_info(&priv->spi->dev, "loading user eeprom...\n");
195 ret = p54_parse_eeprom(dev, (void *) eeprom->data,
196 (int)eeprom->size);
197 release_firmware(eeprom);
198 }
199 return ret;
200}
201
202static int p54spi_upload_firmware(struct ieee80211_hw *dev)
203{
204 struct p54s_priv *priv = dev->priv;
205 unsigned long fw_len, _fw_len;
206 unsigned int offset = 0;
207 int err = 0;
208 u8 *fw;
209
210 fw_len = priv->firmware->size;
211 fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
212 if (!fw)
213 return -ENOMEM;
214
215 /* stop the device */
216 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
217 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
218 SPI_CTRL_STAT_START_HALTED));
219
220 msleep(TARGET_BOOT_SLEEP);
221
222 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
223 SPI_CTRL_STAT_HOST_OVERRIDE |
224 SPI_CTRL_STAT_START_HALTED));
225
226 msleep(TARGET_BOOT_SLEEP);
227
228 while (fw_len > 0) {
229 _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
230
231 err = p54spi_spi_write_dma(priv, cpu_to_le32(
232 ISL38XX_DEV_FIRMWARE_ADDR + offset),
233 (fw + offset), _fw_len);
234 if (err < 0)
235 goto out;
236
237 fw_len -= _fw_len;
238 offset += _fw_len;
239 }
240
241 BUG_ON(fw_len != 0);
242
243 /* enable host interrupts */
244 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
245 cpu_to_le32(SPI_HOST_INTS_DEFAULT));
246
247 /* boot the device */
248 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
249 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
250 SPI_CTRL_STAT_RAM_BOOT));
251
252 msleep(TARGET_BOOT_SLEEP);
253
254 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
255 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
256 msleep(TARGET_BOOT_SLEEP);
257
258out:
259 kfree(fw);
260 return err;
261}
262
263static void p54spi_power_off(struct p54s_priv *priv)
264{
265 disable_irq(gpio_to_irq(p54spi_gpio_irq));
266 gpio_set_value(p54spi_gpio_power, 0);
267}
268
269static void p54spi_power_on(struct p54s_priv *priv)
270{
271 gpio_set_value(p54spi_gpio_power, 1);
272 enable_irq(gpio_to_irq(p54spi_gpio_irq));
273
274 /* need to wait a while before device can be accessed, the length
275 * is just a guess
276 */
277 msleep(10);
278}
279
280static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
281{
282 p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
283}
284
285static int p54spi_wakeup(struct p54s_priv *priv)
286{
287 /* wake the chip */
288 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
289 cpu_to_le32(SPI_TARGET_INT_WAKEUP));
290
291 /* And wait for the READY interrupt */
292 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
293 SPI_HOST_INT_READY)) {
294 dev_err(&priv->spi->dev, "INT_READY timeout\n");
295 return -EBUSY;
296 }
297
298 p54spi_int_ack(priv, SPI_HOST_INT_READY);
299 return 0;
300}
301
302static inline void p54spi_sleep(struct p54s_priv *priv)
303{
304 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
305 cpu_to_le32(SPI_TARGET_INT_SLEEP));
306}
307
308static void p54spi_int_ready(struct p54s_priv *priv)
309{
310 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
311 SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
312
313 switch (priv->fw_state) {
314 case FW_STATE_BOOTING:
315 priv->fw_state = FW_STATE_READY;
316 complete(&priv->fw_comp);
317 break;
318 case FW_STATE_RESETTING:
319 priv->fw_state = FW_STATE_READY;
320 /* TODO: reinitialize state */
321 break;
322 default:
323 break;
324 }
325}
326
327static int p54spi_rx(struct p54s_priv *priv)
328{
329 struct sk_buff *skb;
330 u16 len;
331 u16 rx_head[2];
332#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
333
334 if (p54spi_wakeup(priv) < 0)
335 return -EBUSY;
336
337 /* Read data size and first data word in one SPI transaction
338 * This is workaround for firmware/DMA bug,
339 * when first data word gets lost under high load.
340 */
341 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
342 len = rx_head[0];
343
344 if (len == 0) {
345 p54spi_sleep(priv);
346 dev_err(&priv->spi->dev, "rx request of zero bytes\n");
347 return 0;
348 }
349
350 /* Firmware may insert up to 4 padding bytes after the lmac header,
351 * but it does not amend the size of SPI data transfer.
352 * Such packets has correct data size in header, thus referencing
353 * past the end of allocated skb. Reserve extra 4 bytes for this case
354 */
355 skb = dev_alloc_skb(len + 4);
356 if (!skb) {
357 p54spi_sleep(priv);
358 dev_err(&priv->spi->dev, "could not alloc skb");
359 return -ENOMEM;
360 }
361
362 if (len <= READAHEAD_SZ) {
363 skb_put_data(skb, rx_head + 1, len);
364 } else {
365 skb_put_data(skb, rx_head + 1, READAHEAD_SZ);
366 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
367 skb_put(skb, len - READAHEAD_SZ),
368 len - READAHEAD_SZ);
369 }
370 p54spi_sleep(priv);
371 /* Put additional bytes to compensate for the possible
372 * alignment-caused truncation
373 */
374 skb_put(skb, 4);
375
376 if (p54_rx(priv->hw, skb) == 0)
377 dev_kfree_skb(skb);
378
379 return 0;
380}
381
382
383static irqreturn_t p54spi_interrupt(int irq, void *config)
384{
385 struct spi_device *spi = config;
386 struct p54s_priv *priv = spi_get_drvdata(spi);
387
388 ieee80211_queue_work(priv->hw, &priv->work);
389
390 return IRQ_HANDLED;
391}
392
393static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
394{
395 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
396 int ret = 0;
397
398 if (p54spi_wakeup(priv) < 0)
399 return -EBUSY;
400
401 ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
402 if (ret < 0)
403 goto out;
404
405 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
406 SPI_HOST_INT_WR_READY)) {
407 dev_err(&priv->spi->dev, "WR_READY timeout\n");
408 ret = -EAGAIN;
409 goto out;
410 }
411
412 p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
413
414 if (FREE_AFTER_TX(skb))
415 p54_free_skb(priv->hw, skb);
416out:
417 p54spi_sleep(priv);
418 return ret;
419}
420
421static int p54spi_wq_tx(struct p54s_priv *priv)
422{
423 struct p54s_tx_info *entry;
424 struct sk_buff *skb;
425 struct ieee80211_tx_info *info;
426 struct p54_tx_info *minfo;
427 struct p54s_tx_info *dinfo;
428 unsigned long flags;
429 int ret = 0;
430
431 spin_lock_irqsave(&priv->tx_lock, flags);
432
433 while (!list_empty(&priv->tx_pending)) {
434 entry = list_entry(priv->tx_pending.next,
435 struct p54s_tx_info, tx_list);
436
437 list_del_init(&entry->tx_list);
438
439 spin_unlock_irqrestore(&priv->tx_lock, flags);
440
441 dinfo = container_of((void *) entry, struct p54s_tx_info,
442 tx_list);
443 minfo = container_of((void *) dinfo, struct p54_tx_info,
444 data);
445 info = container_of((void *) minfo, struct ieee80211_tx_info,
446 rate_driver_data);
447 skb = container_of((void *) info, struct sk_buff, cb);
448
449 ret = p54spi_tx_frame(priv, skb);
450
451 if (ret < 0) {
452 p54_free_skb(priv->hw, skb);
453 return ret;
454 }
455
456 spin_lock_irqsave(&priv->tx_lock, flags);
457 }
458 spin_unlock_irqrestore(&priv->tx_lock, flags);
459 return ret;
460}
461
462static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
463{
464 struct p54s_priv *priv = dev->priv;
465 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
466 struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
467 struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
468 unsigned long flags;
469
470 BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
471
472 spin_lock_irqsave(&priv->tx_lock, flags);
473 list_add_tail(&di->tx_list, &priv->tx_pending);
474 spin_unlock_irqrestore(&priv->tx_lock, flags);
475
476 ieee80211_queue_work(priv->hw, &priv->work);
477}
478
479static void p54spi_work(struct work_struct *work)
480{
481 struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
482 u32 ints;
483 int ret;
484
485 mutex_lock(&priv->mutex);
486
487 if (priv->fw_state == FW_STATE_OFF)
488 goto out;
489
490 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
491
492 if (ints & SPI_HOST_INT_READY) {
493 p54spi_int_ready(priv);
494 p54spi_int_ack(priv, SPI_HOST_INT_READY);
495 }
496
497 if (priv->fw_state != FW_STATE_READY)
498 goto out;
499
500 if (ints & SPI_HOST_INT_UPDATE) {
501 p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
502 ret = p54spi_rx(priv);
503 if (ret < 0)
504 goto out;
505 }
506 if (ints & SPI_HOST_INT_SW_UPDATE) {
507 p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
508 ret = p54spi_rx(priv);
509 if (ret < 0)
510 goto out;
511 }
512
513 ret = p54spi_wq_tx(priv);
514out:
515 mutex_unlock(&priv->mutex);
516}
517
518static int p54spi_op_start(struct ieee80211_hw *dev)
519{
520 struct p54s_priv *priv = dev->priv;
521 unsigned long timeout;
522 int ret = 0;
523
524 if (mutex_lock_interruptible(&priv->mutex)) {
525 ret = -EINTR;
526 goto out;
527 }
528
529 priv->fw_state = FW_STATE_BOOTING;
530
531 p54spi_power_on(priv);
532
533 ret = p54spi_upload_firmware(dev);
534 if (ret < 0) {
535 p54spi_power_off(priv);
536 goto out_unlock;
537 }
538
539 mutex_unlock(&priv->mutex);
540
541 timeout = msecs_to_jiffies(2000);
542 timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
543 timeout);
544 if (!timeout) {
545 dev_err(&priv->spi->dev, "firmware boot failed");
546 p54spi_power_off(priv);
547 ret = -1;
548 goto out;
549 }
550
551 if (mutex_lock_interruptible(&priv->mutex)) {
552 ret = -EINTR;
553 p54spi_power_off(priv);
554 goto out;
555 }
556
557 WARN_ON(priv->fw_state != FW_STATE_READY);
558
559out_unlock:
560 mutex_unlock(&priv->mutex);
561
562out:
563 return ret;
564}
565
566static void p54spi_op_stop(struct ieee80211_hw *dev)
567{
568 struct p54s_priv *priv = dev->priv;
569 unsigned long flags;
570
571 mutex_lock(&priv->mutex);
572 WARN_ON(priv->fw_state != FW_STATE_READY);
573
574 p54spi_power_off(priv);
575 spin_lock_irqsave(&priv->tx_lock, flags);
576 INIT_LIST_HEAD(&priv->tx_pending);
577 spin_unlock_irqrestore(&priv->tx_lock, flags);
578
579 priv->fw_state = FW_STATE_OFF;
580 mutex_unlock(&priv->mutex);
581
582 cancel_work_sync(&priv->work);
583}
584
585static int p54spi_probe(struct spi_device *spi)
586{
587 struct p54s_priv *priv = NULL;
588 struct ieee80211_hw *hw;
589 int ret = -EINVAL;
590
591 hw = p54_init_common(sizeof(*priv));
592 if (!hw) {
593 dev_err(&spi->dev, "could not alloc ieee80211_hw");
594 return -ENOMEM;
595 }
596
597 priv = hw->priv;
598 priv->hw = hw;
599 spi_set_drvdata(spi, priv);
600 priv->spi = spi;
601
602 spi->bits_per_word = 16;
603 spi->max_speed_hz = 24000000;
604
605 ret = spi_setup(spi);
606 if (ret < 0) {
607 dev_err(&priv->spi->dev, "spi_setup failed");
608 goto err_free;
609 }
610
611 ret = gpio_request(p54spi_gpio_power, "p54spi power");
612 if (ret < 0) {
613 dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
614 goto err_free;
615 }
616
617 ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
618 if (ret < 0) {
619 dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
620 goto err_free_gpio_power;
621 }
622
623 gpio_direction_output(p54spi_gpio_power, 0);
624 gpio_direction_input(p54spi_gpio_irq);
625
626 ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
627 p54spi_interrupt, 0, "p54spi",
628 priv->spi);
629 if (ret < 0) {
630 dev_err(&priv->spi->dev, "request_irq() failed");
631 goto err_free_gpio_irq;
632 }
633
634 irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);
635
636 disable_irq(gpio_to_irq(p54spi_gpio_irq));
637
638 INIT_WORK(&priv->work, p54spi_work);
639 init_completion(&priv->fw_comp);
640 INIT_LIST_HEAD(&priv->tx_pending);
641 mutex_init(&priv->mutex);
642 spin_lock_init(&priv->tx_lock);
643 SET_IEEE80211_DEV(hw, &spi->dev);
644 priv->common.open = p54spi_op_start;
645 priv->common.stop = p54spi_op_stop;
646 priv->common.tx = p54spi_op_tx;
647
648 ret = p54spi_request_firmware(hw);
649 if (ret < 0)
650 goto err_free_common;
651
652 ret = p54spi_request_eeprom(hw);
653 if (ret)
654 goto err_free_common;
655
656 ret = p54_register_common(hw, &priv->spi->dev);
657 if (ret)
658 goto err_free_common;
659
660 return 0;
661
662err_free_common:
663 release_firmware(priv->firmware);
664 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
665err_free_gpio_irq:
666 gpio_free(p54spi_gpio_irq);
667err_free_gpio_power:
668 gpio_free(p54spi_gpio_power);
669err_free:
670 p54_free_common(priv->hw);
671 return ret;
672}
673
674static void p54spi_remove(struct spi_device *spi)
675{
676 struct p54s_priv *priv = spi_get_drvdata(spi);
677
678 p54_unregister_common(priv->hw);
679
680 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
681
682 gpio_free(p54spi_gpio_power);
683 gpio_free(p54spi_gpio_irq);
684 release_firmware(priv->firmware);
685
686 mutex_destroy(&priv->mutex);
687
688 p54_free_common(priv->hw);
689}
690
691
692static struct spi_driver p54spi_driver = {
693 .driver = {
694 .name = "p54spi",
695 },
696
697 .probe = p54spi_probe,
698 .remove = p54spi_remove,
699};
700
701module_spi_driver(p54spi_driver);
702
703MODULE_DESCRIPTION("Prism54 SPI wireless driver");
704MODULE_LICENSE("GPL");
705MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
706MODULE_ALIAS("spi:cx3110x");
707MODULE_ALIAS("spi:p54spi");
708MODULE_ALIAS("spi:stlc45xx");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
4 * Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
5 *
6 * This driver is a port from stlc45xx:
7 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
8 */
9
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/interrupt.h>
13#include <linux/firmware.h>
14#include <linux/delay.h>
15#include <linux/irq.h>
16#include <linux/spi/spi.h>
17#include <linux/etherdevice.h>
18#include <linux/gpio.h>
19#include <linux/slab.h>
20
21#include "p54spi.h"
22#include "p54.h"
23
24#include "lmac.h"
25
26#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
27#include "p54spi_eeprom.h"
28#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
29
30MODULE_FIRMWARE("3826.arm");
31
32/* gpios should be handled in board files and provided via platform data,
33 * but because it's currently impossible for p54spi to have a header file
34 * in include/linux, let's use module paramaters for now
35 */
36
37static int p54spi_gpio_power = 97;
38module_param(p54spi_gpio_power, int, 0444);
39MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
40
41static int p54spi_gpio_irq = 87;
42module_param(p54spi_gpio_irq, int, 0444);
43MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
44
45static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
46 void *buf, size_t len)
47{
48 struct spi_transfer t[2];
49 struct spi_message m;
50 __le16 addr;
51
52 /* We first push the address */
53 addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
54
55 spi_message_init(&m);
56 memset(t, 0, sizeof(t));
57
58 t[0].tx_buf = &addr;
59 t[0].len = sizeof(addr);
60 spi_message_add_tail(&t[0], &m);
61
62 t[1].rx_buf = buf;
63 t[1].len = len;
64 spi_message_add_tail(&t[1], &m);
65
66 spi_sync(priv->spi, &m);
67}
68
69
70static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
71 const void *buf, size_t len)
72{
73 struct spi_transfer t[3];
74 struct spi_message m;
75 __le16 addr;
76
77 /* We first push the address */
78 addr = cpu_to_le16(address << 8);
79
80 spi_message_init(&m);
81 memset(t, 0, sizeof(t));
82
83 t[0].tx_buf = &addr;
84 t[0].len = sizeof(addr);
85 spi_message_add_tail(&t[0], &m);
86
87 t[1].tx_buf = buf;
88 t[1].len = len & ~1;
89 spi_message_add_tail(&t[1], &m);
90
91 if (len % 2) {
92 __le16 last_word;
93 last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
94
95 t[2].tx_buf = &last_word;
96 t[2].len = sizeof(last_word);
97 spi_message_add_tail(&t[2], &m);
98 }
99
100 spi_sync(priv->spi, &m);
101}
102
103static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
104{
105 __le32 val;
106
107 p54spi_spi_read(priv, addr, &val, sizeof(val));
108
109 return le32_to_cpu(val);
110}
111
112static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
113{
114 p54spi_spi_write(priv, addr, &val, sizeof(val));
115}
116
117static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
118{
119 p54spi_spi_write(priv, addr, &val, sizeof(val));
120}
121
122static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
123{
124 int i;
125
126 for (i = 0; i < 2000; i++) {
127 u32 buffer = p54spi_read32(priv, reg);
128 if ((buffer & bits) == bits)
129 return 1;
130 }
131 return 0;
132}
133
134static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
135 const void *buf, size_t len)
136{
137 if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
138 dev_err(&priv->spi->dev, "spi_write_dma not allowed "
139 "to DMA write.\n");
140 return -EAGAIN;
141 }
142
143 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
144 cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
145
146 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
147 p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
148 p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
149 return 0;
150}
151
152static int p54spi_request_firmware(struct ieee80211_hw *dev)
153{
154 struct p54s_priv *priv = dev->priv;
155 int ret;
156
157 /* FIXME: should driver use it's own struct device? */
158 ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
159
160 if (ret < 0) {
161 dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
162 return ret;
163 }
164
165 ret = p54_parse_firmware(dev, priv->firmware);
166 if (ret) {
167 release_firmware(priv->firmware);
168 return ret;
169 }
170
171 return 0;
172}
173
174static int p54spi_request_eeprom(struct ieee80211_hw *dev)
175{
176 struct p54s_priv *priv = dev->priv;
177 const struct firmware *eeprom;
178 int ret;
179
180 /* allow users to customize their eeprom.
181 */
182
183 ret = request_firmware_direct(&eeprom, "3826.eeprom", &priv->spi->dev);
184 if (ret < 0) {
185#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
186 dev_info(&priv->spi->dev, "loading default eeprom...\n");
187 ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
188 sizeof(p54spi_eeprom));
189#else
190 dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
191#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
192 } else {
193 dev_info(&priv->spi->dev, "loading user eeprom...\n");
194 ret = p54_parse_eeprom(dev, (void *) eeprom->data,
195 (int)eeprom->size);
196 release_firmware(eeprom);
197 }
198 return ret;
199}
200
201static int p54spi_upload_firmware(struct ieee80211_hw *dev)
202{
203 struct p54s_priv *priv = dev->priv;
204 unsigned long fw_len, _fw_len;
205 unsigned int offset = 0;
206 int err = 0;
207 u8 *fw;
208
209 fw_len = priv->firmware->size;
210 fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
211 if (!fw)
212 return -ENOMEM;
213
214 /* stop the device */
215 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
216 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
217 SPI_CTRL_STAT_START_HALTED));
218
219 msleep(TARGET_BOOT_SLEEP);
220
221 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
222 SPI_CTRL_STAT_HOST_OVERRIDE |
223 SPI_CTRL_STAT_START_HALTED));
224
225 msleep(TARGET_BOOT_SLEEP);
226
227 while (fw_len > 0) {
228 _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
229
230 err = p54spi_spi_write_dma(priv, cpu_to_le32(
231 ISL38XX_DEV_FIRMWARE_ADDR + offset),
232 (fw + offset), _fw_len);
233 if (err < 0)
234 goto out;
235
236 fw_len -= _fw_len;
237 offset += _fw_len;
238 }
239
240 BUG_ON(fw_len != 0);
241
242 /* enable host interrupts */
243 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
244 cpu_to_le32(SPI_HOST_INTS_DEFAULT));
245
246 /* boot the device */
247 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
248 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
249 SPI_CTRL_STAT_RAM_BOOT));
250
251 msleep(TARGET_BOOT_SLEEP);
252
253 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
254 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
255 msleep(TARGET_BOOT_SLEEP);
256
257out:
258 kfree(fw);
259 return err;
260}
261
262static void p54spi_power_off(struct p54s_priv *priv)
263{
264 disable_irq(gpio_to_irq(p54spi_gpio_irq));
265 gpio_set_value(p54spi_gpio_power, 0);
266}
267
268static void p54spi_power_on(struct p54s_priv *priv)
269{
270 gpio_set_value(p54spi_gpio_power, 1);
271 enable_irq(gpio_to_irq(p54spi_gpio_irq));
272
273 /* need to wait a while before device can be accessed, the length
274 * is just a guess
275 */
276 msleep(10);
277}
278
279static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
280{
281 p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
282}
283
284static int p54spi_wakeup(struct p54s_priv *priv)
285{
286 /* wake the chip */
287 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
288 cpu_to_le32(SPI_TARGET_INT_WAKEUP));
289
290 /* And wait for the READY interrupt */
291 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
292 SPI_HOST_INT_READY)) {
293 dev_err(&priv->spi->dev, "INT_READY timeout\n");
294 return -EBUSY;
295 }
296
297 p54spi_int_ack(priv, SPI_HOST_INT_READY);
298 return 0;
299}
300
301static inline void p54spi_sleep(struct p54s_priv *priv)
302{
303 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
304 cpu_to_le32(SPI_TARGET_INT_SLEEP));
305}
306
307static void p54spi_int_ready(struct p54s_priv *priv)
308{
309 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
310 SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
311
312 switch (priv->fw_state) {
313 case FW_STATE_BOOTING:
314 priv->fw_state = FW_STATE_READY;
315 complete(&priv->fw_comp);
316 break;
317 case FW_STATE_RESETTING:
318 priv->fw_state = FW_STATE_READY;
319 /* TODO: reinitialize state */
320 break;
321 default:
322 break;
323 }
324}
325
326static int p54spi_rx(struct p54s_priv *priv)
327{
328 struct sk_buff *skb;
329 u16 len;
330 u16 rx_head[2];
331#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
332
333 if (p54spi_wakeup(priv) < 0)
334 return -EBUSY;
335
336 /* Read data size and first data word in one SPI transaction
337 * This is workaround for firmware/DMA bug,
338 * when first data word gets lost under high load.
339 */
340 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
341 len = rx_head[0];
342
343 if (len == 0) {
344 p54spi_sleep(priv);
345 dev_err(&priv->spi->dev, "rx request of zero bytes\n");
346 return 0;
347 }
348
349 /* Firmware may insert up to 4 padding bytes after the lmac header,
350 * but it does not amend the size of SPI data transfer.
351 * Such packets has correct data size in header, thus referencing
352 * past the end of allocated skb. Reserve extra 4 bytes for this case
353 */
354 skb = dev_alloc_skb(len + 4);
355 if (!skb) {
356 p54spi_sleep(priv);
357 dev_err(&priv->spi->dev, "could not alloc skb");
358 return -ENOMEM;
359 }
360
361 if (len <= READAHEAD_SZ) {
362 skb_put_data(skb, rx_head + 1, len);
363 } else {
364 skb_put_data(skb, rx_head + 1, READAHEAD_SZ);
365 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
366 skb_put(skb, len - READAHEAD_SZ),
367 len - READAHEAD_SZ);
368 }
369 p54spi_sleep(priv);
370 /* Put additional bytes to compensate for the possible
371 * alignment-caused truncation
372 */
373 skb_put(skb, 4);
374
375 if (p54_rx(priv->hw, skb) == 0)
376 dev_kfree_skb(skb);
377
378 return 0;
379}
380
381
382static irqreturn_t p54spi_interrupt(int irq, void *config)
383{
384 struct spi_device *spi = config;
385 struct p54s_priv *priv = spi_get_drvdata(spi);
386
387 ieee80211_queue_work(priv->hw, &priv->work);
388
389 return IRQ_HANDLED;
390}
391
392static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
393{
394 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
395 int ret = 0;
396
397 if (p54spi_wakeup(priv) < 0)
398 return -EBUSY;
399
400 ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
401 if (ret < 0)
402 goto out;
403
404 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
405 SPI_HOST_INT_WR_READY)) {
406 dev_err(&priv->spi->dev, "WR_READY timeout\n");
407 ret = -EAGAIN;
408 goto out;
409 }
410
411 p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
412
413 if (FREE_AFTER_TX(skb))
414 p54_free_skb(priv->hw, skb);
415out:
416 p54spi_sleep(priv);
417 return ret;
418}
419
420static int p54spi_wq_tx(struct p54s_priv *priv)
421{
422 struct p54s_tx_info *entry;
423 struct sk_buff *skb;
424 struct ieee80211_tx_info *info;
425 struct p54_tx_info *minfo;
426 struct p54s_tx_info *dinfo;
427 unsigned long flags;
428 int ret = 0;
429
430 spin_lock_irqsave(&priv->tx_lock, flags);
431
432 while (!list_empty(&priv->tx_pending)) {
433 entry = list_entry(priv->tx_pending.next,
434 struct p54s_tx_info, tx_list);
435
436 list_del_init(&entry->tx_list);
437
438 spin_unlock_irqrestore(&priv->tx_lock, flags);
439
440 dinfo = container_of((void *) entry, struct p54s_tx_info,
441 tx_list);
442 minfo = container_of((void *) dinfo, struct p54_tx_info,
443 data);
444 info = container_of((void *) minfo, struct ieee80211_tx_info,
445 rate_driver_data);
446 skb = container_of((void *) info, struct sk_buff, cb);
447
448 ret = p54spi_tx_frame(priv, skb);
449
450 if (ret < 0) {
451 p54_free_skb(priv->hw, skb);
452 return ret;
453 }
454
455 spin_lock_irqsave(&priv->tx_lock, flags);
456 }
457 spin_unlock_irqrestore(&priv->tx_lock, flags);
458 return ret;
459}
460
461static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
462{
463 struct p54s_priv *priv = dev->priv;
464 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
465 struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
466 struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
467 unsigned long flags;
468
469 BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
470
471 spin_lock_irqsave(&priv->tx_lock, flags);
472 list_add_tail(&di->tx_list, &priv->tx_pending);
473 spin_unlock_irqrestore(&priv->tx_lock, flags);
474
475 ieee80211_queue_work(priv->hw, &priv->work);
476}
477
478static void p54spi_work(struct work_struct *work)
479{
480 struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
481 u32 ints;
482 int ret;
483
484 mutex_lock(&priv->mutex);
485
486 if (priv->fw_state == FW_STATE_OFF)
487 goto out;
488
489 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
490
491 if (ints & SPI_HOST_INT_READY) {
492 p54spi_int_ready(priv);
493 p54spi_int_ack(priv, SPI_HOST_INT_READY);
494 }
495
496 if (priv->fw_state != FW_STATE_READY)
497 goto out;
498
499 if (ints & SPI_HOST_INT_UPDATE) {
500 p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
501 ret = p54spi_rx(priv);
502 if (ret < 0)
503 goto out;
504 }
505 if (ints & SPI_HOST_INT_SW_UPDATE) {
506 p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
507 ret = p54spi_rx(priv);
508 if (ret < 0)
509 goto out;
510 }
511
512 ret = p54spi_wq_tx(priv);
513out:
514 mutex_unlock(&priv->mutex);
515}
516
517static int p54spi_op_start(struct ieee80211_hw *dev)
518{
519 struct p54s_priv *priv = dev->priv;
520 unsigned long timeout;
521 int ret = 0;
522
523 if (mutex_lock_interruptible(&priv->mutex)) {
524 ret = -EINTR;
525 goto out;
526 }
527
528 priv->fw_state = FW_STATE_BOOTING;
529
530 p54spi_power_on(priv);
531
532 ret = p54spi_upload_firmware(dev);
533 if (ret < 0) {
534 p54spi_power_off(priv);
535 goto out_unlock;
536 }
537
538 mutex_unlock(&priv->mutex);
539
540 timeout = msecs_to_jiffies(2000);
541 timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
542 timeout);
543 if (!timeout) {
544 dev_err(&priv->spi->dev, "firmware boot failed");
545 p54spi_power_off(priv);
546 ret = -1;
547 goto out;
548 }
549
550 if (mutex_lock_interruptible(&priv->mutex)) {
551 ret = -EINTR;
552 p54spi_power_off(priv);
553 goto out;
554 }
555
556 WARN_ON(priv->fw_state != FW_STATE_READY);
557
558out_unlock:
559 mutex_unlock(&priv->mutex);
560
561out:
562 return ret;
563}
564
565static void p54spi_op_stop(struct ieee80211_hw *dev)
566{
567 struct p54s_priv *priv = dev->priv;
568 unsigned long flags;
569
570 mutex_lock(&priv->mutex);
571 WARN_ON(priv->fw_state != FW_STATE_READY);
572
573 p54spi_power_off(priv);
574 spin_lock_irqsave(&priv->tx_lock, flags);
575 INIT_LIST_HEAD(&priv->tx_pending);
576 spin_unlock_irqrestore(&priv->tx_lock, flags);
577
578 priv->fw_state = FW_STATE_OFF;
579 mutex_unlock(&priv->mutex);
580
581 cancel_work_sync(&priv->work);
582}
583
584static int p54spi_probe(struct spi_device *spi)
585{
586 struct p54s_priv *priv = NULL;
587 struct ieee80211_hw *hw;
588 int ret = -EINVAL;
589
590 hw = p54_init_common(sizeof(*priv));
591 if (!hw) {
592 dev_err(&spi->dev, "could not alloc ieee80211_hw");
593 return -ENOMEM;
594 }
595
596 priv = hw->priv;
597 priv->hw = hw;
598 spi_set_drvdata(spi, priv);
599 priv->spi = spi;
600
601 spi->bits_per_word = 16;
602 spi->max_speed_hz = 24000000;
603
604 ret = spi_setup(spi);
605 if (ret < 0) {
606 dev_err(&priv->spi->dev, "spi_setup failed");
607 goto err_free;
608 }
609
610 ret = gpio_request(p54spi_gpio_power, "p54spi power");
611 if (ret < 0) {
612 dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
613 goto err_free;
614 }
615
616 ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
617 if (ret < 0) {
618 dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
619 goto err_free_gpio_power;
620 }
621
622 gpio_direction_output(p54spi_gpio_power, 0);
623 gpio_direction_input(p54spi_gpio_irq);
624
625 ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
626 p54spi_interrupt, 0, "p54spi",
627 priv->spi);
628 if (ret < 0) {
629 dev_err(&priv->spi->dev, "request_irq() failed");
630 goto err_free_gpio_irq;
631 }
632
633 irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);
634
635 disable_irq(gpio_to_irq(p54spi_gpio_irq));
636
637 INIT_WORK(&priv->work, p54spi_work);
638 init_completion(&priv->fw_comp);
639 INIT_LIST_HEAD(&priv->tx_pending);
640 mutex_init(&priv->mutex);
641 spin_lock_init(&priv->tx_lock);
642 SET_IEEE80211_DEV(hw, &spi->dev);
643 priv->common.open = p54spi_op_start;
644 priv->common.stop = p54spi_op_stop;
645 priv->common.tx = p54spi_op_tx;
646
647 ret = p54spi_request_firmware(hw);
648 if (ret < 0)
649 goto err_free_common;
650
651 ret = p54spi_request_eeprom(hw);
652 if (ret)
653 goto err_free_common;
654
655 ret = p54_register_common(hw, &priv->spi->dev);
656 if (ret)
657 goto err_free_common;
658
659 return 0;
660
661err_free_common:
662 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
663err_free_gpio_irq:
664 gpio_free(p54spi_gpio_irq);
665err_free_gpio_power:
666 gpio_free(p54spi_gpio_power);
667err_free:
668 p54_free_common(priv->hw);
669 return ret;
670}
671
672static int p54spi_remove(struct spi_device *spi)
673{
674 struct p54s_priv *priv = spi_get_drvdata(spi);
675
676 p54_unregister_common(priv->hw);
677
678 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
679
680 gpio_free(p54spi_gpio_power);
681 gpio_free(p54spi_gpio_irq);
682 release_firmware(priv->firmware);
683
684 mutex_destroy(&priv->mutex);
685
686 p54_free_common(priv->hw);
687
688 return 0;
689}
690
691
692static struct spi_driver p54spi_driver = {
693 .driver = {
694 .name = "p54spi",
695 },
696
697 .probe = p54spi_probe,
698 .remove = p54spi_remove,
699};
700
701module_spi_driver(p54spi_driver);
702
703MODULE_LICENSE("GPL");
704MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
705MODULE_ALIAS("spi:cx3110x");
706MODULE_ALIAS("spi:p54spi");
707MODULE_ALIAS("spi:stlc45xx");