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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs
4 *
5 * Copyright (C) 2010 Lantiq Deutschland
6 * Copyright (C) 2012 John Crispin <john@phrozen.org>
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8 *
9 * The VLAN and bridge model the GSWIP hardware uses does not directly
10 * matches the model DSA uses.
11 *
12 * The hardware has 64 possible table entries for bridges with one VLAN
13 * ID, one flow id and a list of ports for each bridge. All entries which
14 * match the same flow ID are combined in the mac learning table, they
15 * act as one global bridge.
16 * The hardware does not support VLAN filter on the port, but on the
17 * bridge, this driver converts the DSA model to the hardware.
18 *
19 * The CPU gets all the exception frames which do not match any forwarding
20 * rule and the CPU port is also added to all bridges. This makes it possible
21 * to handle all the special cases easily in software.
22 * At the initialization the driver allocates one bridge table entry for
23 * each switch port which is used when the port is used without an
24 * explicit bridge. This prevents the frames from being forwarded
25 * between all LAN ports by default.
26 */
27
28#include <linux/clk.h>
29#include <linux/delay.h>
30#include <linux/etherdevice.h>
31#include <linux/firmware.h>
32#include <linux/if_bridge.h>
33#include <linux/if_vlan.h>
34#include <linux/iopoll.h>
35#include <linux/mfd/syscon.h>
36#include <linux/module.h>
37#include <linux/of_mdio.h>
38#include <linux/of_net.h>
39#include <linux/of_platform.h>
40#include <linux/phy.h>
41#include <linux/phylink.h>
42#include <linux/platform_device.h>
43#include <linux/regmap.h>
44#include <linux/reset.h>
45#include <net/dsa.h>
46#include <dt-bindings/mips/lantiq_rcu_gphy.h>
47
48#include "lantiq_pce.h"
49
50/* GSWIP MDIO Registers */
51#define GSWIP_MDIO_GLOB 0x00
52#define GSWIP_MDIO_GLOB_ENABLE BIT(15)
53#define GSWIP_MDIO_CTRL 0x08
54#define GSWIP_MDIO_CTRL_BUSY BIT(12)
55#define GSWIP_MDIO_CTRL_RD BIT(11)
56#define GSWIP_MDIO_CTRL_WR BIT(10)
57#define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
58#define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
59#define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
60#define GSWIP_MDIO_READ 0x09
61#define GSWIP_MDIO_WRITE 0x0A
62#define GSWIP_MDIO_MDC_CFG0 0x0B
63#define GSWIP_MDIO_MDC_CFG1 0x0C
64#define GSWIP_MDIO_PHYp(p) (0x15 - (p))
65#define GSWIP_MDIO_PHY_LINK_MASK 0x6000
66#define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
67#define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
68#define GSWIP_MDIO_PHY_LINK_UP 0x2000
69#define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
70#define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
71#define GSWIP_MDIO_PHY_SPEED_M10 0x0000
72#define GSWIP_MDIO_PHY_SPEED_M100 0x0800
73#define GSWIP_MDIO_PHY_SPEED_G1 0x1000
74#define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
75#define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
76#define GSWIP_MDIO_PHY_FDUP_EN 0x0200
77#define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
78#define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
79#define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
80#define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
81#define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
82#define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
83#define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
84#define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
85#define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
86#define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
87#define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
88 GSWIP_MDIO_PHY_FCONRX_MASK | \
89 GSWIP_MDIO_PHY_FCONTX_MASK | \
90 GSWIP_MDIO_PHY_LINK_MASK | \
91 GSWIP_MDIO_PHY_SPEED_MASK | \
92 GSWIP_MDIO_PHY_FDUP_MASK)
93
94/* GSWIP MII Registers */
95#define GSWIP_MII_CFGp(p) (0x2 * (p))
96#define GSWIP_MII_CFG_RESET BIT(15)
97#define GSWIP_MII_CFG_EN BIT(14)
98#define GSWIP_MII_CFG_ISOLATE BIT(13)
99#define GSWIP_MII_CFG_LDCLKDIS BIT(12)
100#define GSWIP_MII_CFG_RGMII_IBS BIT(8)
101#define GSWIP_MII_CFG_RMII_CLK BIT(7)
102#define GSWIP_MII_CFG_MODE_MIIP 0x0
103#define GSWIP_MII_CFG_MODE_MIIM 0x1
104#define GSWIP_MII_CFG_MODE_RMIIP 0x2
105#define GSWIP_MII_CFG_MODE_RMIIM 0x3
106#define GSWIP_MII_CFG_MODE_RGMII 0x4
107#define GSWIP_MII_CFG_MODE_GMII 0x9
108#define GSWIP_MII_CFG_MODE_MASK 0xf
109#define GSWIP_MII_CFG_RATE_M2P5 0x00
110#define GSWIP_MII_CFG_RATE_M25 0x10
111#define GSWIP_MII_CFG_RATE_M125 0x20
112#define GSWIP_MII_CFG_RATE_M50 0x30
113#define GSWIP_MII_CFG_RATE_AUTO 0x40
114#define GSWIP_MII_CFG_RATE_MASK 0x70
115#define GSWIP_MII_PCDU0 0x01
116#define GSWIP_MII_PCDU1 0x03
117#define GSWIP_MII_PCDU5 0x05
118#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
119#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
120
121/* GSWIP Core Registers */
122#define GSWIP_SWRES 0x000
123#define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
124#define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
125#define GSWIP_VERSION 0x013
126#define GSWIP_VERSION_REV_SHIFT 0
127#define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
128#define GSWIP_VERSION_MOD_SHIFT 8
129#define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
130#define GSWIP_VERSION_2_0 0x100
131#define GSWIP_VERSION_2_1 0x021
132#define GSWIP_VERSION_2_2 0x122
133#define GSWIP_VERSION_2_2_ETC 0x022
134
135#define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
136#define GSWIP_BM_RAM_ADDR 0x044
137#define GSWIP_BM_RAM_CTRL 0x045
138#define GSWIP_BM_RAM_CTRL_BAS BIT(15)
139#define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
140#define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
141#define GSWIP_BM_QUEUE_GCTRL 0x04A
142#define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
143/* buffer management Port Configuration Register */
144#define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
145#define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
146#define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
147/* buffer management Port Control Register */
148#define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
149#define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
150#define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
151
152/* PCE */
153#define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
154#define GSWIP_PCE_TBL_MASK 0x448
155#define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
156#define GSWIP_PCE_TBL_ADDR 0x44E
157#define GSWIP_PCE_TBL_CTRL 0x44F
158#define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
159#define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
160#define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
161#define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
162#define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
163#define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
164#define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
165#define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
166#define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
167#define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
168#define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
169#define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
170#define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
171#define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
172#define GSWIP_PCE_GCTRL_0 0x456
173#define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
174#define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
175#define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
176#define GSWIP_PCE_GCTRL_1 0x457
177#define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
178#define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
179#define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
180#define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
181#define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
182#define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
183#define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
184#define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
185#define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
186#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
187#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
188#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
189#define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
190#define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
191#define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
192#define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
193#define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
194#define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
195#define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
196
197#define GSWIP_MAC_FLEN 0x8C5
198#define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
199#define GSWIP_MAC_CTRL_0_PADEN BIT(8)
200#define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
201#define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
202#define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
203#define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
204#define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
205#define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
206#define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
207#define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
208#define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
209#define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
210#define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
211#define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
212#define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
213#define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
214#define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
215#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
216#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */
217#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
218
219/* Ethernet Switch Fetch DMA Port Control Register */
220#define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
221#define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
222#define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
223#define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
224#define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
225#define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
226#define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
227#define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
228#define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
229
230/* Ethernet Switch Store DMA Port Control Register */
231#define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
232#define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
233#define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
234#define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */
235
236#define GSWIP_TABLE_ACTIVE_VLAN 0x01
237#define GSWIP_TABLE_VLAN_MAPPING 0x02
238#define GSWIP_TABLE_MAC_BRIDGE 0x0b
239#define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
240
241#define XRX200_GPHY_FW_ALIGN (16 * 1024)
242
243/* Maximum packet size supported by the switch. In theory this should be 10240,
244 * but long packets currently cause lock-ups with an MTU of over 2526. Medium
245 * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP
246 * over 2526), hence an MTU value of 2400 seems safe. This issue only affects
247 * packet reception. This is probably caused by the PPA engine, which is on the
248 * RX part of the device. Packet transmission works properly up to 10240.
249 */
250#define GSWIP_MAX_PACKET_LENGTH 2400
251
252struct gswip_hw_info {
253 int max_ports;
254 int cpu_port;
255 const struct dsa_switch_ops *ops;
256};
257
258struct xway_gphy_match_data {
259 char *fe_firmware_name;
260 char *ge_firmware_name;
261};
262
263struct gswip_gphy_fw {
264 struct clk *clk_gate;
265 struct reset_control *reset;
266 u32 fw_addr_offset;
267 char *fw_name;
268};
269
270struct gswip_vlan {
271 struct net_device *bridge;
272 u16 vid;
273 u8 fid;
274};
275
276struct gswip_priv {
277 __iomem void *gswip;
278 __iomem void *mdio;
279 __iomem void *mii;
280 const struct gswip_hw_info *hw_info;
281 const struct xway_gphy_match_data *gphy_fw_name_cfg;
282 struct dsa_switch *ds;
283 struct device *dev;
284 struct regmap *rcu_regmap;
285 struct gswip_vlan vlans[64];
286 int num_gphy_fw;
287 struct gswip_gphy_fw *gphy_fw;
288 u32 port_vlan_filter;
289 struct mutex pce_table_lock;
290};
291
292struct gswip_pce_table_entry {
293 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
294 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
295 u16 key[8];
296 u16 val[5];
297 u16 mask;
298 u8 gmap;
299 bool type;
300 bool valid;
301 bool key_mode;
302};
303
304struct gswip_rmon_cnt_desc {
305 unsigned int size;
306 unsigned int offset;
307 const char *name;
308};
309
310#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
311
312static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
313 /** Receive Packet Count (only packets that are accepted and not discarded). */
314 MIB_DESC(1, 0x1F, "RxGoodPkts"),
315 MIB_DESC(1, 0x23, "RxUnicastPkts"),
316 MIB_DESC(1, 0x22, "RxMulticastPkts"),
317 MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
318 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
319 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
320 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
321 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
322 MIB_DESC(1, 0x20, "RxGoodPausePkts"),
323 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
324 MIB_DESC(1, 0x12, "Rx64BytePkts"),
325 MIB_DESC(1, 0x13, "Rx127BytePkts"),
326 MIB_DESC(1, 0x14, "Rx255BytePkts"),
327 MIB_DESC(1, 0x15, "Rx511BytePkts"),
328 MIB_DESC(1, 0x16, "Rx1023BytePkts"),
329 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
330 MIB_DESC(1, 0x17, "RxMaxBytePkts"),
331 MIB_DESC(1, 0x18, "RxDroppedPkts"),
332 MIB_DESC(1, 0x19, "RxFilteredPkts"),
333 MIB_DESC(2, 0x24, "RxGoodBytes"),
334 MIB_DESC(2, 0x26, "RxBadBytes"),
335 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
336 MIB_DESC(1, 0x0C, "TxGoodPkts"),
337 MIB_DESC(1, 0x06, "TxUnicastPkts"),
338 MIB_DESC(1, 0x07, "TxMulticastPkts"),
339 MIB_DESC(1, 0x00, "Tx64BytePkts"),
340 MIB_DESC(1, 0x01, "Tx127BytePkts"),
341 MIB_DESC(1, 0x02, "Tx255BytePkts"),
342 MIB_DESC(1, 0x03, "Tx511BytePkts"),
343 MIB_DESC(1, 0x04, "Tx1023BytePkts"),
344 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
345 MIB_DESC(1, 0x05, "TxMaxBytePkts"),
346 MIB_DESC(1, 0x08, "TxSingleCollCount"),
347 MIB_DESC(1, 0x09, "TxMultCollCount"),
348 MIB_DESC(1, 0x0A, "TxLateCollCount"),
349 MIB_DESC(1, 0x0B, "TxExcessCollCount"),
350 MIB_DESC(1, 0x0D, "TxPauseCount"),
351 MIB_DESC(1, 0x10, "TxDroppedPkts"),
352 MIB_DESC(2, 0x0E, "TxGoodBytes"),
353};
354
355static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
356{
357 return __raw_readl(priv->gswip + (offset * 4));
358}
359
360static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
361{
362 __raw_writel(val, priv->gswip + (offset * 4));
363}
364
365static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
366 u32 offset)
367{
368 u32 val = gswip_switch_r(priv, offset);
369
370 val &= ~(clear);
371 val |= set;
372 gswip_switch_w(priv, val, offset);
373}
374
375static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
376 u32 cleared)
377{
378 u32 val;
379
380 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
381 (val & cleared) == 0, 20, 50000);
382}
383
384static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
385{
386 return __raw_readl(priv->mdio + (offset * 4));
387}
388
389static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
390{
391 __raw_writel(val, priv->mdio + (offset * 4));
392}
393
394static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
395 u32 offset)
396{
397 u32 val = gswip_mdio_r(priv, offset);
398
399 val &= ~(clear);
400 val |= set;
401 gswip_mdio_w(priv, val, offset);
402}
403
404static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
405{
406 return __raw_readl(priv->mii + (offset * 4));
407}
408
409static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
410{
411 __raw_writel(val, priv->mii + (offset * 4));
412}
413
414static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
415 u32 offset)
416{
417 u32 val = gswip_mii_r(priv, offset);
418
419 val &= ~(clear);
420 val |= set;
421 gswip_mii_w(priv, val, offset);
422}
423
424static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
425 int port)
426{
427 /* There's no MII_CFG register for the CPU port */
428 if (!dsa_is_cpu_port(priv->ds, port))
429 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
430}
431
432static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
433 int port)
434{
435 switch (port) {
436 case 0:
437 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
438 break;
439 case 1:
440 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
441 break;
442 case 5:
443 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
444 break;
445 }
446}
447
448static int gswip_mdio_poll(struct gswip_priv *priv)
449{
450 int cnt = 100;
451
452 while (likely(cnt--)) {
453 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
454
455 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
456 return 0;
457 usleep_range(20, 40);
458 }
459
460 return -ETIMEDOUT;
461}
462
463static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
464{
465 struct gswip_priv *priv = bus->priv;
466 int err;
467
468 err = gswip_mdio_poll(priv);
469 if (err) {
470 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
471 return err;
472 }
473
474 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
475 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
476 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
477 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
478 GSWIP_MDIO_CTRL);
479
480 return 0;
481}
482
483static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
484{
485 struct gswip_priv *priv = bus->priv;
486 int err;
487
488 err = gswip_mdio_poll(priv);
489 if (err) {
490 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
491 return err;
492 }
493
494 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
495 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
496 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
497 GSWIP_MDIO_CTRL);
498
499 err = gswip_mdio_poll(priv);
500 if (err) {
501 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
502 return err;
503 }
504
505 return gswip_mdio_r(priv, GSWIP_MDIO_READ);
506}
507
508static int gswip_mdio(struct gswip_priv *priv)
509{
510 struct device_node *mdio_np, *switch_np = priv->dev->of_node;
511 struct device *dev = priv->dev;
512 struct mii_bus *bus;
513 int err = 0;
514
515 mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio");
516 if (!of_device_is_available(mdio_np))
517 goto out_put_node;
518
519 bus = devm_mdiobus_alloc(dev);
520 if (!bus) {
521 err = -ENOMEM;
522 goto out_put_node;
523 }
524
525 bus->priv = priv;
526 bus->read = gswip_mdio_rd;
527 bus->write = gswip_mdio_wr;
528 bus->name = "lantiq,xrx200-mdio";
529 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
530 bus->parent = priv->dev;
531
532 err = devm_of_mdiobus_register(dev, bus, mdio_np);
533
534out_put_node:
535 of_node_put(mdio_np);
536
537 return err;
538}
539
540static int gswip_pce_table_entry_read(struct gswip_priv *priv,
541 struct gswip_pce_table_entry *tbl)
542{
543 int i;
544 int err;
545 u16 crtl;
546 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
547 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
548
549 mutex_lock(&priv->pce_table_lock);
550
551 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
552 GSWIP_PCE_TBL_CTRL_BAS);
553 if (err) {
554 mutex_unlock(&priv->pce_table_lock);
555 return err;
556 }
557
558 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
559 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
560 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
561 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
562 GSWIP_PCE_TBL_CTRL);
563
564 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
565 GSWIP_PCE_TBL_CTRL_BAS);
566 if (err) {
567 mutex_unlock(&priv->pce_table_lock);
568 return err;
569 }
570
571 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
572 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
573
574 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
575 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
576
577 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
578
579 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
580
581 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
582 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
583 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
584
585 mutex_unlock(&priv->pce_table_lock);
586
587 return 0;
588}
589
590static int gswip_pce_table_entry_write(struct gswip_priv *priv,
591 struct gswip_pce_table_entry *tbl)
592{
593 int i;
594 int err;
595 u16 crtl;
596 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
597 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
598
599 mutex_lock(&priv->pce_table_lock);
600
601 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
602 GSWIP_PCE_TBL_CTRL_BAS);
603 if (err) {
604 mutex_unlock(&priv->pce_table_lock);
605 return err;
606 }
607
608 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
609 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
610 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
611 tbl->table | addr_mode,
612 GSWIP_PCE_TBL_CTRL);
613
614 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
615 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
616
617 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
618 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
619
620 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
621 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
622 tbl->table | addr_mode,
623 GSWIP_PCE_TBL_CTRL);
624
625 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
626
627 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
628 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
629 GSWIP_PCE_TBL_CTRL_GMAP_MASK);
630 if (tbl->type)
631 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
632 if (tbl->valid)
633 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
634 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
635 crtl |= GSWIP_PCE_TBL_CTRL_BAS;
636 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
637
638 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
639 GSWIP_PCE_TBL_CTRL_BAS);
640
641 mutex_unlock(&priv->pce_table_lock);
642
643 return err;
644}
645
646/* Add the LAN port into a bridge with the CPU port by
647 * default. This prevents automatic forwarding of
648 * packages between the LAN ports when no explicit
649 * bridge is configured.
650 */
651static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
652{
653 struct gswip_pce_table_entry vlan_active = {0,};
654 struct gswip_pce_table_entry vlan_mapping = {0,};
655 unsigned int cpu_port = priv->hw_info->cpu_port;
656 unsigned int max_ports = priv->hw_info->max_ports;
657 int err;
658
659 if (port >= max_ports) {
660 dev_err(priv->dev, "single port for %i supported\n", port);
661 return -EIO;
662 }
663
664 vlan_active.index = port + 1;
665 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
666 vlan_active.key[0] = 0; /* vid */
667 vlan_active.val[0] = port + 1 /* fid */;
668 vlan_active.valid = add;
669 err = gswip_pce_table_entry_write(priv, &vlan_active);
670 if (err) {
671 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
672 return err;
673 }
674
675 if (!add)
676 return 0;
677
678 vlan_mapping.index = port + 1;
679 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
680 vlan_mapping.val[0] = 0 /* vid */;
681 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
682 vlan_mapping.val[2] = 0;
683 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
684 if (err) {
685 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
686 return err;
687 }
688
689 return 0;
690}
691
692static int gswip_port_enable(struct dsa_switch *ds, int port,
693 struct phy_device *phydev)
694{
695 struct gswip_priv *priv = ds->priv;
696 int err;
697
698 if (!dsa_is_user_port(ds, port))
699 return 0;
700
701 if (!dsa_is_cpu_port(ds, port)) {
702 err = gswip_add_single_port_br(priv, port, true);
703 if (err)
704 return err;
705 }
706
707 /* RMON Counter Enable for port */
708 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
709
710 /* enable port fetch/store dma & VLAN Modification */
711 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
712 GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
713 GSWIP_FDMA_PCTRLp(port));
714 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
715 GSWIP_SDMA_PCTRLp(port));
716
717 if (!dsa_is_cpu_port(ds, port)) {
718 u32 mdio_phy = 0;
719
720 if (phydev)
721 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
722
723 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
724 GSWIP_MDIO_PHYp(port));
725 }
726
727 return 0;
728}
729
730static void gswip_port_disable(struct dsa_switch *ds, int port)
731{
732 struct gswip_priv *priv = ds->priv;
733
734 if (!dsa_is_user_port(ds, port))
735 return;
736
737 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
738 GSWIP_FDMA_PCTRLp(port));
739 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
740 GSWIP_SDMA_PCTRLp(port));
741}
742
743static int gswip_pce_load_microcode(struct gswip_priv *priv)
744{
745 int i;
746 int err;
747
748 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
749 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
750 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
751 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
752
753 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
754 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
755 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
756 GSWIP_PCE_TBL_VAL(0));
757 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
758 GSWIP_PCE_TBL_VAL(1));
759 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
760 GSWIP_PCE_TBL_VAL(2));
761 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
762 GSWIP_PCE_TBL_VAL(3));
763
764 /* start the table access: */
765 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
766 GSWIP_PCE_TBL_CTRL);
767 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
768 GSWIP_PCE_TBL_CTRL_BAS);
769 if (err)
770 return err;
771 }
772
773 /* tell the switch that the microcode is loaded */
774 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
775 GSWIP_PCE_GCTRL_0);
776
777 return 0;
778}
779
780static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
781 bool vlan_filtering,
782 struct netlink_ext_ack *extack)
783{
784 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
785 struct gswip_priv *priv = ds->priv;
786
787 /* Do not allow changing the VLAN filtering options while in bridge */
788 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) {
789 NL_SET_ERR_MSG_MOD(extack,
790 "Dynamic toggling of vlan_filtering not supported");
791 return -EIO;
792 }
793
794 if (vlan_filtering) {
795 /* Use port based VLAN tag */
796 gswip_switch_mask(priv,
797 GSWIP_PCE_VCTRL_VSR,
798 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
799 GSWIP_PCE_VCTRL_VEMR,
800 GSWIP_PCE_VCTRL(port));
801 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
802 GSWIP_PCE_PCTRL_0p(port));
803 } else {
804 /* Use port based VLAN tag */
805 gswip_switch_mask(priv,
806 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
807 GSWIP_PCE_VCTRL_VEMR,
808 GSWIP_PCE_VCTRL_VSR,
809 GSWIP_PCE_VCTRL(port));
810 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
811 GSWIP_PCE_PCTRL_0p(port));
812 }
813
814 return 0;
815}
816
817static int gswip_setup(struct dsa_switch *ds)
818{
819 struct gswip_priv *priv = ds->priv;
820 unsigned int cpu_port = priv->hw_info->cpu_port;
821 int i;
822 int err;
823
824 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
825 usleep_range(5000, 10000);
826 gswip_switch_w(priv, 0, GSWIP_SWRES);
827
828 /* disable port fetch/store dma on all ports */
829 for (i = 0; i < priv->hw_info->max_ports; i++) {
830 gswip_port_disable(ds, i);
831 gswip_port_vlan_filtering(ds, i, false, NULL);
832 }
833
834 /* enable Switch */
835 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
836
837 err = gswip_pce_load_microcode(priv);
838 if (err) {
839 dev_err(priv->dev, "writing PCE microcode failed, %i", err);
840 return err;
841 }
842
843 /* Default unknown Broadcast/Multicast/Unicast port maps */
844 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
845 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
846 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
847
848 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
849 * interoperability problem with this auto polling mechanism because
850 * their status registers think that the link is in a different state
851 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
852 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
853 * auto polling state machine consider the link being negotiated with
854 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
855 * to the switch port being completely dead (RX and TX are both not
856 * working).
857 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
858 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
859 * it would work fine for a few minutes to hours and then stop, on
860 * other device it would no traffic could be sent or received at all.
861 * Testing shows that when PHY auto polling is disabled these problems
862 * go away.
863 */
864 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
865
866 /* Configure the MDIO Clock 2.5 MHz */
867 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
868
869 /* Disable the xMII interface and clear it's isolation bit */
870 for (i = 0; i < priv->hw_info->max_ports; i++)
871 gswip_mii_mask_cfg(priv,
872 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
873 0, i);
874
875 /* enable special tag insertion on cpu port */
876 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
877 GSWIP_FDMA_PCTRLp(cpu_port));
878
879 /* accept special tag in ingress direction */
880 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
881 GSWIP_PCE_PCTRL_0p(cpu_port));
882
883 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
884 GSWIP_BM_QUEUE_GCTRL);
885
886 /* VLAN aware Switching */
887 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
888
889 /* Flush MAC Table */
890 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
891
892 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
893 GSWIP_PCE_GCTRL_0_MTFL);
894 if (err) {
895 dev_err(priv->dev, "MAC flushing didn't finish\n");
896 return err;
897 }
898
899 ds->mtu_enforcement_ingress = true;
900
901 gswip_port_enable(ds, cpu_port, NULL);
902
903 ds->configure_vlan_while_not_filtering = false;
904
905 return 0;
906}
907
908static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
909 int port,
910 enum dsa_tag_protocol mp)
911{
912 return DSA_TAG_PROTO_GSWIP;
913}
914
915static int gswip_vlan_active_create(struct gswip_priv *priv,
916 struct net_device *bridge,
917 int fid, u16 vid)
918{
919 struct gswip_pce_table_entry vlan_active = {0,};
920 unsigned int max_ports = priv->hw_info->max_ports;
921 int idx = -1;
922 int err;
923 int i;
924
925 /* Look for a free slot */
926 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
927 if (!priv->vlans[i].bridge) {
928 idx = i;
929 break;
930 }
931 }
932
933 if (idx == -1)
934 return -ENOSPC;
935
936 if (fid == -1)
937 fid = idx;
938
939 vlan_active.index = idx;
940 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
941 vlan_active.key[0] = vid;
942 vlan_active.val[0] = fid;
943 vlan_active.valid = true;
944
945 err = gswip_pce_table_entry_write(priv, &vlan_active);
946 if (err) {
947 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
948 return err;
949 }
950
951 priv->vlans[idx].bridge = bridge;
952 priv->vlans[idx].vid = vid;
953 priv->vlans[idx].fid = fid;
954
955 return idx;
956}
957
958static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
959{
960 struct gswip_pce_table_entry vlan_active = {0,};
961 int err;
962
963 vlan_active.index = idx;
964 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
965 vlan_active.valid = false;
966 err = gswip_pce_table_entry_write(priv, &vlan_active);
967 if (err)
968 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
969 priv->vlans[idx].bridge = NULL;
970
971 return err;
972}
973
974static int gswip_vlan_add_unaware(struct gswip_priv *priv,
975 struct net_device *bridge, int port)
976{
977 struct gswip_pce_table_entry vlan_mapping = {0,};
978 unsigned int max_ports = priv->hw_info->max_ports;
979 unsigned int cpu_port = priv->hw_info->cpu_port;
980 bool active_vlan_created = false;
981 int idx = -1;
982 int i;
983 int err;
984
985 /* Check if there is already a page for this bridge */
986 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
987 if (priv->vlans[i].bridge == bridge) {
988 idx = i;
989 break;
990 }
991 }
992
993 /* If this bridge is not programmed yet, add a Active VLAN table
994 * entry in a free slot and prepare the VLAN mapping table entry.
995 */
996 if (idx == -1) {
997 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
998 if (idx < 0)
999 return idx;
1000 active_vlan_created = true;
1001
1002 vlan_mapping.index = idx;
1003 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1004 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1005 vlan_mapping.val[0] = 0;
1006 } else {
1007 /* Read the existing VLAN mapping entry from the switch */
1008 vlan_mapping.index = idx;
1009 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1010 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1011 if (err) {
1012 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1013 err);
1014 return err;
1015 }
1016 }
1017
1018 /* Update the VLAN mapping entry and write it to the switch */
1019 vlan_mapping.val[1] |= BIT(cpu_port);
1020 vlan_mapping.val[1] |= BIT(port);
1021 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1022 if (err) {
1023 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1024 /* In case an Active VLAN was creaetd delete it again */
1025 if (active_vlan_created)
1026 gswip_vlan_active_remove(priv, idx);
1027 return err;
1028 }
1029
1030 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1031 return 0;
1032}
1033
1034static int gswip_vlan_add_aware(struct gswip_priv *priv,
1035 struct net_device *bridge, int port,
1036 u16 vid, bool untagged,
1037 bool pvid)
1038{
1039 struct gswip_pce_table_entry vlan_mapping = {0,};
1040 unsigned int max_ports = priv->hw_info->max_ports;
1041 unsigned int cpu_port = priv->hw_info->cpu_port;
1042 bool active_vlan_created = false;
1043 int idx = -1;
1044 int fid = -1;
1045 int i;
1046 int err;
1047
1048 /* Check if there is already a page for this bridge */
1049 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1050 if (priv->vlans[i].bridge == bridge) {
1051 if (fid != -1 && fid != priv->vlans[i].fid)
1052 dev_err(priv->dev, "one bridge with multiple flow ids\n");
1053 fid = priv->vlans[i].fid;
1054 if (priv->vlans[i].vid == vid) {
1055 idx = i;
1056 break;
1057 }
1058 }
1059 }
1060
1061 /* If this bridge is not programmed yet, add a Active VLAN table
1062 * entry in a free slot and prepare the VLAN mapping table entry.
1063 */
1064 if (idx == -1) {
1065 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1066 if (idx < 0)
1067 return idx;
1068 active_vlan_created = true;
1069
1070 vlan_mapping.index = idx;
1071 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1072 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1073 vlan_mapping.val[0] = vid;
1074 } else {
1075 /* Read the existing VLAN mapping entry from the switch */
1076 vlan_mapping.index = idx;
1077 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1078 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1079 if (err) {
1080 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1081 err);
1082 return err;
1083 }
1084 }
1085
1086 vlan_mapping.val[0] = vid;
1087 /* Update the VLAN mapping entry and write it to the switch */
1088 vlan_mapping.val[1] |= BIT(cpu_port);
1089 vlan_mapping.val[2] |= BIT(cpu_port);
1090 vlan_mapping.val[1] |= BIT(port);
1091 if (untagged)
1092 vlan_mapping.val[2] &= ~BIT(port);
1093 else
1094 vlan_mapping.val[2] |= BIT(port);
1095 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1096 if (err) {
1097 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1098 /* In case an Active VLAN was creaetd delete it again */
1099 if (active_vlan_created)
1100 gswip_vlan_active_remove(priv, idx);
1101 return err;
1102 }
1103
1104 if (pvid)
1105 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1106
1107 return 0;
1108}
1109
1110static int gswip_vlan_remove(struct gswip_priv *priv,
1111 struct net_device *bridge, int port,
1112 u16 vid, bool pvid, bool vlan_aware)
1113{
1114 struct gswip_pce_table_entry vlan_mapping = {0,};
1115 unsigned int max_ports = priv->hw_info->max_ports;
1116 unsigned int cpu_port = priv->hw_info->cpu_port;
1117 int idx = -1;
1118 int i;
1119 int err;
1120
1121 /* Check if there is already a page for this bridge */
1122 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1123 if (priv->vlans[i].bridge == bridge &&
1124 (!vlan_aware || priv->vlans[i].vid == vid)) {
1125 idx = i;
1126 break;
1127 }
1128 }
1129
1130 if (idx == -1) {
1131 dev_err(priv->dev, "bridge to leave does not exists\n");
1132 return -ENOENT;
1133 }
1134
1135 vlan_mapping.index = idx;
1136 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1137 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1138 if (err) {
1139 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1140 return err;
1141 }
1142
1143 vlan_mapping.val[1] &= ~BIT(port);
1144 vlan_mapping.val[2] &= ~BIT(port);
1145 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1146 if (err) {
1147 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1148 return err;
1149 }
1150
1151 /* In case all ports are removed from the bridge, remove the VLAN */
1152 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1153 err = gswip_vlan_active_remove(priv, idx);
1154 if (err) {
1155 dev_err(priv->dev, "failed to write active VLAN: %d\n",
1156 err);
1157 return err;
1158 }
1159 }
1160
1161 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1162 if (pvid)
1163 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1164
1165 return 0;
1166}
1167
1168static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1169 struct dsa_bridge bridge,
1170 bool *tx_fwd_offload,
1171 struct netlink_ext_ack *extack)
1172{
1173 struct net_device *br = bridge.dev;
1174 struct gswip_priv *priv = ds->priv;
1175 int err;
1176
1177 /* When the bridge uses VLAN filtering we have to configure VLAN
1178 * specific bridges. No bridge is configured here.
1179 */
1180 if (!br_vlan_enabled(br)) {
1181 err = gswip_vlan_add_unaware(priv, br, port);
1182 if (err)
1183 return err;
1184 priv->port_vlan_filter &= ~BIT(port);
1185 } else {
1186 priv->port_vlan_filter |= BIT(port);
1187 }
1188 return gswip_add_single_port_br(priv, port, false);
1189}
1190
1191static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1192 struct dsa_bridge bridge)
1193{
1194 struct net_device *br = bridge.dev;
1195 struct gswip_priv *priv = ds->priv;
1196
1197 gswip_add_single_port_br(priv, port, true);
1198
1199 /* When the bridge uses VLAN filtering we have to configure VLAN
1200 * specific bridges. No bridge is configured here.
1201 */
1202 if (!br_vlan_enabled(br))
1203 gswip_vlan_remove(priv, br, port, 0, true, false);
1204}
1205
1206static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1207 const struct switchdev_obj_port_vlan *vlan,
1208 struct netlink_ext_ack *extack)
1209{
1210 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1211 struct gswip_priv *priv = ds->priv;
1212 unsigned int max_ports = priv->hw_info->max_ports;
1213 int pos = max_ports;
1214 int i, idx = -1;
1215
1216 /* We only support VLAN filtering on bridges */
1217 if (!dsa_is_cpu_port(ds, port) && !bridge)
1218 return -EOPNOTSUPP;
1219
1220 /* Check if there is already a page for this VLAN */
1221 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1222 if (priv->vlans[i].bridge == bridge &&
1223 priv->vlans[i].vid == vlan->vid) {
1224 idx = i;
1225 break;
1226 }
1227 }
1228
1229 /* If this VLAN is not programmed yet, we have to reserve
1230 * one entry in the VLAN table. Make sure we start at the
1231 * next position round.
1232 */
1233 if (idx == -1) {
1234 /* Look for a free slot */
1235 for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1236 if (!priv->vlans[pos].bridge) {
1237 idx = pos;
1238 pos++;
1239 break;
1240 }
1241 }
1242
1243 if (idx == -1) {
1244 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table");
1245 return -ENOSPC;
1246 }
1247 }
1248
1249 return 0;
1250}
1251
1252static int gswip_port_vlan_add(struct dsa_switch *ds, int port,
1253 const struct switchdev_obj_port_vlan *vlan,
1254 struct netlink_ext_ack *extack)
1255{
1256 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1257 struct gswip_priv *priv = ds->priv;
1258 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1259 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1260 int err;
1261
1262 err = gswip_port_vlan_prepare(ds, port, vlan, extack);
1263 if (err)
1264 return err;
1265
1266 /* We have to receive all packets on the CPU port and should not
1267 * do any VLAN filtering here. This is also called with bridge
1268 * NULL and then we do not know for which bridge to configure
1269 * this.
1270 */
1271 if (dsa_is_cpu_port(ds, port))
1272 return 0;
1273
1274 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid,
1275 untagged, pvid);
1276}
1277
1278static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1279 const struct switchdev_obj_port_vlan *vlan)
1280{
1281 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1282 struct gswip_priv *priv = ds->priv;
1283 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1284
1285 /* We have to receive all packets on the CPU port and should not
1286 * do any VLAN filtering here. This is also called with bridge
1287 * NULL and then we do not know for which bridge to configure
1288 * this.
1289 */
1290 if (dsa_is_cpu_port(ds, port))
1291 return 0;
1292
1293 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true);
1294}
1295
1296static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1297{
1298 struct gswip_priv *priv = ds->priv;
1299 struct gswip_pce_table_entry mac_bridge = {0,};
1300 int i;
1301 int err;
1302
1303 for (i = 0; i < 2048; i++) {
1304 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1305 mac_bridge.index = i;
1306
1307 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1308 if (err) {
1309 dev_err(priv->dev, "failed to read mac bridge: %d\n",
1310 err);
1311 return;
1312 }
1313
1314 if (!mac_bridge.valid)
1315 continue;
1316
1317 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
1318 continue;
1319
1320 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
1321 continue;
1322
1323 mac_bridge.valid = false;
1324 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1325 if (err) {
1326 dev_err(priv->dev, "failed to write mac bridge: %d\n",
1327 err);
1328 return;
1329 }
1330 }
1331}
1332
1333static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1334{
1335 struct gswip_priv *priv = ds->priv;
1336 u32 stp_state;
1337
1338 switch (state) {
1339 case BR_STATE_DISABLED:
1340 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1341 GSWIP_SDMA_PCTRLp(port));
1342 return;
1343 case BR_STATE_BLOCKING:
1344 case BR_STATE_LISTENING:
1345 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1346 break;
1347 case BR_STATE_LEARNING:
1348 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1349 break;
1350 case BR_STATE_FORWARDING:
1351 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1352 break;
1353 default:
1354 dev_err(priv->dev, "invalid STP state: %d\n", state);
1355 return;
1356 }
1357
1358 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1359 GSWIP_SDMA_PCTRLp(port));
1360 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1361 GSWIP_PCE_PCTRL_0p(port));
1362}
1363
1364static int gswip_port_fdb(struct dsa_switch *ds, int port,
1365 const unsigned char *addr, u16 vid, bool add)
1366{
1367 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1368 struct gswip_priv *priv = ds->priv;
1369 struct gswip_pce_table_entry mac_bridge = {0,};
1370 unsigned int max_ports = priv->hw_info->max_ports;
1371 int fid = -1;
1372 int i;
1373 int err;
1374
1375 if (!bridge)
1376 return -EINVAL;
1377
1378 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1379 if (priv->vlans[i].bridge == bridge) {
1380 fid = priv->vlans[i].fid;
1381 break;
1382 }
1383 }
1384
1385 if (fid == -1) {
1386 dev_err(priv->dev, "Port not part of a bridge\n");
1387 return -EINVAL;
1388 }
1389
1390 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1391 mac_bridge.key_mode = true;
1392 mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1393 mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1394 mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1395 mac_bridge.key[3] = fid;
1396 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1397 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
1398 mac_bridge.valid = add;
1399
1400 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1401 if (err)
1402 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1403
1404 return err;
1405}
1406
1407static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1408 const unsigned char *addr, u16 vid,
1409 struct dsa_db db)
1410{
1411 return gswip_port_fdb(ds, port, addr, vid, true);
1412}
1413
1414static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1415 const unsigned char *addr, u16 vid,
1416 struct dsa_db db)
1417{
1418 return gswip_port_fdb(ds, port, addr, vid, false);
1419}
1420
1421static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1422 dsa_fdb_dump_cb_t *cb, void *data)
1423{
1424 struct gswip_priv *priv = ds->priv;
1425 struct gswip_pce_table_entry mac_bridge = {0,};
1426 unsigned char addr[6];
1427 int i;
1428 int err;
1429
1430 for (i = 0; i < 2048; i++) {
1431 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1432 mac_bridge.index = i;
1433
1434 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1435 if (err) {
1436 dev_err(priv->dev,
1437 "failed to read mac bridge entry %d: %d\n",
1438 i, err);
1439 return err;
1440 }
1441
1442 if (!mac_bridge.valid)
1443 continue;
1444
1445 addr[5] = mac_bridge.key[0] & 0xff;
1446 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1447 addr[3] = mac_bridge.key[1] & 0xff;
1448 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1449 addr[1] = mac_bridge.key[2] & 0xff;
1450 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1451 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
1452 if (mac_bridge.val[0] & BIT(port)) {
1453 err = cb(addr, 0, true, data);
1454 if (err)
1455 return err;
1456 }
1457 } else {
1458 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
1459 err = cb(addr, 0, false, data);
1460 if (err)
1461 return err;
1462 }
1463 }
1464 }
1465 return 0;
1466}
1467
1468static int gswip_port_max_mtu(struct dsa_switch *ds, int port)
1469{
1470 /* Includes 8 bytes for special header. */
1471 return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN;
1472}
1473
1474static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1475{
1476 struct gswip_priv *priv = ds->priv;
1477 int cpu_port = priv->hw_info->cpu_port;
1478
1479 /* CPU port always has maximum mtu of user ports, so use it to set
1480 * switch frame size, including 8 byte special header.
1481 */
1482 if (port == cpu_port) {
1483 new_mtu += 8;
1484 gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
1485 GSWIP_MAC_FLEN);
1486 }
1487
1488 /* Enable MLEN for ports with non-standard MTUs, including the special
1489 * header on the CPU port added above.
1490 */
1491 if (new_mtu != ETH_DATA_LEN)
1492 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
1493 GSWIP_MAC_CTRL_2p(port));
1494 else
1495 gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0,
1496 GSWIP_MAC_CTRL_2p(port));
1497
1498 return 0;
1499}
1500
1501static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port,
1502 struct phylink_config *config)
1503{
1504 switch (port) {
1505 case 0:
1506 case 1:
1507 phy_interface_set_rgmii(config->supported_interfaces);
1508 __set_bit(PHY_INTERFACE_MODE_MII,
1509 config->supported_interfaces);
1510 __set_bit(PHY_INTERFACE_MODE_REVMII,
1511 config->supported_interfaces);
1512 __set_bit(PHY_INTERFACE_MODE_RMII,
1513 config->supported_interfaces);
1514 break;
1515
1516 case 2:
1517 case 3:
1518 case 4:
1519 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1520 config->supported_interfaces);
1521 break;
1522
1523 case 5:
1524 phy_interface_set_rgmii(config->supported_interfaces);
1525 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1526 config->supported_interfaces);
1527 break;
1528 }
1529
1530 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1531 MAC_10 | MAC_100 | MAC_1000;
1532}
1533
1534static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port,
1535 struct phylink_config *config)
1536{
1537 switch (port) {
1538 case 0:
1539 phy_interface_set_rgmii(config->supported_interfaces);
1540 __set_bit(PHY_INTERFACE_MODE_GMII,
1541 config->supported_interfaces);
1542 __set_bit(PHY_INTERFACE_MODE_RMII,
1543 config->supported_interfaces);
1544 break;
1545
1546 case 1:
1547 case 2:
1548 case 3:
1549 case 4:
1550 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1551 config->supported_interfaces);
1552 break;
1553
1554 case 5:
1555 phy_interface_set_rgmii(config->supported_interfaces);
1556 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1557 config->supported_interfaces);
1558 __set_bit(PHY_INTERFACE_MODE_RMII,
1559 config->supported_interfaces);
1560 break;
1561 }
1562
1563 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1564 MAC_10 | MAC_100 | MAC_1000;
1565}
1566
1567static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
1568{
1569 u32 mdio_phy;
1570
1571 if (link)
1572 mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
1573 else
1574 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
1575
1576 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,
1577 GSWIP_MDIO_PHYp(port));
1578}
1579
1580static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
1581 phy_interface_t interface)
1582{
1583 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
1584
1585 switch (speed) {
1586 case SPEED_10:
1587 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
1588
1589 if (interface == PHY_INTERFACE_MODE_RMII)
1590 mii_cfg = GSWIP_MII_CFG_RATE_M50;
1591 else
1592 mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
1593
1594 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1595 break;
1596
1597 case SPEED_100:
1598 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
1599
1600 if (interface == PHY_INTERFACE_MODE_RMII)
1601 mii_cfg = GSWIP_MII_CFG_RATE_M50;
1602 else
1603 mii_cfg = GSWIP_MII_CFG_RATE_M25;
1604
1605 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1606 break;
1607
1608 case SPEED_1000:
1609 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
1610
1611 mii_cfg = GSWIP_MII_CFG_RATE_M125;
1612
1613 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
1614 break;
1615 }
1616
1617 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,
1618 GSWIP_MDIO_PHYp(port));
1619 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
1620 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,
1621 GSWIP_MAC_CTRL_0p(port));
1622}
1623
1624static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
1625{
1626 u32 mac_ctrl_0, mdio_phy;
1627
1628 if (duplex == DUPLEX_FULL) {
1629 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
1630 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
1631 } else {
1632 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
1633 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
1634 }
1635
1636 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,
1637 GSWIP_MAC_CTRL_0p(port));
1638 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,
1639 GSWIP_MDIO_PHYp(port));
1640}
1641
1642static void gswip_port_set_pause(struct gswip_priv *priv, int port,
1643 bool tx_pause, bool rx_pause)
1644{
1645 u32 mac_ctrl_0, mdio_phy;
1646
1647 if (tx_pause && rx_pause) {
1648 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
1649 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1650 GSWIP_MDIO_PHY_FCONRX_EN;
1651 } else if (tx_pause) {
1652 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
1653 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1654 GSWIP_MDIO_PHY_FCONRX_DIS;
1655 } else if (rx_pause) {
1656 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
1657 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1658 GSWIP_MDIO_PHY_FCONRX_EN;
1659 } else {
1660 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
1661 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1662 GSWIP_MDIO_PHY_FCONRX_DIS;
1663 }
1664
1665 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,
1666 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));
1667 gswip_mdio_mask(priv,
1668 GSWIP_MDIO_PHY_FCONTX_MASK |
1669 GSWIP_MDIO_PHY_FCONRX_MASK,
1670 mdio_phy, GSWIP_MDIO_PHYp(port));
1671}
1672
1673static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
1674 unsigned int mode,
1675 const struct phylink_link_state *state)
1676{
1677 struct gswip_priv *priv = ds->priv;
1678 u32 miicfg = 0;
1679
1680 miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1681
1682 switch (state->interface) {
1683 case PHY_INTERFACE_MODE_MII:
1684 case PHY_INTERFACE_MODE_INTERNAL:
1685 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1686 break;
1687 case PHY_INTERFACE_MODE_REVMII:
1688 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1689 break;
1690 case PHY_INTERFACE_MODE_RMII:
1691 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1692 break;
1693 case PHY_INTERFACE_MODE_RGMII:
1694 case PHY_INTERFACE_MODE_RGMII_ID:
1695 case PHY_INTERFACE_MODE_RGMII_RXID:
1696 case PHY_INTERFACE_MODE_RGMII_TXID:
1697 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1698 break;
1699 case PHY_INTERFACE_MODE_GMII:
1700 miicfg |= GSWIP_MII_CFG_MODE_GMII;
1701 break;
1702 default:
1703 dev_err(ds->dev,
1704 "Unsupported interface: %d\n", state->interface);
1705 return;
1706 }
1707
1708 gswip_mii_mask_cfg(priv,
1709 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
1710 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
1711 miicfg, port);
1712
1713 switch (state->interface) {
1714 case PHY_INTERFACE_MODE_RGMII_ID:
1715 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1716 GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1717 break;
1718 case PHY_INTERFACE_MODE_RGMII_RXID:
1719 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1720 break;
1721 case PHY_INTERFACE_MODE_RGMII_TXID:
1722 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1723 break;
1724 default:
1725 break;
1726 }
1727}
1728
1729static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
1730 unsigned int mode,
1731 phy_interface_t interface)
1732{
1733 struct gswip_priv *priv = ds->priv;
1734
1735 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1736
1737 if (!dsa_is_cpu_port(ds, port))
1738 gswip_port_set_link(priv, port, false);
1739}
1740
1741static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
1742 unsigned int mode,
1743 phy_interface_t interface,
1744 struct phy_device *phydev,
1745 int speed, int duplex,
1746 bool tx_pause, bool rx_pause)
1747{
1748 struct gswip_priv *priv = ds->priv;
1749
1750 if (!dsa_is_cpu_port(ds, port)) {
1751 gswip_port_set_link(priv, port, true);
1752 gswip_port_set_speed(priv, port, speed, interface);
1753 gswip_port_set_duplex(priv, port, duplex);
1754 gswip_port_set_pause(priv, port, tx_pause, rx_pause);
1755 }
1756
1757 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1758}
1759
1760static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1761 uint8_t *data)
1762{
1763 int i;
1764
1765 if (stringset != ETH_SS_STATS)
1766 return;
1767
1768 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1769 ethtool_puts(&data, gswip_rmon_cnt[i].name);
1770}
1771
1772static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1773 u32 index)
1774{
1775 u32 result;
1776 int err;
1777
1778 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1779 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1780 GSWIP_BM_RAM_CTRL_OPMOD,
1781 table | GSWIP_BM_RAM_CTRL_BAS,
1782 GSWIP_BM_RAM_CTRL);
1783
1784 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1785 GSWIP_BM_RAM_CTRL_BAS);
1786 if (err) {
1787 dev_err(priv->dev, "timeout while reading table: %u, index: %u",
1788 table, index);
1789 return 0;
1790 }
1791
1792 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1793 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1794
1795 return result;
1796}
1797
1798static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1799 uint64_t *data)
1800{
1801 struct gswip_priv *priv = ds->priv;
1802 const struct gswip_rmon_cnt_desc *rmon_cnt;
1803 int i;
1804 u64 high;
1805
1806 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1807 rmon_cnt = &gswip_rmon_cnt[i];
1808
1809 data[i] = gswip_bcm_ram_entry_read(priv, port,
1810 rmon_cnt->offset);
1811 if (rmon_cnt->size == 2) {
1812 high = gswip_bcm_ram_entry_read(priv, port,
1813 rmon_cnt->offset + 1);
1814 data[i] |= high << 32;
1815 }
1816 }
1817}
1818
1819static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1820{
1821 if (sset != ETH_SS_STATS)
1822 return 0;
1823
1824 return ARRAY_SIZE(gswip_rmon_cnt);
1825}
1826
1827static const struct dsa_switch_ops gswip_xrx200_switch_ops = {
1828 .get_tag_protocol = gswip_get_tag_protocol,
1829 .setup = gswip_setup,
1830 .port_enable = gswip_port_enable,
1831 .port_disable = gswip_port_disable,
1832 .port_bridge_join = gswip_port_bridge_join,
1833 .port_bridge_leave = gswip_port_bridge_leave,
1834 .port_fast_age = gswip_port_fast_age,
1835 .port_vlan_filtering = gswip_port_vlan_filtering,
1836 .port_vlan_add = gswip_port_vlan_add,
1837 .port_vlan_del = gswip_port_vlan_del,
1838 .port_stp_state_set = gswip_port_stp_state_set,
1839 .port_fdb_add = gswip_port_fdb_add,
1840 .port_fdb_del = gswip_port_fdb_del,
1841 .port_fdb_dump = gswip_port_fdb_dump,
1842 .port_change_mtu = gswip_port_change_mtu,
1843 .port_max_mtu = gswip_port_max_mtu,
1844 .phylink_get_caps = gswip_xrx200_phylink_get_caps,
1845 .phylink_mac_config = gswip_phylink_mac_config,
1846 .phylink_mac_link_down = gswip_phylink_mac_link_down,
1847 .phylink_mac_link_up = gswip_phylink_mac_link_up,
1848 .get_strings = gswip_get_strings,
1849 .get_ethtool_stats = gswip_get_ethtool_stats,
1850 .get_sset_count = gswip_get_sset_count,
1851};
1852
1853static const struct dsa_switch_ops gswip_xrx300_switch_ops = {
1854 .get_tag_protocol = gswip_get_tag_protocol,
1855 .setup = gswip_setup,
1856 .port_enable = gswip_port_enable,
1857 .port_disable = gswip_port_disable,
1858 .port_bridge_join = gswip_port_bridge_join,
1859 .port_bridge_leave = gswip_port_bridge_leave,
1860 .port_fast_age = gswip_port_fast_age,
1861 .port_vlan_filtering = gswip_port_vlan_filtering,
1862 .port_vlan_add = gswip_port_vlan_add,
1863 .port_vlan_del = gswip_port_vlan_del,
1864 .port_stp_state_set = gswip_port_stp_state_set,
1865 .port_fdb_add = gswip_port_fdb_add,
1866 .port_fdb_del = gswip_port_fdb_del,
1867 .port_fdb_dump = gswip_port_fdb_dump,
1868 .port_change_mtu = gswip_port_change_mtu,
1869 .port_max_mtu = gswip_port_max_mtu,
1870 .phylink_get_caps = gswip_xrx300_phylink_get_caps,
1871 .phylink_mac_config = gswip_phylink_mac_config,
1872 .phylink_mac_link_down = gswip_phylink_mac_link_down,
1873 .phylink_mac_link_up = gswip_phylink_mac_link_up,
1874 .get_strings = gswip_get_strings,
1875 .get_ethtool_stats = gswip_get_ethtool_stats,
1876 .get_sset_count = gswip_get_sset_count,
1877};
1878
1879static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1880 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
1881 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
1882};
1883
1884static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1885 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
1886 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
1887};
1888
1889static const struct xway_gphy_match_data xrx300_gphy_data = {
1890 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
1891 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
1892};
1893
1894static const struct of_device_id xway_gphy_match[] __maybe_unused = {
1895 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1896 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1897 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1898 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1899 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1900 {},
1901};
1902
1903static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1904{
1905 struct device *dev = priv->dev;
1906 const struct firmware *fw;
1907 void *fw_addr;
1908 dma_addr_t dma_addr;
1909 dma_addr_t dev_addr;
1910 size_t size;
1911 int ret;
1912
1913 ret = clk_prepare_enable(gphy_fw->clk_gate);
1914 if (ret)
1915 return ret;
1916
1917 reset_control_assert(gphy_fw->reset);
1918
1919 /* The vendor BSP uses a 200ms delay after asserting the reset line.
1920 * Without this some users are observing that the PHY is not coming up
1921 * on the MDIO bus.
1922 */
1923 msleep(200);
1924
1925 ret = request_firmware(&fw, gphy_fw->fw_name, dev);
1926 if (ret) {
1927 dev_err(dev, "failed to load firmware: %s, error: %i\n",
1928 gphy_fw->fw_name, ret);
1929 return ret;
1930 }
1931
1932 /* GPHY cores need the firmware code in a persistent and contiguous
1933 * memory area with a 16 kB boundary aligned start address.
1934 */
1935 size = fw->size + XRX200_GPHY_FW_ALIGN;
1936
1937 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1938 if (fw_addr) {
1939 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1940 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1941 memcpy(fw_addr, fw->data, fw->size);
1942 } else {
1943 dev_err(dev, "failed to alloc firmware memory\n");
1944 release_firmware(fw);
1945 return -ENOMEM;
1946 }
1947
1948 release_firmware(fw);
1949
1950 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1951 if (ret)
1952 return ret;
1953
1954 reset_control_deassert(gphy_fw->reset);
1955
1956 return ret;
1957}
1958
1959static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1960 struct gswip_gphy_fw *gphy_fw,
1961 struct device_node *gphy_fw_np, int i)
1962{
1963 struct device *dev = priv->dev;
1964 u32 gphy_mode;
1965 int ret;
1966 char gphyname[10];
1967
1968 snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1969
1970 gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1971 if (IS_ERR(gphy_fw->clk_gate)) {
1972 dev_err(dev, "Failed to lookup gate clock\n");
1973 return PTR_ERR(gphy_fw->clk_gate);
1974 }
1975
1976 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1977 if (ret)
1978 return ret;
1979
1980 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1981 /* Default to GE mode */
1982 if (ret)
1983 gphy_mode = GPHY_MODE_GE;
1984
1985 switch (gphy_mode) {
1986 case GPHY_MODE_FE:
1987 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1988 break;
1989 case GPHY_MODE_GE:
1990 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1991 break;
1992 default:
1993 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
1994 return -EINVAL;
1995 }
1996
1997 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
1998 if (IS_ERR(gphy_fw->reset))
1999 return dev_err_probe(dev, PTR_ERR(gphy_fw->reset),
2000 "Failed to lookup gphy reset\n");
2001
2002 return gswip_gphy_fw_load(priv, gphy_fw);
2003}
2004
2005static void gswip_gphy_fw_remove(struct gswip_priv *priv,
2006 struct gswip_gphy_fw *gphy_fw)
2007{
2008 int ret;
2009
2010 /* check if the device was fully probed */
2011 if (!gphy_fw->fw_name)
2012 return;
2013
2014 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
2015 if (ret)
2016 dev_err(priv->dev, "can not reset GPHY FW pointer");
2017
2018 clk_disable_unprepare(gphy_fw->clk_gate);
2019
2020 reset_control_put(gphy_fw->reset);
2021}
2022
2023static int gswip_gphy_fw_list(struct gswip_priv *priv,
2024 struct device_node *gphy_fw_list_np, u32 version)
2025{
2026 struct device *dev = priv->dev;
2027 struct device_node *gphy_fw_np;
2028 const struct of_device_id *match;
2029 int err;
2030 int i = 0;
2031
2032 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
2033 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
2034 * needs a different GPHY firmware.
2035 */
2036 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
2037 switch (version) {
2038 case GSWIP_VERSION_2_0:
2039 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
2040 break;
2041 case GSWIP_VERSION_2_1:
2042 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
2043 break;
2044 default:
2045 dev_err(dev, "unknown GSWIP version: 0x%x", version);
2046 return -ENOENT;
2047 }
2048 }
2049
2050 match = of_match_node(xway_gphy_match, gphy_fw_list_np);
2051 if (match && match->data)
2052 priv->gphy_fw_name_cfg = match->data;
2053
2054 if (!priv->gphy_fw_name_cfg) {
2055 dev_err(dev, "GPHY compatible type not supported");
2056 return -ENOENT;
2057 }
2058
2059 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
2060 if (!priv->num_gphy_fw)
2061 return -ENOENT;
2062
2063 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
2064 "lantiq,rcu");
2065 if (IS_ERR(priv->rcu_regmap))
2066 return PTR_ERR(priv->rcu_regmap);
2067
2068 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
2069 sizeof(*priv->gphy_fw),
2070 GFP_KERNEL | __GFP_ZERO);
2071 if (!priv->gphy_fw)
2072 return -ENOMEM;
2073
2074 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
2075 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
2076 gphy_fw_np, i);
2077 if (err) {
2078 of_node_put(gphy_fw_np);
2079 goto remove_gphy;
2080 }
2081 i++;
2082 }
2083
2084 /* The standalone PHY11G requires 300ms to be fully
2085 * initialized and ready for any MDIO communication after being
2086 * taken out of reset. For the SoC-internal GPHY variant there
2087 * is no (known) documentation for the minimum time after a
2088 * reset. Use the same value as for the standalone variant as
2089 * some users have reported internal PHYs not being detected
2090 * without any delay.
2091 */
2092 msleep(300);
2093
2094 return 0;
2095
2096remove_gphy:
2097 for (i = 0; i < priv->num_gphy_fw; i++)
2098 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2099 return err;
2100}
2101
2102static int gswip_probe(struct platform_device *pdev)
2103{
2104 struct device_node *np, *gphy_fw_np;
2105 struct device *dev = &pdev->dev;
2106 struct gswip_priv *priv;
2107 int err;
2108 int i;
2109 u32 version;
2110
2111 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2112 if (!priv)
2113 return -ENOMEM;
2114
2115 priv->gswip = devm_platform_ioremap_resource(pdev, 0);
2116 if (IS_ERR(priv->gswip))
2117 return PTR_ERR(priv->gswip);
2118
2119 priv->mdio = devm_platform_ioremap_resource(pdev, 1);
2120 if (IS_ERR(priv->mdio))
2121 return PTR_ERR(priv->mdio);
2122
2123 priv->mii = devm_platform_ioremap_resource(pdev, 2);
2124 if (IS_ERR(priv->mii))
2125 return PTR_ERR(priv->mii);
2126
2127 priv->hw_info = of_device_get_match_data(dev);
2128 if (!priv->hw_info)
2129 return -EINVAL;
2130
2131 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
2132 if (!priv->ds)
2133 return -ENOMEM;
2134
2135 priv->ds->dev = dev;
2136 priv->ds->num_ports = priv->hw_info->max_ports;
2137 priv->ds->priv = priv;
2138 priv->ds->ops = priv->hw_info->ops;
2139 priv->dev = dev;
2140 mutex_init(&priv->pce_table_lock);
2141 version = gswip_switch_r(priv, GSWIP_VERSION);
2142
2143 np = dev->of_node;
2144 switch (version) {
2145 case GSWIP_VERSION_2_0:
2146 case GSWIP_VERSION_2_1:
2147 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip"))
2148 return -EINVAL;
2149 break;
2150 case GSWIP_VERSION_2_2:
2151 case GSWIP_VERSION_2_2_ETC:
2152 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") &&
2153 !of_device_is_compatible(np, "lantiq,xrx330-gswip"))
2154 return -EINVAL;
2155 break;
2156 default:
2157 dev_err(dev, "unknown GSWIP version: 0x%x", version);
2158 return -ENOENT;
2159 }
2160
2161 /* bring up the mdio bus */
2162 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
2163 if (gphy_fw_np) {
2164 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
2165 of_node_put(gphy_fw_np);
2166 if (err) {
2167 dev_err(dev, "gphy fw probe failed\n");
2168 return err;
2169 }
2170 }
2171
2172 /* bring up the mdio bus */
2173 err = gswip_mdio(priv);
2174 if (err) {
2175 dev_err(dev, "mdio probe failed\n");
2176 goto gphy_fw_remove;
2177 }
2178
2179 err = dsa_register_switch(priv->ds);
2180 if (err) {
2181 dev_err(dev, "dsa switch register failed: %i\n", err);
2182 goto gphy_fw_remove;
2183 }
2184 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
2185 dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
2186 priv->hw_info->cpu_port);
2187 err = -EINVAL;
2188 goto disable_switch;
2189 }
2190
2191 platform_set_drvdata(pdev, priv);
2192
2193 dev_info(dev, "probed GSWIP version %lx mod %lx\n",
2194 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
2195 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
2196 return 0;
2197
2198disable_switch:
2199 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2200 dsa_unregister_switch(priv->ds);
2201gphy_fw_remove:
2202 for (i = 0; i < priv->num_gphy_fw; i++)
2203 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2204 return err;
2205}
2206
2207static void gswip_remove(struct platform_device *pdev)
2208{
2209 struct gswip_priv *priv = platform_get_drvdata(pdev);
2210 int i;
2211
2212 if (!priv)
2213 return;
2214
2215 /* disable the switch */
2216 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2217
2218 dsa_unregister_switch(priv->ds);
2219
2220 for (i = 0; i < priv->num_gphy_fw; i++)
2221 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2222}
2223
2224static void gswip_shutdown(struct platform_device *pdev)
2225{
2226 struct gswip_priv *priv = platform_get_drvdata(pdev);
2227
2228 if (!priv)
2229 return;
2230
2231 dsa_switch_shutdown(priv->ds);
2232
2233 platform_set_drvdata(pdev, NULL);
2234}
2235
2236static const struct gswip_hw_info gswip_xrx200 = {
2237 .max_ports = 7,
2238 .cpu_port = 6,
2239 .ops = &gswip_xrx200_switch_ops,
2240};
2241
2242static const struct gswip_hw_info gswip_xrx300 = {
2243 .max_ports = 7,
2244 .cpu_port = 6,
2245 .ops = &gswip_xrx300_switch_ops,
2246};
2247
2248static const struct of_device_id gswip_of_match[] = {
2249 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2250 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 },
2251 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 },
2252 {},
2253};
2254MODULE_DEVICE_TABLE(of, gswip_of_match);
2255
2256static struct platform_driver gswip_driver = {
2257 .probe = gswip_probe,
2258 .remove_new = gswip_remove,
2259 .shutdown = gswip_shutdown,
2260 .driver = {
2261 .name = "gswip",
2262 .of_match_table = gswip_of_match,
2263 },
2264};
2265
2266module_platform_driver(gswip_driver);
2267
2268MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
2269MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
2270MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
2271MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
2272MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
2273MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
2274MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
2275MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
2276MODULE_LICENSE("GPL v2");