Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 | // SPDX-License-Identifier: GPL-2.0 /* * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs * * Copyright (C) 2010 Lantiq Deutschland * Copyright (C) 2012 John Crispin <john@phrozen.org> * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> * * The VLAN and bridge model the GSWIP hardware uses does not directly * matches the model DSA uses. * * The hardware has 64 possible table entries for bridges with one VLAN * ID, one flow id and a list of ports for each bridge. All entries which * match the same flow ID are combined in the mac learning table, they * act as one global bridge. * The hardware does not support VLAN filter on the port, but on the * bridge, this driver converts the DSA model to the hardware. * * The CPU gets all the exception frames which do not match any forwarding * rule and the CPU port is also added to all bridges. This makes it possible * to handle all the special cases easily in software. * At the initialization the driver allocates one bridge table entry for * each switch port which is used when the port is used without an * explicit bridge. This prevents the frames from being forwarded * between all LAN ports by default. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/etherdevice.h> #include <linux/firmware.h> #include <linux/if_bridge.h> #include <linux/if_vlan.h> #include <linux/iopoll.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_mdio.h> #include <linux/of_net.h> #include <linux/of_platform.h> #include <linux/phy.h> #include <linux/phylink.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset.h> #include <net/dsa.h> #include <dt-bindings/mips/lantiq_rcu_gphy.h> #include "lantiq_pce.h" /* GSWIP MDIO Registers */ #define GSWIP_MDIO_GLOB 0x00 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) #define GSWIP_MDIO_CTRL 0x08 #define GSWIP_MDIO_CTRL_BUSY BIT(12) #define GSWIP_MDIO_CTRL_RD BIT(11) #define GSWIP_MDIO_CTRL_WR BIT(10) #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f #define GSWIP_MDIO_READ 0x09 #define GSWIP_MDIO_WRITE 0x0A #define GSWIP_MDIO_MDC_CFG0 0x0B #define GSWIP_MDIO_MDC_CFG1 0x0C #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ GSWIP_MDIO_PHY_FCONRX_MASK | \ GSWIP_MDIO_PHY_FCONTX_MASK | \ GSWIP_MDIO_PHY_LINK_MASK | \ GSWIP_MDIO_PHY_SPEED_MASK | \ GSWIP_MDIO_PHY_FDUP_MASK) /* GSWIP MII Registers */ #define GSWIP_MII_CFGp(p) (0x2 * (p)) #define GSWIP_MII_CFG_RESET BIT(15) #define GSWIP_MII_CFG_EN BIT(14) #define GSWIP_MII_CFG_ISOLATE BIT(13) #define GSWIP_MII_CFG_LDCLKDIS BIT(12) #define GSWIP_MII_CFG_RGMII_IBS BIT(8) #define GSWIP_MII_CFG_RMII_CLK BIT(7) #define GSWIP_MII_CFG_MODE_MIIP 0x0 #define GSWIP_MII_CFG_MODE_MIIM 0x1 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 #define GSWIP_MII_CFG_MODE_RGMII 0x4 #define GSWIP_MII_CFG_MODE_GMII 0x9 #define GSWIP_MII_CFG_MODE_MASK 0xf #define GSWIP_MII_CFG_RATE_M2P5 0x00 #define GSWIP_MII_CFG_RATE_M25 0x10 #define GSWIP_MII_CFG_RATE_M125 0x20 #define GSWIP_MII_CFG_RATE_M50 0x30 #define GSWIP_MII_CFG_RATE_AUTO 0x40 #define GSWIP_MII_CFG_RATE_MASK 0x70 #define GSWIP_MII_PCDU0 0x01 #define GSWIP_MII_PCDU1 0x03 #define GSWIP_MII_PCDU5 0x05 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) /* GSWIP Core Registers */ #define GSWIP_SWRES 0x000 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ #define GSWIP_VERSION 0x013 #define GSWIP_VERSION_REV_SHIFT 0 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) #define GSWIP_VERSION_MOD_SHIFT 8 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) #define GSWIP_VERSION_2_0 0x100 #define GSWIP_VERSION_2_1 0x021 #define GSWIP_VERSION_2_2 0x122 #define GSWIP_VERSION_2_2_ETC 0x022 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) #define GSWIP_BM_RAM_ADDR 0x044 #define GSWIP_BM_RAM_CTRL 0x045 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) #define GSWIP_BM_QUEUE_GCTRL 0x04A #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) /* buffer management Port Configuration Register */ #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ /* buffer management Port Control Register */ #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ /* PCE */ #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) #define GSWIP_PCE_TBL_MASK 0x448 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) #define GSWIP_PCE_TBL_ADDR 0x44E #define GSWIP_PCE_TBL_CTRL 0x44F #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ #define GSWIP_PCE_GCTRL_0 0x456 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ #define GSWIP_PCE_GCTRL_1 0x457 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) #define GSWIP_MAC_FLEN 0x8C5 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) #define GSWIP_MAC_CTRL_0_PADEN BIT(8) #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) #define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */ #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ /* Ethernet Switch Fetch DMA Port Control Register */ #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) /* Ethernet Switch Store DMA Port Control Register */ #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ #define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */ #define GSWIP_TABLE_ACTIVE_VLAN 0x01 #define GSWIP_TABLE_VLAN_MAPPING 0x02 #define GSWIP_TABLE_MAC_BRIDGE 0x0b #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ #define XRX200_GPHY_FW_ALIGN (16 * 1024) /* Maximum packet size supported by the switch. In theory this should be 10240, * but long packets currently cause lock-ups with an MTU of over 2526. Medium * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP * over 2526), hence an MTU value of 2400 seems safe. This issue only affects * packet reception. This is probably caused by the PPA engine, which is on the * RX part of the device. Packet transmission works properly up to 10240. */ #define GSWIP_MAX_PACKET_LENGTH 2400 struct gswip_hw_info { int max_ports; int cpu_port; const struct dsa_switch_ops *ops; }; struct xway_gphy_match_data { char *fe_firmware_name; char *ge_firmware_name; }; struct gswip_gphy_fw { struct clk *clk_gate; struct reset_control *reset; u32 fw_addr_offset; char *fw_name; }; struct gswip_vlan { struct net_device *bridge; u16 vid; u8 fid; }; struct gswip_priv { __iomem void *gswip; __iomem void *mdio; __iomem void *mii; const struct gswip_hw_info *hw_info; const struct xway_gphy_match_data *gphy_fw_name_cfg; struct dsa_switch *ds; struct device *dev; struct regmap *rcu_regmap; struct gswip_vlan vlans[64]; int num_gphy_fw; struct gswip_gphy_fw *gphy_fw; u32 port_vlan_filter; struct mutex pce_table_lock; }; struct gswip_pce_table_entry { u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index u16 table; // PCE_TBL_CTRL.ADDR = pData->table u16 key[8]; u16 val[5]; u16 mask; u8 gmap; bool type; bool valid; bool key_mode; }; struct gswip_rmon_cnt_desc { unsigned int size; unsigned int offset; const char *name; }; #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { /** Receive Packet Count (only packets that are accepted and not discarded). */ MIB_DESC(1, 0x1F, "RxGoodPkts"), MIB_DESC(1, 0x23, "RxUnicastPkts"), MIB_DESC(1, 0x22, "RxMulticastPkts"), MIB_DESC(1, 0x21, "RxFCSErrorPkts"), MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), MIB_DESC(1, 0x20, "RxGoodPausePkts"), MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), MIB_DESC(1, 0x12, "Rx64BytePkts"), MIB_DESC(1, 0x13, "Rx127BytePkts"), MIB_DESC(1, 0x14, "Rx255BytePkts"), MIB_DESC(1, 0x15, "Rx511BytePkts"), MIB_DESC(1, 0x16, "Rx1023BytePkts"), /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ MIB_DESC(1, 0x17, "RxMaxBytePkts"), MIB_DESC(1, 0x18, "RxDroppedPkts"), MIB_DESC(1, 0x19, "RxFilteredPkts"), MIB_DESC(2, 0x24, "RxGoodBytes"), MIB_DESC(2, 0x26, "RxBadBytes"), MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), MIB_DESC(1, 0x0C, "TxGoodPkts"), MIB_DESC(1, 0x06, "TxUnicastPkts"), MIB_DESC(1, 0x07, "TxMulticastPkts"), MIB_DESC(1, 0x00, "Tx64BytePkts"), MIB_DESC(1, 0x01, "Tx127BytePkts"), MIB_DESC(1, 0x02, "Tx255BytePkts"), MIB_DESC(1, 0x03, "Tx511BytePkts"), MIB_DESC(1, 0x04, "Tx1023BytePkts"), /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ MIB_DESC(1, 0x05, "TxMaxBytePkts"), MIB_DESC(1, 0x08, "TxSingleCollCount"), MIB_DESC(1, 0x09, "TxMultCollCount"), MIB_DESC(1, 0x0A, "TxLateCollCount"), MIB_DESC(1, 0x0B, "TxExcessCollCount"), MIB_DESC(1, 0x0D, "TxPauseCount"), MIB_DESC(1, 0x10, "TxDroppedPkts"), MIB_DESC(2, 0x0E, "TxGoodBytes"), }; static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) { return __raw_readl(priv->gswip + (offset * 4)); } static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) { __raw_writel(val, priv->gswip + (offset * 4)); } static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { u32 val = gswip_switch_r(priv, offset); val &= ~(clear); val |= set; gswip_switch_w(priv, val, offset); } static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, u32 cleared) { u32 val; return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, (val & cleared) == 0, 20, 50000); } static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) { return __raw_readl(priv->mdio + (offset * 4)); } static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) { __raw_writel(val, priv->mdio + (offset * 4)); } static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { u32 val = gswip_mdio_r(priv, offset); val &= ~(clear); val |= set; gswip_mdio_w(priv, val, offset); } static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) { return __raw_readl(priv->mii + (offset * 4)); } static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) { __raw_writel(val, priv->mii + (offset * 4)); } static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { u32 val = gswip_mii_r(priv, offset); val &= ~(clear); val |= set; gswip_mii_w(priv, val, offset); } static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, int port) { /* There's no MII_CFG register for the CPU port */ if (!dsa_is_cpu_port(priv->ds, port)) gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); } static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, int port) { switch (port) { case 0: gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); break; case 1: gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); break; case 5: gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); break; } } static int gswip_mdio_poll(struct gswip_priv *priv) { int cnt = 100; while (likely(cnt--)) { u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) return 0; usleep_range(20, 40); } return -ETIMEDOUT; } static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) { struct gswip_priv *priv = bus->priv; int err; err = gswip_mdio_poll(priv); if (err) { dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); return err; } gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | (reg & GSWIP_MDIO_CTRL_REGAD_MASK), GSWIP_MDIO_CTRL); return 0; } static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) { struct gswip_priv *priv = bus->priv; int err; err = gswip_mdio_poll(priv); if (err) { dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); return err; } gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | (reg & GSWIP_MDIO_CTRL_REGAD_MASK), GSWIP_MDIO_CTRL); err = gswip_mdio_poll(priv); if (err) { dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); return err; } return gswip_mdio_r(priv, GSWIP_MDIO_READ); } static int gswip_mdio(struct gswip_priv *priv) { struct device_node *mdio_np, *switch_np = priv->dev->of_node; struct device *dev = priv->dev; struct mii_bus *bus; int err = 0; mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio"); if (!of_device_is_available(mdio_np)) goto out_put_node; bus = devm_mdiobus_alloc(dev); if (!bus) { err = -ENOMEM; goto out_put_node; } bus->priv = priv; bus->read = gswip_mdio_rd; bus->write = gswip_mdio_wr; bus->name = "lantiq,xrx200-mdio"; snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev)); bus->parent = priv->dev; err = devm_of_mdiobus_register(dev, bus, mdio_np); out_put_node: of_node_put(mdio_np); return err; } static int gswip_pce_table_entry_read(struct gswip_priv *priv, struct gswip_pce_table_entry *tbl) { int i; int err; u16 crtl; u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; mutex_lock(&priv->pce_table_lock); err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_BAS); if (err) { mutex_unlock(&priv->pce_table_lock); return err; } gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK, tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, GSWIP_PCE_TBL_CTRL); err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_BAS); if (err) { mutex_unlock(&priv->pce_table_lock); return err; } for (i = 0; i < ARRAY_SIZE(tbl->key); i++) tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); for (i = 0; i < ARRAY_SIZE(tbl->val); i++) tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; mutex_unlock(&priv->pce_table_lock); return 0; } static int gswip_pce_table_entry_write(struct gswip_priv *priv, struct gswip_pce_table_entry *tbl) { int i; int err; u16 crtl; u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; mutex_lock(&priv->pce_table_lock); err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_BAS); if (err) { mutex_unlock(&priv->pce_table_lock); return err; } gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK, tbl->table | addr_mode, GSWIP_PCE_TBL_CTRL); for (i = 0; i < ARRAY_SIZE(tbl->key); i++) gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); for (i = 0; i < ARRAY_SIZE(tbl->val); i++) gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK, tbl->table | addr_mode, GSWIP_PCE_TBL_CTRL); gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | GSWIP_PCE_TBL_CTRL_GMAP_MASK); if (tbl->type) crtl |= GSWIP_PCE_TBL_CTRL_TYPE; if (tbl->valid) crtl |= GSWIP_PCE_TBL_CTRL_VLD; crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; crtl |= GSWIP_PCE_TBL_CTRL_BAS; gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_BAS); mutex_unlock(&priv->pce_table_lock); return err; } /* Add the LAN port into a bridge with the CPU port by * default. This prevents automatic forwarding of * packages between the LAN ports when no explicit * bridge is configured. */ static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) { struct gswip_pce_table_entry vlan_active = {0,}; struct gswip_pce_table_entry vlan_mapping = {0,}; unsigned int cpu_port = priv->hw_info->cpu_port; unsigned int max_ports = priv->hw_info->max_ports; int err; if (port >= max_ports) { dev_err(priv->dev, "single port for %i supported\n", port); return -EIO; } vlan_active.index = port + 1; vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; vlan_active.key[0] = 0; /* vid */ vlan_active.val[0] = port + 1 /* fid */; vlan_active.valid = add; err = gswip_pce_table_entry_write(priv, &vlan_active); if (err) { dev_err(priv->dev, "failed to write active VLAN: %d\n", err); return err; } if (!add) return 0; vlan_mapping.index = port + 1; vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; vlan_mapping.val[0] = 0 /* vid */; vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); vlan_mapping.val[2] = 0; err = gswip_pce_table_entry_write(priv, &vlan_mapping); if (err) { dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); return err; } return 0; } static int gswip_port_enable(struct dsa_switch *ds, int port, struct phy_device *phydev) { struct gswip_priv *priv = ds->priv; int err; if (!dsa_is_user_port(ds, port)) return 0; if (!dsa_is_cpu_port(ds, port)) { err = gswip_add_single_port_br(priv, port, true); if (err) return err; } /* RMON Counter Enable for port */ gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); /* enable port fetch/store dma & VLAN Modification */ gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | GSWIP_FDMA_PCTRL_VLANMOD_BOTH, GSWIP_FDMA_PCTRLp(port)); gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, GSWIP_SDMA_PCTRLp(port)); if (!dsa_is_cpu_port(ds, port)) { u32 mdio_phy = 0; if (phydev) mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, GSWIP_MDIO_PHYp(port)); } return 0; } static void gswip_port_disable(struct dsa_switch *ds, int port) { struct gswip_priv *priv = ds->priv; if (!dsa_is_user_port(ds, port)) return; gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, GSWIP_FDMA_PCTRLp(port)); gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, GSWIP_SDMA_PCTRLp(port)); } static int gswip_pce_load_microcode(struct gswip_priv *priv) { int i; int err; gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK, GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); gswip_switch_w(priv, gswip_pce_microcode[i].val_0, GSWIP_PCE_TBL_VAL(0)); gswip_switch_w(priv, gswip_pce_microcode[i].val_1, GSWIP_PCE_TBL_VAL(1)); gswip_switch_w(priv, gswip_pce_microcode[i].val_2, GSWIP_PCE_TBL_VAL(2)); gswip_switch_w(priv, gswip_pce_microcode[i].val_3, GSWIP_PCE_TBL_VAL(3)); /* start the table access: */ gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, GSWIP_PCE_TBL_CTRL); err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_BAS); if (err) return err; } /* tell the switch that the microcode is loaded */ gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, GSWIP_PCE_GCTRL_0); return 0; } static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack) { struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); struct gswip_priv *priv = ds->priv; /* Do not allow changing the VLAN filtering options while in bridge */ if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { NL_SET_ERR_MSG_MOD(extack, "Dynamic toggling of vlan_filtering not supported"); return -EIO; } if (vlan_filtering) { /* Use port based VLAN tag */ gswip_switch_mask(priv, GSWIP_PCE_VCTRL_VSR, GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | GSWIP_PCE_VCTRL_VEMR, GSWIP_PCE_VCTRL(port)); gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, GSWIP_PCE_PCTRL_0p(port)); } else { /* Use port based VLAN tag */ gswip_switch_mask(priv, GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | GSWIP_PCE_VCTRL_VEMR, GSWIP_PCE_VCTRL_VSR, GSWIP_PCE_VCTRL(port)); gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, GSWIP_PCE_PCTRL_0p(port)); } return 0; } static int gswip_setup(struct dsa_switch *ds) { struct gswip_priv *priv = ds->priv; unsigned int cpu_port = priv->hw_info->cpu_port; int i; int err; gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); usleep_range(5000, 10000); gswip_switch_w(priv, 0, GSWIP_SWRES); /* disable port fetch/store dma on all ports */ for (i = 0; i < priv->hw_info->max_ports; i++) { gswip_port_disable(ds, i); gswip_port_vlan_filtering(ds, i, false, NULL); } /* enable Switch */ gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); err = gswip_pce_load_microcode(priv); if (err) { dev_err(priv->dev, "writing PCE microcode failed, %i", err); return err; } /* Default unknown Broadcast/Multicast/Unicast port maps */ gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an * interoperability problem with this auto polling mechanism because * their status registers think that the link is in a different state * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the * auto polling state machine consider the link being negotiated with * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads * to the switch port being completely dead (RX and TX are both not * working). * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes * it would work fine for a few minutes to hours and then stop, on * other device it would no traffic could be sent or received at all. * Testing shows that when PHY auto polling is disabled these problems * go away. */ gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); /* Configure the MDIO Clock 2.5 MHz */ gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); /* Disable the xMII interface and clear it's isolation bit */ for (i = 0; i < priv->hw_info->max_ports; i++) gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, 0, i); /* enable special tag insertion on cpu port */ gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, GSWIP_FDMA_PCTRLp(cpu_port)); /* accept special tag in ingress direction */ gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, GSWIP_PCE_PCTRL_0p(cpu_port)); gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, GSWIP_BM_QUEUE_GCTRL); /* VLAN aware Switching */ gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); /* Flush MAC Table */ gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, GSWIP_PCE_GCTRL_0_MTFL); if (err) { dev_err(priv->dev, "MAC flushing didn't finish\n"); return err; } ds->mtu_enforcement_ingress = true; gswip_port_enable(ds, cpu_port, NULL); ds->configure_vlan_while_not_filtering = false; return 0; } static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) { return DSA_TAG_PROTO_GSWIP; } static int gswip_vlan_active_create(struct gswip_priv *priv, struct net_device *bridge, int fid, u16 vid) { struct gswip_pce_table_entry vlan_active = {0,}; unsigned int max_ports = priv->hw_info->max_ports; int idx = -1; int err; int i; /* Look for a free slot */ for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { if (!priv->vlans[i].bridge) { idx = i; break; } } if (idx == -1) return -ENOSPC; if (fid == -1) fid = idx; vlan_active.index = idx; vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; vlan_active.key[0] = vid; vlan_active.val[0] = fid; vlan_active.valid = true; err = gswip_pce_table_entry_write(priv, &vlan_active); if (err) { dev_err(priv->dev, "failed to write active VLAN: %d\n", err); return err; } priv->vlans[idx].bridge = bridge; priv->vlans[idx].vid = vid; priv->vlans[idx].fid = fid; return idx; } static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) { struct gswip_pce_table_entry vlan_active = {0,}; int err; vlan_active.index = idx; vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; vlan_active.valid = false; err = gswip_pce_table_entry_write(priv, &vlan_active); if (err) dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); priv->vlans[idx].bridge = NULL; return err; } static int gswip_vlan_add_unaware(struct gswip_priv *priv, struct net_device *bridge, int port) { struct gswip_pce_table_entry vlan_mapping = {0,}; unsigned int max_ports = priv->hw_info->max_ports; unsigned int cpu_port = priv->hw_info->cpu_port; bool active_vlan_created = false; int idx = -1; int i; int err; /* Check if there is already a page for this bridge */ for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { if (priv->vlans[i].bridge == bridge) { idx = i; break; } } /* If this bridge is not programmed yet, add a Active VLAN table * entry in a free slot and prepare the VLAN mapping table entry. */ if (idx == -1) { idx = gswip_vlan_active_create(priv, bridge, -1, 0); if (idx < 0) return idx; active_vlan_created = true; vlan_mapping.index = idx; vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; /* VLAN ID byte, maps to the VLAN ID of vlan active table */ vlan_mapping.val[0] = 0; } else { /* Read the existing VLAN mapping entry from the switch */ vlan_mapping.index = idx; vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; err = gswip_pce_table_entry_read(priv, &vlan_mapping); if (err) { dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); return err; } } /* Update the VLAN mapping entry and write it to the switch */ vlan_mapping.val[1] |= BIT(cpu_port); vlan_mapping.val[1] |= BIT(port); err = gswip_pce_table_entry_write(priv, &vlan_mapping); if (err) { dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); /* In case an Active VLAN was creaetd delete it again */ if (active_vlan_created) gswip_vlan_active_remove(priv, idx); return err; } gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); return 0; } static int gswip_vlan_add_aware(struct gswip_priv *priv, struct net_device *bridge, int port, u16 vid, bool untagged, bool pvid) { struct gswip_pce_table_entry vlan_mapping = {0,}; unsigned int max_ports = priv->hw_info->max_ports; unsigned int cpu_port = priv->hw_info->cpu_port; bool active_vlan_created = false; int idx = -1; int fid = -1; int i; int err; /* Check if there is already a page for this bridge */ for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { if (priv->vlans[i].bridge == bridge) { if (fid != -1 && fid != priv->vlans[i].fid) dev_err(priv->dev, "one bridge with multiple flow ids\n"); fid = priv->vlans[i].fid; if (priv->vlans[i].vid == vid) { idx = i; break; } } } /* If this bridge is not programmed yet, add a Active VLAN table * entry in a free slot and prepare the VLAN mapping table entry. */ if (idx == -1) { idx = gswip_vlan_active_create(priv, bridge, fid, vid); if (idx < 0) return idx; active_vlan_created = true; vlan_mapping.index = idx; vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; /* VLAN ID byte, maps to the VLAN ID of vlan active table */ vlan_mapping.val[0] = vid; } else { /* Read the existing VLAN mapping entry from the switch */ vlan_mapping.index = idx; vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; err = gswip_pce_table_entry_read(priv, &vlan_mapping); if (err) { dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); return err; } } vlan_mapping.val[0] = vid; /* Update the VLAN mapping entry and write it to the switch */ vlan_mapping.val[1] |= BIT(cpu_port); vlan_mapping.val[2] |= BIT(cpu_port); vlan_mapping.val[1] |= BIT(port); if (untagged) vlan_mapping.val[2] &= ~BIT(port); else vlan_mapping.val[2] |= BIT(port); err = gswip_pce_table_entry_write(priv, &vlan_mapping); if (err) { dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); /* In case an Active VLAN was creaetd delete it again */ if (active_vlan_created) gswip_vlan_active_remove(priv, idx); return err; } if (pvid) gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); return 0; } static int gswip_vlan_remove(struct gswip_priv *priv, struct net_device *bridge, int port, u16 vid, bool pvid, bool vlan_aware) { struct gswip_pce_table_entry vlan_mapping = {0,}; unsigned int max_ports = priv->hw_info->max_ports; unsigned int cpu_port = priv->hw_info->cpu_port; int idx = -1; int i; int err; /* Check if there is already a page for this bridge */ for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { if (priv->vlans[i].bridge == bridge && (!vlan_aware || priv->vlans[i].vid == vid)) { idx = i; break; } } if (idx == -1) { dev_err(priv->dev, "bridge to leave does not exists\n"); return -ENOENT; } vlan_mapping.index = idx; vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; err = gswip_pce_table_entry_read(priv, &vlan_mapping); if (err) { dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); return err; } vlan_mapping.val[1] &= ~BIT(port); vlan_mapping.val[2] &= ~BIT(port); err = gswip_pce_table_entry_write(priv, &vlan_mapping); if (err) { dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); return err; } /* In case all ports are removed from the bridge, remove the VLAN */ if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { err = gswip_vlan_active_remove(priv, idx); if (err) { dev_err(priv->dev, "failed to write active VLAN: %d\n", err); return err; } } /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ if (pvid) gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); return 0; } static int gswip_port_bridge_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, bool *tx_fwd_offload, struct netlink_ext_ack *extack) { struct net_device *br = bridge.dev; struct gswip_priv *priv = ds->priv; int err; /* When the bridge uses VLAN filtering we have to configure VLAN * specific bridges. No bridge is configured here. */ if (!br_vlan_enabled(br)) { err = gswip_vlan_add_unaware(priv, br, port); if (err) return err; priv->port_vlan_filter &= ~BIT(port); } else { priv->port_vlan_filter |= BIT(port); } return gswip_add_single_port_br(priv, port, false); } static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) { struct net_device *br = bridge.dev; struct gswip_priv *priv = ds->priv; gswip_add_single_port_br(priv, port, true); /* When the bridge uses VLAN filtering we have to configure VLAN * specific bridges. No bridge is configured here. */ if (!br_vlan_enabled(br)) gswip_vlan_remove(priv, br, port, 0, true, false); } static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan, struct netlink_ext_ack *extack) { struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); struct gswip_priv *priv = ds->priv; unsigned int max_ports = priv->hw_info->max_ports; int pos = max_ports; int i, idx = -1; /* We only support VLAN filtering on bridges */ if (!dsa_is_cpu_port(ds, port) && !bridge) return -EOPNOTSUPP; /* Check if there is already a page for this VLAN */ for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { if (priv->vlans[i].bridge == bridge && priv->vlans[i].vid == vlan->vid) { idx = i; break; } } /* If this VLAN is not programmed yet, we have to reserve * one entry in the VLAN table. Make sure we start at the * next position round. */ if (idx == -1) { /* Look for a free slot */ for (; pos < ARRAY_SIZE(priv->vlans); pos++) { if (!priv->vlans[pos].bridge) { idx = pos; pos++; break; } } if (idx == -1) { NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); return -ENOSPC; } } return 0; } static int gswip_port_vlan_add(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan, struct netlink_ext_ack *extack) { struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); struct gswip_priv *priv = ds->priv; bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; int err; err = gswip_port_vlan_prepare(ds, port, vlan, extack); if (err) return err; /* We have to receive all packets on the CPU port and should not * do any VLAN filtering here. This is also called with bridge * NULL and then we do not know for which bridge to configure * this. */ if (dsa_is_cpu_port(ds, port)) return 0; return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, untagged, pvid); } static int gswip_port_vlan_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan) { struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); struct gswip_priv *priv = ds->priv; bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; /* We have to receive all packets on the CPU port and should not * do any VLAN filtering here. This is also called with bridge * NULL and then we do not know for which bridge to configure * this. */ if (dsa_is_cpu_port(ds, port)) return 0; return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); } static void gswip_port_fast_age(struct dsa_switch *ds, int port) { struct gswip_priv *priv = ds->priv; struct gswip_pce_table_entry mac_bridge = {0,}; int i; int err; for (i = 0; i < 2048; i++) { mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; mac_bridge.index = i; err = gswip_pce_table_entry_read(priv, &mac_bridge); if (err) { dev_err(priv->dev, "failed to read mac bridge: %d\n", err); return; } if (!mac_bridge.valid) continue; if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) continue; if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) continue; mac_bridge.valid = false; err = gswip_pce_table_entry_write(priv, &mac_bridge); if (err) { dev_err(priv->dev, "failed to write mac bridge: %d\n", err); return; } } } static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { struct gswip_priv *priv = ds->priv; u32 stp_state; switch (state) { case BR_STATE_DISABLED: gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, GSWIP_SDMA_PCTRLp(port)); return; case BR_STATE_BLOCKING: case BR_STATE_LISTENING: stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; break; case BR_STATE_LEARNING: stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; break; case BR_STATE_FORWARDING: stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; break; default: dev_err(priv->dev, "invalid STP state: %d\n", state); return; } gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, GSWIP_SDMA_PCTRLp(port)); gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, GSWIP_PCE_PCTRL_0p(port)); } static int gswip_port_fdb(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid, bool add) { struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); struct gswip_priv *priv = ds->priv; struct gswip_pce_table_entry mac_bridge = {0,}; unsigned int max_ports = priv->hw_info->max_ports; int fid = -1; int i; int err; if (!bridge) return -EINVAL; for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { if (priv->vlans[i].bridge == bridge) { fid = priv->vlans[i].fid; break; } } if (fid == -1) { dev_err(priv->dev, "Port not part of a bridge\n"); return -EINVAL; } mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; mac_bridge.key_mode = true; mac_bridge.key[0] = addr[5] | (addr[4] << 8); mac_bridge.key[1] = addr[3] | (addr[2] << 8); mac_bridge.key[2] = addr[1] | (addr[0] << 8); mac_bridge.key[3] = fid; mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; mac_bridge.valid = add; err = gswip_pce_table_entry_write(priv, &mac_bridge); if (err) dev_err(priv->dev, "failed to write mac bridge: %d\n", err); return err; } static int gswip_port_fdb_add(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid, struct dsa_db db) { return gswip_port_fdb(ds, port, addr, vid, true); } static int gswip_port_fdb_del(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid, struct dsa_db db) { return gswip_port_fdb(ds, port, addr, vid, false); } static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, dsa_fdb_dump_cb_t *cb, void *data) { struct gswip_priv *priv = ds->priv; struct gswip_pce_table_entry mac_bridge = {0,}; unsigned char addr[6]; int i; int err; for (i = 0; i < 2048; i++) { mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; mac_bridge.index = i; err = gswip_pce_table_entry_read(priv, &mac_bridge); if (err) { dev_err(priv->dev, "failed to read mac bridge entry %d: %d\n", i, err); return err; } if (!mac_bridge.valid) continue; addr[5] = mac_bridge.key[0] & 0xff; addr[4] = (mac_bridge.key[0] >> 8) & 0xff; addr[3] = mac_bridge.key[1] & 0xff; addr[2] = (mac_bridge.key[1] >> 8) & 0xff; addr[1] = mac_bridge.key[2] & 0xff; addr[0] = (mac_bridge.key[2] >> 8) & 0xff; if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { if (mac_bridge.val[0] & BIT(port)) { err = cb(addr, 0, true, data); if (err) return err; } } else { if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) { err = cb(addr, 0, false, data); if (err) return err; } } } return 0; } static int gswip_port_max_mtu(struct dsa_switch *ds, int port) { /* Includes 8 bytes for special header. */ return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN; } static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct gswip_priv *priv = ds->priv; int cpu_port = priv->hw_info->cpu_port; /* CPU port always has maximum mtu of user ports, so use it to set * switch frame size, including 8 byte special header. */ if (port == cpu_port) { new_mtu += 8; gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, GSWIP_MAC_FLEN); } /* Enable MLEN for ports with non-standard MTUs, including the special * header on the CPU port added above. */ if (new_mtu != ETH_DATA_LEN) gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, GSWIP_MAC_CTRL_2p(port)); else gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0, GSWIP_MAC_CTRL_2p(port)); return 0; } static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { switch (port) { case 0: case 1: phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_RMII, config->supported_interfaces); break; case 2: case 3: case 4: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; case 5: phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; } config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; } static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { switch (port) { case 0: phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_RMII, config->supported_interfaces); break; case 1: case 2: case 3: case 4: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; case 5: phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_RMII, config->supported_interfaces); break; } config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; } static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) { u32 mdio_phy; if (link) mdio_phy = GSWIP_MDIO_PHY_LINK_UP; else mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, GSWIP_MDIO_PHYp(port)); } static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, phy_interface_t interface) { u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0; switch (speed) { case SPEED_10: mdio_phy = GSWIP_MDIO_PHY_SPEED_M10; if (interface == PHY_INTERFACE_MODE_RMII) mii_cfg = GSWIP_MII_CFG_RATE_M50; else mii_cfg = GSWIP_MII_CFG_RATE_M2P5; mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; break; case SPEED_100: mdio_phy = GSWIP_MDIO_PHY_SPEED_M100; if (interface == PHY_INTERFACE_MODE_RMII) mii_cfg = GSWIP_MII_CFG_RATE_M50; else mii_cfg = GSWIP_MII_CFG_RATE_M25; mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; break; case SPEED_1000: mdio_phy = GSWIP_MDIO_PHY_SPEED_G1; mii_cfg = GSWIP_MII_CFG_RATE_M125; mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII; break; } gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, GSWIP_MDIO_PHYp(port)); gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); } static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) { u32 mac_ctrl_0, mdio_phy; if (duplex == DUPLEX_FULL) { mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN; mdio_phy = GSWIP_MDIO_PHY_FDUP_EN; } else { mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS; mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; } gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, GSWIP_MDIO_PHYp(port)); } static void gswip_port_set_pause(struct gswip_priv *priv, int port, bool tx_pause, bool rx_pause) { u32 mac_ctrl_0, mdio_phy; if (tx_pause && rx_pause) { mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX; mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | GSWIP_MDIO_PHY_FCONRX_EN; } else if (tx_pause) { mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX; mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | GSWIP_MDIO_PHY_FCONRX_DIS; } else if (rx_pause) { mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX; mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | GSWIP_MDIO_PHY_FCONRX_EN; } else { mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE; mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | GSWIP_MDIO_PHY_FCONRX_DIS; } gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FCONTX_MASK | GSWIP_MDIO_PHY_FCONRX_MASK, mdio_phy, GSWIP_MDIO_PHYp(port)); } static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct gswip_priv *priv = ds->priv; u32 miicfg = 0; miicfg |= GSWIP_MII_CFG_LDCLKDIS; switch (state->interface) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_INTERNAL: miicfg |= GSWIP_MII_CFG_MODE_MIIM; break; case PHY_INTERFACE_MODE_REVMII: miicfg |= GSWIP_MII_CFG_MODE_MIIP; break; case PHY_INTERFACE_MODE_RMII: miicfg |= GSWIP_MII_CFG_MODE_RMIIM; break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: miicfg |= GSWIP_MII_CFG_MODE_RGMII; break; case PHY_INTERFACE_MODE_GMII: miicfg |= GSWIP_MII_CFG_MODE_GMII; break; default: dev_err(ds->dev, "Unsupported interface: %d\n", state->interface); return; } gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK | GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, miicfg, port); switch (state->interface) { case PHY_INTERFACE_MODE_RGMII_ID: gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | GSWIP_MII_PCDU_RXDLY_MASK, 0, port); break; case PHY_INTERFACE_MODE_RGMII_RXID: gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); break; case PHY_INTERFACE_MODE_RGMII_TXID: gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); break; default: break; } } static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { struct gswip_priv *priv = ds->priv; gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); if (!dsa_is_cpu_port(ds, port)) gswip_port_set_link(priv, port, false); } static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface, struct phy_device *phydev, int speed, int duplex, bool tx_pause, bool rx_pause) { struct gswip_priv *priv = ds->priv; if (!dsa_is_cpu_port(ds, port)) { gswip_port_set_link(priv, port, true); gswip_port_set_speed(priv, port, speed, interface); gswip_port_set_duplex(priv, port, duplex); gswip_port_set_pause(priv, port, tx_pause, rx_pause); } gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); } static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) { int i; if (stringset != ETH_SS_STATS) return; for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) ethtool_puts(&data, gswip_rmon_cnt[i].name); } static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, u32 index) { u32 result; int err; gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | GSWIP_BM_RAM_CTRL_OPMOD, table | GSWIP_BM_RAM_CTRL_BAS, GSWIP_BM_RAM_CTRL); err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, GSWIP_BM_RAM_CTRL_BAS); if (err) { dev_err(priv->dev, "timeout while reading table: %u, index: %u", table, index); return 0; } result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; return result; } static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) { struct gswip_priv *priv = ds->priv; const struct gswip_rmon_cnt_desc *rmon_cnt; int i; u64 high; for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { rmon_cnt = &gswip_rmon_cnt[i]; data[i] = gswip_bcm_ram_entry_read(priv, port, rmon_cnt->offset); if (rmon_cnt->size == 2) { high = gswip_bcm_ram_entry_read(priv, port, rmon_cnt->offset + 1); data[i] |= high << 32; } } } static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) { if (sset != ETH_SS_STATS) return 0; return ARRAY_SIZE(gswip_rmon_cnt); } static const struct dsa_switch_ops gswip_xrx200_switch_ops = { .get_tag_protocol = gswip_get_tag_protocol, .setup = gswip_setup, .port_enable = gswip_port_enable, .port_disable = gswip_port_disable, .port_bridge_join = gswip_port_bridge_join, .port_bridge_leave = gswip_port_bridge_leave, .port_fast_age = gswip_port_fast_age, .port_vlan_filtering = gswip_port_vlan_filtering, .port_vlan_add = gswip_port_vlan_add, .port_vlan_del = gswip_port_vlan_del, .port_stp_state_set = gswip_port_stp_state_set, .port_fdb_add = gswip_port_fdb_add, .port_fdb_del = gswip_port_fdb_del, .port_fdb_dump = gswip_port_fdb_dump, .port_change_mtu = gswip_port_change_mtu, .port_max_mtu = gswip_port_max_mtu, .phylink_get_caps = gswip_xrx200_phylink_get_caps, .phylink_mac_config = gswip_phylink_mac_config, .phylink_mac_link_down = gswip_phylink_mac_link_down, .phylink_mac_link_up = gswip_phylink_mac_link_up, .get_strings = gswip_get_strings, .get_ethtool_stats = gswip_get_ethtool_stats, .get_sset_count = gswip_get_sset_count, }; static const struct dsa_switch_ops gswip_xrx300_switch_ops = { .get_tag_protocol = gswip_get_tag_protocol, .setup = gswip_setup, .port_enable = gswip_port_enable, .port_disable = gswip_port_disable, .port_bridge_join = gswip_port_bridge_join, .port_bridge_leave = gswip_port_bridge_leave, .port_fast_age = gswip_port_fast_age, .port_vlan_filtering = gswip_port_vlan_filtering, .port_vlan_add = gswip_port_vlan_add, .port_vlan_del = gswip_port_vlan_del, .port_stp_state_set = gswip_port_stp_state_set, .port_fdb_add = gswip_port_fdb_add, .port_fdb_del = gswip_port_fdb_del, .port_fdb_dump = gswip_port_fdb_dump, .port_change_mtu = gswip_port_change_mtu, .port_max_mtu = gswip_port_max_mtu, .phylink_get_caps = gswip_xrx300_phylink_get_caps, .phylink_mac_config = gswip_phylink_mac_config, .phylink_mac_link_down = gswip_phylink_mac_link_down, .phylink_mac_link_up = gswip_phylink_mac_link_up, .get_strings = gswip_get_strings, .get_ethtool_stats = gswip_get_ethtool_stats, .get_sset_count = gswip_get_sset_count, }; static const struct xway_gphy_match_data xrx200a1x_gphy_data = { .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", }; static const struct xway_gphy_match_data xrx200a2x_gphy_data = { .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", }; static const struct xway_gphy_match_data xrx300_gphy_data = { .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", }; static const struct of_device_id xway_gphy_match[] __maybe_unused = { { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, {}, }; static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) { struct device *dev = priv->dev; const struct firmware *fw; void *fw_addr; dma_addr_t dma_addr; dma_addr_t dev_addr; size_t size; int ret; ret = clk_prepare_enable(gphy_fw->clk_gate); if (ret) return ret; reset_control_assert(gphy_fw->reset); /* The vendor BSP uses a 200ms delay after asserting the reset line. * Without this some users are observing that the PHY is not coming up * on the MDIO bus. */ msleep(200); ret = request_firmware(&fw, gphy_fw->fw_name, dev); if (ret) { dev_err(dev, "failed to load firmware: %s, error: %i\n", gphy_fw->fw_name, ret); return ret; } /* GPHY cores need the firmware code in a persistent and contiguous * memory area with a 16 kB boundary aligned start address. */ size = fw->size + XRX200_GPHY_FW_ALIGN; fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); if (fw_addr) { fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); memcpy(fw_addr, fw->data, fw->size); } else { dev_err(dev, "failed to alloc firmware memory\n"); release_firmware(fw); return -ENOMEM; } release_firmware(fw); ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); if (ret) return ret; reset_control_deassert(gphy_fw->reset); return ret; } static int gswip_gphy_fw_probe(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw, struct device_node *gphy_fw_np, int i) { struct device *dev = priv->dev; u32 gphy_mode; int ret; char gphyname[10]; snprintf(gphyname, sizeof(gphyname), "gphy%d", i); gphy_fw->clk_gate = devm_clk_get(dev, gphyname); if (IS_ERR(gphy_fw->clk_gate)) { dev_err(dev, "Failed to lookup gate clock\n"); return PTR_ERR(gphy_fw->clk_gate); } ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); if (ret) return ret; ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); /* Default to GE mode */ if (ret) gphy_mode = GPHY_MODE_GE; switch (gphy_mode) { case GPHY_MODE_FE: gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; break; case GPHY_MODE_GE: gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; break; default: dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); return -EINVAL; } gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); if (IS_ERR(gphy_fw->reset)) return dev_err_probe(dev, PTR_ERR(gphy_fw->reset), "Failed to lookup gphy reset\n"); return gswip_gphy_fw_load(priv, gphy_fw); } static void gswip_gphy_fw_remove(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) { int ret; /* check if the device was fully probed */ if (!gphy_fw->fw_name) return; ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); if (ret) dev_err(priv->dev, "can not reset GPHY FW pointer"); clk_disable_unprepare(gphy_fw->clk_gate); reset_control_put(gphy_fw->reset); } static int gswip_gphy_fw_list(struct gswip_priv *priv, struct device_node *gphy_fw_list_np, u32 version) { struct device *dev = priv->dev; struct device_node *gphy_fw_np; const struct of_device_id *match; int err; int i = 0; /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also * needs a different GPHY firmware. */ if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { switch (version) { case GSWIP_VERSION_2_0: priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; break; case GSWIP_VERSION_2_1: priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; break; default: dev_err(dev, "unknown GSWIP version: 0x%x", version); return -ENOENT; } } match = of_match_node(xway_gphy_match, gphy_fw_list_np); if (match && match->data) priv->gphy_fw_name_cfg = match->data; if (!priv->gphy_fw_name_cfg) { dev_err(dev, "GPHY compatible type not supported"); return -ENOENT; } priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); if (!priv->num_gphy_fw) return -ENOENT; priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, "lantiq,rcu"); if (IS_ERR(priv->rcu_regmap)) return PTR_ERR(priv->rcu_regmap); priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, sizeof(*priv->gphy_fw), GFP_KERNEL | __GFP_ZERO); if (!priv->gphy_fw) return -ENOMEM; for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], gphy_fw_np, i); if (err) { of_node_put(gphy_fw_np); goto remove_gphy; } i++; } /* The standalone PHY11G requires 300ms to be fully * initialized and ready for any MDIO communication after being * taken out of reset. For the SoC-internal GPHY variant there * is no (known) documentation for the minimum time after a * reset. Use the same value as for the standalone variant as * some users have reported internal PHYs not being detected * without any delay. */ msleep(300); return 0; remove_gphy: for (i = 0; i < priv->num_gphy_fw; i++) gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); return err; } static int gswip_probe(struct platform_device *pdev) { struct device_node *np, *gphy_fw_np; struct device *dev = &pdev->dev; struct gswip_priv *priv; int err; int i; u32 version; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->gswip = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->gswip)) return PTR_ERR(priv->gswip); priv->mdio = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(priv->mdio)) return PTR_ERR(priv->mdio); priv->mii = devm_platform_ioremap_resource(pdev, 2); if (IS_ERR(priv->mii)) return PTR_ERR(priv->mii); priv->hw_info = of_device_get_match_data(dev); if (!priv->hw_info) return -EINVAL; priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); if (!priv->ds) return -ENOMEM; priv->ds->dev = dev; priv->ds->num_ports = priv->hw_info->max_ports; priv->ds->priv = priv; priv->ds->ops = priv->hw_info->ops; priv->dev = dev; mutex_init(&priv->pce_table_lock); version = gswip_switch_r(priv, GSWIP_VERSION); np = dev->of_node; switch (version) { case GSWIP_VERSION_2_0: case GSWIP_VERSION_2_1: if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) return -EINVAL; break; case GSWIP_VERSION_2_2: case GSWIP_VERSION_2_2_ETC: if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && !of_device_is_compatible(np, "lantiq,xrx330-gswip")) return -EINVAL; break; default: dev_err(dev, "unknown GSWIP version: 0x%x", version); return -ENOENT; } /* bring up the mdio bus */ gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); if (gphy_fw_np) { err = gswip_gphy_fw_list(priv, gphy_fw_np, version); of_node_put(gphy_fw_np); if (err) { dev_err(dev, "gphy fw probe failed\n"); return err; } } /* bring up the mdio bus */ err = gswip_mdio(priv); if (err) { dev_err(dev, "mdio probe failed\n"); goto gphy_fw_remove; } err = dsa_register_switch(priv->ds); if (err) { dev_err(dev, "dsa switch register failed: %i\n", err); goto gphy_fw_remove; } if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { dev_err(dev, "wrong CPU port defined, HW only supports port: %i", priv->hw_info->cpu_port); err = -EINVAL; goto disable_switch; } platform_set_drvdata(pdev, priv); dev_info(dev, "probed GSWIP version %lx mod %lx\n", (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); return 0; disable_switch: gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); dsa_unregister_switch(priv->ds); gphy_fw_remove: for (i = 0; i < priv->num_gphy_fw; i++) gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); return err; } static void gswip_remove(struct platform_device *pdev) { struct gswip_priv *priv = platform_get_drvdata(pdev); int i; if (!priv) return; /* disable the switch */ gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); dsa_unregister_switch(priv->ds); for (i = 0; i < priv->num_gphy_fw; i++) gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); } static void gswip_shutdown(struct platform_device *pdev) { struct gswip_priv *priv = platform_get_drvdata(pdev); if (!priv) return; dsa_switch_shutdown(priv->ds); platform_set_drvdata(pdev, NULL); } static const struct gswip_hw_info gswip_xrx200 = { .max_ports = 7, .cpu_port = 6, .ops = &gswip_xrx200_switch_ops, }; static const struct gswip_hw_info gswip_xrx300 = { .max_ports = 7, .cpu_port = 6, .ops = &gswip_xrx300_switch_ops, }; static const struct of_device_id gswip_of_match[] = { { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, {}, }; MODULE_DEVICE_TABLE(of, gswip_of_match); static struct platform_driver gswip_driver = { .probe = gswip_probe, .remove_new = gswip_remove, .shutdown = gswip_shutdown, .driver = { .name = "gswip", .of_match_table = gswip_of_match, }, }; module_platform_driver(gswip_driver); MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); MODULE_LICENSE("GPL v2"); |