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1// SPDX-License-Identifier: GPL-2.0
2/*
3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5#include <linux/kernel.h>
6#include <linux/serial.h>
7#include <linux/serial_reg.h>
8#include <linux/slab.h>
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/console.h>
12#include <linux/serial_core.h>
13#include <linux/tty.h>
14#include <linux/tty_flip.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/dmi.h>
18#include <linux/nmi.h>
19#include <linux/delay.h>
20#include <linux/of.h>
21
22#include <linux/debugfs.h>
23#include <linux/dmaengine.h>
24#include <linux/pch_dma.h>
25
26enum {
27 PCH_UART_HANDLED_RX_INT_SHIFT,
28 PCH_UART_HANDLED_TX_INT_SHIFT,
29 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
30 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
31 PCH_UART_HANDLED_MS_INT_SHIFT,
32 PCH_UART_HANDLED_LS_INT_SHIFT,
33};
34
35#define PCH_UART_DRIVER_DEVICE "ttyPCH"
36
37/* Set the max number of UART port
38 * Intel EG20T PCH: 4 port
39 * LAPIS Semiconductor ML7213 IOH: 3 port
40 * LAPIS Semiconductor ML7223 IOH: 2 port
41*/
42#define PCH_UART_NR 4
43
44#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
45#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
46#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
47 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
48#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
49 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
50#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
51
52#define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
53
54#define PCH_UART_RBR 0x00
55#define PCH_UART_THR 0x00
56
57#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
58 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
59#define PCH_UART_IER_ERBFI 0x00000001
60#define PCH_UART_IER_ETBEI 0x00000002
61#define PCH_UART_IER_ELSI 0x00000004
62#define PCH_UART_IER_EDSSI 0x00000008
63
64#define PCH_UART_IIR_IP 0x00000001
65#define PCH_UART_IIR_IID 0x00000006
66#define PCH_UART_IIR_MSI 0x00000000
67#define PCH_UART_IIR_TRI 0x00000002
68#define PCH_UART_IIR_RRI 0x00000004
69#define PCH_UART_IIR_REI 0x00000006
70#define PCH_UART_IIR_TOI 0x00000008
71#define PCH_UART_IIR_FIFO256 0x00000020
72#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
73#define PCH_UART_IIR_FE 0x000000C0
74
75#define PCH_UART_FCR_FIFOE 0x00000001
76#define PCH_UART_FCR_RFR 0x00000002
77#define PCH_UART_FCR_TFR 0x00000004
78#define PCH_UART_FCR_DMS 0x00000008
79#define PCH_UART_FCR_FIFO256 0x00000020
80#define PCH_UART_FCR_RFTL 0x000000C0
81
82#define PCH_UART_FCR_RFTL1 0x00000000
83#define PCH_UART_FCR_RFTL64 0x00000040
84#define PCH_UART_FCR_RFTL128 0x00000080
85#define PCH_UART_FCR_RFTL224 0x000000C0
86#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
87#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
88#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
89#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
90#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
91#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
92#define PCH_UART_FCR_RFTL_SHIFT 6
93
94#define PCH_UART_LCR_WLS 0x00000003
95#define PCH_UART_LCR_STB 0x00000004
96#define PCH_UART_LCR_PEN 0x00000008
97#define PCH_UART_LCR_EPS 0x00000010
98#define PCH_UART_LCR_SP 0x00000020
99#define PCH_UART_LCR_SB 0x00000040
100#define PCH_UART_LCR_DLAB 0x00000080
101#define PCH_UART_LCR_NP 0x00000000
102#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
103#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
104#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
105#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
106 PCH_UART_LCR_SP)
107
108#define PCH_UART_LCR_5BIT 0x00000000
109#define PCH_UART_LCR_6BIT 0x00000001
110#define PCH_UART_LCR_7BIT 0x00000002
111#define PCH_UART_LCR_8BIT 0x00000003
112
113#define PCH_UART_MCR_DTR 0x00000001
114#define PCH_UART_MCR_RTS 0x00000002
115#define PCH_UART_MCR_OUT 0x0000000C
116#define PCH_UART_MCR_LOOP 0x00000010
117#define PCH_UART_MCR_AFE 0x00000020
118
119#define PCH_UART_LSR_DR 0x00000001
120#define PCH_UART_LSR_ERR (1<<7)
121
122#define PCH_UART_MSR_DCTS 0x00000001
123#define PCH_UART_MSR_DDSR 0x00000002
124#define PCH_UART_MSR_TERI 0x00000004
125#define PCH_UART_MSR_DDCD 0x00000008
126#define PCH_UART_MSR_CTS 0x00000010
127#define PCH_UART_MSR_DSR 0x00000020
128#define PCH_UART_MSR_RI 0x00000040
129#define PCH_UART_MSR_DCD 0x00000080
130#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
131 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
132
133#define PCH_UART_DLL 0x00
134#define PCH_UART_DLM 0x01
135
136#define PCH_UART_BRCSR 0x0E
137
138#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
139#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
140#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
141#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
142#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
143
144#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
145#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
146#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
147#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
148#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
149#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
150#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
151#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
152#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
153#define PCH_UART_HAL_STB1 0
154#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
155
156#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
157#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
158#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
159 PCH_UART_HAL_CLR_RX_FIFO)
160
161#define PCH_UART_HAL_DMA_MODE0 0
162#define PCH_UART_HAL_FIFO_DIS 0
163#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
164#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
165 PCH_UART_FCR_FIFO256)
166#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
167#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
168#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
169#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
170#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
171#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
172#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
173#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
174#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
175#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
176#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
177#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
178#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
179#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
180
181#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
182#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
183#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
184#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
185#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
186
187#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
188#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
189#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
190#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
191#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
192
193#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
194#define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
195#define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
196#define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
197#define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
198#define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
199
200struct pch_uart_buffer {
201 unsigned char *buf;
202 int size;
203};
204
205struct eg20t_port {
206 struct uart_port port;
207 int port_type;
208 void __iomem *membase;
209 resource_size_t mapbase;
210 unsigned int iobase;
211 struct pci_dev *pdev;
212 int fifo_size;
213 unsigned int uartclk;
214 int start_tx;
215 int start_rx;
216 int tx_empty;
217 int trigger;
218 int trigger_level;
219 struct pch_uart_buffer rxbuf;
220 unsigned int dmsr;
221 unsigned int fcr;
222 unsigned int mcr;
223 unsigned int use_dma;
224 struct dma_async_tx_descriptor *desc_tx;
225 struct dma_async_tx_descriptor *desc_rx;
226 struct pch_dma_slave param_tx;
227 struct pch_dma_slave param_rx;
228 struct dma_chan *chan_tx;
229 struct dma_chan *chan_rx;
230 struct scatterlist *sg_tx_p;
231 int nent;
232 int orig_nent;
233 struct scatterlist sg_rx;
234 int tx_dma_use;
235 void *rx_buf_virt;
236 dma_addr_t rx_buf_dma;
237
238#define IRQ_NAME_SIZE 17
239 char irq_name[IRQ_NAME_SIZE];
240
241 /* protect the eg20t_port private structure and io access to membase */
242 spinlock_t lock;
243};
244
245/**
246 * struct pch_uart_driver_data - private data structure for UART-DMA
247 * @port_type: The type of UART port
248 * @line_no: UART port line number (0, 1, 2...)
249 */
250struct pch_uart_driver_data {
251 int port_type;
252 int line_no;
253};
254
255enum pch_uart_num_t {
256 pch_et20t_uart0 = 0,
257 pch_et20t_uart1,
258 pch_et20t_uart2,
259 pch_et20t_uart3,
260 pch_ml7213_uart0,
261 pch_ml7213_uart1,
262 pch_ml7213_uart2,
263 pch_ml7223_uart0,
264 pch_ml7223_uart1,
265 pch_ml7831_uart0,
266 pch_ml7831_uart1,
267};
268
269static struct pch_uart_driver_data drv_dat[] = {
270 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
271 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
272 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
273 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
274 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
275 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
276 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
277 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
278 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
279 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
280 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
281};
282
283#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
284static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
285#endif
286static unsigned int default_baud = 9600;
287static unsigned int user_uartclk = 0;
288static const int trigger_level_256[4] = { 1, 64, 128, 224 };
289static const int trigger_level_64[4] = { 1, 16, 32, 56 };
290static const int trigger_level_16[4] = { 1, 4, 8, 14 };
291static const int trigger_level_1[4] = { 1, 1, 1, 1 };
292
293#define PCH_REGS_BUFSIZE 1024
294
295
296static ssize_t port_show_regs(struct file *file, char __user *user_buf,
297 size_t count, loff_t *ppos)
298{
299 struct eg20t_port *priv = file->private_data;
300 char *buf;
301 u32 len = 0;
302 ssize_t ret;
303 unsigned char lcr;
304
305 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
306 if (!buf)
307 return 0;
308
309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
310 "PCH EG20T port[%d] regs:\n", priv->port.line);
311
312 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
313 "=================================\n");
314 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
315 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
316 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
317 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
318 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
319 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
320 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
321 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
322 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
323 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
324 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
325 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
326 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
327 "BRCSR: \t0x%02x\n",
328 ioread8(priv->membase + PCH_UART_BRCSR));
329
330 lcr = ioread8(priv->membase + UART_LCR);
331 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
332 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
333 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
334 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
336 iowrite8(lcr, priv->membase + UART_LCR);
337
338 if (len > PCH_REGS_BUFSIZE)
339 len = PCH_REGS_BUFSIZE;
340
341 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
342 kfree(buf);
343 return ret;
344}
345
346static const struct file_operations port_regs_ops = {
347 .owner = THIS_MODULE,
348 .open = simple_open,
349 .read = port_show_regs,
350 .llseek = default_llseek,
351};
352
353static const struct dmi_system_id pch_uart_dmi_table[] = {
354 {
355 .ident = "CM-iTC",
356 {
357 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
358 },
359 (void *)CMITC_UARTCLK,
360 },
361 {
362 .ident = "FRI2",
363 {
364 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
365 },
366 (void *)FRI2_64_UARTCLK,
367 },
368 {
369 .ident = "Fish River Island II",
370 {
371 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
372 },
373 (void *)FRI2_48_UARTCLK,
374 },
375 {
376 .ident = "COMe-mTT",
377 {
378 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
379 },
380 (void *)NTC1_UARTCLK,
381 },
382 {
383 .ident = "nanoETXexpress-TT",
384 {
385 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
386 },
387 (void *)NTC1_UARTCLK,
388 },
389 {
390 .ident = "MinnowBoard",
391 {
392 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
393 },
394 (void *)MINNOW_UARTCLK,
395 },
396 { }
397};
398
399/* Return UART clock, checking for board specific clocks. */
400static unsigned int pch_uart_get_uartclk(void)
401{
402 const struct dmi_system_id *d;
403
404 if (user_uartclk)
405 return user_uartclk;
406
407 d = dmi_first_match(pch_uart_dmi_table);
408 if (d)
409 return (unsigned long)d->driver_data;
410
411 return DEFAULT_UARTCLK;
412}
413
414static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
415 unsigned int flag)
416{
417 u8 ier = ioread8(priv->membase + UART_IER);
418 ier |= flag & PCH_UART_IER_MASK;
419 iowrite8(ier, priv->membase + UART_IER);
420}
421
422static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
423 unsigned int flag)
424{
425 u8 ier = ioread8(priv->membase + UART_IER);
426 ier &= ~(flag & PCH_UART_IER_MASK);
427 iowrite8(ier, priv->membase + UART_IER);
428}
429
430static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
431 unsigned int parity, unsigned int bits,
432 unsigned int stb)
433{
434 unsigned int dll, dlm, lcr;
435 int div;
436
437 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
438 if (div < 0 || USHRT_MAX <= div) {
439 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
440 return -EINVAL;
441 }
442
443 dll = (unsigned int)div & 0x00FFU;
444 dlm = ((unsigned int)div >> 8) & 0x00FFU;
445
446 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
447 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
448 return -EINVAL;
449 }
450
451 if (bits & ~PCH_UART_LCR_WLS) {
452 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
453 return -EINVAL;
454 }
455
456 if (stb & ~PCH_UART_LCR_STB) {
457 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
458 return -EINVAL;
459 }
460
461 lcr = parity;
462 lcr |= bits;
463 lcr |= stb;
464
465 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
466 __func__, baud, div, lcr, jiffies);
467 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
468 iowrite8(dll, priv->membase + PCH_UART_DLL);
469 iowrite8(dlm, priv->membase + PCH_UART_DLM);
470 iowrite8(lcr, priv->membase + UART_LCR);
471
472 return 0;
473}
474
475static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
476 unsigned int flag)
477{
478 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
479 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
480 __func__, flag);
481 return -EINVAL;
482 }
483
484 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
485 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
486 priv->membase + UART_FCR);
487 iowrite8(priv->fcr, priv->membase + UART_FCR);
488
489 return 0;
490}
491
492static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
493 unsigned int dmamode,
494 unsigned int fifo_size, unsigned int trigger)
495{
496 u8 fcr;
497
498 if (dmamode & ~PCH_UART_FCR_DMS) {
499 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
500 __func__, dmamode);
501 return -EINVAL;
502 }
503
504 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
505 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
506 __func__, fifo_size);
507 return -EINVAL;
508 }
509
510 if (trigger & ~PCH_UART_FCR_RFTL) {
511 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
512 __func__, trigger);
513 return -EINVAL;
514 }
515
516 switch (priv->fifo_size) {
517 case 256:
518 priv->trigger_level =
519 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
520 break;
521 case 64:
522 priv->trigger_level =
523 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
524 break;
525 case 16:
526 priv->trigger_level =
527 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
528 break;
529 default:
530 priv->trigger_level =
531 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
532 break;
533 }
534 fcr =
535 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
536 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
537 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
538 priv->membase + UART_FCR);
539 iowrite8(fcr, priv->membase + UART_FCR);
540 priv->fcr = fcr;
541
542 return 0;
543}
544
545static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
546{
547 unsigned int msr = ioread8(priv->membase + UART_MSR);
548 priv->dmsr = msr & PCH_UART_MSR_DELTA;
549 return (u8)msr;
550}
551
552static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
553 int rx_size)
554{
555 int i;
556 u8 rbr, lsr;
557 struct uart_port *port = &priv->port;
558
559 lsr = ioread8(priv->membase + UART_LSR);
560 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
561 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
562 lsr = ioread8(priv->membase + UART_LSR)) {
563 rbr = ioread8(priv->membase + PCH_UART_RBR);
564
565 if (lsr & UART_LSR_BI) {
566 port->icount.brk++;
567 if (uart_handle_break(port))
568 continue;
569 }
570 if (uart_handle_sysrq_char(port, rbr))
571 continue;
572
573 buf[i++] = rbr;
574 }
575 return i;
576}
577
578static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
579{
580 return ioread8(priv->membase + UART_IIR) &\
581 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
582}
583
584static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
585{
586 return ioread8(priv->membase + UART_LSR);
587}
588
589static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
590{
591 unsigned int lcr;
592
593 lcr = ioread8(priv->membase + UART_LCR);
594 if (on)
595 lcr |= PCH_UART_LCR_SB;
596 else
597 lcr &= ~PCH_UART_LCR_SB;
598
599 iowrite8(lcr, priv->membase + UART_LCR);
600}
601
602static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
603 int size)
604{
605 struct uart_port *port = &priv->port;
606 struct tty_port *tport = &port->state->port;
607
608 tty_insert_flip_string(tport, buf, size);
609 tty_flip_buffer_push(tport);
610
611 return 0;
612}
613
614static int dma_push_rx(struct eg20t_port *priv, int size)
615{
616 int room;
617 struct uart_port *port = &priv->port;
618 struct tty_port *tport = &port->state->port;
619
620 room = tty_buffer_request_room(tport, size);
621
622 if (room < size)
623 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
624 size - room);
625 if (!room)
626 return 0;
627
628 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
629
630 port->icount.rx += room;
631
632 return room;
633}
634
635static void pch_free_dma(struct uart_port *port)
636{
637 struct eg20t_port *priv;
638 priv = container_of(port, struct eg20t_port, port);
639
640 if (priv->chan_tx) {
641 dma_release_channel(priv->chan_tx);
642 priv->chan_tx = NULL;
643 }
644 if (priv->chan_rx) {
645 dma_release_channel(priv->chan_rx);
646 priv->chan_rx = NULL;
647 }
648
649 if (priv->rx_buf_dma) {
650 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
651 priv->rx_buf_dma);
652 priv->rx_buf_virt = NULL;
653 priv->rx_buf_dma = 0;
654 }
655
656 return;
657}
658
659static bool filter(struct dma_chan *chan, void *slave)
660{
661 struct pch_dma_slave *param = slave;
662
663 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
664 chan->device->dev)) {
665 chan->private = param;
666 return true;
667 } else {
668 return false;
669 }
670}
671
672static void pch_request_dma(struct uart_port *port)
673{
674 dma_cap_mask_t mask;
675 struct dma_chan *chan;
676 struct pci_dev *dma_dev;
677 struct pch_dma_slave *param;
678 struct eg20t_port *priv =
679 container_of(port, struct eg20t_port, port);
680 dma_cap_zero(mask);
681 dma_cap_set(DMA_SLAVE, mask);
682
683 /* Get DMA's dev information */
684 dma_dev = pci_get_slot(priv->pdev->bus,
685 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
686
687 /* Set Tx DMA */
688 param = &priv->param_tx;
689 param->dma_dev = &dma_dev->dev;
690 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
691
692 param->tx_reg = port->mapbase + UART_TX;
693 chan = dma_request_channel(mask, filter, param);
694 if (!chan) {
695 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
696 __func__);
697 pci_dev_put(dma_dev);
698 return;
699 }
700 priv->chan_tx = chan;
701
702 /* Set Rx DMA */
703 param = &priv->param_rx;
704 param->dma_dev = &dma_dev->dev;
705 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
706
707 param->rx_reg = port->mapbase + UART_RX;
708 chan = dma_request_channel(mask, filter, param);
709 if (!chan) {
710 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
711 __func__);
712 dma_release_channel(priv->chan_tx);
713 priv->chan_tx = NULL;
714 pci_dev_put(dma_dev);
715 return;
716 }
717
718 /* Get Consistent memory for DMA */
719 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
720 &priv->rx_buf_dma, GFP_KERNEL);
721 priv->chan_rx = chan;
722
723 pci_dev_put(dma_dev);
724}
725
726static void pch_dma_rx_complete(void *arg)
727{
728 struct eg20t_port *priv = arg;
729 struct uart_port *port = &priv->port;
730 int count;
731
732 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
733 count = dma_push_rx(priv, priv->trigger_level);
734 if (count)
735 tty_flip_buffer_push(&port->state->port);
736 async_tx_ack(priv->desc_rx);
737 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
738 PCH_UART_HAL_RX_ERR_INT);
739}
740
741static void pch_dma_tx_complete(void *arg)
742{
743 struct eg20t_port *priv = arg;
744 struct uart_port *port = &priv->port;
745 struct scatterlist *sg = priv->sg_tx_p;
746 int i;
747
748 for (i = 0; i < priv->nent; i++, sg++)
749 uart_xmit_advance(port, sg_dma_len(sg));
750
751 async_tx_ack(priv->desc_tx);
752 dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE);
753 priv->tx_dma_use = 0;
754 priv->nent = 0;
755 priv->orig_nent = 0;
756 kfree(priv->sg_tx_p);
757 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
758}
759
760static int handle_rx_to(struct eg20t_port *priv)
761{
762 struct pch_uart_buffer *buf;
763 int rx_size;
764 int ret;
765 if (!priv->start_rx) {
766 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
767 PCH_UART_HAL_RX_ERR_INT);
768 return 0;
769 }
770 buf = &priv->rxbuf;
771 do {
772 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
773 ret = push_rx(priv, buf->buf, rx_size);
774 if (ret)
775 return 0;
776 } while (rx_size == buf->size);
777
778 return PCH_UART_HANDLED_RX_INT;
779}
780
781static int handle_rx(struct eg20t_port *priv)
782{
783 return handle_rx_to(priv);
784}
785
786static int dma_handle_rx(struct eg20t_port *priv)
787{
788 struct uart_port *port = &priv->port;
789 struct dma_async_tx_descriptor *desc;
790 struct scatterlist *sg;
791
792 priv = container_of(port, struct eg20t_port, port);
793 sg = &priv->sg_rx;
794
795 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
796
797 sg_dma_len(sg) = priv->trigger_level;
798
799 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
800 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
801
802 sg_dma_address(sg) = priv->rx_buf_dma;
803
804 desc = dmaengine_prep_slave_sg(priv->chan_rx,
805 sg, 1, DMA_DEV_TO_MEM,
806 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
807
808 if (!desc)
809 return 0;
810
811 priv->desc_rx = desc;
812 desc->callback = pch_dma_rx_complete;
813 desc->callback_param = priv;
814 desc->tx_submit(desc);
815 dma_async_issue_pending(priv->chan_rx);
816
817 return PCH_UART_HANDLED_RX_INT;
818}
819
820static unsigned int handle_tx(struct eg20t_port *priv)
821{
822 struct uart_port *port = &priv->port;
823 struct circ_buf *xmit = &port->state->xmit;
824 int fifo_size;
825 int tx_empty;
826
827 if (!priv->start_tx) {
828 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
829 __func__, jiffies);
830 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
831 priv->tx_empty = 1;
832 return 0;
833 }
834
835 fifo_size = max(priv->fifo_size, 1);
836 tx_empty = 1;
837 if (port->x_char) {
838 iowrite8(port->x_char, priv->membase + PCH_UART_THR);
839 port->icount.tx++;
840 port->x_char = 0;
841 tx_empty = 0;
842 fifo_size--;
843 }
844
845 while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) {
846 iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR);
847 uart_xmit_advance(port, 1);
848 fifo_size--;
849 tx_empty = 0;
850 }
851
852 priv->tx_empty = tx_empty;
853
854 if (tx_empty) {
855 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
856 uart_write_wakeup(port);
857 }
858
859 return PCH_UART_HANDLED_TX_INT;
860}
861
862static unsigned int dma_handle_tx(struct eg20t_port *priv)
863{
864 struct uart_port *port = &priv->port;
865 struct circ_buf *xmit = &port->state->xmit;
866 struct scatterlist *sg;
867 int nent;
868 int fifo_size;
869 struct dma_async_tx_descriptor *desc;
870 int num;
871 int i;
872 int bytes;
873 int size;
874 int rem;
875
876 if (!priv->start_tx) {
877 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
878 __func__, jiffies);
879 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
880 priv->tx_empty = 1;
881 return 0;
882 }
883
884 if (priv->tx_dma_use) {
885 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
886 __func__, jiffies);
887 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
888 priv->tx_empty = 1;
889 return 0;
890 }
891
892 fifo_size = max(priv->fifo_size, 1);
893
894 if (port->x_char) {
895 iowrite8(port->x_char, priv->membase + PCH_UART_THR);
896 port->icount.tx++;
897 port->x_char = 0;
898 fifo_size--;
899 }
900
901 bytes = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
902 if (!bytes) {
903 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
904 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
905 uart_write_wakeup(port);
906 return 0;
907 }
908
909 if (bytes > fifo_size) {
910 num = bytes / fifo_size + 1;
911 size = fifo_size;
912 rem = bytes % fifo_size;
913 } else {
914 num = 1;
915 size = bytes;
916 rem = bytes;
917 }
918
919 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
920 __func__, num, size, rem);
921
922 priv->tx_dma_use = 1;
923
924 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);
925 if (!priv->sg_tx_p) {
926 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
927 return 0;
928 }
929
930 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
931 sg = priv->sg_tx_p;
932
933 for (i = 0; i < num; i++, sg++) {
934 if (i == (num - 1))
935 sg_set_page(sg, virt_to_page(xmit->buf),
936 rem, fifo_size * i);
937 else
938 sg_set_page(sg, virt_to_page(xmit->buf),
939 size, fifo_size * i);
940 }
941
942 sg = priv->sg_tx_p;
943 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
944 if (!nent) {
945 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
946 return 0;
947 }
948 priv->orig_nent = num;
949 priv->nent = nent;
950
951 for (i = 0; i < nent; i++, sg++) {
952 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
953 fifo_size * i;
954 sg_dma_address(sg) = (sg_dma_address(sg) &
955 ~(UART_XMIT_SIZE - 1)) + sg->offset;
956 if (i == (nent - 1))
957 sg_dma_len(sg) = rem;
958 else
959 sg_dma_len(sg) = size;
960 }
961
962 desc = dmaengine_prep_slave_sg(priv->chan_tx,
963 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
964 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
965 if (!desc) {
966 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
967 __func__);
968 return 0;
969 }
970 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
971 priv->desc_tx = desc;
972 desc->callback = pch_dma_tx_complete;
973 desc->callback_param = priv;
974
975 desc->tx_submit(desc);
976
977 dma_async_issue_pending(priv->chan_tx);
978
979 return PCH_UART_HANDLED_TX_INT;
980}
981
982static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
983{
984 struct uart_port *port = &priv->port;
985 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
986 char *error_msg[5] = {};
987 int i = 0;
988
989 if (lsr & PCH_UART_LSR_ERR)
990 error_msg[i++] = "Error data in FIFO\n";
991
992 if (lsr & UART_LSR_FE) {
993 port->icount.frame++;
994 error_msg[i++] = " Framing Error\n";
995 }
996
997 if (lsr & UART_LSR_PE) {
998 port->icount.parity++;
999 error_msg[i++] = " Parity Error\n";
1000 }
1001
1002 if (lsr & UART_LSR_OE) {
1003 port->icount.overrun++;
1004 error_msg[i++] = " Overrun Error\n";
1005 }
1006
1007 if (tty == NULL) {
1008 for (i = 0; error_msg[i] != NULL; i++)
1009 dev_err(&priv->pdev->dev, error_msg[i]);
1010 } else {
1011 tty_kref_put(tty);
1012 }
1013}
1014
1015static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1016{
1017 struct eg20t_port *priv = dev_id;
1018 unsigned int handled;
1019 u8 lsr;
1020 int ret = 0;
1021 unsigned char iid;
1022 unsigned long flags;
1023 int next = 1;
1024 u8 msr;
1025
1026 spin_lock_irqsave(&priv->lock, flags);
1027 handled = 0;
1028 while (next) {
1029 iid = pch_uart_hal_get_iid(priv);
1030 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1031 break;
1032 switch (iid) {
1033 case PCH_UART_IID_RLS: /* Receiver Line Status */
1034 lsr = pch_uart_hal_get_line_status(priv);
1035 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1036 UART_LSR_PE | UART_LSR_OE)) {
1037 pch_uart_err_ir(priv, lsr);
1038 ret = PCH_UART_HANDLED_RX_ERR_INT;
1039 } else {
1040 ret = PCH_UART_HANDLED_LS_INT;
1041 }
1042 break;
1043 case PCH_UART_IID_RDR: /* Received Data Ready */
1044 if (priv->use_dma) {
1045 pch_uart_hal_disable_interrupt(priv,
1046 PCH_UART_HAL_RX_INT |
1047 PCH_UART_HAL_RX_ERR_INT);
1048 ret = dma_handle_rx(priv);
1049 if (!ret)
1050 pch_uart_hal_enable_interrupt(priv,
1051 PCH_UART_HAL_RX_INT |
1052 PCH_UART_HAL_RX_ERR_INT);
1053 } else {
1054 ret = handle_rx(priv);
1055 }
1056 break;
1057 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1058 (FIFO Timeout) */
1059 ret = handle_rx_to(priv);
1060 break;
1061 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1062 Empty */
1063 if (priv->use_dma)
1064 ret = dma_handle_tx(priv);
1065 else
1066 ret = handle_tx(priv);
1067 break;
1068 case PCH_UART_IID_MS: /* Modem Status */
1069 msr = pch_uart_hal_get_modem(priv);
1070 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1071 means final interrupt */
1072 if ((msr & UART_MSR_ANY_DELTA) == 0)
1073 break;
1074 ret |= PCH_UART_HANDLED_MS_INT;
1075 break;
1076 default: /* Never junp to this label */
1077 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1078 iid, jiffies);
1079 ret = -1;
1080 next = 0;
1081 break;
1082 }
1083 handled |= (unsigned int)ret;
1084 }
1085
1086 spin_unlock_irqrestore(&priv->lock, flags);
1087 return IRQ_RETVAL(handled);
1088}
1089
1090/* This function tests whether the transmitter fifo and shifter for the port
1091 described by 'port' is empty. */
1092static unsigned int pch_uart_tx_empty(struct uart_port *port)
1093{
1094 struct eg20t_port *priv;
1095
1096 priv = container_of(port, struct eg20t_port, port);
1097 if (priv->tx_empty)
1098 return TIOCSER_TEMT;
1099 else
1100 return 0;
1101}
1102
1103/* Returns the current state of modem control inputs. */
1104static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1105{
1106 struct eg20t_port *priv;
1107 u8 modem;
1108 unsigned int ret = 0;
1109
1110 priv = container_of(port, struct eg20t_port, port);
1111 modem = pch_uart_hal_get_modem(priv);
1112
1113 if (modem & UART_MSR_DCD)
1114 ret |= TIOCM_CAR;
1115
1116 if (modem & UART_MSR_RI)
1117 ret |= TIOCM_RNG;
1118
1119 if (modem & UART_MSR_DSR)
1120 ret |= TIOCM_DSR;
1121
1122 if (modem & UART_MSR_CTS)
1123 ret |= TIOCM_CTS;
1124
1125 return ret;
1126}
1127
1128static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1129{
1130 u32 mcr = 0;
1131 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1132
1133 if (mctrl & TIOCM_DTR)
1134 mcr |= UART_MCR_DTR;
1135 if (mctrl & TIOCM_RTS)
1136 mcr |= UART_MCR_RTS;
1137 if (mctrl & TIOCM_LOOP)
1138 mcr |= UART_MCR_LOOP;
1139
1140 if (priv->mcr & UART_MCR_AFE)
1141 mcr |= UART_MCR_AFE;
1142
1143 if (mctrl)
1144 iowrite8(mcr, priv->membase + UART_MCR);
1145}
1146
1147static void pch_uart_stop_tx(struct uart_port *port)
1148{
1149 struct eg20t_port *priv;
1150 priv = container_of(port, struct eg20t_port, port);
1151 priv->start_tx = 0;
1152 priv->tx_dma_use = 0;
1153}
1154
1155static void pch_uart_start_tx(struct uart_port *port)
1156{
1157 struct eg20t_port *priv;
1158
1159 priv = container_of(port, struct eg20t_port, port);
1160
1161 if (priv->use_dma) {
1162 if (priv->tx_dma_use) {
1163 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1164 __func__);
1165 return;
1166 }
1167 }
1168
1169 priv->start_tx = 1;
1170 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1171}
1172
1173static void pch_uart_stop_rx(struct uart_port *port)
1174{
1175 struct eg20t_port *priv;
1176 priv = container_of(port, struct eg20t_port, port);
1177 priv->start_rx = 0;
1178 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1179 PCH_UART_HAL_RX_ERR_INT);
1180}
1181
1182/* Enable the modem status interrupts. */
1183static void pch_uart_enable_ms(struct uart_port *port)
1184{
1185 struct eg20t_port *priv;
1186 priv = container_of(port, struct eg20t_port, port);
1187 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1188}
1189
1190/* Control the transmission of a break signal. */
1191static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1192{
1193 struct eg20t_port *priv;
1194 unsigned long flags;
1195
1196 priv = container_of(port, struct eg20t_port, port);
1197 spin_lock_irqsave(&priv->lock, flags);
1198 pch_uart_hal_set_break(priv, ctl);
1199 spin_unlock_irqrestore(&priv->lock, flags);
1200}
1201
1202/* Grab any interrupt resources and initialise any low level driver state. */
1203static int pch_uart_startup(struct uart_port *port)
1204{
1205 struct eg20t_port *priv;
1206 int ret;
1207 int fifo_size;
1208 int trigger_level;
1209
1210 priv = container_of(port, struct eg20t_port, port);
1211 priv->tx_empty = 1;
1212
1213 if (port->uartclk)
1214 priv->uartclk = port->uartclk;
1215 else
1216 port->uartclk = priv->uartclk;
1217
1218 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1219 ret = pch_uart_hal_set_line(priv, default_baud,
1220 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1221 PCH_UART_HAL_STB1);
1222 if (ret)
1223 return ret;
1224
1225 switch (priv->fifo_size) {
1226 case 256:
1227 fifo_size = PCH_UART_HAL_FIFO256;
1228 break;
1229 case 64:
1230 fifo_size = PCH_UART_HAL_FIFO64;
1231 break;
1232 case 16:
1233 fifo_size = PCH_UART_HAL_FIFO16;
1234 break;
1235 case 1:
1236 default:
1237 fifo_size = PCH_UART_HAL_FIFO_DIS;
1238 break;
1239 }
1240
1241 switch (priv->trigger) {
1242 case PCH_UART_HAL_TRIGGER1:
1243 trigger_level = 1;
1244 break;
1245 case PCH_UART_HAL_TRIGGER_L:
1246 trigger_level = priv->fifo_size / 4;
1247 break;
1248 case PCH_UART_HAL_TRIGGER_M:
1249 trigger_level = priv->fifo_size / 2;
1250 break;
1251 case PCH_UART_HAL_TRIGGER_H:
1252 default:
1253 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1254 break;
1255 }
1256
1257 priv->trigger_level = trigger_level;
1258 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1259 fifo_size, priv->trigger);
1260 if (ret < 0)
1261 return ret;
1262
1263 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1264 priv->irq_name, priv);
1265 if (ret < 0)
1266 return ret;
1267
1268 if (priv->use_dma)
1269 pch_request_dma(port);
1270
1271 priv->start_rx = 1;
1272 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1273 PCH_UART_HAL_RX_ERR_INT);
1274 uart_update_timeout(port, CS8, default_baud);
1275
1276 return 0;
1277}
1278
1279static void pch_uart_shutdown(struct uart_port *port)
1280{
1281 struct eg20t_port *priv;
1282 int ret;
1283
1284 priv = container_of(port, struct eg20t_port, port);
1285 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1286 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1287 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1288 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1289 if (ret)
1290 dev_err(priv->port.dev,
1291 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1292
1293 pch_free_dma(port);
1294
1295 free_irq(priv->port.irq, priv);
1296}
1297
1298/* Change the port parameters, including word length, parity, stop
1299 *bits. Update read_status_mask and ignore_status_mask to indicate
1300 *the types of events we are interested in receiving. */
1301static void pch_uart_set_termios(struct uart_port *port,
1302 struct ktermios *termios,
1303 const struct ktermios *old)
1304{
1305 int rtn;
1306 unsigned int baud, parity, bits, stb;
1307 struct eg20t_port *priv;
1308 unsigned long flags;
1309
1310 priv = container_of(port, struct eg20t_port, port);
1311 switch (termios->c_cflag & CSIZE) {
1312 case CS5:
1313 bits = PCH_UART_HAL_5BIT;
1314 break;
1315 case CS6:
1316 bits = PCH_UART_HAL_6BIT;
1317 break;
1318 case CS7:
1319 bits = PCH_UART_HAL_7BIT;
1320 break;
1321 default: /* CS8 */
1322 bits = PCH_UART_HAL_8BIT;
1323 break;
1324 }
1325 if (termios->c_cflag & CSTOPB)
1326 stb = PCH_UART_HAL_STB2;
1327 else
1328 stb = PCH_UART_HAL_STB1;
1329
1330 if (termios->c_cflag & PARENB) {
1331 if (termios->c_cflag & PARODD)
1332 parity = PCH_UART_HAL_PARITY_ODD;
1333 else
1334 parity = PCH_UART_HAL_PARITY_EVEN;
1335
1336 } else
1337 parity = PCH_UART_HAL_PARITY_NONE;
1338
1339 /* Only UART0 has auto hardware flow function */
1340 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1341 priv->mcr |= UART_MCR_AFE;
1342 else
1343 priv->mcr &= ~UART_MCR_AFE;
1344
1345 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1346
1347 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1348
1349 spin_lock_irqsave(&priv->lock, flags);
1350 uart_port_lock(port);
1351
1352 uart_update_timeout(port, termios->c_cflag, baud);
1353 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1354 if (rtn)
1355 goto out;
1356
1357 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1358 /* Don't rewrite B0 */
1359 if (tty_termios_baud_rate(termios))
1360 tty_termios_encode_baud_rate(termios, baud, baud);
1361
1362out:
1363 uart_port_unlock(port);
1364 spin_unlock_irqrestore(&priv->lock, flags);
1365}
1366
1367static const char *pch_uart_type(struct uart_port *port)
1368{
1369 return KBUILD_MODNAME;
1370}
1371
1372static void pch_uart_release_port(struct uart_port *port)
1373{
1374 struct eg20t_port *priv;
1375
1376 priv = container_of(port, struct eg20t_port, port);
1377 pci_iounmap(priv->pdev, priv->membase);
1378 pci_release_regions(priv->pdev);
1379}
1380
1381static int pch_uart_request_port(struct uart_port *port)
1382{
1383 struct eg20t_port *priv;
1384 int ret;
1385 void __iomem *membase;
1386
1387 priv = container_of(port, struct eg20t_port, port);
1388 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1389 if (ret < 0)
1390 return -EBUSY;
1391
1392 membase = pci_iomap(priv->pdev, 1, 0);
1393 if (!membase) {
1394 pci_release_regions(priv->pdev);
1395 return -EBUSY;
1396 }
1397 priv->membase = port->membase = membase;
1398
1399 return 0;
1400}
1401
1402static void pch_uart_config_port(struct uart_port *port, int type)
1403{
1404 struct eg20t_port *priv;
1405
1406 priv = container_of(port, struct eg20t_port, port);
1407 if (type & UART_CONFIG_TYPE) {
1408 port->type = priv->port_type;
1409 pch_uart_request_port(port);
1410 }
1411}
1412
1413static int pch_uart_verify_port(struct uart_port *port,
1414 struct serial_struct *serinfo)
1415{
1416 struct eg20t_port *priv;
1417
1418 priv = container_of(port, struct eg20t_port, port);
1419 if (serinfo->flags & UPF_LOW_LATENCY) {
1420 dev_info(priv->port.dev,
1421 "PCH UART : Use PIO Mode (without DMA)\n");
1422 priv->use_dma = 0;
1423 serinfo->flags &= ~UPF_LOW_LATENCY;
1424 } else {
1425#ifndef CONFIG_PCH_DMA
1426 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1427 __func__);
1428 return -EOPNOTSUPP;
1429#endif
1430 if (!priv->use_dma) {
1431 pch_request_dma(port);
1432 if (priv->chan_rx)
1433 priv->use_dma = 1;
1434 }
1435 dev_info(priv->port.dev, "PCH UART: %s\n",
1436 priv->use_dma ?
1437 "Use DMA Mode" : "No DMA");
1438 }
1439
1440 return 0;
1441}
1442
1443#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1444/*
1445 * Wait for transmitter & holding register to empty
1446 */
1447static void wait_for_xmitr(struct eg20t_port *up, int bits)
1448{
1449 unsigned int status, tmout = 10000;
1450
1451 /* Wait up to 10ms for the character(s) to be sent. */
1452 for (;;) {
1453 status = ioread8(up->membase + UART_LSR);
1454
1455 if ((status & bits) == bits)
1456 break;
1457 if (--tmout == 0)
1458 break;
1459 udelay(1);
1460 }
1461
1462 /* Wait up to 1s for flow control if necessary */
1463 if (up->port.flags & UPF_CONS_FLOW) {
1464 unsigned int tmout;
1465 for (tmout = 1000000; tmout; tmout--) {
1466 unsigned int msr = ioread8(up->membase + UART_MSR);
1467 if (msr & UART_MSR_CTS)
1468 break;
1469 udelay(1);
1470 touch_nmi_watchdog();
1471 }
1472 }
1473}
1474#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1475
1476#ifdef CONFIG_CONSOLE_POLL
1477/*
1478 * Console polling routines for communicate via uart while
1479 * in an interrupt or debug context.
1480 */
1481static int pch_uart_get_poll_char(struct uart_port *port)
1482{
1483 struct eg20t_port *priv =
1484 container_of(port, struct eg20t_port, port);
1485 u8 lsr = ioread8(priv->membase + UART_LSR);
1486
1487 if (!(lsr & UART_LSR_DR))
1488 return NO_POLL_CHAR;
1489
1490 return ioread8(priv->membase + PCH_UART_RBR);
1491}
1492
1493
1494static void pch_uart_put_poll_char(struct uart_port *port,
1495 unsigned char c)
1496{
1497 unsigned int ier;
1498 struct eg20t_port *priv =
1499 container_of(port, struct eg20t_port, port);
1500
1501 /*
1502 * First save the IER then disable the interrupts
1503 */
1504 ier = ioread8(priv->membase + UART_IER);
1505 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1506
1507 wait_for_xmitr(priv, UART_LSR_THRE);
1508 /*
1509 * Send the character out.
1510 */
1511 iowrite8(c, priv->membase + PCH_UART_THR);
1512
1513 /*
1514 * Finally, wait for transmitter to become empty
1515 * and restore the IER
1516 */
1517 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);
1518 iowrite8(ier, priv->membase + UART_IER);
1519}
1520#endif /* CONFIG_CONSOLE_POLL */
1521
1522static const struct uart_ops pch_uart_ops = {
1523 .tx_empty = pch_uart_tx_empty,
1524 .set_mctrl = pch_uart_set_mctrl,
1525 .get_mctrl = pch_uart_get_mctrl,
1526 .stop_tx = pch_uart_stop_tx,
1527 .start_tx = pch_uart_start_tx,
1528 .stop_rx = pch_uart_stop_rx,
1529 .enable_ms = pch_uart_enable_ms,
1530 .break_ctl = pch_uart_break_ctl,
1531 .startup = pch_uart_startup,
1532 .shutdown = pch_uart_shutdown,
1533 .set_termios = pch_uart_set_termios,
1534/* .pm = pch_uart_pm, Not supported yet */
1535 .type = pch_uart_type,
1536 .release_port = pch_uart_release_port,
1537 .request_port = pch_uart_request_port,
1538 .config_port = pch_uart_config_port,
1539 .verify_port = pch_uart_verify_port,
1540#ifdef CONFIG_CONSOLE_POLL
1541 .poll_get_char = pch_uart_get_poll_char,
1542 .poll_put_char = pch_uart_put_poll_char,
1543#endif
1544};
1545
1546#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1547
1548static void pch_console_putchar(struct uart_port *port, unsigned char ch)
1549{
1550 struct eg20t_port *priv =
1551 container_of(port, struct eg20t_port, port);
1552
1553 wait_for_xmitr(priv, UART_LSR_THRE);
1554 iowrite8(ch, priv->membase + PCH_UART_THR);
1555}
1556
1557/*
1558 * Print a string to the serial port trying not to disturb
1559 * any possible real use of the port...
1560 *
1561 * The console_lock must be held when we get here.
1562 */
1563static void
1564pch_console_write(struct console *co, const char *s, unsigned int count)
1565{
1566 struct eg20t_port *priv;
1567 unsigned long flags;
1568 int priv_locked = 1;
1569 int port_locked = 1;
1570 u8 ier;
1571
1572 priv = pch_uart_ports[co->index];
1573
1574 touch_nmi_watchdog();
1575
1576 local_irq_save(flags);
1577 if (priv->port.sysrq) {
1578 /* call to uart_handle_sysrq_char already took the priv lock */
1579 priv_locked = 0;
1580 /* serial8250_handle_port() already took the port lock */
1581 port_locked = 0;
1582 } else if (oops_in_progress) {
1583 priv_locked = spin_trylock(&priv->lock);
1584 port_locked = uart_port_trylock(&priv->port);
1585 } else {
1586 spin_lock(&priv->lock);
1587 uart_port_lock(&priv->port);
1588 }
1589
1590 /*
1591 * First save the IER then disable the interrupts
1592 */
1593 ier = ioread8(priv->membase + UART_IER);
1594
1595 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1596
1597 uart_console_write(&priv->port, s, count, pch_console_putchar);
1598
1599 /*
1600 * Finally, wait for transmitter to become empty
1601 * and restore the IER
1602 */
1603 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);
1604 iowrite8(ier, priv->membase + UART_IER);
1605
1606 if (port_locked)
1607 uart_port_unlock(&priv->port);
1608 if (priv_locked)
1609 spin_unlock(&priv->lock);
1610 local_irq_restore(flags);
1611}
1612
1613static int __init pch_console_setup(struct console *co, char *options)
1614{
1615 struct uart_port *port;
1616 int baud = default_baud;
1617 int bits = 8;
1618 int parity = 'n';
1619 int flow = 'n';
1620
1621 /*
1622 * Check whether an invalid uart number has been specified, and
1623 * if so, search for the first available port that does have
1624 * console support.
1625 */
1626 if (co->index >= PCH_UART_NR)
1627 co->index = 0;
1628 port = &pch_uart_ports[co->index]->port;
1629
1630 if (!port || (!port->iobase && !port->membase))
1631 return -ENODEV;
1632
1633 port->uartclk = pch_uart_get_uartclk();
1634
1635 if (options)
1636 uart_parse_options(options, &baud, &parity, &bits, &flow);
1637
1638 return uart_set_options(port, co, baud, parity, bits, flow);
1639}
1640
1641static struct uart_driver pch_uart_driver;
1642
1643static struct console pch_console = {
1644 .name = PCH_UART_DRIVER_DEVICE,
1645 .write = pch_console_write,
1646 .device = uart_console_device,
1647 .setup = pch_console_setup,
1648 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1649 .index = -1,
1650 .data = &pch_uart_driver,
1651};
1652
1653#define PCH_CONSOLE (&pch_console)
1654#else
1655#define PCH_CONSOLE NULL
1656#endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1657
1658static struct uart_driver pch_uart_driver = {
1659 .owner = THIS_MODULE,
1660 .driver_name = KBUILD_MODNAME,
1661 .dev_name = PCH_UART_DRIVER_DEVICE,
1662 .major = 0,
1663 .minor = 0,
1664 .nr = PCH_UART_NR,
1665 .cons = PCH_CONSOLE,
1666};
1667
1668static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1669 const struct pci_device_id *id)
1670{
1671 struct eg20t_port *priv;
1672 int ret;
1673 unsigned int iobase;
1674 unsigned int mapbase;
1675 unsigned char *rxbuf;
1676 int fifosize;
1677 int port_type;
1678 struct pch_uart_driver_data *board;
1679 char name[32];
1680
1681 board = &drv_dat[id->driver_data];
1682 port_type = board->port_type;
1683
1684 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1685 if (priv == NULL)
1686 goto init_port_alloc_err;
1687
1688 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1689 if (!rxbuf)
1690 goto init_port_free_txbuf;
1691
1692 switch (port_type) {
1693 case PORT_PCH_8LINE:
1694 fifosize = 256; /* EG20T/ML7213: UART0 */
1695 break;
1696 case PORT_PCH_2LINE:
1697 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1698 break;
1699 default:
1700 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1701 goto init_port_hal_free;
1702 }
1703
1704 pci_enable_msi(pdev);
1705 pci_set_master(pdev);
1706
1707 spin_lock_init(&priv->lock);
1708
1709 iobase = pci_resource_start(pdev, 0);
1710 mapbase = pci_resource_start(pdev, 1);
1711 priv->mapbase = mapbase;
1712 priv->iobase = iobase;
1713 priv->pdev = pdev;
1714 priv->tx_empty = 1;
1715 priv->rxbuf.buf = rxbuf;
1716 priv->rxbuf.size = PAGE_SIZE;
1717
1718 priv->fifo_size = fifosize;
1719 priv->uartclk = pch_uart_get_uartclk();
1720 priv->port_type = port_type;
1721 priv->port.dev = &pdev->dev;
1722 priv->port.iobase = iobase;
1723 priv->port.membase = NULL;
1724 priv->port.mapbase = mapbase;
1725 priv->port.irq = pdev->irq;
1726 priv->port.iotype = UPIO_PORT;
1727 priv->port.ops = &pch_uart_ops;
1728 priv->port.flags = UPF_BOOT_AUTOCONF;
1729 priv->port.fifosize = fifosize;
1730 priv->port.line = board->line_no;
1731 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
1732 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1733
1734 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1735 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1736 priv->port.line);
1737
1738 spin_lock_init(&priv->port.lock);
1739
1740 pci_set_drvdata(pdev, priv);
1741 priv->trigger_level = 1;
1742 priv->fcr = 0;
1743
1744 if (pdev->dev.of_node)
1745 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1746 , &user_uartclk);
1747
1748#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1749 pch_uart_ports[board->line_no] = priv;
1750#endif
1751 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1752 if (ret < 0)
1753 goto init_port_hal_free;
1754
1755 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
1756 debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv,
1757 &port_regs_ops);
1758
1759 return priv;
1760
1761init_port_hal_free:
1762#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1763 pch_uart_ports[board->line_no] = NULL;
1764#endif
1765 free_page((unsigned long)rxbuf);
1766init_port_free_txbuf:
1767 kfree(priv);
1768init_port_alloc_err:
1769
1770 return NULL;
1771}
1772
1773static void pch_uart_exit_port(struct eg20t_port *priv)
1774{
1775 char name[32];
1776
1777 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
1778 debugfs_lookup_and_remove(name, NULL);
1779 uart_remove_one_port(&pch_uart_driver, &priv->port);
1780 free_page((unsigned long)priv->rxbuf.buf);
1781}
1782
1783static void pch_uart_pci_remove(struct pci_dev *pdev)
1784{
1785 struct eg20t_port *priv = pci_get_drvdata(pdev);
1786
1787 pci_disable_msi(pdev);
1788
1789#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1790 pch_uart_ports[priv->port.line] = NULL;
1791#endif
1792 pch_uart_exit_port(priv);
1793 pci_disable_device(pdev);
1794 kfree(priv);
1795 return;
1796}
1797
1798static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
1799{
1800 struct eg20t_port *priv = dev_get_drvdata(dev);
1801
1802 uart_suspend_port(&pch_uart_driver, &priv->port);
1803
1804 return 0;
1805}
1806
1807static int __maybe_unused pch_uart_pci_resume(struct device *dev)
1808{
1809 struct eg20t_port *priv = dev_get_drvdata(dev);
1810
1811 uart_resume_port(&pch_uart_driver, &priv->port);
1812
1813 return 0;
1814}
1815
1816static const struct pci_device_id pch_uart_pci_id[] = {
1817 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1818 .driver_data = pch_et20t_uart0},
1819 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1820 .driver_data = pch_et20t_uart1},
1821 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1822 .driver_data = pch_et20t_uart2},
1823 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1824 .driver_data = pch_et20t_uart3},
1825 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1826 .driver_data = pch_ml7213_uart0},
1827 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1828 .driver_data = pch_ml7213_uart1},
1829 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1830 .driver_data = pch_ml7213_uart2},
1831 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1832 .driver_data = pch_ml7223_uart0},
1833 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1834 .driver_data = pch_ml7223_uart1},
1835 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1836 .driver_data = pch_ml7831_uart0},
1837 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1838 .driver_data = pch_ml7831_uart1},
1839 {0,},
1840};
1841
1842static int pch_uart_pci_probe(struct pci_dev *pdev,
1843 const struct pci_device_id *id)
1844{
1845 int ret;
1846 struct eg20t_port *priv;
1847
1848 ret = pci_enable_device(pdev);
1849 if (ret < 0)
1850 goto probe_error;
1851
1852 priv = pch_uart_init_port(pdev, id);
1853 if (!priv) {
1854 ret = -EBUSY;
1855 goto probe_disable_device;
1856 }
1857 pci_set_drvdata(pdev, priv);
1858
1859 return ret;
1860
1861probe_disable_device:
1862 pci_disable_msi(pdev);
1863 pci_disable_device(pdev);
1864probe_error:
1865 return ret;
1866}
1867
1868static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
1869 pch_uart_pci_suspend,
1870 pch_uart_pci_resume);
1871
1872static struct pci_driver pch_uart_pci_driver = {
1873 .name = "pch_uart",
1874 .id_table = pch_uart_pci_id,
1875 .probe = pch_uart_pci_probe,
1876 .remove = pch_uart_pci_remove,
1877 .driver.pm = &pch_uart_pci_pm_ops,
1878};
1879
1880static int __init pch_uart_module_init(void)
1881{
1882 int ret;
1883
1884 /* register as UART driver */
1885 ret = uart_register_driver(&pch_uart_driver);
1886 if (ret < 0)
1887 return ret;
1888
1889 /* register as PCI driver */
1890 ret = pci_register_driver(&pch_uart_pci_driver);
1891 if (ret < 0)
1892 uart_unregister_driver(&pch_uart_driver);
1893
1894 return ret;
1895}
1896module_init(pch_uart_module_init);
1897
1898static void __exit pch_uart_module_exit(void)
1899{
1900 pci_unregister_driver(&pch_uart_pci_driver);
1901 uart_unregister_driver(&pch_uart_driver);
1902}
1903module_exit(pch_uart_module_exit);
1904
1905MODULE_LICENSE("GPL v2");
1906MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1907MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1908
1909module_param(default_baud, uint, S_IRUGO);
1910MODULE_PARM_DESC(default_baud,
1911 "Default BAUD for initial driver state and console (default 9600)");
1912module_param(user_uartclk, uint, S_IRUGO);
1913MODULE_PARM_DESC(user_uartclk,
1914 "Override UART default or board specific UART clock");
1/*
2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
20#include <linux/kernel.h>
21#include <linux/serial_reg.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/console.h>
26#include <linux/serial_core.h>
27#include <linux/tty.h>
28#include <linux/tty_flip.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/dmi.h>
32#include <linux/nmi.h>
33#include <linux/delay.h>
34#include <linux/of.h>
35
36#include <linux/debugfs.h>
37#include <linux/dmaengine.h>
38#include <linux/pch_dma.h>
39
40enum {
41 PCH_UART_HANDLED_RX_INT_SHIFT,
42 PCH_UART_HANDLED_TX_INT_SHIFT,
43 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
44 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
45 PCH_UART_HANDLED_MS_INT_SHIFT,
46 PCH_UART_HANDLED_LS_INT_SHIFT,
47};
48
49enum {
50 PCH_UART_8LINE,
51 PCH_UART_2LINE,
52};
53
54#define PCH_UART_DRIVER_DEVICE "ttyPCH"
55
56/* Set the max number of UART port
57 * Intel EG20T PCH: 4 port
58 * LAPIS Semiconductor ML7213 IOH: 3 port
59 * LAPIS Semiconductor ML7223 IOH: 2 port
60*/
61#define PCH_UART_NR 4
62
63#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
64#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
65#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
66 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
67#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
68 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
69#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
70
71#define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
72
73#define PCH_UART_RBR 0x00
74#define PCH_UART_THR 0x00
75
76#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
77 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
78#define PCH_UART_IER_ERBFI 0x00000001
79#define PCH_UART_IER_ETBEI 0x00000002
80#define PCH_UART_IER_ELSI 0x00000004
81#define PCH_UART_IER_EDSSI 0x00000008
82
83#define PCH_UART_IIR_IP 0x00000001
84#define PCH_UART_IIR_IID 0x00000006
85#define PCH_UART_IIR_MSI 0x00000000
86#define PCH_UART_IIR_TRI 0x00000002
87#define PCH_UART_IIR_RRI 0x00000004
88#define PCH_UART_IIR_REI 0x00000006
89#define PCH_UART_IIR_TOI 0x00000008
90#define PCH_UART_IIR_FIFO256 0x00000020
91#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
92#define PCH_UART_IIR_FE 0x000000C0
93
94#define PCH_UART_FCR_FIFOE 0x00000001
95#define PCH_UART_FCR_RFR 0x00000002
96#define PCH_UART_FCR_TFR 0x00000004
97#define PCH_UART_FCR_DMS 0x00000008
98#define PCH_UART_FCR_FIFO256 0x00000020
99#define PCH_UART_FCR_RFTL 0x000000C0
100
101#define PCH_UART_FCR_RFTL1 0x00000000
102#define PCH_UART_FCR_RFTL64 0x00000040
103#define PCH_UART_FCR_RFTL128 0x00000080
104#define PCH_UART_FCR_RFTL224 0x000000C0
105#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
106#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
107#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
108#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
109#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
110#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
111#define PCH_UART_FCR_RFTL_SHIFT 6
112
113#define PCH_UART_LCR_WLS 0x00000003
114#define PCH_UART_LCR_STB 0x00000004
115#define PCH_UART_LCR_PEN 0x00000008
116#define PCH_UART_LCR_EPS 0x00000010
117#define PCH_UART_LCR_SP 0x00000020
118#define PCH_UART_LCR_SB 0x00000040
119#define PCH_UART_LCR_DLAB 0x00000080
120#define PCH_UART_LCR_NP 0x00000000
121#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
122#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
123#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
124#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
125 PCH_UART_LCR_SP)
126
127#define PCH_UART_LCR_5BIT 0x00000000
128#define PCH_UART_LCR_6BIT 0x00000001
129#define PCH_UART_LCR_7BIT 0x00000002
130#define PCH_UART_LCR_8BIT 0x00000003
131
132#define PCH_UART_MCR_DTR 0x00000001
133#define PCH_UART_MCR_RTS 0x00000002
134#define PCH_UART_MCR_OUT 0x0000000C
135#define PCH_UART_MCR_LOOP 0x00000010
136#define PCH_UART_MCR_AFE 0x00000020
137
138#define PCH_UART_LSR_DR 0x00000001
139#define PCH_UART_LSR_ERR (1<<7)
140
141#define PCH_UART_MSR_DCTS 0x00000001
142#define PCH_UART_MSR_DDSR 0x00000002
143#define PCH_UART_MSR_TERI 0x00000004
144#define PCH_UART_MSR_DDCD 0x00000008
145#define PCH_UART_MSR_CTS 0x00000010
146#define PCH_UART_MSR_DSR 0x00000020
147#define PCH_UART_MSR_RI 0x00000040
148#define PCH_UART_MSR_DCD 0x00000080
149#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
150 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
151
152#define PCH_UART_DLL 0x00
153#define PCH_UART_DLM 0x01
154
155#define PCH_UART_BRCSR 0x0E
156
157#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
158#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
159#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
160#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
161#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
162
163#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
164#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
165#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
166#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
167#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
168#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
169#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
170#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
171#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
172#define PCH_UART_HAL_STB1 0
173#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
174
175#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
176#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
177#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
178 PCH_UART_HAL_CLR_RX_FIFO)
179
180#define PCH_UART_HAL_DMA_MODE0 0
181#define PCH_UART_HAL_FIFO_DIS 0
182#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
183#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
184 PCH_UART_FCR_FIFO256)
185#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
186#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
187#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
188#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
189#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
190#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
191#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
192#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
193#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
194#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
195#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
196#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
197#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
198#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
199
200#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
201#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
202#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
203#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
204#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
205
206#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
207#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
208#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
209#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
210#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
211
212#define PCI_VENDOR_ID_ROHM 0x10DB
213
214#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
215
216#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
217#define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
218#define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
219#define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
220#define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
221#define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
222
223struct pch_uart_buffer {
224 unsigned char *buf;
225 int size;
226};
227
228struct eg20t_port {
229 struct uart_port port;
230 int port_type;
231 void __iomem *membase;
232 resource_size_t mapbase;
233 unsigned int iobase;
234 struct pci_dev *pdev;
235 int fifo_size;
236 unsigned int uartclk;
237 int start_tx;
238 int start_rx;
239 int tx_empty;
240 int trigger;
241 int trigger_level;
242 struct pch_uart_buffer rxbuf;
243 unsigned int dmsr;
244 unsigned int fcr;
245 unsigned int mcr;
246 unsigned int use_dma;
247 struct dma_async_tx_descriptor *desc_tx;
248 struct dma_async_tx_descriptor *desc_rx;
249 struct pch_dma_slave param_tx;
250 struct pch_dma_slave param_rx;
251 struct dma_chan *chan_tx;
252 struct dma_chan *chan_rx;
253 struct scatterlist *sg_tx_p;
254 int nent;
255 struct scatterlist sg_rx;
256 int tx_dma_use;
257 void *rx_buf_virt;
258 dma_addr_t rx_buf_dma;
259
260 struct dentry *debugfs;
261#define IRQ_NAME_SIZE 17
262 char irq_name[IRQ_NAME_SIZE];
263
264 /* protect the eg20t_port private structure and io access to membase */
265 spinlock_t lock;
266};
267
268/**
269 * struct pch_uart_driver_data - private data structure for UART-DMA
270 * @port_type: The number of DMA channel
271 * @line_no: UART port line number (0, 1, 2...)
272 */
273struct pch_uart_driver_data {
274 int port_type;
275 int line_no;
276};
277
278enum pch_uart_num_t {
279 pch_et20t_uart0 = 0,
280 pch_et20t_uart1,
281 pch_et20t_uart2,
282 pch_et20t_uart3,
283 pch_ml7213_uart0,
284 pch_ml7213_uart1,
285 pch_ml7213_uart2,
286 pch_ml7223_uart0,
287 pch_ml7223_uart1,
288 pch_ml7831_uart0,
289 pch_ml7831_uart1,
290};
291
292static struct pch_uart_driver_data drv_dat[] = {
293 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
294 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
295 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
296 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
297 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
298 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
299 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
300 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
301 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
302 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
303 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
304};
305
306#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
307static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
308#endif
309static unsigned int default_baud = 9600;
310static unsigned int user_uartclk = 0;
311static const int trigger_level_256[4] = { 1, 64, 128, 224 };
312static const int trigger_level_64[4] = { 1, 16, 32, 56 };
313static const int trigger_level_16[4] = { 1, 4, 8, 14 };
314static const int trigger_level_1[4] = { 1, 1, 1, 1 };
315
316#ifdef CONFIG_DEBUG_FS
317
318#define PCH_REGS_BUFSIZE 1024
319
320
321static ssize_t port_show_regs(struct file *file, char __user *user_buf,
322 size_t count, loff_t *ppos)
323{
324 struct eg20t_port *priv = file->private_data;
325 char *buf;
326 u32 len = 0;
327 ssize_t ret;
328 unsigned char lcr;
329
330 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
331 if (!buf)
332 return 0;
333
334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "PCH EG20T port[%d] regs:\n", priv->port.line);
336
337 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
338 "=================================\n");
339 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
340 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
341 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
342 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
343 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
344 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
345 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
346 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
347 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
348 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
349 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
350 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
351 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
352 "BRCSR: \t0x%02x\n",
353 ioread8(priv->membase + PCH_UART_BRCSR));
354
355 lcr = ioread8(priv->membase + UART_LCR);
356 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
357 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
358 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
359 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
360 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
361 iowrite8(lcr, priv->membase + UART_LCR);
362
363 if (len > PCH_REGS_BUFSIZE)
364 len = PCH_REGS_BUFSIZE;
365
366 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
367 kfree(buf);
368 return ret;
369}
370
371static const struct file_operations port_regs_ops = {
372 .owner = THIS_MODULE,
373 .open = simple_open,
374 .read = port_show_regs,
375 .llseek = default_llseek,
376};
377#endif /* CONFIG_DEBUG_FS */
378
379static struct dmi_system_id pch_uart_dmi_table[] = {
380 {
381 .ident = "CM-iTC",
382 {
383 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
384 },
385 (void *)CMITC_UARTCLK,
386 },
387 {
388 .ident = "FRI2",
389 {
390 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
391 },
392 (void *)FRI2_64_UARTCLK,
393 },
394 {
395 .ident = "Fish River Island II",
396 {
397 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
398 },
399 (void *)FRI2_48_UARTCLK,
400 },
401 {
402 .ident = "COMe-mTT",
403 {
404 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
405 },
406 (void *)NTC1_UARTCLK,
407 },
408 {
409 .ident = "nanoETXexpress-TT",
410 {
411 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
412 },
413 (void *)NTC1_UARTCLK,
414 },
415 {
416 .ident = "MinnowBoard",
417 {
418 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
419 },
420 (void *)MINNOW_UARTCLK,
421 },
422 { }
423};
424
425/* Return UART clock, checking for board specific clocks. */
426static unsigned int pch_uart_get_uartclk(void)
427{
428 const struct dmi_system_id *d;
429
430 if (user_uartclk)
431 return user_uartclk;
432
433 d = dmi_first_match(pch_uart_dmi_table);
434 if (d)
435 return (unsigned long)d->driver_data;
436
437 return DEFAULT_UARTCLK;
438}
439
440static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
441 unsigned int flag)
442{
443 u8 ier = ioread8(priv->membase + UART_IER);
444 ier |= flag & PCH_UART_IER_MASK;
445 iowrite8(ier, priv->membase + UART_IER);
446}
447
448static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
449 unsigned int flag)
450{
451 u8 ier = ioread8(priv->membase + UART_IER);
452 ier &= ~(flag & PCH_UART_IER_MASK);
453 iowrite8(ier, priv->membase + UART_IER);
454}
455
456static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
457 unsigned int parity, unsigned int bits,
458 unsigned int stb)
459{
460 unsigned int dll, dlm, lcr;
461 int div;
462
463 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
464 if (div < 0 || USHRT_MAX <= div) {
465 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
466 return -EINVAL;
467 }
468
469 dll = (unsigned int)div & 0x00FFU;
470 dlm = ((unsigned int)div >> 8) & 0x00FFU;
471
472 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
473 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
474 return -EINVAL;
475 }
476
477 if (bits & ~PCH_UART_LCR_WLS) {
478 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
479 return -EINVAL;
480 }
481
482 if (stb & ~PCH_UART_LCR_STB) {
483 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
484 return -EINVAL;
485 }
486
487 lcr = parity;
488 lcr |= bits;
489 lcr |= stb;
490
491 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
492 __func__, baud, div, lcr, jiffies);
493 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
494 iowrite8(dll, priv->membase + PCH_UART_DLL);
495 iowrite8(dlm, priv->membase + PCH_UART_DLM);
496 iowrite8(lcr, priv->membase + UART_LCR);
497
498 return 0;
499}
500
501static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
502 unsigned int flag)
503{
504 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
505 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
506 __func__, flag);
507 return -EINVAL;
508 }
509
510 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
511 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
512 priv->membase + UART_FCR);
513 iowrite8(priv->fcr, priv->membase + UART_FCR);
514
515 return 0;
516}
517
518static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
519 unsigned int dmamode,
520 unsigned int fifo_size, unsigned int trigger)
521{
522 u8 fcr;
523
524 if (dmamode & ~PCH_UART_FCR_DMS) {
525 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
526 __func__, dmamode);
527 return -EINVAL;
528 }
529
530 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
531 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
532 __func__, fifo_size);
533 return -EINVAL;
534 }
535
536 if (trigger & ~PCH_UART_FCR_RFTL) {
537 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
538 __func__, trigger);
539 return -EINVAL;
540 }
541
542 switch (priv->fifo_size) {
543 case 256:
544 priv->trigger_level =
545 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
546 break;
547 case 64:
548 priv->trigger_level =
549 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
550 break;
551 case 16:
552 priv->trigger_level =
553 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
554 break;
555 default:
556 priv->trigger_level =
557 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
558 break;
559 }
560 fcr =
561 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
562 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
563 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
564 priv->membase + UART_FCR);
565 iowrite8(fcr, priv->membase + UART_FCR);
566 priv->fcr = fcr;
567
568 return 0;
569}
570
571static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
572{
573 unsigned int msr = ioread8(priv->membase + UART_MSR);
574 priv->dmsr = msr & PCH_UART_MSR_DELTA;
575 return (u8)msr;
576}
577
578static void pch_uart_hal_write(struct eg20t_port *priv,
579 const unsigned char *buf, int tx_size)
580{
581 int i;
582 unsigned int thr;
583
584 for (i = 0; i < tx_size;) {
585 thr = buf[i++];
586 iowrite8(thr, priv->membase + PCH_UART_THR);
587 }
588}
589
590static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
591 int rx_size)
592{
593 int i;
594 u8 rbr, lsr;
595 struct uart_port *port = &priv->port;
596
597 lsr = ioread8(priv->membase + UART_LSR);
598 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
599 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
600 lsr = ioread8(priv->membase + UART_LSR)) {
601 rbr = ioread8(priv->membase + PCH_UART_RBR);
602
603 if (lsr & UART_LSR_BI) {
604 port->icount.brk++;
605 if (uart_handle_break(port))
606 continue;
607 }
608#ifdef SUPPORT_SYSRQ
609 if (port->sysrq) {
610 if (uart_handle_sysrq_char(port, rbr))
611 continue;
612 }
613#endif
614
615 buf[i++] = rbr;
616 }
617 return i;
618}
619
620static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
621{
622 return ioread8(priv->membase + UART_IIR) &\
623 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
624}
625
626static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
627{
628 return ioread8(priv->membase + UART_LSR);
629}
630
631static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
632{
633 unsigned int lcr;
634
635 lcr = ioread8(priv->membase + UART_LCR);
636 if (on)
637 lcr |= PCH_UART_LCR_SB;
638 else
639 lcr &= ~PCH_UART_LCR_SB;
640
641 iowrite8(lcr, priv->membase + UART_LCR);
642}
643
644static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
645 int size)
646{
647 struct uart_port *port = &priv->port;
648 struct tty_port *tport = &port->state->port;
649
650 tty_insert_flip_string(tport, buf, size);
651 tty_flip_buffer_push(tport);
652
653 return 0;
654}
655
656static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
657{
658 int ret = 0;
659 struct uart_port *port = &priv->port;
660
661 if (port->x_char) {
662 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
663 __func__, port->x_char, jiffies);
664 buf[0] = port->x_char;
665 port->x_char = 0;
666 ret = 1;
667 }
668
669 return ret;
670}
671
672static int dma_push_rx(struct eg20t_port *priv, int size)
673{
674 int room;
675 struct uart_port *port = &priv->port;
676 struct tty_port *tport = &port->state->port;
677
678 room = tty_buffer_request_room(tport, size);
679
680 if (room < size)
681 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
682 size - room);
683 if (!room)
684 return 0;
685
686 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
687
688 port->icount.rx += room;
689
690 return room;
691}
692
693static void pch_free_dma(struct uart_port *port)
694{
695 struct eg20t_port *priv;
696 priv = container_of(port, struct eg20t_port, port);
697
698 if (priv->chan_tx) {
699 dma_release_channel(priv->chan_tx);
700 priv->chan_tx = NULL;
701 }
702 if (priv->chan_rx) {
703 dma_release_channel(priv->chan_rx);
704 priv->chan_rx = NULL;
705 }
706
707 if (priv->rx_buf_dma) {
708 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
709 priv->rx_buf_dma);
710 priv->rx_buf_virt = NULL;
711 priv->rx_buf_dma = 0;
712 }
713
714 return;
715}
716
717static bool filter(struct dma_chan *chan, void *slave)
718{
719 struct pch_dma_slave *param = slave;
720
721 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
722 chan->device->dev)) {
723 chan->private = param;
724 return true;
725 } else {
726 return false;
727 }
728}
729
730static void pch_request_dma(struct uart_port *port)
731{
732 dma_cap_mask_t mask;
733 struct dma_chan *chan;
734 struct pci_dev *dma_dev;
735 struct pch_dma_slave *param;
736 struct eg20t_port *priv =
737 container_of(port, struct eg20t_port, port);
738 dma_cap_zero(mask);
739 dma_cap_set(DMA_SLAVE, mask);
740
741 /* Get DMA's dev information */
742 dma_dev = pci_get_slot(priv->pdev->bus,
743 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
744
745 /* Set Tx DMA */
746 param = &priv->param_tx;
747 param->dma_dev = &dma_dev->dev;
748 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
749
750 param->tx_reg = port->mapbase + UART_TX;
751 chan = dma_request_channel(mask, filter, param);
752 if (!chan) {
753 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
754 __func__);
755 return;
756 }
757 priv->chan_tx = chan;
758
759 /* Set Rx DMA */
760 param = &priv->param_rx;
761 param->dma_dev = &dma_dev->dev;
762 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
763
764 param->rx_reg = port->mapbase + UART_RX;
765 chan = dma_request_channel(mask, filter, param);
766 if (!chan) {
767 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
768 __func__);
769 dma_release_channel(priv->chan_tx);
770 priv->chan_tx = NULL;
771 return;
772 }
773
774 /* Get Consistent memory for DMA */
775 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
776 &priv->rx_buf_dma, GFP_KERNEL);
777 priv->chan_rx = chan;
778}
779
780static void pch_dma_rx_complete(void *arg)
781{
782 struct eg20t_port *priv = arg;
783 struct uart_port *port = &priv->port;
784 int count;
785
786 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
787 count = dma_push_rx(priv, priv->trigger_level);
788 if (count)
789 tty_flip_buffer_push(&port->state->port);
790 async_tx_ack(priv->desc_rx);
791 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
792 PCH_UART_HAL_RX_ERR_INT);
793}
794
795static void pch_dma_tx_complete(void *arg)
796{
797 struct eg20t_port *priv = arg;
798 struct uart_port *port = &priv->port;
799 struct circ_buf *xmit = &port->state->xmit;
800 struct scatterlist *sg = priv->sg_tx_p;
801 int i;
802
803 for (i = 0; i < priv->nent; i++, sg++) {
804 xmit->tail += sg_dma_len(sg);
805 port->icount.tx += sg_dma_len(sg);
806 }
807 xmit->tail &= UART_XMIT_SIZE - 1;
808 async_tx_ack(priv->desc_tx);
809 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
810 priv->tx_dma_use = 0;
811 priv->nent = 0;
812 kfree(priv->sg_tx_p);
813 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
814}
815
816static int pop_tx(struct eg20t_port *priv, int size)
817{
818 int count = 0;
819 struct uart_port *port = &priv->port;
820 struct circ_buf *xmit = &port->state->xmit;
821
822 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
823 goto pop_tx_end;
824
825 do {
826 int cnt_to_end =
827 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
828 int sz = min(size - count, cnt_to_end);
829 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
830 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
831 count += sz;
832 } while (!uart_circ_empty(xmit) && count < size);
833
834pop_tx_end:
835 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
836 count, size - count, jiffies);
837
838 return count;
839}
840
841static int handle_rx_to(struct eg20t_port *priv)
842{
843 struct pch_uart_buffer *buf;
844 int rx_size;
845 int ret;
846 if (!priv->start_rx) {
847 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
848 PCH_UART_HAL_RX_ERR_INT);
849 return 0;
850 }
851 buf = &priv->rxbuf;
852 do {
853 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
854 ret = push_rx(priv, buf->buf, rx_size);
855 if (ret)
856 return 0;
857 } while (rx_size == buf->size);
858
859 return PCH_UART_HANDLED_RX_INT;
860}
861
862static int handle_rx(struct eg20t_port *priv)
863{
864 return handle_rx_to(priv);
865}
866
867static int dma_handle_rx(struct eg20t_port *priv)
868{
869 struct uart_port *port = &priv->port;
870 struct dma_async_tx_descriptor *desc;
871 struct scatterlist *sg;
872
873 priv = container_of(port, struct eg20t_port, port);
874 sg = &priv->sg_rx;
875
876 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
877
878 sg_dma_len(sg) = priv->trigger_level;
879
880 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
881 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
882 ~PAGE_MASK);
883
884 sg_dma_address(sg) = priv->rx_buf_dma;
885
886 desc = dmaengine_prep_slave_sg(priv->chan_rx,
887 sg, 1, DMA_DEV_TO_MEM,
888 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
889
890 if (!desc)
891 return 0;
892
893 priv->desc_rx = desc;
894 desc->callback = pch_dma_rx_complete;
895 desc->callback_param = priv;
896 desc->tx_submit(desc);
897 dma_async_issue_pending(priv->chan_rx);
898
899 return PCH_UART_HANDLED_RX_INT;
900}
901
902static unsigned int handle_tx(struct eg20t_port *priv)
903{
904 struct uart_port *port = &priv->port;
905 struct circ_buf *xmit = &port->state->xmit;
906 int fifo_size;
907 int tx_size;
908 int size;
909 int tx_empty;
910
911 if (!priv->start_tx) {
912 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
913 __func__, jiffies);
914 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
915 priv->tx_empty = 1;
916 return 0;
917 }
918
919 fifo_size = max(priv->fifo_size, 1);
920 tx_empty = 1;
921 if (pop_tx_x(priv, xmit->buf)) {
922 pch_uart_hal_write(priv, xmit->buf, 1);
923 port->icount.tx++;
924 tx_empty = 0;
925 fifo_size--;
926 }
927 size = min(xmit->head - xmit->tail, fifo_size);
928 if (size < 0)
929 size = fifo_size;
930
931 tx_size = pop_tx(priv, size);
932 if (tx_size > 0) {
933 port->icount.tx += tx_size;
934 tx_empty = 0;
935 }
936
937 priv->tx_empty = tx_empty;
938
939 if (tx_empty) {
940 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
941 uart_write_wakeup(port);
942 }
943
944 return PCH_UART_HANDLED_TX_INT;
945}
946
947static unsigned int dma_handle_tx(struct eg20t_port *priv)
948{
949 struct uart_port *port = &priv->port;
950 struct circ_buf *xmit = &port->state->xmit;
951 struct scatterlist *sg;
952 int nent;
953 int fifo_size;
954 int tx_empty;
955 struct dma_async_tx_descriptor *desc;
956 int num;
957 int i;
958 int bytes;
959 int size;
960 int rem;
961
962 if (!priv->start_tx) {
963 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
964 __func__, jiffies);
965 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
966 priv->tx_empty = 1;
967 return 0;
968 }
969
970 if (priv->tx_dma_use) {
971 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
972 __func__, jiffies);
973 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
974 priv->tx_empty = 1;
975 return 0;
976 }
977
978 fifo_size = max(priv->fifo_size, 1);
979 tx_empty = 1;
980 if (pop_tx_x(priv, xmit->buf)) {
981 pch_uart_hal_write(priv, xmit->buf, 1);
982 port->icount.tx++;
983 tx_empty = 0;
984 fifo_size--;
985 }
986
987 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
988 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
989 xmit->tail, UART_XMIT_SIZE));
990 if (!bytes) {
991 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
992 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
993 uart_write_wakeup(port);
994 return 0;
995 }
996
997 if (bytes > fifo_size) {
998 num = bytes / fifo_size + 1;
999 size = fifo_size;
1000 rem = bytes % fifo_size;
1001 } else {
1002 num = 1;
1003 size = bytes;
1004 rem = bytes;
1005 }
1006
1007 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1008 __func__, num, size, rem);
1009
1010 priv->tx_dma_use = 1;
1011
1012 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1013 if (!priv->sg_tx_p) {
1014 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1015 return 0;
1016 }
1017
1018 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1019 sg = priv->sg_tx_p;
1020
1021 for (i = 0; i < num; i++, sg++) {
1022 if (i == (num - 1))
1023 sg_set_page(sg, virt_to_page(xmit->buf),
1024 rem, fifo_size * i);
1025 else
1026 sg_set_page(sg, virt_to_page(xmit->buf),
1027 size, fifo_size * i);
1028 }
1029
1030 sg = priv->sg_tx_p;
1031 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1032 if (!nent) {
1033 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1034 return 0;
1035 }
1036 priv->nent = nent;
1037
1038 for (i = 0; i < nent; i++, sg++) {
1039 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1040 fifo_size * i;
1041 sg_dma_address(sg) = (sg_dma_address(sg) &
1042 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1043 if (i == (nent - 1))
1044 sg_dma_len(sg) = rem;
1045 else
1046 sg_dma_len(sg) = size;
1047 }
1048
1049 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1050 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1051 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1052 if (!desc) {
1053 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1054 __func__);
1055 return 0;
1056 }
1057 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1058 priv->desc_tx = desc;
1059 desc->callback = pch_dma_tx_complete;
1060 desc->callback_param = priv;
1061
1062 desc->tx_submit(desc);
1063
1064 dma_async_issue_pending(priv->chan_tx);
1065
1066 return PCH_UART_HANDLED_TX_INT;
1067}
1068
1069static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1070{
1071 struct uart_port *port = &priv->port;
1072 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1073 char *error_msg[5] = {};
1074 int i = 0;
1075
1076 if (lsr & PCH_UART_LSR_ERR)
1077 error_msg[i++] = "Error data in FIFO\n";
1078
1079 if (lsr & UART_LSR_FE) {
1080 port->icount.frame++;
1081 error_msg[i++] = " Framing Error\n";
1082 }
1083
1084 if (lsr & UART_LSR_PE) {
1085 port->icount.parity++;
1086 error_msg[i++] = " Parity Error\n";
1087 }
1088
1089 if (lsr & UART_LSR_OE) {
1090 port->icount.overrun++;
1091 error_msg[i++] = " Overrun Error\n";
1092 }
1093
1094 if (tty == NULL) {
1095 for (i = 0; error_msg[i] != NULL; i++)
1096 dev_err(&priv->pdev->dev, error_msg[i]);
1097 } else {
1098 tty_kref_put(tty);
1099 }
1100}
1101
1102static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1103{
1104 struct eg20t_port *priv = dev_id;
1105 unsigned int handled;
1106 u8 lsr;
1107 int ret = 0;
1108 unsigned char iid;
1109 unsigned long flags;
1110 int next = 1;
1111 u8 msr;
1112
1113 spin_lock_irqsave(&priv->lock, flags);
1114 handled = 0;
1115 while (next) {
1116 iid = pch_uart_hal_get_iid(priv);
1117 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1118 break;
1119 switch (iid) {
1120 case PCH_UART_IID_RLS: /* Receiver Line Status */
1121 lsr = pch_uart_hal_get_line_status(priv);
1122 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1123 UART_LSR_PE | UART_LSR_OE)) {
1124 pch_uart_err_ir(priv, lsr);
1125 ret = PCH_UART_HANDLED_RX_ERR_INT;
1126 } else {
1127 ret = PCH_UART_HANDLED_LS_INT;
1128 }
1129 break;
1130 case PCH_UART_IID_RDR: /* Received Data Ready */
1131 if (priv->use_dma) {
1132 pch_uart_hal_disable_interrupt(priv,
1133 PCH_UART_HAL_RX_INT |
1134 PCH_UART_HAL_RX_ERR_INT);
1135 ret = dma_handle_rx(priv);
1136 if (!ret)
1137 pch_uart_hal_enable_interrupt(priv,
1138 PCH_UART_HAL_RX_INT |
1139 PCH_UART_HAL_RX_ERR_INT);
1140 } else {
1141 ret = handle_rx(priv);
1142 }
1143 break;
1144 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1145 (FIFO Timeout) */
1146 ret = handle_rx_to(priv);
1147 break;
1148 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1149 Empty */
1150 if (priv->use_dma)
1151 ret = dma_handle_tx(priv);
1152 else
1153 ret = handle_tx(priv);
1154 break;
1155 case PCH_UART_IID_MS: /* Modem Status */
1156 msr = pch_uart_hal_get_modem(priv);
1157 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1158 means final interrupt */
1159 if ((msr & UART_MSR_ANY_DELTA) == 0)
1160 break;
1161 ret |= PCH_UART_HANDLED_MS_INT;
1162 break;
1163 default: /* Never junp to this label */
1164 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1165 iid, jiffies);
1166 ret = -1;
1167 next = 0;
1168 break;
1169 }
1170 handled |= (unsigned int)ret;
1171 }
1172
1173 spin_unlock_irqrestore(&priv->lock, flags);
1174 return IRQ_RETVAL(handled);
1175}
1176
1177/* This function tests whether the transmitter fifo and shifter for the port
1178 described by 'port' is empty. */
1179static unsigned int pch_uart_tx_empty(struct uart_port *port)
1180{
1181 struct eg20t_port *priv;
1182
1183 priv = container_of(port, struct eg20t_port, port);
1184 if (priv->tx_empty)
1185 return TIOCSER_TEMT;
1186 else
1187 return 0;
1188}
1189
1190/* Returns the current state of modem control inputs. */
1191static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1192{
1193 struct eg20t_port *priv;
1194 u8 modem;
1195 unsigned int ret = 0;
1196
1197 priv = container_of(port, struct eg20t_port, port);
1198 modem = pch_uart_hal_get_modem(priv);
1199
1200 if (modem & UART_MSR_DCD)
1201 ret |= TIOCM_CAR;
1202
1203 if (modem & UART_MSR_RI)
1204 ret |= TIOCM_RNG;
1205
1206 if (modem & UART_MSR_DSR)
1207 ret |= TIOCM_DSR;
1208
1209 if (modem & UART_MSR_CTS)
1210 ret |= TIOCM_CTS;
1211
1212 return ret;
1213}
1214
1215static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1216{
1217 u32 mcr = 0;
1218 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1219
1220 if (mctrl & TIOCM_DTR)
1221 mcr |= UART_MCR_DTR;
1222 if (mctrl & TIOCM_RTS)
1223 mcr |= UART_MCR_RTS;
1224 if (mctrl & TIOCM_LOOP)
1225 mcr |= UART_MCR_LOOP;
1226
1227 if (priv->mcr & UART_MCR_AFE)
1228 mcr |= UART_MCR_AFE;
1229
1230 if (mctrl)
1231 iowrite8(mcr, priv->membase + UART_MCR);
1232}
1233
1234static void pch_uart_stop_tx(struct uart_port *port)
1235{
1236 struct eg20t_port *priv;
1237 priv = container_of(port, struct eg20t_port, port);
1238 priv->start_tx = 0;
1239 priv->tx_dma_use = 0;
1240}
1241
1242static void pch_uart_start_tx(struct uart_port *port)
1243{
1244 struct eg20t_port *priv;
1245
1246 priv = container_of(port, struct eg20t_port, port);
1247
1248 if (priv->use_dma) {
1249 if (priv->tx_dma_use) {
1250 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1251 __func__);
1252 return;
1253 }
1254 }
1255
1256 priv->start_tx = 1;
1257 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1258}
1259
1260static void pch_uart_stop_rx(struct uart_port *port)
1261{
1262 struct eg20t_port *priv;
1263 priv = container_of(port, struct eg20t_port, port);
1264 priv->start_rx = 0;
1265 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1266 PCH_UART_HAL_RX_ERR_INT);
1267}
1268
1269/* Enable the modem status interrupts. */
1270static void pch_uart_enable_ms(struct uart_port *port)
1271{
1272 struct eg20t_port *priv;
1273 priv = container_of(port, struct eg20t_port, port);
1274 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1275}
1276
1277/* Control the transmission of a break signal. */
1278static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1279{
1280 struct eg20t_port *priv;
1281 unsigned long flags;
1282
1283 priv = container_of(port, struct eg20t_port, port);
1284 spin_lock_irqsave(&priv->lock, flags);
1285 pch_uart_hal_set_break(priv, ctl);
1286 spin_unlock_irqrestore(&priv->lock, flags);
1287}
1288
1289/* Grab any interrupt resources and initialise any low level driver state. */
1290static int pch_uart_startup(struct uart_port *port)
1291{
1292 struct eg20t_port *priv;
1293 int ret;
1294 int fifo_size;
1295 int trigger_level;
1296
1297 priv = container_of(port, struct eg20t_port, port);
1298 priv->tx_empty = 1;
1299
1300 if (port->uartclk)
1301 priv->uartclk = port->uartclk;
1302 else
1303 port->uartclk = priv->uartclk;
1304
1305 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1306 ret = pch_uart_hal_set_line(priv, default_baud,
1307 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1308 PCH_UART_HAL_STB1);
1309 if (ret)
1310 return ret;
1311
1312 switch (priv->fifo_size) {
1313 case 256:
1314 fifo_size = PCH_UART_HAL_FIFO256;
1315 break;
1316 case 64:
1317 fifo_size = PCH_UART_HAL_FIFO64;
1318 break;
1319 case 16:
1320 fifo_size = PCH_UART_HAL_FIFO16;
1321 break;
1322 case 1:
1323 default:
1324 fifo_size = PCH_UART_HAL_FIFO_DIS;
1325 break;
1326 }
1327
1328 switch (priv->trigger) {
1329 case PCH_UART_HAL_TRIGGER1:
1330 trigger_level = 1;
1331 break;
1332 case PCH_UART_HAL_TRIGGER_L:
1333 trigger_level = priv->fifo_size / 4;
1334 break;
1335 case PCH_UART_HAL_TRIGGER_M:
1336 trigger_level = priv->fifo_size / 2;
1337 break;
1338 case PCH_UART_HAL_TRIGGER_H:
1339 default:
1340 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1341 break;
1342 }
1343
1344 priv->trigger_level = trigger_level;
1345 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1346 fifo_size, priv->trigger);
1347 if (ret < 0)
1348 return ret;
1349
1350 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1351 priv->irq_name, priv);
1352 if (ret < 0)
1353 return ret;
1354
1355 if (priv->use_dma)
1356 pch_request_dma(port);
1357
1358 priv->start_rx = 1;
1359 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1360 PCH_UART_HAL_RX_ERR_INT);
1361 uart_update_timeout(port, CS8, default_baud);
1362
1363 return 0;
1364}
1365
1366static void pch_uart_shutdown(struct uart_port *port)
1367{
1368 struct eg20t_port *priv;
1369 int ret;
1370
1371 priv = container_of(port, struct eg20t_port, port);
1372 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1373 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1374 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1375 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1376 if (ret)
1377 dev_err(priv->port.dev,
1378 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1379
1380 pch_free_dma(port);
1381
1382 free_irq(priv->port.irq, priv);
1383}
1384
1385/* Change the port parameters, including word length, parity, stop
1386 *bits. Update read_status_mask and ignore_status_mask to indicate
1387 *the types of events we are interested in receiving. */
1388static void pch_uart_set_termios(struct uart_port *port,
1389 struct ktermios *termios, struct ktermios *old)
1390{
1391 int rtn;
1392 unsigned int baud, parity, bits, stb;
1393 struct eg20t_port *priv;
1394 unsigned long flags;
1395
1396 priv = container_of(port, struct eg20t_port, port);
1397 switch (termios->c_cflag & CSIZE) {
1398 case CS5:
1399 bits = PCH_UART_HAL_5BIT;
1400 break;
1401 case CS6:
1402 bits = PCH_UART_HAL_6BIT;
1403 break;
1404 case CS7:
1405 bits = PCH_UART_HAL_7BIT;
1406 break;
1407 default: /* CS8 */
1408 bits = PCH_UART_HAL_8BIT;
1409 break;
1410 }
1411 if (termios->c_cflag & CSTOPB)
1412 stb = PCH_UART_HAL_STB2;
1413 else
1414 stb = PCH_UART_HAL_STB1;
1415
1416 if (termios->c_cflag & PARENB) {
1417 if (termios->c_cflag & PARODD)
1418 parity = PCH_UART_HAL_PARITY_ODD;
1419 else
1420 parity = PCH_UART_HAL_PARITY_EVEN;
1421
1422 } else
1423 parity = PCH_UART_HAL_PARITY_NONE;
1424
1425 /* Only UART0 has auto hardware flow function */
1426 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1427 priv->mcr |= UART_MCR_AFE;
1428 else
1429 priv->mcr &= ~UART_MCR_AFE;
1430
1431 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1432
1433 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1434
1435 spin_lock_irqsave(&priv->lock, flags);
1436 spin_lock(&port->lock);
1437
1438 uart_update_timeout(port, termios->c_cflag, baud);
1439 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1440 if (rtn)
1441 goto out;
1442
1443 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1444 /* Don't rewrite B0 */
1445 if (tty_termios_baud_rate(termios))
1446 tty_termios_encode_baud_rate(termios, baud, baud);
1447
1448out:
1449 spin_unlock(&port->lock);
1450 spin_unlock_irqrestore(&priv->lock, flags);
1451}
1452
1453static const char *pch_uart_type(struct uart_port *port)
1454{
1455 return KBUILD_MODNAME;
1456}
1457
1458static void pch_uart_release_port(struct uart_port *port)
1459{
1460 struct eg20t_port *priv;
1461
1462 priv = container_of(port, struct eg20t_port, port);
1463 pci_iounmap(priv->pdev, priv->membase);
1464 pci_release_regions(priv->pdev);
1465}
1466
1467static int pch_uart_request_port(struct uart_port *port)
1468{
1469 struct eg20t_port *priv;
1470 int ret;
1471 void __iomem *membase;
1472
1473 priv = container_of(port, struct eg20t_port, port);
1474 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1475 if (ret < 0)
1476 return -EBUSY;
1477
1478 membase = pci_iomap(priv->pdev, 1, 0);
1479 if (!membase) {
1480 pci_release_regions(priv->pdev);
1481 return -EBUSY;
1482 }
1483 priv->membase = port->membase = membase;
1484
1485 return 0;
1486}
1487
1488static void pch_uart_config_port(struct uart_port *port, int type)
1489{
1490 struct eg20t_port *priv;
1491
1492 priv = container_of(port, struct eg20t_port, port);
1493 if (type & UART_CONFIG_TYPE) {
1494 port->type = priv->port_type;
1495 pch_uart_request_port(port);
1496 }
1497}
1498
1499static int pch_uart_verify_port(struct uart_port *port,
1500 struct serial_struct *serinfo)
1501{
1502 struct eg20t_port *priv;
1503
1504 priv = container_of(port, struct eg20t_port, port);
1505 if (serinfo->flags & UPF_LOW_LATENCY) {
1506 dev_info(priv->port.dev,
1507 "PCH UART : Use PIO Mode (without DMA)\n");
1508 priv->use_dma = 0;
1509 serinfo->flags &= ~UPF_LOW_LATENCY;
1510 } else {
1511#ifndef CONFIG_PCH_DMA
1512 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1513 __func__);
1514 return -EOPNOTSUPP;
1515#endif
1516 if (!priv->use_dma) {
1517 pch_request_dma(port);
1518 if (priv->chan_rx)
1519 priv->use_dma = 1;
1520 }
1521 dev_info(priv->port.dev, "PCH UART: %s\n",
1522 priv->use_dma ?
1523 "Use DMA Mode" : "No DMA");
1524 }
1525
1526 return 0;
1527}
1528
1529#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1530/*
1531 * Wait for transmitter & holding register to empty
1532 */
1533static void wait_for_xmitr(struct eg20t_port *up, int bits)
1534{
1535 unsigned int status, tmout = 10000;
1536
1537 /* Wait up to 10ms for the character(s) to be sent. */
1538 for (;;) {
1539 status = ioread8(up->membase + UART_LSR);
1540
1541 if ((status & bits) == bits)
1542 break;
1543 if (--tmout == 0)
1544 break;
1545 udelay(1);
1546 }
1547
1548 /* Wait up to 1s for flow control if necessary */
1549 if (up->port.flags & UPF_CONS_FLOW) {
1550 unsigned int tmout;
1551 for (tmout = 1000000; tmout; tmout--) {
1552 unsigned int msr = ioread8(up->membase + UART_MSR);
1553 if (msr & UART_MSR_CTS)
1554 break;
1555 udelay(1);
1556 touch_nmi_watchdog();
1557 }
1558 }
1559}
1560#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1561
1562#ifdef CONFIG_CONSOLE_POLL
1563/*
1564 * Console polling routines for communicate via uart while
1565 * in an interrupt or debug context.
1566 */
1567static int pch_uart_get_poll_char(struct uart_port *port)
1568{
1569 struct eg20t_port *priv =
1570 container_of(port, struct eg20t_port, port);
1571 u8 lsr = ioread8(priv->membase + UART_LSR);
1572
1573 if (!(lsr & UART_LSR_DR))
1574 return NO_POLL_CHAR;
1575
1576 return ioread8(priv->membase + PCH_UART_RBR);
1577}
1578
1579
1580static void pch_uart_put_poll_char(struct uart_port *port,
1581 unsigned char c)
1582{
1583 unsigned int ier;
1584 struct eg20t_port *priv =
1585 container_of(port, struct eg20t_port, port);
1586
1587 /*
1588 * First save the IER then disable the interrupts
1589 */
1590 ier = ioread8(priv->membase + UART_IER);
1591 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1592
1593 wait_for_xmitr(priv, UART_LSR_THRE);
1594 /*
1595 * Send the character out.
1596 */
1597 iowrite8(c, priv->membase + PCH_UART_THR);
1598
1599 /*
1600 * Finally, wait for transmitter to become empty
1601 * and restore the IER
1602 */
1603 wait_for_xmitr(priv, BOTH_EMPTY);
1604 iowrite8(ier, priv->membase + UART_IER);
1605}
1606#endif /* CONFIG_CONSOLE_POLL */
1607
1608static const struct uart_ops pch_uart_ops = {
1609 .tx_empty = pch_uart_tx_empty,
1610 .set_mctrl = pch_uart_set_mctrl,
1611 .get_mctrl = pch_uart_get_mctrl,
1612 .stop_tx = pch_uart_stop_tx,
1613 .start_tx = pch_uart_start_tx,
1614 .stop_rx = pch_uart_stop_rx,
1615 .enable_ms = pch_uart_enable_ms,
1616 .break_ctl = pch_uart_break_ctl,
1617 .startup = pch_uart_startup,
1618 .shutdown = pch_uart_shutdown,
1619 .set_termios = pch_uart_set_termios,
1620/* .pm = pch_uart_pm, Not supported yet */
1621 .type = pch_uart_type,
1622 .release_port = pch_uart_release_port,
1623 .request_port = pch_uart_request_port,
1624 .config_port = pch_uart_config_port,
1625 .verify_port = pch_uart_verify_port,
1626#ifdef CONFIG_CONSOLE_POLL
1627 .poll_get_char = pch_uart_get_poll_char,
1628 .poll_put_char = pch_uart_put_poll_char,
1629#endif
1630};
1631
1632#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1633
1634static void pch_console_putchar(struct uart_port *port, int ch)
1635{
1636 struct eg20t_port *priv =
1637 container_of(port, struct eg20t_port, port);
1638
1639 wait_for_xmitr(priv, UART_LSR_THRE);
1640 iowrite8(ch, priv->membase + PCH_UART_THR);
1641}
1642
1643/*
1644 * Print a string to the serial port trying not to disturb
1645 * any possible real use of the port...
1646 *
1647 * The console_lock must be held when we get here.
1648 */
1649static void
1650pch_console_write(struct console *co, const char *s, unsigned int count)
1651{
1652 struct eg20t_port *priv;
1653 unsigned long flags;
1654 int priv_locked = 1;
1655 int port_locked = 1;
1656 u8 ier;
1657
1658 priv = pch_uart_ports[co->index];
1659
1660 touch_nmi_watchdog();
1661
1662 local_irq_save(flags);
1663 if (priv->port.sysrq) {
1664 /* call to uart_handle_sysrq_char already took the priv lock */
1665 priv_locked = 0;
1666 /* serial8250_handle_port() already took the port lock */
1667 port_locked = 0;
1668 } else if (oops_in_progress) {
1669 priv_locked = spin_trylock(&priv->lock);
1670 port_locked = spin_trylock(&priv->port.lock);
1671 } else {
1672 spin_lock(&priv->lock);
1673 spin_lock(&priv->port.lock);
1674 }
1675
1676 /*
1677 * First save the IER then disable the interrupts
1678 */
1679 ier = ioread8(priv->membase + UART_IER);
1680
1681 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1682
1683 uart_console_write(&priv->port, s, count, pch_console_putchar);
1684
1685 /*
1686 * Finally, wait for transmitter to become empty
1687 * and restore the IER
1688 */
1689 wait_for_xmitr(priv, BOTH_EMPTY);
1690 iowrite8(ier, priv->membase + UART_IER);
1691
1692 if (port_locked)
1693 spin_unlock(&priv->port.lock);
1694 if (priv_locked)
1695 spin_unlock(&priv->lock);
1696 local_irq_restore(flags);
1697}
1698
1699static int __init pch_console_setup(struct console *co, char *options)
1700{
1701 struct uart_port *port;
1702 int baud = default_baud;
1703 int bits = 8;
1704 int parity = 'n';
1705 int flow = 'n';
1706
1707 /*
1708 * Check whether an invalid uart number has been specified, and
1709 * if so, search for the first available port that does have
1710 * console support.
1711 */
1712 if (co->index >= PCH_UART_NR)
1713 co->index = 0;
1714 port = &pch_uart_ports[co->index]->port;
1715
1716 if (!port || (!port->iobase && !port->membase))
1717 return -ENODEV;
1718
1719 port->uartclk = pch_uart_get_uartclk();
1720
1721 if (options)
1722 uart_parse_options(options, &baud, &parity, &bits, &flow);
1723
1724 return uart_set_options(port, co, baud, parity, bits, flow);
1725}
1726
1727static struct uart_driver pch_uart_driver;
1728
1729static struct console pch_console = {
1730 .name = PCH_UART_DRIVER_DEVICE,
1731 .write = pch_console_write,
1732 .device = uart_console_device,
1733 .setup = pch_console_setup,
1734 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1735 .index = -1,
1736 .data = &pch_uart_driver,
1737};
1738
1739#define PCH_CONSOLE (&pch_console)
1740#else
1741#define PCH_CONSOLE NULL
1742#endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1743
1744static struct uart_driver pch_uart_driver = {
1745 .owner = THIS_MODULE,
1746 .driver_name = KBUILD_MODNAME,
1747 .dev_name = PCH_UART_DRIVER_DEVICE,
1748 .major = 0,
1749 .minor = 0,
1750 .nr = PCH_UART_NR,
1751 .cons = PCH_CONSOLE,
1752};
1753
1754static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1755 const struct pci_device_id *id)
1756{
1757 struct eg20t_port *priv;
1758 int ret;
1759 unsigned int iobase;
1760 unsigned int mapbase;
1761 unsigned char *rxbuf;
1762 int fifosize;
1763 int port_type;
1764 struct pch_uart_driver_data *board;
1765#ifdef CONFIG_DEBUG_FS
1766 char name[32]; /* for debugfs file name */
1767#endif
1768
1769 board = &drv_dat[id->driver_data];
1770 port_type = board->port_type;
1771
1772 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1773 if (priv == NULL)
1774 goto init_port_alloc_err;
1775
1776 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1777 if (!rxbuf)
1778 goto init_port_free_txbuf;
1779
1780 switch (port_type) {
1781 case PORT_UNKNOWN:
1782 fifosize = 256; /* EG20T/ML7213: UART0 */
1783 break;
1784 case PORT_8250:
1785 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1786 break;
1787 default:
1788 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1789 goto init_port_hal_free;
1790 }
1791
1792 pci_enable_msi(pdev);
1793 pci_set_master(pdev);
1794
1795 spin_lock_init(&priv->lock);
1796
1797 iobase = pci_resource_start(pdev, 0);
1798 mapbase = pci_resource_start(pdev, 1);
1799 priv->mapbase = mapbase;
1800 priv->iobase = iobase;
1801 priv->pdev = pdev;
1802 priv->tx_empty = 1;
1803 priv->rxbuf.buf = rxbuf;
1804 priv->rxbuf.size = PAGE_SIZE;
1805
1806 priv->fifo_size = fifosize;
1807 priv->uartclk = pch_uart_get_uartclk();
1808 priv->port_type = PORT_MAX_8250 + port_type + 1;
1809 priv->port.dev = &pdev->dev;
1810 priv->port.iobase = iobase;
1811 priv->port.membase = NULL;
1812 priv->port.mapbase = mapbase;
1813 priv->port.irq = pdev->irq;
1814 priv->port.iotype = UPIO_PORT;
1815 priv->port.ops = &pch_uart_ops;
1816 priv->port.flags = UPF_BOOT_AUTOCONF;
1817 priv->port.fifosize = fifosize;
1818 priv->port.line = board->line_no;
1819 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1820
1821 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1822 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1823 priv->port.line);
1824
1825 spin_lock_init(&priv->port.lock);
1826
1827 pci_set_drvdata(pdev, priv);
1828 priv->trigger_level = 1;
1829 priv->fcr = 0;
1830
1831 if (pdev->dev.of_node)
1832 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1833 , &user_uartclk);
1834
1835#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1836 pch_uart_ports[board->line_no] = priv;
1837#endif
1838 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1839 if (ret < 0)
1840 goto init_port_hal_free;
1841
1842#ifdef CONFIG_DEBUG_FS
1843 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1844 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1845 NULL, priv, &port_regs_ops);
1846#endif
1847
1848 return priv;
1849
1850init_port_hal_free:
1851#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1852 pch_uart_ports[board->line_no] = NULL;
1853#endif
1854 free_page((unsigned long)rxbuf);
1855init_port_free_txbuf:
1856 kfree(priv);
1857init_port_alloc_err:
1858
1859 return NULL;
1860}
1861
1862static void pch_uart_exit_port(struct eg20t_port *priv)
1863{
1864
1865#ifdef CONFIG_DEBUG_FS
1866 if (priv->debugfs)
1867 debugfs_remove(priv->debugfs);
1868#endif
1869 uart_remove_one_port(&pch_uart_driver, &priv->port);
1870 free_page((unsigned long)priv->rxbuf.buf);
1871}
1872
1873static void pch_uart_pci_remove(struct pci_dev *pdev)
1874{
1875 struct eg20t_port *priv = pci_get_drvdata(pdev);
1876
1877 pci_disable_msi(pdev);
1878
1879#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1880 pch_uart_ports[priv->port.line] = NULL;
1881#endif
1882 pch_uart_exit_port(priv);
1883 pci_disable_device(pdev);
1884 kfree(priv);
1885 return;
1886}
1887#ifdef CONFIG_PM
1888static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1889{
1890 struct eg20t_port *priv = pci_get_drvdata(pdev);
1891
1892 uart_suspend_port(&pch_uart_driver, &priv->port);
1893
1894 pci_save_state(pdev);
1895 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1896 return 0;
1897}
1898
1899static int pch_uart_pci_resume(struct pci_dev *pdev)
1900{
1901 struct eg20t_port *priv = pci_get_drvdata(pdev);
1902 int ret;
1903
1904 pci_set_power_state(pdev, PCI_D0);
1905 pci_restore_state(pdev);
1906
1907 ret = pci_enable_device(pdev);
1908 if (ret) {
1909 dev_err(&pdev->dev,
1910 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1911 return ret;
1912 }
1913
1914 uart_resume_port(&pch_uart_driver, &priv->port);
1915
1916 return 0;
1917}
1918#else
1919#define pch_uart_pci_suspend NULL
1920#define pch_uart_pci_resume NULL
1921#endif
1922
1923static const struct pci_device_id pch_uart_pci_id[] = {
1924 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1925 .driver_data = pch_et20t_uart0},
1926 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1927 .driver_data = pch_et20t_uart1},
1928 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1929 .driver_data = pch_et20t_uart2},
1930 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1931 .driver_data = pch_et20t_uart3},
1932 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1933 .driver_data = pch_ml7213_uart0},
1934 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1935 .driver_data = pch_ml7213_uart1},
1936 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1937 .driver_data = pch_ml7213_uart2},
1938 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1939 .driver_data = pch_ml7223_uart0},
1940 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1941 .driver_data = pch_ml7223_uart1},
1942 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1943 .driver_data = pch_ml7831_uart0},
1944 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1945 .driver_data = pch_ml7831_uart1},
1946 {0,},
1947};
1948
1949static int pch_uart_pci_probe(struct pci_dev *pdev,
1950 const struct pci_device_id *id)
1951{
1952 int ret;
1953 struct eg20t_port *priv;
1954
1955 ret = pci_enable_device(pdev);
1956 if (ret < 0)
1957 goto probe_error;
1958
1959 priv = pch_uart_init_port(pdev, id);
1960 if (!priv) {
1961 ret = -EBUSY;
1962 goto probe_disable_device;
1963 }
1964 pci_set_drvdata(pdev, priv);
1965
1966 return ret;
1967
1968probe_disable_device:
1969 pci_disable_msi(pdev);
1970 pci_disable_device(pdev);
1971probe_error:
1972 return ret;
1973}
1974
1975static struct pci_driver pch_uart_pci_driver = {
1976 .name = "pch_uart",
1977 .id_table = pch_uart_pci_id,
1978 .probe = pch_uart_pci_probe,
1979 .remove = pch_uart_pci_remove,
1980 .suspend = pch_uart_pci_suspend,
1981 .resume = pch_uart_pci_resume,
1982};
1983
1984static int __init pch_uart_module_init(void)
1985{
1986 int ret;
1987
1988 /* register as UART driver */
1989 ret = uart_register_driver(&pch_uart_driver);
1990 if (ret < 0)
1991 return ret;
1992
1993 /* register as PCI driver */
1994 ret = pci_register_driver(&pch_uart_pci_driver);
1995 if (ret < 0)
1996 uart_unregister_driver(&pch_uart_driver);
1997
1998 return ret;
1999}
2000module_init(pch_uart_module_init);
2001
2002static void __exit pch_uart_module_exit(void)
2003{
2004 pci_unregister_driver(&pch_uart_pci_driver);
2005 uart_unregister_driver(&pch_uart_driver);
2006}
2007module_exit(pch_uart_module_exit);
2008
2009MODULE_LICENSE("GPL v2");
2010MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2011MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2012
2013module_param(default_baud, uint, S_IRUGO);
2014MODULE_PARM_DESC(default_baud,
2015 "Default BAUD for initial driver state and console (default 9600)");
2016module_param(user_uartclk, uint, S_IRUGO);
2017MODULE_PARM_DESC(user_uartclk,
2018 "Override UART default or board specific UART clock");