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1// SPDX-License-Identifier: GPL-2.0+
2/************************************************************************
3 * Copyright 2003 Digi International (www.digi.com)
4 *
5 * Copyright (C) 2004 IBM Corporation. All rights reserved.
6 *
7 * Contact Information:
8 * Scott H Kilau <Scott_Kilau@digi.com>
9 * Wendy Xiong <wendyx@us.ibm.com>
10 *
11 ***********************************************************************/
12#include <linux/delay.h> /* For udelay */
13#include <linux/serial_reg.h> /* For the various UART offsets */
14#include <linux/tty.h>
15#include <linux/pci.h>
16#include <asm/io.h>
17
18#include "jsm.h" /* Driver main header file */
19
20static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
21
22/*
23 * This function allows calls to ensure that all outstanding
24 * PCI writes have been completed, by doing a PCI read against
25 * a non-destructive, read-only location on the Neo card.
26 *
27 * In this case, we are reading the DVID (Read-only Device Identification)
28 * value of the Neo card.
29 */
30static inline void neo_pci_posting_flush(struct jsm_board *bd)
31{
32 readb(bd->re_map_membase + 0x8D);
33}
34
35static void neo_set_cts_flow_control(struct jsm_channel *ch)
36{
37 u8 ier, efr;
38 ier = readb(&ch->ch_neo_uart->ier);
39 efr = readb(&ch->ch_neo_uart->efr);
40
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
42
43 /* Turn on auto CTS flow control */
44 ier |= (UART_17158_IER_CTSDSR);
45 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
46
47 /* Turn off auto Xon flow control */
48 efr &= ~(UART_17158_EFR_IXON);
49
50 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
51 writeb(0, &ch->ch_neo_uart->efr);
52
53 /* Turn on UART enhanced bits */
54 writeb(efr, &ch->ch_neo_uart->efr);
55
56 /* Turn on table D, with 8 char hi/low watermarks */
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
58
59 /* Feed the UART our trigger levels */
60 writeb(8, &ch->ch_neo_uart->tfifo);
61 ch->ch_t_tlevel = 8;
62
63 writeb(ier, &ch->ch_neo_uart->ier);
64}
65
66static void neo_set_rts_flow_control(struct jsm_channel *ch)
67{
68 u8 ier, efr;
69 ier = readb(&ch->ch_neo_uart->ier);
70 efr = readb(&ch->ch_neo_uart->efr);
71
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
73
74 /* Turn on auto RTS flow control */
75 ier |= (UART_17158_IER_RTSDTR);
76 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
77
78 /* Turn off auto Xoff flow control */
79 ier &= ~(UART_17158_IER_XOFF);
80 efr &= ~(UART_17158_EFR_IXOFF);
81
82 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
83 writeb(0, &ch->ch_neo_uart->efr);
84
85 /* Turn on UART enhanced bits */
86 writeb(efr, &ch->ch_neo_uart->efr);
87
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
89 ch->ch_r_watermark = 4;
90
91 writeb(56, &ch->ch_neo_uart->rfifo);
92 ch->ch_r_tlevel = 56;
93
94 writeb(ier, &ch->ch_neo_uart->ier);
95
96 /*
97 * From the Neo UART spec sheet:
98 * The auto RTS/DTR function must be started by asserting
99 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
100 * it is enabled.
101 */
102 ch->ch_mostat |= (UART_MCR_RTS);
103}
104
105
106static void neo_set_ixon_flow_control(struct jsm_channel *ch)
107{
108 u8 ier, efr;
109 ier = readb(&ch->ch_neo_uart->ier);
110 efr = readb(&ch->ch_neo_uart->efr);
111
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
113
114 /* Turn off auto CTS flow control */
115 ier &= ~(UART_17158_IER_CTSDSR);
116 efr &= ~(UART_17158_EFR_CTSDSR);
117
118 /* Turn on auto Xon flow control */
119 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
120
121 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
122 writeb(0, &ch->ch_neo_uart->efr);
123
124 /* Turn on UART enhanced bits */
125 writeb(efr, &ch->ch_neo_uart->efr);
126
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
128 ch->ch_r_watermark = 4;
129
130 writeb(32, &ch->ch_neo_uart->rfifo);
131 ch->ch_r_tlevel = 32;
132
133 /* Tell UART what start/stop chars it should be looking for */
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
135 writeb(0, &ch->ch_neo_uart->xonchar2);
136
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
138 writeb(0, &ch->ch_neo_uart->xoffchar2);
139
140 writeb(ier, &ch->ch_neo_uart->ier);
141}
142
143static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
144{
145 u8 ier, efr;
146 ier = readb(&ch->ch_neo_uart->ier);
147 efr = readb(&ch->ch_neo_uart->efr);
148
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
150
151 /* Turn off auto RTS flow control */
152 ier &= ~(UART_17158_IER_RTSDTR);
153 efr &= ~(UART_17158_EFR_RTSDTR);
154
155 /* Turn on auto Xoff flow control */
156 ier |= (UART_17158_IER_XOFF);
157 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
158
159 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
160 writeb(0, &ch->ch_neo_uart->efr);
161
162 /* Turn on UART enhanced bits */
163 writeb(efr, &ch->ch_neo_uart->efr);
164
165 /* Turn on table D, with 8 char hi/low watermarks */
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
167
168 writeb(8, &ch->ch_neo_uart->tfifo);
169 ch->ch_t_tlevel = 8;
170
171 /* Tell UART what start/stop chars it should be looking for */
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
173 writeb(0, &ch->ch_neo_uart->xonchar2);
174
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
176 writeb(0, &ch->ch_neo_uart->xoffchar2);
177
178 writeb(ier, &ch->ch_neo_uart->ier);
179}
180
181static void neo_set_no_input_flow_control(struct jsm_channel *ch)
182{
183 u8 ier, efr;
184 ier = readb(&ch->ch_neo_uart->ier);
185 efr = readb(&ch->ch_neo_uart->efr);
186
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
188
189 /* Turn off auto RTS flow control */
190 ier &= ~(UART_17158_IER_RTSDTR);
191 efr &= ~(UART_17158_EFR_RTSDTR);
192
193 /* Turn off auto Xoff flow control */
194 ier &= ~(UART_17158_IER_XOFF);
195 if (ch->ch_c_iflag & IXON)
196 efr &= ~(UART_17158_EFR_IXOFF);
197 else
198 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
199
200 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
201 writeb(0, &ch->ch_neo_uart->efr);
202
203 /* Turn on UART enhanced bits */
204 writeb(efr, &ch->ch_neo_uart->efr);
205
206 /* Turn on table D, with 8 char hi/low watermarks */
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
208
209 ch->ch_r_watermark = 0;
210
211 writeb(16, &ch->ch_neo_uart->tfifo);
212 ch->ch_t_tlevel = 16;
213
214 writeb(16, &ch->ch_neo_uart->rfifo);
215 ch->ch_r_tlevel = 16;
216
217 writeb(ier, &ch->ch_neo_uart->ier);
218}
219
220static void neo_set_no_output_flow_control(struct jsm_channel *ch)
221{
222 u8 ier, efr;
223 ier = readb(&ch->ch_neo_uart->ier);
224 efr = readb(&ch->ch_neo_uart->efr);
225
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
227
228 /* Turn off auto CTS flow control */
229 ier &= ~(UART_17158_IER_CTSDSR);
230 efr &= ~(UART_17158_EFR_CTSDSR);
231
232 /* Turn off auto Xon flow control */
233 if (ch->ch_c_iflag & IXOFF)
234 efr &= ~(UART_17158_EFR_IXON);
235 else
236 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
237
238 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
239 writeb(0, &ch->ch_neo_uart->efr);
240
241 /* Turn on UART enhanced bits */
242 writeb(efr, &ch->ch_neo_uart->efr);
243
244 /* Turn on table D, with 8 char hi/low watermarks */
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
246
247 ch->ch_r_watermark = 0;
248
249 writeb(16, &ch->ch_neo_uart->tfifo);
250 ch->ch_t_tlevel = 16;
251
252 writeb(16, &ch->ch_neo_uart->rfifo);
253 ch->ch_r_tlevel = 16;
254
255 writeb(ier, &ch->ch_neo_uart->ier);
256}
257
258static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
259{
260
261 /* if hardware flow control is set, then skip this whole thing */
262 if (ch->ch_c_cflag & CRTSCTS)
263 return;
264
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
266
267 /* Tell UART what start/stop chars it should be looking for */
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
269 writeb(0, &ch->ch_neo_uart->xonchar2);
270
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
272 writeb(0, &ch->ch_neo_uart->xoffchar2);
273}
274
275static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
276{
277 int qleft = 0;
278 u8 linestatus = 0;
279 u8 error_mask = 0;
280 int n = 0;
281 int total = 0;
282 u16 head;
283 u16 tail;
284
285 /* cache head and tail of queue */
286 head = ch->ch_r_head & RQUEUEMASK;
287 tail = ch->ch_r_tail & RQUEUEMASK;
288
289 /* Get our cached LSR */
290 linestatus = ch->ch_cached_lsr;
291 ch->ch_cached_lsr = 0;
292
293 /* Store how much space we have left in the queue */
294 qleft = tail - head - 1;
295 if (qleft < 0)
296 qleft += RQUEUEMASK + 1;
297
298 /*
299 * If the UART is not in FIFO mode, force the FIFO copy to
300 * NOT be run, by setting total to 0.
301 *
302 * On the other hand, if the UART IS in FIFO mode, then ask
303 * the UART to give us an approximation of data it has RX'ed.
304 */
305 if (!(ch->ch_flags & CH_FIFO_ENABLED))
306 total = 0;
307 else {
308 total = readb(&ch->ch_neo_uart->rfifo);
309
310 /*
311 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
312 *
313 * This resolves a problem/bug with the Exar chip that sometimes
314 * returns a bogus value in the rfifo register.
315 * The count can be any where from 0-3 bytes "off".
316 * Bizarre, but true.
317 */
318 total -= 3;
319 }
320
321 /*
322 * Finally, bound the copy to make sure we don't overflow
323 * our own queue...
324 * The byte by byte copy loop below this loop this will
325 * deal with the queue overflow possibility.
326 */
327 total = min(total, qleft);
328
329 while (total > 0) {
330 /*
331 * Grab the linestatus register, we need to check
332 * to see if there are any errors in the FIFO.
333 */
334 linestatus = readb(&ch->ch_neo_uart->lsr);
335
336 /*
337 * Break out if there is a FIFO error somewhere.
338 * This will allow us to go byte by byte down below,
339 * finding the exact location of the error.
340 */
341 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
342 break;
343
344 /* Make sure we don't go over the end of our queue */
345 n = min(((u32) total), (RQUEUESIZE - (u32) head));
346
347 /*
348 * Cut down n even further if needed, this is to fix
349 * a problem with memcpy_fromio() with the Neo on the
350 * IBM pSeries platform.
351 * 15 bytes max appears to be the magic number.
352 */
353 n = min((u32) n, (u32) 12);
354
355 /*
356 * Since we are grabbing the linestatus register, which
357 * will reset some bits after our read, we need to ensure
358 * we don't miss our TX FIFO emptys.
359 */
360 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
361 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
362
363 linestatus = 0;
364
365 /* Copy data from uart to the queue */
366 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
367 /*
368 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
369 * that all the data currently in the FIFO is free of
370 * breaks and parity/frame/orun errors.
371 */
372 memset(ch->ch_equeue + head, 0, n);
373
374 /* Add to and flip head if needed */
375 head = (head + n) & RQUEUEMASK;
376 total -= n;
377 qleft -= n;
378 ch->ch_rxcount += n;
379 }
380
381 /*
382 * Create a mask to determine whether we should
383 * insert the character (if any) into our queue.
384 */
385 if (ch->ch_c_iflag & IGNBRK)
386 error_mask |= UART_LSR_BI;
387
388 /*
389 * Now cleanup any leftover bytes still in the UART.
390 * Also deal with any possible queue overflow here as well.
391 */
392 while (1) {
393
394 /*
395 * Its possible we have a linestatus from the loop above
396 * this, so we "OR" on any extra bits.
397 */
398 linestatus |= readb(&ch->ch_neo_uart->lsr);
399
400 /*
401 * If the chip tells us there is no more data pending to
402 * be read, we can then leave.
403 * But before we do, cache the linestatus, just in case.
404 */
405 if (!(linestatus & UART_LSR_DR)) {
406 ch->ch_cached_lsr = linestatus;
407 break;
408 }
409
410 /* No need to store this bit */
411 linestatus &= ~UART_LSR_DR;
412
413 /*
414 * Since we are grabbing the linestatus register, which
415 * will reset some bits after our read, we need to ensure
416 * we don't miss our TX FIFO emptys.
417 */
418 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
419 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
420 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
421 }
422
423 /*
424 * Discard character if we are ignoring the error mask.
425 */
426 if (linestatus & error_mask) {
427 u8 discard;
428 linestatus = 0;
429 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
430 continue;
431 }
432
433 /*
434 * If our queue is full, we have no choice but to drop some data.
435 * The assumption is that HWFLOW or SWFLOW should have stopped
436 * things way way before we got to this point.
437 *
438 * I decided that I wanted to ditch the oldest data first,
439 * I hope thats okay with everyone? Yes? Good.
440 */
441 while (qleft < 1) {
442 jsm_dbg(READ, &ch->ch_bd->pci_dev,
443 "Queue full, dropping DATA:%x LSR:%x\n",
444 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
445
446 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
447 ch->ch_err_overrun++;
448 qleft++;
449 }
450
451 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
452 ch->ch_equeue[head] = (u8) linestatus;
453
454 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
455 ch->ch_rqueue[head], ch->ch_equeue[head]);
456
457 /* Ditch any remaining linestatus value. */
458 linestatus = 0;
459
460 /* Add to and flip head if needed */
461 head = (head + 1) & RQUEUEMASK;
462
463 qleft--;
464 ch->ch_rxcount++;
465 }
466
467 /*
468 * Write new final heads to channel structure.
469 */
470 ch->ch_r_head = head & RQUEUEMASK;
471 ch->ch_e_head = head & EQUEUEMASK;
472 jsm_input(ch);
473}
474
475static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
476{
477 u16 head;
478 u16 tail;
479 int n;
480 int s;
481 int qlen;
482 u32 len_written = 0;
483 struct circ_buf *circ;
484
485 if (!ch)
486 return;
487
488 circ = &ch->uart_port.state->xmit;
489
490 /* No data to write to the UART */
491 if (uart_circ_empty(circ))
492 return;
493
494 /* If port is "stopped", don't send any data to the UART */
495 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
496 return;
497 /*
498 * If FIFOs are disabled. Send data directly to txrx register
499 */
500 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
501 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
502
503 ch->ch_cached_lsr |= lsrbits;
504 if (ch->ch_cached_lsr & UART_LSR_THRE) {
505 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
506
507 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
508 jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
509 "Tx data: %x\n", circ->buf[circ->tail]);
510 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1);
511 ch->ch_txcount++;
512 }
513 return;
514 }
515
516 /*
517 * We have to do it this way, because of the EXAR TXFIFO count bug.
518 */
519 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
520 return;
521
522 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
523
524 /* cache head and tail of queue */
525 head = circ->head & (UART_XMIT_SIZE - 1);
526 tail = circ->tail & (UART_XMIT_SIZE - 1);
527 qlen = uart_circ_chars_pending(circ);
528
529 /* Find minimum of the FIFO space, versus queue length */
530 n = min(n, qlen);
531
532 while (n > 0) {
533
534 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
535 s = min(s, n);
536
537 if (s <= 0)
538 break;
539
540 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
541 /* Add and flip queue if needed */
542 tail = (tail + s) & (UART_XMIT_SIZE - 1);
543 n -= s;
544 ch->ch_txcount += s;
545 len_written += s;
546 }
547
548 /* Update the final tail */
549 circ->tail = tail & (UART_XMIT_SIZE - 1);
550
551 if (len_written >= ch->ch_t_tlevel)
552 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
553
554 if (uart_circ_empty(circ))
555 uart_write_wakeup(&ch->uart_port);
556}
557
558static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
559{
560 u8 msignals = signals;
561
562 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
563 "neo_parse_modem: port: %d msignals: %x\n",
564 ch->ch_portnum, msignals);
565
566 /* Scrub off lower bits. They signify delta's, which I don't care about */
567 /* Keep DDCD and DDSR though */
568 msignals &= 0xf8;
569
570 if (msignals & UART_MSR_DDCD)
571 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
572 if (msignals & UART_MSR_DDSR)
573 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
574 if (msignals & UART_MSR_DCD)
575 ch->ch_mistat |= UART_MSR_DCD;
576 else
577 ch->ch_mistat &= ~UART_MSR_DCD;
578
579 if (msignals & UART_MSR_DSR)
580 ch->ch_mistat |= UART_MSR_DSR;
581 else
582 ch->ch_mistat &= ~UART_MSR_DSR;
583
584 if (msignals & UART_MSR_RI)
585 ch->ch_mistat |= UART_MSR_RI;
586 else
587 ch->ch_mistat &= ~UART_MSR_RI;
588
589 if (msignals & UART_MSR_CTS)
590 ch->ch_mistat |= UART_MSR_CTS;
591 else
592 ch->ch_mistat &= ~UART_MSR_CTS;
593
594 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
595 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
596 ch->ch_portnum,
597 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
598 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
602 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
603}
604
605/* Make the UART raise any of the output signals we want up */
606static void neo_assert_modem_signals(struct jsm_channel *ch)
607{
608 if (!ch)
609 return;
610
611 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
612
613 /* flush write operation */
614 neo_pci_posting_flush(ch->ch_bd);
615}
616
617/*
618 * Flush the WRITE FIFO on the Neo.
619 *
620 * NOTE: Channel lock MUST be held before calling this function!
621 */
622static void neo_flush_uart_write(struct jsm_channel *ch)
623{
624 u8 tmp = 0;
625 int i = 0;
626
627 if (!ch)
628 return;
629
630 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
631
632 for (i = 0; i < 10; i++) {
633
634 /* Check to see if the UART feels it completely flushed the FIFO. */
635 tmp = readb(&ch->ch_neo_uart->isr_fcr);
636 if (tmp & UART_FCR_CLEAR_XMIT) {
637 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
638 "Still flushing TX UART... i: %d\n", i);
639 udelay(10);
640 }
641 else
642 break;
643 }
644
645 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
646}
647
648
649/*
650 * Flush the READ FIFO on the Neo.
651 *
652 * NOTE: Channel lock MUST be held before calling this function!
653 */
654static void neo_flush_uart_read(struct jsm_channel *ch)
655{
656 u8 tmp = 0;
657 int i = 0;
658
659 if (!ch)
660 return;
661
662 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
663
664 for (i = 0; i < 10; i++) {
665
666 /* Check to see if the UART feels it completely flushed the FIFO. */
667 tmp = readb(&ch->ch_neo_uart->isr_fcr);
668 if (tmp & 2) {
669 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
670 "Still flushing RX UART... i: %d\n", i);
671 udelay(10);
672 }
673 else
674 break;
675 }
676}
677
678/*
679 * No locks are assumed to be held when calling this function.
680 */
681static void neo_clear_break(struct jsm_channel *ch)
682{
683 unsigned long lock_flags;
684
685 spin_lock_irqsave(&ch->ch_lock, lock_flags);
686
687 /* Turn break off, and unset some variables */
688 if (ch->ch_flags & CH_BREAK_SENDING) {
689 u8 temp = readb(&ch->ch_neo_uart->lcr);
690 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
691
692 ch->ch_flags &= ~(CH_BREAK_SENDING);
693 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
694 "clear break Finishing UART_LCR_SBC! finished: %lx\n",
695 jiffies);
696
697 /* flush write operation */
698 neo_pci_posting_flush(ch->ch_bd);
699 }
700 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
701}
702
703/*
704 * Parse the ISR register.
705 */
706static void neo_parse_isr(struct jsm_board *brd, u32 port)
707{
708 struct jsm_channel *ch;
709 u8 isr;
710 u8 cause;
711 unsigned long lock_flags;
712
713 if (!brd)
714 return;
715
716 if (port >= brd->maxports)
717 return;
718
719 ch = brd->channels[port];
720 if (!ch)
721 return;
722
723 /* Here we try to figure out what caused the interrupt to happen */
724 while (1) {
725
726 isr = readb(&ch->ch_neo_uart->isr_fcr);
727
728 /* Bail if no pending interrupt */
729 if (isr & UART_IIR_NO_INT)
730 break;
731
732 /*
733 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
734 */
735 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
736
737 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
738 __FILE__, __LINE__, isr);
739
740 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
741 /* Read data from uart -> queue */
742 neo_copy_data_from_uart_to_queue(ch);
743
744 /* Call our tty layer to enforce queue flow control if needed. */
745 spin_lock_irqsave(&ch->ch_lock, lock_flags);
746 jsm_check_queue_flow_control(ch);
747 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
748 }
749
750 if (isr & UART_IIR_THRI) {
751 /* Transfer data (if any) from Write Queue -> UART. */
752 spin_lock_irqsave(&ch->ch_lock, lock_flags);
753 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
754 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
755 neo_copy_data_from_queue_to_uart(ch);
756 }
757
758 if (isr & UART_17158_IIR_XONXOFF) {
759 cause = readb(&ch->ch_neo_uart->xoffchar1);
760
761 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
762 "Port %d. Got ISR_XONXOFF: cause:%x\n",
763 port, cause);
764
765 /*
766 * Since the UART detected either an XON or
767 * XOFF match, we need to figure out which
768 * one it was, so we can suspend or resume data flow.
769 */
770 spin_lock_irqsave(&ch->ch_lock, lock_flags);
771 if (cause == UART_17158_XON_DETECT) {
772 /* Is output stopped right now, if so, resume it */
773 if (brd->channels[port]->ch_flags & CH_STOP) {
774 ch->ch_flags &= ~(CH_STOP);
775 }
776 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
777 "Port %d. XON detected in incoming data\n",
778 port);
779 }
780 else if (cause == UART_17158_XOFF_DETECT) {
781 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
782 ch->ch_flags |= CH_STOP;
783 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
784 "Setting CH_STOP\n");
785 }
786 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
787 "Port: %d. XOFF detected in incoming data\n",
788 port);
789 }
790 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
791 }
792
793 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
794 /*
795 * If we get here, this means the hardware is doing auto flow control.
796 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
797 */
798 cause = readb(&ch->ch_neo_uart->mcr);
799
800 /* Which pin is doing auto flow? RTS or DTR? */
801 spin_lock_irqsave(&ch->ch_lock, lock_flags);
802 if ((cause & 0x4) == 0) {
803 if (cause & UART_MCR_RTS)
804 ch->ch_mostat |= UART_MCR_RTS;
805 else
806 ch->ch_mostat &= ~(UART_MCR_RTS);
807 } else {
808 if (cause & UART_MCR_DTR)
809 ch->ch_mostat |= UART_MCR_DTR;
810 else
811 ch->ch_mostat &= ~(UART_MCR_DTR);
812 }
813 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
814 }
815
816 /* Parse any modem signal changes */
817 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
818 "MOD_STAT: sending to parse_modem_sigs\n");
819 uart_port_lock_irqsave(&ch->uart_port, &lock_flags);
820 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
821 uart_port_unlock_irqrestore(&ch->uart_port, lock_flags);
822 }
823}
824
825static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
826{
827 struct jsm_channel *ch;
828 int linestatus;
829 unsigned long lock_flags;
830
831 if (!brd)
832 return;
833
834 if (port >= brd->maxports)
835 return;
836
837 ch = brd->channels[port];
838 if (!ch)
839 return;
840
841 linestatus = readb(&ch->ch_neo_uart->lsr);
842
843 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
844 __FILE__, __LINE__, port, linestatus);
845
846 ch->ch_cached_lsr |= linestatus;
847
848 if (ch->ch_cached_lsr & UART_LSR_DR) {
849 /* Read data from uart -> queue */
850 neo_copy_data_from_uart_to_queue(ch);
851 spin_lock_irqsave(&ch->ch_lock, lock_flags);
852 jsm_check_queue_flow_control(ch);
853 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
854 }
855
856 /*
857 * This is a special flag. It indicates that at least 1
858 * RX error (parity, framing, or break) has happened.
859 * Mark this in our struct, which will tell me that I have
860 *to do the special RX+LSR read for this FIFO load.
861 */
862 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
863 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
864 "%s:%d Port: %d Got an RX error, need to parse LSR\n",
865 __FILE__, __LINE__, port);
866
867 /*
868 * The next 3 tests should *NOT* happen, as the above test
869 * should encapsulate all 3... At least, thats what Exar says.
870 */
871
872 if (linestatus & UART_LSR_PE) {
873 ch->ch_err_parity++;
874 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
875 __FILE__, __LINE__, port);
876 }
877
878 if (linestatus & UART_LSR_FE) {
879 ch->ch_err_frame++;
880 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
881 __FILE__, __LINE__, port);
882 }
883
884 if (linestatus & UART_LSR_BI) {
885 ch->ch_err_break++;
886 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
887 "%s:%d Port: %d. BRK INTR!\n",
888 __FILE__, __LINE__, port);
889 }
890
891 if (linestatus & UART_LSR_OE) {
892 /*
893 * Rx Oruns. Exar says that an orun will NOT corrupt
894 * the FIFO. It will just replace the holding register
895 * with this new data byte. So basically just ignore this.
896 * Probably we should eventually have an orun stat in our driver...
897 */
898 ch->ch_err_overrun++;
899 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
900 "%s:%d Port: %d. Rx Overrun!\n",
901 __FILE__, __LINE__, port);
902 }
903
904 if (linestatus & UART_LSR_THRE) {
905 spin_lock_irqsave(&ch->ch_lock, lock_flags);
906 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
907 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
908
909 /* Transfer data (if any) from Write Queue -> UART. */
910 neo_copy_data_from_queue_to_uart(ch);
911 }
912 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
913 spin_lock_irqsave(&ch->ch_lock, lock_flags);
914 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
915 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
916
917 /* Transfer data (if any) from Write Queue -> UART. */
918 neo_copy_data_from_queue_to_uart(ch);
919 }
920}
921
922/*
923 * neo_param()
924 * Send any/all changes to the line to the UART.
925 */
926static void neo_param(struct jsm_channel *ch)
927{
928 u8 lcr = 0;
929 u8 uart_lcr, ier;
930 u32 baud;
931 int quot;
932 struct jsm_board *bd;
933
934 bd = ch->ch_bd;
935 if (!bd)
936 return;
937
938 /*
939 * If baud rate is zero, flush queues, and set mval to drop DTR.
940 */
941 if ((ch->ch_c_cflag & CBAUD) == B0) {
942 ch->ch_r_head = ch->ch_r_tail = 0;
943 ch->ch_e_head = ch->ch_e_tail = 0;
944
945 neo_flush_uart_write(ch);
946 neo_flush_uart_read(ch);
947
948 ch->ch_flags |= (CH_BAUD0);
949 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
950 neo_assert_modem_signals(ch);
951 return;
952
953 } else {
954 int i;
955 unsigned int cflag;
956 static struct {
957 unsigned int rate;
958 unsigned int cflag;
959 } baud_rates[] = {
960 { 921600, B921600 },
961 { 460800, B460800 },
962 { 230400, B230400 },
963 { 115200, B115200 },
964 { 57600, B57600 },
965 { 38400, B38400 },
966 { 19200, B19200 },
967 { 9600, B9600 },
968 { 4800, B4800 },
969 { 2400, B2400 },
970 { 1200, B1200 },
971 { 600, B600 },
972 { 300, B300 },
973 { 200, B200 },
974 { 150, B150 },
975 { 134, B134 },
976 { 110, B110 },
977 { 75, B75 },
978 { 50, B50 },
979 };
980
981 cflag = C_BAUD(ch->uart_port.state->port.tty);
982 baud = 9600;
983 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
984 if (baud_rates[i].cflag == cflag) {
985 baud = baud_rates[i].rate;
986 break;
987 }
988 }
989
990 if (ch->ch_flags & CH_BAUD0)
991 ch->ch_flags &= ~(CH_BAUD0);
992 }
993
994 if (ch->ch_c_cflag & PARENB)
995 lcr |= UART_LCR_PARITY;
996
997 if (!(ch->ch_c_cflag & PARODD))
998 lcr |= UART_LCR_EPAR;
999
1000 if (ch->ch_c_cflag & CMSPAR)
1001 lcr |= UART_LCR_SPAR;
1002
1003 if (ch->ch_c_cflag & CSTOPB)
1004 lcr |= UART_LCR_STOP;
1005
1006 lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag));
1007
1008 ier = readb(&ch->ch_neo_uart->ier);
1009 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1010
1011 quot = ch->ch_bd->bd_dividend / baud;
1012
1013 if (quot != 0) {
1014 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1015 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1016 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1017 writeb(lcr, &ch->ch_neo_uart->lcr);
1018 }
1019
1020 if (uart_lcr != lcr)
1021 writeb(lcr, &ch->ch_neo_uart->lcr);
1022
1023 if (ch->ch_c_cflag & CREAD)
1024 ier |= (UART_IER_RDI | UART_IER_RLSI);
1025
1026 ier |= (UART_IER_THRI | UART_IER_MSI);
1027
1028 writeb(ier, &ch->ch_neo_uart->ier);
1029
1030 /* Set new start/stop chars */
1031 neo_set_new_start_stop_chars(ch);
1032
1033 if (ch->ch_c_cflag & CRTSCTS)
1034 neo_set_cts_flow_control(ch);
1035 else if (ch->ch_c_iflag & IXON) {
1036 /* If start/stop is set to disable, then we should disable flow control */
1037 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1038 neo_set_no_output_flow_control(ch);
1039 else
1040 neo_set_ixon_flow_control(ch);
1041 }
1042 else
1043 neo_set_no_output_flow_control(ch);
1044
1045 if (ch->ch_c_cflag & CRTSCTS)
1046 neo_set_rts_flow_control(ch);
1047 else if (ch->ch_c_iflag & IXOFF) {
1048 /* If start/stop is set to disable, then we should disable flow control */
1049 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1050 neo_set_no_input_flow_control(ch);
1051 else
1052 neo_set_ixoff_flow_control(ch);
1053 }
1054 else
1055 neo_set_no_input_flow_control(ch);
1056 /*
1057 * Adjust the RX FIFO Trigger level if baud is less than 9600.
1058 * Not exactly elegant, but this is needed because of the Exar chip's
1059 * delay on firing off the RX FIFO interrupt on slower baud rates.
1060 */
1061 if (baud < 9600) {
1062 writeb(1, &ch->ch_neo_uart->rfifo);
1063 ch->ch_r_tlevel = 1;
1064 }
1065
1066 neo_assert_modem_signals(ch);
1067
1068 /* Get current status of the modem signals now */
1069 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1070 return;
1071}
1072
1073/*
1074 * jsm_neo_intr()
1075 *
1076 * Neo specific interrupt handler.
1077 */
1078static irqreturn_t neo_intr(int irq, void *voidbrd)
1079{
1080 struct jsm_board *brd = voidbrd;
1081 struct jsm_channel *ch;
1082 int port = 0;
1083 int type = 0;
1084 int current_port;
1085 u32 tmp;
1086 u32 uart_poll;
1087 unsigned long lock_flags;
1088 unsigned long lock_flags2;
1089 int outofloop_count = 0;
1090
1091 /* Lock out the slow poller from running on this board. */
1092 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1093
1094 /*
1095 * Read in "extended" IRQ information from the 32bit Neo register.
1096 * Bits 0-7: What port triggered the interrupt.
1097 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1098 */
1099 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1100
1101 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
1102 __FILE__, __LINE__, uart_poll);
1103
1104 if (!uart_poll) {
1105 jsm_dbg(INTR, &brd->pci_dev,
1106 "Kernel interrupted to me, but no pending interrupts...\n");
1107 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1108 return IRQ_NONE;
1109 }
1110
1111 /* At this point, we have at least SOMETHING to service, dig further... */
1112
1113 current_port = 0;
1114
1115 /* Loop on each port */
1116 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1117
1118 tmp = uart_poll;
1119 outofloop_count++;
1120
1121 /* Check current port to see if it has interrupt pending */
1122 if ((tmp & jsm_offset_table[current_port]) != 0) {
1123 port = current_port;
1124 type = tmp >> (8 + (port * 3));
1125 type &= 0x7;
1126 } else {
1127 current_port++;
1128 continue;
1129 }
1130
1131 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n",
1132 __FILE__, __LINE__, port, type);
1133
1134 /* Remove this port + type from uart_poll */
1135 uart_poll &= ~(jsm_offset_table[port]);
1136
1137 if (!type) {
1138 /* If no type, just ignore it, and move onto next port */
1139 jsm_dbg(INTR, &brd->pci_dev,
1140 "Interrupt with no type! port: %d\n", port);
1141 continue;
1142 }
1143
1144 /* Switch on type of interrupt we have */
1145 switch (type) {
1146
1147 case UART_17158_RXRDY_TIMEOUT:
1148 /*
1149 * RXRDY Time-out is cleared by reading data in the
1150 * RX FIFO until it falls below the trigger level.
1151 */
1152
1153 /* Verify the port is in range. */
1154 if (port >= brd->nasync)
1155 continue;
1156
1157 ch = brd->channels[port];
1158 if (!ch)
1159 continue;
1160
1161 neo_copy_data_from_uart_to_queue(ch);
1162
1163 /* Call our tty layer to enforce queue flow control if needed. */
1164 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1165 jsm_check_queue_flow_control(ch);
1166 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1167
1168 continue;
1169
1170 case UART_17158_RX_LINE_STATUS:
1171 /*
1172 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1173 */
1174 neo_parse_lsr(brd, port);
1175 continue;
1176
1177 case UART_17158_TXRDY:
1178 /*
1179 * TXRDY interrupt clears after reading ISR register for the UART channel.
1180 */
1181
1182 /*
1183 * Yes, this is odd...
1184 * Why would I check EVERY possibility of type of
1185 * interrupt, when we know its TXRDY???
1186 * Becuz for some reason, even tho we got triggered for TXRDY,
1187 * it seems to be occasionally wrong. Instead of TX, which
1188 * it should be, I was getting things like RXDY too. Weird.
1189 */
1190 neo_parse_isr(brd, port);
1191 continue;
1192
1193 case UART_17158_MSR:
1194 /*
1195 * MSR or flow control was seen.
1196 */
1197 neo_parse_isr(brd, port);
1198 continue;
1199
1200 default:
1201 /*
1202 * The UART triggered us with a bogus interrupt type.
1203 * It appears the Exar chip, when REALLY bogged down, will throw
1204 * these once and awhile.
1205 * Its harmless, just ignore it and move on.
1206 */
1207 jsm_dbg(INTR, &brd->pci_dev,
1208 "%s:%d Unknown Interrupt type: %x\n",
1209 __FILE__, __LINE__, type);
1210 continue;
1211 }
1212 }
1213
1214 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1215
1216 jsm_dbg(INTR, &brd->pci_dev, "finish\n");
1217 return IRQ_HANDLED;
1218}
1219
1220/*
1221 * Neo specific way of turning off the receiver.
1222 * Used as a way to enforce queue flow control when in
1223 * hardware flow control mode.
1224 */
1225static void neo_disable_receiver(struct jsm_channel *ch)
1226{
1227 u8 tmp = readb(&ch->ch_neo_uart->ier);
1228 tmp &= ~(UART_IER_RDI);
1229 writeb(tmp, &ch->ch_neo_uart->ier);
1230
1231 /* flush write operation */
1232 neo_pci_posting_flush(ch->ch_bd);
1233}
1234
1235
1236/*
1237 * Neo specific way of turning on the receiver.
1238 * Used as a way to un-enforce queue flow control when in
1239 * hardware flow control mode.
1240 */
1241static void neo_enable_receiver(struct jsm_channel *ch)
1242{
1243 u8 tmp = readb(&ch->ch_neo_uart->ier);
1244 tmp |= (UART_IER_RDI);
1245 writeb(tmp, &ch->ch_neo_uart->ier);
1246
1247 /* flush write operation */
1248 neo_pci_posting_flush(ch->ch_bd);
1249}
1250
1251static void neo_send_start_character(struct jsm_channel *ch)
1252{
1253 if (!ch)
1254 return;
1255
1256 if (ch->ch_startc != __DISABLED_CHAR) {
1257 ch->ch_xon_sends++;
1258 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1259
1260 /* flush write operation */
1261 neo_pci_posting_flush(ch->ch_bd);
1262 }
1263}
1264
1265static void neo_send_stop_character(struct jsm_channel *ch)
1266{
1267 if (!ch)
1268 return;
1269
1270 if (ch->ch_stopc != __DISABLED_CHAR) {
1271 ch->ch_xoff_sends++;
1272 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1273
1274 /* flush write operation */
1275 neo_pci_posting_flush(ch->ch_bd);
1276 }
1277}
1278
1279/*
1280 * neo_uart_init
1281 */
1282static void neo_uart_init(struct jsm_channel *ch)
1283{
1284 writeb(0, &ch->ch_neo_uart->ier);
1285 writeb(0, &ch->ch_neo_uart->efr);
1286 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1287
1288 /* Clear out UART and FIFO */
1289 readb(&ch->ch_neo_uart->txrx);
1290 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1291 readb(&ch->ch_neo_uart->lsr);
1292 readb(&ch->ch_neo_uart->msr);
1293
1294 ch->ch_flags |= CH_FIFO_ENABLED;
1295
1296 /* Assert any signals we want up */
1297 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1298}
1299
1300/*
1301 * Make the UART completely turn off.
1302 */
1303static void neo_uart_off(struct jsm_channel *ch)
1304{
1305 /* Turn off UART enhanced bits */
1306 writeb(0, &ch->ch_neo_uart->efr);
1307
1308 /* Stop all interrupts from occurring. */
1309 writeb(0, &ch->ch_neo_uart->ier);
1310}
1311
1312/* Channel lock MUST be held by the calling function! */
1313static void neo_send_break(struct jsm_channel *ch)
1314{
1315 /*
1316 * Set the time we should stop sending the break.
1317 * If we are already sending a break, toss away the existing
1318 * time to stop, and use this new value instead.
1319 */
1320
1321 /* Tell the UART to start sending the break */
1322 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1323 u8 temp = readb(&ch->ch_neo_uart->lcr);
1324 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1325 ch->ch_flags |= (CH_BREAK_SENDING);
1326
1327 /* flush write operation */
1328 neo_pci_posting_flush(ch->ch_bd);
1329 }
1330}
1331
1332struct board_ops jsm_neo_ops = {
1333 .intr = neo_intr,
1334 .uart_init = neo_uart_init,
1335 .uart_off = neo_uart_off,
1336 .param = neo_param,
1337 .assert_modem_signals = neo_assert_modem_signals,
1338 .flush_uart_write = neo_flush_uart_write,
1339 .flush_uart_read = neo_flush_uart_read,
1340 .disable_receiver = neo_disable_receiver,
1341 .enable_receiver = neo_enable_receiver,
1342 .send_break = neo_send_break,
1343 .clear_break = neo_clear_break,
1344 .send_start_character = neo_send_start_character,
1345 .send_stop_character = neo_send_stop_character,
1346 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
1347};
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * Contact Information:
17 * Scott H Kilau <Scott_Kilau@digi.com>
18 * Wendy Xiong <wendyx@us.ibm.com>
19 *
20 ***********************************************************************/
21#include <linux/delay.h> /* For udelay */
22#include <linux/serial_reg.h> /* For the various UART offsets */
23#include <linux/tty.h>
24#include <linux/pci.h>
25#include <asm/io.h>
26
27#include "jsm.h" /* Driver main header file */
28
29static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
30
31/*
32 * This function allows calls to ensure that all outstanding
33 * PCI writes have been completed, by doing a PCI read against
34 * a non-destructive, read-only location on the Neo card.
35 *
36 * In this case, we are reading the DVID (Read-only Device Identification)
37 * value of the Neo card.
38 */
39static inline void neo_pci_posting_flush(struct jsm_board *bd)
40{
41 readb(bd->re_map_membase + 0x8D);
42}
43
44static void neo_set_cts_flow_control(struct jsm_channel *ch)
45{
46 u8 ier, efr;
47 ier = readb(&ch->ch_neo_uart->ier);
48 efr = readb(&ch->ch_neo_uart->efr);
49
50 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
51
52 /* Turn on auto CTS flow control */
53 ier |= (UART_17158_IER_CTSDSR);
54 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
55
56 /* Turn off auto Xon flow control */
57 efr &= ~(UART_17158_EFR_IXON);
58
59 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
60 writeb(0, &ch->ch_neo_uart->efr);
61
62 /* Turn on UART enhanced bits */
63 writeb(efr, &ch->ch_neo_uart->efr);
64
65 /* Turn on table D, with 8 char hi/low watermarks */
66 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
67
68 /* Feed the UART our trigger levels */
69 writeb(8, &ch->ch_neo_uart->tfifo);
70 ch->ch_t_tlevel = 8;
71
72 writeb(ier, &ch->ch_neo_uart->ier);
73}
74
75static void neo_set_rts_flow_control(struct jsm_channel *ch)
76{
77 u8 ier, efr;
78 ier = readb(&ch->ch_neo_uart->ier);
79 efr = readb(&ch->ch_neo_uart->efr);
80
81 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
82
83 /* Turn on auto RTS flow control */
84 ier |= (UART_17158_IER_RTSDTR);
85 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
86
87 /* Turn off auto Xoff flow control */
88 ier &= ~(UART_17158_IER_XOFF);
89 efr &= ~(UART_17158_EFR_IXOFF);
90
91 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
92 writeb(0, &ch->ch_neo_uart->efr);
93
94 /* Turn on UART enhanced bits */
95 writeb(efr, &ch->ch_neo_uart->efr);
96
97 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
98 ch->ch_r_watermark = 4;
99
100 writeb(56, &ch->ch_neo_uart->rfifo);
101 ch->ch_r_tlevel = 56;
102
103 writeb(ier, &ch->ch_neo_uart->ier);
104
105 /*
106 * From the Neo UART spec sheet:
107 * The auto RTS/DTR function must be started by asserting
108 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
109 * it is enabled.
110 */
111 ch->ch_mostat |= (UART_MCR_RTS);
112}
113
114
115static void neo_set_ixon_flow_control(struct jsm_channel *ch)
116{
117 u8 ier, efr;
118 ier = readb(&ch->ch_neo_uart->ier);
119 efr = readb(&ch->ch_neo_uart->efr);
120
121 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
122
123 /* Turn off auto CTS flow control */
124 ier &= ~(UART_17158_IER_CTSDSR);
125 efr &= ~(UART_17158_EFR_CTSDSR);
126
127 /* Turn on auto Xon flow control */
128 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
129
130 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
131 writeb(0, &ch->ch_neo_uart->efr);
132
133 /* Turn on UART enhanced bits */
134 writeb(efr, &ch->ch_neo_uart->efr);
135
136 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
137 ch->ch_r_watermark = 4;
138
139 writeb(32, &ch->ch_neo_uart->rfifo);
140 ch->ch_r_tlevel = 32;
141
142 /* Tell UART what start/stop chars it should be looking for */
143 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
144 writeb(0, &ch->ch_neo_uart->xonchar2);
145
146 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
147 writeb(0, &ch->ch_neo_uart->xoffchar2);
148
149 writeb(ier, &ch->ch_neo_uart->ier);
150}
151
152static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
153{
154 u8 ier, efr;
155 ier = readb(&ch->ch_neo_uart->ier);
156 efr = readb(&ch->ch_neo_uart->efr);
157
158 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
159
160 /* Turn off auto RTS flow control */
161 ier &= ~(UART_17158_IER_RTSDTR);
162 efr &= ~(UART_17158_EFR_RTSDTR);
163
164 /* Turn on auto Xoff flow control */
165 ier |= (UART_17158_IER_XOFF);
166 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
167
168 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
169 writeb(0, &ch->ch_neo_uart->efr);
170
171 /* Turn on UART enhanced bits */
172 writeb(efr, &ch->ch_neo_uart->efr);
173
174 /* Turn on table D, with 8 char hi/low watermarks */
175 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
176
177 writeb(8, &ch->ch_neo_uart->tfifo);
178 ch->ch_t_tlevel = 8;
179
180 /* Tell UART what start/stop chars it should be looking for */
181 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
182 writeb(0, &ch->ch_neo_uart->xonchar2);
183
184 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
185 writeb(0, &ch->ch_neo_uart->xoffchar2);
186
187 writeb(ier, &ch->ch_neo_uart->ier);
188}
189
190static void neo_set_no_input_flow_control(struct jsm_channel *ch)
191{
192 u8 ier, efr;
193 ier = readb(&ch->ch_neo_uart->ier);
194 efr = readb(&ch->ch_neo_uart->efr);
195
196 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
197
198 /* Turn off auto RTS flow control */
199 ier &= ~(UART_17158_IER_RTSDTR);
200 efr &= ~(UART_17158_EFR_RTSDTR);
201
202 /* Turn off auto Xoff flow control */
203 ier &= ~(UART_17158_IER_XOFF);
204 if (ch->ch_c_iflag & IXON)
205 efr &= ~(UART_17158_EFR_IXOFF);
206 else
207 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
208
209 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
210 writeb(0, &ch->ch_neo_uart->efr);
211
212 /* Turn on UART enhanced bits */
213 writeb(efr, &ch->ch_neo_uart->efr);
214
215 /* Turn on table D, with 8 char hi/low watermarks */
216 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
217
218 ch->ch_r_watermark = 0;
219
220 writeb(16, &ch->ch_neo_uart->tfifo);
221 ch->ch_t_tlevel = 16;
222
223 writeb(16, &ch->ch_neo_uart->rfifo);
224 ch->ch_r_tlevel = 16;
225
226 writeb(ier, &ch->ch_neo_uart->ier);
227}
228
229static void neo_set_no_output_flow_control(struct jsm_channel *ch)
230{
231 u8 ier, efr;
232 ier = readb(&ch->ch_neo_uart->ier);
233 efr = readb(&ch->ch_neo_uart->efr);
234
235 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
236
237 /* Turn off auto CTS flow control */
238 ier &= ~(UART_17158_IER_CTSDSR);
239 efr &= ~(UART_17158_EFR_CTSDSR);
240
241 /* Turn off auto Xon flow control */
242 if (ch->ch_c_iflag & IXOFF)
243 efr &= ~(UART_17158_EFR_IXON);
244 else
245 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
246
247 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
248 writeb(0, &ch->ch_neo_uart->efr);
249
250 /* Turn on UART enhanced bits */
251 writeb(efr, &ch->ch_neo_uart->efr);
252
253 /* Turn on table D, with 8 char hi/low watermarks */
254 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
255
256 ch->ch_r_watermark = 0;
257
258 writeb(16, &ch->ch_neo_uart->tfifo);
259 ch->ch_t_tlevel = 16;
260
261 writeb(16, &ch->ch_neo_uart->rfifo);
262 ch->ch_r_tlevel = 16;
263
264 writeb(ier, &ch->ch_neo_uart->ier);
265}
266
267static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
268{
269
270 /* if hardware flow control is set, then skip this whole thing */
271 if (ch->ch_c_cflag & CRTSCTS)
272 return;
273
274 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
275
276 /* Tell UART what start/stop chars it should be looking for */
277 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
278 writeb(0, &ch->ch_neo_uart->xonchar2);
279
280 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
281 writeb(0, &ch->ch_neo_uart->xoffchar2);
282}
283
284static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
285{
286 int qleft = 0;
287 u8 linestatus = 0;
288 u8 error_mask = 0;
289 int n = 0;
290 int total = 0;
291 u16 head;
292 u16 tail;
293
294 if (!ch)
295 return;
296
297 /* cache head and tail of queue */
298 head = ch->ch_r_head & RQUEUEMASK;
299 tail = ch->ch_r_tail & RQUEUEMASK;
300
301 /* Get our cached LSR */
302 linestatus = ch->ch_cached_lsr;
303 ch->ch_cached_lsr = 0;
304
305 /* Store how much space we have left in the queue */
306 if ((qleft = tail - head - 1) < 0)
307 qleft += RQUEUEMASK + 1;
308
309 /*
310 * If the UART is not in FIFO mode, force the FIFO copy to
311 * NOT be run, by setting total to 0.
312 *
313 * On the other hand, if the UART IS in FIFO mode, then ask
314 * the UART to give us an approximation of data it has RX'ed.
315 */
316 if (!(ch->ch_flags & CH_FIFO_ENABLED))
317 total = 0;
318 else {
319 total = readb(&ch->ch_neo_uart->rfifo);
320
321 /*
322 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
323 *
324 * This resolves a problem/bug with the Exar chip that sometimes
325 * returns a bogus value in the rfifo register.
326 * The count can be any where from 0-3 bytes "off".
327 * Bizarre, but true.
328 */
329 total -= 3;
330 }
331
332 /*
333 * Finally, bound the copy to make sure we don't overflow
334 * our own queue...
335 * The byte by byte copy loop below this loop this will
336 * deal with the queue overflow possibility.
337 */
338 total = min(total, qleft);
339
340 while (total > 0) {
341 /*
342 * Grab the linestatus register, we need to check
343 * to see if there are any errors in the FIFO.
344 */
345 linestatus = readb(&ch->ch_neo_uart->lsr);
346
347 /*
348 * Break out if there is a FIFO error somewhere.
349 * This will allow us to go byte by byte down below,
350 * finding the exact location of the error.
351 */
352 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
353 break;
354
355 /* Make sure we don't go over the end of our queue */
356 n = min(((u32) total), (RQUEUESIZE - (u32) head));
357
358 /*
359 * Cut down n even further if needed, this is to fix
360 * a problem with memcpy_fromio() with the Neo on the
361 * IBM pSeries platform.
362 * 15 bytes max appears to be the magic number.
363 */
364 n = min((u32) n, (u32) 12);
365
366 /*
367 * Since we are grabbing the linestatus register, which
368 * will reset some bits after our read, we need to ensure
369 * we don't miss our TX FIFO emptys.
370 */
371 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
372 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
373
374 linestatus = 0;
375
376 /* Copy data from uart to the queue */
377 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
378 /*
379 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
380 * that all the data currently in the FIFO is free of
381 * breaks and parity/frame/orun errors.
382 */
383 memset(ch->ch_equeue + head, 0, n);
384
385 /* Add to and flip head if needed */
386 head = (head + n) & RQUEUEMASK;
387 total -= n;
388 qleft -= n;
389 ch->ch_rxcount += n;
390 }
391
392 /*
393 * Create a mask to determine whether we should
394 * insert the character (if any) into our queue.
395 */
396 if (ch->ch_c_iflag & IGNBRK)
397 error_mask |= UART_LSR_BI;
398
399 /*
400 * Now cleanup any leftover bytes still in the UART.
401 * Also deal with any possible queue overflow here as well.
402 */
403 while (1) {
404
405 /*
406 * Its possible we have a linestatus from the loop above
407 * this, so we "OR" on any extra bits.
408 */
409 linestatus |= readb(&ch->ch_neo_uart->lsr);
410
411 /*
412 * If the chip tells us there is no more data pending to
413 * be read, we can then leave.
414 * But before we do, cache the linestatus, just in case.
415 */
416 if (!(linestatus & UART_LSR_DR)) {
417 ch->ch_cached_lsr = linestatus;
418 break;
419 }
420
421 /* No need to store this bit */
422 linestatus &= ~UART_LSR_DR;
423
424 /*
425 * Since we are grabbing the linestatus register, which
426 * will reset some bits after our read, we need to ensure
427 * we don't miss our TX FIFO emptys.
428 */
429 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
430 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
431 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
432 }
433
434 /*
435 * Discard character if we are ignoring the error mask.
436 */
437 if (linestatus & error_mask) {
438 u8 discard;
439 linestatus = 0;
440 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
441 continue;
442 }
443
444 /*
445 * If our queue is full, we have no choice but to drop some data.
446 * The assumption is that HWFLOW or SWFLOW should have stopped
447 * things way way before we got to this point.
448 *
449 * I decided that I wanted to ditch the oldest data first,
450 * I hope thats okay with everyone? Yes? Good.
451 */
452 while (qleft < 1) {
453 jsm_dbg(READ, &ch->ch_bd->pci_dev,
454 "Queue full, dropping DATA:%x LSR:%x\n",
455 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
456
457 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
458 ch->ch_err_overrun++;
459 qleft++;
460 }
461
462 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
463 ch->ch_equeue[head] = (u8) linestatus;
464
465 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
466 ch->ch_rqueue[head], ch->ch_equeue[head]);
467
468 /* Ditch any remaining linestatus value. */
469 linestatus = 0;
470
471 /* Add to and flip head if needed */
472 head = (head + 1) & RQUEUEMASK;
473
474 qleft--;
475 ch->ch_rxcount++;
476 }
477
478 /*
479 * Write new final heads to channel structure.
480 */
481 ch->ch_r_head = head & RQUEUEMASK;
482 ch->ch_e_head = head & EQUEUEMASK;
483 jsm_input(ch);
484}
485
486static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
487{
488 u16 head;
489 u16 tail;
490 int n;
491 int s;
492 int qlen;
493 u32 len_written = 0;
494 struct circ_buf *circ;
495
496 if (!ch)
497 return;
498
499 circ = &ch->uart_port.state->xmit;
500
501 /* No data to write to the UART */
502 if (uart_circ_empty(circ))
503 return;
504
505 /* If port is "stopped", don't send any data to the UART */
506 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
507 return;
508 /*
509 * If FIFOs are disabled. Send data directly to txrx register
510 */
511 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
512 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
513
514 ch->ch_cached_lsr |= lsrbits;
515 if (ch->ch_cached_lsr & UART_LSR_THRE) {
516 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
517
518 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
519 jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
520 "Tx data: %x\n", circ->buf[circ->tail]);
521 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1);
522 ch->ch_txcount++;
523 }
524 return;
525 }
526
527 /*
528 * We have to do it this way, because of the EXAR TXFIFO count bug.
529 */
530 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
531 return;
532
533 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
534
535 /* cache head and tail of queue */
536 head = circ->head & (UART_XMIT_SIZE - 1);
537 tail = circ->tail & (UART_XMIT_SIZE - 1);
538 qlen = uart_circ_chars_pending(circ);
539
540 /* Find minimum of the FIFO space, versus queue length */
541 n = min(n, qlen);
542
543 while (n > 0) {
544
545 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
546 s = min(s, n);
547
548 if (s <= 0)
549 break;
550
551 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
552 /* Add and flip queue if needed */
553 tail = (tail + s) & (UART_XMIT_SIZE - 1);
554 n -= s;
555 ch->ch_txcount += s;
556 len_written += s;
557 }
558
559 /* Update the final tail */
560 circ->tail = tail & (UART_XMIT_SIZE - 1);
561
562 if (len_written >= ch->ch_t_tlevel)
563 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
564
565 if (uart_circ_empty(circ))
566 uart_write_wakeup(&ch->uart_port);
567}
568
569static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
570{
571 u8 msignals = signals;
572
573 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
574 "neo_parse_modem: port: %d msignals: %x\n",
575 ch->ch_portnum, msignals);
576
577 /* Scrub off lower bits. They signify delta's, which I don't care about */
578 /* Keep DDCD and DDSR though */
579 msignals &= 0xf8;
580
581 if (msignals & UART_MSR_DDCD)
582 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
583 if (msignals & UART_MSR_DDSR)
584 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
585 if (msignals & UART_MSR_DCD)
586 ch->ch_mistat |= UART_MSR_DCD;
587 else
588 ch->ch_mistat &= ~UART_MSR_DCD;
589
590 if (msignals & UART_MSR_DSR)
591 ch->ch_mistat |= UART_MSR_DSR;
592 else
593 ch->ch_mistat &= ~UART_MSR_DSR;
594
595 if (msignals & UART_MSR_RI)
596 ch->ch_mistat |= UART_MSR_RI;
597 else
598 ch->ch_mistat &= ~UART_MSR_RI;
599
600 if (msignals & UART_MSR_CTS)
601 ch->ch_mistat |= UART_MSR_CTS;
602 else
603 ch->ch_mistat &= ~UART_MSR_CTS;
604
605 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
606 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
607 ch->ch_portnum,
608 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
609 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
610 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
611 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
612 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
613 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
614}
615
616/* Make the UART raise any of the output signals we want up */
617static void neo_assert_modem_signals(struct jsm_channel *ch)
618{
619 if (!ch)
620 return;
621
622 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
623
624 /* flush write operation */
625 neo_pci_posting_flush(ch->ch_bd);
626}
627
628/*
629 * Flush the WRITE FIFO on the Neo.
630 *
631 * NOTE: Channel lock MUST be held before calling this function!
632 */
633static void neo_flush_uart_write(struct jsm_channel *ch)
634{
635 u8 tmp = 0;
636 int i = 0;
637
638 if (!ch)
639 return;
640
641 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
642
643 for (i = 0; i < 10; i++) {
644
645 /* Check to see if the UART feels it completely flushed the FIFO. */
646 tmp = readb(&ch->ch_neo_uart->isr_fcr);
647 if (tmp & UART_FCR_CLEAR_XMIT) {
648 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
649 "Still flushing TX UART... i: %d\n", i);
650 udelay(10);
651 }
652 else
653 break;
654 }
655
656 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
657}
658
659
660/*
661 * Flush the READ FIFO on the Neo.
662 *
663 * NOTE: Channel lock MUST be held before calling this function!
664 */
665static void neo_flush_uart_read(struct jsm_channel *ch)
666{
667 u8 tmp = 0;
668 int i = 0;
669
670 if (!ch)
671 return;
672
673 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
674
675 for (i = 0; i < 10; i++) {
676
677 /* Check to see if the UART feels it completely flushed the FIFO. */
678 tmp = readb(&ch->ch_neo_uart->isr_fcr);
679 if (tmp & 2) {
680 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
681 "Still flushing RX UART... i: %d\n", i);
682 udelay(10);
683 }
684 else
685 break;
686 }
687}
688
689/*
690 * No locks are assumed to be held when calling this function.
691 */
692static void neo_clear_break(struct jsm_channel *ch)
693{
694 unsigned long lock_flags;
695
696 spin_lock_irqsave(&ch->ch_lock, lock_flags);
697
698 /* Turn break off, and unset some variables */
699 if (ch->ch_flags & CH_BREAK_SENDING) {
700 u8 temp = readb(&ch->ch_neo_uart->lcr);
701 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
702
703 ch->ch_flags &= ~(CH_BREAK_SENDING);
704 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
705 "clear break Finishing UART_LCR_SBC! finished: %lx\n",
706 jiffies);
707
708 /* flush write operation */
709 neo_pci_posting_flush(ch->ch_bd);
710 }
711 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
712}
713
714/*
715 * Parse the ISR register.
716 */
717static void neo_parse_isr(struct jsm_board *brd, u32 port)
718{
719 struct jsm_channel *ch;
720 u8 isr;
721 u8 cause;
722 unsigned long lock_flags;
723
724 if (!brd)
725 return;
726
727 if (port >= brd->maxports)
728 return;
729
730 ch = brd->channels[port];
731 if (!ch)
732 return;
733
734 /* Here we try to figure out what caused the interrupt to happen */
735 while (1) {
736
737 isr = readb(&ch->ch_neo_uart->isr_fcr);
738
739 /* Bail if no pending interrupt */
740 if (isr & UART_IIR_NO_INT)
741 break;
742
743 /*
744 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
745 */
746 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
747
748 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
749 __FILE__, __LINE__, isr);
750
751 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
752 /* Read data from uart -> queue */
753 neo_copy_data_from_uart_to_queue(ch);
754
755 /* Call our tty layer to enforce queue flow control if needed. */
756 spin_lock_irqsave(&ch->ch_lock, lock_flags);
757 jsm_check_queue_flow_control(ch);
758 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
759 }
760
761 if (isr & UART_IIR_THRI) {
762 /* Transfer data (if any) from Write Queue -> UART. */
763 spin_lock_irqsave(&ch->ch_lock, lock_flags);
764 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
765 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
766 neo_copy_data_from_queue_to_uart(ch);
767 }
768
769 if (isr & UART_17158_IIR_XONXOFF) {
770 cause = readb(&ch->ch_neo_uart->xoffchar1);
771
772 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
773 "Port %d. Got ISR_XONXOFF: cause:%x\n",
774 port, cause);
775
776 /*
777 * Since the UART detected either an XON or
778 * XOFF match, we need to figure out which
779 * one it was, so we can suspend or resume data flow.
780 */
781 spin_lock_irqsave(&ch->ch_lock, lock_flags);
782 if (cause == UART_17158_XON_DETECT) {
783 /* Is output stopped right now, if so, resume it */
784 if (brd->channels[port]->ch_flags & CH_STOP) {
785 ch->ch_flags &= ~(CH_STOP);
786 }
787 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
788 "Port %d. XON detected in incoming data\n",
789 port);
790 }
791 else if (cause == UART_17158_XOFF_DETECT) {
792 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
793 ch->ch_flags |= CH_STOP;
794 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
795 "Setting CH_STOP\n");
796 }
797 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
798 "Port: %d. XOFF detected in incoming data\n",
799 port);
800 }
801 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
802 }
803
804 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
805 /*
806 * If we get here, this means the hardware is doing auto flow control.
807 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
808 */
809 cause = readb(&ch->ch_neo_uart->mcr);
810
811 /* Which pin is doing auto flow? RTS or DTR? */
812 spin_lock_irqsave(&ch->ch_lock, lock_flags);
813 if ((cause & 0x4) == 0) {
814 if (cause & UART_MCR_RTS)
815 ch->ch_mostat |= UART_MCR_RTS;
816 else
817 ch->ch_mostat &= ~(UART_MCR_RTS);
818 } else {
819 if (cause & UART_MCR_DTR)
820 ch->ch_mostat |= UART_MCR_DTR;
821 else
822 ch->ch_mostat &= ~(UART_MCR_DTR);
823 }
824 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
825 }
826
827 /* Parse any modem signal changes */
828 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
829 "MOD_STAT: sending to parse_modem_sigs\n");
830 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
831 }
832}
833
834static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
835{
836 struct jsm_channel *ch;
837 int linestatus;
838 unsigned long lock_flags;
839
840 if (!brd)
841 return;
842
843 if (port >= brd->maxports)
844 return;
845
846 ch = brd->channels[port];
847 if (!ch)
848 return;
849
850 linestatus = readb(&ch->ch_neo_uart->lsr);
851
852 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
853 __FILE__, __LINE__, port, linestatus);
854
855 ch->ch_cached_lsr |= linestatus;
856
857 if (ch->ch_cached_lsr & UART_LSR_DR) {
858 /* Read data from uart -> queue */
859 neo_copy_data_from_uart_to_queue(ch);
860 spin_lock_irqsave(&ch->ch_lock, lock_flags);
861 jsm_check_queue_flow_control(ch);
862 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
863 }
864
865 /*
866 * This is a special flag. It indicates that at least 1
867 * RX error (parity, framing, or break) has happened.
868 * Mark this in our struct, which will tell me that I have
869 *to do the special RX+LSR read for this FIFO load.
870 */
871 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
872 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
873 "%s:%d Port: %d Got an RX error, need to parse LSR\n",
874 __FILE__, __LINE__, port);
875
876 /*
877 * The next 3 tests should *NOT* happen, as the above test
878 * should encapsulate all 3... At least, thats what Exar says.
879 */
880
881 if (linestatus & UART_LSR_PE) {
882 ch->ch_err_parity++;
883 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
884 __FILE__, __LINE__, port);
885 }
886
887 if (linestatus & UART_LSR_FE) {
888 ch->ch_err_frame++;
889 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
890 __FILE__, __LINE__, port);
891 }
892
893 if (linestatus & UART_LSR_BI) {
894 ch->ch_err_break++;
895 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
896 "%s:%d Port: %d. BRK INTR!\n",
897 __FILE__, __LINE__, port);
898 }
899
900 if (linestatus & UART_LSR_OE) {
901 /*
902 * Rx Oruns. Exar says that an orun will NOT corrupt
903 * the FIFO. It will just replace the holding register
904 * with this new data byte. So basically just ignore this.
905 * Probably we should eventually have an orun stat in our driver...
906 */
907 ch->ch_err_overrun++;
908 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
909 "%s:%d Port: %d. Rx Overrun!\n",
910 __FILE__, __LINE__, port);
911 }
912
913 if (linestatus & UART_LSR_THRE) {
914 spin_lock_irqsave(&ch->ch_lock, lock_flags);
915 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
916 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
917
918 /* Transfer data (if any) from Write Queue -> UART. */
919 neo_copy_data_from_queue_to_uart(ch);
920 }
921 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
922 spin_lock_irqsave(&ch->ch_lock, lock_flags);
923 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
924 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
925
926 /* Transfer data (if any) from Write Queue -> UART. */
927 neo_copy_data_from_queue_to_uart(ch);
928 }
929}
930
931/*
932 * neo_param()
933 * Send any/all changes to the line to the UART.
934 */
935static void neo_param(struct jsm_channel *ch)
936{
937 u8 lcr = 0;
938 u8 uart_lcr, ier;
939 u32 baud;
940 int quot;
941 struct jsm_board *bd;
942
943 bd = ch->ch_bd;
944 if (!bd)
945 return;
946
947 /*
948 * If baud rate is zero, flush queues, and set mval to drop DTR.
949 */
950 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
951 ch->ch_r_head = ch->ch_r_tail = 0;
952 ch->ch_e_head = ch->ch_e_tail = 0;
953
954 neo_flush_uart_write(ch);
955 neo_flush_uart_read(ch);
956
957 ch->ch_flags |= (CH_BAUD0);
958 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
959 neo_assert_modem_signals(ch);
960 return;
961
962 } else {
963 int i;
964 unsigned int cflag;
965 static struct {
966 unsigned int rate;
967 unsigned int cflag;
968 } baud_rates[] = {
969 { 921600, B921600 },
970 { 460800, B460800 },
971 { 230400, B230400 },
972 { 115200, B115200 },
973 { 57600, B57600 },
974 { 38400, B38400 },
975 { 19200, B19200 },
976 { 9600, B9600 },
977 { 4800, B4800 },
978 { 2400, B2400 },
979 { 1200, B1200 },
980 { 600, B600 },
981 { 300, B300 },
982 { 200, B200 },
983 { 150, B150 },
984 { 134, B134 },
985 { 110, B110 },
986 { 75, B75 },
987 { 50, B50 },
988 };
989
990 cflag = C_BAUD(ch->uart_port.state->port.tty);
991 baud = 9600;
992 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
993 if (baud_rates[i].cflag == cflag) {
994 baud = baud_rates[i].rate;
995 break;
996 }
997 }
998
999 if (ch->ch_flags & CH_BAUD0)
1000 ch->ch_flags &= ~(CH_BAUD0);
1001 }
1002
1003 if (ch->ch_c_cflag & PARENB)
1004 lcr |= UART_LCR_PARITY;
1005
1006 if (!(ch->ch_c_cflag & PARODD))
1007 lcr |= UART_LCR_EPAR;
1008
1009 /*
1010 * Not all platforms support mark/space parity,
1011 * so this will hide behind an ifdef.
1012 */
1013#ifdef CMSPAR
1014 if (ch->ch_c_cflag & CMSPAR)
1015 lcr |= UART_LCR_SPAR;
1016#endif
1017
1018 if (ch->ch_c_cflag & CSTOPB)
1019 lcr |= UART_LCR_STOP;
1020
1021 switch (ch->ch_c_cflag & CSIZE) {
1022 case CS5:
1023 lcr |= UART_LCR_WLEN5;
1024 break;
1025 case CS6:
1026 lcr |= UART_LCR_WLEN6;
1027 break;
1028 case CS7:
1029 lcr |= UART_LCR_WLEN7;
1030 break;
1031 case CS8:
1032 default:
1033 lcr |= UART_LCR_WLEN8;
1034 break;
1035 }
1036
1037 ier = readb(&ch->ch_neo_uart->ier);
1038 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1039
1040 quot = ch->ch_bd->bd_dividend / baud;
1041
1042 if (quot != 0) {
1043 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1044 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1045 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1046 writeb(lcr, &ch->ch_neo_uart->lcr);
1047 }
1048
1049 if (uart_lcr != lcr)
1050 writeb(lcr, &ch->ch_neo_uart->lcr);
1051
1052 if (ch->ch_c_cflag & CREAD)
1053 ier |= (UART_IER_RDI | UART_IER_RLSI);
1054
1055 ier |= (UART_IER_THRI | UART_IER_MSI);
1056
1057 writeb(ier, &ch->ch_neo_uart->ier);
1058
1059 /* Set new start/stop chars */
1060 neo_set_new_start_stop_chars(ch);
1061
1062 if (ch->ch_c_cflag & CRTSCTS)
1063 neo_set_cts_flow_control(ch);
1064 else if (ch->ch_c_iflag & IXON) {
1065 /* If start/stop is set to disable, then we should disable flow control */
1066 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1067 neo_set_no_output_flow_control(ch);
1068 else
1069 neo_set_ixon_flow_control(ch);
1070 }
1071 else
1072 neo_set_no_output_flow_control(ch);
1073
1074 if (ch->ch_c_cflag & CRTSCTS)
1075 neo_set_rts_flow_control(ch);
1076 else if (ch->ch_c_iflag & IXOFF) {
1077 /* If start/stop is set to disable, then we should disable flow control */
1078 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1079 neo_set_no_input_flow_control(ch);
1080 else
1081 neo_set_ixoff_flow_control(ch);
1082 }
1083 else
1084 neo_set_no_input_flow_control(ch);
1085 /*
1086 * Adjust the RX FIFO Trigger level if baud is less than 9600.
1087 * Not exactly elegant, but this is needed because of the Exar chip's
1088 * delay on firing off the RX FIFO interrupt on slower baud rates.
1089 */
1090 if (baud < 9600) {
1091 writeb(1, &ch->ch_neo_uart->rfifo);
1092 ch->ch_r_tlevel = 1;
1093 }
1094
1095 neo_assert_modem_signals(ch);
1096
1097 /* Get current status of the modem signals now */
1098 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1099 return;
1100}
1101
1102/*
1103 * jsm_neo_intr()
1104 *
1105 * Neo specific interrupt handler.
1106 */
1107static irqreturn_t neo_intr(int irq, void *voidbrd)
1108{
1109 struct jsm_board *brd = voidbrd;
1110 struct jsm_channel *ch;
1111 int port = 0;
1112 int type = 0;
1113 int current_port;
1114 u32 tmp;
1115 u32 uart_poll;
1116 unsigned long lock_flags;
1117 unsigned long lock_flags2;
1118 int outofloop_count = 0;
1119
1120 /* Lock out the slow poller from running on this board. */
1121 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1122
1123 /*
1124 * Read in "extended" IRQ information from the 32bit Neo register.
1125 * Bits 0-7: What port triggered the interrupt.
1126 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1127 */
1128 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1129
1130 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
1131 __FILE__, __LINE__, uart_poll);
1132
1133 if (!uart_poll) {
1134 jsm_dbg(INTR, &brd->pci_dev,
1135 "Kernel interrupted to me, but no pending interrupts...\n");
1136 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1137 return IRQ_NONE;
1138 }
1139
1140 /* At this point, we have at least SOMETHING to service, dig further... */
1141
1142 current_port = 0;
1143
1144 /* Loop on each port */
1145 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1146
1147 tmp = uart_poll;
1148 outofloop_count++;
1149
1150 /* Check current port to see if it has interrupt pending */
1151 if ((tmp & jsm_offset_table[current_port]) != 0) {
1152 port = current_port;
1153 type = tmp >> (8 + (port * 3));
1154 type &= 0x7;
1155 } else {
1156 current_port++;
1157 continue;
1158 }
1159
1160 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n",
1161 __FILE__, __LINE__, port, type);
1162
1163 /* Remove this port + type from uart_poll */
1164 uart_poll &= ~(jsm_offset_table[port]);
1165
1166 if (!type) {
1167 /* If no type, just ignore it, and move onto next port */
1168 jsm_dbg(INTR, &brd->pci_dev,
1169 "Interrupt with no type! port: %d\n", port);
1170 continue;
1171 }
1172
1173 /* Switch on type of interrupt we have */
1174 switch (type) {
1175
1176 case UART_17158_RXRDY_TIMEOUT:
1177 /*
1178 * RXRDY Time-out is cleared by reading data in the
1179 * RX FIFO until it falls below the trigger level.
1180 */
1181
1182 /* Verify the port is in range. */
1183 if (port >= brd->nasync)
1184 continue;
1185
1186 ch = brd->channels[port];
1187 neo_copy_data_from_uart_to_queue(ch);
1188
1189 /* Call our tty layer to enforce queue flow control if needed. */
1190 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1191 jsm_check_queue_flow_control(ch);
1192 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1193
1194 continue;
1195
1196 case UART_17158_RX_LINE_STATUS:
1197 /*
1198 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1199 */
1200 neo_parse_lsr(brd, port);
1201 continue;
1202
1203 case UART_17158_TXRDY:
1204 /*
1205 * TXRDY interrupt clears after reading ISR register for the UART channel.
1206 */
1207
1208 /*
1209 * Yes, this is odd...
1210 * Why would I check EVERY possibility of type of
1211 * interrupt, when we know its TXRDY???
1212 * Becuz for some reason, even tho we got triggered for TXRDY,
1213 * it seems to be occasionally wrong. Instead of TX, which
1214 * it should be, I was getting things like RXDY too. Weird.
1215 */
1216 neo_parse_isr(brd, port);
1217 continue;
1218
1219 case UART_17158_MSR:
1220 /*
1221 * MSR or flow control was seen.
1222 */
1223 neo_parse_isr(brd, port);
1224 continue;
1225
1226 default:
1227 /*
1228 * The UART triggered us with a bogus interrupt type.
1229 * It appears the Exar chip, when REALLY bogged down, will throw
1230 * these once and awhile.
1231 * Its harmless, just ignore it and move on.
1232 */
1233 jsm_dbg(INTR, &brd->pci_dev,
1234 "%s:%d Unknown Interrupt type: %x\n",
1235 __FILE__, __LINE__, type);
1236 continue;
1237 }
1238 }
1239
1240 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1241
1242 jsm_dbg(INTR, &brd->pci_dev, "finish\n");
1243 return IRQ_HANDLED;
1244}
1245
1246/*
1247 * Neo specific way of turning off the receiver.
1248 * Used as a way to enforce queue flow control when in
1249 * hardware flow control mode.
1250 */
1251static void neo_disable_receiver(struct jsm_channel *ch)
1252{
1253 u8 tmp = readb(&ch->ch_neo_uart->ier);
1254 tmp &= ~(UART_IER_RDI);
1255 writeb(tmp, &ch->ch_neo_uart->ier);
1256
1257 /* flush write operation */
1258 neo_pci_posting_flush(ch->ch_bd);
1259}
1260
1261
1262/*
1263 * Neo specific way of turning on the receiver.
1264 * Used as a way to un-enforce queue flow control when in
1265 * hardware flow control mode.
1266 */
1267static void neo_enable_receiver(struct jsm_channel *ch)
1268{
1269 u8 tmp = readb(&ch->ch_neo_uart->ier);
1270 tmp |= (UART_IER_RDI);
1271 writeb(tmp, &ch->ch_neo_uart->ier);
1272
1273 /* flush write operation */
1274 neo_pci_posting_flush(ch->ch_bd);
1275}
1276
1277static void neo_send_start_character(struct jsm_channel *ch)
1278{
1279 if (!ch)
1280 return;
1281
1282 if (ch->ch_startc != __DISABLED_CHAR) {
1283 ch->ch_xon_sends++;
1284 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1285
1286 /* flush write operation */
1287 neo_pci_posting_flush(ch->ch_bd);
1288 }
1289}
1290
1291static void neo_send_stop_character(struct jsm_channel *ch)
1292{
1293 if (!ch)
1294 return;
1295
1296 if (ch->ch_stopc != __DISABLED_CHAR) {
1297 ch->ch_xoff_sends++;
1298 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1299
1300 /* flush write operation */
1301 neo_pci_posting_flush(ch->ch_bd);
1302 }
1303}
1304
1305/*
1306 * neo_uart_init
1307 */
1308static void neo_uart_init(struct jsm_channel *ch)
1309{
1310 writeb(0, &ch->ch_neo_uart->ier);
1311 writeb(0, &ch->ch_neo_uart->efr);
1312 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1313
1314 /* Clear out UART and FIFO */
1315 readb(&ch->ch_neo_uart->txrx);
1316 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1317 readb(&ch->ch_neo_uart->lsr);
1318 readb(&ch->ch_neo_uart->msr);
1319
1320 ch->ch_flags |= CH_FIFO_ENABLED;
1321
1322 /* Assert any signals we want up */
1323 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1324}
1325
1326/*
1327 * Make the UART completely turn off.
1328 */
1329static void neo_uart_off(struct jsm_channel *ch)
1330{
1331 /* Turn off UART enhanced bits */
1332 writeb(0, &ch->ch_neo_uart->efr);
1333
1334 /* Stop all interrupts from occurring. */
1335 writeb(0, &ch->ch_neo_uart->ier);
1336}
1337
1338static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1339{
1340 u8 left = 0;
1341 u8 lsr = readb(&ch->ch_neo_uart->lsr);
1342
1343 /* We must cache the LSR as some of the bits get reset once read... */
1344 ch->ch_cached_lsr |= lsr;
1345
1346 /* Determine whether the Transmitter is empty or not */
1347 if (!(lsr & UART_LSR_TEMT))
1348 left = 1;
1349 else {
1350 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1351 left = 0;
1352 }
1353
1354 return left;
1355}
1356
1357/* Channel lock MUST be held by the calling function! */
1358static void neo_send_break(struct jsm_channel *ch)
1359{
1360 /*
1361 * Set the time we should stop sending the break.
1362 * If we are already sending a break, toss away the existing
1363 * time to stop, and use this new value instead.
1364 */
1365
1366 /* Tell the UART to start sending the break */
1367 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1368 u8 temp = readb(&ch->ch_neo_uart->lcr);
1369 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1370 ch->ch_flags |= (CH_BREAK_SENDING);
1371
1372 /* flush write operation */
1373 neo_pci_posting_flush(ch->ch_bd);
1374 }
1375}
1376
1377/*
1378 * neo_send_immediate_char.
1379 *
1380 * Sends a specific character as soon as possible to the UART,
1381 * jumping over any bytes that might be in the write queue.
1382 *
1383 * The channel lock MUST be held by the calling function.
1384 */
1385static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1386{
1387 if (!ch)
1388 return;
1389
1390 writeb(c, &ch->ch_neo_uart->txrx);
1391
1392 /* flush write operation */
1393 neo_pci_posting_flush(ch->ch_bd);
1394}
1395
1396struct board_ops jsm_neo_ops = {
1397 .intr = neo_intr,
1398 .uart_init = neo_uart_init,
1399 .uart_off = neo_uart_off,
1400 .param = neo_param,
1401 .assert_modem_signals = neo_assert_modem_signals,
1402 .flush_uart_write = neo_flush_uart_write,
1403 .flush_uart_read = neo_flush_uart_read,
1404 .disable_receiver = neo_disable_receiver,
1405 .enable_receiver = neo_enable_receiver,
1406 .send_break = neo_send_break,
1407 .clear_break = neo_clear_break,
1408 .send_start_character = neo_send_start_character,
1409 .send_stop_character = neo_send_stop_character,
1410 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
1411 .get_uart_bytes_left = neo_get_uart_bytes_left,
1412 .send_immediate_char = neo_send_immediate_char
1413};