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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Common prep/pmac/chrp boot and setup code.
4 */
5
6#include <linux/module.h>
7#include <linux/string.h>
8#include <linux/sched.h>
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/reboot.h>
12#include <linux/delay.h>
13#include <linux/initrd.h>
14#include <linux/tty.h>
15#include <linux/seq_file.h>
16#include <linux/root_dev.h>
17#include <linux/cpu.h>
18#include <linux/console.h>
19#include <linux/memblock.h>
20#include <linux/export.h>
21#include <linux/nvram.h>
22#include <linux/pgtable.h>
23#include <linux/of_fdt.h>
24#include <linux/irq.h>
25
26#include <asm/io.h>
27#include <asm/processor.h>
28#include <asm/setup.h>
29#include <asm/smp.h>
30#include <asm/elf.h>
31#include <asm/cputable.h>
32#include <asm/bootx.h>
33#include <asm/btext.h>
34#include <asm/machdep.h>
35#include <linux/uaccess.h>
36#include <asm/pmac_feature.h>
37#include <asm/sections.h>
38#include <asm/nvram.h>
39#include <asm/xmon.h>
40#include <asm/time.h>
41#include <asm/serial.h>
42#include <asm/udbg.h>
43#include <asm/code-patching.h>
44#include <asm/cpu_has_feature.h>
45#include <asm/asm-prototypes.h>
46#include <asm/kdump.h>
47#include <asm/feature-fixups.h>
48#include <asm/early_ioremap.h>
49
50#include "setup.h"
51
52#define DBG(fmt...)
53
54extern void bootx_init(unsigned long r4, unsigned long phys);
55
56int boot_cpuid_phys;
57EXPORT_SYMBOL_GPL(boot_cpuid_phys);
58
59int smp_hw_index[NR_CPUS];
60EXPORT_SYMBOL(smp_hw_index);
61
62unsigned int DMA_MODE_READ;
63unsigned int DMA_MODE_WRITE;
64
65EXPORT_SYMBOL(DMA_MODE_READ);
66EXPORT_SYMBOL(DMA_MODE_WRITE);
67
68/*
69 * This is run before start_kernel(), the kernel has been relocated
70 * and we are running with enough of the MMU enabled to have our
71 * proper kernel virtual addresses
72 *
73 * We do the initial parsing of the flat device-tree and prepares
74 * for the MMU to be fully initialized.
75 */
76notrace void __init machine_init(u64 dt_ptr)
77{
78 u32 *addr = (u32 *)patch_site_addr(&patch__memset_nocache);
79 ppc_inst_t insn;
80
81 /* Configure static keys first, now that we're relocated. */
82 setup_feature_keys();
83
84 early_ioremap_init();
85
86 /* Enable early debugging if any specified (see udbg.h) */
87 udbg_early_init();
88
89 patch_instruction_site(&patch__memcpy_nocache, ppc_inst(PPC_RAW_NOP()));
90
91 create_cond_branch(&insn, addr, branch_target(addr), 0x820000);
92 patch_instruction(addr, insn); /* replace b by bne cr0 */
93
94 /* Do some early initialization based on the flat device tree */
95 early_init_devtree(__va(dt_ptr));
96
97 early_init_mmu();
98
99 setup_kdump_trampoline();
100}
101
102/* Checks "l2cr=xxxx" command-line option */
103static int __init ppc_setup_l2cr(char *str)
104{
105 if (cpu_has_feature(CPU_FTR_L2CR)) {
106 unsigned long val = simple_strtoul(str, NULL, 0);
107 printk(KERN_INFO "l2cr set to %lx\n", val);
108 _set_L2CR(0); /* force invalidate by disable cache */
109 _set_L2CR(val); /* and enable it */
110 }
111 return 1;
112}
113__setup("l2cr=", ppc_setup_l2cr);
114
115/* Checks "l3cr=xxxx" command-line option */
116static int __init ppc_setup_l3cr(char *str)
117{
118 if (cpu_has_feature(CPU_FTR_L3CR)) {
119 unsigned long val = simple_strtoul(str, NULL, 0);
120 printk(KERN_INFO "l3cr set to %lx\n", val);
121 _set_L3CR(val); /* and enable it */
122 }
123 return 1;
124}
125__setup("l3cr=", ppc_setup_l3cr);
126
127static int __init ppc_init(void)
128{
129 /* clear the progress line */
130 if (ppc_md.progress)
131 ppc_md.progress(" ", 0xffff);
132
133 /* call platform init */
134 if (ppc_md.init != NULL) {
135 ppc_md.init();
136 }
137 return 0;
138}
139arch_initcall(ppc_init);
140
141static void *__init alloc_stack(void)
142{
143 void *ptr = memblock_alloc(THREAD_SIZE, THREAD_ALIGN);
144
145 if (!ptr)
146 panic("cannot allocate %d bytes for stack at %pS\n",
147 THREAD_SIZE, (void *)_RET_IP_);
148
149 return ptr;
150}
151
152void __init irqstack_early_init(void)
153{
154 unsigned int i;
155
156 if (IS_ENABLED(CONFIG_VMAP_STACK))
157 return;
158
159 /* interrupt stacks must be in lowmem, we get that for free on ppc32
160 * as the memblock is limited to lowmem by default */
161 for_each_possible_cpu(i) {
162 softirq_ctx[i] = alloc_stack();
163 hardirq_ctx[i] = alloc_stack();
164 }
165}
166
167#ifdef CONFIG_VMAP_STACK
168void *emergency_ctx[NR_CPUS] __ro_after_init = {[0] = &init_stack};
169
170void __init emergency_stack_init(void)
171{
172 unsigned int i;
173
174 for_each_possible_cpu(i)
175 emergency_ctx[i] = alloc_stack();
176}
177#endif
178
179#ifdef CONFIG_BOOKE_OR_40x
180void __init exc_lvl_early_init(void)
181{
182 unsigned int i, hw_cpu;
183
184 /* interrupt stacks must be in lowmem, we get that for free on ppc32
185 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
186 for_each_possible_cpu(i) {
187#ifdef CONFIG_SMP
188 hw_cpu = get_hard_smp_processor_id(i);
189#else
190 hw_cpu = 0;
191#endif
192
193 critirq_ctx[hw_cpu] = alloc_stack();
194#ifdef CONFIG_BOOKE
195 dbgirq_ctx[hw_cpu] = alloc_stack();
196 mcheckirq_ctx[hw_cpu] = alloc_stack();
197#endif
198 }
199}
200#endif
201
202void __init setup_power_save(void)
203{
204#ifdef CONFIG_PPC_BOOK3S_32
205 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
206 cpu_has_feature(CPU_FTR_CAN_NAP))
207 ppc_md.power_save = ppc6xx_idle;
208#endif
209
210#ifdef CONFIG_PPC_E500
211 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
212 cpu_has_feature(CPU_FTR_CAN_NAP))
213 ppc_md.power_save = e500_idle;
214#endif
215}
216
217__init void initialize_cache_info(void)
218{
219 /*
220 * Set cache line size based on type of cpu as a default.
221 * Systems with OF can look in the properties on the cpu node(s)
222 * for a possibly more accurate value.
223 */
224 dcache_bsize = cur_cpu_spec->dcache_bsize;
225 icache_bsize = cur_cpu_spec->icache_bsize;
226}
1/*
2 * Common prep/pmac/chrp boot and setup code.
3 */
4
5#include <linux/module.h>
6#include <linux/string.h>
7#include <linux/sched.h>
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/reboot.h>
11#include <linux/delay.h>
12#include <linux/initrd.h>
13#include <linux/tty.h>
14#include <linux/seq_file.h>
15#include <linux/root_dev.h>
16#include <linux/cpu.h>
17#include <linux/console.h>
18#include <linux/memblock.h>
19#include <linux/export.h>
20
21#include <asm/io.h>
22#include <asm/prom.h>
23#include <asm/processor.h>
24#include <asm/pgtable.h>
25#include <asm/setup.h>
26#include <asm/smp.h>
27#include <asm/elf.h>
28#include <asm/cputable.h>
29#include <asm/bootx.h>
30#include <asm/btext.h>
31#include <asm/machdep.h>
32#include <linux/uaccess.h>
33#include <asm/pmac_feature.h>
34#include <asm/sections.h>
35#include <asm/nvram.h>
36#include <asm/xmon.h>
37#include <asm/time.h>
38#include <asm/serial.h>
39#include <asm/udbg.h>
40#include <asm/code-patching.h>
41#include <asm/cpu_has_feature.h>
42
43#define DBG(fmt...)
44
45extern void bootx_init(unsigned long r4, unsigned long phys);
46
47int boot_cpuid_phys;
48EXPORT_SYMBOL_GPL(boot_cpuid_phys);
49
50int smp_hw_index[NR_CPUS];
51EXPORT_SYMBOL(smp_hw_index);
52
53unsigned long ISA_DMA_THRESHOLD;
54unsigned int DMA_MODE_READ;
55unsigned int DMA_MODE_WRITE;
56
57EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
58EXPORT_SYMBOL(DMA_MODE_READ);
59EXPORT_SYMBOL(DMA_MODE_WRITE);
60
61/*
62 * These are used in binfmt_elf.c to put aux entries on the stack
63 * for each elf executable being started.
64 */
65int dcache_bsize;
66int icache_bsize;
67int ucache_bsize;
68
69/*
70 * We're called here very early in the boot.
71 *
72 * Note that the kernel may be running at an address which is different
73 * from the address that it was linked at, so we must use RELOC/PTRRELOC
74 * to access static data (including strings). -- paulus
75 */
76notrace unsigned long __init early_init(unsigned long dt_ptr)
77{
78 unsigned long offset = reloc_offset();
79
80 /* First zero the BSS -- use memset_io, some platforms don't have
81 * caches on yet */
82 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
83 __bss_stop - __bss_start);
84
85 /*
86 * Identify the CPU type and fix up code sections
87 * that depend on which cpu we have.
88 */
89 identify_cpu(offset, mfspr(SPRN_PVR));
90
91 apply_feature_fixups();
92
93 return KERNELBASE + offset;
94}
95
96
97/*
98 * This is run before start_kernel(), the kernel has been relocated
99 * and we are running with enough of the MMU enabled to have our
100 * proper kernel virtual addresses
101 *
102 * We do the initial parsing of the flat device-tree and prepares
103 * for the MMU to be fully initialized.
104 */
105extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */
106
107notrace void __init machine_init(u64 dt_ptr)
108{
109 /* Configure static keys first, now that we're relocated. */
110 setup_feature_keys();
111
112 /* Enable early debugging if any specified (see udbg.h) */
113 udbg_early_init();
114
115 patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP);
116 patch_instruction(&memset_nocache_branch, PPC_INST_NOP);
117
118 /* Do some early initialization based on the flat device tree */
119 early_init_devtree(__va(dt_ptr));
120
121 early_init_mmu();
122
123 setup_kdump_trampoline();
124}
125
126/* Checks "l2cr=xxxx" command-line option */
127int __init ppc_setup_l2cr(char *str)
128{
129 if (cpu_has_feature(CPU_FTR_L2CR)) {
130 unsigned long val = simple_strtoul(str, NULL, 0);
131 printk(KERN_INFO "l2cr set to %lx\n", val);
132 _set_L2CR(0); /* force invalidate by disable cache */
133 _set_L2CR(val); /* and enable it */
134 }
135 return 1;
136}
137__setup("l2cr=", ppc_setup_l2cr);
138
139/* Checks "l3cr=xxxx" command-line option */
140int __init ppc_setup_l3cr(char *str)
141{
142 if (cpu_has_feature(CPU_FTR_L3CR)) {
143 unsigned long val = simple_strtoul(str, NULL, 0);
144 printk(KERN_INFO "l3cr set to %lx\n", val);
145 _set_L3CR(val); /* and enable it */
146 }
147 return 1;
148}
149__setup("l3cr=", ppc_setup_l3cr);
150
151#ifdef CONFIG_GENERIC_NVRAM
152
153/* Generic nvram hooks used by drivers/char/gen_nvram.c */
154unsigned char nvram_read_byte(int addr)
155{
156 if (ppc_md.nvram_read_val)
157 return ppc_md.nvram_read_val(addr);
158 return 0xff;
159}
160EXPORT_SYMBOL(nvram_read_byte);
161
162void nvram_write_byte(unsigned char val, int addr)
163{
164 if (ppc_md.nvram_write_val)
165 ppc_md.nvram_write_val(addr, val);
166}
167EXPORT_SYMBOL(nvram_write_byte);
168
169ssize_t nvram_get_size(void)
170{
171 if (ppc_md.nvram_size)
172 return ppc_md.nvram_size();
173 return -1;
174}
175EXPORT_SYMBOL(nvram_get_size);
176
177void nvram_sync(void)
178{
179 if (ppc_md.nvram_sync)
180 ppc_md.nvram_sync();
181}
182EXPORT_SYMBOL(nvram_sync);
183
184#endif /* CONFIG_NVRAM */
185
186int __init ppc_init(void)
187{
188 /* clear the progress line */
189 if (ppc_md.progress)
190 ppc_md.progress(" ", 0xffff);
191
192 /* call platform init */
193 if (ppc_md.init != NULL) {
194 ppc_md.init();
195 }
196 return 0;
197}
198
199arch_initcall(ppc_init);
200
201void __init irqstack_early_init(void)
202{
203 unsigned int i;
204
205 /* interrupt stacks must be in lowmem, we get that for free on ppc32
206 * as the memblock is limited to lowmem by default */
207 for_each_possible_cpu(i) {
208 softirq_ctx[i] = (struct thread_info *)
209 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
210 hardirq_ctx[i] = (struct thread_info *)
211 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
212 }
213}
214
215#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
216void __init exc_lvl_early_init(void)
217{
218 unsigned int i, hw_cpu;
219
220 /* interrupt stacks must be in lowmem, we get that for free on ppc32
221 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
222 for_each_possible_cpu(i) {
223#ifdef CONFIG_SMP
224 hw_cpu = get_hard_smp_processor_id(i);
225#else
226 hw_cpu = 0;
227#endif
228
229 critirq_ctx[hw_cpu] = (struct thread_info *)
230 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
231#ifdef CONFIG_BOOKE
232 dbgirq_ctx[hw_cpu] = (struct thread_info *)
233 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
234 mcheckirq_ctx[hw_cpu] = (struct thread_info *)
235 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
236#endif
237 }
238}
239#endif
240
241void __init setup_power_save(void)
242{
243#ifdef CONFIG_6xx
244 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
245 cpu_has_feature(CPU_FTR_CAN_NAP))
246 ppc_md.power_save = ppc6xx_idle;
247#endif
248
249#ifdef CONFIG_E500
250 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
251 cpu_has_feature(CPU_FTR_CAN_NAP))
252 ppc_md.power_save = e500_idle;
253#endif
254}
255
256__init void initialize_cache_info(void)
257{
258 /*
259 * Set cache line size based on type of cpu as a default.
260 * Systems with OF can look in the properties on the cpu node(s)
261 * for a possibly more accurate value.
262 */
263 dcache_bsize = cur_cpu_spec->dcache_bsize;
264 icache_bsize = cur_cpu_spec->icache_bsize;
265 ucache_bsize = 0;
266 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
267 ucache_bsize = icache_bsize = dcache_bsize;
268}