Loading...
Note: File does not exist in v6.8.
1/*
2 * Marvell Wireless LAN device driver: SDIO specific definitions
3 *
4 * Copyright (C) 2011, Marvell International Ltd.
5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#ifndef _MWIFIEX_SDIO_H
21#define _MWIFIEX_SDIO_H
22
23
24#include <linux/mmc/sdio.h>
25#include <linux/mmc/sdio_ids.h>
26#include <linux/mmc/sdio_func.h>
27#include <linux/mmc/card.h>
28
29#include "main.h"
30
31#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
32#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
33#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
34
35#define BLOCK_MODE 1
36#define BYTE_MODE 0
37
38#define REG_PORT 0
39#define RD_BITMAP_L 0x04
40#define RD_BITMAP_U 0x05
41#define WR_BITMAP_L 0x06
42#define WR_BITMAP_U 0x07
43#define RD_LEN_P0_L 0x08
44#define RD_LEN_P0_U 0x09
45
46#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
47
48#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
49
50#define CTRL_PORT 0
51#define CTRL_PORT_MASK 0x0001
52#define DATA_PORT_MASK 0xfffe
53
54#define MAX_MP_REGS 64
55#define MAX_PORT 16
56
57#define SDIO_MP_AGGR_DEF_PKT_LIMIT 8
58
59#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
60
61/* Multi port RX aggregation buffer size */
62#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
63
64/* Misc. Config Register : Auto Re-enable interrupts */
65#define AUTO_RE_ENABLE_INT BIT(4)
66
67/* Host Control Registers */
68/* Host Control Registers : I/O port 0 */
69#define IO_PORT_0_REG 0x78
70/* Host Control Registers : I/O port 1 */
71#define IO_PORT_1_REG 0x79
72/* Host Control Registers : I/O port 2 */
73#define IO_PORT_2_REG 0x7A
74
75/* Host Control Registers : Configuration */
76#define CONFIGURATION_REG 0x00
77/* Host Control Registers : Host without Command 53 finish host*/
78#define HOST_TO_CARD_EVENT (0x1U << 3)
79/* Host Control Registers : Host without Command 53 finish host */
80#define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
81/* Host Control Registers : Host power up */
82#define HOST_POWER_UP (0x1U << 1)
83/* Host Control Registers : Host power down */
84#define HOST_POWER_DOWN (0x1U << 0)
85
86/* Host Control Registers : Host interrupt mask */
87#define HOST_INT_MASK_REG 0x02
88/* Host Control Registers : Upload host interrupt mask */
89#define UP_LD_HOST_INT_MASK (0x1U)
90/* Host Control Registers : Download host interrupt mask */
91#define DN_LD_HOST_INT_MASK (0x2U)
92/* Enable Host interrupt mask */
93#define HOST_INT_ENABLE (UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK)
94/* Disable Host interrupt mask */
95#define HOST_INT_DISABLE 0xff
96
97/* Host Control Registers : Host interrupt status */
98#define HOST_INTSTATUS_REG 0x03
99/* Host Control Registers : Upload host interrupt status */
100#define UP_LD_HOST_INT_STATUS (0x1U)
101/* Host Control Registers : Download host interrupt status */
102#define DN_LD_HOST_INT_STATUS (0x2U)
103
104/* Host Control Registers : Host interrupt RSR */
105#define HOST_INT_RSR_REG 0x01
106/* Host Control Registers : Upload host interrupt RSR */
107#define UP_LD_HOST_INT_RSR (0x1U)
108#define SDIO_INT_MASK 0x3F
109
110/* Host Control Registers : Host interrupt status */
111#define HOST_INT_STATUS_REG 0x28
112/* Host Control Registers : Upload CRC error */
113#define UP_LD_CRC_ERR (0x1U << 2)
114/* Host Control Registers : Upload restart */
115#define UP_LD_RESTART (0x1U << 1)
116/* Host Control Registers : Download restart */
117#define DN_LD_RESTART (0x1U << 0)
118
119/* Card Control Registers : Card status register */
120#define CARD_STATUS_REG 0x30
121/* Card Control Registers : Card I/O ready */
122#define CARD_IO_READY (0x1U << 3)
123/* Card Control Registers : CIS card ready */
124#define CIS_CARD_RDY (0x1U << 2)
125/* Card Control Registers : Upload card ready */
126#define UP_LD_CARD_RDY (0x1U << 1)
127/* Card Control Registers : Download card ready */
128#define DN_LD_CARD_RDY (0x1U << 0)
129
130/* Card Control Registers : Host interrupt mask register */
131#define HOST_INTERRUPT_MASK_REG 0x34
132/* Card Control Registers : Host power interrupt mask */
133#define HOST_POWER_INT_MASK (0x1U << 3)
134/* Card Control Registers : Abort card interrupt mask */
135#define ABORT_CARD_INT_MASK (0x1U << 2)
136/* Card Control Registers : Upload card interrupt mask */
137#define UP_LD_CARD_INT_MASK (0x1U << 1)
138/* Card Control Registers : Download card interrupt mask */
139#define DN_LD_CARD_INT_MASK (0x1U << 0)
140
141/* Card Control Registers : Card interrupt status register */
142#define CARD_INTERRUPT_STATUS_REG 0x38
143/* Card Control Registers : Power up interrupt */
144#define POWER_UP_INT (0x1U << 4)
145/* Card Control Registers : Power down interrupt */
146#define POWER_DOWN_INT (0x1U << 3)
147
148/* Card Control Registers : Card interrupt RSR register */
149#define CARD_INTERRUPT_RSR_REG 0x3c
150/* Card Control Registers : Power up RSR */
151#define POWER_UP_RSR (0x1U << 4)
152/* Card Control Registers : Power down RSR */
153#define POWER_DOWN_RSR (0x1U << 3)
154
155/* Card Control Registers : Miscellaneous Configuration Register */
156#define CARD_MISC_CFG_REG 0x6C
157
158/* Host F1 read base 0 */
159#define HOST_F1_RD_BASE_0 0x0040
160/* Host F1 read base 1 */
161#define HOST_F1_RD_BASE_1 0x0041
162/* Host F1 card ready */
163#define HOST_F1_CARD_RDY 0x0020
164
165/* Firmware status 0 register */
166#define CARD_FW_STATUS0_REG 0x60
167/* Firmware status 1 register */
168#define CARD_FW_STATUS1_REG 0x61
169/* Rx length register */
170#define CARD_RX_LEN_REG 0x62
171/* Rx unit register */
172#define CARD_RX_UNIT_REG 0x63
173
174/* Max retry number of CMD53 write */
175#define MAX_WRITE_IOMEM_RETRY 2
176
177/* SDIO Tx aggregation in progress ? */
178#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
179
180/* SDIO Tx aggregation buffer room for next packet ? */
181#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
182 <= a->mpa_tx.buf_size)
183
184/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
185#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
186 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
187 payload, pkt_len); \
188 a->mpa_tx.buf_len += pkt_len; \
189 if (!a->mpa_tx.pkt_cnt) \
190 a->mpa_tx.start_port = port; \
191 if (a->mpa_tx.start_port <= port) \
192 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
193 else \
194 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+(MAX_PORT - \
195 a->mp_end_port))); \
196 a->mpa_tx.pkt_cnt++; \
197} while (0)
198
199/* SDIO Tx aggregation limit ? */
200#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
201 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
202
203/* SDIO Tx aggregation port limit ? */
204#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port < \
205 a->mpa_tx.start_port) && (((MAX_PORT - \
206 a->mpa_tx.start_port) + a->curr_wr_port) >= \
207 SDIO_MP_AGGR_DEF_PKT_LIMIT))
208
209/* Reset SDIO Tx aggregation buffer parameters */
210#define MP_TX_AGGR_BUF_RESET(a) do { \
211 a->mpa_tx.pkt_cnt = 0; \
212 a->mpa_tx.buf_len = 0; \
213 a->mpa_tx.ports = 0; \
214 a->mpa_tx.start_port = 0; \
215} while (0)
216
217/* SDIO Rx aggregation limit ? */
218#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
219 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
220
221/* SDIO Tx aggregation port limit ? */
222#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port < \
223 a->mpa_rx.start_port) && (((MAX_PORT - \
224 a->mpa_rx.start_port) + a->curr_rd_port) >= \
225 SDIO_MP_AGGR_DEF_PKT_LIMIT))
226
227/* SDIO Rx aggregation in progress ? */
228#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
229
230/* SDIO Rx aggregation buffer room for next packet ? */
231#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
232 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
233
234/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
235#define MP_RX_AGGR_SETUP(a, skb, port) do { \
236 a->mpa_rx.buf_len += skb->len; \
237 if (!a->mpa_rx.pkt_cnt) \
238 a->mpa_rx.start_port = port; \
239 if (a->mpa_rx.start_port <= port) \
240 a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt)); \
241 else \
242 a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt+1)); \
243 a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb; \
244 a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len; \
245 a->mpa_rx.pkt_cnt++; \
246} while (0)
247
248/* Reset SDIO Rx aggregation buffer parameters */
249#define MP_RX_AGGR_BUF_RESET(a) do { \
250 a->mpa_rx.pkt_cnt = 0; \
251 a->mpa_rx.buf_len = 0; \
252 a->mpa_rx.ports = 0; \
253 a->mpa_rx.start_port = 0; \
254} while (0)
255
256
257/* data structure for SDIO MPA TX */
258struct mwifiex_sdio_mpa_tx {
259 /* multiport tx aggregation buffer pointer */
260 u8 *buf;
261 u32 buf_len;
262 u32 pkt_cnt;
263 u16 ports;
264 u16 start_port;
265 u8 enabled;
266 u32 buf_size;
267 u32 pkt_aggr_limit;
268};
269
270struct mwifiex_sdio_mpa_rx {
271 u8 *buf;
272 u32 buf_len;
273 u32 pkt_cnt;
274 u16 ports;
275 u16 start_port;
276
277 struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
278 u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
279
280 u8 enabled;
281 u32 buf_size;
282 u32 pkt_aggr_limit;
283};
284
285int mwifiex_bus_register(void);
286void mwifiex_bus_unregister(void);
287
288struct sdio_mmc_card {
289 struct sdio_func *func;
290 struct mwifiex_adapter *adapter;
291
292 u16 mp_rd_bitmap;
293 u16 mp_wr_bitmap;
294
295 u16 mp_end_port;
296 u16 mp_data_port_mask;
297
298 u8 curr_rd_port;
299 u8 curr_wr_port;
300
301 u8 *mp_regs;
302
303 struct mwifiex_sdio_mpa_tx mpa_tx;
304 struct mwifiex_sdio_mpa_rx mpa_rx;
305};
306
307/*
308 * .cmdrsp_complete handler
309 */
310static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
311 struct sk_buff *skb)
312{
313 dev_kfree_skb_any(skb);
314 return 0;
315}
316
317/*
318 * .event_complete handler
319 */
320static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
321 struct sk_buff *skb)
322{
323 dev_kfree_skb_any(skb);
324 return 0;
325}
326
327#endif /* _MWIFIEX_SDIO_H */