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1/*
2 * Marvell Wireless LAN device driver: SDIO specific definitions
3 *
4 * Copyright (C) 2011, Marvell International Ltd.
5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#ifndef _MWIFIEX_SDIO_H
21#define _MWIFIEX_SDIO_H
22
23
24#include <linux/mmc/sdio.h>
25#include <linux/mmc/sdio_ids.h>
26#include <linux/mmc/sdio_func.h>
27#include <linux/mmc/card.h>
28#include <linux/mmc/host.h>
29
30#include "main.h"
31
32#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
33#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
34#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
35#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
36
37#define BLOCK_MODE 1
38#define BYTE_MODE 0
39
40#define REG_PORT 0
41
42#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
43
44#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
45
46#define SDIO_MPA_ADDR_BASE 0x1000
47#define CTRL_PORT 0
48#define CTRL_PORT_MASK 0x0001
49
50#define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
51#define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
52#define HOST_TERM_CMD53 (0x1U << 2)
53#define REG_PORT 0
54#define MEM_PORT 0x10000
55#define CMD_RD_LEN_0 0xB4
56#define CMD_RD_LEN_1 0xB5
57#define CARD_CONFIG_2_1_REG 0xCD
58#define CMD53_NEW_MODE (0x1U << 0)
59#define CMD_CONFIG_0 0xB8
60#define CMD_PORT_RD_LEN_EN (0x1U << 2)
61#define CMD_CONFIG_1 0xB9
62#define CMD_PORT_AUTO_EN (0x1U << 0)
63#define CMD_PORT_SLCT 0x8000
64#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
65#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
66
67#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
68
69/* Multi port RX aggregation buffer size */
70#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
71
72/* Misc. Config Register : Auto Re-enable interrupts */
73#define AUTO_RE_ENABLE_INT BIT(4)
74
75/* Host Control Registers */
76/* Host Control Registers : I/O port 0 */
77#define IO_PORT_0_REG 0x78
78/* Host Control Registers : I/O port 1 */
79#define IO_PORT_1_REG 0x79
80/* Host Control Registers : I/O port 2 */
81#define IO_PORT_2_REG 0x7A
82
83/* Host Control Registers : Configuration */
84#define CONFIGURATION_REG 0x00
85/* Host Control Registers : Host power up */
86#define HOST_POWER_UP (0x1U << 1)
87
88/* Host Control Registers : Host interrupt mask */
89#define HOST_INT_MASK_REG 0x02
90/* Host Control Registers : Upload host interrupt mask */
91#define UP_LD_HOST_INT_MASK (0x1U)
92/* Host Control Registers : Download host interrupt mask */
93#define DN_LD_HOST_INT_MASK (0x2U)
94
95/* Host Control Registers : Host interrupt status */
96#define HOST_INTSTATUS_REG 0x03
97/* Host Control Registers : Upload host interrupt status */
98#define UP_LD_HOST_INT_STATUS (0x1U)
99/* Host Control Registers : Download host interrupt status */
100#define DN_LD_HOST_INT_STATUS (0x2U)
101
102/* Host Control Registers : Host interrupt RSR */
103#define HOST_INT_RSR_REG 0x01
104
105/* Host Control Registers : Host interrupt status */
106#define HOST_INT_STATUS_REG 0x28
107
108/* Card Control Registers : Card I/O ready */
109#define CARD_IO_READY (0x1U << 3)
110/* Card Control Registers : Download card ready */
111#define DN_LD_CARD_RDY (0x1U << 0)
112
113/* Max retry number of CMD53 write */
114#define MAX_WRITE_IOMEM_RETRY 2
115
116/* SDIO Tx aggregation in progress ? */
117#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
118
119/* SDIO Tx aggregation buffer room for next packet ? */
120#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
121 <= a->mpa_tx.buf_size)
122
123/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
124#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
125 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
126 payload, pkt_len); \
127 a->mpa_tx.buf_len += pkt_len; \
128 if (!a->mpa_tx.pkt_cnt) \
129 a->mpa_tx.start_port = port; \
130 if (a->mpa_tx.start_port <= port) \
131 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
132 else \
133 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
134 (a->max_ports - \
135 a->mp_end_port))); \
136 a->mpa_tx.pkt_cnt++; \
137} while (0)
138
139/* SDIO Tx aggregation limit ? */
140#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
141 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
142
143/* Reset SDIO Tx aggregation buffer parameters */
144#define MP_TX_AGGR_BUF_RESET(a) do { \
145 a->mpa_tx.pkt_cnt = 0; \
146 a->mpa_tx.buf_len = 0; \
147 a->mpa_tx.ports = 0; \
148 a->mpa_tx.start_port = 0; \
149} while (0)
150
151/* SDIO Rx aggregation limit ? */
152#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
153 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
154
155/* SDIO Rx aggregation in progress ? */
156#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
157
158/* SDIO Rx aggregation buffer room for next packet ? */
159#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
160 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
161
162/* Reset SDIO Rx aggregation buffer parameters */
163#define MP_RX_AGGR_BUF_RESET(a) do { \
164 a->mpa_rx.pkt_cnt = 0; \
165 a->mpa_rx.buf_len = 0; \
166 a->mpa_rx.ports = 0; \
167 a->mpa_rx.start_port = 0; \
168} while (0)
169
170/* data structure for SDIO MPA TX */
171struct mwifiex_sdio_mpa_tx {
172 /* multiport tx aggregation buffer pointer */
173 u8 *buf;
174 u32 buf_len;
175 u32 pkt_cnt;
176 u32 ports;
177 u16 start_port;
178 u8 enabled;
179 u32 buf_size;
180 u32 pkt_aggr_limit;
181};
182
183struct mwifiex_sdio_mpa_rx {
184 u8 *buf;
185 u32 buf_len;
186 u32 pkt_cnt;
187 u32 ports;
188 u16 start_port;
189
190 struct sk_buff **skb_arr;
191 u32 *len_arr;
192
193 u8 enabled;
194 u32 buf_size;
195 u32 pkt_aggr_limit;
196};
197
198int mwifiex_bus_register(void);
199void mwifiex_bus_unregister(void);
200
201struct mwifiex_sdio_card_reg {
202 u8 start_rd_port;
203 u8 start_wr_port;
204 u8 base_0_reg;
205 u8 base_1_reg;
206 u8 poll_reg;
207 u8 host_int_enable;
208 u8 status_reg_0;
209 u8 status_reg_1;
210 u8 sdio_int_mask;
211 u32 data_port_mask;
212 u8 max_mp_regs;
213 u8 rd_bitmap_l;
214 u8 rd_bitmap_u;
215 u8 rd_bitmap_1l;
216 u8 rd_bitmap_1u;
217 u8 wr_bitmap_l;
218 u8 wr_bitmap_u;
219 u8 wr_bitmap_1l;
220 u8 wr_bitmap_1u;
221 u8 rd_len_p0_l;
222 u8 rd_len_p0_u;
223 u8 card_misc_cfg_reg;
224};
225
226struct sdio_mmc_card {
227 struct sdio_func *func;
228 struct mwifiex_adapter *adapter;
229
230 const char *firmware;
231 const struct mwifiex_sdio_card_reg *reg;
232 u8 max_ports;
233 u8 mp_agg_pkt_limit;
234 bool supports_sdio_new_mode;
235 bool has_control_mask;
236 u16 tx_buf_size;
237
238 u32 mp_rd_bitmap;
239 u32 mp_wr_bitmap;
240
241 u16 mp_end_port;
242 u32 mp_data_port_mask;
243
244 u8 curr_rd_port;
245 u8 curr_wr_port;
246
247 u8 *mp_regs;
248
249 struct mwifiex_sdio_mpa_tx mpa_tx;
250 struct mwifiex_sdio_mpa_rx mpa_rx;
251};
252
253struct mwifiex_sdio_device {
254 const char *firmware;
255 const struct mwifiex_sdio_card_reg *reg;
256 u8 max_ports;
257 u8 mp_agg_pkt_limit;
258 bool supports_sdio_new_mode;
259 bool has_control_mask;
260 u16 tx_buf_size;
261};
262
263static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
264 .start_rd_port = 1,
265 .start_wr_port = 1,
266 .base_0_reg = 0x0040,
267 .base_1_reg = 0x0041,
268 .poll_reg = 0x30,
269 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
270 .status_reg_0 = 0x60,
271 .status_reg_1 = 0x61,
272 .sdio_int_mask = 0x3f,
273 .data_port_mask = 0x0000fffe,
274 .max_mp_regs = 64,
275 .rd_bitmap_l = 0x04,
276 .rd_bitmap_u = 0x05,
277 .wr_bitmap_l = 0x06,
278 .wr_bitmap_u = 0x07,
279 .rd_len_p0_l = 0x08,
280 .rd_len_p0_u = 0x09,
281 .card_misc_cfg_reg = 0x6c,
282};
283
284static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
285 .start_rd_port = 0,
286 .start_wr_port = 0,
287 .base_0_reg = 0x60,
288 .base_1_reg = 0x61,
289 .poll_reg = 0x50,
290 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
291 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
292 .status_reg_0 = 0xc0,
293 .status_reg_1 = 0xc1,
294 .sdio_int_mask = 0xff,
295 .data_port_mask = 0xffffffff,
296 .max_mp_regs = 184,
297 .rd_bitmap_l = 0x04,
298 .rd_bitmap_u = 0x05,
299 .rd_bitmap_1l = 0x06,
300 .rd_bitmap_1u = 0x07,
301 .wr_bitmap_l = 0x08,
302 .wr_bitmap_u = 0x09,
303 .wr_bitmap_1l = 0x0a,
304 .wr_bitmap_1u = 0x0b,
305 .rd_len_p0_l = 0x0c,
306 .rd_len_p0_u = 0x0d,
307 .card_misc_cfg_reg = 0xcc,
308};
309
310static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
311 .firmware = SD8786_DEFAULT_FW_NAME,
312 .reg = &mwifiex_reg_sd87xx,
313 .max_ports = 16,
314 .mp_agg_pkt_limit = 8,
315 .supports_sdio_new_mode = false,
316 .has_control_mask = true,
317 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
318};
319
320static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
321 .firmware = SD8787_DEFAULT_FW_NAME,
322 .reg = &mwifiex_reg_sd87xx,
323 .max_ports = 16,
324 .mp_agg_pkt_limit = 8,
325 .supports_sdio_new_mode = false,
326 .has_control_mask = true,
327 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
328};
329
330static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
331 .firmware = SD8797_DEFAULT_FW_NAME,
332 .reg = &mwifiex_reg_sd87xx,
333 .max_ports = 16,
334 .mp_agg_pkt_limit = 8,
335 .supports_sdio_new_mode = false,
336 .has_control_mask = true,
337 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
338};
339
340static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
341 .firmware = SD8897_DEFAULT_FW_NAME,
342 .reg = &mwifiex_reg_sd8897,
343 .max_ports = 32,
344 .mp_agg_pkt_limit = 16,
345 .supports_sdio_new_mode = true,
346 .has_control_mask = false,
347 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
348};
349
350/*
351 * .cmdrsp_complete handler
352 */
353static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
354 struct sk_buff *skb)
355{
356 dev_kfree_skb_any(skb);
357 return 0;
358}
359
360/*
361 * .event_complete handler
362 */
363static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
364 struct sk_buff *skb)
365{
366 dev_kfree_skb_any(skb);
367 return 0;
368}
369
370static inline bool
371mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
372{
373 u8 tmp;
374
375 if (card->curr_rd_port < card->mpa_rx.start_port) {
376 if (card->supports_sdio_new_mode)
377 tmp = card->mp_end_port >> 1;
378 else
379 tmp = card->mp_agg_pkt_limit;
380
381 if (((card->max_ports - card->mpa_rx.start_port) +
382 card->curr_rd_port) >= tmp)
383 return true;
384 }
385
386 if (!card->supports_sdio_new_mode)
387 return false;
388
389 if ((card->curr_rd_port - card->mpa_rx.start_port) >=
390 (card->mp_end_port >> 1))
391 return true;
392
393 return false;
394}
395
396static inline bool
397mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
398{
399 u16 tmp;
400
401 if (card->curr_wr_port < card->mpa_tx.start_port) {
402 if (card->supports_sdio_new_mode)
403 tmp = card->mp_end_port >> 1;
404 else
405 tmp = card->mp_agg_pkt_limit;
406
407 if (((card->max_ports - card->mpa_tx.start_port) +
408 card->curr_wr_port) >= tmp)
409 return true;
410 }
411
412 if (!card->supports_sdio_new_mode)
413 return false;
414
415 if ((card->curr_wr_port - card->mpa_tx.start_port) >=
416 (card->mp_end_port >> 1))
417 return true;
418
419 return false;
420}
421
422/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
423static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
424 struct sk_buff *skb, u8 port)
425{
426 card->mpa_rx.buf_len += skb->len;
427
428 if (!card->mpa_rx.pkt_cnt)
429 card->mpa_rx.start_port = port;
430
431 if (card->supports_sdio_new_mode) {
432 card->mpa_rx.ports |= (1 << port);
433 } else {
434 if (card->mpa_rx.start_port <= port)
435 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
436 else
437 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
438 }
439 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
440 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
441 card->mpa_rx.pkt_cnt++;
442}
443#endif /* _MWIFIEX_SDIO_H */