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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#ifndef _E1000E_HW_H_
5#define _E1000E_HW_H_
6
7#include "regs.h"
8#include "defines.h"
9
10struct e1000_hw;
11
12#define E1000_DEV_ID_82571EB_COPPER 0x105E
13#define E1000_DEV_ID_82571EB_FIBER 0x105F
14#define E1000_DEV_ID_82571EB_SERDES 0x1060
15#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
16#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
17#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
18#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
19#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
20#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
21#define E1000_DEV_ID_82572EI_COPPER 0x107D
22#define E1000_DEV_ID_82572EI_FIBER 0x107E
23#define E1000_DEV_ID_82572EI_SERDES 0x107F
24#define E1000_DEV_ID_82572EI 0x10B9
25#define E1000_DEV_ID_82573E 0x108B
26#define E1000_DEV_ID_82573E_IAMT 0x108C
27#define E1000_DEV_ID_82573L 0x109A
28#define E1000_DEV_ID_82574L 0x10D3
29#define E1000_DEV_ID_82574LA 0x10F6
30#define E1000_DEV_ID_82583V 0x150C
31#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
32#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
33#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
34#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
35#define E1000_DEV_ID_ICH8_82567V_3 0x1501
36#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
37#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
38#define E1000_DEV_ID_ICH8_IGP_C 0x104B
39#define E1000_DEV_ID_ICH8_IFE 0x104C
40#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
41#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
42#define E1000_DEV_ID_ICH8_IGP_M 0x104D
43#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
44#define E1000_DEV_ID_ICH9_BM 0x10E5
45#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
46#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
47#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
48#define E1000_DEV_ID_ICH9_IGP_C 0x294C
49#define E1000_DEV_ID_ICH9_IFE 0x10C0
50#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
51#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
52#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
53#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
54#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
55#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
56#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
57#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
58#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
59#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
60#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
61#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
62#define E1000_DEV_ID_PCH2_LV_LM 0x1502
63#define E1000_DEV_ID_PCH2_LV_V 0x1503
64#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
65#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
66#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
67#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
68#define E1000_DEV_ID_PCH_I218_LM2 0x15A0
69#define E1000_DEV_ID_PCH_I218_V2 0x15A1
70#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
71#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
72#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
73#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
74#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
75#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
76#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */
77#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
78#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
79#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
80#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
81#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
82#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
83#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
84#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
85#define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF
86#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
87#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
88#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
89#define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E
90#define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F
91#define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C
92#define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D
93#define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53
94#define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55
95#define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB
96#define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC
97#define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9
98#define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA
99#define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4
100#define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5
101#define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5
102#define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6
103#define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E
104#define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F
105#define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C
106#define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D
107#define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7
108#define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8
109#define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A
110#define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B
111#define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C
112#define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D
113#define E1000_DEV_ID_PCH_LNP_I219_LM20 0x550E
114#define E1000_DEV_ID_PCH_LNP_I219_V20 0x550F
115#define E1000_DEV_ID_PCH_LNP_I219_LM21 0x5510
116#define E1000_DEV_ID_PCH_LNP_I219_V21 0x5511
117#define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0
118#define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1
119#define E1000_DEV_ID_PCH_PTP_I219_LM25 0x57B3
120#define E1000_DEV_ID_PCH_PTP_I219_V25 0x57B4
121#define E1000_DEV_ID_PCH_PTP_I219_LM26 0x57B5
122#define E1000_DEV_ID_PCH_PTP_I219_V26 0x57B6
123#define E1000_DEV_ID_PCH_PTP_I219_LM27 0x57B7
124#define E1000_DEV_ID_PCH_PTP_I219_V27 0x57B8
125#define E1000_DEV_ID_PCH_NVL_I219_LM29 0x57B9
126#define E1000_DEV_ID_PCH_NVL_I219_V29 0x57BA
127
128#define E1000_REVISION_4 4
129
130#define E1000_FUNC_1 1
131
132#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
133#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
134
135enum e1000_mac_type {
136 e1000_82571,
137 e1000_82572,
138 e1000_82573,
139 e1000_82574,
140 e1000_82583,
141 e1000_80003es2lan,
142 e1000_ich8lan,
143 e1000_ich9lan,
144 e1000_ich10lan,
145 e1000_pchlan,
146 e1000_pch2lan,
147 e1000_pch_lpt,
148 e1000_pch_spt,
149 e1000_pch_cnp,
150 e1000_pch_tgp,
151 e1000_pch_adp,
152 e1000_pch_mtp,
153 e1000_pch_lnp,
154 e1000_pch_ptp,
155 e1000_pch_nvp,
156};
157
158enum e1000_media_type {
159 e1000_media_type_unknown = 0,
160 e1000_media_type_copper = 1,
161 e1000_media_type_fiber = 2,
162 e1000_media_type_internal_serdes = 3,
163 e1000_num_media_types
164};
165
166enum e1000_nvm_type {
167 e1000_nvm_unknown = 0,
168 e1000_nvm_none,
169 e1000_nvm_eeprom_spi,
170 e1000_nvm_flash_hw,
171 e1000_nvm_flash_sw
172};
173
174enum e1000_nvm_override {
175 e1000_nvm_override_none = 0,
176 e1000_nvm_override_spi_small,
177 e1000_nvm_override_spi_large
178};
179
180enum e1000_phy_type {
181 e1000_phy_unknown = 0,
182 e1000_phy_none,
183 e1000_phy_m88,
184 e1000_phy_igp,
185 e1000_phy_igp_2,
186 e1000_phy_gg82563,
187 e1000_phy_igp_3,
188 e1000_phy_ife,
189 e1000_phy_bm,
190 e1000_phy_82578,
191 e1000_phy_82577,
192 e1000_phy_82579,
193 e1000_phy_i217,
194};
195
196enum e1000_bus_width {
197 e1000_bus_width_unknown = 0,
198 e1000_bus_width_pcie_x1,
199 e1000_bus_width_pcie_x2,
200 e1000_bus_width_pcie_x4 = 4,
201 e1000_bus_width_pcie_x8 = 8,
202 e1000_bus_width_32,
203 e1000_bus_width_64,
204 e1000_bus_width_reserved
205};
206
207enum e1000_1000t_rx_status {
208 e1000_1000t_rx_status_not_ok = 0,
209 e1000_1000t_rx_status_ok,
210 e1000_1000t_rx_status_undefined = 0xFF
211};
212
213enum e1000_rev_polarity {
214 e1000_rev_polarity_normal = 0,
215 e1000_rev_polarity_reversed,
216 e1000_rev_polarity_undefined = 0xFF
217};
218
219enum e1000_fc_mode {
220 e1000_fc_none = 0,
221 e1000_fc_rx_pause,
222 e1000_fc_tx_pause,
223 e1000_fc_full,
224 e1000_fc_default = 0xFF
225};
226
227enum e1000_ms_type {
228 e1000_ms_hw_default = 0,
229 e1000_ms_force_master,
230 e1000_ms_force_slave,
231 e1000_ms_auto
232};
233
234enum e1000_smart_speed {
235 e1000_smart_speed_default = 0,
236 e1000_smart_speed_on,
237 e1000_smart_speed_off
238};
239
240enum e1000_serdes_link_state {
241 e1000_serdes_link_down = 0,
242 e1000_serdes_link_autoneg_progress,
243 e1000_serdes_link_autoneg_complete,
244 e1000_serdes_link_forced_up
245};
246
247/* Receive Descriptor - Extended */
248union e1000_rx_desc_extended {
249 struct {
250 __le64 buffer_addr;
251 __le64 reserved;
252 } read;
253 struct {
254 struct {
255 __le32 mrq; /* Multiple Rx Queues */
256 union {
257 __le32 rss; /* RSS Hash */
258 struct {
259 __le16 ip_id; /* IP id */
260 __le16 csum; /* Packet Checksum */
261 } csum_ip;
262 } hi_dword;
263 } lower;
264 struct {
265 __le32 status_error; /* ext status/error */
266 __le16 length;
267 __le16 vlan; /* VLAN tag */
268 } upper;
269 } wb; /* writeback */
270};
271
272#define MAX_PS_BUFFERS 4
273
274/* Number of packet split data buffers (not including the header buffer) */
275#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
276
277/* Receive Descriptor - Packet Split */
278union e1000_rx_desc_packet_split {
279 struct {
280 /* one buffer for protocol header(s), three data buffers */
281 __le64 buffer_addr[MAX_PS_BUFFERS];
282 } read;
283 struct {
284 struct {
285 __le32 mrq; /* Multiple Rx Queues */
286 union {
287 __le32 rss; /* RSS Hash */
288 struct {
289 __le16 ip_id; /* IP id */
290 __le16 csum; /* Packet Checksum */
291 } csum_ip;
292 } hi_dword;
293 } lower;
294 struct {
295 __le32 status_error; /* ext status/error */
296 __le16 length0; /* length of buffer 0 */
297 __le16 vlan; /* VLAN tag */
298 } middle;
299 struct {
300 __le16 header_status;
301 /* length of buffers 1-3 */
302 __le16 length[PS_PAGE_BUFFERS];
303 } upper;
304 __le64 reserved;
305 } wb; /* writeback */
306};
307
308/* Transmit Descriptor */
309struct e1000_tx_desc {
310 __le64 buffer_addr; /* Address of the descriptor's data buffer */
311 union {
312 __le32 data;
313 struct {
314 __le16 length; /* Data buffer length */
315 u8 cso; /* Checksum offset */
316 u8 cmd; /* Descriptor control */
317 } flags;
318 } lower;
319 union {
320 __le32 data;
321 struct {
322 u8 status; /* Descriptor status */
323 u8 css; /* Checksum start */
324 __le16 special;
325 } fields;
326 } upper;
327};
328
329/* Offload Context Descriptor */
330struct e1000_context_desc {
331 union {
332 __le32 ip_config;
333 struct {
334 u8 ipcss; /* IP checksum start */
335 u8 ipcso; /* IP checksum offset */
336 __le16 ipcse; /* IP checksum end */
337 } ip_fields;
338 } lower_setup;
339 union {
340 __le32 tcp_config;
341 struct {
342 u8 tucss; /* TCP checksum start */
343 u8 tucso; /* TCP checksum offset */
344 __le16 tucse; /* TCP checksum end */
345 } tcp_fields;
346 } upper_setup;
347 __le32 cmd_and_length;
348 union {
349 __le32 data;
350 struct {
351 u8 status; /* Descriptor status */
352 u8 hdr_len; /* Header length */
353 __le16 mss; /* Maximum segment size */
354 } fields;
355 } tcp_seg_setup;
356};
357
358/* Offload data descriptor */
359struct e1000_data_desc {
360 __le64 buffer_addr; /* Address of the descriptor's buffer address */
361 union {
362 __le32 data;
363 struct {
364 __le16 length; /* Data buffer length */
365 u8 typ_len_ext;
366 u8 cmd;
367 } flags;
368 } lower;
369 union {
370 __le32 data;
371 struct {
372 u8 status; /* Descriptor status */
373 u8 popts; /* Packet Options */
374 __le16 special;
375 } fields;
376 } upper;
377};
378
379/* Statistics counters collected by the MAC */
380struct e1000_hw_stats {
381 u64 crcerrs;
382 u64 algnerrc;
383 u64 symerrs;
384 u64 rxerrc;
385 u64 mpc;
386 u64 scc;
387 u64 ecol;
388 u64 mcc;
389 u64 latecol;
390 u64 colc;
391 u64 dc;
392 u64 tncrs;
393 u64 sec;
394 u64 cexterr;
395 u64 rlec;
396 u64 xonrxc;
397 u64 xontxc;
398 u64 xoffrxc;
399 u64 xofftxc;
400 u64 fcruc;
401 u64 prc64;
402 u64 prc127;
403 u64 prc255;
404 u64 prc511;
405 u64 prc1023;
406 u64 prc1522;
407 u64 gprc;
408 u64 bprc;
409 u64 mprc;
410 u64 gptc;
411 u64 gorc;
412 u64 gotc;
413 u64 rnbc;
414 u64 ruc;
415 u64 rfc;
416 u64 roc;
417 u64 rjc;
418 u64 mgprc;
419 u64 mgpdc;
420 u64 mgptc;
421 u64 tor;
422 u64 tot;
423 u64 tpr;
424 u64 tpt;
425 u64 ptc64;
426 u64 ptc127;
427 u64 ptc255;
428 u64 ptc511;
429 u64 ptc1023;
430 u64 ptc1522;
431 u64 mptc;
432 u64 bptc;
433 u64 tsctc;
434 u64 tsctfc;
435 u64 iac;
436 u64 icrxptc;
437 u64 icrxatc;
438 u64 ictxptc;
439 u64 ictxatc;
440 u64 ictxqec;
441 u64 ictxqmtc;
442 u64 icrxdmtc;
443 u64 icrxoc;
444};
445
446struct e1000_phy_stats {
447 u32 idle_errors;
448 u32 receive_errors;
449};
450
451struct e1000_host_mng_dhcp_cookie {
452 u32 signature;
453 u8 status;
454 u8 reserved0;
455 u16 vlan_id;
456 u32 reserved1;
457 u16 reserved2;
458 u8 reserved3;
459 u8 checksum;
460};
461
462/* Host Interface "Rev 1" */
463struct e1000_host_command_header {
464 u8 command_id;
465 u8 command_length;
466 u8 command_options;
467 u8 checksum;
468};
469
470#define E1000_HI_MAX_DATA_LENGTH 252
471struct e1000_host_command_info {
472 struct e1000_host_command_header command_header;
473 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
474};
475
476/* Host Interface "Rev 2" */
477struct e1000_host_mng_command_header {
478 u8 command_id;
479 u8 checksum;
480 u16 reserved1;
481 u16 reserved2;
482 u16 command_length;
483};
484
485#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
486struct e1000_host_mng_command_info {
487 struct e1000_host_mng_command_header command_header;
488 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
489};
490
491#include "mac.h"
492#include "phy.h"
493#include "nvm.h"
494#include "manage.h"
495
496/* Function pointers for the MAC. */
497struct e1000_mac_operations {
498 s32 (*id_led_init)(struct e1000_hw *);
499 s32 (*blink_led)(struct e1000_hw *);
500 bool (*check_mng_mode)(struct e1000_hw *);
501 s32 (*check_for_link)(struct e1000_hw *);
502 s32 (*cleanup_led)(struct e1000_hw *);
503 void (*clear_hw_cntrs)(struct e1000_hw *);
504 void (*clear_vfta)(struct e1000_hw *);
505 s32 (*get_bus_info)(struct e1000_hw *);
506 void (*set_lan_id)(struct e1000_hw *);
507 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
508 s32 (*led_on)(struct e1000_hw *);
509 s32 (*led_off)(struct e1000_hw *);
510 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
511 s32 (*reset_hw)(struct e1000_hw *);
512 s32 (*init_hw)(struct e1000_hw *);
513 s32 (*setup_link)(struct e1000_hw *);
514 s32 (*setup_physical_interface)(struct e1000_hw *);
515 s32 (*setup_led)(struct e1000_hw *);
516 void (*write_vfta)(struct e1000_hw *, u32, u32);
517 void (*config_collision_dist)(struct e1000_hw *);
518 int (*rar_set)(struct e1000_hw *, u8 *, u32);
519 s32 (*read_mac_addr)(struct e1000_hw *);
520 u32 (*rar_get_count)(struct e1000_hw *);
521};
522
523/* When to use various PHY register access functions:
524 *
525 * Func Caller
526 * Function Does Does When to use
527 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
528 * X_reg L,P,A n/a for simple PHY reg accesses
529 * X_reg_locked P,A L for multiple accesses of different regs
530 * on different pages
531 * X_reg_page A L,P for multiple accesses of different regs
532 * on the same page
533 *
534 * Where X=[read|write], L=locking, P=sets page, A=register access
535 *
536 */
537struct e1000_phy_operations {
538 s32 (*acquire)(struct e1000_hw *);
539 s32 (*cfg_on_link_up)(struct e1000_hw *);
540 s32 (*check_polarity)(struct e1000_hw *);
541 s32 (*check_reset_block)(struct e1000_hw *);
542 s32 (*commit)(struct e1000_hw *);
543 s32 (*force_speed_duplex)(struct e1000_hw *);
544 s32 (*get_cfg_done)(struct e1000_hw *hw);
545 s32 (*get_cable_length)(struct e1000_hw *);
546 s32 (*get_info)(struct e1000_hw *);
547 s32 (*set_page)(struct e1000_hw *, u16);
548 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
549 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
550 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
551 void (*release)(struct e1000_hw *);
552 s32 (*reset)(struct e1000_hw *);
553 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
554 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
555 s32 (*write_reg)(struct e1000_hw *, u32, u16);
556 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
557 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
558 void (*power_up)(struct e1000_hw *);
559 void (*power_down)(struct e1000_hw *);
560};
561
562/* Function pointers for the NVM. */
563struct e1000_nvm_operations {
564 s32 (*acquire)(struct e1000_hw *);
565 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
566 void (*release)(struct e1000_hw *);
567 void (*reload)(struct e1000_hw *);
568 s32 (*update)(struct e1000_hw *);
569 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
570 s32 (*validate)(struct e1000_hw *);
571 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
572};
573
574struct e1000_mac_info {
575 struct e1000_mac_operations ops;
576 u8 addr[ETH_ALEN];
577 u8 perm_addr[ETH_ALEN];
578
579 enum e1000_mac_type type;
580
581 u32 collision_delta;
582 u32 ledctl_default;
583 u32 ledctl_mode1;
584 u32 ledctl_mode2;
585 u32 mc_filter_type;
586 u32 tx_packet_delta;
587 u32 txcw;
588
589 u16 current_ifs_val;
590 u16 ifs_max_val;
591 u16 ifs_min_val;
592 u16 ifs_ratio;
593 u16 ifs_step_size;
594 u16 mta_reg_count;
595
596 /* Maximum size of the MTA register table in all supported adapters */
597#define MAX_MTA_REG 128
598 u32 mta_shadow[MAX_MTA_REG];
599 u16 rar_entry_count;
600
601 u8 forced_speed_duplex;
602
603 bool adaptive_ifs;
604 bool has_fwsm;
605 bool arc_subsystem_valid;
606 bool autoneg;
607 bool autoneg_failed;
608 bool get_link_status;
609 bool in_ifs_mode;
610 bool serdes_has_link;
611 bool tx_pkt_filtering;
612 enum e1000_serdes_link_state serdes_link_state;
613};
614
615struct e1000_phy_info {
616 struct e1000_phy_operations ops;
617
618 enum e1000_phy_type type;
619
620 enum e1000_1000t_rx_status local_rx;
621 enum e1000_1000t_rx_status remote_rx;
622 enum e1000_ms_type ms_type;
623 enum e1000_ms_type original_ms_type;
624 enum e1000_rev_polarity cable_polarity;
625 enum e1000_smart_speed smart_speed;
626
627 u32 addr;
628 u32 id;
629 u32 reset_delay_us; /* in usec */
630 u32 revision;
631
632 enum e1000_media_type media_type;
633
634 u16 autoneg_advertised;
635 u16 autoneg_mask;
636 u16 cable_length;
637 u16 max_cable_length;
638 u16 min_cable_length;
639
640 u8 mdix;
641
642 bool disable_polarity_correction;
643 bool is_mdix;
644 bool polarity_correction;
645 bool speed_downgraded;
646 bool autoneg_wait_to_complete;
647};
648
649struct e1000_nvm_info {
650 struct e1000_nvm_operations ops;
651
652 enum e1000_nvm_type type;
653 enum e1000_nvm_override override;
654
655 u32 flash_bank_size;
656 u32 flash_base_addr;
657
658 u16 word_size;
659 u16 delay_usec;
660 u16 address_bits;
661 u16 opcode_bits;
662 u16 page_size;
663};
664
665struct e1000_bus_info {
666 enum e1000_bus_width width;
667
668 u16 func;
669};
670
671struct e1000_fc_info {
672 u32 high_water; /* Flow control high-water mark */
673 u32 low_water; /* Flow control low-water mark */
674 u16 pause_time; /* Flow control pause timer */
675 u16 refresh_time; /* Flow control refresh timer */
676 bool send_xon; /* Flow control send XON */
677 bool strict_ieee; /* Strict IEEE mode */
678 enum e1000_fc_mode current_mode; /* FC mode in effect */
679 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
680};
681
682struct e1000_dev_spec_82571 {
683 bool laa_is_present;
684 u32 smb_counter;
685};
686
687struct e1000_dev_spec_80003es2lan {
688 bool mdic_wa_enable;
689};
690
691struct e1000_shadow_ram {
692 u16 value;
693 bool modified;
694};
695
696#define E1000_ICH8_SHADOW_RAM_WORDS 2048
697
698/* I218 PHY Ultra Low Power (ULP) states */
699enum e1000_ulp_state {
700 e1000_ulp_state_unknown,
701 e1000_ulp_state_off,
702 e1000_ulp_state_on,
703};
704
705struct e1000_dev_spec_ich8lan {
706 bool kmrn_lock_loss_workaround_enabled;
707 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
708 bool nvm_k1_enabled;
709 bool eee_disable;
710 u16 eee_lp_ability;
711 enum e1000_ulp_state ulp_state;
712};
713
714struct e1000_hw {
715 struct e1000_adapter *adapter;
716
717 void __iomem *hw_addr;
718 void __iomem *flash_address;
719
720 struct e1000_mac_info mac;
721 struct e1000_fc_info fc;
722 struct e1000_phy_info phy;
723 struct e1000_nvm_info nvm;
724 struct e1000_bus_info bus;
725 struct e1000_host_mng_dhcp_cookie mng_cookie;
726
727 union {
728 struct e1000_dev_spec_82571 e82571;
729 struct e1000_dev_spec_80003es2lan e80003es2lan;
730 struct e1000_dev_spec_ich8lan ich8lan;
731 } dev_spec;
732};
733
734#include "82571.h"
735#include "80003es2lan.h"
736#include "ich8lan.h"
737
738#endif /* _E1000E_HW_H_ */
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_
31
32#include <linux/types.h>
33
34struct e1000_hw;
35struct e1000_adapter;
36
37#include "defines.h"
38
39enum e1e_registers {
40 E1000_CTRL = 0x00000, /* Device Control - RW */
41 E1000_STATUS = 0x00008, /* Device Status - RO */
42 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
43 E1000_EERD = 0x00014, /* EEPROM Read - RW */
44 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
45 E1000_FLA = 0x0001C, /* Flash Access - RW */
46 E1000_MDIC = 0x00020, /* MDI Control - RW */
47 E1000_SCTL = 0x00024, /* SerDes Control - RW */
48 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
49 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
50 E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
51 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
52 E1000_FCT = 0x00030, /* Flow Control Type - RW */
53 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
54 E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */
55 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
56 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
57 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
58 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
59 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
60 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
61 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
62 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
63 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
64#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
65 E1000_RCTL = 0x00100, /* Rx Control - RW */
66 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
67 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
68 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
69 E1000_TCTL = 0x00400, /* Tx Control - RW */
70 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
71 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
72 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
73 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
74 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
75 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
76 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
77#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
78 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
79 E1000_PBS = 0x01008, /* Packet Buffer Size */
80 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
81 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
82 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
83 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
84 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
85 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
86 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
87 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
88/*
89 * Convenience macros
90 *
91 * Note: "_n" is the queue number of the register to be written to.
92 *
93 * Example usage:
94 * E1000_RDBAL(current_rx_queue)
95 */
96 E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
97#define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
98 E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
99#define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
100 E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
101#define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
102 E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
103#define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
104 E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
105#define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
106 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
107 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
108#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
109 E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
110
111 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
112 E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
113#define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
114 E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
115#define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
116 E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
117#define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
118 E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
119#define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
120 E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
121#define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
122 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
123 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
124#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
125 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
126 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
127#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
128 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
129 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
130 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
131 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
132 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
133 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
134 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
135 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
136 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
137 E1000_COLC = 0x04028, /* Collision Count - R/clr */
138 E1000_DC = 0x04030, /* Defer Count - R/clr */
139 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
140 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
141 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
142 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
143 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
144 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
145 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
146 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
147 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
148 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
149 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
150 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
151 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
152 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
153 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
154 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
155 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
156 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
157 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
158 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
159 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
160 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
161 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
162 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
163 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
164 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
165 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
166 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
167 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
168 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
169 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
170 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
171 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
172 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
173 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
174 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
175 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
176 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
177 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
178 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
179 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
180 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
181 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
182 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
183 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
184 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
185 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
186 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
187 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
188 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
189 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
190 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
191 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
192 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
193 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
194 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
195 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
196 E1000_RFCTL = 0x05008, /* Receive Filter Control */
197 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
198 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
199#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
200#define E1000_RA (E1000_RAL(0))
201 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
202#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
203 E1000_SHRAL_PCH_LPT_BASE = 0x05408,
204#define E1000_SHRAL_PCH_LPT(_n) (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
205 E1000_SHRAH_PCH_LTP_BASE = 0x0540C,
206#define E1000_SHRAH_PCH_LPT(_n) (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
207 E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
208#define E1000_SHRAL(_n) (E1000_SHRAL_BASE + ((_n) * 8))
209 E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
210#define E1000_SHRAH(_n) (E1000_SHRAH_BASE + ((_n) * 8))
211 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
212 E1000_WUC = 0x05800, /* Wakeup Control - RW */
213 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
214 E1000_WUS = 0x05810, /* Wakeup Status - RO */
215 E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
216 E1000_MANC = 0x05820, /* Management Control - RW */
217 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
218 E1000_HOST_IF = 0x08800, /* Host Interface */
219
220 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
221 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
222 E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
223#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
224 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
225 E1000_GCR = 0x05B00, /* PCI-Ex Control */
226 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
227 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
228 E1000_SWSM = 0x05B50, /* SW Semaphore */
229 E1000_FWSM = 0x05B54, /* FW Semaphore */
230 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
231 E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
232#define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4))
233 E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
234#define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
235 E1000_FFLT_DBG = 0x05F04, /* Debug Register */
236 E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
237#define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
238#define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
239 E1000_HICR = 0x08F00, /* Host Interface Control */
240};
241
242#define E1000_MAX_PHY_ADDR 4
243
244/* IGP01E1000 Specific Registers */
245#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
246#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
247#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
248#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
249#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
250#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
251#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
252#define IGP_PAGE_SHIFT 5
253#define PHY_REG_MASK 0x1F
254
255#define BM_WUC_PAGE 800
256#define BM_WUC_ADDRESS_OPCODE 0x11
257#define BM_WUC_DATA_OPCODE 0x12
258#define BM_WUC_ENABLE_PAGE 769
259#define BM_WUC_ENABLE_REG 17
260#define BM_WUC_ENABLE_BIT (1 << 2)
261#define BM_WUC_HOST_WU_BIT (1 << 4)
262#define BM_WUC_ME_WU_BIT (1 << 5)
263
264#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
265#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
266#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
267
268#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
269#define IGP01E1000_PHY_POLARITY_MASK 0x0078
270
271#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
272#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
273
274#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
275
276#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
277#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
278#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
279
280#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
281
282#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
283#define IGP01E1000_PSSR_MDIX 0x0800
284#define IGP01E1000_PSSR_SPEED_MASK 0xC000
285#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
286
287#define IGP02E1000_PHY_CHANNEL_NUM 4
288#define IGP02E1000_PHY_AGC_A 0x11B1
289#define IGP02E1000_PHY_AGC_B 0x12B1
290#define IGP02E1000_PHY_AGC_C 0x14B1
291#define IGP02E1000_PHY_AGC_D 0x18B1
292
293#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
294#define IGP02E1000_AGC_LENGTH_MASK 0x7F
295#define IGP02E1000_AGC_RANGE 15
296
297/* manage.c */
298#define E1000_VFTA_ENTRY_SHIFT 5
299#define E1000_VFTA_ENTRY_MASK 0x7F
300#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
301
302#define E1000_HICR_EN 0x01 /* Enable bit - RO */
303/* Driver sets this bit when done to put command in RAM */
304#define E1000_HICR_C 0x02
305#define E1000_HICR_FW_RESET_ENABLE 0x40
306#define E1000_HICR_FW_RESET 0x80
307
308#define E1000_FWSM_MODE_MASK 0xE
309#define E1000_FWSM_MODE_SHIFT 1
310
311#define E1000_MNG_IAMT_MODE 0x3
312#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
313#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
314#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
315#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
316#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
317#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
318
319/* nvm.c */
320#define E1000_STM_OPCODE 0xDB00
321
322#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
323#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
324#define E1000_KMRNCTRLSTA_REN 0x00200000
325#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
326#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
327#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
328#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
329#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
330#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
331#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
332#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
333#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
334
335#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
336#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
337#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
338#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
339
340/* IFE PHY Extended Status Control */
341#define IFE_PESC_POLARITY_REVERSED 0x0100
342
343/* IFE PHY Special Control */
344#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
345#define IFE_PSC_FORCE_POLARITY 0x0020
346
347/* IFE PHY Special Control and LED Control */
348#define IFE_PSCL_PROBE_MODE 0x0020
349#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
350#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
351
352/* IFE PHY MDIX Control */
353#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
354#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
355#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
356
357#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
358
359#define E1000_DEV_ID_82571EB_COPPER 0x105E
360#define E1000_DEV_ID_82571EB_FIBER 0x105F
361#define E1000_DEV_ID_82571EB_SERDES 0x1060
362#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
363#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
364#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
365#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
366#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
367#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
368#define E1000_DEV_ID_82572EI_COPPER 0x107D
369#define E1000_DEV_ID_82572EI_FIBER 0x107E
370#define E1000_DEV_ID_82572EI_SERDES 0x107F
371#define E1000_DEV_ID_82572EI 0x10B9
372#define E1000_DEV_ID_82573E 0x108B
373#define E1000_DEV_ID_82573E_IAMT 0x108C
374#define E1000_DEV_ID_82573L 0x109A
375#define E1000_DEV_ID_82574L 0x10D3
376#define E1000_DEV_ID_82574LA 0x10F6
377#define E1000_DEV_ID_82583V 0x150C
378
379#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
380#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
381#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
382#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
383
384#define E1000_DEV_ID_ICH8_82567V_3 0x1501
385#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
386#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
387#define E1000_DEV_ID_ICH8_IGP_C 0x104B
388#define E1000_DEV_ID_ICH8_IFE 0x104C
389#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
390#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
391#define E1000_DEV_ID_ICH8_IGP_M 0x104D
392#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
393#define E1000_DEV_ID_ICH9_BM 0x10E5
394#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
395#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
396#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
397#define E1000_DEV_ID_ICH9_IGP_C 0x294C
398#define E1000_DEV_ID_ICH9_IFE 0x10C0
399#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
400#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
401#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
402#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
403#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
404#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
405#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
406#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
407#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
408#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
409#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
410#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
411#define E1000_DEV_ID_PCH2_LV_LM 0x1502
412#define E1000_DEV_ID_PCH2_LV_V 0x1503
413#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
414#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
415
416#define E1000_REVISION_4 4
417
418#define E1000_FUNC_1 1
419
420#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
421#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
422
423enum e1000_mac_type {
424 e1000_82571,
425 e1000_82572,
426 e1000_82573,
427 e1000_82574,
428 e1000_82583,
429 e1000_80003es2lan,
430 e1000_ich8lan,
431 e1000_ich9lan,
432 e1000_ich10lan,
433 e1000_pchlan,
434 e1000_pch2lan,
435 e1000_pch_lpt,
436};
437
438enum e1000_media_type {
439 e1000_media_type_unknown = 0,
440 e1000_media_type_copper = 1,
441 e1000_media_type_fiber = 2,
442 e1000_media_type_internal_serdes = 3,
443 e1000_num_media_types
444};
445
446enum e1000_nvm_type {
447 e1000_nvm_unknown = 0,
448 e1000_nvm_none,
449 e1000_nvm_eeprom_spi,
450 e1000_nvm_flash_hw,
451 e1000_nvm_flash_sw
452};
453
454enum e1000_nvm_override {
455 e1000_nvm_override_none = 0,
456 e1000_nvm_override_spi_small,
457 e1000_nvm_override_spi_large
458};
459
460enum e1000_phy_type {
461 e1000_phy_unknown = 0,
462 e1000_phy_none,
463 e1000_phy_m88,
464 e1000_phy_igp,
465 e1000_phy_igp_2,
466 e1000_phy_gg82563,
467 e1000_phy_igp_3,
468 e1000_phy_ife,
469 e1000_phy_bm,
470 e1000_phy_82578,
471 e1000_phy_82577,
472 e1000_phy_82579,
473 e1000_phy_i217,
474};
475
476enum e1000_bus_width {
477 e1000_bus_width_unknown = 0,
478 e1000_bus_width_pcie_x1,
479 e1000_bus_width_pcie_x2,
480 e1000_bus_width_pcie_x4 = 4,
481 e1000_bus_width_32,
482 e1000_bus_width_64,
483 e1000_bus_width_reserved
484};
485
486enum e1000_1000t_rx_status {
487 e1000_1000t_rx_status_not_ok = 0,
488 e1000_1000t_rx_status_ok,
489 e1000_1000t_rx_status_undefined = 0xFF
490};
491
492enum e1000_rev_polarity{
493 e1000_rev_polarity_normal = 0,
494 e1000_rev_polarity_reversed,
495 e1000_rev_polarity_undefined = 0xFF
496};
497
498enum e1000_fc_mode {
499 e1000_fc_none = 0,
500 e1000_fc_rx_pause,
501 e1000_fc_tx_pause,
502 e1000_fc_full,
503 e1000_fc_default = 0xFF
504};
505
506enum e1000_ms_type {
507 e1000_ms_hw_default = 0,
508 e1000_ms_force_master,
509 e1000_ms_force_slave,
510 e1000_ms_auto
511};
512
513enum e1000_smart_speed {
514 e1000_smart_speed_default = 0,
515 e1000_smart_speed_on,
516 e1000_smart_speed_off
517};
518
519enum e1000_serdes_link_state {
520 e1000_serdes_link_down = 0,
521 e1000_serdes_link_autoneg_progress,
522 e1000_serdes_link_autoneg_complete,
523 e1000_serdes_link_forced_up
524};
525
526/* Receive Descriptor */
527struct e1000_rx_desc {
528 __le64 buffer_addr; /* Address of the descriptor's data buffer */
529 __le16 length; /* Length of data DMAed into data buffer */
530 __le16 csum; /* Packet checksum */
531 u8 status; /* Descriptor status */
532 u8 errors; /* Descriptor Errors */
533 __le16 special;
534};
535
536/* Receive Descriptor - Extended */
537union e1000_rx_desc_extended {
538 struct {
539 __le64 buffer_addr;
540 __le64 reserved;
541 } read;
542 struct {
543 struct {
544 __le32 mrq; /* Multiple Rx Queues */
545 union {
546 __le32 rss; /* RSS Hash */
547 struct {
548 __le16 ip_id; /* IP id */
549 __le16 csum; /* Packet Checksum */
550 } csum_ip;
551 } hi_dword;
552 } lower;
553 struct {
554 __le32 status_error; /* ext status/error */
555 __le16 length;
556 __le16 vlan; /* VLAN tag */
557 } upper;
558 } wb; /* writeback */
559};
560
561#define MAX_PS_BUFFERS 4
562/* Receive Descriptor - Packet Split */
563union e1000_rx_desc_packet_split {
564 struct {
565 /* one buffer for protocol header(s), three data buffers */
566 __le64 buffer_addr[MAX_PS_BUFFERS];
567 } read;
568 struct {
569 struct {
570 __le32 mrq; /* Multiple Rx Queues */
571 union {
572 __le32 rss; /* RSS Hash */
573 struct {
574 __le16 ip_id; /* IP id */
575 __le16 csum; /* Packet Checksum */
576 } csum_ip;
577 } hi_dword;
578 } lower;
579 struct {
580 __le32 status_error; /* ext status/error */
581 __le16 length0; /* length of buffer 0 */
582 __le16 vlan; /* VLAN tag */
583 } middle;
584 struct {
585 __le16 header_status;
586 __le16 length[3]; /* length of buffers 1-3 */
587 } upper;
588 __le64 reserved;
589 } wb; /* writeback */
590};
591
592/* Transmit Descriptor */
593struct e1000_tx_desc {
594 __le64 buffer_addr; /* Address of the descriptor's data buffer */
595 union {
596 __le32 data;
597 struct {
598 __le16 length; /* Data buffer length */
599 u8 cso; /* Checksum offset */
600 u8 cmd; /* Descriptor control */
601 } flags;
602 } lower;
603 union {
604 __le32 data;
605 struct {
606 u8 status; /* Descriptor status */
607 u8 css; /* Checksum start */
608 __le16 special;
609 } fields;
610 } upper;
611};
612
613/* Offload Context Descriptor */
614struct e1000_context_desc {
615 union {
616 __le32 ip_config;
617 struct {
618 u8 ipcss; /* IP checksum start */
619 u8 ipcso; /* IP checksum offset */
620 __le16 ipcse; /* IP checksum end */
621 } ip_fields;
622 } lower_setup;
623 union {
624 __le32 tcp_config;
625 struct {
626 u8 tucss; /* TCP checksum start */
627 u8 tucso; /* TCP checksum offset */
628 __le16 tucse; /* TCP checksum end */
629 } tcp_fields;
630 } upper_setup;
631 __le32 cmd_and_length;
632 union {
633 __le32 data;
634 struct {
635 u8 status; /* Descriptor status */
636 u8 hdr_len; /* Header length */
637 __le16 mss; /* Maximum segment size */
638 } fields;
639 } tcp_seg_setup;
640};
641
642/* Offload data descriptor */
643struct e1000_data_desc {
644 __le64 buffer_addr; /* Address of the descriptor's buffer address */
645 union {
646 __le32 data;
647 struct {
648 __le16 length; /* Data buffer length */
649 u8 typ_len_ext;
650 u8 cmd;
651 } flags;
652 } lower;
653 union {
654 __le32 data;
655 struct {
656 u8 status; /* Descriptor status */
657 u8 popts; /* Packet Options */
658 __le16 special; /* */
659 } fields;
660 } upper;
661};
662
663/* Statistics counters collected by the MAC */
664struct e1000_hw_stats {
665 u64 crcerrs;
666 u64 algnerrc;
667 u64 symerrs;
668 u64 rxerrc;
669 u64 mpc;
670 u64 scc;
671 u64 ecol;
672 u64 mcc;
673 u64 latecol;
674 u64 colc;
675 u64 dc;
676 u64 tncrs;
677 u64 sec;
678 u64 cexterr;
679 u64 rlec;
680 u64 xonrxc;
681 u64 xontxc;
682 u64 xoffrxc;
683 u64 xofftxc;
684 u64 fcruc;
685 u64 prc64;
686 u64 prc127;
687 u64 prc255;
688 u64 prc511;
689 u64 prc1023;
690 u64 prc1522;
691 u64 gprc;
692 u64 bprc;
693 u64 mprc;
694 u64 gptc;
695 u64 gorc;
696 u64 gotc;
697 u64 rnbc;
698 u64 ruc;
699 u64 rfc;
700 u64 roc;
701 u64 rjc;
702 u64 mgprc;
703 u64 mgpdc;
704 u64 mgptc;
705 u64 tor;
706 u64 tot;
707 u64 tpr;
708 u64 tpt;
709 u64 ptc64;
710 u64 ptc127;
711 u64 ptc255;
712 u64 ptc511;
713 u64 ptc1023;
714 u64 ptc1522;
715 u64 mptc;
716 u64 bptc;
717 u64 tsctc;
718 u64 tsctfc;
719 u64 iac;
720 u64 icrxptc;
721 u64 icrxatc;
722 u64 ictxptc;
723 u64 ictxatc;
724 u64 ictxqec;
725 u64 ictxqmtc;
726 u64 icrxdmtc;
727 u64 icrxoc;
728};
729
730struct e1000_phy_stats {
731 u32 idle_errors;
732 u32 receive_errors;
733};
734
735struct e1000_host_mng_dhcp_cookie {
736 u32 signature;
737 u8 status;
738 u8 reserved0;
739 u16 vlan_id;
740 u32 reserved1;
741 u16 reserved2;
742 u8 reserved3;
743 u8 checksum;
744};
745
746/* Host Interface "Rev 1" */
747struct e1000_host_command_header {
748 u8 command_id;
749 u8 command_length;
750 u8 command_options;
751 u8 checksum;
752};
753
754#define E1000_HI_MAX_DATA_LENGTH 252
755struct e1000_host_command_info {
756 struct e1000_host_command_header command_header;
757 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
758};
759
760/* Host Interface "Rev 2" */
761struct e1000_host_mng_command_header {
762 u8 command_id;
763 u8 checksum;
764 u16 reserved1;
765 u16 reserved2;
766 u16 command_length;
767};
768
769#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
770struct e1000_host_mng_command_info {
771 struct e1000_host_mng_command_header command_header;
772 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
773};
774
775/* Function pointers and static data for the MAC. */
776struct e1000_mac_operations {
777 s32 (*id_led_init)(struct e1000_hw *);
778 s32 (*blink_led)(struct e1000_hw *);
779 bool (*check_mng_mode)(struct e1000_hw *);
780 s32 (*check_for_link)(struct e1000_hw *);
781 s32 (*cleanup_led)(struct e1000_hw *);
782 void (*clear_hw_cntrs)(struct e1000_hw *);
783 void (*clear_vfta)(struct e1000_hw *);
784 s32 (*get_bus_info)(struct e1000_hw *);
785 void (*set_lan_id)(struct e1000_hw *);
786 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
787 s32 (*led_on)(struct e1000_hw *);
788 s32 (*led_off)(struct e1000_hw *);
789 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
790 s32 (*reset_hw)(struct e1000_hw *);
791 s32 (*init_hw)(struct e1000_hw *);
792 s32 (*setup_link)(struct e1000_hw *);
793 s32 (*setup_physical_interface)(struct e1000_hw *);
794 s32 (*setup_led)(struct e1000_hw *);
795 void (*write_vfta)(struct e1000_hw *, u32, u32);
796 void (*config_collision_dist)(struct e1000_hw *);
797 void (*rar_set)(struct e1000_hw *, u8 *, u32);
798 s32 (*read_mac_addr)(struct e1000_hw *);
799};
800
801/*
802 * When to use various PHY register access functions:
803 *
804 * Func Caller
805 * Function Does Does When to use
806 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
807 * X_reg L,P,A n/a for simple PHY reg accesses
808 * X_reg_locked P,A L for multiple accesses of different regs
809 * on different pages
810 * X_reg_page A L,P for multiple accesses of different regs
811 * on the same page
812 *
813 * Where X=[read|write], L=locking, P=sets page, A=register access
814 *
815 */
816struct e1000_phy_operations {
817 s32 (*acquire)(struct e1000_hw *);
818 s32 (*cfg_on_link_up)(struct e1000_hw *);
819 s32 (*check_polarity)(struct e1000_hw *);
820 s32 (*check_reset_block)(struct e1000_hw *);
821 s32 (*commit)(struct e1000_hw *);
822 s32 (*force_speed_duplex)(struct e1000_hw *);
823 s32 (*get_cfg_done)(struct e1000_hw *hw);
824 s32 (*get_cable_length)(struct e1000_hw *);
825 s32 (*get_info)(struct e1000_hw *);
826 s32 (*set_page)(struct e1000_hw *, u16);
827 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
828 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
829 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
830 void (*release)(struct e1000_hw *);
831 s32 (*reset)(struct e1000_hw *);
832 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
833 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
834 s32 (*write_reg)(struct e1000_hw *, u32, u16);
835 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
836 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
837 void (*power_up)(struct e1000_hw *);
838 void (*power_down)(struct e1000_hw *);
839};
840
841/* Function pointers for the NVM. */
842struct e1000_nvm_operations {
843 s32 (*acquire)(struct e1000_hw *);
844 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
845 void (*release)(struct e1000_hw *);
846 void (*reload)(struct e1000_hw *);
847 s32 (*update)(struct e1000_hw *);
848 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
849 s32 (*validate)(struct e1000_hw *);
850 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
851};
852
853struct e1000_mac_info {
854 struct e1000_mac_operations ops;
855 u8 addr[ETH_ALEN];
856 u8 perm_addr[ETH_ALEN];
857
858 enum e1000_mac_type type;
859
860 u32 collision_delta;
861 u32 ledctl_default;
862 u32 ledctl_mode1;
863 u32 ledctl_mode2;
864 u32 mc_filter_type;
865 u32 tx_packet_delta;
866 u32 txcw;
867
868 u16 current_ifs_val;
869 u16 ifs_max_val;
870 u16 ifs_min_val;
871 u16 ifs_ratio;
872 u16 ifs_step_size;
873 u16 mta_reg_count;
874
875 /* Maximum size of the MTA register table in all supported adapters */
876 #define MAX_MTA_REG 128
877 u32 mta_shadow[MAX_MTA_REG];
878 u16 rar_entry_count;
879
880 u8 forced_speed_duplex;
881
882 bool adaptive_ifs;
883 bool has_fwsm;
884 bool arc_subsystem_valid;
885 bool autoneg;
886 bool autoneg_failed;
887 bool get_link_status;
888 bool in_ifs_mode;
889 bool serdes_has_link;
890 bool tx_pkt_filtering;
891 enum e1000_serdes_link_state serdes_link_state;
892};
893
894struct e1000_phy_info {
895 struct e1000_phy_operations ops;
896
897 enum e1000_phy_type type;
898
899 enum e1000_1000t_rx_status local_rx;
900 enum e1000_1000t_rx_status remote_rx;
901 enum e1000_ms_type ms_type;
902 enum e1000_ms_type original_ms_type;
903 enum e1000_rev_polarity cable_polarity;
904 enum e1000_smart_speed smart_speed;
905
906 u32 addr;
907 u32 id;
908 u32 reset_delay_us; /* in usec */
909 u32 revision;
910
911 enum e1000_media_type media_type;
912
913 u16 autoneg_advertised;
914 u16 autoneg_mask;
915 u16 cable_length;
916 u16 max_cable_length;
917 u16 min_cable_length;
918
919 u8 mdix;
920
921 bool disable_polarity_correction;
922 bool is_mdix;
923 bool polarity_correction;
924 bool speed_downgraded;
925 bool autoneg_wait_to_complete;
926};
927
928struct e1000_nvm_info {
929 struct e1000_nvm_operations ops;
930
931 enum e1000_nvm_type type;
932 enum e1000_nvm_override override;
933
934 u32 flash_bank_size;
935 u32 flash_base_addr;
936
937 u16 word_size;
938 u16 delay_usec;
939 u16 address_bits;
940 u16 opcode_bits;
941 u16 page_size;
942};
943
944struct e1000_bus_info {
945 enum e1000_bus_width width;
946
947 u16 func;
948};
949
950struct e1000_fc_info {
951 u32 high_water; /* Flow control high-water mark */
952 u32 low_water; /* Flow control low-water mark */
953 u16 pause_time; /* Flow control pause timer */
954 u16 refresh_time; /* Flow control refresh timer */
955 bool send_xon; /* Flow control send XON */
956 bool strict_ieee; /* Strict IEEE mode */
957 enum e1000_fc_mode current_mode; /* FC mode in effect */
958 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
959};
960
961struct e1000_dev_spec_82571 {
962 bool laa_is_present;
963 u32 smb_counter;
964};
965
966struct e1000_dev_spec_80003es2lan {
967 bool mdic_wa_enable;
968};
969
970struct e1000_shadow_ram {
971 u16 value;
972 bool modified;
973};
974
975#define E1000_ICH8_SHADOW_RAM_WORDS 2048
976
977struct e1000_dev_spec_ich8lan {
978 bool kmrn_lock_loss_workaround_enabled;
979 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
980 bool nvm_k1_enabled;
981 bool eee_disable;
982 u16 eee_lp_ability;
983};
984
985struct e1000_hw {
986 struct e1000_adapter *adapter;
987
988 void __iomem *hw_addr;
989 void __iomem *flash_address;
990
991 struct e1000_mac_info mac;
992 struct e1000_fc_info fc;
993 struct e1000_phy_info phy;
994 struct e1000_nvm_info nvm;
995 struct e1000_bus_info bus;
996 struct e1000_host_mng_dhcp_cookie mng_cookie;
997
998 union {
999 struct e1000_dev_spec_82571 e82571;
1000 struct e1000_dev_spec_80003es2lan e80003es2lan;
1001 struct e1000_dev_spec_ich8lan ich8lan;
1002 } dev_spec;
1003};
1004
1005#endif