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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx XADC driver
4 *
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 *
8 * Documentation for the parts can be found at:
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
12 */
13
14#include <linux/clk.h>
15#include <linux/device.h>
16#include <linux/err.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/mod_devicetable.h>
21#include <linux/module.h>
22#include <linux/overflow.h>
23#include <linux/platform_device.h>
24#include <linux/property.h>
25#include <linux/slab.h>
26#include <linux/sysfs.h>
27
28#include <linux/iio/buffer.h>
29#include <linux/iio/events.h>
30#include <linux/iio/iio.h>
31#include <linux/iio/sysfs.h>
32#include <linux/iio/trigger.h>
33#include <linux/iio/trigger_consumer.h>
34#include <linux/iio/triggered_buffer.h>
35
36#include "xilinx-xadc.h"
37
38static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
39
40/* ZYNQ register definitions */
41#define XADC_ZYNQ_REG_CFG 0x00
42#define XADC_ZYNQ_REG_INTSTS 0x04
43#define XADC_ZYNQ_REG_INTMSK 0x08
44#define XADC_ZYNQ_REG_STATUS 0x0c
45#define XADC_ZYNQ_REG_CFIFO 0x10
46#define XADC_ZYNQ_REG_DFIFO 0x14
47#define XADC_ZYNQ_REG_CTL 0x18
48
49#define XADC_ZYNQ_CFG_ENABLE BIT(31)
50#define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
51#define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
52#define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
53#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
54#define XADC_ZYNQ_CFG_WEDGE BIT(13)
55#define XADC_ZYNQ_CFG_REDGE BIT(12)
56#define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
57#define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
58#define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
59#define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
60#define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
61#define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
62#define XADC_ZYNQ_CFG_IGAP(x) (x)
63
64#define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
65#define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
66#define XADC_ZYNQ_INT_ALARM_MASK 0xff
67#define XADC_ZYNQ_INT_ALARM_OFFSET 0
68
69#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
70#define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
71#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
72#define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
73#define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
74#define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
75#define XADC_ZYNQ_STATUS_DFIFOF BIT(9)
76#define XADC_ZYNQ_STATUS_DFIFOE BIT(8)
77#define XADC_ZYNQ_STATUS_OT BIT(7)
78#define XADC_ZYNQ_STATUS_ALM(x) BIT(x)
79
80#define XADC_ZYNQ_CTL_RESET BIT(4)
81
82#define XADC_ZYNQ_CMD_NOP 0x00
83#define XADC_ZYNQ_CMD_READ 0x01
84#define XADC_ZYNQ_CMD_WRITE 0x02
85
86#define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
87
88/* AXI register definitions */
89#define XADC_AXI_REG_RESET 0x00
90#define XADC_AXI_REG_STATUS 0x04
91#define XADC_AXI_REG_ALARM_STATUS 0x08
92#define XADC_AXI_REG_CONVST 0x0c
93#define XADC_AXI_REG_XADC_RESET 0x10
94#define XADC_AXI_REG_GIER 0x5c
95#define XADC_AXI_REG_IPISR 0x60
96#define XADC_AXI_REG_IPIER 0x68
97
98/* 7 Series */
99#define XADC_7S_AXI_ADC_REG_OFFSET 0x200
100
101/* UltraScale */
102#define XADC_US_AXI_ADC_REG_OFFSET 0x400
103
104#define XADC_AXI_RESET_MAGIC 0xa
105#define XADC_AXI_GIER_ENABLE BIT(31)
106
107#define XADC_AXI_INT_EOS BIT(4)
108#define XADC_AXI_INT_ALARM_MASK 0x3c0f
109
110#define XADC_FLAGS_BUFFERED BIT(0)
111#define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
112
113/*
114 * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
115 * not have a hardware FIFO. Which means an interrupt is generated for each
116 * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
117 * overloaded by the interrupts that it soft-lockups. For this reason the driver
118 * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
119 * but still responsive.
120 */
121#define XADC_MAX_SAMPLERATE 150000
122
123static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
124 uint32_t val)
125{
126 writel(val, xadc->base + reg);
127}
128
129static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
130 uint32_t *val)
131{
132 *val = readl(xadc->base + reg);
133}
134
135/*
136 * The ZYNQ interface uses two asynchronous FIFOs for communication with the
137 * XADC. Reads and writes to the XADC register are performed by submitting a
138 * request to the command FIFO (CFIFO), once the request has been completed the
139 * result can be read from the data FIFO (DFIFO). The method currently used in
140 * this driver is to submit the request for a read/write operation, then go to
141 * sleep and wait for an interrupt that signals that a response is available in
142 * the data FIFO.
143 */
144
145static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
146 unsigned int n)
147{
148 unsigned int i;
149
150 for (i = 0; i < n; i++)
151 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
152}
153
154static void xadc_zynq_drain_fifo(struct xadc *xadc)
155{
156 uint32_t status, tmp;
157
158 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
159
160 while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
161 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
162 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
163 }
164}
165
166static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
167 unsigned int val)
168{
169 xadc->zynq_intmask &= ~mask;
170 xadc->zynq_intmask |= val;
171
172 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
173 xadc->zynq_intmask | xadc->zynq_masked_alarm);
174}
175
176static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
177 uint16_t val)
178{
179 uint32_t cmd[1];
180 uint32_t tmp;
181 int ret;
182
183 spin_lock_irq(&xadc->lock);
184 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
185 XADC_ZYNQ_INT_DFIFO_GTH);
186
187 reinit_completion(&xadc->completion);
188
189 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
190 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
191 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
192 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
193 tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
194 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
195
196 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
197 spin_unlock_irq(&xadc->lock);
198
199 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
200 if (ret == 0)
201 ret = -EIO;
202 else
203 ret = 0;
204
205 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
206
207 return ret;
208}
209
210static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
211 uint16_t *val)
212{
213 uint32_t cmd[2];
214 uint32_t resp, tmp;
215 int ret;
216
217 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
218 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
219
220 spin_lock_irq(&xadc->lock);
221 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
222 XADC_ZYNQ_INT_DFIFO_GTH);
223 xadc_zynq_drain_fifo(xadc);
224 reinit_completion(&xadc->completion);
225
226 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
227 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
228 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
229 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
230 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
231
232 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
233 spin_unlock_irq(&xadc->lock);
234 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
235 if (ret == 0)
236 ret = -EIO;
237 if (ret < 0)
238 return ret;
239
240 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
241 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
242
243 *val = resp & 0xffff;
244
245 return 0;
246}
247
248static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
249{
250 return ((alarm & 0x80) >> 4) |
251 ((alarm & 0x78) << 1) |
252 (alarm & 0x07);
253}
254
255/*
256 * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
257 * threshold condition go way from within the interrupt handler, this means as
258 * soon as a threshold condition is present we would enter the interrupt handler
259 * again and again. To work around this we mask all active thresholds interrupts
260 * in the interrupt handler and start a timer. In this timer we poll the
261 * interrupt status and only if the interrupt is inactive we unmask it again.
262 */
263static void xadc_zynq_unmask_worker(struct work_struct *work)
264{
265 struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
266 unsigned int misc_sts, unmask;
267
268 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
269
270 misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
271
272 spin_lock_irq(&xadc->lock);
273
274 /* Clear those bits which are not active anymore */
275 unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
276 xadc->zynq_masked_alarm &= misc_sts;
277
278 /* Also clear those which are masked out anyway */
279 xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
280
281 /* Clear the interrupts before we unmask them */
282 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
283
284 xadc_zynq_update_intmsk(xadc, 0, 0);
285
286 spin_unlock_irq(&xadc->lock);
287
288 /* if still pending some alarm re-trigger the timer */
289 if (xadc->zynq_masked_alarm) {
290 schedule_delayed_work(&xadc->zynq_unmask_work,
291 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
292 }
293
294}
295
296static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
297{
298 struct iio_dev *indio_dev = devid;
299 struct xadc *xadc = iio_priv(indio_dev);
300 uint32_t status;
301
302 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
303
304 status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
305
306 if (!status)
307 return IRQ_NONE;
308
309 spin_lock(&xadc->lock);
310
311 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
312
313 if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
314 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
315 XADC_ZYNQ_INT_DFIFO_GTH);
316 complete(&xadc->completion);
317 }
318
319 status &= XADC_ZYNQ_INT_ALARM_MASK;
320 if (status) {
321 xadc->zynq_masked_alarm |= status;
322 /*
323 * mask the current event interrupt,
324 * unmask it when the interrupt is no more active.
325 */
326 xadc_zynq_update_intmsk(xadc, 0, 0);
327
328 xadc_handle_events(indio_dev,
329 xadc_zynq_transform_alarm(status));
330
331 /* unmask the required interrupts in timer. */
332 schedule_delayed_work(&xadc->zynq_unmask_work,
333 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
334 }
335 spin_unlock(&xadc->lock);
336
337 return IRQ_HANDLED;
338}
339
340#define XADC_ZYNQ_TCK_RATE_MAX 50000000
341#define XADC_ZYNQ_IGAP_DEFAULT 20
342#define XADC_ZYNQ_PCAP_RATE_MAX 200000000
343
344static int xadc_zynq_setup(struct platform_device *pdev,
345 struct iio_dev *indio_dev, int irq)
346{
347 struct xadc *xadc = iio_priv(indio_dev);
348 unsigned long pcap_rate;
349 unsigned int tck_div;
350 unsigned int div;
351 unsigned int igap;
352 unsigned int tck_rate;
353 int ret;
354
355 /* TODO: Figure out how to make igap and tck_rate configurable */
356 igap = XADC_ZYNQ_IGAP_DEFAULT;
357 tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
358
359 xadc->zynq_intmask = ~0;
360
361 pcap_rate = clk_get_rate(xadc->clk);
362 if (!pcap_rate)
363 return -EINVAL;
364
365 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
366 ret = clk_set_rate(xadc->clk,
367 (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
368 if (ret)
369 return ret;
370 }
371
372 if (tck_rate > pcap_rate / 2) {
373 div = 2;
374 } else {
375 div = pcap_rate / tck_rate;
376 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
377 div++;
378 }
379
380 if (div <= 3)
381 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
382 else if (div <= 7)
383 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
384 else if (div <= 15)
385 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
386 else
387 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
388
389 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
390 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
391 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
392 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
393 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
394 XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
395 tck_div | XADC_ZYNQ_CFG_IGAP(igap));
396
397 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
398 ret = clk_set_rate(xadc->clk, pcap_rate);
399 if (ret)
400 return ret;
401 }
402
403 return 0;
404}
405
406static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
407{
408 unsigned int div;
409 uint32_t val;
410
411 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
412
413 switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
414 case XADC_ZYNQ_CFG_TCKRATE_DIV4:
415 div = 4;
416 break;
417 case XADC_ZYNQ_CFG_TCKRATE_DIV8:
418 div = 8;
419 break;
420 case XADC_ZYNQ_CFG_TCKRATE_DIV16:
421 div = 16;
422 break;
423 default:
424 div = 2;
425 break;
426 }
427
428 return clk_get_rate(xadc->clk) / div;
429}
430
431static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
432{
433 unsigned long flags;
434 uint32_t status;
435
436 /* Move OT to bit 7 */
437 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
438
439 spin_lock_irqsave(&xadc->lock, flags);
440
441 /* Clear previous interrupts if any. */
442 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
443 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
444
445 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
446 ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
447
448 spin_unlock_irqrestore(&xadc->lock, flags);
449}
450
451static const struct xadc_ops xadc_zynq_ops = {
452 .read = xadc_zynq_read_adc_reg,
453 .write = xadc_zynq_write_adc_reg,
454 .setup = xadc_zynq_setup,
455 .get_dclk_rate = xadc_zynq_get_dclk_rate,
456 .interrupt_handler = xadc_zynq_interrupt_handler,
457 .update_alarm = xadc_zynq_update_alarm,
458 .type = XADC_TYPE_S7,
459 /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
460 .temp_scale = 503975,
461 .temp_offset = 273150,
462};
463
464static const unsigned int xadc_axi_reg_offsets[] = {
465 [XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
466 [XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
467};
468
469static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
470 uint16_t *val)
471{
472 uint32_t val32;
473
474 xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
475 &val32);
476 *val = val32 & 0xffff;
477
478 return 0;
479}
480
481static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
482 uint16_t val)
483{
484 xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
485 val);
486
487 return 0;
488}
489
490static int xadc_axi_setup(struct platform_device *pdev,
491 struct iio_dev *indio_dev, int irq)
492{
493 struct xadc *xadc = iio_priv(indio_dev);
494
495 xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
496 xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
497
498 return 0;
499}
500
501static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
502{
503 struct iio_dev *indio_dev = devid;
504 struct xadc *xadc = iio_priv(indio_dev);
505 uint32_t status, mask;
506 unsigned int events;
507
508 xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
509 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
510 status &= mask;
511
512 if (!status)
513 return IRQ_NONE;
514
515 if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
516 iio_trigger_poll(xadc->trigger);
517
518 if (status & XADC_AXI_INT_ALARM_MASK) {
519 /*
520 * The order of the bits in the AXI-XADC status register does
521 * not match the order of the bits in the XADC alarm enable
522 * register. xadc_handle_events() expects the events to be in
523 * the same order as the XADC alarm enable register.
524 */
525 events = (status & 0x000e) >> 1;
526 events |= (status & 0x0001) << 3;
527 events |= (status & 0x3c00) >> 6;
528 xadc_handle_events(indio_dev, events);
529 }
530
531 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
532
533 return IRQ_HANDLED;
534}
535
536static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
537{
538 uint32_t val;
539 unsigned long flags;
540
541 /*
542 * The order of the bits in the AXI-XADC status register does not match
543 * the order of the bits in the XADC alarm enable register. We get
544 * passed the alarm mask in the same order as in the XADC alarm enable
545 * register.
546 */
547 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
548 ((alarm & 0xf0) << 6);
549
550 spin_lock_irqsave(&xadc->lock, flags);
551 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
552 val &= ~XADC_AXI_INT_ALARM_MASK;
553 val |= alarm;
554 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
555 spin_unlock_irqrestore(&xadc->lock, flags);
556}
557
558static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
559{
560 return clk_get_rate(xadc->clk);
561}
562
563static const struct xadc_ops xadc_7s_axi_ops = {
564 .read = xadc_axi_read_adc_reg,
565 .write = xadc_axi_write_adc_reg,
566 .setup = xadc_axi_setup,
567 .get_dclk_rate = xadc_axi_get_dclk,
568 .update_alarm = xadc_axi_update_alarm,
569 .interrupt_handler = xadc_axi_interrupt_handler,
570 .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
571 .type = XADC_TYPE_S7,
572 /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
573 .temp_scale = 503975,
574 .temp_offset = 273150,
575};
576
577static const struct xadc_ops xadc_us_axi_ops = {
578 .read = xadc_axi_read_adc_reg,
579 .write = xadc_axi_write_adc_reg,
580 .setup = xadc_axi_setup,
581 .get_dclk_rate = xadc_axi_get_dclk,
582 .update_alarm = xadc_axi_update_alarm,
583 .interrupt_handler = xadc_axi_interrupt_handler,
584 .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
585 .type = XADC_TYPE_US,
586 /**
587 * Values below are for UltraScale+ (SYSMONE4) using internal reference.
588 * See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
589 */
590 .temp_scale = 509314,
591 .temp_offset = 280231,
592};
593
594static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
595 uint16_t mask, uint16_t val)
596{
597 uint16_t tmp;
598 int ret;
599
600 ret = _xadc_read_adc_reg(xadc, reg, &tmp);
601 if (ret)
602 return ret;
603
604 return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
605}
606
607static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
608 uint16_t mask, uint16_t val)
609{
610 int ret;
611
612 mutex_lock(&xadc->mutex);
613 ret = _xadc_update_adc_reg(xadc, reg, mask, val);
614 mutex_unlock(&xadc->mutex);
615
616 return ret;
617}
618
619static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
620{
621 return xadc->ops->get_dclk_rate(xadc);
622}
623
624static int xadc_update_scan_mode(struct iio_dev *indio_dev,
625 const unsigned long *mask)
626{
627 struct xadc *xadc = iio_priv(indio_dev);
628 size_t n;
629 void *data;
630
631 n = bitmap_weight(mask, indio_dev->masklength);
632
633 data = devm_krealloc_array(indio_dev->dev.parent, xadc->data,
634 n, sizeof(*xadc->data), GFP_KERNEL);
635 if (!data)
636 return -ENOMEM;
637
638 memset(data, 0, n * sizeof(*xadc->data));
639 xadc->data = data;
640
641 return 0;
642}
643
644static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
645{
646 switch (scan_index) {
647 case 5:
648 return XADC_REG_VCCPINT;
649 case 6:
650 return XADC_REG_VCCPAUX;
651 case 7:
652 return XADC_REG_VCCO_DDR;
653 case 8:
654 return XADC_REG_TEMP;
655 case 9:
656 return XADC_REG_VCCINT;
657 case 10:
658 return XADC_REG_VCCAUX;
659 case 11:
660 return XADC_REG_VPVN;
661 case 12:
662 return XADC_REG_VREFP;
663 case 13:
664 return XADC_REG_VREFN;
665 case 14:
666 return XADC_REG_VCCBRAM;
667 default:
668 return XADC_REG_VAUX(scan_index - 16);
669 }
670}
671
672static irqreturn_t xadc_trigger_handler(int irq, void *p)
673{
674 struct iio_poll_func *pf = p;
675 struct iio_dev *indio_dev = pf->indio_dev;
676 struct xadc *xadc = iio_priv(indio_dev);
677 unsigned int chan;
678 int i, j;
679
680 if (!xadc->data)
681 goto out;
682
683 j = 0;
684 for_each_set_bit(i, indio_dev->active_scan_mask,
685 indio_dev->masklength) {
686 chan = xadc_scan_index_to_channel(i);
687 xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
688 j++;
689 }
690
691 iio_push_to_buffers(indio_dev, xadc->data);
692
693out:
694 iio_trigger_notify_done(indio_dev->trig);
695
696 return IRQ_HANDLED;
697}
698
699static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
700{
701 struct xadc *xadc = iio_trigger_get_drvdata(trigger);
702 unsigned long flags;
703 unsigned int convst;
704 unsigned int val;
705 int ret = 0;
706
707 mutex_lock(&xadc->mutex);
708
709 if (state) {
710 /* Only one of the two triggers can be active at a time. */
711 if (xadc->trigger != NULL) {
712 ret = -EBUSY;
713 goto err_out;
714 } else {
715 xadc->trigger = trigger;
716 if (trigger == xadc->convst_trigger)
717 convst = XADC_CONF0_EC;
718 else
719 convst = 0;
720 }
721 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
722 convst);
723 if (ret)
724 goto err_out;
725 } else {
726 xadc->trigger = NULL;
727 }
728
729 spin_lock_irqsave(&xadc->lock, flags);
730 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
731 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
732 if (state)
733 val |= XADC_AXI_INT_EOS;
734 else
735 val &= ~XADC_AXI_INT_EOS;
736 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
737 spin_unlock_irqrestore(&xadc->lock, flags);
738
739err_out:
740 mutex_unlock(&xadc->mutex);
741
742 return ret;
743}
744
745static const struct iio_trigger_ops xadc_trigger_ops = {
746 .set_trigger_state = &xadc_trigger_set_state,
747};
748
749static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
750 const char *name)
751{
752 struct device *dev = indio_dev->dev.parent;
753 struct iio_trigger *trig;
754 int ret;
755
756 trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
757 iio_device_id(indio_dev), name);
758 if (trig == NULL)
759 return ERR_PTR(-ENOMEM);
760
761 trig->ops = &xadc_trigger_ops;
762 iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
763
764 ret = devm_iio_trigger_register(dev, trig);
765 if (ret)
766 return ERR_PTR(ret);
767
768 return trig;
769}
770
771static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
772{
773 uint16_t val;
774
775 /*
776 * As per datasheet the power-down bits are don't care in the
777 * UltraScale, but as per reality setting the power-down bit for the
778 * non-existing ADC-B powers down the main ADC, so just return and don't
779 * do anything.
780 */
781 if (xadc->ops->type == XADC_TYPE_US)
782 return 0;
783
784 /* Powerdown the ADC-B when it is not needed. */
785 switch (seq_mode) {
786 case XADC_CONF1_SEQ_SIMULTANEOUS:
787 case XADC_CONF1_SEQ_INDEPENDENT:
788 val = 0;
789 break;
790 default:
791 val = XADC_CONF2_PD_ADC_B;
792 break;
793 }
794
795 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
796 val);
797}
798
799static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
800{
801 unsigned int aux_scan_mode = scan_mode >> 16;
802
803 /* UltraScale has only one ADC and supports only continuous mode */
804 if (xadc->ops->type == XADC_TYPE_US)
805 return XADC_CONF1_SEQ_CONTINUOUS;
806
807 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
808 return XADC_CONF1_SEQ_SIMULTANEOUS;
809
810 if ((aux_scan_mode & 0xff00) == 0 ||
811 (aux_scan_mode & 0x00ff) == 0)
812 return XADC_CONF1_SEQ_CONTINUOUS;
813
814 return XADC_CONF1_SEQ_SIMULTANEOUS;
815}
816
817static int xadc_postdisable(struct iio_dev *indio_dev)
818{
819 struct xadc *xadc = iio_priv(indio_dev);
820 unsigned long scan_mask;
821 int ret;
822 int i;
823
824 scan_mask = 1; /* Run calibration as part of the sequence */
825 for (i = 0; i < indio_dev->num_channels; i++)
826 scan_mask |= BIT(indio_dev->channels[i].scan_index);
827
828 /* Enable all channels and calibration */
829 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
830 if (ret)
831 return ret;
832
833 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
834 if (ret)
835 return ret;
836
837 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
838 XADC_CONF1_SEQ_CONTINUOUS);
839 if (ret)
840 return ret;
841
842 return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
843}
844
845static int xadc_preenable(struct iio_dev *indio_dev)
846{
847 struct xadc *xadc = iio_priv(indio_dev);
848 unsigned long scan_mask;
849 int seq_mode;
850 int ret;
851
852 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
853 XADC_CONF1_SEQ_DEFAULT);
854 if (ret)
855 goto err;
856
857 scan_mask = *indio_dev->active_scan_mask;
858 seq_mode = xadc_get_seq_mode(xadc, scan_mask);
859
860 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
861 if (ret)
862 goto err;
863
864 /*
865 * In simultaneous mode the upper and lower aux channels are samples at
866 * the same time. In this mode the upper 8 bits in the sequencer
867 * register are don't care and the lower 8 bits control two channels
868 * each. As such we must set the bit if either the channel in the lower
869 * group or the upper group is enabled.
870 */
871 if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
872 scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
873
874 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
875 if (ret)
876 goto err;
877
878 ret = xadc_power_adc_b(xadc, seq_mode);
879 if (ret)
880 goto err;
881
882 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
883 seq_mode);
884 if (ret)
885 goto err;
886
887 return 0;
888err:
889 xadc_postdisable(indio_dev);
890 return ret;
891}
892
893static const struct iio_buffer_setup_ops xadc_buffer_ops = {
894 .preenable = &xadc_preenable,
895 .postdisable = &xadc_postdisable,
896};
897
898static int xadc_read_samplerate(struct xadc *xadc)
899{
900 unsigned int div;
901 uint16_t val16;
902 int ret;
903
904 ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
905 if (ret)
906 return ret;
907
908 div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
909 if (div < 2)
910 div = 2;
911
912 return xadc_get_dclk_rate(xadc) / div / 26;
913}
914
915static int xadc_read_raw(struct iio_dev *indio_dev,
916 struct iio_chan_spec const *chan, int *val, int *val2, long info)
917{
918 struct xadc *xadc = iio_priv(indio_dev);
919 unsigned int bits = chan->scan_type.realbits;
920 uint16_t val16;
921 int ret;
922
923 switch (info) {
924 case IIO_CHAN_INFO_RAW:
925 if (iio_buffer_enabled(indio_dev))
926 return -EBUSY;
927 ret = xadc_read_adc_reg(xadc, chan->address, &val16);
928 if (ret < 0)
929 return ret;
930
931 val16 >>= chan->scan_type.shift;
932 if (chan->scan_type.sign == 'u')
933 *val = val16;
934 else
935 *val = sign_extend32(val16, bits - 1);
936
937 return IIO_VAL_INT;
938 case IIO_CHAN_INFO_SCALE:
939 switch (chan->type) {
940 case IIO_VOLTAGE:
941 /* V = (val * 3.0) / 2**bits */
942 switch (chan->address) {
943 case XADC_REG_VCCINT:
944 case XADC_REG_VCCAUX:
945 case XADC_REG_VREFP:
946 case XADC_REG_VREFN:
947 case XADC_REG_VCCBRAM:
948 case XADC_REG_VCCPINT:
949 case XADC_REG_VCCPAUX:
950 case XADC_REG_VCCO_DDR:
951 *val = 3000;
952 break;
953 default:
954 *val = 1000;
955 break;
956 }
957 *val2 = bits;
958 return IIO_VAL_FRACTIONAL_LOG2;
959 case IIO_TEMP:
960 *val = xadc->ops->temp_scale;
961 *val2 = bits;
962 return IIO_VAL_FRACTIONAL_LOG2;
963 default:
964 return -EINVAL;
965 }
966 case IIO_CHAN_INFO_OFFSET:
967 /* Only the temperature channel has an offset */
968 *val = -((xadc->ops->temp_offset << bits) / xadc->ops->temp_scale);
969 return IIO_VAL_INT;
970 case IIO_CHAN_INFO_SAMP_FREQ:
971 ret = xadc_read_samplerate(xadc);
972 if (ret < 0)
973 return ret;
974
975 *val = ret;
976 return IIO_VAL_INT;
977 default:
978 return -EINVAL;
979 }
980}
981
982static int xadc_write_samplerate(struct xadc *xadc, int val)
983{
984 unsigned long clk_rate = xadc_get_dclk_rate(xadc);
985 unsigned int div;
986
987 if (!clk_rate)
988 return -EINVAL;
989
990 if (val <= 0)
991 return -EINVAL;
992
993 /* Max. 150 kSPS */
994 if (val > XADC_MAX_SAMPLERATE)
995 val = XADC_MAX_SAMPLERATE;
996
997 val *= 26;
998
999 /* Min 1MHz */
1000 if (val < 1000000)
1001 val = 1000000;
1002
1003 /*
1004 * We want to round down, but only if we do not exceed the 150 kSPS
1005 * limit.
1006 */
1007 div = clk_rate / val;
1008 if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
1009 div++;
1010 if (div < 2)
1011 div = 2;
1012 else if (div > 0xff)
1013 div = 0xff;
1014
1015 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
1016 div << XADC_CONF2_DIV_OFFSET);
1017}
1018
1019static int xadc_write_raw(struct iio_dev *indio_dev,
1020 struct iio_chan_spec const *chan, int val, int val2, long info)
1021{
1022 struct xadc *xadc = iio_priv(indio_dev);
1023
1024 if (info != IIO_CHAN_INFO_SAMP_FREQ)
1025 return -EINVAL;
1026
1027 return xadc_write_samplerate(xadc, val);
1028}
1029
1030static const struct iio_event_spec xadc_temp_events[] = {
1031 {
1032 .type = IIO_EV_TYPE_THRESH,
1033 .dir = IIO_EV_DIR_RISING,
1034 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1035 BIT(IIO_EV_INFO_VALUE) |
1036 BIT(IIO_EV_INFO_HYSTERESIS),
1037 },
1038};
1039
1040/* Separate values for upper and lower thresholds, but only a shared enabled */
1041static const struct iio_event_spec xadc_voltage_events[] = {
1042 {
1043 .type = IIO_EV_TYPE_THRESH,
1044 .dir = IIO_EV_DIR_RISING,
1045 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1046 }, {
1047 .type = IIO_EV_TYPE_THRESH,
1048 .dir = IIO_EV_DIR_FALLING,
1049 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1050 }, {
1051 .type = IIO_EV_TYPE_THRESH,
1052 .dir = IIO_EV_DIR_EITHER,
1053 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1054 },
1055};
1056
1057#define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
1058 .type = IIO_TEMP, \
1059 .indexed = 1, \
1060 .channel = (_chan), \
1061 .address = (_addr), \
1062 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1063 BIT(IIO_CHAN_INFO_SCALE) | \
1064 BIT(IIO_CHAN_INFO_OFFSET), \
1065 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1066 .event_spec = xadc_temp_events, \
1067 .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
1068 .scan_index = (_scan_index), \
1069 .scan_type = { \
1070 .sign = 'u', \
1071 .realbits = (_bits), \
1072 .storagebits = 16, \
1073 .shift = 16 - (_bits), \
1074 .endianness = IIO_CPU, \
1075 }, \
1076}
1077
1078#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
1079 .type = IIO_VOLTAGE, \
1080 .indexed = 1, \
1081 .channel = (_chan), \
1082 .address = (_addr), \
1083 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1084 BIT(IIO_CHAN_INFO_SCALE), \
1085 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1086 .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
1087 .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
1088 .scan_index = (_scan_index), \
1089 .scan_type = { \
1090 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1091 .realbits = (_bits), \
1092 .storagebits = 16, \
1093 .shift = 16 - (_bits), \
1094 .endianness = IIO_CPU, \
1095 }, \
1096 .extend_name = _ext, \
1097}
1098
1099/* 7 Series */
1100#define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
1101 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1102#define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1103 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
1104
1105static const struct iio_chan_spec xadc_7s_channels[] = {
1106 XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1107 XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1108 XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1109 XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1110 XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1111 XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1112 XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1113 XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1114 XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1115 XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1116 XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1117 XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1118 XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1119 XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1120 XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1121 XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1122 XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1123 XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1124 XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1125 XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1126 XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1127 XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1128 XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1129 XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1130 XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1131 XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1132};
1133
1134/* UltraScale */
1135#define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
1136 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
1137#define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1138 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
1139
1140static const struct iio_chan_spec xadc_us_channels[] = {
1141 XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1142 XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1143 XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1144 XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1145 XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
1146 XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
1147 XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
1148 XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1149 XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1150 XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1151 XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1152 XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1153 XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1154 XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1155 XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1156 XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1157 XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1158 XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1159 XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1160 XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1161 XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1162 XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1163 XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1164 XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1165 XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1166 XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1167};
1168
1169static const struct iio_info xadc_info = {
1170 .read_raw = &xadc_read_raw,
1171 .write_raw = &xadc_write_raw,
1172 .read_event_config = &xadc_read_event_config,
1173 .write_event_config = &xadc_write_event_config,
1174 .read_event_value = &xadc_read_event_value,
1175 .write_event_value = &xadc_write_event_value,
1176 .update_scan_mode = &xadc_update_scan_mode,
1177};
1178
1179static const struct of_device_id xadc_of_match_table[] = {
1180 {
1181 .compatible = "xlnx,zynq-xadc-1.00.a",
1182 .data = &xadc_zynq_ops
1183 }, {
1184 .compatible = "xlnx,axi-xadc-1.00.a",
1185 .data = &xadc_7s_axi_ops
1186 }, {
1187 .compatible = "xlnx,system-management-wiz-1.3",
1188 .data = &xadc_us_axi_ops
1189 },
1190 { },
1191};
1192MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1193
1194static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
1195{
1196 struct device *dev = indio_dev->dev.parent;
1197 struct xadc *xadc = iio_priv(indio_dev);
1198 const struct iio_chan_spec *channel_templates;
1199 struct iio_chan_spec *channels, *chan;
1200 struct fwnode_handle *chan_node, *child;
1201 unsigned int max_channels;
1202 unsigned int num_channels;
1203 const char *external_mux;
1204 u32 ext_mux_chan;
1205 u32 reg;
1206 int ret;
1207 int i;
1208
1209 *conf = 0;
1210
1211 ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux);
1212 if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1213 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1214 else if (strcasecmp(external_mux, "single") == 0)
1215 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1216 else if (strcasecmp(external_mux, "dual") == 0)
1217 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1218 else
1219 return -EINVAL;
1220
1221 if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1222 ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan);
1223 if (ret < 0)
1224 return ret;
1225
1226 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1227 if (ext_mux_chan == 0)
1228 ext_mux_chan = XADC_REG_VPVN;
1229 else if (ext_mux_chan <= 16)
1230 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1231 else
1232 return -EINVAL;
1233 } else {
1234 if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1235 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1236 else
1237 return -EINVAL;
1238 }
1239
1240 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1241 }
1242 if (xadc->ops->type == XADC_TYPE_S7) {
1243 channel_templates = xadc_7s_channels;
1244 max_channels = ARRAY_SIZE(xadc_7s_channels);
1245 } else {
1246 channel_templates = xadc_us_channels;
1247 max_channels = ARRAY_SIZE(xadc_us_channels);
1248 }
1249 channels = devm_kmemdup(dev, channel_templates,
1250 sizeof(channels[0]) * max_channels, GFP_KERNEL);
1251 if (!channels)
1252 return -ENOMEM;
1253
1254 num_channels = 9;
1255 chan = &channels[9];
1256
1257 chan_node = device_get_named_child_node(dev, "xlnx,channels");
1258 fwnode_for_each_child_node(chan_node, child) {
1259 if (num_channels >= max_channels) {
1260 fwnode_handle_put(child);
1261 break;
1262 }
1263
1264 ret = fwnode_property_read_u32(child, "reg", ®);
1265 if (ret || reg > 16)
1266 continue;
1267
1268 if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1269 chan->scan_type.sign = 's';
1270
1271 if (reg == 0) {
1272 chan->scan_index = 11;
1273 chan->address = XADC_REG_VPVN;
1274 } else {
1275 chan->scan_index = 15 + reg;
1276 chan->address = XADC_REG_VAUX(reg - 1);
1277 }
1278 num_channels++;
1279 chan++;
1280 }
1281 fwnode_handle_put(chan_node);
1282
1283 /* No IRQ => no events */
1284 if (irq <= 0) {
1285 for (i = 0; i < num_channels; i++) {
1286 channels[i].event_spec = NULL;
1287 channels[i].num_event_specs = 0;
1288 }
1289 }
1290
1291 indio_dev->num_channels = num_channels;
1292 indio_dev->channels = devm_krealloc_array(dev, channels,
1293 num_channels, sizeof(*channels),
1294 GFP_KERNEL);
1295 /* If we can't resize the channels array, just use the original */
1296 if (!indio_dev->channels)
1297 indio_dev->channels = channels;
1298
1299 return 0;
1300}
1301
1302static const char * const xadc_type_names[] = {
1303 [XADC_TYPE_S7] = "xadc",
1304 [XADC_TYPE_US] = "xilinx-system-monitor",
1305};
1306
1307static void xadc_cancel_delayed_work(void *data)
1308{
1309 struct delayed_work *work = data;
1310
1311 cancel_delayed_work_sync(work);
1312}
1313
1314static int xadc_probe(struct platform_device *pdev)
1315{
1316 struct device *dev = &pdev->dev;
1317 const struct xadc_ops *ops;
1318 struct iio_dev *indio_dev;
1319 unsigned int bipolar_mask;
1320 unsigned int conf0;
1321 struct xadc *xadc;
1322 int ret;
1323 int irq;
1324 int i;
1325
1326 ops = device_get_match_data(dev);
1327 if (!ops)
1328 return -EINVAL;
1329
1330 irq = platform_get_irq_optional(pdev, 0);
1331 if (irq < 0 &&
1332 (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
1333 return irq;
1334
1335 indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
1336 if (!indio_dev)
1337 return -ENOMEM;
1338
1339 xadc = iio_priv(indio_dev);
1340 xadc->ops = ops;
1341 init_completion(&xadc->completion);
1342 mutex_init(&xadc->mutex);
1343 spin_lock_init(&xadc->lock);
1344 INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1345
1346 xadc->base = devm_platform_ioremap_resource(pdev, 0);
1347 if (IS_ERR(xadc->base))
1348 return PTR_ERR(xadc->base);
1349
1350 indio_dev->name = xadc_type_names[xadc->ops->type];
1351 indio_dev->modes = INDIO_DIRECT_MODE;
1352 indio_dev->info = &xadc_info;
1353
1354 ret = xadc_parse_dt(indio_dev, &conf0, irq);
1355 if (ret)
1356 return ret;
1357
1358 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1359 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1360 &iio_pollfunc_store_time,
1361 &xadc_trigger_handler,
1362 &xadc_buffer_ops);
1363 if (ret)
1364 return ret;
1365
1366 if (irq > 0) {
1367 xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1368 if (IS_ERR(xadc->convst_trigger))
1369 return PTR_ERR(xadc->convst_trigger);
1370
1371 xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1372 "samplerate");
1373 if (IS_ERR(xadc->samplerate_trigger))
1374 return PTR_ERR(xadc->samplerate_trigger);
1375 }
1376 }
1377
1378 xadc->clk = devm_clk_get_enabled(dev, NULL);
1379 if (IS_ERR(xadc->clk))
1380 return PTR_ERR(xadc->clk);
1381
1382 /*
1383 * Make sure not to exceed the maximum samplerate since otherwise the
1384 * resulting interrupt storm will soft-lock the system.
1385 */
1386 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1387 ret = xadc_read_samplerate(xadc);
1388 if (ret < 0)
1389 return ret;
1390
1391 if (ret > XADC_MAX_SAMPLERATE) {
1392 ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
1393 if (ret < 0)
1394 return ret;
1395 }
1396 }
1397
1398 if (irq > 0) {
1399 ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler,
1400 0, dev_name(dev), indio_dev);
1401 if (ret)
1402 return ret;
1403
1404 ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
1405 &xadc->zynq_unmask_work);
1406 if (ret)
1407 return ret;
1408 }
1409
1410 ret = xadc->ops->setup(pdev, indio_dev, irq);
1411 if (ret)
1412 return ret;
1413
1414 for (i = 0; i < 16; i++)
1415 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1416 &xadc->threshold[i]);
1417
1418 ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1419 if (ret)
1420 return ret;
1421
1422 bipolar_mask = 0;
1423 for (i = 0; i < indio_dev->num_channels; i++) {
1424 if (indio_dev->channels[i].scan_type.sign == 's')
1425 bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1426 }
1427
1428 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1429 if (ret)
1430 return ret;
1431
1432 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1433 bipolar_mask >> 16);
1434 if (ret)
1435 return ret;
1436
1437 /* Go to non-buffered mode */
1438 xadc_postdisable(indio_dev);
1439
1440 return devm_iio_device_register(dev, indio_dev);
1441}
1442
1443static struct platform_driver xadc_driver = {
1444 .probe = xadc_probe,
1445 .driver = {
1446 .name = "xadc",
1447 .of_match_table = xadc_of_match_table,
1448 },
1449};
1450module_platform_driver(xadc_driver);
1451
1452MODULE_LICENSE("GPL v2");
1453MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1454MODULE_DESCRIPTION("Xilinx XADC IIO driver");