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1/*
2 * arch/powerpc/sysdev/uic.c
3 *
4 * IBM PowerPC 4xx Universal Interrupt Controller
5 *
6 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/device.h>
22#include <linux/bootmem.h>
23#include <linux/spinlock.h>
24#include <linux/irq.h>
25#include <linux/interrupt.h>
26#include <linux/kernel_stat.h>
27#include <asm/irq.h>
28#include <asm/io.h>
29#include <asm/prom.h>
30#include <asm/dcr.h>
31
32#define NR_UIC_INTS 32
33
34#define UIC_SR 0x0
35#define UIC_ER 0x2
36#define UIC_CR 0x3
37#define UIC_PR 0x4
38#define UIC_TR 0x5
39#define UIC_MSR 0x6
40#define UIC_VR 0x7
41#define UIC_VCR 0x8
42
43struct uic *primary_uic;
44
45struct uic {
46 int index;
47 int dcrbase;
48
49 raw_spinlock_t lock;
50
51 /* The remapper for this UIC */
52 struct irq_domain *irqhost;
53};
54
55static void uic_unmask_irq(struct irq_data *d)
56{
57 struct uic *uic = irq_data_get_irq_chip_data(d);
58 unsigned int src = irqd_to_hwirq(d);
59 unsigned long flags;
60 u32 er, sr;
61
62 sr = 1 << (31-src);
63 raw_spin_lock_irqsave(&uic->lock, flags);
64 /* ack level-triggered interrupts here */
65 if (irqd_is_level_type(d))
66 mtdcr(uic->dcrbase + UIC_SR, sr);
67 er = mfdcr(uic->dcrbase + UIC_ER);
68 er |= sr;
69 mtdcr(uic->dcrbase + UIC_ER, er);
70 raw_spin_unlock_irqrestore(&uic->lock, flags);
71}
72
73static void uic_mask_irq(struct irq_data *d)
74{
75 struct uic *uic = irq_data_get_irq_chip_data(d);
76 unsigned int src = irqd_to_hwirq(d);
77 unsigned long flags;
78 u32 er;
79
80 raw_spin_lock_irqsave(&uic->lock, flags);
81 er = mfdcr(uic->dcrbase + UIC_ER);
82 er &= ~(1 << (31 - src));
83 mtdcr(uic->dcrbase + UIC_ER, er);
84 raw_spin_unlock_irqrestore(&uic->lock, flags);
85}
86
87static void uic_ack_irq(struct irq_data *d)
88{
89 struct uic *uic = irq_data_get_irq_chip_data(d);
90 unsigned int src = irqd_to_hwirq(d);
91 unsigned long flags;
92
93 raw_spin_lock_irqsave(&uic->lock, flags);
94 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
95 raw_spin_unlock_irqrestore(&uic->lock, flags);
96}
97
98static void uic_mask_ack_irq(struct irq_data *d)
99{
100 struct uic *uic = irq_data_get_irq_chip_data(d);
101 unsigned int src = irqd_to_hwirq(d);
102 unsigned long flags;
103 u32 er, sr;
104
105 sr = 1 << (31-src);
106 raw_spin_lock_irqsave(&uic->lock, flags);
107 er = mfdcr(uic->dcrbase + UIC_ER);
108 er &= ~sr;
109 mtdcr(uic->dcrbase + UIC_ER, er);
110 /* On the UIC, acking (i.e. clearing the SR bit)
111 * a level irq will have no effect if the interrupt
112 * is still asserted by the device, even if
113 * the interrupt is already masked. Therefore
114 * we only ack the egde interrupts here, while
115 * level interrupts are ack'ed after the actual
116 * isr call in the uic_unmask_irq()
117 */
118 if (!irqd_is_level_type(d))
119 mtdcr(uic->dcrbase + UIC_SR, sr);
120 raw_spin_unlock_irqrestore(&uic->lock, flags);
121}
122
123static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
124{
125 struct uic *uic = irq_data_get_irq_chip_data(d);
126 unsigned int src = irqd_to_hwirq(d);
127 unsigned long flags;
128 int trigger, polarity;
129 u32 tr, pr, mask;
130
131 switch (flow_type & IRQ_TYPE_SENSE_MASK) {
132 case IRQ_TYPE_NONE:
133 uic_mask_irq(d);
134 return 0;
135
136 case IRQ_TYPE_EDGE_RISING:
137 trigger = 1; polarity = 1;
138 break;
139 case IRQ_TYPE_EDGE_FALLING:
140 trigger = 1; polarity = 0;
141 break;
142 case IRQ_TYPE_LEVEL_HIGH:
143 trigger = 0; polarity = 1;
144 break;
145 case IRQ_TYPE_LEVEL_LOW:
146 trigger = 0; polarity = 0;
147 break;
148 default:
149 return -EINVAL;
150 }
151
152 mask = ~(1 << (31 - src));
153
154 raw_spin_lock_irqsave(&uic->lock, flags);
155 tr = mfdcr(uic->dcrbase + UIC_TR);
156 pr = mfdcr(uic->dcrbase + UIC_PR);
157 tr = (tr & mask) | (trigger << (31-src));
158 pr = (pr & mask) | (polarity << (31-src));
159
160 mtdcr(uic->dcrbase + UIC_PR, pr);
161 mtdcr(uic->dcrbase + UIC_TR, tr);
162
163 raw_spin_unlock_irqrestore(&uic->lock, flags);
164
165 return 0;
166}
167
168static struct irq_chip uic_irq_chip = {
169 .name = "UIC",
170 .irq_unmask = uic_unmask_irq,
171 .irq_mask = uic_mask_irq,
172 .irq_mask_ack = uic_mask_ack_irq,
173 .irq_ack = uic_ack_irq,
174 .irq_set_type = uic_set_irq_type,
175};
176
177static int uic_host_map(struct irq_domain *h, unsigned int virq,
178 irq_hw_number_t hw)
179{
180 struct uic *uic = h->host_data;
181
182 irq_set_chip_data(virq, uic);
183 /* Despite the name, handle_level_irq() works for both level
184 * and edge irqs on UIC. FIXME: check this is correct */
185 irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
186
187 /* Set default irq type */
188 irq_set_irq_type(virq, IRQ_TYPE_NONE);
189
190 return 0;
191}
192
193static struct irq_domain_ops uic_host_ops = {
194 .map = uic_host_map,
195 .xlate = irq_domain_xlate_twocell,
196};
197
198void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
199{
200 struct irq_chip *chip = irq_desc_get_chip(desc);
201 struct irq_data *idata = irq_desc_get_irq_data(desc);
202 struct uic *uic = irq_get_handler_data(virq);
203 u32 msr;
204 int src;
205 int subvirq;
206
207 raw_spin_lock(&desc->lock);
208 if (irqd_is_level_type(idata))
209 chip->irq_mask(idata);
210 else
211 chip->irq_mask_ack(idata);
212 raw_spin_unlock(&desc->lock);
213
214 msr = mfdcr(uic->dcrbase + UIC_MSR);
215 if (!msr) /* spurious interrupt */
216 goto uic_irq_ret;
217
218 src = 32 - ffs(msr);
219
220 subvirq = irq_linear_revmap(uic->irqhost, src);
221 generic_handle_irq(subvirq);
222
223uic_irq_ret:
224 raw_spin_lock(&desc->lock);
225 if (irqd_is_level_type(idata))
226 chip->irq_ack(idata);
227 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
228 chip->irq_unmask(idata);
229 raw_spin_unlock(&desc->lock);
230}
231
232static struct uic * __init uic_init_one(struct device_node *node)
233{
234 struct uic *uic;
235 const u32 *indexp, *dcrreg;
236 int len;
237
238 BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
239
240 uic = kzalloc(sizeof(*uic), GFP_KERNEL);
241 if (! uic)
242 return NULL; /* FIXME: panic? */
243
244 raw_spin_lock_init(&uic->lock);
245 indexp = of_get_property(node, "cell-index", &len);
246 if (!indexp || (len != sizeof(u32))) {
247 printk(KERN_ERR "uic: Device node %s has missing or invalid "
248 "cell-index property\n", node->full_name);
249 return NULL;
250 }
251 uic->index = *indexp;
252
253 dcrreg = of_get_property(node, "dcr-reg", &len);
254 if (!dcrreg || (len != 2*sizeof(u32))) {
255 printk(KERN_ERR "uic: Device node %s has missing or invalid "
256 "dcr-reg property\n", node->full_name);
257 return NULL;
258 }
259 uic->dcrbase = *dcrreg;
260
261 uic->irqhost = irq_domain_add_linear(node, NR_UIC_INTS, &uic_host_ops,
262 uic);
263 if (! uic->irqhost)
264 return NULL; /* FIXME: panic? */
265
266 /* Start with all interrupts disabled, level and non-critical */
267 mtdcr(uic->dcrbase + UIC_ER, 0);
268 mtdcr(uic->dcrbase + UIC_CR, 0);
269 mtdcr(uic->dcrbase + UIC_TR, 0);
270 /* Clear any pending interrupts, in case the firmware left some */
271 mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
272
273 printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
274 NR_UIC_INTS, uic->dcrbase);
275
276 return uic;
277}
278
279void __init uic_init_tree(void)
280{
281 struct device_node *np;
282 struct uic *uic;
283 const u32 *interrupts;
284
285 /* First locate and initialize the top-level UIC */
286 for_each_compatible_node(np, NULL, "ibm,uic") {
287 interrupts = of_get_property(np, "interrupts", NULL);
288 if (!interrupts)
289 break;
290 }
291
292 BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
293 * top-level interrupt controller */
294 primary_uic = uic_init_one(np);
295 if (!primary_uic)
296 panic("Unable to initialize primary UIC %s\n", np->full_name);
297
298 irq_set_default_host(primary_uic->irqhost);
299 of_node_put(np);
300
301 /* The scan again for cascaded UICs */
302 for_each_compatible_node(np, NULL, "ibm,uic") {
303 interrupts = of_get_property(np, "interrupts", NULL);
304 if (interrupts) {
305 /* Secondary UIC */
306 int cascade_virq;
307
308 uic = uic_init_one(np);
309 if (! uic)
310 panic("Unable to initialize a secondary UIC %s\n",
311 np->full_name);
312
313 cascade_virq = irq_of_parse_and_map(np, 0);
314
315 irq_set_handler_data(cascade_virq, uic);
316 irq_set_chained_handler(cascade_virq, uic_irq_cascade);
317
318 /* FIXME: setup critical cascade?? */
319 }
320 }
321}
322
323/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
324unsigned int uic_get_irq(void)
325{
326 u32 msr;
327 int src;
328
329 BUG_ON(! primary_uic);
330
331 msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
332 src = 32 - ffs(msr);
333
334 return irq_linear_revmap(primary_uic->irqhost, src);
335}