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1/*
2 * arch/powerpc/sysdev/uic.c
3 *
4 * IBM PowerPC 4xx Universal Interrupt Controller
5 *
6 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/sysdev.h>
22#include <linux/device.h>
23#include <linux/bootmem.h>
24#include <linux/spinlock.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/kernel_stat.h>
28#include <asm/irq.h>
29#include <asm/io.h>
30#include <asm/prom.h>
31#include <asm/dcr.h>
32
33#define NR_UIC_INTS 32
34
35#define UIC_SR 0x0
36#define UIC_ER 0x2
37#define UIC_CR 0x3
38#define UIC_PR 0x4
39#define UIC_TR 0x5
40#define UIC_MSR 0x6
41#define UIC_VR 0x7
42#define UIC_VCR 0x8
43
44struct uic *primary_uic;
45
46struct uic {
47 int index;
48 int dcrbase;
49
50 spinlock_t lock;
51
52 /* The remapper for this UIC */
53 struct irq_host *irqhost;
54};
55
56static void uic_unmask_irq(struct irq_data *d)
57{
58 struct uic *uic = irq_data_get_irq_chip_data(d);
59 unsigned int src = irqd_to_hwirq(d);
60 unsigned long flags;
61 u32 er, sr;
62
63 sr = 1 << (31-src);
64 spin_lock_irqsave(&uic->lock, flags);
65 /* ack level-triggered interrupts here */
66 if (irqd_is_level_type(d))
67 mtdcr(uic->dcrbase + UIC_SR, sr);
68 er = mfdcr(uic->dcrbase + UIC_ER);
69 er |= sr;
70 mtdcr(uic->dcrbase + UIC_ER, er);
71 spin_unlock_irqrestore(&uic->lock, flags);
72}
73
74static void uic_mask_irq(struct irq_data *d)
75{
76 struct uic *uic = irq_data_get_irq_chip_data(d);
77 unsigned int src = irqd_to_hwirq(d);
78 unsigned long flags;
79 u32 er;
80
81 spin_lock_irqsave(&uic->lock, flags);
82 er = mfdcr(uic->dcrbase + UIC_ER);
83 er &= ~(1 << (31 - src));
84 mtdcr(uic->dcrbase + UIC_ER, er);
85 spin_unlock_irqrestore(&uic->lock, flags);
86}
87
88static void uic_ack_irq(struct irq_data *d)
89{
90 struct uic *uic = irq_data_get_irq_chip_data(d);
91 unsigned int src = irqd_to_hwirq(d);
92 unsigned long flags;
93
94 spin_lock_irqsave(&uic->lock, flags);
95 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
96 spin_unlock_irqrestore(&uic->lock, flags);
97}
98
99static void uic_mask_ack_irq(struct irq_data *d)
100{
101 struct uic *uic = irq_data_get_irq_chip_data(d);
102 unsigned int src = irqd_to_hwirq(d);
103 unsigned long flags;
104 u32 er, sr;
105
106 sr = 1 << (31-src);
107 spin_lock_irqsave(&uic->lock, flags);
108 er = mfdcr(uic->dcrbase + UIC_ER);
109 er &= ~sr;
110 mtdcr(uic->dcrbase + UIC_ER, er);
111 /* On the UIC, acking (i.e. clearing the SR bit)
112 * a level irq will have no effect if the interrupt
113 * is still asserted by the device, even if
114 * the interrupt is already masked. Therefore
115 * we only ack the egde interrupts here, while
116 * level interrupts are ack'ed after the actual
117 * isr call in the uic_unmask_irq()
118 */
119 if (!irqd_is_level_type(d))
120 mtdcr(uic->dcrbase + UIC_SR, sr);
121 spin_unlock_irqrestore(&uic->lock, flags);
122}
123
124static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
125{
126 struct uic *uic = irq_data_get_irq_chip_data(d);
127 unsigned int src = irqd_to_hwirq(d);
128 unsigned long flags;
129 int trigger, polarity;
130 u32 tr, pr, mask;
131
132 switch (flow_type & IRQ_TYPE_SENSE_MASK) {
133 case IRQ_TYPE_NONE:
134 uic_mask_irq(d);
135 return 0;
136
137 case IRQ_TYPE_EDGE_RISING:
138 trigger = 1; polarity = 1;
139 break;
140 case IRQ_TYPE_EDGE_FALLING:
141 trigger = 1; polarity = 0;
142 break;
143 case IRQ_TYPE_LEVEL_HIGH:
144 trigger = 0; polarity = 1;
145 break;
146 case IRQ_TYPE_LEVEL_LOW:
147 trigger = 0; polarity = 0;
148 break;
149 default:
150 return -EINVAL;
151 }
152
153 mask = ~(1 << (31 - src));
154
155 spin_lock_irqsave(&uic->lock, flags);
156 tr = mfdcr(uic->dcrbase + UIC_TR);
157 pr = mfdcr(uic->dcrbase + UIC_PR);
158 tr = (tr & mask) | (trigger << (31-src));
159 pr = (pr & mask) | (polarity << (31-src));
160
161 mtdcr(uic->dcrbase + UIC_PR, pr);
162 mtdcr(uic->dcrbase + UIC_TR, tr);
163
164 spin_unlock_irqrestore(&uic->lock, flags);
165
166 return 0;
167}
168
169static struct irq_chip uic_irq_chip = {
170 .name = "UIC",
171 .irq_unmask = uic_unmask_irq,
172 .irq_mask = uic_mask_irq,
173 .irq_mask_ack = uic_mask_ack_irq,
174 .irq_ack = uic_ack_irq,
175 .irq_set_type = uic_set_irq_type,
176};
177
178static int uic_host_map(struct irq_host *h, unsigned int virq,
179 irq_hw_number_t hw)
180{
181 struct uic *uic = h->host_data;
182
183 irq_set_chip_data(virq, uic);
184 /* Despite the name, handle_level_irq() works for both level
185 * and edge irqs on UIC. FIXME: check this is correct */
186 irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
187
188 /* Set default irq type */
189 irq_set_irq_type(virq, IRQ_TYPE_NONE);
190
191 return 0;
192}
193
194static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
195 const u32 *intspec, unsigned int intsize,
196 irq_hw_number_t *out_hwirq, unsigned int *out_type)
197
198{
199 /* UIC intspecs must have 2 cells */
200 BUG_ON(intsize != 2);
201 *out_hwirq = intspec[0];
202 *out_type = intspec[1];
203 return 0;
204}
205
206static struct irq_host_ops uic_host_ops = {
207 .map = uic_host_map,
208 .xlate = uic_host_xlate,
209};
210
211void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
212{
213 struct irq_chip *chip = irq_desc_get_chip(desc);
214 struct irq_data *idata = irq_desc_get_irq_data(desc);
215 struct uic *uic = irq_get_handler_data(virq);
216 u32 msr;
217 int src;
218 int subvirq;
219
220 raw_spin_lock(&desc->lock);
221 if (irqd_is_level_type(idata))
222 chip->irq_mask(idata);
223 else
224 chip->irq_mask_ack(idata);
225 raw_spin_unlock(&desc->lock);
226
227 msr = mfdcr(uic->dcrbase + UIC_MSR);
228 if (!msr) /* spurious interrupt */
229 goto uic_irq_ret;
230
231 src = 32 - ffs(msr);
232
233 subvirq = irq_linear_revmap(uic->irqhost, src);
234 generic_handle_irq(subvirq);
235
236uic_irq_ret:
237 raw_spin_lock(&desc->lock);
238 if (irqd_is_level_type(idata))
239 chip->irq_ack(idata);
240 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
241 chip->irq_unmask(idata);
242 raw_spin_unlock(&desc->lock);
243}
244
245static struct uic * __init uic_init_one(struct device_node *node)
246{
247 struct uic *uic;
248 const u32 *indexp, *dcrreg;
249 int len;
250
251 BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
252
253 uic = kzalloc(sizeof(*uic), GFP_KERNEL);
254 if (! uic)
255 return NULL; /* FIXME: panic? */
256
257 spin_lock_init(&uic->lock);
258 indexp = of_get_property(node, "cell-index", &len);
259 if (!indexp || (len != sizeof(u32))) {
260 printk(KERN_ERR "uic: Device node %s has missing or invalid "
261 "cell-index property\n", node->full_name);
262 return NULL;
263 }
264 uic->index = *indexp;
265
266 dcrreg = of_get_property(node, "dcr-reg", &len);
267 if (!dcrreg || (len != 2*sizeof(u32))) {
268 printk(KERN_ERR "uic: Device node %s has missing or invalid "
269 "dcr-reg property\n", node->full_name);
270 return NULL;
271 }
272 uic->dcrbase = *dcrreg;
273
274 uic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
275 NR_UIC_INTS, &uic_host_ops, -1);
276 if (! uic->irqhost)
277 return NULL; /* FIXME: panic? */
278
279 uic->irqhost->host_data = uic;
280
281 /* Start with all interrupts disabled, level and non-critical */
282 mtdcr(uic->dcrbase + UIC_ER, 0);
283 mtdcr(uic->dcrbase + UIC_CR, 0);
284 mtdcr(uic->dcrbase + UIC_TR, 0);
285 /* Clear any pending interrupts, in case the firmware left some */
286 mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
287
288 printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
289 NR_UIC_INTS, uic->dcrbase);
290
291 return uic;
292}
293
294void __init uic_init_tree(void)
295{
296 struct device_node *np;
297 struct uic *uic;
298 const u32 *interrupts;
299
300 /* First locate and initialize the top-level UIC */
301 for_each_compatible_node(np, NULL, "ibm,uic") {
302 interrupts = of_get_property(np, "interrupts", NULL);
303 if (!interrupts)
304 break;
305 }
306
307 BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
308 * top-level interrupt controller */
309 primary_uic = uic_init_one(np);
310 if (!primary_uic)
311 panic("Unable to initialize primary UIC %s\n", np->full_name);
312
313 irq_set_default_host(primary_uic->irqhost);
314 of_node_put(np);
315
316 /* The scan again for cascaded UICs */
317 for_each_compatible_node(np, NULL, "ibm,uic") {
318 interrupts = of_get_property(np, "interrupts", NULL);
319 if (interrupts) {
320 /* Secondary UIC */
321 int cascade_virq;
322
323 uic = uic_init_one(np);
324 if (! uic)
325 panic("Unable to initialize a secondary UIC %s\n",
326 np->full_name);
327
328 cascade_virq = irq_of_parse_and_map(np, 0);
329
330 irq_set_handler_data(cascade_virq, uic);
331 irq_set_chained_handler(cascade_virq, uic_irq_cascade);
332
333 /* FIXME: setup critical cascade?? */
334 }
335 }
336}
337
338/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
339unsigned int uic_get_irq(void)
340{
341 u32 msr;
342 int src;
343
344 BUG_ON(! primary_uic);
345
346 msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
347 src = 32 - ffs(msr);
348
349 return irq_linear_revmap(primary_uic->irqhost, src);
350}