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1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * OHCI HCD (Host Controller Driver) for USB.
4 *
5 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 *
8 * [ Initialisation is based on Linus' ]
9 * [ uhci code and gregs ohci fragments ]
10 * [ (C) Copyright 1999 Linus Torvalds ]
11 * [ (C) Copyright 1999 Gregory P. Smith]
12 *
13 * PCI Bus Glue
14 *
15 * This file is licenced under the GPL.
16 */
17
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/usb.h>
23#include <linux/usb/hcd.h>
24
25#include "ohci.h"
26#include "pci-quirks.h"
27
28#define DRIVER_DESC "OHCI PCI platform driver"
29
30static const char hcd_name[] = "ohci-pci";
31
32
33/*-------------------------------------------------------------------------*/
34
35static int broken_suspend(struct usb_hcd *hcd)
36{
37 device_init_wakeup(&hcd->self.root_hub->dev, 0);
38 return 0;
39}
40
41/* AMD 756, for most chips (early revs), corrupts register
42 * values on read ... so enable the vendor workaround.
43 */
44static int ohci_quirk_amd756(struct usb_hcd *hcd)
45{
46 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
47
48 ohci->flags = OHCI_QUIRK_AMD756;
49 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
50
51 /* also erratum 10 (suspend/resume issues) */
52 return broken_suspend(hcd);
53}
54
55/* Apple's OHCI driver has a lot of bizarre workarounds
56 * for this chip. Evidently control and bulk lists
57 * can get confused. (B&W G3 models, and ...)
58 */
59static int ohci_quirk_opti(struct usb_hcd *hcd)
60{
61 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
62
63 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
64
65 return 0;
66}
67
68/* Check for NSC87560. We have to look at the bridge (fn1) to
69 * identify the USB (fn2). This quirk might apply to more or
70 * even all NSC stuff.
71 */
72static int ohci_quirk_ns(struct usb_hcd *hcd)
73{
74 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
75 struct pci_dev *b;
76
77 b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
78 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
79 && b->vendor == PCI_VENDOR_ID_NS) {
80 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
81
82 ohci->flags |= OHCI_QUIRK_SUPERIO;
83 ohci_dbg (ohci, "Using NSC SuperIO setup\n");
84 }
85 pci_dev_put(b);
86
87 return 0;
88}
89
90/* Check for Compaq's ZFMicro chipset, which needs short
91 * delays before control or bulk queues get re-activated
92 * in finish_unlinks()
93 */
94static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
95{
96 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
97
98 ohci->flags |= OHCI_QUIRK_ZFMICRO;
99 ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
100
101 return 0;
102}
103
104/* Check for Toshiba SCC OHCI which has big endian registers
105 * and little endian in memory data structures
106 */
107static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
108{
109 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
110
111 /* That chip is only present in the southbridge of some
112 * cell based platforms which are supposed to select
113 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
114 * that was the case though.
115 */
116#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
117 ohci->flags |= OHCI_QUIRK_BE_MMIO;
118 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
119 return 0;
120#else
121 ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
122 return -ENXIO;
123#endif
124}
125
126/* Check for NEC chip and apply quirk for allegedly lost interrupts.
127 */
128
129static void ohci_quirk_nec_worker(struct work_struct *work)
130{
131 struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
132 int status;
133
134 status = ohci_restart(ohci);
135 if (status != 0)
136 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
137 "ohci_restart", status);
138}
139
140static int ohci_quirk_nec(struct usb_hcd *hcd)
141{
142 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
143
144 ohci->flags |= OHCI_QUIRK_NEC;
145 INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
146 ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
147
148 return 0;
149}
150
151static int ohci_quirk_amd700(struct usb_hcd *hcd)
152{
153 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
154
155 if (usb_amd_quirk_pll_check())
156 ohci->flags |= OHCI_QUIRK_AMD_PLL;
157
158 /* SB800 needs pre-fetch fix */
159 if (usb_amd_prefetch_quirk()) {
160 ohci->flags |= OHCI_QUIRK_AMD_PREFETCH;
161 ohci_dbg(ohci, "enabled AMD prefetch quirk\n");
162 }
163
164 ohci->flags |= OHCI_QUIRK_GLOBAL_SUSPEND;
165 return 0;
166}
167
168static int ohci_quirk_qemu(struct usb_hcd *hcd)
169{
170 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
171
172 ohci->flags |= OHCI_QUIRK_QEMU;
173 ohci_dbg(ohci, "enabled qemu quirk\n");
174 return 0;
175}
176
177/* List of quirks for OHCI */
178static const struct pci_device_id ohci_pci_quirks[] = {
179 {
180 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
181 .driver_data = (unsigned long)ohci_quirk_amd756,
182 },
183 {
184 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
185 .driver_data = (unsigned long)ohci_quirk_opti,
186 },
187 {
188 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
189 .driver_data = (unsigned long)ohci_quirk_ns,
190 },
191 {
192 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
193 .driver_data = (unsigned long)ohci_quirk_zfmicro,
194 },
195 {
196 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
197 .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
198 },
199 {
200 PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
201 .driver_data = (unsigned long)ohci_quirk_nec,
202 },
203 {
204 /* Toshiba portege 4000 */
205 .vendor = PCI_VENDOR_ID_AL,
206 .device = 0x5237,
207 .subvendor = PCI_VENDOR_ID_TOSHIBA,
208 .subdevice = 0x0004,
209 .driver_data = (unsigned long) broken_suspend,
210 },
211 {
212 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
213 .driver_data = (unsigned long) broken_suspend,
214 },
215 {
216 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397),
217 .driver_data = (unsigned long)ohci_quirk_amd700,
218 },
219 {
220 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398),
221 .driver_data = (unsigned long)ohci_quirk_amd700,
222 },
223 {
224 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399),
225 .driver_data = (unsigned long)ohci_quirk_amd700,
226 },
227 {
228 .vendor = PCI_VENDOR_ID_APPLE,
229 .device = 0x003f,
230 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,
231 .subdevice = PCI_SUBDEVICE_ID_QEMU,
232 .driver_data = (unsigned long)ohci_quirk_qemu,
233 },
234
235 {},
236};
237
238static int ohci_pci_reset (struct usb_hcd *hcd)
239{
240 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
241 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
242 int ret = 0;
243
244 if (hcd->self.controller) {
245 const struct pci_device_id *quirk_id;
246
247 quirk_id = pci_match_id(ohci_pci_quirks, pdev);
248 if (quirk_id != NULL) {
249 int (*quirk)(struct usb_hcd *ohci);
250 quirk = (void *)quirk_id->driver_data;
251 ret = quirk(hcd);
252 }
253 }
254
255 if (ret == 0)
256 ret = ohci_setup(hcd);
257 /*
258 * After ohci setup RWC may not be set for add-in PCI cards.
259 * This transfers PCI PM wakeup capabilities.
260 */
261 if (device_can_wakeup(&pdev->dev))
262 ohci->hc_control |= OHCI_CTRL_RWC;
263 return ret;
264}
265
266static struct hc_driver __read_mostly ohci_pci_hc_driver;
267
268static const struct ohci_driver_overrides pci_overrides __initconst = {
269 .product_desc = "OHCI PCI host controller",
270 .reset = ohci_pci_reset,
271};
272
273static const struct pci_device_id pci_ids[] = { {
274 /* handle any USB OHCI controller */
275 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
276 }, {
277 /* The device in the ConneXT I/O hub has no class reg */
278 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_OHCI),
279 }, { /* end: all zeroes */ }
280};
281MODULE_DEVICE_TABLE (pci, pci_ids);
282
283static int ohci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
284{
285 return usb_hcd_pci_probe(dev, &ohci_pci_hc_driver);
286}
287
288/* pci driver glue; this is a "new style" PCI driver module */
289static struct pci_driver ohci_pci_driver = {
290 .name = hcd_name,
291 .id_table = pci_ids,
292
293 .probe = ohci_pci_probe,
294 .remove = usb_hcd_pci_remove,
295 .shutdown = usb_hcd_pci_shutdown,
296
297#ifdef CONFIG_PM
298 .driver = {
299 .pm = &usb_hcd_pci_pm_ops
300 },
301#endif
302};
303
304#ifdef CONFIG_PM
305static int ohci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
306{
307 return ohci_resume(hcd, msg.event == PM_EVENT_RESTORE);
308}
309#endif
310static int __init ohci_pci_init(void)
311{
312 if (usb_disabled())
313 return -ENODEV;
314
315 ohci_init_driver(&ohci_pci_hc_driver, &pci_overrides);
316
317#ifdef CONFIG_PM
318 /* Entries for the PCI suspend/resume callbacks are special */
319 ohci_pci_hc_driver.pci_suspend = ohci_suspend;
320 ohci_pci_hc_driver.pci_resume = ohci_pci_resume;
321#endif
322
323 return pci_register_driver(&ohci_pci_driver);
324}
325module_init(ohci_pci_init);
326
327static void __exit ohci_pci_cleanup(void)
328{
329 pci_unregister_driver(&ohci_pci_driver);
330}
331module_exit(ohci_pci_cleanup);
332
333MODULE_DESCRIPTION(DRIVER_DESC);
334MODULE_LICENSE("GPL");
335MODULE_SOFTDEP("pre: ehci_pci");
1/*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 * PCI Bus Glue
13 *
14 * This file is licenced under the GPL.
15 */
16
17#ifndef CONFIG_PCI
18#error "This file is PCI bus glue. CONFIG_PCI must be defined."
19#endif
20
21#include <linux/pci.h>
22#include <linux/io.h>
23
24
25/*-------------------------------------------------------------------------*/
26
27static int broken_suspend(struct usb_hcd *hcd)
28{
29 device_init_wakeup(&hcd->self.root_hub->dev, 0);
30 return 0;
31}
32
33/* AMD 756, for most chips (early revs), corrupts register
34 * values on read ... so enable the vendor workaround.
35 */
36static int ohci_quirk_amd756(struct usb_hcd *hcd)
37{
38 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
39
40 ohci->flags = OHCI_QUIRK_AMD756;
41 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
42
43 /* also erratum 10 (suspend/resume issues) */
44 return broken_suspend(hcd);
45}
46
47/* Apple's OHCI driver has a lot of bizarre workarounds
48 * for this chip. Evidently control and bulk lists
49 * can get confused. (B&W G3 models, and ...)
50 */
51static int ohci_quirk_opti(struct usb_hcd *hcd)
52{
53 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
54
55 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
56
57 return 0;
58}
59
60/* Check for NSC87560. We have to look at the bridge (fn1) to
61 * identify the USB (fn2). This quirk might apply to more or
62 * even all NSC stuff.
63 */
64static int ohci_quirk_ns(struct usb_hcd *hcd)
65{
66 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
67 struct pci_dev *b;
68
69 b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
70 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
71 && b->vendor == PCI_VENDOR_ID_NS) {
72 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
73
74 ohci->flags |= OHCI_QUIRK_SUPERIO;
75 ohci_dbg (ohci, "Using NSC SuperIO setup\n");
76 }
77 pci_dev_put(b);
78
79 return 0;
80}
81
82/* Check for Compaq's ZFMicro chipset, which needs short
83 * delays before control or bulk queues get re-activated
84 * in finish_unlinks()
85 */
86static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
87{
88 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
89
90 ohci->flags |= OHCI_QUIRK_ZFMICRO;
91 ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
92
93 return 0;
94}
95
96/* Check for Toshiba SCC OHCI which has big endian registers
97 * and little endian in memory data structures
98 */
99static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
100{
101 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
102
103 /* That chip is only present in the southbridge of some
104 * cell based platforms which are supposed to select
105 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
106 * that was the case though.
107 */
108#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
109 ohci->flags |= OHCI_QUIRK_BE_MMIO;
110 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
111 return 0;
112#else
113 ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
114 return -ENXIO;
115#endif
116}
117
118/* Check for NEC chip and apply quirk for allegedly lost interrupts.
119 */
120
121static void ohci_quirk_nec_worker(struct work_struct *work)
122{
123 struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
124 int status;
125
126 status = ohci_init(ohci);
127 if (status != 0) {
128 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
129 "ohci_init", status);
130 return;
131 }
132
133 status = ohci_restart(ohci);
134 if (status != 0)
135 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
136 "ohci_restart", status);
137}
138
139static int ohci_quirk_nec(struct usb_hcd *hcd)
140{
141 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
142
143 ohci->flags |= OHCI_QUIRK_NEC;
144 INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
145 ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
146
147 return 0;
148}
149
150static int ohci_quirk_amd700(struct usb_hcd *hcd)
151{
152 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
153 struct pci_dev *amd_smbus_dev;
154 u8 rev;
155
156 if (usb_amd_find_chipset_info())
157 ohci->flags |= OHCI_QUIRK_AMD_PLL;
158
159 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
160 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
161 if (!amd_smbus_dev)
162 return 0;
163
164 rev = amd_smbus_dev->revision;
165
166 /* SB800 needs pre-fetch fix */
167 if ((rev >= 0x40) && (rev <= 0x4f)) {
168 ohci->flags |= OHCI_QUIRK_AMD_PREFETCH;
169 ohci_dbg(ohci, "enabled AMD prefetch quirk\n");
170 }
171
172 pci_dev_put(amd_smbus_dev);
173 amd_smbus_dev = NULL;
174
175 return 0;
176}
177
178static void sb800_prefetch(struct ohci_hcd *ohci, int on)
179{
180 struct pci_dev *pdev;
181 u16 misc;
182
183 pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
184 pci_read_config_word(pdev, 0x50, &misc);
185 if (on == 0)
186 pci_write_config_word(pdev, 0x50, misc & 0xfcff);
187 else
188 pci_write_config_word(pdev, 0x50, misc | 0x0300);
189}
190
191/* List of quirks for OHCI */
192static const struct pci_device_id ohci_pci_quirks[] = {
193 {
194 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
195 .driver_data = (unsigned long)ohci_quirk_amd756,
196 },
197 {
198 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
199 .driver_data = (unsigned long)ohci_quirk_opti,
200 },
201 {
202 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
203 .driver_data = (unsigned long)ohci_quirk_ns,
204 },
205 {
206 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
207 .driver_data = (unsigned long)ohci_quirk_zfmicro,
208 },
209 {
210 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
211 .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
212 },
213 {
214 PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
215 .driver_data = (unsigned long)ohci_quirk_nec,
216 },
217 {
218 /* Toshiba portege 4000 */
219 .vendor = PCI_VENDOR_ID_AL,
220 .device = 0x5237,
221 .subvendor = PCI_VENDOR_ID_TOSHIBA,
222 .subdevice = 0x0004,
223 .driver_data = (unsigned long) broken_suspend,
224 },
225 {
226 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
227 .driver_data = (unsigned long) broken_suspend,
228 },
229 {
230 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397),
231 .driver_data = (unsigned long)ohci_quirk_amd700,
232 },
233 {
234 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398),
235 .driver_data = (unsigned long)ohci_quirk_amd700,
236 },
237 {
238 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399),
239 .driver_data = (unsigned long)ohci_quirk_amd700,
240 },
241
242 /* FIXME for some of the early AMD 760 southbridges, OHCI
243 * won't work at all. blacklist them.
244 */
245
246 {},
247};
248
249static int ohci_pci_reset (struct usb_hcd *hcd)
250{
251 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
252 int ret = 0;
253
254 if (hcd->self.controller) {
255 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
256 const struct pci_device_id *quirk_id;
257
258 quirk_id = pci_match_id(ohci_pci_quirks, pdev);
259 if (quirk_id != NULL) {
260 int (*quirk)(struct usb_hcd *ohci);
261 quirk = (void *)quirk_id->driver_data;
262 ret = quirk(hcd);
263 }
264 }
265 if (ret == 0) {
266 ohci_hcd_init (ohci);
267 return ohci_init (ohci);
268 }
269 return ret;
270}
271
272
273static int __devinit ohci_pci_start (struct usb_hcd *hcd)
274{
275 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
276 int ret;
277
278#ifdef CONFIG_PM /* avoid warnings about unused pdev */
279 if (hcd->self.controller) {
280 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
281
282 /* RWC may not be set for add-in PCI cards, since boot
283 * firmware probably ignored them. This transfers PCI
284 * PM wakeup capabilities.
285 */
286 if (device_can_wakeup(&pdev->dev))
287 ohci->hc_control |= OHCI_CTRL_RWC;
288 }
289#endif /* CONFIG_PM */
290
291 ret = ohci_run (ohci);
292 if (ret < 0) {
293 ohci_err (ohci, "can't start\n");
294 ohci_stop (hcd);
295 }
296 return ret;
297}
298
299#ifdef CONFIG_PM
300
301static int ohci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
302{
303 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
304 unsigned long flags;
305 int rc = 0;
306
307 /* Root hub was already suspended. Disable irq emission and
308 * mark HW unaccessible, bail out if RH has been resumed. Use
309 * the spinlock to properly synchronize with possible pending
310 * RH suspend or resume activity.
311 */
312 spin_lock_irqsave (&ohci->lock, flags);
313 if (ohci->rh_state != OHCI_RH_SUSPENDED) {
314 rc = -EINVAL;
315 goto bail;
316 }
317 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
318 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
319
320 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
321 bail:
322 spin_unlock_irqrestore (&ohci->lock, flags);
323
324 return rc;
325}
326
327
328static int ohci_pci_resume(struct usb_hcd *hcd, bool hibernated)
329{
330 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
331
332 /* Make sure resume from hibernation re-enumerates everything */
333 if (hibernated)
334 ohci_usb_reset(hcd_to_ohci(hcd));
335
336 ohci_finish_controller_resume(hcd);
337 return 0;
338}
339
340#endif /* CONFIG_PM */
341
342
343/*-------------------------------------------------------------------------*/
344
345static const struct hc_driver ohci_pci_hc_driver = {
346 .description = hcd_name,
347 .product_desc = "OHCI Host Controller",
348 .hcd_priv_size = sizeof(struct ohci_hcd),
349
350 /*
351 * generic hardware linkage
352 */
353 .irq = ohci_irq,
354 .flags = HCD_MEMORY | HCD_USB11,
355
356 /*
357 * basic lifecycle operations
358 */
359 .reset = ohci_pci_reset,
360 .start = ohci_pci_start,
361 .stop = ohci_stop,
362 .shutdown = ohci_shutdown,
363
364#ifdef CONFIG_PM
365 .pci_suspend = ohci_pci_suspend,
366 .pci_resume = ohci_pci_resume,
367#endif
368
369 /*
370 * managing i/o requests and associated device resources
371 */
372 .urb_enqueue = ohci_urb_enqueue,
373 .urb_dequeue = ohci_urb_dequeue,
374 .endpoint_disable = ohci_endpoint_disable,
375
376 /*
377 * scheduling support
378 */
379 .get_frame_number = ohci_get_frame,
380
381 /*
382 * root hub support
383 */
384 .hub_status_data = ohci_hub_status_data,
385 .hub_control = ohci_hub_control,
386#ifdef CONFIG_PM
387 .bus_suspend = ohci_bus_suspend,
388 .bus_resume = ohci_bus_resume,
389#endif
390 .start_port_reset = ohci_start_port_reset,
391};
392
393/*-------------------------------------------------------------------------*/
394
395
396static const struct pci_device_id pci_ids [] = { {
397 /* handle any USB OHCI controller */
398 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
399 .driver_data = (unsigned long) &ohci_pci_hc_driver,
400 }, {
401 /* The device in the ConneXT I/O hub has no class reg */
402 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_OHCI),
403 .driver_data = (unsigned long) &ohci_pci_hc_driver,
404 }, { /* end: all zeroes */ }
405};
406MODULE_DEVICE_TABLE (pci, pci_ids);
407
408/* pci driver glue; this is a "new style" PCI driver module */
409static struct pci_driver ohci_pci_driver = {
410 .name = (char *) hcd_name,
411 .id_table = pci_ids,
412
413 .probe = usb_hcd_pci_probe,
414 .remove = usb_hcd_pci_remove,
415 .shutdown = usb_hcd_pci_shutdown,
416
417#ifdef CONFIG_PM_SLEEP
418 .driver = {
419 .pm = &usb_hcd_pci_pm_ops
420 },
421#endif
422};