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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/device.h>
27#include <linux/dmi.h>
28#include <linux/gfp.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_cmnd.h>
31#include <linux/libata.h>
32#include <linux/ahci-remap.h>
33#include <linux/io-64-nonatomic-lo-hi.h>
34#include "ahci.h"
35
36#define DRV_NAME "ahci"
37#define DRV_VERSION "3.0"
38
39enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46};
47
48enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_low_power,
54 board_ahci_no_debounce_delay,
55 board_ahci_nomsi,
56 board_ahci_noncq,
57 board_ahci_nosntf,
58 board_ahci_yes_fbs,
59
60 /* board IDs for specific chipsets in alphabetical order */
61 board_ahci_al,
62 board_ahci_avn,
63 board_ahci_mcp65,
64 board_ahci_mcp77,
65 board_ahci_mcp89,
66 board_ahci_mv,
67 board_ahci_sb600,
68 board_ahci_sb700, /* for SB700 and SB800 */
69 board_ahci_vt8251,
70
71 /*
72 * board IDs for Intel chipsets that support more than 6 ports
73 * *and* end up needing the PCS quirk.
74 */
75 board_ahci_pcs7,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82};
83
84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85static void ahci_remove_one(struct pci_dev *dev);
86static void ahci_shutdown_one(struct pci_dev *dev);
87static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
88static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93static bool is_mcp89_apple(struct pci_dev *pdev);
94static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96#ifdef CONFIG_PM
97static int ahci_pci_device_runtime_suspend(struct device *dev);
98static int ahci_pci_device_runtime_resume(struct device *dev);
99#ifdef CONFIG_PM_SLEEP
100static int ahci_pci_device_suspend(struct device *dev);
101static int ahci_pci_device_resume(struct device *dev);
102#endif
103#endif /* CONFIG_PM */
104
105static const struct scsi_host_template ahci_sht = {
106 AHCI_SHT("ahci"),
107};
108
109static struct ata_port_operations ahci_vt8251_ops = {
110 .inherits = &ahci_ops,
111 .hardreset = ahci_vt8251_hardreset,
112};
113
114static struct ata_port_operations ahci_p5wdh_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_p5wdh_hardreset,
117};
118
119static struct ata_port_operations ahci_avn_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_avn_hardreset,
122};
123
124static const struct ata_port_info ahci_port_info[] = {
125 /* by features */
126 [board_ahci] = {
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_43bit_dma] = {
133 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 [board_ahci_ign_iferr] = {
140 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
145 },
146 [board_ahci_low_power] = {
147 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 [board_ahci_no_debounce_delay] = {
154 .flags = AHCI_FLAG_COMMON,
155 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
159 },
160 [board_ahci_nomsi] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_noncq] = {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_nosntf] = {
175 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
176 .flags = AHCI_FLAG_COMMON,
177 .pio_mask = ATA_PIO4,
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &ahci_ops,
180 },
181 [board_ahci_yes_fbs] = {
182 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
183 .flags = AHCI_FLAG_COMMON,
184 .pio_mask = ATA_PIO4,
185 .udma_mask = ATA_UDMA6,
186 .port_ops = &ahci_ops,
187 },
188 /* by chipsets */
189 [board_ahci_al] = {
190 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
191 .flags = AHCI_FLAG_COMMON,
192 .pio_mask = ATA_PIO4,
193 .udma_mask = ATA_UDMA6,
194 .port_ops = &ahci_ops,
195 },
196 [board_ahci_avn] = {
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_avn_ops,
201 },
202 [board_ahci_mcp65] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
204 AHCI_HFLAG_YES_NCQ),
205 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_ops,
209 },
210 [board_ahci_mcp77] = {
211 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_ops,
216 },
217 [board_ahci_mcp89] = {
218 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
223 },
224 [board_ahci_mv] = {
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
226 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
227 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_ops,
231 },
232 [board_ahci_sb600] = {
233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
234 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
235 AHCI_HFLAG_32BIT_ONLY),
236 .flags = AHCI_FLAG_COMMON,
237 .pio_mask = ATA_PIO4,
238 .udma_mask = ATA_UDMA6,
239 .port_ops = &ahci_pmp_retry_srst_ops,
240 },
241 [board_ahci_sb700] = { /* for SB700 and SB800 */
242 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
243 .flags = AHCI_FLAG_COMMON,
244 .pio_mask = ATA_PIO4,
245 .udma_mask = ATA_UDMA6,
246 .port_ops = &ahci_pmp_retry_srst_ops,
247 },
248 [board_ahci_vt8251] = {
249 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
250 .flags = AHCI_FLAG_COMMON,
251 .pio_mask = ATA_PIO4,
252 .udma_mask = ATA_UDMA6,
253 .port_ops = &ahci_vt8251_ops,
254 },
255 [board_ahci_pcs7] = {
256 .flags = AHCI_FLAG_COMMON,
257 .pio_mask = ATA_PIO4,
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &ahci_ops,
260 },
261};
262
263static const struct pci_device_id ahci_pci_tbl[] = {
264 /* Intel */
265 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
266 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
267 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
268 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
269 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
270 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
271 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
272 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
273 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
274 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
275 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
276 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
277 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
278 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
279 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
280 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
281 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
285 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
286 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
287 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
288 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
289 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
290 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
291 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
292 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
293 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
294 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
295 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
296 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
297 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
298 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
299 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
300 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
301 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
302 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
303 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
304 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
305 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
306 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
327 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
328 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
329 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
330 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
331 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
332 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
333 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
334 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
335 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
336 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
337 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
338 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
339 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
340 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
341 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
342 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
343 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
344 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
345 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
346 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
347 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
348 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
349 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
351 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
352 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
353 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
354 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
355 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
369 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
370 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
375 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
376 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
377 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
378 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
379 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
380 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
381 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
382 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
383 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
384 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
385 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
386 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
387 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
388 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
389 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
390 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
391 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
392 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
393 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
394 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
395 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
396 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
397 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
398 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
399 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
400 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
401 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
402 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
403 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
404 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
405 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
406 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
407 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
408 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
409 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
410 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
413 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
414 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
415 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
416 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
417 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
419 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
420 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
421 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
422 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
423 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
424 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
425 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
426 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
427 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
428 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
429 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
430 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
431 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
432 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
433 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
434 { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_low_power }, /* Alder Lake-P AHCI */
435
436 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
437 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
438 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
439 /* JMicron 362B and 362C have an AHCI function with IDE class code */
440 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
441 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
442 /* May need to update quirk_jmicron_async_suspend() for additions */
443
444 /* ATI */
445 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
446 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
449 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
450 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
451 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
452
453 /* Amazon's Annapurna Labs support */
454 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
455 .class = PCI_CLASS_STORAGE_SATA_AHCI,
456 .class_mask = 0xffffff,
457 board_ahci_al },
458 /* AMD */
459 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
460 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
461 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
462 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
463 /* AMD is using RAID class only for ahci controllers */
464 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
465 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
466
467 /* Dell S140/S150 */
468 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
469 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
470
471 /* VIA */
472 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
473 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
474
475 /* NVIDIA */
476 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
480 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
484 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
496 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
512 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
559 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
560
561 /* SiS */
562 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
563 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
564 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
565
566 /* ST Microelectronics */
567 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
568
569 /* Marvell */
570 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
571 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
572 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
573 .class = PCI_CLASS_STORAGE_SATA_AHCI,
574 .class_mask = 0xffffff,
575 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
576 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
577 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
578 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
579 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
580 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
581 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
582 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
583 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
584 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
585 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
586 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
587 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
588 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
589 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
590 .driver_data = board_ahci_yes_fbs },
591 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
592 .driver_data = board_ahci_yes_fbs },
593 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
594 .driver_data = board_ahci_yes_fbs },
595 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
596 .driver_data = board_ahci_yes_fbs },
597 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
598 .driver_data = board_ahci_no_debounce_delay },
599 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
600 .driver_data = board_ahci_yes_fbs },
601 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
602 .driver_data = board_ahci_yes_fbs },
603
604 /* Promise */
605 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
606 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
607
608 /* ASMedia */
609 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
610 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */
611 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
612 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
613 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
614 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */
615 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
616 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
617 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
618 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
619 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
620 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
621
622 /*
623 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
624 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
625 */
626 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
627 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
628
629 /* Enmotus */
630 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
631
632 /* Loongson */
633 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
634
635 /* Generic, PCI class code for AHCI */
636 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
637 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
638
639 { } /* terminate list */
640};
641
642static const struct dev_pm_ops ahci_pci_pm_ops = {
643 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
644 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
645 ahci_pci_device_runtime_resume, NULL)
646};
647
648static struct pci_driver ahci_pci_driver = {
649 .name = DRV_NAME,
650 .id_table = ahci_pci_tbl,
651 .probe = ahci_init_one,
652 .remove = ahci_remove_one,
653 .shutdown = ahci_shutdown_one,
654 .driver = {
655 .pm = &ahci_pci_pm_ops,
656 },
657};
658
659#if IS_ENABLED(CONFIG_PATA_MARVELL)
660static int marvell_enable;
661#else
662static int marvell_enable = 1;
663#endif
664module_param(marvell_enable, int, 0644);
665MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
666
667static int mobile_lpm_policy = -1;
668module_param(mobile_lpm_policy, int, 0644);
669MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
670
671static void ahci_pci_save_initial_config(struct pci_dev *pdev,
672 struct ahci_host_priv *hpriv)
673{
674 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA) {
675 switch (pdev->device) {
676 case 0x1166:
677 dev_info(&pdev->dev, "ASM1166 has only six ports\n");
678 hpriv->saved_port_map = 0x3f;
679 break;
680 case 0x1064:
681 dev_info(&pdev->dev, "ASM1064 has only four ports\n");
682 hpriv->saved_port_map = 0xf;
683 break;
684 }
685 }
686
687 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
688 dev_info(&pdev->dev, "JMB361 has only one port\n");
689 hpriv->saved_port_map = 1;
690 }
691
692 /*
693 * Temporary Marvell 6145 hack: PATA port presence
694 * is asserted through the standard AHCI port
695 * presence register, as bit 4 (counting from 0)
696 */
697 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
698 if (pdev->device == 0x6121)
699 hpriv->mask_port_map = 0x3;
700 else
701 hpriv->mask_port_map = 0xf;
702 dev_info(&pdev->dev,
703 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
704 }
705
706 ahci_save_initial_config(&pdev->dev, hpriv);
707}
708
709static int ahci_pci_reset_controller(struct ata_host *host)
710{
711 struct pci_dev *pdev = to_pci_dev(host->dev);
712 struct ahci_host_priv *hpriv = host->private_data;
713 int rc;
714
715 rc = ahci_reset_controller(host);
716 if (rc)
717 return rc;
718
719 /*
720 * If platform firmware failed to enable ports, try to enable
721 * them here.
722 */
723 ahci_intel_pcs_quirk(pdev, hpriv);
724
725 return 0;
726}
727
728static void ahci_pci_init_controller(struct ata_host *host)
729{
730 struct ahci_host_priv *hpriv = host->private_data;
731 struct pci_dev *pdev = to_pci_dev(host->dev);
732 void __iomem *port_mmio;
733 u32 tmp;
734 int mv;
735
736 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
737 if (pdev->device == 0x6121)
738 mv = 2;
739 else
740 mv = 4;
741 port_mmio = __ahci_port_base(hpriv, mv);
742
743 writel(0, port_mmio + PORT_IRQ_MASK);
744
745 /* clear port IRQ */
746 tmp = readl(port_mmio + PORT_IRQ_STAT);
747 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
748 if (tmp)
749 writel(tmp, port_mmio + PORT_IRQ_STAT);
750 }
751
752 ahci_init_controller(host);
753}
754
755static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
756 unsigned long deadline)
757{
758 struct ata_port *ap = link->ap;
759 struct ahci_host_priv *hpriv = ap->host->private_data;
760 bool online;
761 int rc;
762
763 hpriv->stop_engine(ap);
764
765 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
766 deadline, &online, NULL);
767
768 hpriv->start_engine(ap);
769
770 /* vt8251 doesn't clear BSY on signature FIS reception,
771 * request follow-up softreset.
772 */
773 return online ? -EAGAIN : rc;
774}
775
776static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
777 unsigned long deadline)
778{
779 struct ata_port *ap = link->ap;
780 struct ahci_port_priv *pp = ap->private_data;
781 struct ahci_host_priv *hpriv = ap->host->private_data;
782 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
783 struct ata_taskfile tf;
784 bool online;
785 int rc;
786
787 hpriv->stop_engine(ap);
788
789 /* clear D2H reception area to properly wait for D2H FIS */
790 ata_tf_init(link->device, &tf);
791 tf.status = ATA_BUSY;
792 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
793
794 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
795 deadline, &online, NULL);
796
797 hpriv->start_engine(ap);
798
799 /* The pseudo configuration device on SIMG4726 attached to
800 * ASUS P5W-DH Deluxe doesn't send signature FIS after
801 * hardreset if no device is attached to the first downstream
802 * port && the pseudo device locks up on SRST w/ PMP==0. To
803 * work around this, wait for !BSY only briefly. If BSY isn't
804 * cleared, perform CLO and proceed to IDENTIFY (achieved by
805 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
806 *
807 * Wait for two seconds. Devices attached to downstream port
808 * which can't process the following IDENTIFY after this will
809 * have to be reset again. For most cases, this should
810 * suffice while making probing snappish enough.
811 */
812 if (online) {
813 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
814 ahci_check_ready);
815 if (rc)
816 ahci_kick_engine(ap);
817 }
818 return rc;
819}
820
821/*
822 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
823 *
824 * It has been observed with some SSDs that the timing of events in the
825 * link synchronization phase can leave the port in a state that can not
826 * be recovered by a SATA-hard-reset alone. The failing signature is
827 * SStatus.DET stuck at 1 ("Device presence detected but Phy
828 * communication not established"). It was found that unloading and
829 * reloading the driver when this problem occurs allows the drive
830 * connection to be recovered (DET advanced to 0x3). The critical
831 * component of reloading the driver is that the port state machines are
832 * reset by bouncing "port enable" in the AHCI PCS configuration
833 * register. So, reproduce that effect by bouncing a port whenever we
834 * see DET==1 after a reset.
835 */
836static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
837 unsigned long deadline)
838{
839 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
840 struct ata_port *ap = link->ap;
841 struct ahci_port_priv *pp = ap->private_data;
842 struct ahci_host_priv *hpriv = ap->host->private_data;
843 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
844 unsigned long tmo = deadline - jiffies;
845 struct ata_taskfile tf;
846 bool online;
847 int rc, i;
848
849 hpriv->stop_engine(ap);
850
851 for (i = 0; i < 2; i++) {
852 u16 val;
853 u32 sstatus;
854 int port = ap->port_no;
855 struct ata_host *host = ap->host;
856 struct pci_dev *pdev = to_pci_dev(host->dev);
857
858 /* clear D2H reception area to properly wait for D2H FIS */
859 ata_tf_init(link->device, &tf);
860 tf.status = ATA_BUSY;
861 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
862
863 rc = sata_link_hardreset(link, timing, deadline, &online,
864 ahci_check_ready);
865
866 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
867 (sstatus & 0xf) != 1)
868 break;
869
870 ata_link_info(link, "avn bounce port%d\n", port);
871
872 pci_read_config_word(pdev, 0x92, &val);
873 val &= ~(1 << port);
874 pci_write_config_word(pdev, 0x92, val);
875 ata_msleep(ap, 1000);
876 val |= 1 << port;
877 pci_write_config_word(pdev, 0x92, val);
878 deadline += tmo;
879 }
880
881 hpriv->start_engine(ap);
882
883 if (online)
884 *class = ahci_dev_classify(ap);
885
886 return rc;
887}
888
889
890#ifdef CONFIG_PM
891static void ahci_pci_disable_interrupts(struct ata_host *host)
892{
893 struct ahci_host_priv *hpriv = host->private_data;
894 void __iomem *mmio = hpriv->mmio;
895 u32 ctl;
896
897 /* AHCI spec rev1.1 section 8.3.3:
898 * Software must disable interrupts prior to requesting a
899 * transition of the HBA to D3 state.
900 */
901 ctl = readl(mmio + HOST_CTL);
902 ctl &= ~HOST_IRQ_EN;
903 writel(ctl, mmio + HOST_CTL);
904 readl(mmio + HOST_CTL); /* flush */
905}
906
907static int ahci_pci_device_runtime_suspend(struct device *dev)
908{
909 struct pci_dev *pdev = to_pci_dev(dev);
910 struct ata_host *host = pci_get_drvdata(pdev);
911
912 ahci_pci_disable_interrupts(host);
913 return 0;
914}
915
916static int ahci_pci_device_runtime_resume(struct device *dev)
917{
918 struct pci_dev *pdev = to_pci_dev(dev);
919 struct ata_host *host = pci_get_drvdata(pdev);
920 int rc;
921
922 rc = ahci_pci_reset_controller(host);
923 if (rc)
924 return rc;
925 ahci_pci_init_controller(host);
926 return 0;
927}
928
929#ifdef CONFIG_PM_SLEEP
930static int ahci_pci_device_suspend(struct device *dev)
931{
932 struct pci_dev *pdev = to_pci_dev(dev);
933 struct ata_host *host = pci_get_drvdata(pdev);
934 struct ahci_host_priv *hpriv = host->private_data;
935
936 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
937 dev_err(&pdev->dev,
938 "BIOS update required for suspend/resume\n");
939 return -EIO;
940 }
941
942 ahci_pci_disable_interrupts(host);
943 ata_host_suspend(host, PMSG_SUSPEND);
944 return 0;
945}
946
947static int ahci_pci_device_resume(struct device *dev)
948{
949 struct pci_dev *pdev = to_pci_dev(dev);
950 struct ata_host *host = pci_get_drvdata(pdev);
951 int rc;
952
953 /* Apple BIOS helpfully mangles the registers on resume */
954 if (is_mcp89_apple(pdev))
955 ahci_mcp89_apple_enable(pdev);
956
957 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
958 rc = ahci_pci_reset_controller(host);
959 if (rc)
960 return rc;
961
962 ahci_pci_init_controller(host);
963 }
964
965 ata_host_resume(host);
966
967 return 0;
968}
969#endif
970
971#endif /* CONFIG_PM */
972
973static int ahci_configure_dma_masks(struct pci_dev *pdev,
974 struct ahci_host_priv *hpriv)
975{
976 int dma_bits;
977 int rc;
978
979 if (hpriv->cap & HOST_CAP_64) {
980 dma_bits = 64;
981 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
982 dma_bits = 43;
983 } else {
984 dma_bits = 32;
985 }
986
987 /*
988 * If the device fixup already set the dma_mask to some non-standard
989 * value, don't extend it here. This happens on STA2X11, for example.
990 *
991 * XXX: manipulating the DMA mask from platform code is completely
992 * bogus, platform code should use dev->bus_dma_limit instead..
993 */
994 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
995 return 0;
996
997 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
998 if (rc)
999 dev_err(&pdev->dev, "DMA enable failed\n");
1000 return rc;
1001}
1002
1003static void ahci_pci_print_info(struct ata_host *host)
1004{
1005 struct pci_dev *pdev = to_pci_dev(host->dev);
1006 u16 cc;
1007 const char *scc_s;
1008
1009 pci_read_config_word(pdev, 0x0a, &cc);
1010 if (cc == PCI_CLASS_STORAGE_IDE)
1011 scc_s = "IDE";
1012 else if (cc == PCI_CLASS_STORAGE_SATA)
1013 scc_s = "SATA";
1014 else if (cc == PCI_CLASS_STORAGE_RAID)
1015 scc_s = "RAID";
1016 else
1017 scc_s = "unknown";
1018
1019 ahci_print_info(host, scc_s);
1020}
1021
1022/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1023 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1024 * support PMP and the 4726 either directly exports the device
1025 * attached to the first downstream port or acts as a hardware storage
1026 * controller and emulate a single ATA device (can be RAID 0/1 or some
1027 * other configuration).
1028 *
1029 * When there's no device attached to the first downstream port of the
1030 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1031 * configure the 4726. However, ATA emulation of the device is very
1032 * lame. It doesn't send signature D2H Reg FIS after the initial
1033 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1034 *
1035 * The following function works around the problem by always using
1036 * hardreset on the port and not depending on receiving signature FIS
1037 * afterward. If signature FIS isn't received soon, ATA class is
1038 * assumed without follow-up softreset.
1039 */
1040static void ahci_p5wdh_workaround(struct ata_host *host)
1041{
1042 static const struct dmi_system_id sysids[] = {
1043 {
1044 .ident = "P5W DH Deluxe",
1045 .matches = {
1046 DMI_MATCH(DMI_SYS_VENDOR,
1047 "ASUSTEK COMPUTER INC"),
1048 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1049 },
1050 },
1051 { }
1052 };
1053 struct pci_dev *pdev = to_pci_dev(host->dev);
1054
1055 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1056 dmi_check_system(sysids)) {
1057 struct ata_port *ap = host->ports[1];
1058
1059 dev_info(&pdev->dev,
1060 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1061
1062 ap->ops = &ahci_p5wdh_ops;
1063 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1064 }
1065}
1066
1067/*
1068 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1069 * booting in BIOS compatibility mode. We restore the registers but not ID.
1070 */
1071static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1072{
1073 u32 val;
1074
1075 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1076
1077 pci_read_config_dword(pdev, 0xf8, &val);
1078 val |= 1 << 0x1b;
1079 /* the following changes the device ID, but appears not to affect function */
1080 /* val = (val & ~0xf0000000) | 0x80000000; */
1081 pci_write_config_dword(pdev, 0xf8, val);
1082
1083 pci_read_config_dword(pdev, 0x54c, &val);
1084 val |= 1 << 0xc;
1085 pci_write_config_dword(pdev, 0x54c, val);
1086
1087 pci_read_config_dword(pdev, 0x4a4, &val);
1088 val &= 0xff;
1089 val |= 0x01060100;
1090 pci_write_config_dword(pdev, 0x4a4, val);
1091
1092 pci_read_config_dword(pdev, 0x54c, &val);
1093 val &= ~(1 << 0xc);
1094 pci_write_config_dword(pdev, 0x54c, val);
1095
1096 pci_read_config_dword(pdev, 0xf8, &val);
1097 val &= ~(1 << 0x1b);
1098 pci_write_config_dword(pdev, 0xf8, val);
1099}
1100
1101static bool is_mcp89_apple(struct pci_dev *pdev)
1102{
1103 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1104 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1105 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1106 pdev->subsystem_device == 0xcb89;
1107}
1108
1109/* only some SB600 ahci controllers can do 64bit DMA */
1110static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1111{
1112 static const struct dmi_system_id sysids[] = {
1113 /*
1114 * The oldest version known to be broken is 0901 and
1115 * working is 1501 which was released on 2007-10-26.
1116 * Enable 64bit DMA on 1501 and anything newer.
1117 *
1118 * Please read bko#9412 for more info.
1119 */
1120 {
1121 .ident = "ASUS M2A-VM",
1122 .matches = {
1123 DMI_MATCH(DMI_BOARD_VENDOR,
1124 "ASUSTeK Computer INC."),
1125 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1126 },
1127 .driver_data = "20071026", /* yyyymmdd */
1128 },
1129 /*
1130 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1131 * support 64bit DMA.
1132 *
1133 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1134 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1135 * This spelling mistake was fixed in BIOS version 1.5, so
1136 * 1.5 and later have the Manufacturer as
1137 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1138 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1139 *
1140 * BIOS versions earlier than 1.9 had a Board Product Name
1141 * DMI field of "MS-7376". This was changed to be
1142 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1143 * match on DMI_BOARD_NAME of "MS-7376".
1144 */
1145 {
1146 .ident = "MSI K9A2 Platinum",
1147 .matches = {
1148 DMI_MATCH(DMI_BOARD_VENDOR,
1149 "MICRO-STAR INTER"),
1150 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1151 },
1152 },
1153 /*
1154 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1155 * 64bit DMA.
1156 *
1157 * This board also had the typo mentioned above in the
1158 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1159 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1160 */
1161 {
1162 .ident = "MSI K9AGM2",
1163 .matches = {
1164 DMI_MATCH(DMI_BOARD_VENDOR,
1165 "MICRO-STAR INTER"),
1166 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1167 },
1168 },
1169 /*
1170 * All BIOS versions for the Asus M3A support 64bit DMA.
1171 * (all release versions from 0301 to 1206 were tested)
1172 */
1173 {
1174 .ident = "ASUS M3A",
1175 .matches = {
1176 DMI_MATCH(DMI_BOARD_VENDOR,
1177 "ASUSTeK Computer INC."),
1178 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1179 },
1180 },
1181 { }
1182 };
1183 const struct dmi_system_id *match;
1184 int year, month, date;
1185 char buf[9];
1186
1187 match = dmi_first_match(sysids);
1188 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1189 !match)
1190 return false;
1191
1192 if (!match->driver_data)
1193 goto enable_64bit;
1194
1195 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1196 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1197
1198 if (strcmp(buf, match->driver_data) >= 0)
1199 goto enable_64bit;
1200 else {
1201 dev_warn(&pdev->dev,
1202 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1203 match->ident);
1204 return false;
1205 }
1206
1207enable_64bit:
1208 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1209 return true;
1210}
1211
1212static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1213{
1214 static const struct dmi_system_id broken_systems[] = {
1215 {
1216 .ident = "HP Compaq nx6310",
1217 .matches = {
1218 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1219 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1220 },
1221 /* PCI slot number of the controller */
1222 .driver_data = (void *)0x1FUL,
1223 },
1224 {
1225 .ident = "HP Compaq 6720s",
1226 .matches = {
1227 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1228 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1229 },
1230 /* PCI slot number of the controller */
1231 .driver_data = (void *)0x1FUL,
1232 },
1233
1234 { } /* terminate list */
1235 };
1236 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1237
1238 if (dmi) {
1239 unsigned long slot = (unsigned long)dmi->driver_data;
1240 /* apply the quirk only to on-board controllers */
1241 return slot == PCI_SLOT(pdev->devfn);
1242 }
1243
1244 return false;
1245}
1246
1247static bool ahci_broken_suspend(struct pci_dev *pdev)
1248{
1249 static const struct dmi_system_id sysids[] = {
1250 /*
1251 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1252 * to the harddisk doesn't become online after
1253 * resuming from STR. Warn and fail suspend.
1254 *
1255 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1256 *
1257 * Use dates instead of versions to match as HP is
1258 * apparently recycling both product and version
1259 * strings.
1260 *
1261 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1262 */
1263 {
1264 .ident = "dv4",
1265 .matches = {
1266 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1267 DMI_MATCH(DMI_PRODUCT_NAME,
1268 "HP Pavilion dv4 Notebook PC"),
1269 },
1270 .driver_data = "20090105", /* F.30 */
1271 },
1272 {
1273 .ident = "dv5",
1274 .matches = {
1275 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1276 DMI_MATCH(DMI_PRODUCT_NAME,
1277 "HP Pavilion dv5 Notebook PC"),
1278 },
1279 .driver_data = "20090506", /* F.16 */
1280 },
1281 {
1282 .ident = "dv6",
1283 .matches = {
1284 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1285 DMI_MATCH(DMI_PRODUCT_NAME,
1286 "HP Pavilion dv6 Notebook PC"),
1287 },
1288 .driver_data = "20090423", /* F.21 */
1289 },
1290 {
1291 .ident = "HDX18",
1292 .matches = {
1293 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1294 DMI_MATCH(DMI_PRODUCT_NAME,
1295 "HP HDX18 Notebook PC"),
1296 },
1297 .driver_data = "20090430", /* F.23 */
1298 },
1299 /*
1300 * Acer eMachines G725 has the same problem. BIOS
1301 * V1.03 is known to be broken. V3.04 is known to
1302 * work. Between, there are V1.06, V2.06 and V3.03
1303 * that we don't have much idea about. For now,
1304 * blacklist anything older than V3.04.
1305 *
1306 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1307 */
1308 {
1309 .ident = "G725",
1310 .matches = {
1311 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1312 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1313 },
1314 .driver_data = "20091216", /* V3.04 */
1315 },
1316 { } /* terminate list */
1317 };
1318 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1319 int year, month, date;
1320 char buf[9];
1321
1322 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1323 return false;
1324
1325 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1326 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1327
1328 return strcmp(buf, dmi->driver_data) < 0;
1329}
1330
1331static bool ahci_broken_lpm(struct pci_dev *pdev)
1332{
1333 static const struct dmi_system_id sysids[] = {
1334 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1335 {
1336 .matches = {
1337 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1338 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1339 },
1340 .driver_data = "20180406", /* 1.31 */
1341 },
1342 {
1343 .matches = {
1344 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1345 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1346 },
1347 .driver_data = "20180420", /* 1.28 */
1348 },
1349 {
1350 .matches = {
1351 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1352 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1353 },
1354 .driver_data = "20180315", /* 1.33 */
1355 },
1356 {
1357 .matches = {
1358 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1359 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1360 },
1361 /*
1362 * Note date based on release notes, 2.35 has been
1363 * reported to be good, but I've been unable to get
1364 * a hold of the reporter to get the DMI BIOS date.
1365 * TODO: fix this.
1366 */
1367 .driver_data = "20180310", /* 2.35 */
1368 },
1369 { } /* terminate list */
1370 };
1371 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1372 int year, month, date;
1373 char buf[9];
1374
1375 if (!dmi)
1376 return false;
1377
1378 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1379 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1380
1381 return strcmp(buf, dmi->driver_data) < 0;
1382}
1383
1384static bool ahci_broken_online(struct pci_dev *pdev)
1385{
1386#define ENCODE_BUSDEVFN(bus, slot, func) \
1387 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1388 static const struct dmi_system_id sysids[] = {
1389 /*
1390 * There are several gigabyte boards which use
1391 * SIMG5723s configured as hardware RAID. Certain
1392 * 5723 firmware revisions shipped there keep the link
1393 * online but fail to answer properly to SRST or
1394 * IDENTIFY when no device is attached downstream
1395 * causing libata to retry quite a few times leading
1396 * to excessive detection delay.
1397 *
1398 * As these firmwares respond to the second reset try
1399 * with invalid device signature, considering unknown
1400 * sig as offline works around the problem acceptably.
1401 */
1402 {
1403 .ident = "EP45-DQ6",
1404 .matches = {
1405 DMI_MATCH(DMI_BOARD_VENDOR,
1406 "Gigabyte Technology Co., Ltd."),
1407 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1408 },
1409 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1410 },
1411 {
1412 .ident = "EP45-DS5",
1413 .matches = {
1414 DMI_MATCH(DMI_BOARD_VENDOR,
1415 "Gigabyte Technology Co., Ltd."),
1416 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1417 },
1418 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1419 },
1420 { } /* terminate list */
1421 };
1422#undef ENCODE_BUSDEVFN
1423 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1424 unsigned int val;
1425
1426 if (!dmi)
1427 return false;
1428
1429 val = (unsigned long)dmi->driver_data;
1430
1431 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1432}
1433
1434static bool ahci_broken_devslp(struct pci_dev *pdev)
1435{
1436 /* device with broken DEVSLP but still showing SDS capability */
1437 static const struct pci_device_id ids[] = {
1438 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1439 {}
1440 };
1441
1442 return pci_match_id(ids, pdev);
1443}
1444
1445#ifdef CONFIG_ATA_ACPI
1446static void ahci_gtf_filter_workaround(struct ata_host *host)
1447{
1448 static const struct dmi_system_id sysids[] = {
1449 /*
1450 * Aspire 3810T issues a bunch of SATA enable commands
1451 * via _GTF including an invalid one and one which is
1452 * rejected by the device. Among the successful ones
1453 * is FPDMA non-zero offset enable which when enabled
1454 * only on the drive side leads to NCQ command
1455 * failures. Filter it out.
1456 */
1457 {
1458 .ident = "Aspire 3810T",
1459 .matches = {
1460 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1461 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1462 },
1463 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1464 },
1465 { }
1466 };
1467 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1468 unsigned int filter;
1469 int i;
1470
1471 if (!dmi)
1472 return;
1473
1474 filter = (unsigned long)dmi->driver_data;
1475 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1476 filter, dmi->ident);
1477
1478 for (i = 0; i < host->n_ports; i++) {
1479 struct ata_port *ap = host->ports[i];
1480 struct ata_link *link;
1481 struct ata_device *dev;
1482
1483 ata_for_each_link(link, ap, EDGE)
1484 ata_for_each_dev(dev, link, ALL)
1485 dev->gtf_filter |= filter;
1486 }
1487}
1488#else
1489static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1490{}
1491#endif
1492
1493/*
1494 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1495 * as DUMMY, or detected but eventually get a "link down" and never get up
1496 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1497 * port_map may hold a value of 0x00.
1498 *
1499 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1500 * and can significantly reduce the occurrence of the problem.
1501 *
1502 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1503 */
1504static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1505 struct pci_dev *pdev)
1506{
1507 static const struct dmi_system_id sysids[] = {
1508 {
1509 .ident = "Acer Switch Alpha 12",
1510 .matches = {
1511 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1512 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1513 },
1514 },
1515 { }
1516 };
1517
1518 if (dmi_check_system(sysids)) {
1519 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1520 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1521 hpriv->port_map = 0x7;
1522 hpriv->cap = 0xC734FF02;
1523 }
1524 }
1525}
1526
1527#ifdef CONFIG_ARM64
1528/*
1529 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1530 * Workaround is to make sure all pending IRQs are served before leaving
1531 * handler.
1532 */
1533static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1534{
1535 struct ata_host *host = dev_instance;
1536 struct ahci_host_priv *hpriv;
1537 unsigned int rc = 0;
1538 void __iomem *mmio;
1539 u32 irq_stat, irq_masked;
1540 unsigned int handled = 1;
1541
1542 hpriv = host->private_data;
1543 mmio = hpriv->mmio;
1544 irq_stat = readl(mmio + HOST_IRQ_STAT);
1545 if (!irq_stat)
1546 return IRQ_NONE;
1547
1548 do {
1549 irq_masked = irq_stat & hpriv->port_map;
1550 spin_lock(&host->lock);
1551 rc = ahci_handle_port_intr(host, irq_masked);
1552 if (!rc)
1553 handled = 0;
1554 writel(irq_stat, mmio + HOST_IRQ_STAT);
1555 irq_stat = readl(mmio + HOST_IRQ_STAT);
1556 spin_unlock(&host->lock);
1557 } while (irq_stat);
1558
1559 return IRQ_RETVAL(handled);
1560}
1561#endif
1562
1563static void ahci_remap_check(struct pci_dev *pdev, int bar,
1564 struct ahci_host_priv *hpriv)
1565{
1566 int i;
1567 u32 cap;
1568
1569 /*
1570 * Check if this device might have remapped nvme devices.
1571 */
1572 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1573 pci_resource_len(pdev, bar) < SZ_512K ||
1574 bar != AHCI_PCI_BAR_STANDARD ||
1575 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1576 return;
1577
1578 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1579 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1580 if ((cap & (1 << i)) == 0)
1581 continue;
1582 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1583 != PCI_CLASS_STORAGE_EXPRESS)
1584 continue;
1585
1586 /* We've found a remapped device */
1587 hpriv->remapped_nvme++;
1588 }
1589
1590 if (!hpriv->remapped_nvme)
1591 return;
1592
1593 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1594 hpriv->remapped_nvme);
1595 dev_warn(&pdev->dev,
1596 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1597
1598 /*
1599 * Don't rely on the msi-x capability in the remap case,
1600 * share the legacy interrupt across ahci and remapped devices.
1601 */
1602 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1603}
1604
1605static int ahci_get_irq_vector(struct ata_host *host, int port)
1606{
1607 return pci_irq_vector(to_pci_dev(host->dev), port);
1608}
1609
1610static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1611 struct ahci_host_priv *hpriv)
1612{
1613 int nvec;
1614
1615 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1616 return -ENODEV;
1617
1618 /*
1619 * If number of MSIs is less than number of ports then Sharing Last
1620 * Message mode could be enforced. In this case assume that advantage
1621 * of multipe MSIs is negated and use single MSI mode instead.
1622 */
1623 if (n_ports > 1) {
1624 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1625 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1626 if (nvec > 0) {
1627 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1628 hpriv->get_irq_vector = ahci_get_irq_vector;
1629 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1630 return nvec;
1631 }
1632
1633 /*
1634 * Fallback to single MSI mode if the controller
1635 * enforced MRSM mode.
1636 */
1637 printk(KERN_INFO
1638 "ahci: MRSM is on, fallback to single MSI\n");
1639 pci_free_irq_vectors(pdev);
1640 }
1641 }
1642
1643 /*
1644 * If the host is not capable of supporting per-port vectors, fall
1645 * back to single MSI before finally attempting single MSI-X.
1646 */
1647 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1648 if (nvec == 1)
1649 return nvec;
1650 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1651}
1652
1653static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1654 struct ahci_host_priv *hpriv)
1655{
1656 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1657
1658
1659 /* Ignore processing for chipsets that don't use policy */
1660 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1661 return;
1662
1663 /* user modified policy via module param */
1664 if (mobile_lpm_policy != -1) {
1665 policy = mobile_lpm_policy;
1666 goto update_policy;
1667 }
1668
1669 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1670 if (hpriv->cap & HOST_CAP_PART)
1671 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1672 else if (hpriv->cap & HOST_CAP_SSC)
1673 policy = ATA_LPM_MIN_POWER;
1674 }
1675
1676update_policy:
1677 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1678 ap->target_lpm_policy = policy;
1679}
1680
1681static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1682{
1683 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1684 u16 tmp16;
1685
1686 /*
1687 * Only apply the 6-port PCS quirk for known legacy platforms.
1688 */
1689 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1690 return;
1691
1692 /* Skip applying the quirk on Denverton and beyond */
1693 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1694 return;
1695
1696 /*
1697 * port_map is determined from PORTS_IMPL PCI register which is
1698 * implemented as write or write-once register. If the register
1699 * isn't programmed, ahci automatically generates it from number
1700 * of ports, which is good enough for PCS programming. It is
1701 * otherwise expected that platform firmware enables the ports
1702 * before the OS boots.
1703 */
1704 pci_read_config_word(pdev, PCS_6, &tmp16);
1705 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1706 tmp16 |= hpriv->port_map;
1707 pci_write_config_word(pdev, PCS_6, tmp16);
1708 }
1709}
1710
1711static ssize_t remapped_nvme_show(struct device *dev,
1712 struct device_attribute *attr,
1713 char *buf)
1714{
1715 struct ata_host *host = dev_get_drvdata(dev);
1716 struct ahci_host_priv *hpriv = host->private_data;
1717
1718 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1719}
1720
1721static DEVICE_ATTR_RO(remapped_nvme);
1722
1723static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1724{
1725 unsigned int board_id = ent->driver_data;
1726 struct ata_port_info pi = ahci_port_info[board_id];
1727 const struct ata_port_info *ppi[] = { &pi, NULL };
1728 struct device *dev = &pdev->dev;
1729 struct ahci_host_priv *hpriv;
1730 struct ata_host *host;
1731 int n_ports, i, rc;
1732 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1733
1734 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1735
1736 ata_print_version_once(&pdev->dev, DRV_VERSION);
1737
1738 /* The AHCI driver can only drive the SATA ports, the PATA driver
1739 can drive them all so if both drivers are selected make sure
1740 AHCI stays out of the way */
1741 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1742 return -ENODEV;
1743
1744 /* Apple BIOS on MCP89 prevents us using AHCI */
1745 if (is_mcp89_apple(pdev))
1746 ahci_mcp89_apple_enable(pdev);
1747
1748 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1749 * At the moment, we can only use the AHCI mode. Let the users know
1750 * that for SAS drives they're out of luck.
1751 */
1752 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1753 dev_info(&pdev->dev,
1754 "PDC42819 can only drive SATA devices with this driver\n");
1755
1756 /* Some devices use non-standard BARs */
1757 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1758 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1759 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1760 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1761 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1762 if (pdev->device == 0xa01c)
1763 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1764 if (pdev->device == 0xa084)
1765 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1766 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1767 if (pdev->device == 0x7a08)
1768 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1769 }
1770
1771 /* acquire resources */
1772 rc = pcim_enable_device(pdev);
1773 if (rc)
1774 return rc;
1775
1776 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1777 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1778 u8 map;
1779
1780 /* ICH6s share the same PCI ID for both piix and ahci
1781 * modes. Enabling ahci mode while MAP indicates
1782 * combined mode is a bad idea. Yield to ata_piix.
1783 */
1784 pci_read_config_byte(pdev, ICH_MAP, &map);
1785 if (map & 0x3) {
1786 dev_info(&pdev->dev,
1787 "controller is in combined mode, can't enable AHCI mode\n");
1788 return -ENODEV;
1789 }
1790 }
1791
1792 /* AHCI controllers often implement SFF compatible interface.
1793 * Grab all PCI BARs just in case.
1794 */
1795 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1796 if (rc == -EBUSY)
1797 pcim_pin_device(pdev);
1798 if (rc)
1799 return rc;
1800
1801 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1802 if (!hpriv)
1803 return -ENOMEM;
1804 hpriv->flags |= (unsigned long)pi.private_data;
1805
1806 /* MCP65 revision A1 and A2 can't do MSI */
1807 if (board_id == board_ahci_mcp65 &&
1808 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1809 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1810
1811 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1812 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1813 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1814
1815 /* only some SB600s can do 64bit DMA */
1816 if (ahci_sb600_enable_64bit(pdev))
1817 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1818
1819 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1820
1821 /* detect remapped nvme devices */
1822 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1823
1824 sysfs_add_file_to_group(&pdev->dev.kobj,
1825 &dev_attr_remapped_nvme.attr,
1826 NULL);
1827
1828 /* must set flag prior to save config in order to take effect */
1829 if (ahci_broken_devslp(pdev))
1830 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1831
1832#ifdef CONFIG_ARM64
1833 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1834 pdev->device == 0xa235 &&
1835 pdev->revision < 0x30)
1836 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1837
1838 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1839 hpriv->irq_handler = ahci_thunderx_irq_handler;
1840#endif
1841
1842 /* save initial config */
1843 ahci_pci_save_initial_config(pdev, hpriv);
1844
1845 /* prepare host */
1846 if (hpriv->cap & HOST_CAP_NCQ) {
1847 pi.flags |= ATA_FLAG_NCQ;
1848 /*
1849 * Auto-activate optimization is supposed to be
1850 * supported on all AHCI controllers indicating NCQ
1851 * capability, but it seems to be broken on some
1852 * chipsets including NVIDIAs.
1853 */
1854 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1855 pi.flags |= ATA_FLAG_FPDMA_AA;
1856
1857 /*
1858 * All AHCI controllers should be forward-compatible
1859 * with the new auxiliary field. This code should be
1860 * conditionalized if any buggy AHCI controllers are
1861 * encountered.
1862 */
1863 pi.flags |= ATA_FLAG_FPDMA_AUX;
1864 }
1865
1866 if (hpriv->cap & HOST_CAP_PMP)
1867 pi.flags |= ATA_FLAG_PMP;
1868
1869 ahci_set_em_messages(hpriv, &pi);
1870
1871 if (ahci_broken_system_poweroff(pdev)) {
1872 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1873 dev_info(&pdev->dev,
1874 "quirky BIOS, skipping spindown on poweroff\n");
1875 }
1876
1877 if (ahci_broken_lpm(pdev)) {
1878 pi.flags |= ATA_FLAG_NO_LPM;
1879 dev_warn(&pdev->dev,
1880 "BIOS update required for Link Power Management support\n");
1881 }
1882
1883 if (ahci_broken_suspend(pdev)) {
1884 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1885 dev_warn(&pdev->dev,
1886 "BIOS update required for suspend/resume\n");
1887 }
1888
1889 if (ahci_broken_online(pdev)) {
1890 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1891 dev_info(&pdev->dev,
1892 "online status unreliable, applying workaround\n");
1893 }
1894
1895
1896 /* Acer SA5-271 workaround modifies private_data */
1897 acer_sa5_271_workaround(hpriv, pdev);
1898
1899 /* CAP.NP sometimes indicate the index of the last enabled
1900 * port, at other times, that of the last possible port, so
1901 * determining the maximum port number requires looking at
1902 * both CAP.NP and port_map.
1903 */
1904 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1905
1906 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1907 if (!host)
1908 return -ENOMEM;
1909 host->private_data = hpriv;
1910
1911 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1912 /* legacy intx interrupts */
1913 pci_intx(pdev, 1);
1914 }
1915 hpriv->irq = pci_irq_vector(pdev, 0);
1916
1917 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1918 host->flags |= ATA_HOST_PARALLEL_SCAN;
1919 else
1920 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1921
1922 if (!(hpriv->cap & HOST_CAP_PART))
1923 host->flags |= ATA_HOST_NO_PART;
1924
1925 if (!(hpriv->cap & HOST_CAP_SSC))
1926 host->flags |= ATA_HOST_NO_SSC;
1927
1928 if (!(hpriv->cap2 & HOST_CAP2_SDS))
1929 host->flags |= ATA_HOST_NO_DEVSLP;
1930
1931 if (pi.flags & ATA_FLAG_EM)
1932 ahci_reset_em(host);
1933
1934 for (i = 0; i < host->n_ports; i++) {
1935 struct ata_port *ap = host->ports[i];
1936
1937 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1938 ata_port_pbar_desc(ap, ahci_pci_bar,
1939 0x100 + ap->port_no * 0x80, "port");
1940
1941 /* set enclosure management message type */
1942 if (ap->flags & ATA_FLAG_EM)
1943 ap->em_message_type = hpriv->em_msg_type;
1944
1945 ahci_update_initial_lpm_policy(ap, hpriv);
1946
1947 /* disabled/not-implemented port */
1948 if (!(hpriv->port_map & (1 << i)))
1949 ap->ops = &ata_dummy_port_ops;
1950 }
1951
1952 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1953 ahci_p5wdh_workaround(host);
1954
1955 /* apply gtf filter quirk */
1956 ahci_gtf_filter_workaround(host);
1957
1958 /* initialize adapter */
1959 rc = ahci_configure_dma_masks(pdev, hpriv);
1960 if (rc)
1961 return rc;
1962
1963 rc = ahci_pci_reset_controller(host);
1964 if (rc)
1965 return rc;
1966
1967 ahci_pci_init_controller(host);
1968 ahci_pci_print_info(host);
1969
1970 pci_set_master(pdev);
1971
1972 rc = ahci_host_activate(host, &ahci_sht);
1973 if (rc)
1974 return rc;
1975
1976 pm_runtime_put_noidle(&pdev->dev);
1977 return 0;
1978}
1979
1980static void ahci_shutdown_one(struct pci_dev *pdev)
1981{
1982 ata_pci_shutdown_one(pdev);
1983}
1984
1985static void ahci_remove_one(struct pci_dev *pdev)
1986{
1987 sysfs_remove_file_from_group(&pdev->dev.kobj,
1988 &dev_attr_remapped_nvme.attr,
1989 NULL);
1990 pm_runtime_get_noresume(&pdev->dev);
1991 ata_pci_remove_one(pdev);
1992}
1993
1994module_pci_driver(ahci_pci_driver);
1995
1996MODULE_AUTHOR("Jeff Garzik");
1997MODULE_DESCRIPTION("AHCI SATA low-level driver");
1998MODULE_LICENSE("GPL");
1999MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2000MODULE_VERSION(DRV_VERSION);
1/*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <linux/dmi.h>
45#include <linux/gfp.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h>
49#include "ahci.h"
50
51#define DRV_NAME "ahci"
52#define DRV_VERSION "3.0"
53
54enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
64 board_ahci_yes_fbs,
65
66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
68 board_ahci_mcp77,
69 board_ahci_mcp89,
70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
79 board_ahci_mcp79 = board_ahci_mcp77,
80};
81
82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87#ifdef CONFIG_PM
88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
90#endif
91
92static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
96static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
98 .hardreset = ahci_vt8251_hardreset,
99};
100
101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
103 .hardreset = ahci_p5wdh_hardreset,
104};
105
106static const struct ata_port_info ahci_port_info[] = {
107 /* by features */
108 [board_ahci] =
109 {
110 .flags = AHCI_FLAG_COMMON,
111 .pio_mask = ATA_PIO4,
112 .udma_mask = ATA_UDMA6,
113 .port_ops = &ahci_ops,
114 },
115 [board_ahci_ign_iferr] =
116 {
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
122 },
123 [board_ahci_nosntf] =
124 {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_yes_fbs] =
132 {
133 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 /* by chipsets */
140 [board_ahci_mcp65] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
143 AHCI_HFLAG_YES_NCQ),
144 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_mcp77] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
157 [board_ahci_mcp89] =
158 {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_mv] =
166 {
167 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
168 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
169 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_sb600] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_pmp_retry_srst_ops,
183 },
184 [board_ahci_sb700] = /* for SB700 and SB800 */
185 {
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
191 },
192 [board_ahci_vt8251] =
193 {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_vt8251_ops,
199 },
200};
201
202static const struct pci_device_id ahci_pci_tbl[] = {
203 /* Intel */
204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
270
271 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
272 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
273 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
274
275 /* ATI */
276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
283
284 /* AMD */
285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
290 /* VIA */
291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
293
294 /* NVIDIA */
295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
379
380 /* SiS */
381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
384
385 /* ST Microelectronics */
386 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
387
388 /* Marvell */
389 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
390 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
391 { PCI_DEVICE(0x1b4b, 0x9123),
392 .class = PCI_CLASS_STORAGE_SATA_AHCI,
393 .class_mask = 0xffffff,
394 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
395 { PCI_DEVICE(0x1b4b, 0x9125),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
397 { PCI_DEVICE(0x1b4b, 0x917a),
398 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
399 { PCI_DEVICE(0x1b4b, 0x9192),
400 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
401 { PCI_DEVICE(0x1b4b, 0x91a3),
402 .driver_data = board_ahci_yes_fbs },
403
404 /* Promise */
405 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
406
407 /* Asmedia */
408 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
409
410 /* Generic, PCI class code for AHCI */
411 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
412 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
413
414 { } /* terminate list */
415};
416
417
418static struct pci_driver ahci_pci_driver = {
419 .name = DRV_NAME,
420 .id_table = ahci_pci_tbl,
421 .probe = ahci_init_one,
422 .remove = ata_pci_remove_one,
423#ifdef CONFIG_PM
424 .suspend = ahci_pci_device_suspend,
425 .resume = ahci_pci_device_resume,
426#endif
427};
428
429#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
430static int marvell_enable;
431#else
432static int marvell_enable = 1;
433#endif
434module_param(marvell_enable, int, 0644);
435MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
436
437
438static void ahci_pci_save_initial_config(struct pci_dev *pdev,
439 struct ahci_host_priv *hpriv)
440{
441 unsigned int force_port_map = 0;
442 unsigned int mask_port_map = 0;
443
444 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
445 dev_info(&pdev->dev, "JMB361 has only one port\n");
446 force_port_map = 1;
447 }
448
449 /*
450 * Temporary Marvell 6145 hack: PATA port presence
451 * is asserted through the standard AHCI port
452 * presence register, as bit 4 (counting from 0)
453 */
454 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
455 if (pdev->device == 0x6121)
456 mask_port_map = 0x3;
457 else
458 mask_port_map = 0xf;
459 dev_info(&pdev->dev,
460 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
461 }
462
463 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
464 mask_port_map);
465}
466
467static int ahci_pci_reset_controller(struct ata_host *host)
468{
469 struct pci_dev *pdev = to_pci_dev(host->dev);
470
471 ahci_reset_controller(host);
472
473 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
474 struct ahci_host_priv *hpriv = host->private_data;
475 u16 tmp16;
476
477 /* configure PCS */
478 pci_read_config_word(pdev, 0x92, &tmp16);
479 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
480 tmp16 |= hpriv->port_map;
481 pci_write_config_word(pdev, 0x92, tmp16);
482 }
483 }
484
485 return 0;
486}
487
488static void ahci_pci_init_controller(struct ata_host *host)
489{
490 struct ahci_host_priv *hpriv = host->private_data;
491 struct pci_dev *pdev = to_pci_dev(host->dev);
492 void __iomem *port_mmio;
493 u32 tmp;
494 int mv;
495
496 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
497 if (pdev->device == 0x6121)
498 mv = 2;
499 else
500 mv = 4;
501 port_mmio = __ahci_port_base(host, mv);
502
503 writel(0, port_mmio + PORT_IRQ_MASK);
504
505 /* clear port IRQ */
506 tmp = readl(port_mmio + PORT_IRQ_STAT);
507 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
508 if (tmp)
509 writel(tmp, port_mmio + PORT_IRQ_STAT);
510 }
511
512 ahci_init_controller(host);
513}
514
515static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
516 unsigned long deadline)
517{
518 struct ata_port *ap = link->ap;
519 bool online;
520 int rc;
521
522 DPRINTK("ENTER\n");
523
524 ahci_stop_engine(ap);
525
526 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
527 deadline, &online, NULL);
528
529 ahci_start_engine(ap);
530
531 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
532
533 /* vt8251 doesn't clear BSY on signature FIS reception,
534 * request follow-up softreset.
535 */
536 return online ? -EAGAIN : rc;
537}
538
539static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
540 unsigned long deadline)
541{
542 struct ata_port *ap = link->ap;
543 struct ahci_port_priv *pp = ap->private_data;
544 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
545 struct ata_taskfile tf;
546 bool online;
547 int rc;
548
549 ahci_stop_engine(ap);
550
551 /* clear D2H reception area to properly wait for D2H FIS */
552 ata_tf_init(link->device, &tf);
553 tf.command = 0x80;
554 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
555
556 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
557 deadline, &online, NULL);
558
559 ahci_start_engine(ap);
560
561 /* The pseudo configuration device on SIMG4726 attached to
562 * ASUS P5W-DH Deluxe doesn't send signature FIS after
563 * hardreset if no device is attached to the first downstream
564 * port && the pseudo device locks up on SRST w/ PMP==0. To
565 * work around this, wait for !BSY only briefly. If BSY isn't
566 * cleared, perform CLO and proceed to IDENTIFY (achieved by
567 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
568 *
569 * Wait for two seconds. Devices attached to downstream port
570 * which can't process the following IDENTIFY after this will
571 * have to be reset again. For most cases, this should
572 * suffice while making probing snappish enough.
573 */
574 if (online) {
575 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
576 ahci_check_ready);
577 if (rc)
578 ahci_kick_engine(ap);
579 }
580 return rc;
581}
582
583#ifdef CONFIG_PM
584static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
585{
586 struct ata_host *host = dev_get_drvdata(&pdev->dev);
587 struct ahci_host_priv *hpriv = host->private_data;
588 void __iomem *mmio = hpriv->mmio;
589 u32 ctl;
590
591 if (mesg.event & PM_EVENT_SUSPEND &&
592 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
593 dev_err(&pdev->dev,
594 "BIOS update required for suspend/resume\n");
595 return -EIO;
596 }
597
598 if (mesg.event & PM_EVENT_SLEEP) {
599 /* AHCI spec rev1.1 section 8.3.3:
600 * Software must disable interrupts prior to requesting a
601 * transition of the HBA to D3 state.
602 */
603 ctl = readl(mmio + HOST_CTL);
604 ctl &= ~HOST_IRQ_EN;
605 writel(ctl, mmio + HOST_CTL);
606 readl(mmio + HOST_CTL); /* flush */
607 }
608
609 return ata_pci_device_suspend(pdev, mesg);
610}
611
612static int ahci_pci_device_resume(struct pci_dev *pdev)
613{
614 struct ata_host *host = dev_get_drvdata(&pdev->dev);
615 int rc;
616
617 rc = ata_pci_device_do_resume(pdev);
618 if (rc)
619 return rc;
620
621 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
622 rc = ahci_pci_reset_controller(host);
623 if (rc)
624 return rc;
625
626 ahci_pci_init_controller(host);
627 }
628
629 ata_host_resume(host);
630
631 return 0;
632}
633#endif
634
635static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
636{
637 int rc;
638
639 /*
640 * If the device fixup already set the dma_mask to some non-standard
641 * value, don't extend it here. This happens on STA2X11, for example.
642 */
643 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
644 return 0;
645
646 if (using_dac &&
647 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
648 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
649 if (rc) {
650 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
651 if (rc) {
652 dev_err(&pdev->dev,
653 "64-bit DMA enable failed\n");
654 return rc;
655 }
656 }
657 } else {
658 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
659 if (rc) {
660 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
661 return rc;
662 }
663 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
664 if (rc) {
665 dev_err(&pdev->dev,
666 "32-bit consistent DMA enable failed\n");
667 return rc;
668 }
669 }
670 return 0;
671}
672
673static void ahci_pci_print_info(struct ata_host *host)
674{
675 struct pci_dev *pdev = to_pci_dev(host->dev);
676 u16 cc;
677 const char *scc_s;
678
679 pci_read_config_word(pdev, 0x0a, &cc);
680 if (cc == PCI_CLASS_STORAGE_IDE)
681 scc_s = "IDE";
682 else if (cc == PCI_CLASS_STORAGE_SATA)
683 scc_s = "SATA";
684 else if (cc == PCI_CLASS_STORAGE_RAID)
685 scc_s = "RAID";
686 else
687 scc_s = "unknown";
688
689 ahci_print_info(host, scc_s);
690}
691
692/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
693 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
694 * support PMP and the 4726 either directly exports the device
695 * attached to the first downstream port or acts as a hardware storage
696 * controller and emulate a single ATA device (can be RAID 0/1 or some
697 * other configuration).
698 *
699 * When there's no device attached to the first downstream port of the
700 * 4726, "Config Disk" appears, which is a pseudo ATA device to
701 * configure the 4726. However, ATA emulation of the device is very
702 * lame. It doesn't send signature D2H Reg FIS after the initial
703 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
704 *
705 * The following function works around the problem by always using
706 * hardreset on the port and not depending on receiving signature FIS
707 * afterward. If signature FIS isn't received soon, ATA class is
708 * assumed without follow-up softreset.
709 */
710static void ahci_p5wdh_workaround(struct ata_host *host)
711{
712 static struct dmi_system_id sysids[] = {
713 {
714 .ident = "P5W DH Deluxe",
715 .matches = {
716 DMI_MATCH(DMI_SYS_VENDOR,
717 "ASUSTEK COMPUTER INC"),
718 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
719 },
720 },
721 { }
722 };
723 struct pci_dev *pdev = to_pci_dev(host->dev);
724
725 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
726 dmi_check_system(sysids)) {
727 struct ata_port *ap = host->ports[1];
728
729 dev_info(&pdev->dev,
730 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
731
732 ap->ops = &ahci_p5wdh_ops;
733 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
734 }
735}
736
737/* only some SB600 ahci controllers can do 64bit DMA */
738static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
739{
740 static const struct dmi_system_id sysids[] = {
741 /*
742 * The oldest version known to be broken is 0901 and
743 * working is 1501 which was released on 2007-10-26.
744 * Enable 64bit DMA on 1501 and anything newer.
745 *
746 * Please read bko#9412 for more info.
747 */
748 {
749 .ident = "ASUS M2A-VM",
750 .matches = {
751 DMI_MATCH(DMI_BOARD_VENDOR,
752 "ASUSTeK Computer INC."),
753 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
754 },
755 .driver_data = "20071026", /* yyyymmdd */
756 },
757 /*
758 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
759 * support 64bit DMA.
760 *
761 * BIOS versions earlier than 1.5 had the Manufacturer DMI
762 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
763 * This spelling mistake was fixed in BIOS version 1.5, so
764 * 1.5 and later have the Manufacturer as
765 * "MICRO-STAR INTERNATIONAL CO.,LTD".
766 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
767 *
768 * BIOS versions earlier than 1.9 had a Board Product Name
769 * DMI field of "MS-7376". This was changed to be
770 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
771 * match on DMI_BOARD_NAME of "MS-7376".
772 */
773 {
774 .ident = "MSI K9A2 Platinum",
775 .matches = {
776 DMI_MATCH(DMI_BOARD_VENDOR,
777 "MICRO-STAR INTER"),
778 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
779 },
780 },
781 /*
782 * All BIOS versions for the Asus M3A support 64bit DMA.
783 * (all release versions from 0301 to 1206 were tested)
784 */
785 {
786 .ident = "ASUS M3A",
787 .matches = {
788 DMI_MATCH(DMI_BOARD_VENDOR,
789 "ASUSTeK Computer INC."),
790 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
791 },
792 },
793 { }
794 };
795 const struct dmi_system_id *match;
796 int year, month, date;
797 char buf[9];
798
799 match = dmi_first_match(sysids);
800 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
801 !match)
802 return false;
803
804 if (!match->driver_data)
805 goto enable_64bit;
806
807 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
808 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
809
810 if (strcmp(buf, match->driver_data) >= 0)
811 goto enable_64bit;
812 else {
813 dev_warn(&pdev->dev,
814 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
815 match->ident);
816 return false;
817 }
818
819enable_64bit:
820 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
821 return true;
822}
823
824static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
825{
826 static const struct dmi_system_id broken_systems[] = {
827 {
828 .ident = "HP Compaq nx6310",
829 .matches = {
830 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
831 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
832 },
833 /* PCI slot number of the controller */
834 .driver_data = (void *)0x1FUL,
835 },
836 {
837 .ident = "HP Compaq 6720s",
838 .matches = {
839 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
840 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
841 },
842 /* PCI slot number of the controller */
843 .driver_data = (void *)0x1FUL,
844 },
845
846 { } /* terminate list */
847 };
848 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
849
850 if (dmi) {
851 unsigned long slot = (unsigned long)dmi->driver_data;
852 /* apply the quirk only to on-board controllers */
853 return slot == PCI_SLOT(pdev->devfn);
854 }
855
856 return false;
857}
858
859static bool ahci_broken_suspend(struct pci_dev *pdev)
860{
861 static const struct dmi_system_id sysids[] = {
862 /*
863 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
864 * to the harddisk doesn't become online after
865 * resuming from STR. Warn and fail suspend.
866 *
867 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
868 *
869 * Use dates instead of versions to match as HP is
870 * apparently recycling both product and version
871 * strings.
872 *
873 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
874 */
875 {
876 .ident = "dv4",
877 .matches = {
878 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
879 DMI_MATCH(DMI_PRODUCT_NAME,
880 "HP Pavilion dv4 Notebook PC"),
881 },
882 .driver_data = "20090105", /* F.30 */
883 },
884 {
885 .ident = "dv5",
886 .matches = {
887 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
888 DMI_MATCH(DMI_PRODUCT_NAME,
889 "HP Pavilion dv5 Notebook PC"),
890 },
891 .driver_data = "20090506", /* F.16 */
892 },
893 {
894 .ident = "dv6",
895 .matches = {
896 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
897 DMI_MATCH(DMI_PRODUCT_NAME,
898 "HP Pavilion dv6 Notebook PC"),
899 },
900 .driver_data = "20090423", /* F.21 */
901 },
902 {
903 .ident = "HDX18",
904 .matches = {
905 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
906 DMI_MATCH(DMI_PRODUCT_NAME,
907 "HP HDX18 Notebook PC"),
908 },
909 .driver_data = "20090430", /* F.23 */
910 },
911 /*
912 * Acer eMachines G725 has the same problem. BIOS
913 * V1.03 is known to be broken. V3.04 is known to
914 * work. Between, there are V1.06, V2.06 and V3.03
915 * that we don't have much idea about. For now,
916 * blacklist anything older than V3.04.
917 *
918 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
919 */
920 {
921 .ident = "G725",
922 .matches = {
923 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
924 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
925 },
926 .driver_data = "20091216", /* V3.04 */
927 },
928 { } /* terminate list */
929 };
930 const struct dmi_system_id *dmi = dmi_first_match(sysids);
931 int year, month, date;
932 char buf[9];
933
934 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
935 return false;
936
937 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
938 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
939
940 return strcmp(buf, dmi->driver_data) < 0;
941}
942
943static bool ahci_broken_online(struct pci_dev *pdev)
944{
945#define ENCODE_BUSDEVFN(bus, slot, func) \
946 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
947 static const struct dmi_system_id sysids[] = {
948 /*
949 * There are several gigabyte boards which use
950 * SIMG5723s configured as hardware RAID. Certain
951 * 5723 firmware revisions shipped there keep the link
952 * online but fail to answer properly to SRST or
953 * IDENTIFY when no device is attached downstream
954 * causing libata to retry quite a few times leading
955 * to excessive detection delay.
956 *
957 * As these firmwares respond to the second reset try
958 * with invalid device signature, considering unknown
959 * sig as offline works around the problem acceptably.
960 */
961 {
962 .ident = "EP45-DQ6",
963 .matches = {
964 DMI_MATCH(DMI_BOARD_VENDOR,
965 "Gigabyte Technology Co., Ltd."),
966 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
967 },
968 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
969 },
970 {
971 .ident = "EP45-DS5",
972 .matches = {
973 DMI_MATCH(DMI_BOARD_VENDOR,
974 "Gigabyte Technology Co., Ltd."),
975 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
976 },
977 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
978 },
979 { } /* terminate list */
980 };
981#undef ENCODE_BUSDEVFN
982 const struct dmi_system_id *dmi = dmi_first_match(sysids);
983 unsigned int val;
984
985 if (!dmi)
986 return false;
987
988 val = (unsigned long)dmi->driver_data;
989
990 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
991}
992
993#ifdef CONFIG_ATA_ACPI
994static void ahci_gtf_filter_workaround(struct ata_host *host)
995{
996 static const struct dmi_system_id sysids[] = {
997 /*
998 * Aspire 3810T issues a bunch of SATA enable commands
999 * via _GTF including an invalid one and one which is
1000 * rejected by the device. Among the successful ones
1001 * is FPDMA non-zero offset enable which when enabled
1002 * only on the drive side leads to NCQ command
1003 * failures. Filter it out.
1004 */
1005 {
1006 .ident = "Aspire 3810T",
1007 .matches = {
1008 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1009 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1010 },
1011 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1012 },
1013 { }
1014 };
1015 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1016 unsigned int filter;
1017 int i;
1018
1019 if (!dmi)
1020 return;
1021
1022 filter = (unsigned long)dmi->driver_data;
1023 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1024 filter, dmi->ident);
1025
1026 for (i = 0; i < host->n_ports; i++) {
1027 struct ata_port *ap = host->ports[i];
1028 struct ata_link *link;
1029 struct ata_device *dev;
1030
1031 ata_for_each_link(link, ap, EDGE)
1032 ata_for_each_dev(dev, link, ALL)
1033 dev->gtf_filter |= filter;
1034 }
1035}
1036#else
1037static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1038{}
1039#endif
1040
1041static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1042{
1043 unsigned int board_id = ent->driver_data;
1044 struct ata_port_info pi = ahci_port_info[board_id];
1045 const struct ata_port_info *ppi[] = { &pi, NULL };
1046 struct device *dev = &pdev->dev;
1047 struct ahci_host_priv *hpriv;
1048 struct ata_host *host;
1049 int n_ports, i, rc;
1050 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1051
1052 VPRINTK("ENTER\n");
1053
1054 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1055
1056 ata_print_version_once(&pdev->dev, DRV_VERSION);
1057
1058 /* The AHCI driver can only drive the SATA ports, the PATA driver
1059 can drive them all so if both drivers are selected make sure
1060 AHCI stays out of the way */
1061 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1062 return -ENODEV;
1063
1064 /*
1065 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1066 * ahci, use ata_generic instead.
1067 */
1068 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1069 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1070 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1071 pdev->subsystem_device == 0xcb89)
1072 return -ENODEV;
1073
1074 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1075 * At the moment, we can only use the AHCI mode. Let the users know
1076 * that for SAS drives they're out of luck.
1077 */
1078 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1079 dev_info(&pdev->dev,
1080 "PDC42819 can only drive SATA devices with this driver\n");
1081
1082 /* The Connext uses non-standard BAR */
1083 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1084 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1085
1086 /* acquire resources */
1087 rc = pcim_enable_device(pdev);
1088 if (rc)
1089 return rc;
1090
1091 /* AHCI controllers often implement SFF compatible interface.
1092 * Grab all PCI BARs just in case.
1093 */
1094 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1095 if (rc == -EBUSY)
1096 pcim_pin_device(pdev);
1097 if (rc)
1098 return rc;
1099
1100 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1101 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1102 u8 map;
1103
1104 /* ICH6s share the same PCI ID for both piix and ahci
1105 * modes. Enabling ahci mode while MAP indicates
1106 * combined mode is a bad idea. Yield to ata_piix.
1107 */
1108 pci_read_config_byte(pdev, ICH_MAP, &map);
1109 if (map & 0x3) {
1110 dev_info(&pdev->dev,
1111 "controller is in combined mode, can't enable AHCI mode\n");
1112 return -ENODEV;
1113 }
1114 }
1115
1116 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1117 if (!hpriv)
1118 return -ENOMEM;
1119 hpriv->flags |= (unsigned long)pi.private_data;
1120
1121 /* MCP65 revision A1 and A2 can't do MSI */
1122 if (board_id == board_ahci_mcp65 &&
1123 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1124 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1125
1126 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1127 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1128 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1129
1130 /* only some SB600s can do 64bit DMA */
1131 if (ahci_sb600_enable_64bit(pdev))
1132 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1133
1134 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1135 pci_intx(pdev, 1);
1136
1137 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1138
1139 /* save initial config */
1140 ahci_pci_save_initial_config(pdev, hpriv);
1141
1142 /* prepare host */
1143 if (hpriv->cap & HOST_CAP_NCQ) {
1144 pi.flags |= ATA_FLAG_NCQ;
1145 /*
1146 * Auto-activate optimization is supposed to be
1147 * supported on all AHCI controllers indicating NCQ
1148 * capability, but it seems to be broken on some
1149 * chipsets including NVIDIAs.
1150 */
1151 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1152 pi.flags |= ATA_FLAG_FPDMA_AA;
1153 }
1154
1155 if (hpriv->cap & HOST_CAP_PMP)
1156 pi.flags |= ATA_FLAG_PMP;
1157
1158 ahci_set_em_messages(hpriv, &pi);
1159
1160 if (ahci_broken_system_poweroff(pdev)) {
1161 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1162 dev_info(&pdev->dev,
1163 "quirky BIOS, skipping spindown on poweroff\n");
1164 }
1165
1166 if (ahci_broken_suspend(pdev)) {
1167 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1168 dev_warn(&pdev->dev,
1169 "BIOS update required for suspend/resume\n");
1170 }
1171
1172 if (ahci_broken_online(pdev)) {
1173 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1174 dev_info(&pdev->dev,
1175 "online status unreliable, applying workaround\n");
1176 }
1177
1178 /* CAP.NP sometimes indicate the index of the last enabled
1179 * port, at other times, that of the last possible port, so
1180 * determining the maximum port number requires looking at
1181 * both CAP.NP and port_map.
1182 */
1183 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1184
1185 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1186 if (!host)
1187 return -ENOMEM;
1188 host->private_data = hpriv;
1189
1190 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1191 host->flags |= ATA_HOST_PARALLEL_SCAN;
1192 else
1193 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1194
1195 if (pi.flags & ATA_FLAG_EM)
1196 ahci_reset_em(host);
1197
1198 for (i = 0; i < host->n_ports; i++) {
1199 struct ata_port *ap = host->ports[i];
1200
1201 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1202 ata_port_pbar_desc(ap, ahci_pci_bar,
1203 0x100 + ap->port_no * 0x80, "port");
1204
1205 /* set enclosure management message type */
1206 if (ap->flags & ATA_FLAG_EM)
1207 ap->em_message_type = hpriv->em_msg_type;
1208
1209
1210 /* disabled/not-implemented port */
1211 if (!(hpriv->port_map & (1 << i)))
1212 ap->ops = &ata_dummy_port_ops;
1213 }
1214
1215 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1216 ahci_p5wdh_workaround(host);
1217
1218 /* apply gtf filter quirk */
1219 ahci_gtf_filter_workaround(host);
1220
1221 /* initialize adapter */
1222 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1223 if (rc)
1224 return rc;
1225
1226 rc = ahci_pci_reset_controller(host);
1227 if (rc)
1228 return rc;
1229
1230 ahci_pci_init_controller(host);
1231 ahci_pci_print_info(host);
1232
1233 pci_set_master(pdev);
1234 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1235 &ahci_sht);
1236}
1237
1238static int __init ahci_init(void)
1239{
1240 return pci_register_driver(&ahci_pci_driver);
1241}
1242
1243static void __exit ahci_exit(void)
1244{
1245 pci_unregister_driver(&ahci_pci_driver);
1246}
1247
1248
1249MODULE_AUTHOR("Jeff Garzik");
1250MODULE_DESCRIPTION("AHCI SATA low-level driver");
1251MODULE_LICENSE("GPL");
1252MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1253MODULE_VERSION(DRV_VERSION);
1254
1255module_init(ahci_init);
1256module_exit(ahci_exit);