Loading...
1/*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <linux/dmi.h>
45#include <linux/gfp.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h>
49#include "ahci.h"
50
51#define DRV_NAME "ahci"
52#define DRV_VERSION "3.0"
53
54enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
64 board_ahci_yes_fbs,
65
66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
68 board_ahci_mcp77,
69 board_ahci_mcp89,
70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
79 board_ahci_mcp79 = board_ahci_mcp77,
80};
81
82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87#ifdef CONFIG_PM
88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
90#endif
91
92static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
96static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
98 .hardreset = ahci_vt8251_hardreset,
99};
100
101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
103 .hardreset = ahci_p5wdh_hardreset,
104};
105
106static const struct ata_port_info ahci_port_info[] = {
107 /* by features */
108 [board_ahci] =
109 {
110 .flags = AHCI_FLAG_COMMON,
111 .pio_mask = ATA_PIO4,
112 .udma_mask = ATA_UDMA6,
113 .port_ops = &ahci_ops,
114 },
115 [board_ahci_ign_iferr] =
116 {
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
122 },
123 [board_ahci_nosntf] =
124 {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_yes_fbs] =
132 {
133 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 /* by chipsets */
140 [board_ahci_mcp65] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
143 AHCI_HFLAG_YES_NCQ),
144 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_mcp77] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
157 [board_ahci_mcp89] =
158 {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_mv] =
166 {
167 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
168 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
169 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_sb600] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_pmp_retry_srst_ops,
183 },
184 [board_ahci_sb700] = /* for SB700 and SB800 */
185 {
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
191 },
192 [board_ahci_vt8251] =
193 {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_vt8251_ops,
199 },
200};
201
202static const struct pci_device_id ahci_pci_tbl[] = {
203 /* Intel */
204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
270
271 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
272 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
273 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
274
275 /* ATI */
276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
283
284 /* AMD */
285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
290 /* VIA */
291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
293
294 /* NVIDIA */
295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
379
380 /* SiS */
381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
384
385 /* ST Microelectronics */
386 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
387
388 /* Marvell */
389 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
390 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
391 { PCI_DEVICE(0x1b4b, 0x9123),
392 .class = PCI_CLASS_STORAGE_SATA_AHCI,
393 .class_mask = 0xffffff,
394 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
395 { PCI_DEVICE(0x1b4b, 0x9125),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
397 { PCI_DEVICE(0x1b4b, 0x917a),
398 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
399 { PCI_DEVICE(0x1b4b, 0x9192),
400 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
401 { PCI_DEVICE(0x1b4b, 0x91a3),
402 .driver_data = board_ahci_yes_fbs },
403
404 /* Promise */
405 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
406
407 /* Asmedia */
408 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
409
410 /* Generic, PCI class code for AHCI */
411 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
412 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
413
414 { } /* terminate list */
415};
416
417
418static struct pci_driver ahci_pci_driver = {
419 .name = DRV_NAME,
420 .id_table = ahci_pci_tbl,
421 .probe = ahci_init_one,
422 .remove = ata_pci_remove_one,
423#ifdef CONFIG_PM
424 .suspend = ahci_pci_device_suspend,
425 .resume = ahci_pci_device_resume,
426#endif
427};
428
429#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
430static int marvell_enable;
431#else
432static int marvell_enable = 1;
433#endif
434module_param(marvell_enable, int, 0644);
435MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
436
437
438static void ahci_pci_save_initial_config(struct pci_dev *pdev,
439 struct ahci_host_priv *hpriv)
440{
441 unsigned int force_port_map = 0;
442 unsigned int mask_port_map = 0;
443
444 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
445 dev_info(&pdev->dev, "JMB361 has only one port\n");
446 force_port_map = 1;
447 }
448
449 /*
450 * Temporary Marvell 6145 hack: PATA port presence
451 * is asserted through the standard AHCI port
452 * presence register, as bit 4 (counting from 0)
453 */
454 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
455 if (pdev->device == 0x6121)
456 mask_port_map = 0x3;
457 else
458 mask_port_map = 0xf;
459 dev_info(&pdev->dev,
460 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
461 }
462
463 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
464 mask_port_map);
465}
466
467static int ahci_pci_reset_controller(struct ata_host *host)
468{
469 struct pci_dev *pdev = to_pci_dev(host->dev);
470
471 ahci_reset_controller(host);
472
473 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
474 struct ahci_host_priv *hpriv = host->private_data;
475 u16 tmp16;
476
477 /* configure PCS */
478 pci_read_config_word(pdev, 0x92, &tmp16);
479 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
480 tmp16 |= hpriv->port_map;
481 pci_write_config_word(pdev, 0x92, tmp16);
482 }
483 }
484
485 return 0;
486}
487
488static void ahci_pci_init_controller(struct ata_host *host)
489{
490 struct ahci_host_priv *hpriv = host->private_data;
491 struct pci_dev *pdev = to_pci_dev(host->dev);
492 void __iomem *port_mmio;
493 u32 tmp;
494 int mv;
495
496 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
497 if (pdev->device == 0x6121)
498 mv = 2;
499 else
500 mv = 4;
501 port_mmio = __ahci_port_base(host, mv);
502
503 writel(0, port_mmio + PORT_IRQ_MASK);
504
505 /* clear port IRQ */
506 tmp = readl(port_mmio + PORT_IRQ_STAT);
507 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
508 if (tmp)
509 writel(tmp, port_mmio + PORT_IRQ_STAT);
510 }
511
512 ahci_init_controller(host);
513}
514
515static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
516 unsigned long deadline)
517{
518 struct ata_port *ap = link->ap;
519 bool online;
520 int rc;
521
522 DPRINTK("ENTER\n");
523
524 ahci_stop_engine(ap);
525
526 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
527 deadline, &online, NULL);
528
529 ahci_start_engine(ap);
530
531 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
532
533 /* vt8251 doesn't clear BSY on signature FIS reception,
534 * request follow-up softreset.
535 */
536 return online ? -EAGAIN : rc;
537}
538
539static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
540 unsigned long deadline)
541{
542 struct ata_port *ap = link->ap;
543 struct ahci_port_priv *pp = ap->private_data;
544 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
545 struct ata_taskfile tf;
546 bool online;
547 int rc;
548
549 ahci_stop_engine(ap);
550
551 /* clear D2H reception area to properly wait for D2H FIS */
552 ata_tf_init(link->device, &tf);
553 tf.command = 0x80;
554 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
555
556 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
557 deadline, &online, NULL);
558
559 ahci_start_engine(ap);
560
561 /* The pseudo configuration device on SIMG4726 attached to
562 * ASUS P5W-DH Deluxe doesn't send signature FIS after
563 * hardreset if no device is attached to the first downstream
564 * port && the pseudo device locks up on SRST w/ PMP==0. To
565 * work around this, wait for !BSY only briefly. If BSY isn't
566 * cleared, perform CLO and proceed to IDENTIFY (achieved by
567 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
568 *
569 * Wait for two seconds. Devices attached to downstream port
570 * which can't process the following IDENTIFY after this will
571 * have to be reset again. For most cases, this should
572 * suffice while making probing snappish enough.
573 */
574 if (online) {
575 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
576 ahci_check_ready);
577 if (rc)
578 ahci_kick_engine(ap);
579 }
580 return rc;
581}
582
583#ifdef CONFIG_PM
584static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
585{
586 struct ata_host *host = dev_get_drvdata(&pdev->dev);
587 struct ahci_host_priv *hpriv = host->private_data;
588 void __iomem *mmio = hpriv->mmio;
589 u32 ctl;
590
591 if (mesg.event & PM_EVENT_SUSPEND &&
592 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
593 dev_err(&pdev->dev,
594 "BIOS update required for suspend/resume\n");
595 return -EIO;
596 }
597
598 if (mesg.event & PM_EVENT_SLEEP) {
599 /* AHCI spec rev1.1 section 8.3.3:
600 * Software must disable interrupts prior to requesting a
601 * transition of the HBA to D3 state.
602 */
603 ctl = readl(mmio + HOST_CTL);
604 ctl &= ~HOST_IRQ_EN;
605 writel(ctl, mmio + HOST_CTL);
606 readl(mmio + HOST_CTL); /* flush */
607 }
608
609 return ata_pci_device_suspend(pdev, mesg);
610}
611
612static int ahci_pci_device_resume(struct pci_dev *pdev)
613{
614 struct ata_host *host = dev_get_drvdata(&pdev->dev);
615 int rc;
616
617 rc = ata_pci_device_do_resume(pdev);
618 if (rc)
619 return rc;
620
621 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
622 rc = ahci_pci_reset_controller(host);
623 if (rc)
624 return rc;
625
626 ahci_pci_init_controller(host);
627 }
628
629 ata_host_resume(host);
630
631 return 0;
632}
633#endif
634
635static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
636{
637 int rc;
638
639 /*
640 * If the device fixup already set the dma_mask to some non-standard
641 * value, don't extend it here. This happens on STA2X11, for example.
642 */
643 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
644 return 0;
645
646 if (using_dac &&
647 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
648 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
649 if (rc) {
650 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
651 if (rc) {
652 dev_err(&pdev->dev,
653 "64-bit DMA enable failed\n");
654 return rc;
655 }
656 }
657 } else {
658 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
659 if (rc) {
660 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
661 return rc;
662 }
663 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
664 if (rc) {
665 dev_err(&pdev->dev,
666 "32-bit consistent DMA enable failed\n");
667 return rc;
668 }
669 }
670 return 0;
671}
672
673static void ahci_pci_print_info(struct ata_host *host)
674{
675 struct pci_dev *pdev = to_pci_dev(host->dev);
676 u16 cc;
677 const char *scc_s;
678
679 pci_read_config_word(pdev, 0x0a, &cc);
680 if (cc == PCI_CLASS_STORAGE_IDE)
681 scc_s = "IDE";
682 else if (cc == PCI_CLASS_STORAGE_SATA)
683 scc_s = "SATA";
684 else if (cc == PCI_CLASS_STORAGE_RAID)
685 scc_s = "RAID";
686 else
687 scc_s = "unknown";
688
689 ahci_print_info(host, scc_s);
690}
691
692/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
693 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
694 * support PMP and the 4726 either directly exports the device
695 * attached to the first downstream port or acts as a hardware storage
696 * controller and emulate a single ATA device (can be RAID 0/1 or some
697 * other configuration).
698 *
699 * When there's no device attached to the first downstream port of the
700 * 4726, "Config Disk" appears, which is a pseudo ATA device to
701 * configure the 4726. However, ATA emulation of the device is very
702 * lame. It doesn't send signature D2H Reg FIS after the initial
703 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
704 *
705 * The following function works around the problem by always using
706 * hardreset on the port and not depending on receiving signature FIS
707 * afterward. If signature FIS isn't received soon, ATA class is
708 * assumed without follow-up softreset.
709 */
710static void ahci_p5wdh_workaround(struct ata_host *host)
711{
712 static struct dmi_system_id sysids[] = {
713 {
714 .ident = "P5W DH Deluxe",
715 .matches = {
716 DMI_MATCH(DMI_SYS_VENDOR,
717 "ASUSTEK COMPUTER INC"),
718 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
719 },
720 },
721 { }
722 };
723 struct pci_dev *pdev = to_pci_dev(host->dev);
724
725 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
726 dmi_check_system(sysids)) {
727 struct ata_port *ap = host->ports[1];
728
729 dev_info(&pdev->dev,
730 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
731
732 ap->ops = &ahci_p5wdh_ops;
733 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
734 }
735}
736
737/* only some SB600 ahci controllers can do 64bit DMA */
738static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
739{
740 static const struct dmi_system_id sysids[] = {
741 /*
742 * The oldest version known to be broken is 0901 and
743 * working is 1501 which was released on 2007-10-26.
744 * Enable 64bit DMA on 1501 and anything newer.
745 *
746 * Please read bko#9412 for more info.
747 */
748 {
749 .ident = "ASUS M2A-VM",
750 .matches = {
751 DMI_MATCH(DMI_BOARD_VENDOR,
752 "ASUSTeK Computer INC."),
753 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
754 },
755 .driver_data = "20071026", /* yyyymmdd */
756 },
757 /*
758 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
759 * support 64bit DMA.
760 *
761 * BIOS versions earlier than 1.5 had the Manufacturer DMI
762 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
763 * This spelling mistake was fixed in BIOS version 1.5, so
764 * 1.5 and later have the Manufacturer as
765 * "MICRO-STAR INTERNATIONAL CO.,LTD".
766 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
767 *
768 * BIOS versions earlier than 1.9 had a Board Product Name
769 * DMI field of "MS-7376". This was changed to be
770 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
771 * match on DMI_BOARD_NAME of "MS-7376".
772 */
773 {
774 .ident = "MSI K9A2 Platinum",
775 .matches = {
776 DMI_MATCH(DMI_BOARD_VENDOR,
777 "MICRO-STAR INTER"),
778 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
779 },
780 },
781 /*
782 * All BIOS versions for the Asus M3A support 64bit DMA.
783 * (all release versions from 0301 to 1206 were tested)
784 */
785 {
786 .ident = "ASUS M3A",
787 .matches = {
788 DMI_MATCH(DMI_BOARD_VENDOR,
789 "ASUSTeK Computer INC."),
790 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
791 },
792 },
793 { }
794 };
795 const struct dmi_system_id *match;
796 int year, month, date;
797 char buf[9];
798
799 match = dmi_first_match(sysids);
800 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
801 !match)
802 return false;
803
804 if (!match->driver_data)
805 goto enable_64bit;
806
807 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
808 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
809
810 if (strcmp(buf, match->driver_data) >= 0)
811 goto enable_64bit;
812 else {
813 dev_warn(&pdev->dev,
814 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
815 match->ident);
816 return false;
817 }
818
819enable_64bit:
820 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
821 return true;
822}
823
824static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
825{
826 static const struct dmi_system_id broken_systems[] = {
827 {
828 .ident = "HP Compaq nx6310",
829 .matches = {
830 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
831 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
832 },
833 /* PCI slot number of the controller */
834 .driver_data = (void *)0x1FUL,
835 },
836 {
837 .ident = "HP Compaq 6720s",
838 .matches = {
839 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
840 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
841 },
842 /* PCI slot number of the controller */
843 .driver_data = (void *)0x1FUL,
844 },
845
846 { } /* terminate list */
847 };
848 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
849
850 if (dmi) {
851 unsigned long slot = (unsigned long)dmi->driver_data;
852 /* apply the quirk only to on-board controllers */
853 return slot == PCI_SLOT(pdev->devfn);
854 }
855
856 return false;
857}
858
859static bool ahci_broken_suspend(struct pci_dev *pdev)
860{
861 static const struct dmi_system_id sysids[] = {
862 /*
863 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
864 * to the harddisk doesn't become online after
865 * resuming from STR. Warn and fail suspend.
866 *
867 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
868 *
869 * Use dates instead of versions to match as HP is
870 * apparently recycling both product and version
871 * strings.
872 *
873 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
874 */
875 {
876 .ident = "dv4",
877 .matches = {
878 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
879 DMI_MATCH(DMI_PRODUCT_NAME,
880 "HP Pavilion dv4 Notebook PC"),
881 },
882 .driver_data = "20090105", /* F.30 */
883 },
884 {
885 .ident = "dv5",
886 .matches = {
887 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
888 DMI_MATCH(DMI_PRODUCT_NAME,
889 "HP Pavilion dv5 Notebook PC"),
890 },
891 .driver_data = "20090506", /* F.16 */
892 },
893 {
894 .ident = "dv6",
895 .matches = {
896 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
897 DMI_MATCH(DMI_PRODUCT_NAME,
898 "HP Pavilion dv6 Notebook PC"),
899 },
900 .driver_data = "20090423", /* F.21 */
901 },
902 {
903 .ident = "HDX18",
904 .matches = {
905 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
906 DMI_MATCH(DMI_PRODUCT_NAME,
907 "HP HDX18 Notebook PC"),
908 },
909 .driver_data = "20090430", /* F.23 */
910 },
911 /*
912 * Acer eMachines G725 has the same problem. BIOS
913 * V1.03 is known to be broken. V3.04 is known to
914 * work. Between, there are V1.06, V2.06 and V3.03
915 * that we don't have much idea about. For now,
916 * blacklist anything older than V3.04.
917 *
918 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
919 */
920 {
921 .ident = "G725",
922 .matches = {
923 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
924 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
925 },
926 .driver_data = "20091216", /* V3.04 */
927 },
928 { } /* terminate list */
929 };
930 const struct dmi_system_id *dmi = dmi_first_match(sysids);
931 int year, month, date;
932 char buf[9];
933
934 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
935 return false;
936
937 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
938 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
939
940 return strcmp(buf, dmi->driver_data) < 0;
941}
942
943static bool ahci_broken_online(struct pci_dev *pdev)
944{
945#define ENCODE_BUSDEVFN(bus, slot, func) \
946 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
947 static const struct dmi_system_id sysids[] = {
948 /*
949 * There are several gigabyte boards which use
950 * SIMG5723s configured as hardware RAID. Certain
951 * 5723 firmware revisions shipped there keep the link
952 * online but fail to answer properly to SRST or
953 * IDENTIFY when no device is attached downstream
954 * causing libata to retry quite a few times leading
955 * to excessive detection delay.
956 *
957 * As these firmwares respond to the second reset try
958 * with invalid device signature, considering unknown
959 * sig as offline works around the problem acceptably.
960 */
961 {
962 .ident = "EP45-DQ6",
963 .matches = {
964 DMI_MATCH(DMI_BOARD_VENDOR,
965 "Gigabyte Technology Co., Ltd."),
966 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
967 },
968 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
969 },
970 {
971 .ident = "EP45-DS5",
972 .matches = {
973 DMI_MATCH(DMI_BOARD_VENDOR,
974 "Gigabyte Technology Co., Ltd."),
975 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
976 },
977 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
978 },
979 { } /* terminate list */
980 };
981#undef ENCODE_BUSDEVFN
982 const struct dmi_system_id *dmi = dmi_first_match(sysids);
983 unsigned int val;
984
985 if (!dmi)
986 return false;
987
988 val = (unsigned long)dmi->driver_data;
989
990 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
991}
992
993#ifdef CONFIG_ATA_ACPI
994static void ahci_gtf_filter_workaround(struct ata_host *host)
995{
996 static const struct dmi_system_id sysids[] = {
997 /*
998 * Aspire 3810T issues a bunch of SATA enable commands
999 * via _GTF including an invalid one and one which is
1000 * rejected by the device. Among the successful ones
1001 * is FPDMA non-zero offset enable which when enabled
1002 * only on the drive side leads to NCQ command
1003 * failures. Filter it out.
1004 */
1005 {
1006 .ident = "Aspire 3810T",
1007 .matches = {
1008 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1009 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1010 },
1011 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1012 },
1013 { }
1014 };
1015 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1016 unsigned int filter;
1017 int i;
1018
1019 if (!dmi)
1020 return;
1021
1022 filter = (unsigned long)dmi->driver_data;
1023 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1024 filter, dmi->ident);
1025
1026 for (i = 0; i < host->n_ports; i++) {
1027 struct ata_port *ap = host->ports[i];
1028 struct ata_link *link;
1029 struct ata_device *dev;
1030
1031 ata_for_each_link(link, ap, EDGE)
1032 ata_for_each_dev(dev, link, ALL)
1033 dev->gtf_filter |= filter;
1034 }
1035}
1036#else
1037static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1038{}
1039#endif
1040
1041static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1042{
1043 unsigned int board_id = ent->driver_data;
1044 struct ata_port_info pi = ahci_port_info[board_id];
1045 const struct ata_port_info *ppi[] = { &pi, NULL };
1046 struct device *dev = &pdev->dev;
1047 struct ahci_host_priv *hpriv;
1048 struct ata_host *host;
1049 int n_ports, i, rc;
1050 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1051
1052 VPRINTK("ENTER\n");
1053
1054 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1055
1056 ata_print_version_once(&pdev->dev, DRV_VERSION);
1057
1058 /* The AHCI driver can only drive the SATA ports, the PATA driver
1059 can drive them all so if both drivers are selected make sure
1060 AHCI stays out of the way */
1061 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1062 return -ENODEV;
1063
1064 /*
1065 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1066 * ahci, use ata_generic instead.
1067 */
1068 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1069 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1070 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1071 pdev->subsystem_device == 0xcb89)
1072 return -ENODEV;
1073
1074 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1075 * At the moment, we can only use the AHCI mode. Let the users know
1076 * that for SAS drives they're out of luck.
1077 */
1078 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1079 dev_info(&pdev->dev,
1080 "PDC42819 can only drive SATA devices with this driver\n");
1081
1082 /* The Connext uses non-standard BAR */
1083 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1084 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1085
1086 /* acquire resources */
1087 rc = pcim_enable_device(pdev);
1088 if (rc)
1089 return rc;
1090
1091 /* AHCI controllers often implement SFF compatible interface.
1092 * Grab all PCI BARs just in case.
1093 */
1094 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1095 if (rc == -EBUSY)
1096 pcim_pin_device(pdev);
1097 if (rc)
1098 return rc;
1099
1100 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1101 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1102 u8 map;
1103
1104 /* ICH6s share the same PCI ID for both piix and ahci
1105 * modes. Enabling ahci mode while MAP indicates
1106 * combined mode is a bad idea. Yield to ata_piix.
1107 */
1108 pci_read_config_byte(pdev, ICH_MAP, &map);
1109 if (map & 0x3) {
1110 dev_info(&pdev->dev,
1111 "controller is in combined mode, can't enable AHCI mode\n");
1112 return -ENODEV;
1113 }
1114 }
1115
1116 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1117 if (!hpriv)
1118 return -ENOMEM;
1119 hpriv->flags |= (unsigned long)pi.private_data;
1120
1121 /* MCP65 revision A1 and A2 can't do MSI */
1122 if (board_id == board_ahci_mcp65 &&
1123 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1124 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1125
1126 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1127 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1128 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1129
1130 /* only some SB600s can do 64bit DMA */
1131 if (ahci_sb600_enable_64bit(pdev))
1132 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1133
1134 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1135 pci_intx(pdev, 1);
1136
1137 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1138
1139 /* save initial config */
1140 ahci_pci_save_initial_config(pdev, hpriv);
1141
1142 /* prepare host */
1143 if (hpriv->cap & HOST_CAP_NCQ) {
1144 pi.flags |= ATA_FLAG_NCQ;
1145 /*
1146 * Auto-activate optimization is supposed to be
1147 * supported on all AHCI controllers indicating NCQ
1148 * capability, but it seems to be broken on some
1149 * chipsets including NVIDIAs.
1150 */
1151 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1152 pi.flags |= ATA_FLAG_FPDMA_AA;
1153 }
1154
1155 if (hpriv->cap & HOST_CAP_PMP)
1156 pi.flags |= ATA_FLAG_PMP;
1157
1158 ahci_set_em_messages(hpriv, &pi);
1159
1160 if (ahci_broken_system_poweroff(pdev)) {
1161 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1162 dev_info(&pdev->dev,
1163 "quirky BIOS, skipping spindown on poweroff\n");
1164 }
1165
1166 if (ahci_broken_suspend(pdev)) {
1167 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1168 dev_warn(&pdev->dev,
1169 "BIOS update required for suspend/resume\n");
1170 }
1171
1172 if (ahci_broken_online(pdev)) {
1173 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1174 dev_info(&pdev->dev,
1175 "online status unreliable, applying workaround\n");
1176 }
1177
1178 /* CAP.NP sometimes indicate the index of the last enabled
1179 * port, at other times, that of the last possible port, so
1180 * determining the maximum port number requires looking at
1181 * both CAP.NP and port_map.
1182 */
1183 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1184
1185 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1186 if (!host)
1187 return -ENOMEM;
1188 host->private_data = hpriv;
1189
1190 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1191 host->flags |= ATA_HOST_PARALLEL_SCAN;
1192 else
1193 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1194
1195 if (pi.flags & ATA_FLAG_EM)
1196 ahci_reset_em(host);
1197
1198 for (i = 0; i < host->n_ports; i++) {
1199 struct ata_port *ap = host->ports[i];
1200
1201 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1202 ata_port_pbar_desc(ap, ahci_pci_bar,
1203 0x100 + ap->port_no * 0x80, "port");
1204
1205 /* set enclosure management message type */
1206 if (ap->flags & ATA_FLAG_EM)
1207 ap->em_message_type = hpriv->em_msg_type;
1208
1209
1210 /* disabled/not-implemented port */
1211 if (!(hpriv->port_map & (1 << i)))
1212 ap->ops = &ata_dummy_port_ops;
1213 }
1214
1215 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1216 ahci_p5wdh_workaround(host);
1217
1218 /* apply gtf filter quirk */
1219 ahci_gtf_filter_workaround(host);
1220
1221 /* initialize adapter */
1222 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1223 if (rc)
1224 return rc;
1225
1226 rc = ahci_pci_reset_controller(host);
1227 if (rc)
1228 return rc;
1229
1230 ahci_pci_init_controller(host);
1231 ahci_pci_print_info(host);
1232
1233 pci_set_master(pdev);
1234 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1235 &ahci_sht);
1236}
1237
1238static int __init ahci_init(void)
1239{
1240 return pci_register_driver(&ahci_pci_driver);
1241}
1242
1243static void __exit ahci_exit(void)
1244{
1245 pci_unregister_driver(&ahci_pci_driver);
1246}
1247
1248
1249MODULE_AUTHOR("Jeff Garzik");
1250MODULE_DESCRIPTION("AHCI SATA low-level driver");
1251MODULE_LICENSE("GPL");
1252MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1253MODULE_VERSION(DRV_VERSION);
1254
1255module_init(ahci_init);
1256module_exit(ahci_exit);