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1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/export.h>
45#include <linux/sched.h>
46#include <linux/sched/topology.h>
47#include <linux/sched/hotplug.h>
48#include <linux/sched/task_stack.h>
49#include <linux/percpu.h>
50#include <linux/memblock.h>
51#include <linux/err.h>
52#include <linux/nmi.h>
53#include <linux/tboot.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56#include <linux/kexec.h>
57#include <linux/numa.h>
58#include <linux/pgtable.h>
59#include <linux/overflow.h>
60#include <linux/stackprotector.h>
61#include <linux/cpuhotplug.h>
62#include <linux/mc146818rtc.h>
63
64#include <asm/acpi.h>
65#include <asm/cacheinfo.h>
66#include <asm/desc.h>
67#include <asm/nmi.h>
68#include <asm/irq.h>
69#include <asm/realmode.h>
70#include <asm/cpu.h>
71#include <asm/numa.h>
72#include <asm/tlbflush.h>
73#include <asm/mtrr.h>
74#include <asm/mwait.h>
75#include <asm/apic.h>
76#include <asm/io_apic.h>
77#include <asm/fpu/api.h>
78#include <asm/setup.h>
79#include <asm/uv/uv.h>
80#include <asm/microcode.h>
81#include <asm/i8259.h>
82#include <asm/misc.h>
83#include <asm/qspinlock.h>
84#include <asm/intel-family.h>
85#include <asm/cpu_device_id.h>
86#include <asm/spec-ctrl.h>
87#include <asm/hw_irq.h>
88#include <asm/stackprotector.h>
89#include <asm/sev.h>
90#include <asm/spec-ctrl.h>
91
92/* representing HT siblings of each logical CPU */
93DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
94EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
95
96/* representing HT and core siblings of each logical CPU */
97DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
98EXPORT_PER_CPU_SYMBOL(cpu_core_map);
99
100/* representing HT, core, and die siblings of each logical CPU */
101DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
102EXPORT_PER_CPU_SYMBOL(cpu_die_map);
103
104/* Per CPU bogomips and other parameters */
105DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
106EXPORT_PER_CPU_SYMBOL(cpu_info);
107
108/* CPUs which are the primary SMT threads */
109struct cpumask __cpu_primary_thread_mask __read_mostly;
110
111/* Representing CPUs for which sibling maps can be computed */
112static cpumask_var_t cpu_sibling_setup_mask;
113
114struct mwait_cpu_dead {
115 unsigned int control;
116 unsigned int status;
117};
118
119#define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
120#define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
121
122/*
123 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
124 * that it's unlikely to be touched by other CPUs.
125 */
126static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
127
128/* Logical package management. */
129struct logical_maps {
130 u32 phys_pkg_id;
131 u32 phys_die_id;
132 u32 logical_pkg_id;
133 u32 logical_die_id;
134};
135
136/* Temporary workaround until the full topology mechanics is in place */
137static DEFINE_PER_CPU_READ_MOSTLY(struct logical_maps, logical_maps) = {
138 .phys_pkg_id = U32_MAX,
139 .phys_die_id = U32_MAX,
140};
141
142unsigned int __max_logical_packages __read_mostly;
143EXPORT_SYMBOL(__max_logical_packages);
144static unsigned int logical_packages __read_mostly;
145static unsigned int logical_die __read_mostly;
146
147/* Maximum number of SMT threads on any online core */
148int __read_mostly __max_smt_threads = 1;
149
150/* Flag to indicate if a complete sched domain rebuild is required */
151bool x86_topology_update;
152
153int arch_update_cpu_topology(void)
154{
155 int retval = x86_topology_update;
156
157 x86_topology_update = false;
158 return retval;
159}
160
161static unsigned int smpboot_warm_reset_vector_count;
162
163static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&rtc_lock, flags);
168 if (!smpboot_warm_reset_vector_count++) {
169 CMOS_WRITE(0xa, 0xf);
170 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
171 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
172 }
173 spin_unlock_irqrestore(&rtc_lock, flags);
174}
175
176static inline void smpboot_restore_warm_reset_vector(void)
177{
178 unsigned long flags;
179
180 /*
181 * Paranoid: Set warm reset code and vector here back
182 * to default values.
183 */
184 spin_lock_irqsave(&rtc_lock, flags);
185 if (!--smpboot_warm_reset_vector_count) {
186 CMOS_WRITE(0, 0xf);
187 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
188 }
189 spin_unlock_irqrestore(&rtc_lock, flags);
190
191}
192
193/* Run the next set of setup steps for the upcoming CPU */
194static void ap_starting(void)
195{
196 int cpuid = smp_processor_id();
197
198 /* Mop up eventual mwait_play_dead() wreckage */
199 this_cpu_write(mwait_cpu_dead.status, 0);
200 this_cpu_write(mwait_cpu_dead.control, 0);
201
202 /*
203 * If woken up by an INIT in an 82489DX configuration the alive
204 * synchronization guarantees that the CPU does not reach this
205 * point before an INIT_deassert IPI reaches the local APIC, so it
206 * is now safe to touch the local APIC.
207 *
208 * Set up this CPU, first the APIC, which is probably redundant on
209 * most boards.
210 */
211 apic_ap_setup();
212
213 /* Save the processor parameters. */
214 smp_store_cpu_info(cpuid);
215
216 /*
217 * The topology information must be up to date before
218 * notify_cpu_starting().
219 */
220 set_cpu_sibling_map(cpuid);
221
222 ap_init_aperfmperf();
223
224 pr_debug("Stack at about %p\n", &cpuid);
225
226 wmb();
227
228 /*
229 * This runs the AP through all the cpuhp states to its target
230 * state CPUHP_ONLINE.
231 */
232 notify_cpu_starting(cpuid);
233}
234
235static void ap_calibrate_delay(void)
236{
237 /*
238 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
239 * smp_store_cpu_info() stored a value that is close but not as
240 * accurate as the value just calculated.
241 *
242 * As this is invoked after the TSC synchronization check,
243 * calibrate_delay_is_known() will skip the calibration routine
244 * when TSC is synchronized across sockets.
245 */
246 calibrate_delay();
247 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
248}
249
250/*
251 * Activate a secondary processor.
252 */
253static void notrace start_secondary(void *unused)
254{
255 /*
256 * Don't put *anything* except direct CPU state initialization
257 * before cpu_init(), SMP booting is too fragile that we want to
258 * limit the things done here to the most necessary things.
259 */
260 cr4_init();
261
262 /*
263 * 32-bit specific. 64-bit reaches this code with the correct page
264 * table established. Yet another historical divergence.
265 */
266 if (IS_ENABLED(CONFIG_X86_32)) {
267 /* switch away from the initial page table */
268 load_cr3(swapper_pg_dir);
269 __flush_tlb_all();
270 }
271
272 cpu_init_exception_handling();
273
274 /*
275 * Load the microcode before reaching the AP alive synchronization
276 * point below so it is not part of the full per CPU serialized
277 * bringup part when "parallel" bringup is enabled.
278 *
279 * That's even safe when hyperthreading is enabled in the CPU as
280 * the core code starts the primary threads first and leaves the
281 * secondary threads waiting for SIPI. Loading microcode on
282 * physical cores concurrently is a safe operation.
283 *
284 * This covers both the Intel specific issue that concurrent
285 * microcode loading on SMT siblings must be prohibited and the
286 * vendor independent issue`that microcode loading which changes
287 * CPUID, MSRs etc. must be strictly serialized to maintain
288 * software state correctness.
289 */
290 load_ucode_ap();
291
292 /*
293 * Synchronization point with the hotplug core. Sets this CPUs
294 * synchronization state to ALIVE and spin-waits for the control CPU to
295 * release this CPU for further bringup.
296 */
297 cpuhp_ap_sync_alive();
298
299 cpu_init();
300 fpu__init_cpu();
301 rcutree_report_cpu_starting(raw_smp_processor_id());
302 x86_cpuinit.early_percpu_clock_init();
303
304 ap_starting();
305
306 /* Check TSC synchronization with the control CPU. */
307 check_tsc_sync_target();
308
309 /*
310 * Calibrate the delay loop after the TSC synchronization check.
311 * This allows to skip the calibration when TSC is synchronized
312 * across sockets.
313 */
314 ap_calibrate_delay();
315
316 speculative_store_bypass_ht_init();
317
318 /*
319 * Lock vector_lock, set CPU online and bring the vector
320 * allocator online. Online must be set with vector_lock held
321 * to prevent a concurrent irq setup/teardown from seeing a
322 * half valid vector space.
323 */
324 lock_vector_lock();
325 set_cpu_online(smp_processor_id(), true);
326 lapic_online();
327 unlock_vector_lock();
328 x86_platform.nmi_init();
329
330 /* enable local interrupts */
331 local_irq_enable();
332
333 x86_cpuinit.setup_percpu_clockev();
334
335 wmb();
336 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
337}
338
339/**
340 * topology_phys_to_logical_pkg - Map a physical package id to a logical
341 * @phys_pkg: The physical package id to map
342 *
343 * Returns logical package id or -1 if not found
344 */
345int topology_phys_to_logical_pkg(unsigned int phys_pkg)
346{
347 int cpu;
348
349 for_each_possible_cpu(cpu) {
350 if (per_cpu(logical_maps.phys_pkg_id, cpu) == phys_pkg)
351 return per_cpu(logical_maps.logical_pkg_id, cpu);
352 }
353 return -1;
354}
355EXPORT_SYMBOL(topology_phys_to_logical_pkg);
356
357/**
358 * topology_phys_to_logical_die - Map a physical die id to logical
359 * @die_id: The physical die id to map
360 * @cur_cpu: The CPU for which the mapping is done
361 *
362 * Returns logical die id or -1 if not found
363 */
364static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
365{
366 int cpu, proc_id = cpu_data(cur_cpu).topo.pkg_id;
367
368 for_each_possible_cpu(cpu) {
369 if (per_cpu(logical_maps.phys_pkg_id, cpu) == proc_id &&
370 per_cpu(logical_maps.phys_die_id, cpu) == die_id)
371 return per_cpu(logical_maps.logical_die_id, cpu);
372 }
373 return -1;
374}
375
376/**
377 * topology_update_package_map - Update the physical to logical package map
378 * @pkg: The physical package id as retrieved via CPUID
379 * @cpu: The cpu for which this is updated
380 */
381int topology_update_package_map(unsigned int pkg, unsigned int cpu)
382{
383 int new;
384
385 /* Already available somewhere? */
386 new = topology_phys_to_logical_pkg(pkg);
387 if (new >= 0)
388 goto found;
389
390 new = logical_packages++;
391 if (new != pkg) {
392 pr_info("CPU %u Converting physical %u to logical package %u\n",
393 cpu, pkg, new);
394 }
395found:
396 per_cpu(logical_maps.phys_pkg_id, cpu) = pkg;
397 per_cpu(logical_maps.logical_pkg_id, cpu) = new;
398 cpu_data(cpu).topo.logical_pkg_id = new;
399 return 0;
400}
401/**
402 * topology_update_die_map - Update the physical to logical die map
403 * @die: The die id as retrieved via CPUID
404 * @cpu: The cpu for which this is updated
405 */
406int topology_update_die_map(unsigned int die, unsigned int cpu)
407{
408 int new;
409
410 /* Already available somewhere? */
411 new = topology_phys_to_logical_die(die, cpu);
412 if (new >= 0)
413 goto found;
414
415 new = logical_die++;
416 if (new != die) {
417 pr_info("CPU %u Converting physical %u to logical die %u\n",
418 cpu, die, new);
419 }
420found:
421 per_cpu(logical_maps.phys_die_id, cpu) = die;
422 per_cpu(logical_maps.logical_die_id, cpu) = new;
423 cpu_data(cpu).topo.logical_die_id = new;
424 return 0;
425}
426
427static void __init smp_store_boot_cpu_info(void)
428{
429 int id = 0; /* CPU 0 */
430 struct cpuinfo_x86 *c = &cpu_data(id);
431
432 *c = boot_cpu_data;
433 c->cpu_index = id;
434 topology_update_package_map(c->topo.pkg_id, id);
435 topology_update_die_map(c->topo.die_id, id);
436 c->initialized = true;
437}
438
439/*
440 * The bootstrap kernel entry code has set these up. Save them for
441 * a given CPU
442 */
443void smp_store_cpu_info(int id)
444{
445 struct cpuinfo_x86 *c = &cpu_data(id);
446
447 /* Copy boot_cpu_data only on the first bringup */
448 if (!c->initialized)
449 *c = boot_cpu_data;
450 c->cpu_index = id;
451 /*
452 * During boot time, CPU0 has this setup already. Save the info when
453 * bringing up an AP.
454 */
455 identify_secondary_cpu(c);
456 c->initialized = true;
457}
458
459static bool
460topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
461{
462 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
463
464 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
465}
466
467static bool
468topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
469{
470 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
471
472 return !WARN_ONCE(!topology_same_node(c, o),
473 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
474 "[node: %d != %d]. Ignoring dependency.\n",
475 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
476}
477
478#define link_mask(mfunc, c1, c2) \
479do { \
480 cpumask_set_cpu((c1), mfunc(c2)); \
481 cpumask_set_cpu((c2), mfunc(c1)); \
482} while (0)
483
484static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
485{
486 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
487 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
488
489 if (c->topo.pkg_id == o->topo.pkg_id &&
490 c->topo.die_id == o->topo.die_id &&
491 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) {
492 if (c->topo.core_id == o->topo.core_id)
493 return topology_sane(c, o, "smt");
494
495 if ((c->topo.cu_id != 0xff) &&
496 (o->topo.cu_id != 0xff) &&
497 (c->topo.cu_id == o->topo.cu_id))
498 return topology_sane(c, o, "smt");
499 }
500
501 } else if (c->topo.pkg_id == o->topo.pkg_id &&
502 c->topo.die_id == o->topo.die_id &&
503 c->topo.core_id == o->topo.core_id) {
504 return topology_sane(c, o, "smt");
505 }
506
507 return false;
508}
509
510static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
511{
512 if (c->topo.pkg_id == o->topo.pkg_id &&
513 c->topo.die_id == o->topo.die_id)
514 return true;
515 return false;
516}
517
518static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
519{
520 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
521
522 /* If the arch didn't set up l2c_id, fall back to SMT */
523 if (per_cpu_l2c_id(cpu1) == BAD_APICID)
524 return match_smt(c, o);
525
526 /* Do not match if L2 cache id does not match: */
527 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2))
528 return false;
529
530 return topology_sane(c, o, "l2c");
531}
532
533/*
534 * Unlike the other levels, we do not enforce keeping a
535 * multicore group inside a NUMA node. If this happens, we will
536 * discard the MC level of the topology later.
537 */
538static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
539{
540 if (c->topo.pkg_id == o->topo.pkg_id)
541 return true;
542 return false;
543}
544
545/*
546 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
547 *
548 * Any Intel CPU that has multiple nodes per package and does not
549 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
550 *
551 * When in SNC mode, these CPUs enumerate an LLC that is shared
552 * by multiple NUMA nodes. The LLC is shared for off-package data
553 * access but private to the NUMA node (half of the package) for
554 * on-package access. CPUID (the source of the information about
555 * the LLC) can only enumerate the cache as shared or unshared,
556 * but not this particular configuration.
557 */
558
559static const struct x86_cpu_id intel_cod_cpu[] = {
560 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
561 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
562 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
563 {}
564};
565
566static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
567{
568 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
569 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
570 bool intel_snc = id && id->driver_data;
571
572 /* Do not match if we do not have a valid APICID for cpu: */
573 if (per_cpu_llc_id(cpu1) == BAD_APICID)
574 return false;
575
576 /* Do not match if LLC id does not match: */
577 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2))
578 return false;
579
580 /*
581 * Allow the SNC topology without warning. Return of false
582 * means 'c' does not share the LLC of 'o'. This will be
583 * reflected to userspace.
584 */
585 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
586 return false;
587
588 return topology_sane(c, o, "llc");
589}
590
591
592static inline int x86_sched_itmt_flags(void)
593{
594 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
595}
596
597#ifdef CONFIG_SCHED_MC
598static int x86_core_flags(void)
599{
600 return cpu_core_flags() | x86_sched_itmt_flags();
601}
602#endif
603#ifdef CONFIG_SCHED_SMT
604static int x86_smt_flags(void)
605{
606 return cpu_smt_flags();
607}
608#endif
609#ifdef CONFIG_SCHED_CLUSTER
610static int x86_cluster_flags(void)
611{
612 return cpu_cluster_flags() | x86_sched_itmt_flags();
613}
614#endif
615
616static int x86_die_flags(void)
617{
618 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
619 return x86_sched_itmt_flags();
620
621 return 0;
622}
623
624/*
625 * Set if a package/die has multiple NUMA nodes inside.
626 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
627 * Sub-NUMA Clustering have this.
628 */
629static bool x86_has_numa_in_package;
630
631static struct sched_domain_topology_level x86_topology[6];
632
633static void __init build_sched_topology(void)
634{
635 int i = 0;
636
637#ifdef CONFIG_SCHED_SMT
638 x86_topology[i++] = (struct sched_domain_topology_level){
639 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT)
640 };
641#endif
642#ifdef CONFIG_SCHED_CLUSTER
643 x86_topology[i++] = (struct sched_domain_topology_level){
644 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS)
645 };
646#endif
647#ifdef CONFIG_SCHED_MC
648 x86_topology[i++] = (struct sched_domain_topology_level){
649 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC)
650 };
651#endif
652 /*
653 * When there is NUMA topology inside the package skip the PKG domain
654 * since the NUMA domains will auto-magically create the right spanning
655 * domains based on the SLIT.
656 */
657 if (!x86_has_numa_in_package) {
658 x86_topology[i++] = (struct sched_domain_topology_level){
659 cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(PKG)
660 };
661 }
662
663 /*
664 * There must be one trailing NULL entry left.
665 */
666 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1);
667
668 set_sched_topology(x86_topology);
669}
670
671void set_cpu_sibling_map(int cpu)
672{
673 bool has_smt = smp_num_siblings > 1;
674 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
675 struct cpuinfo_x86 *c = &cpu_data(cpu);
676 struct cpuinfo_x86 *o;
677 int i, threads;
678
679 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
680
681 if (!has_mp) {
682 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
683 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
684 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
685 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
686 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
687 c->booted_cores = 1;
688 return;
689 }
690
691 for_each_cpu(i, cpu_sibling_setup_mask) {
692 o = &cpu_data(i);
693
694 if (match_pkg(c, o) && !topology_same_node(c, o))
695 x86_has_numa_in_package = true;
696
697 if ((i == cpu) || (has_smt && match_smt(c, o)))
698 link_mask(topology_sibling_cpumask, cpu, i);
699
700 if ((i == cpu) || (has_mp && match_llc(c, o)))
701 link_mask(cpu_llc_shared_mask, cpu, i);
702
703 if ((i == cpu) || (has_mp && match_l2c(c, o)))
704 link_mask(cpu_l2c_shared_mask, cpu, i);
705
706 if ((i == cpu) || (has_mp && match_die(c, o)))
707 link_mask(topology_die_cpumask, cpu, i);
708 }
709
710 threads = cpumask_weight(topology_sibling_cpumask(cpu));
711 if (threads > __max_smt_threads)
712 __max_smt_threads = threads;
713
714 for_each_cpu(i, topology_sibling_cpumask(cpu))
715 cpu_data(i).smt_active = threads > 1;
716
717 /*
718 * This needs a separate iteration over the cpus because we rely on all
719 * topology_sibling_cpumask links to be set-up.
720 */
721 for_each_cpu(i, cpu_sibling_setup_mask) {
722 o = &cpu_data(i);
723
724 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
725 link_mask(topology_core_cpumask, cpu, i);
726
727 /*
728 * Does this new cpu bringup a new core?
729 */
730 if (threads == 1) {
731 /*
732 * for each core in package, increment
733 * the booted_cores for this new cpu
734 */
735 if (cpumask_first(
736 topology_sibling_cpumask(i)) == i)
737 c->booted_cores++;
738 /*
739 * increment the core count for all
740 * the other cpus in this package
741 */
742 if (i != cpu)
743 cpu_data(i).booted_cores++;
744 } else if (i != cpu && !c->booted_cores)
745 c->booted_cores = cpu_data(i).booted_cores;
746 }
747 }
748}
749
750/* maps the cpu to the sched domain representing multi-core */
751const struct cpumask *cpu_coregroup_mask(int cpu)
752{
753 return cpu_llc_shared_mask(cpu);
754}
755
756const struct cpumask *cpu_clustergroup_mask(int cpu)
757{
758 return cpu_l2c_shared_mask(cpu);
759}
760EXPORT_SYMBOL_GPL(cpu_clustergroup_mask);
761
762static void impress_friends(void)
763{
764 int cpu;
765 unsigned long bogosum = 0;
766 /*
767 * Allow the user to impress friends.
768 */
769 pr_debug("Before bogomips\n");
770 for_each_online_cpu(cpu)
771 bogosum += cpu_data(cpu).loops_per_jiffy;
772
773 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
774 num_online_cpus(),
775 bogosum/(500000/HZ),
776 (bogosum/(5000/HZ))%100);
777
778 pr_debug("Before bogocount - setting activated=1\n");
779}
780
781/*
782 * The Multiprocessor Specification 1.4 (1997) example code suggests
783 * that there should be a 10ms delay between the BSP asserting INIT
784 * and de-asserting INIT, when starting a remote processor.
785 * But that slows boot and resume on modern processors, which include
786 * many cores and don't require that delay.
787 *
788 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
789 * Modern processor families are quirked to remove the delay entirely.
790 */
791#define UDELAY_10MS_DEFAULT 10000
792
793static unsigned int init_udelay = UINT_MAX;
794
795static int __init cpu_init_udelay(char *str)
796{
797 get_option(&str, &init_udelay);
798
799 return 0;
800}
801early_param("cpu_init_udelay", cpu_init_udelay);
802
803static void __init smp_quirk_init_udelay(void)
804{
805 /* if cmdline changed it from default, leave it alone */
806 if (init_udelay != UINT_MAX)
807 return;
808
809 /* if modern processor, use no delay */
810 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
811 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
812 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
813 init_udelay = 0;
814 return;
815 }
816 /* else, use legacy delay */
817 init_udelay = UDELAY_10MS_DEFAULT;
818}
819
820/*
821 * Wake up AP by INIT, INIT, STARTUP sequence.
822 */
823static void send_init_sequence(u32 phys_apicid)
824{
825 int maxlvt = lapic_get_maxlvt();
826
827 /* Be paranoid about clearing APIC errors. */
828 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
829 /* Due to the Pentium erratum 3AP. */
830 if (maxlvt > 3)
831 apic_write(APIC_ESR, 0);
832 apic_read(APIC_ESR);
833 }
834
835 /* Assert INIT on the target CPU */
836 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid);
837 safe_apic_wait_icr_idle();
838
839 udelay(init_udelay);
840
841 /* Deassert INIT on the target CPU */
842 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
843 safe_apic_wait_icr_idle();
844}
845
846/*
847 * Wake up AP by INIT, INIT, STARTUP sequence.
848 */
849static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip)
850{
851 unsigned long send_status = 0, accept_status = 0;
852 int num_starts, j, maxlvt;
853
854 preempt_disable();
855 maxlvt = lapic_get_maxlvt();
856 send_init_sequence(phys_apicid);
857
858 mb();
859
860 /*
861 * Should we send STARTUP IPIs ?
862 *
863 * Determine this based on the APIC version.
864 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
865 */
866 if (APIC_INTEGRATED(boot_cpu_apic_version))
867 num_starts = 2;
868 else
869 num_starts = 0;
870
871 /*
872 * Run STARTUP IPI loop.
873 */
874 pr_debug("#startup loops: %d\n", num_starts);
875
876 for (j = 1; j <= num_starts; j++) {
877 pr_debug("Sending STARTUP #%d\n", j);
878 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
879 apic_write(APIC_ESR, 0);
880 apic_read(APIC_ESR);
881 pr_debug("After apic_write\n");
882
883 /*
884 * STARTUP IPI
885 */
886
887 /* Target chip */
888 /* Boot on the stack */
889 /* Kick the second */
890 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
891 phys_apicid);
892
893 /*
894 * Give the other CPU some time to accept the IPI.
895 */
896 if (init_udelay == 0)
897 udelay(10);
898 else
899 udelay(300);
900
901 pr_debug("Startup point 1\n");
902
903 pr_debug("Waiting for send to finish...\n");
904 send_status = safe_apic_wait_icr_idle();
905
906 /*
907 * Give the other CPU some time to accept the IPI.
908 */
909 if (init_udelay == 0)
910 udelay(10);
911 else
912 udelay(200);
913
914 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
915 apic_write(APIC_ESR, 0);
916 accept_status = (apic_read(APIC_ESR) & 0xEF);
917 if (send_status || accept_status)
918 break;
919 }
920 pr_debug("After Startup\n");
921
922 if (send_status)
923 pr_err("APIC never delivered???\n");
924 if (accept_status)
925 pr_err("APIC delivery error (%lx)\n", accept_status);
926
927 preempt_enable();
928 return (send_status | accept_status);
929}
930
931/* reduce the number of lines printed when booting a large cpu count system */
932static void announce_cpu(int cpu, int apicid)
933{
934 static int width, node_width, first = 1;
935 static int current_node = NUMA_NO_NODE;
936 int node = early_cpu_to_node(cpu);
937
938 if (!width)
939 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
940
941 if (!node_width)
942 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
943
944 if (system_state < SYSTEM_RUNNING) {
945 if (first)
946 pr_info("x86: Booting SMP configuration:\n");
947
948 if (node != current_node) {
949 if (current_node > (-1))
950 pr_cont("\n");
951 current_node = node;
952
953 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
954 node_width - num_digits(node), " ", node);
955 }
956
957 /* Add padding for the BSP */
958 if (first)
959 pr_cont("%*s", width + 1, " ");
960 first = 0;
961
962 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
963 } else
964 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
965 node, cpu, apicid);
966}
967
968int common_cpu_up(unsigned int cpu, struct task_struct *idle)
969{
970 int ret;
971
972 /* Just in case we booted with a single CPU. */
973 alternatives_enable_smp();
974
975 per_cpu(pcpu_hot.current_task, cpu) = idle;
976 cpu_init_stack_canary(cpu, idle);
977
978 /* Initialize the interrupt stack(s) */
979 ret = irq_init_percpu_irqstack(cpu);
980 if (ret)
981 return ret;
982
983#ifdef CONFIG_X86_32
984 /* Stack for startup_32 can be just as for start_secondary onwards */
985 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle);
986#endif
987 return 0;
988}
989
990/*
991 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
992 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
993 * Returns zero if startup was successfully sent, else error code from
994 * ->wakeup_secondary_cpu.
995 */
996static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle)
997{
998 unsigned long start_ip = real_mode_header->trampoline_start;
999 int ret;
1000
1001#ifdef CONFIG_X86_64
1002 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
1003 if (apic->wakeup_secondary_cpu_64)
1004 start_ip = real_mode_header->trampoline_start64;
1005#endif
1006 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1007 initial_code = (unsigned long)start_secondary;
1008
1009 if (IS_ENABLED(CONFIG_X86_32)) {
1010 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1011 initial_stack = idle->thread.sp;
1012 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
1013 smpboot_control = cpu;
1014 }
1015
1016 /* Enable the espfix hack for this CPU */
1017 init_espfix_ap(cpu);
1018
1019 /* So we see what's up */
1020 announce_cpu(cpu, apicid);
1021
1022 /*
1023 * This grunge runs the startup process for
1024 * the targeted processor.
1025 */
1026 if (x86_platform.legacy.warm_reset) {
1027
1028 pr_debug("Setting warm reset code and vector.\n");
1029
1030 smpboot_setup_warm_reset_vector(start_ip);
1031 /*
1032 * Be paranoid about clearing APIC errors.
1033 */
1034 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1035 apic_write(APIC_ESR, 0);
1036 apic_read(APIC_ESR);
1037 }
1038 }
1039
1040 smp_mb();
1041
1042 /*
1043 * Wake up a CPU in difference cases:
1044 * - Use a method from the APIC driver if one defined, with wakeup
1045 * straight to 64-bit mode preferred over wakeup to RM.
1046 * Otherwise,
1047 * - Use an INIT boot APIC message
1048 */
1049 if (apic->wakeup_secondary_cpu_64)
1050 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip);
1051 else if (apic->wakeup_secondary_cpu)
1052 ret = apic->wakeup_secondary_cpu(apicid, start_ip);
1053 else
1054 ret = wakeup_secondary_cpu_via_init(apicid, start_ip);
1055
1056 /* If the wakeup mechanism failed, cleanup the warm reset vector */
1057 if (ret)
1058 arch_cpuhp_cleanup_kick_cpu(cpu);
1059 return ret;
1060}
1061
1062int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
1063{
1064 u32 apicid = apic->cpu_present_to_apicid(cpu);
1065 int err;
1066
1067 lockdep_assert_irqs_enabled();
1068
1069 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1070
1071 if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) ||
1072 !apic_id_valid(apicid)) {
1073 pr_err("%s: bad cpu %d\n", __func__, cpu);
1074 return -EINVAL;
1075 }
1076
1077 /*
1078 * Save current MTRR state in case it was changed since early boot
1079 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1080 */
1081 mtrr_save_state();
1082
1083 /* the FPU context is blank, nobody can own it */
1084 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1085
1086 err = common_cpu_up(cpu, tidle);
1087 if (err)
1088 return err;
1089
1090 err = do_boot_cpu(apicid, cpu, tidle);
1091 if (err)
1092 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1093
1094 return err;
1095}
1096
1097int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
1098{
1099 return smp_ops.kick_ap_alive(cpu, tidle);
1100}
1101
1102void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
1103{
1104 /* Cleanup possible dangling ends... */
1105 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
1106 smpboot_restore_warm_reset_vector();
1107}
1108
1109void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
1110{
1111 if (smp_ops.cleanup_dead_cpu)
1112 smp_ops.cleanup_dead_cpu(cpu);
1113
1114 if (system_state == SYSTEM_RUNNING)
1115 pr_info("CPU %u is now offline\n", cpu);
1116}
1117
1118void arch_cpuhp_sync_state_poll(void)
1119{
1120 if (smp_ops.poll_sync_state)
1121 smp_ops.poll_sync_state();
1122}
1123
1124/**
1125 * arch_disable_smp_support() - Disables SMP support for x86 at boottime
1126 */
1127void __init arch_disable_smp_support(void)
1128{
1129 disable_ioapic_support();
1130}
1131
1132/*
1133 * Fall back to non SMP mode after errors.
1134 *
1135 * RED-PEN audit/test this more. I bet there is more state messed up here.
1136 */
1137static __init void disable_smp(void)
1138{
1139 pr_info("SMP disabled\n");
1140
1141 disable_ioapic_support();
1142
1143 init_cpu_present(cpumask_of(0));
1144 init_cpu_possible(cpumask_of(0));
1145
1146 if (smp_found_config)
1147 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1148 else
1149 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1150 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1151 cpumask_set_cpu(0, topology_core_cpumask(0));
1152 cpumask_set_cpu(0, topology_die_cpumask(0));
1153}
1154
1155static void __init smp_cpu_index_default(void)
1156{
1157 int i;
1158 struct cpuinfo_x86 *c;
1159
1160 for_each_possible_cpu(i) {
1161 c = &cpu_data(i);
1162 /* mark all to hotplug */
1163 c->cpu_index = nr_cpu_ids;
1164 }
1165}
1166
1167void __init smp_prepare_cpus_common(void)
1168{
1169 unsigned int i;
1170
1171 smp_cpu_index_default();
1172
1173 /*
1174 * Setup boot CPU information
1175 */
1176 smp_store_boot_cpu_info(); /* Final full version of the data */
1177 mb();
1178
1179 for_each_possible_cpu(i) {
1180 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1181 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1182 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1183 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1184 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
1185 }
1186
1187 set_cpu_sibling_map(0);
1188}
1189
1190#ifdef CONFIG_X86_64
1191/* Establish whether parallel bringup can be supported. */
1192bool __init arch_cpuhp_init_parallel_bringup(void)
1193{
1194 if (!x86_cpuinit.parallel_bringup) {
1195 pr_info("Parallel CPU startup disabled by the platform\n");
1196 return false;
1197 }
1198
1199 smpboot_control = STARTUP_READ_APICID;
1200 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1201 return true;
1202}
1203#endif
1204
1205/*
1206 * Prepare for SMP bootup.
1207 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1208 * for common interface support.
1209 */
1210void __init native_smp_prepare_cpus(unsigned int max_cpus)
1211{
1212 smp_prepare_cpus_common();
1213
1214 switch (apic_intr_mode) {
1215 case APIC_PIC:
1216 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1217 disable_smp();
1218 return;
1219 case APIC_SYMMETRIC_IO_NO_ROUTING:
1220 disable_smp();
1221 /* Setup local timer */
1222 x86_init.timers.setup_percpu_clockev();
1223 return;
1224 case APIC_VIRTUAL_WIRE:
1225 case APIC_SYMMETRIC_IO:
1226 break;
1227 }
1228
1229 /* Setup local timer */
1230 x86_init.timers.setup_percpu_clockev();
1231
1232 pr_info("CPU0: ");
1233 print_cpu_info(&cpu_data(0));
1234
1235 uv_system_init();
1236
1237 smp_quirk_init_udelay();
1238
1239 speculative_store_bypass_ht_init();
1240
1241 snp_set_wakeup_secondary_cpu();
1242}
1243
1244void arch_thaw_secondary_cpus_begin(void)
1245{
1246 set_cache_aps_delayed_init(true);
1247}
1248
1249void arch_thaw_secondary_cpus_end(void)
1250{
1251 cache_aps_init();
1252}
1253
1254/*
1255 * Early setup to make printk work.
1256 */
1257void __init native_smp_prepare_boot_cpu(void)
1258{
1259 int me = smp_processor_id();
1260
1261 /* SMP handles this from setup_per_cpu_areas() */
1262 if (!IS_ENABLED(CONFIG_SMP))
1263 switch_gdt_and_percpu_base(me);
1264
1265 native_pv_lock_init();
1266}
1267
1268void __init calculate_max_logical_packages(void)
1269{
1270 int ncpus;
1271
1272 /*
1273 * Today neither Intel nor AMD support heterogeneous systems so
1274 * extrapolate the boot cpu's data to all packages.
1275 */
1276 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1277 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1278 pr_info("Max logical packages: %u\n", __max_logical_packages);
1279}
1280
1281void __init native_smp_cpus_done(unsigned int max_cpus)
1282{
1283 pr_debug("Boot done\n");
1284
1285 calculate_max_logical_packages();
1286 build_sched_topology();
1287 nmi_selftest();
1288 impress_friends();
1289 cache_aps_init();
1290}
1291
1292static int __initdata setup_possible_cpus = -1;
1293static int __init _setup_possible_cpus(char *str)
1294{
1295 get_option(&str, &setup_possible_cpus);
1296 return 0;
1297}
1298early_param("possible_cpus", _setup_possible_cpus);
1299
1300
1301/*
1302 * cpu_possible_mask should be static, it cannot change as cpu's
1303 * are onlined, or offlined. The reason is per-cpu data-structures
1304 * are allocated by some modules at init time, and don't expect to
1305 * do this dynamically on cpu arrival/departure.
1306 * cpu_present_mask on the other hand can change dynamically.
1307 * In case when cpu_hotplug is not compiled, then we resort to current
1308 * behaviour, which is cpu_possible == cpu_present.
1309 * - Ashok Raj
1310 *
1311 * Three ways to find out the number of additional hotplug CPUs:
1312 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1313 * - The user can overwrite it with possible_cpus=NUM
1314 * - Otherwise don't reserve additional CPUs.
1315 * We do this because additional CPUs waste a lot of memory.
1316 * -AK
1317 */
1318__init void prefill_possible_map(void)
1319{
1320 int i, possible;
1321
1322 i = setup_max_cpus ?: 1;
1323 if (setup_possible_cpus == -1) {
1324 possible = num_processors;
1325#ifdef CONFIG_HOTPLUG_CPU
1326 if (setup_max_cpus)
1327 possible += disabled_cpus;
1328#else
1329 if (possible > i)
1330 possible = i;
1331#endif
1332 } else
1333 possible = setup_possible_cpus;
1334
1335 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1336
1337 /* nr_cpu_ids could be reduced via nr_cpus= */
1338 if (possible > nr_cpu_ids) {
1339 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1340 possible, nr_cpu_ids);
1341 possible = nr_cpu_ids;
1342 }
1343
1344#ifdef CONFIG_HOTPLUG_CPU
1345 if (!setup_max_cpus)
1346#endif
1347 if (possible > i) {
1348 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1349 possible, setup_max_cpus);
1350 possible = i;
1351 }
1352
1353 set_nr_cpu_ids(possible);
1354
1355 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1356 possible, max_t(int, possible - num_processors, 0));
1357
1358 reset_cpu_possible_mask();
1359
1360 for (i = 0; i < possible; i++)
1361 set_cpu_possible(i, true);
1362}
1363
1364/* correctly size the local cpu masks */
1365void __init setup_cpu_local_masks(void)
1366{
1367 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
1368}
1369
1370#ifdef CONFIG_HOTPLUG_CPU
1371
1372/* Recompute SMT state for all CPUs on offline */
1373static void recompute_smt_state(void)
1374{
1375 int max_threads, cpu;
1376
1377 max_threads = 0;
1378 for_each_online_cpu (cpu) {
1379 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1380
1381 if (threads > max_threads)
1382 max_threads = threads;
1383 }
1384 __max_smt_threads = max_threads;
1385}
1386
1387static void remove_siblinginfo(int cpu)
1388{
1389 int sibling;
1390 struct cpuinfo_x86 *c = &cpu_data(cpu);
1391
1392 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1393 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1394 /*/
1395 * last thread sibling in this cpu core going down
1396 */
1397 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1398 cpu_data(sibling).booted_cores--;
1399 }
1400
1401 for_each_cpu(sibling, topology_die_cpumask(cpu))
1402 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1403
1404 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1405 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1406 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1407 cpu_data(sibling).smt_active = false;
1408 }
1409
1410 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1411 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1412 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1413 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1414 cpumask_clear(cpu_llc_shared_mask(cpu));
1415 cpumask_clear(cpu_l2c_shared_mask(cpu));
1416 cpumask_clear(topology_sibling_cpumask(cpu));
1417 cpumask_clear(topology_core_cpumask(cpu));
1418 cpumask_clear(topology_die_cpumask(cpu));
1419 c->topo.core_id = 0;
1420 c->booted_cores = 0;
1421 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1422 recompute_smt_state();
1423}
1424
1425static void remove_cpu_from_maps(int cpu)
1426{
1427 set_cpu_online(cpu, false);
1428 numa_remove_cpu(cpu);
1429}
1430
1431void cpu_disable_common(void)
1432{
1433 int cpu = smp_processor_id();
1434
1435 remove_siblinginfo(cpu);
1436
1437 /* It's now safe to remove this processor from the online map */
1438 lock_vector_lock();
1439 remove_cpu_from_maps(cpu);
1440 unlock_vector_lock();
1441 fixup_irqs();
1442 lapic_offline();
1443}
1444
1445int native_cpu_disable(void)
1446{
1447 int ret;
1448
1449 ret = lapic_can_unplug_cpu();
1450 if (ret)
1451 return ret;
1452
1453 cpu_disable_common();
1454
1455 /*
1456 * Disable the local APIC. Otherwise IPI broadcasts will reach
1457 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1458 * messages.
1459 *
1460 * Disabling the APIC must happen after cpu_disable_common()
1461 * which invokes fixup_irqs().
1462 *
1463 * Disabling the APIC preserves already set bits in IRR, but
1464 * an interrupt arriving after disabling the local APIC does not
1465 * set the corresponding IRR bit.
1466 *
1467 * fixup_irqs() scans IRR for set bits so it can raise a not
1468 * yet handled interrupt on the new destination CPU via an IPI
1469 * but obviously it can't do so for IRR bits which are not set.
1470 * IOW, interrupts arriving after disabling the local APIC will
1471 * be lost.
1472 */
1473 apic_soft_disable();
1474
1475 return 0;
1476}
1477
1478void play_dead_common(void)
1479{
1480 idle_task_exit();
1481
1482 cpuhp_ap_report_dead();
1483
1484 local_irq_disable();
1485}
1486
1487/*
1488 * We need to flush the caches before going to sleep, lest we have
1489 * dirty data in our caches when we come back up.
1490 */
1491static inline void mwait_play_dead(void)
1492{
1493 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1494 unsigned int eax, ebx, ecx, edx;
1495 unsigned int highest_cstate = 0;
1496 unsigned int highest_subcstate = 0;
1497 int i;
1498
1499 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1500 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1501 return;
1502 if (!this_cpu_has(X86_FEATURE_MWAIT))
1503 return;
1504 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1505 return;
1506 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1507 return;
1508
1509 eax = CPUID_MWAIT_LEAF;
1510 ecx = 0;
1511 native_cpuid(&eax, &ebx, &ecx, &edx);
1512
1513 /*
1514 * eax will be 0 if EDX enumeration is not valid.
1515 * Initialized below to cstate, sub_cstate value when EDX is valid.
1516 */
1517 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1518 eax = 0;
1519 } else {
1520 edx >>= MWAIT_SUBSTATE_SIZE;
1521 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1522 if (edx & MWAIT_SUBSTATE_MASK) {
1523 highest_cstate = i;
1524 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1525 }
1526 }
1527 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1528 (highest_subcstate - 1);
1529 }
1530
1531 /* Set up state for the kexec() hack below */
1532 md->status = CPUDEAD_MWAIT_WAIT;
1533 md->control = CPUDEAD_MWAIT_WAIT;
1534
1535 wbinvd();
1536
1537 while (1) {
1538 /*
1539 * The CLFLUSH is a workaround for erratum AAI65 for
1540 * the Xeon 7400 series. It's not clear it is actually
1541 * needed, but it should be harmless in either case.
1542 * The WBINVD is insufficient due to the spurious-wakeup
1543 * case where we return around the loop.
1544 */
1545 mb();
1546 clflush(md);
1547 mb();
1548 __monitor(md, 0, 0);
1549 mb();
1550 __mwait(eax, 0);
1551
1552 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1553 /*
1554 * Kexec is about to happen. Don't go back into mwait() as
1555 * the kexec kernel might overwrite text and data including
1556 * page tables and stack. So mwait() would resume when the
1557 * monitor cache line is written to and then the CPU goes
1558 * south due to overwritten text, page tables and stack.
1559 *
1560 * Note: This does _NOT_ protect against a stray MCE, NMI,
1561 * SMI. They will resume execution at the instruction
1562 * following the HLT instruction and run into the problem
1563 * which this is trying to prevent.
1564 */
1565 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1566 while(1)
1567 native_halt();
1568 }
1569 }
1570}
1571
1572/*
1573 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1574 * mwait_play_dead().
1575 */
1576void smp_kick_mwait_play_dead(void)
1577{
1578 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1579 struct mwait_cpu_dead *md;
1580 unsigned int cpu, i;
1581
1582 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1583 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1584
1585 /* Does it sit in mwait_play_dead() ? */
1586 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1587 continue;
1588
1589 /* Wait up to 5ms */
1590 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1591 /* Bring it out of mwait */
1592 WRITE_ONCE(md->control, newstate);
1593 udelay(5);
1594 }
1595
1596 if (READ_ONCE(md->status) != newstate)
1597 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1598 }
1599}
1600
1601void __noreturn hlt_play_dead(void)
1602{
1603 if (__this_cpu_read(cpu_info.x86) >= 4)
1604 wbinvd();
1605
1606 while (1)
1607 native_halt();
1608}
1609
1610/*
1611 * native_play_dead() is essentially a __noreturn function, but it can't
1612 * be marked as such as the compiler may complain about it.
1613 */
1614void native_play_dead(void)
1615{
1616 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
1617 __update_spec_ctrl(0);
1618
1619 play_dead_common();
1620 tboot_shutdown(TB_SHUTDOWN_WFS);
1621
1622 mwait_play_dead();
1623 if (cpuidle_play_dead())
1624 hlt_play_dead();
1625}
1626
1627#else /* ... !CONFIG_HOTPLUG_CPU */
1628int native_cpu_disable(void)
1629{
1630 return -ENOSYS;
1631}
1632
1633void native_play_dead(void)
1634{
1635 BUG();
1636}
1637
1638#endif
1/*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/module.h>
45#include <linux/sched.h>
46#include <linux/percpu.h>
47#include <linux/bootmem.h>
48#include <linux/err.h>
49#include <linux/nmi.h>
50#include <linux/tboot.h>
51#include <linux/stackprotector.h>
52#include <linux/gfp.h>
53#include <linux/cpuidle.h>
54
55#include <asm/acpi.h>
56#include <asm/desc.h>
57#include <asm/nmi.h>
58#include <asm/irq.h>
59#include <asm/idle.h>
60#include <asm/realmode.h>
61#include <asm/cpu.h>
62#include <asm/numa.h>
63#include <asm/pgtable.h>
64#include <asm/tlbflush.h>
65#include <asm/mtrr.h>
66#include <asm/mwait.h>
67#include <asm/apic.h>
68#include <asm/io_apic.h>
69#include <asm/setup.h>
70#include <asm/uv/uv.h>
71#include <linux/mc146818rtc.h>
72
73#include <asm/smpboot_hooks.h>
74#include <asm/i8259.h>
75
76#include <asm/realmode.h>
77
78/* State of each CPU */
79DEFINE_PER_CPU(int, cpu_state) = { 0 };
80
81#ifdef CONFIG_HOTPLUG_CPU
82/*
83 * We need this for trampoline_base protection from concurrent accesses when
84 * off- and onlining cores wildly.
85 */
86static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
87
88void cpu_hotplug_driver_lock(void)
89{
90 mutex_lock(&x86_cpu_hotplug_driver_mutex);
91}
92
93void cpu_hotplug_driver_unlock(void)
94{
95 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
96}
97
98ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
99ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
100#endif
101
102/* Number of siblings per CPU package */
103int smp_num_siblings = 1;
104EXPORT_SYMBOL(smp_num_siblings);
105
106/* Last level cache ID of each logical CPU */
107DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
108
109/* representing HT siblings of each logical CPU */
110DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
111EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
112
113/* representing HT and core siblings of each logical CPU */
114DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
115EXPORT_PER_CPU_SYMBOL(cpu_core_map);
116
117DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
118
119/* Per CPU bogomips and other parameters */
120DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
121EXPORT_PER_CPU_SYMBOL(cpu_info);
122
123atomic_t init_deasserted;
124
125/*
126 * Report back to the Boot Processor.
127 * Running on AP.
128 */
129static void __cpuinit smp_callin(void)
130{
131 int cpuid, phys_id;
132 unsigned long timeout;
133
134 /*
135 * If waken up by an INIT in an 82489DX configuration
136 * we may get here before an INIT-deassert IPI reaches
137 * our local APIC. We have to wait for the IPI or we'll
138 * lock up on an APIC access.
139 */
140 if (apic->wait_for_init_deassert)
141 apic->wait_for_init_deassert(&init_deasserted);
142
143 /*
144 * (This works even if the APIC is not enabled.)
145 */
146 phys_id = read_apic_id();
147 cpuid = smp_processor_id();
148 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
149 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
150 phys_id, cpuid);
151 }
152 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
153
154 /*
155 * STARTUP IPIs are fragile beasts as they might sometimes
156 * trigger some glue motherboard logic. Complete APIC bus
157 * silence for 1 second, this overestimates the time the
158 * boot CPU is spending to send the up to 2 STARTUP IPIs
159 * by a factor of two. This should be enough.
160 */
161
162 /*
163 * Waiting 2s total for startup (udelay is not yet working)
164 */
165 timeout = jiffies + 2*HZ;
166 while (time_before(jiffies, timeout)) {
167 /*
168 * Has the boot CPU finished it's STARTUP sequence?
169 */
170 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
171 break;
172 cpu_relax();
173 }
174
175 if (!time_before(jiffies, timeout)) {
176 panic("%s: CPU%d started up but did not get a callout!\n",
177 __func__, cpuid);
178 }
179
180 /*
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
184 * boards)
185 */
186
187 pr_debug("CALLIN, before setup_local_APIC().\n");
188 if (apic->smp_callin_clear_local_apic)
189 apic->smp_callin_clear_local_apic();
190 setup_local_APIC();
191 end_local_APIC_setup();
192
193 /*
194 * Need to setup vector mappings before we enable interrupts.
195 */
196 setup_vector_irq(smp_processor_id());
197
198 /*
199 * Save our processor parameters. Note: this information
200 * is needed for clock calibration.
201 */
202 smp_store_cpu_info(cpuid);
203
204 /*
205 * Get our bogomips.
206 * Update loops_per_jiffy in cpu_data. Previous call to
207 * smp_store_cpu_info() stored a value that is close but not as
208 * accurate as the value just calculated.
209 */
210 calibrate_delay();
211 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
212 pr_debug("Stack at about %p\n", &cpuid);
213
214 /*
215 * This must be done before setting cpu_online_mask
216 * or calling notify_cpu_starting.
217 */
218 set_cpu_sibling_map(raw_smp_processor_id());
219 wmb();
220
221 notify_cpu_starting(cpuid);
222
223 /*
224 * Allow the master to continue.
225 */
226 cpumask_set_cpu(cpuid, cpu_callin_mask);
227}
228
229/*
230 * Activate a secondary processor.
231 */
232notrace static void __cpuinit start_secondary(void *unused)
233{
234 /*
235 * Don't put *anything* before cpu_init(), SMP booting is too
236 * fragile that we want to limit the things done here to the
237 * most necessary things.
238 */
239 cpu_init();
240 x86_cpuinit.early_percpu_clock_init();
241 preempt_disable();
242 smp_callin();
243
244#ifdef CONFIG_X86_32
245 /* switch away from the initial page table */
246 load_cr3(swapper_pg_dir);
247 __flush_tlb_all();
248#endif
249
250 /* otherwise gcc will move up smp_processor_id before the cpu_init */
251 barrier();
252 /*
253 * Check TSC synchronization with the BP:
254 */
255 check_tsc_sync_target();
256
257 /*
258 * We need to hold call_lock, so there is no inconsistency
259 * between the time smp_call_function() determines number of
260 * IPI recipients, and the time when the determination is made
261 * for which cpus receive the IPI. Holding this
262 * lock helps us to not include this cpu in a currently in progress
263 * smp_call_function().
264 *
265 * We need to hold vector_lock so there the set of online cpus
266 * does not change while we are assigning vectors to cpus. Holding
267 * this lock ensures we don't half assign or remove an irq from a cpu.
268 */
269 ipi_call_lock();
270 lock_vector_lock();
271 set_cpu_online(smp_processor_id(), true);
272 unlock_vector_lock();
273 ipi_call_unlock();
274 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
275 x86_platform.nmi_init();
276
277 /* enable local interrupts */
278 local_irq_enable();
279
280 /* to prevent fake stack check failure in clock setup */
281 boot_init_stack_canary();
282
283 x86_cpuinit.setup_percpu_clockev();
284
285 wmb();
286 cpu_idle();
287}
288
289/*
290 * The bootstrap kernel entry code has set these up. Save them for
291 * a given CPU
292 */
293
294void __cpuinit smp_store_cpu_info(int id)
295{
296 struct cpuinfo_x86 *c = &cpu_data(id);
297
298 *c = boot_cpu_data;
299 c->cpu_index = id;
300 if (id != 0)
301 identify_secondary_cpu(c);
302}
303
304static bool __cpuinit
305topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
306{
307 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
308
309 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
310 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
311 "[node: %d != %d]. Ignoring dependency.\n",
312 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
313}
314
315#define link_mask(_m, c1, c2) \
316do { \
317 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
318 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
319} while (0)
320
321static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
322{
323 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
324 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
325
326 if (c->phys_proc_id == o->phys_proc_id &&
327 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
328 c->compute_unit_id == o->compute_unit_id)
329 return topology_sane(c, o, "smt");
330
331 } else if (c->phys_proc_id == o->phys_proc_id &&
332 c->cpu_core_id == o->cpu_core_id) {
333 return topology_sane(c, o, "smt");
334 }
335
336 return false;
337}
338
339static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
340{
341 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
342
343 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
344 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
345 return topology_sane(c, o, "llc");
346
347 return false;
348}
349
350static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
351{
352 if (c->phys_proc_id == o->phys_proc_id) {
353 if (cpu_has(c, X86_FEATURE_AMD_DCM))
354 return true;
355
356 return topology_sane(c, o, "mc");
357 }
358 return false;
359}
360
361void __cpuinit set_cpu_sibling_map(int cpu)
362{
363 bool has_mc = boot_cpu_data.x86_max_cores > 1;
364 bool has_smt = smp_num_siblings > 1;
365 struct cpuinfo_x86 *c = &cpu_data(cpu);
366 struct cpuinfo_x86 *o;
367 int i;
368
369 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
370
371 if (!has_smt && !has_mc) {
372 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
373 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
374 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
375 c->booted_cores = 1;
376 return;
377 }
378
379 for_each_cpu(i, cpu_sibling_setup_mask) {
380 o = &cpu_data(i);
381
382 if ((i == cpu) || (has_smt && match_smt(c, o)))
383 link_mask(sibling, cpu, i);
384
385 if ((i == cpu) || (has_mc && match_llc(c, o)))
386 link_mask(llc_shared, cpu, i);
387
388 }
389
390 /*
391 * This needs a separate iteration over the cpus because we rely on all
392 * cpu_sibling_mask links to be set-up.
393 */
394 for_each_cpu(i, cpu_sibling_setup_mask) {
395 o = &cpu_data(i);
396
397 if ((i == cpu) || (has_mc && match_mc(c, o))) {
398 link_mask(core, cpu, i);
399
400 /*
401 * Does this new cpu bringup a new core?
402 */
403 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
404 /*
405 * for each core in package, increment
406 * the booted_cores for this new cpu
407 */
408 if (cpumask_first(cpu_sibling_mask(i)) == i)
409 c->booted_cores++;
410 /*
411 * increment the core count for all
412 * the other cpus in this package
413 */
414 if (i != cpu)
415 cpu_data(i).booted_cores++;
416 } else if (i != cpu && !c->booted_cores)
417 c->booted_cores = cpu_data(i).booted_cores;
418 }
419 }
420}
421
422/* maps the cpu to the sched domain representing multi-core */
423const struct cpumask *cpu_coregroup_mask(int cpu)
424{
425 return cpu_llc_shared_mask(cpu);
426}
427
428static void impress_friends(void)
429{
430 int cpu;
431 unsigned long bogosum = 0;
432 /*
433 * Allow the user to impress friends.
434 */
435 pr_debug("Before bogomips.\n");
436 for_each_possible_cpu(cpu)
437 if (cpumask_test_cpu(cpu, cpu_callout_mask))
438 bogosum += cpu_data(cpu).loops_per_jiffy;
439 printk(KERN_INFO
440 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
441 num_online_cpus(),
442 bogosum/(500000/HZ),
443 (bogosum/(5000/HZ))%100);
444
445 pr_debug("Before bogocount - setting activated=1.\n");
446}
447
448void __inquire_remote_apic(int apicid)
449{
450 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
451 const char * const names[] = { "ID", "VERSION", "SPIV" };
452 int timeout;
453 u32 status;
454
455 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
456
457 for (i = 0; i < ARRAY_SIZE(regs); i++) {
458 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
459
460 /*
461 * Wait for idle.
462 */
463 status = safe_apic_wait_icr_idle();
464 if (status)
465 printk(KERN_CONT
466 "a previous APIC delivery may have failed\n");
467
468 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
469
470 timeout = 0;
471 do {
472 udelay(100);
473 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
474 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
475
476 switch (status) {
477 case APIC_ICR_RR_VALID:
478 status = apic_read(APIC_RRR);
479 printk(KERN_CONT "%08x\n", status);
480 break;
481 default:
482 printk(KERN_CONT "failed\n");
483 }
484 }
485}
486
487/*
488 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
489 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
490 * won't ... remember to clear down the APIC, etc later.
491 */
492int __cpuinit
493wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
494{
495 unsigned long send_status, accept_status = 0;
496 int maxlvt;
497
498 /* Target chip */
499 /* Boot on the stack */
500 /* Kick the second */
501 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
502
503 pr_debug("Waiting for send to finish...\n");
504 send_status = safe_apic_wait_icr_idle();
505
506 /*
507 * Give the other CPU some time to accept the IPI.
508 */
509 udelay(200);
510 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
511 maxlvt = lapic_get_maxlvt();
512 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
513 apic_write(APIC_ESR, 0);
514 accept_status = (apic_read(APIC_ESR) & 0xEF);
515 }
516 pr_debug("NMI sent.\n");
517
518 if (send_status)
519 printk(KERN_ERR "APIC never delivered???\n");
520 if (accept_status)
521 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
522
523 return (send_status | accept_status);
524}
525
526static int __cpuinit
527wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
528{
529 unsigned long send_status, accept_status = 0;
530 int maxlvt, num_starts, j;
531
532 maxlvt = lapic_get_maxlvt();
533
534 /*
535 * Be paranoid about clearing APIC errors.
536 */
537 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
538 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
539 apic_write(APIC_ESR, 0);
540 apic_read(APIC_ESR);
541 }
542
543 pr_debug("Asserting INIT.\n");
544
545 /*
546 * Turn INIT on target chip
547 */
548 /*
549 * Send IPI
550 */
551 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
552 phys_apicid);
553
554 pr_debug("Waiting for send to finish...\n");
555 send_status = safe_apic_wait_icr_idle();
556
557 mdelay(10);
558
559 pr_debug("Deasserting INIT.\n");
560
561 /* Target chip */
562 /* Send IPI */
563 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
564
565 pr_debug("Waiting for send to finish...\n");
566 send_status = safe_apic_wait_icr_idle();
567
568 mb();
569 atomic_set(&init_deasserted, 1);
570
571 /*
572 * Should we send STARTUP IPIs ?
573 *
574 * Determine this based on the APIC version.
575 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
576 */
577 if (APIC_INTEGRATED(apic_version[phys_apicid]))
578 num_starts = 2;
579 else
580 num_starts = 0;
581
582 /*
583 * Paravirt / VMI wants a startup IPI hook here to set up the
584 * target processor state.
585 */
586 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
587 stack_start);
588
589 /*
590 * Run STARTUP IPI loop.
591 */
592 pr_debug("#startup loops: %d.\n", num_starts);
593
594 for (j = 1; j <= num_starts; j++) {
595 pr_debug("Sending STARTUP #%d.\n", j);
596 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
597 apic_write(APIC_ESR, 0);
598 apic_read(APIC_ESR);
599 pr_debug("After apic_write.\n");
600
601 /*
602 * STARTUP IPI
603 */
604
605 /* Target chip */
606 /* Boot on the stack */
607 /* Kick the second */
608 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
609 phys_apicid);
610
611 /*
612 * Give the other CPU some time to accept the IPI.
613 */
614 udelay(300);
615
616 pr_debug("Startup point 1.\n");
617
618 pr_debug("Waiting for send to finish...\n");
619 send_status = safe_apic_wait_icr_idle();
620
621 /*
622 * Give the other CPU some time to accept the IPI.
623 */
624 udelay(200);
625 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
626 apic_write(APIC_ESR, 0);
627 accept_status = (apic_read(APIC_ESR) & 0xEF);
628 if (send_status || accept_status)
629 break;
630 }
631 pr_debug("After Startup.\n");
632
633 if (send_status)
634 printk(KERN_ERR "APIC never delivered???\n");
635 if (accept_status)
636 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
637
638 return (send_status | accept_status);
639}
640
641/* reduce the number of lines printed when booting a large cpu count system */
642static void __cpuinit announce_cpu(int cpu, int apicid)
643{
644 static int current_node = -1;
645 int node = early_cpu_to_node(cpu);
646
647 if (system_state == SYSTEM_BOOTING) {
648 if (node != current_node) {
649 if (current_node > (-1))
650 pr_cont(" Ok.\n");
651 current_node = node;
652 pr_info("Booting Node %3d, Processors ", node);
653 }
654 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
655 return;
656 } else
657 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
658 node, cpu, apicid);
659}
660
661/*
662 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
663 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
664 * Returns zero if CPU booted OK, else error code from
665 * ->wakeup_secondary_cpu.
666 */
667static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
668{
669 volatile u32 *trampoline_status =
670 (volatile u32 *) __va(real_mode_header->trampoline_status);
671 /* start_ip had better be page-aligned! */
672 unsigned long start_ip = real_mode_header->trampoline_start;
673
674 unsigned long boot_error = 0;
675 int timeout;
676
677 alternatives_smp_switch(1);
678
679 idle->thread.sp = (unsigned long) (((struct pt_regs *)
680 (THREAD_SIZE + task_stack_page(idle))) - 1);
681 per_cpu(current_task, cpu) = idle;
682
683#ifdef CONFIG_X86_32
684 /* Stack for startup_32 can be just as for start_secondary onwards */
685 irq_ctx_init(cpu);
686#else
687 clear_tsk_thread_flag(idle, TIF_FORK);
688 initial_gs = per_cpu_offset(cpu);
689 per_cpu(kernel_stack, cpu) =
690 (unsigned long)task_stack_page(idle) -
691 KERNEL_STACK_OFFSET + THREAD_SIZE;
692#endif
693 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
694 initial_code = (unsigned long)start_secondary;
695 stack_start = idle->thread.sp;
696
697 /* So we see what's up */
698 announce_cpu(cpu, apicid);
699
700 /*
701 * This grunge runs the startup process for
702 * the targeted processor.
703 */
704
705 atomic_set(&init_deasserted, 0);
706
707 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
708
709 pr_debug("Setting warm reset code and vector.\n");
710
711 smpboot_setup_warm_reset_vector(start_ip);
712 /*
713 * Be paranoid about clearing APIC errors.
714 */
715 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
716 apic_write(APIC_ESR, 0);
717 apic_read(APIC_ESR);
718 }
719 }
720
721 /*
722 * Kick the secondary CPU. Use the method in the APIC driver
723 * if it's defined - or use an INIT boot APIC message otherwise:
724 */
725 if (apic->wakeup_secondary_cpu)
726 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
727 else
728 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
729
730 if (!boot_error) {
731 /*
732 * allow APs to start initializing.
733 */
734 pr_debug("Before Callout %d.\n", cpu);
735 cpumask_set_cpu(cpu, cpu_callout_mask);
736 pr_debug("After Callout %d.\n", cpu);
737
738 /*
739 * Wait 5s total for a response
740 */
741 for (timeout = 0; timeout < 50000; timeout++) {
742 if (cpumask_test_cpu(cpu, cpu_callin_mask))
743 break; /* It has booted */
744 udelay(100);
745 /*
746 * Allow other tasks to run while we wait for the
747 * AP to come online. This also gives a chance
748 * for the MTRR work(triggered by the AP coming online)
749 * to be completed in the stop machine context.
750 */
751 schedule();
752 }
753
754 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
755 print_cpu_msr(&cpu_data(cpu));
756 pr_debug("CPU%d: has booted.\n", cpu);
757 } else {
758 boot_error = 1;
759 if (*trampoline_status == 0xA5A5A5A5)
760 /* trampoline started but...? */
761 pr_err("CPU%d: Stuck ??\n", cpu);
762 else
763 /* trampoline code not run */
764 pr_err("CPU%d: Not responding.\n", cpu);
765 if (apic->inquire_remote_apic)
766 apic->inquire_remote_apic(apicid);
767 }
768 }
769
770 if (boot_error) {
771 /* Try to put things back the way they were before ... */
772 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
773
774 /* was set by do_boot_cpu() */
775 cpumask_clear_cpu(cpu, cpu_callout_mask);
776
777 /* was set by cpu_init() */
778 cpumask_clear_cpu(cpu, cpu_initialized_mask);
779
780 set_cpu_present(cpu, false);
781 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
782 }
783
784 /* mark "stuck" area as not stuck */
785 *trampoline_status = 0;
786
787 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
788 /*
789 * Cleanup possible dangling ends...
790 */
791 smpboot_restore_warm_reset_vector();
792 }
793 return boot_error;
794}
795
796int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle)
797{
798 int apicid = apic->cpu_present_to_apicid(cpu);
799 unsigned long flags;
800 int err;
801
802 WARN_ON(irqs_disabled());
803
804 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
805
806 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
807 !physid_isset(apicid, phys_cpu_present_map) ||
808 !apic->apic_id_valid(apicid)) {
809 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
810 return -EINVAL;
811 }
812
813 /*
814 * Already booted CPU?
815 */
816 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
817 pr_debug("do_boot_cpu %d Already started\n", cpu);
818 return -ENOSYS;
819 }
820
821 /*
822 * Save current MTRR state in case it was changed since early boot
823 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
824 */
825 mtrr_save_state();
826
827 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
828
829 err = do_boot_cpu(apicid, cpu, tidle);
830 if (err) {
831 pr_debug("do_boot_cpu failed %d\n", err);
832 return -EIO;
833 }
834
835 /*
836 * Check TSC synchronization with the AP (keep irqs disabled
837 * while doing so):
838 */
839 local_irq_save(flags);
840 check_tsc_sync_source(cpu);
841 local_irq_restore(flags);
842
843 while (!cpu_online(cpu)) {
844 cpu_relax();
845 touch_nmi_watchdog();
846 }
847
848 return 0;
849}
850
851/**
852 * arch_disable_smp_support() - disables SMP support for x86 at runtime
853 */
854void arch_disable_smp_support(void)
855{
856 disable_ioapic_support();
857}
858
859/*
860 * Fall back to non SMP mode after errors.
861 *
862 * RED-PEN audit/test this more. I bet there is more state messed up here.
863 */
864static __init void disable_smp(void)
865{
866 init_cpu_present(cpumask_of(0));
867 init_cpu_possible(cpumask_of(0));
868 smpboot_clear_io_apic_irqs();
869
870 if (smp_found_config)
871 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
872 else
873 physid_set_mask_of_physid(0, &phys_cpu_present_map);
874 cpumask_set_cpu(0, cpu_sibling_mask(0));
875 cpumask_set_cpu(0, cpu_core_mask(0));
876}
877
878/*
879 * Various sanity checks.
880 */
881static int __init smp_sanity_check(unsigned max_cpus)
882{
883 preempt_disable();
884
885#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
886 if (def_to_bigsmp && nr_cpu_ids > 8) {
887 unsigned int cpu;
888 unsigned nr;
889
890 printk(KERN_WARNING
891 "More than 8 CPUs detected - skipping them.\n"
892 "Use CONFIG_X86_BIGSMP.\n");
893
894 nr = 0;
895 for_each_present_cpu(cpu) {
896 if (nr >= 8)
897 set_cpu_present(cpu, false);
898 nr++;
899 }
900
901 nr = 0;
902 for_each_possible_cpu(cpu) {
903 if (nr >= 8)
904 set_cpu_possible(cpu, false);
905 nr++;
906 }
907
908 nr_cpu_ids = 8;
909 }
910#endif
911
912 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
913 printk(KERN_WARNING
914 "weird, boot CPU (#%d) not listed by the BIOS.\n",
915 hard_smp_processor_id());
916
917 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
918 }
919
920 /*
921 * If we couldn't find an SMP configuration at boot time,
922 * get out of here now!
923 */
924 if (!smp_found_config && !acpi_lapic) {
925 preempt_enable();
926 printk(KERN_NOTICE "SMP motherboard not detected.\n");
927 disable_smp();
928 if (APIC_init_uniprocessor())
929 printk(KERN_NOTICE "Local APIC not detected."
930 " Using dummy APIC emulation.\n");
931 return -1;
932 }
933
934 /*
935 * Should not be necessary because the MP table should list the boot
936 * CPU too, but we do it for the sake of robustness anyway.
937 */
938 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
939 printk(KERN_NOTICE
940 "weird, boot CPU (#%d) not listed by the BIOS.\n",
941 boot_cpu_physical_apicid);
942 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
943 }
944 preempt_enable();
945
946 /*
947 * If we couldn't find a local APIC, then get out of here now!
948 */
949 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
950 !cpu_has_apic) {
951 if (!disable_apic) {
952 pr_err("BIOS bug, local APIC #%d not detected!...\n",
953 boot_cpu_physical_apicid);
954 pr_err("... forcing use of dummy APIC emulation."
955 "(tell your hw vendor)\n");
956 }
957 smpboot_clear_io_apic();
958 disable_ioapic_support();
959 return -1;
960 }
961
962 verify_local_APIC();
963
964 /*
965 * If SMP should be disabled, then really disable it!
966 */
967 if (!max_cpus) {
968 printk(KERN_INFO "SMP mode deactivated.\n");
969 smpboot_clear_io_apic();
970
971 connect_bsp_APIC();
972 setup_local_APIC();
973 bsp_end_local_APIC_setup();
974 return -1;
975 }
976
977 return 0;
978}
979
980static void __init smp_cpu_index_default(void)
981{
982 int i;
983 struct cpuinfo_x86 *c;
984
985 for_each_possible_cpu(i) {
986 c = &cpu_data(i);
987 /* mark all to hotplug */
988 c->cpu_index = nr_cpu_ids;
989 }
990}
991
992/*
993 * Prepare for SMP bootup. The MP table or ACPI has been read
994 * earlier. Just do some sanity checking here and enable APIC mode.
995 */
996void __init native_smp_prepare_cpus(unsigned int max_cpus)
997{
998 unsigned int i;
999
1000 preempt_disable();
1001 smp_cpu_index_default();
1002
1003 /*
1004 * Setup boot CPU information
1005 */
1006 smp_store_cpu_info(0); /* Final full version of the data */
1007 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1008 mb();
1009
1010 current_thread_info()->cpu = 0; /* needed? */
1011 for_each_possible_cpu(i) {
1012 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1013 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1014 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1015 }
1016 set_cpu_sibling_map(0);
1017
1018
1019 if (smp_sanity_check(max_cpus) < 0) {
1020 printk(KERN_INFO "SMP disabled\n");
1021 disable_smp();
1022 goto out;
1023 }
1024
1025 default_setup_apic_routing();
1026
1027 preempt_disable();
1028 if (read_apic_id() != boot_cpu_physical_apicid) {
1029 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1030 read_apic_id(), boot_cpu_physical_apicid);
1031 /* Or can we switch back to PIC here? */
1032 }
1033 preempt_enable();
1034
1035 connect_bsp_APIC();
1036
1037 /*
1038 * Switch from PIC to APIC mode.
1039 */
1040 setup_local_APIC();
1041
1042 /*
1043 * Enable IO APIC before setting up error vector
1044 */
1045 if (!skip_ioapic_setup && nr_ioapics)
1046 enable_IO_APIC();
1047
1048 bsp_end_local_APIC_setup();
1049
1050 if (apic->setup_portio_remap)
1051 apic->setup_portio_remap();
1052
1053 smpboot_setup_io_apic();
1054 /*
1055 * Set up local APIC timer on boot CPU.
1056 */
1057
1058 printk(KERN_INFO "CPU%d: ", 0);
1059 print_cpu_info(&cpu_data(0));
1060 x86_init.timers.setup_percpu_clockev();
1061
1062 if (is_uv_system())
1063 uv_system_init();
1064
1065 set_mtrr_aps_delayed_init();
1066out:
1067 preempt_enable();
1068}
1069
1070void arch_disable_nonboot_cpus_begin(void)
1071{
1072 /*
1073 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1074 * In the suspend path, we will be back in the SMP mode shortly anyways.
1075 */
1076 skip_smp_alternatives = true;
1077}
1078
1079void arch_disable_nonboot_cpus_end(void)
1080{
1081 skip_smp_alternatives = false;
1082}
1083
1084void arch_enable_nonboot_cpus_begin(void)
1085{
1086 set_mtrr_aps_delayed_init();
1087}
1088
1089void arch_enable_nonboot_cpus_end(void)
1090{
1091 mtrr_aps_init();
1092}
1093
1094/*
1095 * Early setup to make printk work.
1096 */
1097void __init native_smp_prepare_boot_cpu(void)
1098{
1099 int me = smp_processor_id();
1100 switch_to_new_gdt(me);
1101 /* already set me in cpu_online_mask in boot_cpu_init() */
1102 cpumask_set_cpu(me, cpu_callout_mask);
1103 per_cpu(cpu_state, me) = CPU_ONLINE;
1104}
1105
1106void __init native_smp_cpus_done(unsigned int max_cpus)
1107{
1108 pr_debug("Boot done.\n");
1109
1110 nmi_selftest();
1111 impress_friends();
1112#ifdef CONFIG_X86_IO_APIC
1113 setup_ioapic_dest();
1114#endif
1115 mtrr_aps_init();
1116}
1117
1118static int __initdata setup_possible_cpus = -1;
1119static int __init _setup_possible_cpus(char *str)
1120{
1121 get_option(&str, &setup_possible_cpus);
1122 return 0;
1123}
1124early_param("possible_cpus", _setup_possible_cpus);
1125
1126
1127/*
1128 * cpu_possible_mask should be static, it cannot change as cpu's
1129 * are onlined, or offlined. The reason is per-cpu data-structures
1130 * are allocated by some modules at init time, and dont expect to
1131 * do this dynamically on cpu arrival/departure.
1132 * cpu_present_mask on the other hand can change dynamically.
1133 * In case when cpu_hotplug is not compiled, then we resort to current
1134 * behaviour, which is cpu_possible == cpu_present.
1135 * - Ashok Raj
1136 *
1137 * Three ways to find out the number of additional hotplug CPUs:
1138 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1139 * - The user can overwrite it with possible_cpus=NUM
1140 * - Otherwise don't reserve additional CPUs.
1141 * We do this because additional CPUs waste a lot of memory.
1142 * -AK
1143 */
1144__init void prefill_possible_map(void)
1145{
1146 int i, possible;
1147
1148 /* no processor from mptable or madt */
1149 if (!num_processors)
1150 num_processors = 1;
1151
1152 i = setup_max_cpus ?: 1;
1153 if (setup_possible_cpus == -1) {
1154 possible = num_processors;
1155#ifdef CONFIG_HOTPLUG_CPU
1156 if (setup_max_cpus)
1157 possible += disabled_cpus;
1158#else
1159 if (possible > i)
1160 possible = i;
1161#endif
1162 } else
1163 possible = setup_possible_cpus;
1164
1165 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1166
1167 /* nr_cpu_ids could be reduced via nr_cpus= */
1168 if (possible > nr_cpu_ids) {
1169 printk(KERN_WARNING
1170 "%d Processors exceeds NR_CPUS limit of %d\n",
1171 possible, nr_cpu_ids);
1172 possible = nr_cpu_ids;
1173 }
1174
1175#ifdef CONFIG_HOTPLUG_CPU
1176 if (!setup_max_cpus)
1177#endif
1178 if (possible > i) {
1179 printk(KERN_WARNING
1180 "%d Processors exceeds max_cpus limit of %u\n",
1181 possible, setup_max_cpus);
1182 possible = i;
1183 }
1184
1185 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1186 possible, max_t(int, possible - num_processors, 0));
1187
1188 for (i = 0; i < possible; i++)
1189 set_cpu_possible(i, true);
1190 for (; i < NR_CPUS; i++)
1191 set_cpu_possible(i, false);
1192
1193 nr_cpu_ids = possible;
1194}
1195
1196#ifdef CONFIG_HOTPLUG_CPU
1197
1198static void remove_siblinginfo(int cpu)
1199{
1200 int sibling;
1201 struct cpuinfo_x86 *c = &cpu_data(cpu);
1202
1203 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1204 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1205 /*/
1206 * last thread sibling in this cpu core going down
1207 */
1208 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1209 cpu_data(sibling).booted_cores--;
1210 }
1211
1212 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1213 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1214 cpumask_clear(cpu_sibling_mask(cpu));
1215 cpumask_clear(cpu_core_mask(cpu));
1216 c->phys_proc_id = 0;
1217 c->cpu_core_id = 0;
1218 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1219}
1220
1221static void __ref remove_cpu_from_maps(int cpu)
1222{
1223 set_cpu_online(cpu, false);
1224 cpumask_clear_cpu(cpu, cpu_callout_mask);
1225 cpumask_clear_cpu(cpu, cpu_callin_mask);
1226 /* was set by cpu_init() */
1227 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1228 numa_remove_cpu(cpu);
1229}
1230
1231void cpu_disable_common(void)
1232{
1233 int cpu = smp_processor_id();
1234
1235 remove_siblinginfo(cpu);
1236
1237 /* It's now safe to remove this processor from the online map */
1238 lock_vector_lock();
1239 remove_cpu_from_maps(cpu);
1240 unlock_vector_lock();
1241 fixup_irqs();
1242}
1243
1244int native_cpu_disable(void)
1245{
1246 int cpu = smp_processor_id();
1247
1248 /*
1249 * Perhaps use cpufreq to drop frequency, but that could go
1250 * into generic code.
1251 *
1252 * We won't take down the boot processor on i386 due to some
1253 * interrupts only being able to be serviced by the BSP.
1254 * Especially so if we're not using an IOAPIC -zwane
1255 */
1256 if (cpu == 0)
1257 return -EBUSY;
1258
1259 clear_local_APIC();
1260
1261 cpu_disable_common();
1262 return 0;
1263}
1264
1265void native_cpu_die(unsigned int cpu)
1266{
1267 /* We don't do anything here: idle task is faking death itself. */
1268 unsigned int i;
1269
1270 for (i = 0; i < 10; i++) {
1271 /* They ack this in play_dead by setting CPU_DEAD */
1272 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1273 if (system_state == SYSTEM_RUNNING)
1274 pr_info("CPU %u is now offline\n", cpu);
1275
1276 if (1 == num_online_cpus())
1277 alternatives_smp_switch(0);
1278 return;
1279 }
1280 msleep(100);
1281 }
1282 pr_err("CPU %u didn't die...\n", cpu);
1283}
1284
1285void play_dead_common(void)
1286{
1287 idle_task_exit();
1288 reset_lazy_tlbstate();
1289 amd_e400_remove_cpu(raw_smp_processor_id());
1290
1291 mb();
1292 /* Ack it */
1293 __this_cpu_write(cpu_state, CPU_DEAD);
1294
1295 /*
1296 * With physical CPU hotplug, we should halt the cpu
1297 */
1298 local_irq_disable();
1299}
1300
1301/*
1302 * We need to flush the caches before going to sleep, lest we have
1303 * dirty data in our caches when we come back up.
1304 */
1305static inline void mwait_play_dead(void)
1306{
1307 unsigned int eax, ebx, ecx, edx;
1308 unsigned int highest_cstate = 0;
1309 unsigned int highest_subcstate = 0;
1310 int i;
1311 void *mwait_ptr;
1312 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1313
1314 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1315 return;
1316 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1317 return;
1318 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1319 return;
1320
1321 eax = CPUID_MWAIT_LEAF;
1322 ecx = 0;
1323 native_cpuid(&eax, &ebx, &ecx, &edx);
1324
1325 /*
1326 * eax will be 0 if EDX enumeration is not valid.
1327 * Initialized below to cstate, sub_cstate value when EDX is valid.
1328 */
1329 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1330 eax = 0;
1331 } else {
1332 edx >>= MWAIT_SUBSTATE_SIZE;
1333 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1334 if (edx & MWAIT_SUBSTATE_MASK) {
1335 highest_cstate = i;
1336 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1337 }
1338 }
1339 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1340 (highest_subcstate - 1);
1341 }
1342
1343 /*
1344 * This should be a memory location in a cache line which is
1345 * unlikely to be touched by other processors. The actual
1346 * content is immaterial as it is not actually modified in any way.
1347 */
1348 mwait_ptr = ¤t_thread_info()->flags;
1349
1350 wbinvd();
1351
1352 while (1) {
1353 /*
1354 * The CLFLUSH is a workaround for erratum AAI65 for
1355 * the Xeon 7400 series. It's not clear it is actually
1356 * needed, but it should be harmless in either case.
1357 * The WBINVD is insufficient due to the spurious-wakeup
1358 * case where we return around the loop.
1359 */
1360 clflush(mwait_ptr);
1361 __monitor(mwait_ptr, 0, 0);
1362 mb();
1363 __mwait(eax, 0);
1364 }
1365}
1366
1367static inline void hlt_play_dead(void)
1368{
1369 if (__this_cpu_read(cpu_info.x86) >= 4)
1370 wbinvd();
1371
1372 while (1) {
1373 native_halt();
1374 }
1375}
1376
1377void native_play_dead(void)
1378{
1379 play_dead_common();
1380 tboot_shutdown(TB_SHUTDOWN_WFS);
1381
1382 mwait_play_dead(); /* Only returns on failure */
1383 if (cpuidle_play_dead())
1384 hlt_play_dead();
1385}
1386
1387#else /* ... !CONFIG_HOTPLUG_CPU */
1388int native_cpu_disable(void)
1389{
1390 return -ENOSYS;
1391}
1392
1393void native_cpu_die(unsigned int cpu)
1394{
1395 /* We said "no" in __cpu_disable */
1396 BUG();
1397}
1398
1399void native_play_dead(void)
1400{
1401 BUG();
1402}
1403
1404#endif