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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11#include <linux/circ_buf.h>
12#include <linux/tty.h>
13#include <linux/ioport.h>
14#include <linux/slab.h>
15#include <linux/init.h>
16#include <linux/serial.h>
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/console.h>
20#include <linux/sysrq.h>
21#include <linux/tty_flip.h>
22#include <linux/platform_device.h>
23#include <linux/of.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/atmel_pdc.h>
27#include <linux/uaccess.h>
28#include <linux/platform_data/atmel.h>
29#include <linux/timer.h>
30#include <linux/err.h>
31#include <linux/irq.h>
32#include <linux/suspend.h>
33#include <linux/mm.h>
34#include <linux/io.h>
35
36#include <asm/div64.h>
37#include <asm/ioctls.h>
38
39#define PDC_BUFFER_SIZE 512
40/* Revisit: We should calculate this based on the actual port settings */
41#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
42
43/* The minium number of data FIFOs should be able to contain */
44#define ATMEL_MIN_FIFO_SIZE 8
45/*
46 * These two offsets are substracted from the RX FIFO size to define the RTS
47 * high and low thresholds
48 */
49#define ATMEL_RTS_HIGH_OFFSET 16
50#define ATMEL_RTS_LOW_OFFSET 20
51
52#include <linux/serial_core.h>
53
54#include "serial_mctrl_gpio.h"
55#include "atmel_serial.h"
56
57static void atmel_start_rx(struct uart_port *port);
58static void atmel_stop_rx(struct uart_port *port);
59
60#ifdef CONFIG_SERIAL_ATMEL_TTYAT
61
62/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
63 * should coexist with the 8250 driver, such as if we have an external 16C550
64 * UART. */
65#define SERIAL_ATMEL_MAJOR 204
66#define MINOR_START 154
67#define ATMEL_DEVICENAME "ttyAT"
68
69#else
70
71/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
72 * name, but it is legally reserved for the 8250 driver. */
73#define SERIAL_ATMEL_MAJOR TTY_MAJOR
74#define MINOR_START 64
75#define ATMEL_DEVICENAME "ttyS"
76
77#endif
78
79#define ATMEL_ISR_PASS_LIMIT 256
80
81struct atmel_dma_buffer {
82 unsigned char *buf;
83 dma_addr_t dma_addr;
84 unsigned int dma_size;
85 unsigned int ofs;
86};
87
88struct atmel_uart_char {
89 u16 status;
90 u16 ch;
91};
92
93/*
94 * Be careful, the real size of the ring buffer is
95 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
96 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
97 * DMA mode.
98 */
99#define ATMEL_SERIAL_RINGSIZE 1024
100
101/*
102 * at91: 6 USARTs and one DBGU port (SAM9260)
103 * samx7: 3 USARTs and 5 UARTs
104 */
105#define ATMEL_MAX_UART 8
106
107/*
108 * We wrap our port structure around the generic uart_port.
109 */
110struct atmel_uart_port {
111 struct uart_port uart; /* uart */
112 struct clk *clk; /* uart clock */
113 struct clk *gclk; /* uart generic clock */
114 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
115 u32 backup_imr; /* IMR saved during suspend */
116 int break_active; /* break being received */
117
118 bool use_dma_rx; /* enable DMA receiver */
119 bool use_pdc_rx; /* enable PDC receiver */
120 short pdc_rx_idx; /* current PDC RX buffer */
121 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
122
123 bool use_dma_tx; /* enable DMA transmitter */
124 bool use_pdc_tx; /* enable PDC transmitter */
125 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
126
127 spinlock_t lock_tx; /* port lock */
128 spinlock_t lock_rx; /* port lock */
129 struct dma_chan *chan_tx;
130 struct dma_chan *chan_rx;
131 struct dma_async_tx_descriptor *desc_tx;
132 struct dma_async_tx_descriptor *desc_rx;
133 dma_cookie_t cookie_tx;
134 dma_cookie_t cookie_rx;
135 struct scatterlist sg_tx;
136 struct scatterlist sg_rx;
137 struct tasklet_struct tasklet_rx;
138 struct tasklet_struct tasklet_tx;
139 atomic_t tasklet_shutdown;
140 unsigned int irq_status_prev;
141 unsigned int tx_len;
142
143 struct circ_buf rx_ring;
144
145 struct mctrl_gpios *gpios;
146 u32 backup_mode; /* MR saved during iso7816 operations */
147 u32 backup_brgr; /* BRGR saved during iso7816 operations */
148 unsigned int tx_done_mask;
149 u32 fifo_size;
150 u32 rts_high;
151 u32 rts_low;
152 bool ms_irq_enabled;
153 u32 rtor; /* address of receiver timeout register if it exists */
154 bool is_usart;
155 bool has_frac_baudrate;
156 bool has_hw_timer;
157 struct timer_list uart_timer;
158
159 bool tx_stopped;
160 bool suspended;
161 unsigned int pending;
162 unsigned int pending_status;
163 spinlock_t lock_suspended;
164
165 bool hd_start_rx; /* can start RX during half-duplex operation */
166
167 /* ISO7816 */
168 unsigned int fidi_min;
169 unsigned int fidi_max;
170
171 struct {
172 u32 cr;
173 u32 mr;
174 u32 imr;
175 u32 brgr;
176 u32 rtor;
177 u32 ttgr;
178 u32 fmr;
179 u32 fimr;
180 } cache;
181
182 int (*prepare_rx)(struct uart_port *port);
183 int (*prepare_tx)(struct uart_port *port);
184 void (*schedule_rx)(struct uart_port *port);
185 void (*schedule_tx)(struct uart_port *port);
186 void (*release_rx)(struct uart_port *port);
187 void (*release_tx)(struct uart_port *port);
188};
189
190static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
191static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
192
193#if defined(CONFIG_OF)
194static const struct of_device_id atmel_serial_dt_ids[] = {
195 { .compatible = "atmel,at91rm9200-usart-serial" },
196 { /* sentinel */ }
197};
198#endif
199
200static inline struct atmel_uart_port *
201to_atmel_uart_port(struct uart_port *uart)
202{
203 return container_of(uart, struct atmel_uart_port, uart);
204}
205
206static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
207{
208 return __raw_readl(port->membase + reg);
209}
210
211static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
212{
213 __raw_writel(value, port->membase + reg);
214}
215
216static inline u8 atmel_uart_read_char(struct uart_port *port)
217{
218 return __raw_readb(port->membase + ATMEL_US_RHR);
219}
220
221static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
222{
223 __raw_writeb(value, port->membase + ATMEL_US_THR);
224}
225
226static inline int atmel_uart_is_half_duplex(struct uart_port *port)
227{
228 return ((port->rs485.flags & SER_RS485_ENABLED) &&
229 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
230 (port->iso7816.flags & SER_ISO7816_ENABLED);
231}
232
233static inline int atmel_error_rate(int desired_value, int actual_value)
234{
235 return 100 - (desired_value * 100) / actual_value;
236}
237
238#ifdef CONFIG_SERIAL_ATMEL_PDC
239static bool atmel_use_pdc_rx(struct uart_port *port)
240{
241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
242
243 return atmel_port->use_pdc_rx;
244}
245
246static bool atmel_use_pdc_tx(struct uart_port *port)
247{
248 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
249
250 return atmel_port->use_pdc_tx;
251}
252#else
253static bool atmel_use_pdc_rx(struct uart_port *port)
254{
255 return false;
256}
257
258static bool atmel_use_pdc_tx(struct uart_port *port)
259{
260 return false;
261}
262#endif
263
264static bool atmel_use_dma_tx(struct uart_port *port)
265{
266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
267
268 return atmel_port->use_dma_tx;
269}
270
271static bool atmel_use_dma_rx(struct uart_port *port)
272{
273 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
274
275 return atmel_port->use_dma_rx;
276}
277
278static bool atmel_use_fifo(struct uart_port *port)
279{
280 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
281
282 return atmel_port->fifo_size;
283}
284
285static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
286 struct tasklet_struct *t)
287{
288 if (!atomic_read(&atmel_port->tasklet_shutdown))
289 tasklet_schedule(t);
290}
291
292/* Enable or disable the rs485 support */
293static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
294 struct serial_rs485 *rs485conf)
295{
296 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
297 unsigned int mode;
298
299 /* Disable interrupts */
300 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
301
302 mode = atmel_uart_readl(port, ATMEL_US_MR);
303
304 if (rs485conf->flags & SER_RS485_ENABLED) {
305 dev_dbg(port->dev, "Setting UART to RS485\n");
306 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
307 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
308 else
309 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
310
311 atmel_uart_writel(port, ATMEL_US_TTGR,
312 rs485conf->delay_rts_after_send);
313 mode &= ~ATMEL_US_USMODE;
314 mode |= ATMEL_US_USMODE_RS485;
315 } else {
316 dev_dbg(port->dev, "Setting UART to RS232\n");
317 if (atmel_use_pdc_tx(port))
318 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
319 ATMEL_US_TXBUFE;
320 else
321 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
322 }
323 atmel_uart_writel(port, ATMEL_US_MR, mode);
324
325 /* Enable interrupts */
326 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
327
328 return 0;
329}
330
331static unsigned int atmel_calc_cd(struct uart_port *port,
332 struct serial_iso7816 *iso7816conf)
333{
334 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
335 unsigned int cd;
336 u64 mck_rate;
337
338 mck_rate = (u64)clk_get_rate(atmel_port->clk);
339 do_div(mck_rate, iso7816conf->clk);
340 cd = mck_rate;
341 return cd;
342}
343
344static unsigned int atmel_calc_fidi(struct uart_port *port,
345 struct serial_iso7816 *iso7816conf)
346{
347 u64 fidi = 0;
348
349 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
350 fidi = (u64)iso7816conf->sc_fi;
351 do_div(fidi, iso7816conf->sc_di);
352 }
353 return (u32)fidi;
354}
355
356/* Enable or disable the iso7816 support */
357/* Called with interrupts disabled */
358static int atmel_config_iso7816(struct uart_port *port,
359 struct serial_iso7816 *iso7816conf)
360{
361 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
362 unsigned int mode;
363 unsigned int cd, fidi;
364 int ret = 0;
365
366 /* Disable interrupts */
367 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
368
369 mode = atmel_uart_readl(port, ATMEL_US_MR);
370
371 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
372 mode &= ~ATMEL_US_USMODE;
373
374 if (iso7816conf->tg > 255) {
375 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
376 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
377 ret = -EINVAL;
378 goto err_out;
379 }
380
381 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
382 == SER_ISO7816_T(0)) {
383 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
384 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
385 == SER_ISO7816_T(1)) {
386 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
387 } else {
388 dev_err(port->dev, "ISO7816: Type not supported\n");
389 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
390 ret = -EINVAL;
391 goto err_out;
392 }
393
394 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
395
396 /* select mck clock, and output */
397 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
398 /* set parity for normal/inverse mode + max iterations */
399 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
400
401 cd = atmel_calc_cd(port, iso7816conf);
402 fidi = atmel_calc_fidi(port, iso7816conf);
403 if (fidi == 0) {
404 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
405 } else if (fidi < atmel_port->fidi_min
406 || fidi > atmel_port->fidi_max) {
407 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
408 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
409 ret = -EINVAL;
410 goto err_out;
411 }
412
413 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
414 /* port not yet in iso7816 mode: store configuration */
415 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
416 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
417 }
418
419 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
420 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
421 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
422
423 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
424 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
425 } else {
426 dev_dbg(port->dev, "Setting UART back to RS232\n");
427 /* back to last RS232 settings */
428 mode = atmel_port->backup_mode;
429 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
430 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
431 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
432 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
433
434 if (atmel_use_pdc_tx(port))
435 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
436 ATMEL_US_TXBUFE;
437 else
438 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
439 }
440
441 port->iso7816 = *iso7816conf;
442
443 atmel_uart_writel(port, ATMEL_US_MR, mode);
444
445err_out:
446 /* Enable interrupts */
447 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
448
449 return ret;
450}
451
452/*
453 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
454 */
455static u_int atmel_tx_empty(struct uart_port *port)
456{
457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
458
459 if (atmel_port->tx_stopped)
460 return TIOCSER_TEMT;
461 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
462 TIOCSER_TEMT :
463 0;
464}
465
466/*
467 * Set state of the modem control output lines
468 */
469static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
470{
471 unsigned int control = 0;
472 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
473 unsigned int rts_paused, rts_ready;
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
475
476 /* override mode to RS485 if needed, otherwise keep the current mode */
477 if (port->rs485.flags & SER_RS485_ENABLED) {
478 atmel_uart_writel(port, ATMEL_US_TTGR,
479 port->rs485.delay_rts_after_send);
480 mode &= ~ATMEL_US_USMODE;
481 mode |= ATMEL_US_USMODE_RS485;
482 }
483
484 /* set the RTS line state according to the mode */
485 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
486 /* force RTS line to high level */
487 rts_paused = ATMEL_US_RTSEN;
488
489 /* give the control of the RTS line back to the hardware */
490 rts_ready = ATMEL_US_RTSDIS;
491 } else {
492 /* force RTS line to high level */
493 rts_paused = ATMEL_US_RTSDIS;
494
495 /* force RTS line to low level */
496 rts_ready = ATMEL_US_RTSEN;
497 }
498
499 if (mctrl & TIOCM_RTS)
500 control |= rts_ready;
501 else
502 control |= rts_paused;
503
504 if (mctrl & TIOCM_DTR)
505 control |= ATMEL_US_DTREN;
506 else
507 control |= ATMEL_US_DTRDIS;
508
509 atmel_uart_writel(port, ATMEL_US_CR, control);
510
511 mctrl_gpio_set(atmel_port->gpios, mctrl);
512
513 /* Local loopback mode? */
514 mode &= ~ATMEL_US_CHMODE;
515 if (mctrl & TIOCM_LOOP)
516 mode |= ATMEL_US_CHMODE_LOC_LOOP;
517 else
518 mode |= ATMEL_US_CHMODE_NORMAL;
519
520 atmel_uart_writel(port, ATMEL_US_MR, mode);
521}
522
523/*
524 * Get state of the modem control input lines
525 */
526static u_int atmel_get_mctrl(struct uart_port *port)
527{
528 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
529 unsigned int ret = 0, status;
530
531 status = atmel_uart_readl(port, ATMEL_US_CSR);
532
533 /*
534 * The control signals are active low.
535 */
536 if (!(status & ATMEL_US_DCD))
537 ret |= TIOCM_CD;
538 if (!(status & ATMEL_US_CTS))
539 ret |= TIOCM_CTS;
540 if (!(status & ATMEL_US_DSR))
541 ret |= TIOCM_DSR;
542 if (!(status & ATMEL_US_RI))
543 ret |= TIOCM_RI;
544
545 return mctrl_gpio_get(atmel_port->gpios, &ret);
546}
547
548/*
549 * Stop transmitting.
550 */
551static void atmel_stop_tx(struct uart_port *port)
552{
553 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
554 bool is_pdc = atmel_use_pdc_tx(port);
555 bool is_dma = is_pdc || atmel_use_dma_tx(port);
556
557 if (is_pdc) {
558 /* disable PDC transmit */
559 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
560 }
561
562 if (is_dma) {
563 /*
564 * Disable the transmitter.
565 * This is mandatory when DMA is used, otherwise the DMA buffer
566 * is fully transmitted.
567 */
568 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
569 atmel_port->tx_stopped = true;
570 }
571
572 /* Disable interrupts */
573 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
574
575 if (atmel_uart_is_half_duplex(port))
576 if (!atomic_read(&atmel_port->tasklet_shutdown))
577 atmel_start_rx(port);
578}
579
580/*
581 * Start transmitting.
582 */
583static void atmel_start_tx(struct uart_port *port)
584{
585 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
586 bool is_pdc = atmel_use_pdc_tx(port);
587 bool is_dma = is_pdc || atmel_use_dma_tx(port);
588
589 if (is_pdc && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
590 & ATMEL_PDC_TXTEN))
591 /* The transmitter is already running. Yes, we
592 really need this.*/
593 return;
594
595 if (is_dma && atmel_uart_is_half_duplex(port))
596 atmel_stop_rx(port);
597
598 if (is_pdc) {
599 /* re-enable PDC transmit */
600 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
601 }
602
603 /* Enable interrupts */
604 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
605
606 if (is_dma) {
607 /* re-enable the transmitter */
608 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
609 atmel_port->tx_stopped = false;
610 }
611}
612
613/*
614 * start receiving - port is in process of being opened.
615 */
616static void atmel_start_rx(struct uart_port *port)
617{
618 /* reset status and receiver */
619 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
620
621 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
622
623 if (atmel_use_pdc_rx(port)) {
624 /* enable PDC controller */
625 atmel_uart_writel(port, ATMEL_US_IER,
626 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
627 port->read_status_mask);
628 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
629 } else {
630 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
631 }
632}
633
634/*
635 * Stop receiving - port is in process of being closed.
636 */
637static void atmel_stop_rx(struct uart_port *port)
638{
639 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
640
641 if (atmel_use_pdc_rx(port)) {
642 /* disable PDC receive */
643 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
644 atmel_uart_writel(port, ATMEL_US_IDR,
645 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
646 port->read_status_mask);
647 } else {
648 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
649 }
650}
651
652/*
653 * Enable modem status interrupts
654 */
655static void atmel_enable_ms(struct uart_port *port)
656{
657 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
658 uint32_t ier = 0;
659
660 /*
661 * Interrupt should not be enabled twice
662 */
663 if (atmel_port->ms_irq_enabled)
664 return;
665
666 atmel_port->ms_irq_enabled = true;
667
668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
669 ier |= ATMEL_US_CTSIC;
670
671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
672 ier |= ATMEL_US_DSRIC;
673
674 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
675 ier |= ATMEL_US_RIIC;
676
677 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
678 ier |= ATMEL_US_DCDIC;
679
680 atmel_uart_writel(port, ATMEL_US_IER, ier);
681
682 mctrl_gpio_enable_ms(atmel_port->gpios);
683}
684
685/*
686 * Disable modem status interrupts
687 */
688static void atmel_disable_ms(struct uart_port *port)
689{
690 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
691 uint32_t idr = 0;
692
693 /*
694 * Interrupt should not be disabled twice
695 */
696 if (!atmel_port->ms_irq_enabled)
697 return;
698
699 atmel_port->ms_irq_enabled = false;
700
701 mctrl_gpio_disable_ms(atmel_port->gpios);
702
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
704 idr |= ATMEL_US_CTSIC;
705
706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
707 idr |= ATMEL_US_DSRIC;
708
709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
710 idr |= ATMEL_US_RIIC;
711
712 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
713 idr |= ATMEL_US_DCDIC;
714
715 atmel_uart_writel(port, ATMEL_US_IDR, idr);
716}
717
718/*
719 * Control the transmission of a break signal
720 */
721static void atmel_break_ctl(struct uart_port *port, int break_state)
722{
723 if (break_state != 0)
724 /* start break */
725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
726 else
727 /* stop break */
728 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
729}
730
731/*
732 * Stores the incoming character in the ring buffer
733 */
734static void
735atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
736 unsigned int ch)
737{
738 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
739 struct circ_buf *ring = &atmel_port->rx_ring;
740 struct atmel_uart_char *c;
741
742 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
743 /* Buffer overflow, ignore char */
744 return;
745
746 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
747 c->status = status;
748 c->ch = ch;
749
750 /* Make sure the character is stored before we update head. */
751 smp_wmb();
752
753 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
754}
755
756/*
757 * Deal with parity, framing and overrun errors.
758 */
759static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
760{
761 /* clear error */
762 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
763
764 if (status & ATMEL_US_RXBRK) {
765 /* ignore side-effect */
766 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
767 port->icount.brk++;
768 }
769 if (status & ATMEL_US_PARE)
770 port->icount.parity++;
771 if (status & ATMEL_US_FRAME)
772 port->icount.frame++;
773 if (status & ATMEL_US_OVRE)
774 port->icount.overrun++;
775}
776
777/*
778 * Characters received (called from interrupt handler)
779 */
780static void atmel_rx_chars(struct uart_port *port)
781{
782 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
783 unsigned int status, ch;
784
785 status = atmel_uart_readl(port, ATMEL_US_CSR);
786 while (status & ATMEL_US_RXRDY) {
787 ch = atmel_uart_read_char(port);
788
789 /*
790 * note that the error handling code is
791 * out of the main execution path
792 */
793 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
794 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
795 || atmel_port->break_active)) {
796
797 /* clear error */
798 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
799
800 if (status & ATMEL_US_RXBRK
801 && !atmel_port->break_active) {
802 atmel_port->break_active = 1;
803 atmel_uart_writel(port, ATMEL_US_IER,
804 ATMEL_US_RXBRK);
805 } else {
806 /*
807 * This is either the end-of-break
808 * condition or we've received at
809 * least one character without RXBRK
810 * being set. In both cases, the next
811 * RXBRK will indicate start-of-break.
812 */
813 atmel_uart_writel(port, ATMEL_US_IDR,
814 ATMEL_US_RXBRK);
815 status &= ~ATMEL_US_RXBRK;
816 atmel_port->break_active = 0;
817 }
818 }
819
820 atmel_buffer_rx_char(port, status, ch);
821 status = atmel_uart_readl(port, ATMEL_US_CSR);
822 }
823
824 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
825}
826
827/*
828 * Transmit characters (called from tasklet with TXRDY interrupt
829 * disabled)
830 */
831static void atmel_tx_chars(struct uart_port *port)
832{
833 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
834 bool pending;
835 u8 ch;
836
837 pending = uart_port_tx(port, ch,
838 atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY,
839 atmel_uart_write_char(port, ch));
840 if (pending) {
841 /* we still have characters to transmit, so we should continue
842 * transmitting them when TX is ready, regardless of
843 * mode or duplexity
844 */
845 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
846
847 /* Enable interrupts */
848 atmel_uart_writel(port, ATMEL_US_IER,
849 atmel_port->tx_done_mask);
850 } else {
851 if (atmel_uart_is_half_duplex(port))
852 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
853 }
854}
855
856static void atmel_complete_tx_dma(void *arg)
857{
858 struct atmel_uart_port *atmel_port = arg;
859 struct uart_port *port = &atmel_port->uart;
860 struct circ_buf *xmit = &port->state->xmit;
861 struct dma_chan *chan = atmel_port->chan_tx;
862 unsigned long flags;
863
864 uart_port_lock_irqsave(port, &flags);
865
866 if (chan)
867 dmaengine_terminate_all(chan);
868 uart_xmit_advance(port, atmel_port->tx_len);
869
870 spin_lock(&atmel_port->lock_tx);
871 async_tx_ack(atmel_port->desc_tx);
872 atmel_port->cookie_tx = -EINVAL;
873 atmel_port->desc_tx = NULL;
874 spin_unlock(&atmel_port->lock_tx);
875
876 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
877 uart_write_wakeup(port);
878
879 /*
880 * xmit is a circular buffer so, if we have just send data from
881 * xmit->tail to the end of xmit->buf, now we have to transmit the
882 * remaining data from the beginning of xmit->buf to xmit->head.
883 */
884 if (!uart_circ_empty(xmit))
885 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
886 else if (atmel_uart_is_half_duplex(port)) {
887 /*
888 * DMA done, re-enable TXEMPTY and signal that we can stop
889 * TX and start RX for RS485
890 */
891 atmel_port->hd_start_rx = true;
892 atmel_uart_writel(port, ATMEL_US_IER,
893 atmel_port->tx_done_mask);
894 }
895
896 uart_port_unlock_irqrestore(port, flags);
897}
898
899static void atmel_release_tx_dma(struct uart_port *port)
900{
901 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
902 struct dma_chan *chan = atmel_port->chan_tx;
903
904 if (chan) {
905 dmaengine_terminate_all(chan);
906 dma_release_channel(chan);
907 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
908 DMA_TO_DEVICE);
909 }
910
911 atmel_port->desc_tx = NULL;
912 atmel_port->chan_tx = NULL;
913 atmel_port->cookie_tx = -EINVAL;
914}
915
916/*
917 * Called from tasklet with TXRDY interrupt is disabled.
918 */
919static void atmel_tx_dma(struct uart_port *port)
920{
921 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
922 struct circ_buf *xmit = &port->state->xmit;
923 struct dma_chan *chan = atmel_port->chan_tx;
924 struct dma_async_tx_descriptor *desc;
925 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
926 unsigned int tx_len, part1_len, part2_len, sg_len;
927 dma_addr_t phys_addr;
928
929 /* Make sure we have an idle channel */
930 if (atmel_port->desc_tx != NULL)
931 return;
932
933 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
934 /*
935 * DMA is idle now.
936 * Port xmit buffer is already mapped,
937 * and it is one page... Just adjust
938 * offsets and lengths. Since it is a circular buffer,
939 * we have to transmit till the end, and then the rest.
940 * Take the port lock to get a
941 * consistent xmit buffer state.
942 */
943 tx_len = CIRC_CNT_TO_END(xmit->head,
944 xmit->tail,
945 UART_XMIT_SIZE);
946
947 if (atmel_port->fifo_size) {
948 /* multi data mode */
949 part1_len = (tx_len & ~0x3); /* DWORD access */
950 part2_len = (tx_len & 0x3); /* BYTE access */
951 } else {
952 /* single data (legacy) mode */
953 part1_len = 0;
954 part2_len = tx_len; /* BYTE access only */
955 }
956
957 sg_init_table(sgl, 2);
958 sg_len = 0;
959 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
960 if (part1_len) {
961 sg = &sgl[sg_len++];
962 sg_dma_address(sg) = phys_addr;
963 sg_dma_len(sg) = part1_len;
964
965 phys_addr += part1_len;
966 }
967
968 if (part2_len) {
969 sg = &sgl[sg_len++];
970 sg_dma_address(sg) = phys_addr;
971 sg_dma_len(sg) = part2_len;
972 }
973
974 /*
975 * save tx_len so atmel_complete_tx_dma() will increase
976 * xmit->tail correctly
977 */
978 atmel_port->tx_len = tx_len;
979
980 desc = dmaengine_prep_slave_sg(chan,
981 sgl,
982 sg_len,
983 DMA_MEM_TO_DEV,
984 DMA_PREP_INTERRUPT |
985 DMA_CTRL_ACK);
986 if (!desc) {
987 dev_err(port->dev, "Failed to send via dma!\n");
988 return;
989 }
990
991 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
992
993 atmel_port->desc_tx = desc;
994 desc->callback = atmel_complete_tx_dma;
995 desc->callback_param = atmel_port;
996 atmel_port->cookie_tx = dmaengine_submit(desc);
997 if (dma_submit_error(atmel_port->cookie_tx)) {
998 dev_err(port->dev, "dma_submit_error %d\n",
999 atmel_port->cookie_tx);
1000 return;
1001 }
1002
1003 dma_async_issue_pending(chan);
1004 }
1005
1006 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1007 uart_write_wakeup(port);
1008}
1009
1010static int atmel_prepare_tx_dma(struct uart_port *port)
1011{
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1013 struct device *mfd_dev = port->dev->parent;
1014 dma_cap_mask_t mask;
1015 struct dma_slave_config config;
1016 struct dma_chan *chan;
1017 int ret, nent;
1018
1019 dma_cap_zero(mask);
1020 dma_cap_set(DMA_SLAVE, mask);
1021
1022 chan = dma_request_chan(mfd_dev, "tx");
1023 if (IS_ERR(chan)) {
1024 atmel_port->chan_tx = NULL;
1025 goto chan_err;
1026 }
1027 atmel_port->chan_tx = chan;
1028 dev_info(port->dev, "using %s for tx DMA transfers\n",
1029 dma_chan_name(atmel_port->chan_tx));
1030
1031 spin_lock_init(&atmel_port->lock_tx);
1032 sg_init_table(&atmel_port->sg_tx, 1);
1033 /* UART circular tx buffer is an aligned page. */
1034 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1035 sg_set_page(&atmel_port->sg_tx,
1036 virt_to_page(port->state->xmit.buf),
1037 UART_XMIT_SIZE,
1038 offset_in_page(port->state->xmit.buf));
1039 nent = dma_map_sg(port->dev,
1040 &atmel_port->sg_tx,
1041 1,
1042 DMA_TO_DEVICE);
1043
1044 if (!nent) {
1045 dev_dbg(port->dev, "need to release resource of dma\n");
1046 goto chan_err;
1047 } else {
1048 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1049 sg_dma_len(&atmel_port->sg_tx),
1050 port->state->xmit.buf,
1051 &sg_dma_address(&atmel_port->sg_tx));
1052 }
1053
1054 /* Configure the slave DMA */
1055 memset(&config, 0, sizeof(config));
1056 config.direction = DMA_MEM_TO_DEV;
1057 config.dst_addr_width = (atmel_port->fifo_size) ?
1058 DMA_SLAVE_BUSWIDTH_4_BYTES :
1059 DMA_SLAVE_BUSWIDTH_1_BYTE;
1060 config.dst_addr = port->mapbase + ATMEL_US_THR;
1061 config.dst_maxburst = 1;
1062
1063 ret = dmaengine_slave_config(atmel_port->chan_tx,
1064 &config);
1065 if (ret) {
1066 dev_err(port->dev, "DMA tx slave configuration failed\n");
1067 goto chan_err;
1068 }
1069
1070 return 0;
1071
1072chan_err:
1073 dev_err(port->dev, "TX channel not available, switch to pio\n");
1074 atmel_port->use_dma_tx = false;
1075 if (atmel_port->chan_tx)
1076 atmel_release_tx_dma(port);
1077 return -EINVAL;
1078}
1079
1080static void atmel_complete_rx_dma(void *arg)
1081{
1082 struct uart_port *port = arg;
1083 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1084
1085 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1086}
1087
1088static void atmel_release_rx_dma(struct uart_port *port)
1089{
1090 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1091 struct dma_chan *chan = atmel_port->chan_rx;
1092
1093 if (chan) {
1094 dmaengine_terminate_all(chan);
1095 dma_release_channel(chan);
1096 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1097 DMA_FROM_DEVICE);
1098 }
1099
1100 atmel_port->desc_rx = NULL;
1101 atmel_port->chan_rx = NULL;
1102 atmel_port->cookie_rx = -EINVAL;
1103}
1104
1105static void atmel_rx_from_dma(struct uart_port *port)
1106{
1107 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1108 struct tty_port *tport = &port->state->port;
1109 struct circ_buf *ring = &atmel_port->rx_ring;
1110 struct dma_chan *chan = atmel_port->chan_rx;
1111 struct dma_tx_state state;
1112 enum dma_status dmastat;
1113 size_t count;
1114
1115
1116 /* Reset the UART timeout early so that we don't miss one */
1117 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1118 dmastat = dmaengine_tx_status(chan,
1119 atmel_port->cookie_rx,
1120 &state);
1121 /* Restart a new tasklet if DMA status is error */
1122 if (dmastat == DMA_ERROR) {
1123 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1124 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1125 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1126 return;
1127 }
1128
1129 /* CPU claims ownership of RX DMA buffer */
1130 dma_sync_sg_for_cpu(port->dev,
1131 &atmel_port->sg_rx,
1132 1,
1133 DMA_FROM_DEVICE);
1134
1135 /*
1136 * ring->head points to the end of data already written by the DMA.
1137 * ring->tail points to the beginning of data to be read by the
1138 * framework.
1139 * The current transfer size should not be larger than the dma buffer
1140 * length.
1141 */
1142 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1143 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1144 /*
1145 * At this point ring->head may point to the first byte right after the
1146 * last byte of the dma buffer:
1147 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1148 *
1149 * However ring->tail must always points inside the dma buffer:
1150 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1151 *
1152 * Since we use a ring buffer, we have to handle the case
1153 * where head is lower than tail. In such a case, we first read from
1154 * tail to the end of the buffer then reset tail.
1155 */
1156 if (ring->head < ring->tail) {
1157 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1158
1159 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1160 ring->tail = 0;
1161 port->icount.rx += count;
1162 }
1163
1164 /* Finally we read data from tail to head */
1165 if (ring->tail < ring->head) {
1166 count = ring->head - ring->tail;
1167
1168 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1169 /* Wrap ring->head if needed */
1170 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1171 ring->head = 0;
1172 ring->tail = ring->head;
1173 port->icount.rx += count;
1174 }
1175
1176 /* USART retreives ownership of RX DMA buffer */
1177 dma_sync_sg_for_device(port->dev,
1178 &atmel_port->sg_rx,
1179 1,
1180 DMA_FROM_DEVICE);
1181
1182 tty_flip_buffer_push(tport);
1183
1184 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1185}
1186
1187static int atmel_prepare_rx_dma(struct uart_port *port)
1188{
1189 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1190 struct device *mfd_dev = port->dev->parent;
1191 struct dma_async_tx_descriptor *desc;
1192 dma_cap_mask_t mask;
1193 struct dma_slave_config config;
1194 struct circ_buf *ring;
1195 struct dma_chan *chan;
1196 int ret, nent;
1197
1198 ring = &atmel_port->rx_ring;
1199
1200 dma_cap_zero(mask);
1201 dma_cap_set(DMA_CYCLIC, mask);
1202
1203 chan = dma_request_chan(mfd_dev, "rx");
1204 if (IS_ERR(chan)) {
1205 atmel_port->chan_rx = NULL;
1206 goto chan_err;
1207 }
1208 atmel_port->chan_rx = chan;
1209 dev_info(port->dev, "using %s for rx DMA transfers\n",
1210 dma_chan_name(atmel_port->chan_rx));
1211
1212 spin_lock_init(&atmel_port->lock_rx);
1213 sg_init_table(&atmel_port->sg_rx, 1);
1214 /* UART circular rx buffer is an aligned page. */
1215 BUG_ON(!PAGE_ALIGNED(ring->buf));
1216 sg_set_page(&atmel_port->sg_rx,
1217 virt_to_page(ring->buf),
1218 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1219 offset_in_page(ring->buf));
1220 nent = dma_map_sg(port->dev,
1221 &atmel_port->sg_rx,
1222 1,
1223 DMA_FROM_DEVICE);
1224
1225 if (!nent) {
1226 dev_dbg(port->dev, "need to release resource of dma\n");
1227 goto chan_err;
1228 } else {
1229 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1230 sg_dma_len(&atmel_port->sg_rx),
1231 ring->buf,
1232 &sg_dma_address(&atmel_port->sg_rx));
1233 }
1234
1235 /* Configure the slave DMA */
1236 memset(&config, 0, sizeof(config));
1237 config.direction = DMA_DEV_TO_MEM;
1238 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1239 config.src_addr = port->mapbase + ATMEL_US_RHR;
1240 config.src_maxburst = 1;
1241
1242 ret = dmaengine_slave_config(atmel_port->chan_rx,
1243 &config);
1244 if (ret) {
1245 dev_err(port->dev, "DMA rx slave configuration failed\n");
1246 goto chan_err;
1247 }
1248 /*
1249 * Prepare a cyclic dma transfer, assign 2 descriptors,
1250 * each one is half ring buffer size
1251 */
1252 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1253 sg_dma_address(&atmel_port->sg_rx),
1254 sg_dma_len(&atmel_port->sg_rx),
1255 sg_dma_len(&atmel_port->sg_rx)/2,
1256 DMA_DEV_TO_MEM,
1257 DMA_PREP_INTERRUPT);
1258 if (!desc) {
1259 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1260 goto chan_err;
1261 }
1262 desc->callback = atmel_complete_rx_dma;
1263 desc->callback_param = port;
1264 atmel_port->desc_rx = desc;
1265 atmel_port->cookie_rx = dmaengine_submit(desc);
1266 if (dma_submit_error(atmel_port->cookie_rx)) {
1267 dev_err(port->dev, "dma_submit_error %d\n",
1268 atmel_port->cookie_rx);
1269 goto chan_err;
1270 }
1271
1272 dma_async_issue_pending(atmel_port->chan_rx);
1273
1274 return 0;
1275
1276chan_err:
1277 dev_err(port->dev, "RX channel not available, switch to pio\n");
1278 atmel_port->use_dma_rx = false;
1279 if (atmel_port->chan_rx)
1280 atmel_release_rx_dma(port);
1281 return -EINVAL;
1282}
1283
1284static void atmel_uart_timer_callback(struct timer_list *t)
1285{
1286 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1287 uart_timer);
1288 struct uart_port *port = &atmel_port->uart;
1289
1290 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1291 tasklet_schedule(&atmel_port->tasklet_rx);
1292 mod_timer(&atmel_port->uart_timer,
1293 jiffies + uart_poll_timeout(port));
1294 }
1295}
1296
1297/*
1298 * receive interrupt handler.
1299 */
1300static void
1301atmel_handle_receive(struct uart_port *port, unsigned int pending)
1302{
1303 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1304
1305 if (atmel_use_pdc_rx(port)) {
1306 /*
1307 * PDC receive. Just schedule the tasklet and let it
1308 * figure out the details.
1309 *
1310 * TODO: We're not handling error flags correctly at
1311 * the moment.
1312 */
1313 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1314 atmel_uart_writel(port, ATMEL_US_IDR,
1315 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1316 atmel_tasklet_schedule(atmel_port,
1317 &atmel_port->tasklet_rx);
1318 }
1319
1320 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1321 ATMEL_US_FRAME | ATMEL_US_PARE))
1322 atmel_pdc_rxerr(port, pending);
1323 }
1324
1325 if (atmel_use_dma_rx(port)) {
1326 if (pending & ATMEL_US_TIMEOUT) {
1327 atmel_uart_writel(port, ATMEL_US_IDR,
1328 ATMEL_US_TIMEOUT);
1329 atmel_tasklet_schedule(atmel_port,
1330 &atmel_port->tasklet_rx);
1331 }
1332 }
1333
1334 /* Interrupt receive */
1335 if (pending & ATMEL_US_RXRDY)
1336 atmel_rx_chars(port);
1337 else if (pending & ATMEL_US_RXBRK) {
1338 /*
1339 * End of break detected. If it came along with a
1340 * character, atmel_rx_chars will handle it.
1341 */
1342 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1343 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1344 atmel_port->break_active = 0;
1345 }
1346}
1347
1348/*
1349 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1350 */
1351static void
1352atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1353{
1354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1355
1356 if (pending & atmel_port->tx_done_mask) {
1357 atmel_uart_writel(port, ATMEL_US_IDR,
1358 atmel_port->tx_done_mask);
1359
1360 /* Start RX if flag was set and FIFO is empty */
1361 if (atmel_port->hd_start_rx) {
1362 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1363 & ATMEL_US_TXEMPTY))
1364 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1365
1366 atmel_port->hd_start_rx = false;
1367 atmel_start_rx(port);
1368 }
1369
1370 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1371 }
1372}
1373
1374/*
1375 * status flags interrupt handler.
1376 */
1377static void
1378atmel_handle_status(struct uart_port *port, unsigned int pending,
1379 unsigned int status)
1380{
1381 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1382 unsigned int status_change;
1383
1384 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1385 | ATMEL_US_CTSIC)) {
1386 status_change = status ^ atmel_port->irq_status_prev;
1387 atmel_port->irq_status_prev = status;
1388
1389 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1390 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1391 /* TODO: All reads to CSR will clear these interrupts! */
1392 if (status_change & ATMEL_US_RI)
1393 port->icount.rng++;
1394 if (status_change & ATMEL_US_DSR)
1395 port->icount.dsr++;
1396 if (status_change & ATMEL_US_DCD)
1397 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1398 if (status_change & ATMEL_US_CTS)
1399 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1400
1401 wake_up_interruptible(&port->state->port.delta_msr_wait);
1402 }
1403 }
1404
1405 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1406 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1407}
1408
1409/*
1410 * Interrupt handler
1411 */
1412static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1413{
1414 struct uart_port *port = dev_id;
1415 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1416 unsigned int status, pending, mask, pass_counter = 0;
1417
1418 spin_lock(&atmel_port->lock_suspended);
1419
1420 do {
1421 status = atmel_uart_readl(port, ATMEL_US_CSR);
1422 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1423 pending = status & mask;
1424 if (!pending)
1425 break;
1426
1427 if (atmel_port->suspended) {
1428 atmel_port->pending |= pending;
1429 atmel_port->pending_status = status;
1430 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1431 pm_system_wakeup();
1432 break;
1433 }
1434
1435 atmel_handle_receive(port, pending);
1436 atmel_handle_status(port, pending, status);
1437 atmel_handle_transmit(port, pending);
1438 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1439
1440 spin_unlock(&atmel_port->lock_suspended);
1441
1442 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1443}
1444
1445static void atmel_release_tx_pdc(struct uart_port *port)
1446{
1447 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1448 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1449
1450 dma_unmap_single(port->dev,
1451 pdc->dma_addr,
1452 pdc->dma_size,
1453 DMA_TO_DEVICE);
1454}
1455
1456/*
1457 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1458 */
1459static void atmel_tx_pdc(struct uart_port *port)
1460{
1461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1462 struct circ_buf *xmit = &port->state->xmit;
1463 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1464 int count;
1465
1466 /* nothing left to transmit? */
1467 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1468 return;
1469 uart_xmit_advance(port, pdc->ofs);
1470 pdc->ofs = 0;
1471
1472 /* more to transmit - setup next transfer */
1473
1474 /* disable PDC transmit */
1475 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1476
1477 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1478 dma_sync_single_for_device(port->dev,
1479 pdc->dma_addr,
1480 pdc->dma_size,
1481 DMA_TO_DEVICE);
1482
1483 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1484 pdc->ofs = count;
1485
1486 atmel_uart_writel(port, ATMEL_PDC_TPR,
1487 pdc->dma_addr + xmit->tail);
1488 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1489 /* re-enable PDC transmit */
1490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1491 /* Enable interrupts */
1492 atmel_uart_writel(port, ATMEL_US_IER,
1493 atmel_port->tx_done_mask);
1494 } else {
1495 if (atmel_uart_is_half_duplex(port)) {
1496 /* DMA done, stop TX, start RX for RS485 */
1497 atmel_start_rx(port);
1498 }
1499 }
1500
1501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1502 uart_write_wakeup(port);
1503}
1504
1505static int atmel_prepare_tx_pdc(struct uart_port *port)
1506{
1507 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1508 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1509 struct circ_buf *xmit = &port->state->xmit;
1510
1511 pdc->buf = xmit->buf;
1512 pdc->dma_addr = dma_map_single(port->dev,
1513 pdc->buf,
1514 UART_XMIT_SIZE,
1515 DMA_TO_DEVICE);
1516 pdc->dma_size = UART_XMIT_SIZE;
1517 pdc->ofs = 0;
1518
1519 return 0;
1520}
1521
1522static void atmel_rx_from_ring(struct uart_port *port)
1523{
1524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1525 struct circ_buf *ring = &atmel_port->rx_ring;
1526 unsigned int status;
1527 u8 flg;
1528
1529 while (ring->head != ring->tail) {
1530 struct atmel_uart_char c;
1531
1532 /* Make sure c is loaded after head. */
1533 smp_rmb();
1534
1535 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1536
1537 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1538
1539 port->icount.rx++;
1540 status = c.status;
1541 flg = TTY_NORMAL;
1542
1543 /*
1544 * note that the error handling code is
1545 * out of the main execution path
1546 */
1547 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1548 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1549 if (status & ATMEL_US_RXBRK) {
1550 /* ignore side-effect */
1551 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1552
1553 port->icount.brk++;
1554 if (uart_handle_break(port))
1555 continue;
1556 }
1557 if (status & ATMEL_US_PARE)
1558 port->icount.parity++;
1559 if (status & ATMEL_US_FRAME)
1560 port->icount.frame++;
1561 if (status & ATMEL_US_OVRE)
1562 port->icount.overrun++;
1563
1564 status &= port->read_status_mask;
1565
1566 if (status & ATMEL_US_RXBRK)
1567 flg = TTY_BREAK;
1568 else if (status & ATMEL_US_PARE)
1569 flg = TTY_PARITY;
1570 else if (status & ATMEL_US_FRAME)
1571 flg = TTY_FRAME;
1572 }
1573
1574
1575 if (uart_handle_sysrq_char(port, c.ch))
1576 continue;
1577
1578 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1579 }
1580
1581 tty_flip_buffer_push(&port->state->port);
1582}
1583
1584static void atmel_release_rx_pdc(struct uart_port *port)
1585{
1586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1587 int i;
1588
1589 for (i = 0; i < 2; i++) {
1590 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1591
1592 dma_unmap_single(port->dev,
1593 pdc->dma_addr,
1594 pdc->dma_size,
1595 DMA_FROM_DEVICE);
1596 kfree(pdc->buf);
1597 }
1598}
1599
1600static void atmel_rx_from_pdc(struct uart_port *port)
1601{
1602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1603 struct tty_port *tport = &port->state->port;
1604 struct atmel_dma_buffer *pdc;
1605 int rx_idx = atmel_port->pdc_rx_idx;
1606 unsigned int head;
1607 unsigned int tail;
1608 unsigned int count;
1609
1610 do {
1611 /* Reset the UART timeout early so that we don't miss one */
1612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1613
1614 pdc = &atmel_port->pdc_rx[rx_idx];
1615 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1616 tail = pdc->ofs;
1617
1618 /* If the PDC has switched buffers, RPR won't contain
1619 * any address within the current buffer. Since head
1620 * is unsigned, we just need a one-way comparison to
1621 * find out.
1622 *
1623 * In this case, we just need to consume the entire
1624 * buffer and resubmit it for DMA. This will clear the
1625 * ENDRX bit as well, so that we can safely re-enable
1626 * all interrupts below.
1627 */
1628 head = min(head, pdc->dma_size);
1629
1630 if (likely(head != tail)) {
1631 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1632 pdc->dma_size, DMA_FROM_DEVICE);
1633
1634 /*
1635 * head will only wrap around when we recycle
1636 * the DMA buffer, and when that happens, we
1637 * explicitly set tail to 0. So head will
1638 * always be greater than tail.
1639 */
1640 count = head - tail;
1641
1642 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1643 count);
1644
1645 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1646 pdc->dma_size, DMA_FROM_DEVICE);
1647
1648 port->icount.rx += count;
1649 pdc->ofs = head;
1650 }
1651
1652 /*
1653 * If the current buffer is full, we need to check if
1654 * the next one contains any additional data.
1655 */
1656 if (head >= pdc->dma_size) {
1657 pdc->ofs = 0;
1658 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1659 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1660
1661 rx_idx = !rx_idx;
1662 atmel_port->pdc_rx_idx = rx_idx;
1663 }
1664 } while (head >= pdc->dma_size);
1665
1666 tty_flip_buffer_push(tport);
1667
1668 atmel_uart_writel(port, ATMEL_US_IER,
1669 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1670}
1671
1672static int atmel_prepare_rx_pdc(struct uart_port *port)
1673{
1674 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1675 int i;
1676
1677 for (i = 0; i < 2; i++) {
1678 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1679
1680 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1681 if (pdc->buf == NULL) {
1682 if (i != 0) {
1683 dma_unmap_single(port->dev,
1684 atmel_port->pdc_rx[0].dma_addr,
1685 PDC_BUFFER_SIZE,
1686 DMA_FROM_DEVICE);
1687 kfree(atmel_port->pdc_rx[0].buf);
1688 }
1689 atmel_port->use_pdc_rx = false;
1690 return -ENOMEM;
1691 }
1692 pdc->dma_addr = dma_map_single(port->dev,
1693 pdc->buf,
1694 PDC_BUFFER_SIZE,
1695 DMA_FROM_DEVICE);
1696 pdc->dma_size = PDC_BUFFER_SIZE;
1697 pdc->ofs = 0;
1698 }
1699
1700 atmel_port->pdc_rx_idx = 0;
1701
1702 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1703 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1704
1705 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1706 atmel_port->pdc_rx[1].dma_addr);
1707 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1708
1709 return 0;
1710}
1711
1712/*
1713 * tasklet handling tty stuff outside the interrupt handler.
1714 */
1715static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1716{
1717 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1718 tasklet_rx);
1719 struct uart_port *port = &atmel_port->uart;
1720
1721 /* The interrupt handler does not take the lock */
1722 uart_port_lock(port);
1723 atmel_port->schedule_rx(port);
1724 uart_port_unlock(port);
1725}
1726
1727static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1728{
1729 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1730 tasklet_tx);
1731 struct uart_port *port = &atmel_port->uart;
1732
1733 /* The interrupt handler does not take the lock */
1734 uart_port_lock(port);
1735 atmel_port->schedule_tx(port);
1736 uart_port_unlock(port);
1737}
1738
1739static void atmel_init_property(struct atmel_uart_port *atmel_port,
1740 struct platform_device *pdev)
1741{
1742 struct device_node *np = pdev->dev.of_node;
1743
1744 /* DMA/PDC usage specification */
1745 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1746 if (of_property_read_bool(np, "dmas")) {
1747 atmel_port->use_dma_rx = true;
1748 atmel_port->use_pdc_rx = false;
1749 } else {
1750 atmel_port->use_dma_rx = false;
1751 atmel_port->use_pdc_rx = true;
1752 }
1753 } else {
1754 atmel_port->use_dma_rx = false;
1755 atmel_port->use_pdc_rx = false;
1756 }
1757
1758 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1759 if (of_property_read_bool(np, "dmas")) {
1760 atmel_port->use_dma_tx = true;
1761 atmel_port->use_pdc_tx = false;
1762 } else {
1763 atmel_port->use_dma_tx = false;
1764 atmel_port->use_pdc_tx = true;
1765 }
1766 } else {
1767 atmel_port->use_dma_tx = false;
1768 atmel_port->use_pdc_tx = false;
1769 }
1770}
1771
1772static void atmel_set_ops(struct uart_port *port)
1773{
1774 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1775
1776 if (atmel_use_dma_rx(port)) {
1777 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1778 atmel_port->schedule_rx = &atmel_rx_from_dma;
1779 atmel_port->release_rx = &atmel_release_rx_dma;
1780 } else if (atmel_use_pdc_rx(port)) {
1781 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1782 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1783 atmel_port->release_rx = &atmel_release_rx_pdc;
1784 } else {
1785 atmel_port->prepare_rx = NULL;
1786 atmel_port->schedule_rx = &atmel_rx_from_ring;
1787 atmel_port->release_rx = NULL;
1788 }
1789
1790 if (atmel_use_dma_tx(port)) {
1791 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1792 atmel_port->schedule_tx = &atmel_tx_dma;
1793 atmel_port->release_tx = &atmel_release_tx_dma;
1794 } else if (atmel_use_pdc_tx(port)) {
1795 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1796 atmel_port->schedule_tx = &atmel_tx_pdc;
1797 atmel_port->release_tx = &atmel_release_tx_pdc;
1798 } else {
1799 atmel_port->prepare_tx = NULL;
1800 atmel_port->schedule_tx = &atmel_tx_chars;
1801 atmel_port->release_tx = NULL;
1802 }
1803}
1804
1805/*
1806 * Get ip name usart or uart
1807 */
1808static void atmel_get_ip_name(struct uart_port *port)
1809{
1810 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1811 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1812 u32 version;
1813 u32 usart, dbgu_uart, new_uart;
1814 /* ASCII decoding for IP version */
1815 usart = 0x55534152; /* USAR(T) */
1816 dbgu_uart = 0x44424755; /* DBGU */
1817 new_uart = 0x55415254; /* UART */
1818
1819 /*
1820 * Only USART devices from at91sam9260 SOC implement fractional
1821 * baudrate. It is available for all asynchronous modes, with the
1822 * following restriction: the sampling clock's duty cycle is not
1823 * constant.
1824 */
1825 atmel_port->has_frac_baudrate = false;
1826 atmel_port->has_hw_timer = false;
1827 atmel_port->is_usart = false;
1828
1829 if (name == new_uart) {
1830 dev_dbg(port->dev, "Uart with hw timer");
1831 atmel_port->has_hw_timer = true;
1832 atmel_port->rtor = ATMEL_UA_RTOR;
1833 } else if (name == usart) {
1834 dev_dbg(port->dev, "Usart\n");
1835 atmel_port->has_frac_baudrate = true;
1836 atmel_port->has_hw_timer = true;
1837 atmel_port->is_usart = true;
1838 atmel_port->rtor = ATMEL_US_RTOR;
1839 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1840 switch (version) {
1841 case 0x814: /* sama5d2 */
1842 fallthrough;
1843 case 0x701: /* sama5d4 */
1844 atmel_port->fidi_min = 3;
1845 atmel_port->fidi_max = 65535;
1846 break;
1847 case 0x502: /* sam9x5, sama5d3 */
1848 atmel_port->fidi_min = 3;
1849 atmel_port->fidi_max = 2047;
1850 break;
1851 default:
1852 atmel_port->fidi_min = 1;
1853 atmel_port->fidi_max = 2047;
1854 }
1855 } else if (name == dbgu_uart) {
1856 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1857 } else {
1858 /* fallback for older SoCs: use version field */
1859 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1860 switch (version) {
1861 case 0x302:
1862 case 0x10213:
1863 case 0x10302:
1864 dev_dbg(port->dev, "This version is usart\n");
1865 atmel_port->has_frac_baudrate = true;
1866 atmel_port->has_hw_timer = true;
1867 atmel_port->is_usart = true;
1868 atmel_port->rtor = ATMEL_US_RTOR;
1869 break;
1870 case 0x203:
1871 case 0x10202:
1872 dev_dbg(port->dev, "This version is uart\n");
1873 break;
1874 default:
1875 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1876 }
1877 }
1878}
1879
1880/*
1881 * Perform initialization and enable port for reception
1882 */
1883static int atmel_startup(struct uart_port *port)
1884{
1885 struct platform_device *pdev = to_platform_device(port->dev);
1886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1887 int retval;
1888
1889 /*
1890 * Ensure that no interrupts are enabled otherwise when
1891 * request_irq() is called we could get stuck trying to
1892 * handle an unexpected interrupt
1893 */
1894 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1895 atmel_port->ms_irq_enabled = false;
1896
1897 /*
1898 * Allocate the IRQ
1899 */
1900 retval = request_irq(port->irq, atmel_interrupt,
1901 IRQF_SHARED | IRQF_COND_SUSPEND,
1902 dev_name(&pdev->dev), port);
1903 if (retval) {
1904 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1905 return retval;
1906 }
1907
1908 atomic_set(&atmel_port->tasklet_shutdown, 0);
1909 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1910 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1911
1912 /*
1913 * Initialize DMA (if necessary)
1914 */
1915 atmel_init_property(atmel_port, pdev);
1916 atmel_set_ops(port);
1917
1918 if (atmel_port->prepare_rx) {
1919 retval = atmel_port->prepare_rx(port);
1920 if (retval < 0)
1921 atmel_set_ops(port);
1922 }
1923
1924 if (atmel_port->prepare_tx) {
1925 retval = atmel_port->prepare_tx(port);
1926 if (retval < 0)
1927 atmel_set_ops(port);
1928 }
1929
1930 /*
1931 * Enable FIFO when available
1932 */
1933 if (atmel_port->fifo_size) {
1934 unsigned int txrdym = ATMEL_US_ONE_DATA;
1935 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1936 unsigned int fmr;
1937
1938 atmel_uart_writel(port, ATMEL_US_CR,
1939 ATMEL_US_FIFOEN |
1940 ATMEL_US_RXFCLR |
1941 ATMEL_US_TXFLCLR);
1942
1943 if (atmel_use_dma_tx(port))
1944 txrdym = ATMEL_US_FOUR_DATA;
1945
1946 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1947 if (atmel_port->rts_high &&
1948 atmel_port->rts_low)
1949 fmr |= ATMEL_US_FRTSC |
1950 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1951 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1952
1953 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1954 }
1955
1956 /* Save current CSR for comparison in atmel_tasklet_func() */
1957 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1958
1959 /*
1960 * Finally, enable the serial port
1961 */
1962 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1963 /* enable xmit & rcvr */
1964 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1965 atmel_port->tx_stopped = false;
1966
1967 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1968
1969 if (atmel_use_pdc_rx(port)) {
1970 /* set UART timeout */
1971 if (!atmel_port->has_hw_timer) {
1972 mod_timer(&atmel_port->uart_timer,
1973 jiffies + uart_poll_timeout(port));
1974 /* set USART timeout */
1975 } else {
1976 atmel_uart_writel(port, atmel_port->rtor,
1977 PDC_RX_TIMEOUT);
1978 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1979
1980 atmel_uart_writel(port, ATMEL_US_IER,
1981 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1982 }
1983 /* enable PDC controller */
1984 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1985 } else if (atmel_use_dma_rx(port)) {
1986 /* set UART timeout */
1987 if (!atmel_port->has_hw_timer) {
1988 mod_timer(&atmel_port->uart_timer,
1989 jiffies + uart_poll_timeout(port));
1990 /* set USART timeout */
1991 } else {
1992 atmel_uart_writel(port, atmel_port->rtor,
1993 PDC_RX_TIMEOUT);
1994 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1995
1996 atmel_uart_writel(port, ATMEL_US_IER,
1997 ATMEL_US_TIMEOUT);
1998 }
1999 } else {
2000 /* enable receive only */
2001 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2002 }
2003
2004 return 0;
2005}
2006
2007/*
2008 * Flush any TX data submitted for DMA. Called when the TX circular
2009 * buffer is reset.
2010 */
2011static void atmel_flush_buffer(struct uart_port *port)
2012{
2013 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2014
2015 if (atmel_use_pdc_tx(port)) {
2016 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2017 atmel_port->pdc_tx.ofs = 0;
2018 }
2019 /*
2020 * in uart_flush_buffer(), the xmit circular buffer has just
2021 * been cleared, so we have to reset tx_len accordingly.
2022 */
2023 atmel_port->tx_len = 0;
2024}
2025
2026/*
2027 * Disable the port
2028 */
2029static void atmel_shutdown(struct uart_port *port)
2030{
2031 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2032
2033 /* Disable modem control lines interrupts */
2034 atmel_disable_ms(port);
2035
2036 /* Disable interrupts at device level */
2037 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2038
2039 /* Prevent spurious interrupts from scheduling the tasklet */
2040 atomic_inc(&atmel_port->tasklet_shutdown);
2041
2042 /*
2043 * Prevent any tasklets being scheduled during
2044 * cleanup
2045 */
2046 del_timer_sync(&atmel_port->uart_timer);
2047
2048 /* Make sure that no interrupt is on the fly */
2049 synchronize_irq(port->irq);
2050
2051 /*
2052 * Clear out any scheduled tasklets before
2053 * we destroy the buffers
2054 */
2055 tasklet_kill(&atmel_port->tasklet_rx);
2056 tasklet_kill(&atmel_port->tasklet_tx);
2057
2058 /*
2059 * Ensure everything is stopped and
2060 * disable port and break condition.
2061 */
2062 atmel_stop_rx(port);
2063 atmel_stop_tx(port);
2064
2065 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2066
2067 /*
2068 * Shut-down the DMA.
2069 */
2070 if (atmel_port->release_rx)
2071 atmel_port->release_rx(port);
2072 if (atmel_port->release_tx)
2073 atmel_port->release_tx(port);
2074
2075 /*
2076 * Reset ring buffer pointers
2077 */
2078 atmel_port->rx_ring.head = 0;
2079 atmel_port->rx_ring.tail = 0;
2080
2081 /*
2082 * Free the interrupts
2083 */
2084 free_irq(port->irq, port);
2085
2086 atmel_flush_buffer(port);
2087}
2088
2089/*
2090 * Power / Clock management.
2091 */
2092static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2093 unsigned int oldstate)
2094{
2095 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2096
2097 switch (state) {
2098 case UART_PM_STATE_ON:
2099 /*
2100 * Enable the peripheral clock for this serial port.
2101 * This is called on uart_open() or a resume event.
2102 */
2103 clk_prepare_enable(atmel_port->clk);
2104
2105 /* re-enable interrupts if we disabled some on suspend */
2106 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2107 break;
2108 case UART_PM_STATE_OFF:
2109 /* Back up the interrupt mask and disable all interrupts */
2110 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2111 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2112
2113 /*
2114 * Disable the peripheral clock for this serial port.
2115 * This is called on uart_close() or a suspend event.
2116 */
2117 clk_disable_unprepare(atmel_port->clk);
2118 if (__clk_is_enabled(atmel_port->gclk))
2119 clk_disable_unprepare(atmel_port->gclk);
2120 break;
2121 default:
2122 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2123 }
2124}
2125
2126/*
2127 * Change the port parameters
2128 */
2129static void atmel_set_termios(struct uart_port *port,
2130 struct ktermios *termios,
2131 const struct ktermios *old)
2132{
2133 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2134 unsigned long flags;
2135 unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
2136 unsigned int baud, actual_baud, gclk_rate;
2137 int ret;
2138
2139 /* save the current mode register */
2140 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2141
2142 /* reset the mode, clock divisor, parity, stop bits and data size */
2143 if (atmel_port->is_usart)
2144 mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
2145 ATMEL_US_USCLKS | ATMEL_US_USMODE);
2146 else
2147 mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
2148
2149 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2150
2151 /* byte size */
2152 switch (termios->c_cflag & CSIZE) {
2153 case CS5:
2154 mode |= ATMEL_US_CHRL_5;
2155 break;
2156 case CS6:
2157 mode |= ATMEL_US_CHRL_6;
2158 break;
2159 case CS7:
2160 mode |= ATMEL_US_CHRL_7;
2161 break;
2162 default:
2163 mode |= ATMEL_US_CHRL_8;
2164 break;
2165 }
2166
2167 /* stop bits */
2168 if (termios->c_cflag & CSTOPB)
2169 mode |= ATMEL_US_NBSTOP_2;
2170
2171 /* parity */
2172 if (termios->c_cflag & PARENB) {
2173 /* Mark or Space parity */
2174 if (termios->c_cflag & CMSPAR) {
2175 if (termios->c_cflag & PARODD)
2176 mode |= ATMEL_US_PAR_MARK;
2177 else
2178 mode |= ATMEL_US_PAR_SPACE;
2179 } else if (termios->c_cflag & PARODD)
2180 mode |= ATMEL_US_PAR_ODD;
2181 else
2182 mode |= ATMEL_US_PAR_EVEN;
2183 } else
2184 mode |= ATMEL_US_PAR_NONE;
2185
2186 uart_port_lock_irqsave(port, &flags);
2187
2188 port->read_status_mask = ATMEL_US_OVRE;
2189 if (termios->c_iflag & INPCK)
2190 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2191 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2192 port->read_status_mask |= ATMEL_US_RXBRK;
2193
2194 if (atmel_use_pdc_rx(port))
2195 /* need to enable error interrupts */
2196 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2197
2198 /*
2199 * Characters to ignore
2200 */
2201 port->ignore_status_mask = 0;
2202 if (termios->c_iflag & IGNPAR)
2203 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2204 if (termios->c_iflag & IGNBRK) {
2205 port->ignore_status_mask |= ATMEL_US_RXBRK;
2206 /*
2207 * If we're ignoring parity and break indicators,
2208 * ignore overruns too (for real raw support).
2209 */
2210 if (termios->c_iflag & IGNPAR)
2211 port->ignore_status_mask |= ATMEL_US_OVRE;
2212 }
2213 /* TODO: Ignore all characters if CREAD is set.*/
2214
2215 /* update the per-port timeout */
2216 uart_update_timeout(port, termios->c_cflag, baud);
2217
2218 /*
2219 * save/disable interrupts. The tty layer will ensure that the
2220 * transmitter is empty if requested by the caller, so there's
2221 * no need to wait for it here.
2222 */
2223 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2224 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2225
2226 /* disable receiver and transmitter */
2227 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2228 atmel_port->tx_stopped = true;
2229
2230 /* mode */
2231 if (port->rs485.flags & SER_RS485_ENABLED) {
2232 atmel_uart_writel(port, ATMEL_US_TTGR,
2233 port->rs485.delay_rts_after_send);
2234 mode |= ATMEL_US_USMODE_RS485;
2235 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2236 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2237 /* select mck clock, and output */
2238 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2239 /* set max iterations */
2240 mode |= ATMEL_US_MAX_ITER(3);
2241 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2242 == SER_ISO7816_T(0))
2243 mode |= ATMEL_US_USMODE_ISO7816_T0;
2244 else
2245 mode |= ATMEL_US_USMODE_ISO7816_T1;
2246 } else if (termios->c_cflag & CRTSCTS) {
2247 /* RS232 with hardware handshake (RTS/CTS) */
2248 if (atmel_use_fifo(port) &&
2249 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2250 /*
2251 * with ATMEL_US_USMODE_HWHS set, the controller will
2252 * be able to drive the RTS pin high/low when the RX
2253 * FIFO is above RXFTHRES/below RXFTHRES2.
2254 * It will also disable the transmitter when the CTS
2255 * pin is high.
2256 * This mode is not activated if CTS pin is a GPIO
2257 * because in this case, the transmitter is always
2258 * disabled (there must be an internal pull-up
2259 * responsible for this behaviour).
2260 * If the RTS pin is a GPIO, the controller won't be
2261 * able to drive it according to the FIFO thresholds,
2262 * but it will be handled by the driver.
2263 */
2264 mode |= ATMEL_US_USMODE_HWHS;
2265 } else {
2266 /*
2267 * For platforms without FIFO, the flow control is
2268 * handled by the driver.
2269 */
2270 mode |= ATMEL_US_USMODE_NORMAL;
2271 }
2272 } else {
2273 /* RS232 without hadware handshake */
2274 mode |= ATMEL_US_USMODE_NORMAL;
2275 }
2276
2277 /*
2278 * Set the baud rate:
2279 * Fractional baudrate allows to setup output frequency more
2280 * accurately. This feature is enabled only when using normal mode.
2281 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2282 * Currently, OVER is always set to 0 so we get
2283 * baudrate = selected clock / (16 * (CD + FP / 8))
2284 * then
2285 * 8 CD + FP = selected clock / (2 * baudrate)
2286 */
2287 if (atmel_port->has_frac_baudrate) {
2288 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2289 cd = div >> 3;
2290 fp = div & ATMEL_US_FP_MASK;
2291 } else {
2292 cd = uart_get_divisor(port, baud);
2293 }
2294
2295 /*
2296 * If the current value of the Clock Divisor surpasses the 16 bit
2297 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
2298 * Clock implicitly divided by 8.
2299 * If the IP is UART however, keep the highest possible value for
2300 * the CD and avoid needless division of CD, since UART IP's do not
2301 * support implicit division of the Peripheral Clock.
2302 */
2303 if (atmel_port->is_usart && cd > ATMEL_US_CD) {
2304 cd /= 8;
2305 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2306 } else {
2307 cd = min_t(unsigned int, cd, ATMEL_US_CD);
2308 }
2309
2310 /*
2311 * If there is no Fractional Part, there is a high chance that
2312 * we may be able to generate a baudrate closer to the desired one
2313 * if we use the GCLK as the clock source driving the baudrate
2314 * generator.
2315 */
2316 if (!atmel_port->has_frac_baudrate) {
2317 if (__clk_is_enabled(atmel_port->gclk))
2318 clk_disable_unprepare(atmel_port->gclk);
2319 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
2320 actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
2321 if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
2322 abs(atmel_error_rate(baud, gclk_rate / 16))) {
2323 clk_set_rate(atmel_port->gclk, 16 * baud);
2324 ret = clk_prepare_enable(atmel_port->gclk);
2325 if (ret)
2326 goto gclk_fail;
2327
2328 if (atmel_port->is_usart) {
2329 mode &= ~ATMEL_US_USCLKS;
2330 mode |= ATMEL_US_USCLKS_GCLK;
2331 } else {
2332 mode |= ATMEL_UA_BRSRCCK;
2333 }
2334
2335 /*
2336 * Set the Clock Divisor for GCLK to 1.
2337 * Since we were able to generate the smallest
2338 * multiple of the desired baudrate times 16,
2339 * then we surely can generate a bigger multiple
2340 * with the exact error rate for an equally increased
2341 * CD. Thus no need to take into account
2342 * a higher value for CD.
2343 */
2344 cd = 1;
2345 }
2346 }
2347
2348gclk_fail:
2349 quot = cd | fp << ATMEL_US_FP_OFFSET;
2350
2351 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2352 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2353
2354 /* set the mode, clock divisor, parity, stop bits and data size */
2355 atmel_uart_writel(port, ATMEL_US_MR, mode);
2356
2357 /*
2358 * when switching the mode, set the RTS line state according to the
2359 * new mode, otherwise keep the former state
2360 */
2361 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2362 unsigned int rts_state;
2363
2364 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2365 /* let the hardware control the RTS line */
2366 rts_state = ATMEL_US_RTSDIS;
2367 } else {
2368 /* force RTS line to low level */
2369 rts_state = ATMEL_US_RTSEN;
2370 }
2371
2372 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2373 }
2374
2375 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2376 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2377 atmel_port->tx_stopped = false;
2378
2379 /* restore interrupts */
2380 atmel_uart_writel(port, ATMEL_US_IER, imr);
2381
2382 /* CTS flow-control and modem-status interrupts */
2383 if (UART_ENABLE_MS(port, termios->c_cflag))
2384 atmel_enable_ms(port);
2385 else
2386 atmel_disable_ms(port);
2387
2388 uart_port_unlock_irqrestore(port, flags);
2389}
2390
2391static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2392{
2393 if (termios->c_line == N_PPS) {
2394 port->flags |= UPF_HARDPPS_CD;
2395 uart_port_lock_irq(port);
2396 atmel_enable_ms(port);
2397 uart_port_unlock_irq(port);
2398 } else {
2399 port->flags &= ~UPF_HARDPPS_CD;
2400 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2401 uart_port_lock_irq(port);
2402 atmel_disable_ms(port);
2403 uart_port_unlock_irq(port);
2404 }
2405 }
2406}
2407
2408/*
2409 * Return string describing the specified port
2410 */
2411static const char *atmel_type(struct uart_port *port)
2412{
2413 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2414}
2415
2416/*
2417 * Release the memory region(s) being used by 'port'.
2418 */
2419static void atmel_release_port(struct uart_port *port)
2420{
2421 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2422 int size = resource_size(mpdev->resource);
2423
2424 release_mem_region(port->mapbase, size);
2425
2426 if (port->flags & UPF_IOREMAP) {
2427 iounmap(port->membase);
2428 port->membase = NULL;
2429 }
2430}
2431
2432/*
2433 * Request the memory region(s) being used by 'port'.
2434 */
2435static int atmel_request_port(struct uart_port *port)
2436{
2437 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2438 int size = resource_size(mpdev->resource);
2439
2440 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2441 return -EBUSY;
2442
2443 if (port->flags & UPF_IOREMAP) {
2444 port->membase = ioremap(port->mapbase, size);
2445 if (port->membase == NULL) {
2446 release_mem_region(port->mapbase, size);
2447 return -ENOMEM;
2448 }
2449 }
2450
2451 return 0;
2452}
2453
2454/*
2455 * Configure/autoconfigure the port.
2456 */
2457static void atmel_config_port(struct uart_port *port, int flags)
2458{
2459 if (flags & UART_CONFIG_TYPE) {
2460 port->type = PORT_ATMEL;
2461 atmel_request_port(port);
2462 }
2463}
2464
2465/*
2466 * Verify the new serial_struct (for TIOCSSERIAL).
2467 */
2468static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2469{
2470 int ret = 0;
2471 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2472 ret = -EINVAL;
2473 if (port->irq != ser->irq)
2474 ret = -EINVAL;
2475 if (ser->io_type != SERIAL_IO_MEM)
2476 ret = -EINVAL;
2477 if (port->uartclk / 16 != ser->baud_base)
2478 ret = -EINVAL;
2479 if (port->mapbase != (unsigned long)ser->iomem_base)
2480 ret = -EINVAL;
2481 if (port->iobase != ser->port)
2482 ret = -EINVAL;
2483 if (ser->hub6 != 0)
2484 ret = -EINVAL;
2485 return ret;
2486}
2487
2488#ifdef CONFIG_CONSOLE_POLL
2489static int atmel_poll_get_char(struct uart_port *port)
2490{
2491 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2492 cpu_relax();
2493
2494 return atmel_uart_read_char(port);
2495}
2496
2497static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2498{
2499 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2500 cpu_relax();
2501
2502 atmel_uart_write_char(port, ch);
2503}
2504#endif
2505
2506static const struct uart_ops atmel_pops = {
2507 .tx_empty = atmel_tx_empty,
2508 .set_mctrl = atmel_set_mctrl,
2509 .get_mctrl = atmel_get_mctrl,
2510 .stop_tx = atmel_stop_tx,
2511 .start_tx = atmel_start_tx,
2512 .stop_rx = atmel_stop_rx,
2513 .enable_ms = atmel_enable_ms,
2514 .break_ctl = atmel_break_ctl,
2515 .startup = atmel_startup,
2516 .shutdown = atmel_shutdown,
2517 .flush_buffer = atmel_flush_buffer,
2518 .set_termios = atmel_set_termios,
2519 .set_ldisc = atmel_set_ldisc,
2520 .type = atmel_type,
2521 .release_port = atmel_release_port,
2522 .request_port = atmel_request_port,
2523 .config_port = atmel_config_port,
2524 .verify_port = atmel_verify_port,
2525 .pm = atmel_serial_pm,
2526#ifdef CONFIG_CONSOLE_POLL
2527 .poll_get_char = atmel_poll_get_char,
2528 .poll_put_char = atmel_poll_put_char,
2529#endif
2530};
2531
2532static const struct serial_rs485 atmel_rs485_supported = {
2533 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
2534 .delay_rts_before_send = 1,
2535 .delay_rts_after_send = 1,
2536};
2537
2538/*
2539 * Configure the port from the platform device resource info.
2540 */
2541static int atmel_init_port(struct atmel_uart_port *atmel_port,
2542 struct platform_device *pdev)
2543{
2544 int ret;
2545 struct uart_port *port = &atmel_port->uart;
2546 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2547
2548 atmel_init_property(atmel_port, pdev);
2549 atmel_set_ops(port);
2550
2551 port->iotype = UPIO_MEM;
2552 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2553 port->ops = &atmel_pops;
2554 port->fifosize = 1;
2555 port->dev = &pdev->dev;
2556 port->mapbase = mpdev->resource[0].start;
2557 port->irq = platform_get_irq(mpdev, 0);
2558 port->rs485_config = atmel_config_rs485;
2559 port->rs485_supported = atmel_rs485_supported;
2560 port->iso7816_config = atmel_config_iso7816;
2561 port->membase = NULL;
2562
2563 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2564
2565 ret = uart_get_rs485_mode(port);
2566 if (ret)
2567 return ret;
2568
2569 port->uartclk = clk_get_rate(atmel_port->clk);
2570
2571 /*
2572 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2573 * ENDTX|TXBUFE
2574 */
2575 if (atmel_uart_is_half_duplex(port))
2576 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2577 else if (atmel_use_pdc_tx(port)) {
2578 port->fifosize = PDC_BUFFER_SIZE;
2579 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2580 } else {
2581 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2582 }
2583
2584 return 0;
2585}
2586
2587#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2588static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
2589{
2590 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2591 cpu_relax();
2592 atmel_uart_write_char(port, ch);
2593}
2594
2595/*
2596 * Interrupts are disabled on entering
2597 */
2598static void atmel_console_write(struct console *co, const char *s, u_int count)
2599{
2600 struct uart_port *port = &atmel_ports[co->index].uart;
2601 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2602 unsigned int status, imr;
2603 unsigned int pdc_tx;
2604
2605 /*
2606 * First, save IMR and then disable interrupts
2607 */
2608 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2609 atmel_uart_writel(port, ATMEL_US_IDR,
2610 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2611
2612 /* Store PDC transmit status and disable it */
2613 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2614 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2615
2616 /* Make sure that tx path is actually able to send characters */
2617 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2618 atmel_port->tx_stopped = false;
2619
2620 uart_console_write(port, s, count, atmel_console_putchar);
2621
2622 /*
2623 * Finally, wait for transmitter to become empty
2624 * and restore IMR
2625 */
2626 do {
2627 status = atmel_uart_readl(port, ATMEL_US_CSR);
2628 } while (!(status & ATMEL_US_TXRDY));
2629
2630 /* Restore PDC transmit status */
2631 if (pdc_tx)
2632 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2633
2634 /* set interrupts back the way they were */
2635 atmel_uart_writel(port, ATMEL_US_IER, imr);
2636}
2637
2638/*
2639 * If the port was already initialised (eg, by a boot loader),
2640 * try to determine the current setup.
2641 */
2642static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2643 int *parity, int *bits)
2644{
2645 unsigned int mr, quot;
2646
2647 /*
2648 * If the baud rate generator isn't running, the port wasn't
2649 * initialized by the boot loader.
2650 */
2651 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2652 if (!quot)
2653 return;
2654
2655 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2656 if (mr == ATMEL_US_CHRL_8)
2657 *bits = 8;
2658 else
2659 *bits = 7;
2660
2661 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2662 if (mr == ATMEL_US_PAR_EVEN)
2663 *parity = 'e';
2664 else if (mr == ATMEL_US_PAR_ODD)
2665 *parity = 'o';
2666
2667 *baud = port->uartclk / (16 * quot);
2668}
2669
2670static int __init atmel_console_setup(struct console *co, char *options)
2671{
2672 struct uart_port *port = &atmel_ports[co->index].uart;
2673 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2674 int baud = 115200;
2675 int bits = 8;
2676 int parity = 'n';
2677 int flow = 'n';
2678
2679 if (port->membase == NULL) {
2680 /* Port not initialized yet - delay setup */
2681 return -ENODEV;
2682 }
2683
2684 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2685 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2686 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2687 atmel_port->tx_stopped = false;
2688
2689 if (options)
2690 uart_parse_options(options, &baud, &parity, &bits, &flow);
2691 else
2692 atmel_console_get_options(port, &baud, &parity, &bits);
2693
2694 return uart_set_options(port, co, baud, parity, bits, flow);
2695}
2696
2697static struct uart_driver atmel_uart;
2698
2699static struct console atmel_console = {
2700 .name = ATMEL_DEVICENAME,
2701 .write = atmel_console_write,
2702 .device = uart_console_device,
2703 .setup = atmel_console_setup,
2704 .flags = CON_PRINTBUFFER,
2705 .index = -1,
2706 .data = &atmel_uart,
2707};
2708
2709static void atmel_serial_early_write(struct console *con, const char *s,
2710 unsigned int n)
2711{
2712 struct earlycon_device *dev = con->data;
2713
2714 uart_console_write(&dev->port, s, n, atmel_console_putchar);
2715}
2716
2717static int __init atmel_early_console_setup(struct earlycon_device *device,
2718 const char *options)
2719{
2720 if (!device->port.membase)
2721 return -ENODEV;
2722
2723 device->con->write = atmel_serial_early_write;
2724
2725 return 0;
2726}
2727
2728OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2729 atmel_early_console_setup);
2730OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2731 atmel_early_console_setup);
2732
2733#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2734
2735#else
2736#define ATMEL_CONSOLE_DEVICE NULL
2737#endif
2738
2739static struct uart_driver atmel_uart = {
2740 .owner = THIS_MODULE,
2741 .driver_name = "atmel_serial",
2742 .dev_name = ATMEL_DEVICENAME,
2743 .major = SERIAL_ATMEL_MAJOR,
2744 .minor = MINOR_START,
2745 .nr = ATMEL_MAX_UART,
2746 .cons = ATMEL_CONSOLE_DEVICE,
2747};
2748
2749static bool atmel_serial_clk_will_stop(void)
2750{
2751#ifdef CONFIG_ARCH_AT91
2752 return at91_suspend_entering_slow_clock();
2753#else
2754 return false;
2755#endif
2756}
2757
2758static int __maybe_unused atmel_serial_suspend(struct device *dev)
2759{
2760 struct uart_port *port = dev_get_drvdata(dev);
2761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2762
2763 if (uart_console(port) && console_suspend_enabled) {
2764 /* Drain the TX shifter */
2765 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2766 ATMEL_US_TXEMPTY))
2767 cpu_relax();
2768 }
2769
2770 if (uart_console(port) && !console_suspend_enabled) {
2771 /* Cache register values as we won't get a full shutdown/startup
2772 * cycle
2773 */
2774 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2775 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2776 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2777 atmel_port->cache.rtor = atmel_uart_readl(port,
2778 atmel_port->rtor);
2779 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2780 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2781 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2782 }
2783
2784 /* we can not wake up if we're running on slow clock */
2785 atmel_port->may_wakeup = device_may_wakeup(dev);
2786 if (atmel_serial_clk_will_stop()) {
2787 unsigned long flags;
2788
2789 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2790 atmel_port->suspended = true;
2791 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2792 device_set_wakeup_enable(dev, 0);
2793 }
2794
2795 uart_suspend_port(&atmel_uart, port);
2796
2797 return 0;
2798}
2799
2800static int __maybe_unused atmel_serial_resume(struct device *dev)
2801{
2802 struct uart_port *port = dev_get_drvdata(dev);
2803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2804 unsigned long flags;
2805
2806 if (uart_console(port) && !console_suspend_enabled) {
2807 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2808 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2809 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2810 atmel_uart_writel(port, atmel_port->rtor,
2811 atmel_port->cache.rtor);
2812 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2813
2814 if (atmel_port->fifo_size) {
2815 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2816 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2817 atmel_uart_writel(port, ATMEL_US_FMR,
2818 atmel_port->cache.fmr);
2819 atmel_uart_writel(port, ATMEL_US_FIER,
2820 atmel_port->cache.fimr);
2821 }
2822 atmel_start_rx(port);
2823 }
2824
2825 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2826 if (atmel_port->pending) {
2827 atmel_handle_receive(port, atmel_port->pending);
2828 atmel_handle_status(port, atmel_port->pending,
2829 atmel_port->pending_status);
2830 atmel_handle_transmit(port, atmel_port->pending);
2831 atmel_port->pending = 0;
2832 }
2833 atmel_port->suspended = false;
2834 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2835
2836 uart_resume_port(&atmel_uart, port);
2837 device_set_wakeup_enable(dev, atmel_port->may_wakeup);
2838
2839 return 0;
2840}
2841
2842static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2843 struct platform_device *pdev)
2844{
2845 atmel_port->fifo_size = 0;
2846 atmel_port->rts_low = 0;
2847 atmel_port->rts_high = 0;
2848
2849 if (of_property_read_u32(pdev->dev.of_node,
2850 "atmel,fifo-size",
2851 &atmel_port->fifo_size))
2852 return;
2853
2854 if (!atmel_port->fifo_size)
2855 return;
2856
2857 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2858 atmel_port->fifo_size = 0;
2859 dev_err(&pdev->dev, "Invalid FIFO size\n");
2860 return;
2861 }
2862
2863 /*
2864 * 0 <= rts_low <= rts_high <= fifo_size
2865 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2866 * to flush their internal TX FIFO, commonly up to 16 data, before
2867 * actually stopping to send new data. So we try to set the RTS High
2868 * Threshold to a reasonably high value respecting this 16 data
2869 * empirical rule when possible.
2870 */
2871 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2872 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2873 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2874 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2875
2876 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2877 atmel_port->fifo_size);
2878 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2879 atmel_port->rts_high);
2880 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2881 atmel_port->rts_low);
2882}
2883
2884static int atmel_serial_probe(struct platform_device *pdev)
2885{
2886 struct atmel_uart_port *atmel_port;
2887 struct device_node *np = pdev->dev.parent->of_node;
2888 void *data;
2889 int ret;
2890 bool rs485_enabled;
2891
2892 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2893
2894 /*
2895 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2896 * as compatible string. This driver is probed by at91-usart mfd driver
2897 * which is just a wrapper over the atmel_serial driver and
2898 * spi-at91-usart driver. All attributes needed by this driver are
2899 * found in of_node of parent.
2900 */
2901 pdev->dev.of_node = np;
2902
2903 ret = of_alias_get_id(np, "serial");
2904 if (ret < 0)
2905 /* port id not found in platform data nor device-tree aliases:
2906 * auto-enumerate it */
2907 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2908
2909 if (ret >= ATMEL_MAX_UART) {
2910 ret = -ENODEV;
2911 goto err;
2912 }
2913
2914 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2915 /* port already in use */
2916 ret = -EBUSY;
2917 goto err;
2918 }
2919
2920 atmel_port = &atmel_ports[ret];
2921 atmel_port->backup_imr = 0;
2922 atmel_port->uart.line = ret;
2923 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2924 atmel_serial_probe_fifos(atmel_port, pdev);
2925
2926 atomic_set(&atmel_port->tasklet_shutdown, 0);
2927 spin_lock_init(&atmel_port->lock_suspended);
2928
2929 atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2930 if (IS_ERR(atmel_port->clk)) {
2931 ret = PTR_ERR(atmel_port->clk);
2932 goto err;
2933 }
2934 ret = clk_prepare_enable(atmel_port->clk);
2935 if (ret)
2936 goto err;
2937
2938 atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
2939 if (IS_ERR(atmel_port->gclk)) {
2940 ret = PTR_ERR(atmel_port->gclk);
2941 goto err_clk_disable_unprepare;
2942 }
2943
2944 ret = atmel_init_port(atmel_port, pdev);
2945 if (ret)
2946 goto err_clk_disable_unprepare;
2947
2948 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2949 if (IS_ERR(atmel_port->gpios)) {
2950 ret = PTR_ERR(atmel_port->gpios);
2951 goto err_clk_disable_unprepare;
2952 }
2953
2954 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2955 ret = -ENOMEM;
2956 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2957 sizeof(struct atmel_uart_char),
2958 GFP_KERNEL);
2959 if (!data)
2960 goto err_clk_disable_unprepare;
2961 atmel_port->rx_ring.buf = data;
2962 }
2963
2964 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2965
2966 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2967 if (ret)
2968 goto err_add_port;
2969
2970 device_init_wakeup(&pdev->dev, 1);
2971 platform_set_drvdata(pdev, atmel_port);
2972
2973 if (rs485_enabled) {
2974 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2975 ATMEL_US_USMODE_NORMAL);
2976 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2977 ATMEL_US_RTSEN);
2978 }
2979
2980 /*
2981 * Get port name of usart or uart
2982 */
2983 atmel_get_ip_name(&atmel_port->uart);
2984
2985 /*
2986 * The peripheral clock can now safely be disabled till the port
2987 * is used
2988 */
2989 clk_disable_unprepare(atmel_port->clk);
2990
2991 return 0;
2992
2993err_add_port:
2994 kfree(atmel_port->rx_ring.buf);
2995 atmel_port->rx_ring.buf = NULL;
2996err_clk_disable_unprepare:
2997 clk_disable_unprepare(atmel_port->clk);
2998 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2999err:
3000 return ret;
3001}
3002
3003/*
3004 * Even if the driver is not modular, it makes sense to be able to
3005 * unbind a device: there can be many bound devices, and there are
3006 * situations where dynamic binding and unbinding can be useful.
3007 *
3008 * For example, a connected device can require a specific firmware update
3009 * protocol that needs bitbanging on IO lines, but use the regular serial
3010 * port in the normal case.
3011 */
3012static void atmel_serial_remove(struct platform_device *pdev)
3013{
3014 struct uart_port *port = platform_get_drvdata(pdev);
3015 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
3016
3017 tasklet_kill(&atmel_port->tasklet_rx);
3018 tasklet_kill(&atmel_port->tasklet_tx);
3019
3020 device_init_wakeup(&pdev->dev, 0);
3021
3022 uart_remove_one_port(&atmel_uart, port);
3023
3024 kfree(atmel_port->rx_ring.buf);
3025
3026 /* "port" is allocated statically, so we shouldn't free it */
3027
3028 clear_bit(port->line, atmel_ports_in_use);
3029
3030 pdev->dev.of_node = NULL;
3031}
3032
3033static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
3034 atmel_serial_resume);
3035
3036static struct platform_driver atmel_serial_driver = {
3037 .probe = atmel_serial_probe,
3038 .remove_new = atmel_serial_remove,
3039 .driver = {
3040 .name = "atmel_usart_serial",
3041 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3042 .pm = pm_ptr(&atmel_serial_pm_ops),
3043 },
3044};
3045
3046static int __init atmel_serial_init(void)
3047{
3048 int ret;
3049
3050 ret = uart_register_driver(&atmel_uart);
3051 if (ret)
3052 return ret;
3053
3054 ret = platform_driver_register(&atmel_serial_driver);
3055 if (ret)
3056 uart_unregister_driver(&atmel_uart);
3057
3058 return ret;
3059}
3060device_initcall(atmel_serial_init);
1/*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
31#include <linux/clk.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
35#include <linux/platform_device.h>
36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/of_gpio.h>
39#include <linux/dma-mapping.h>
40#include <linux/atmel_pdc.h>
41#include <linux/atmel_serial.h>
42#include <linux/uaccess.h>
43#include <linux/platform_data/atmel.h>
44#include <linux/timer.h>
45#include <linux/gpio.h>
46
47#include <asm/io.h>
48#include <asm/ioctls.h>
49
50#define PDC_BUFFER_SIZE 512
51/* Revisit: We should calculate this based on the actual port settings */
52#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
53
54#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
55#define SUPPORT_SYSRQ
56#endif
57
58#include <linux/serial_core.h>
59
60static void atmel_start_rx(struct uart_port *port);
61static void atmel_stop_rx(struct uart_port *port);
62
63#ifdef CONFIG_SERIAL_ATMEL_TTYAT
64
65/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
66 * should coexist with the 8250 driver, such as if we have an external 16C550
67 * UART. */
68#define SERIAL_ATMEL_MAJOR 204
69#define MINOR_START 154
70#define ATMEL_DEVICENAME "ttyAT"
71
72#else
73
74/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
75 * name, but it is legally reserved for the 8250 driver. */
76#define SERIAL_ATMEL_MAJOR TTY_MAJOR
77#define MINOR_START 64
78#define ATMEL_DEVICENAME "ttyS"
79
80#endif
81
82#define ATMEL_ISR_PASS_LIMIT 256
83
84/* UART registers. CR is write-only, hence no GET macro */
85#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
86#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
87#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
88#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
89#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
90#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
91#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
92#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
93#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
94#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
95#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
96#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
97#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
98#define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
99#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
100
101 /* PDC registers */
102#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
103#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
104
105#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
106#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
107#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
108#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
109#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
110
111#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
112#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
113#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
114
115struct atmel_dma_buffer {
116 unsigned char *buf;
117 dma_addr_t dma_addr;
118 unsigned int dma_size;
119 unsigned int ofs;
120};
121
122struct atmel_uart_char {
123 u16 status;
124 u16 ch;
125};
126
127#define ATMEL_SERIAL_RINGSIZE 1024
128
129/*
130 * We wrap our port structure around the generic uart_port.
131 */
132struct atmel_uart_port {
133 struct uart_port uart; /* uart */
134 struct clk *clk; /* uart clock */
135 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
136 u32 backup_imr; /* IMR saved during suspend */
137 int break_active; /* break being received */
138
139 bool use_dma_rx; /* enable DMA receiver */
140 bool use_pdc_rx; /* enable PDC receiver */
141 short pdc_rx_idx; /* current PDC RX buffer */
142 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
143
144 bool use_dma_tx; /* enable DMA transmitter */
145 bool use_pdc_tx; /* enable PDC transmitter */
146 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
147
148 spinlock_t lock_tx; /* port lock */
149 spinlock_t lock_rx; /* port lock */
150 struct dma_chan *chan_tx;
151 struct dma_chan *chan_rx;
152 struct dma_async_tx_descriptor *desc_tx;
153 struct dma_async_tx_descriptor *desc_rx;
154 dma_cookie_t cookie_tx;
155 dma_cookie_t cookie_rx;
156 struct scatterlist sg_tx;
157 struct scatterlist sg_rx;
158 struct tasklet_struct tasklet;
159 unsigned int irq_status;
160 unsigned int irq_status_prev;
161
162 struct circ_buf rx_ring;
163
164 struct serial_rs485 rs485; /* rs485 settings */
165 int rts_gpio; /* optional RTS GPIO */
166 unsigned int tx_done_mask;
167 bool is_usart; /* usart or uart */
168 struct timer_list uart_timer; /* uart timer */
169 int (*prepare_rx)(struct uart_port *port);
170 int (*prepare_tx)(struct uart_port *port);
171 void (*schedule_rx)(struct uart_port *port);
172 void (*schedule_tx)(struct uart_port *port);
173 void (*release_rx)(struct uart_port *port);
174 void (*release_tx)(struct uart_port *port);
175};
176
177static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
178static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
179
180#ifdef SUPPORT_SYSRQ
181static struct console atmel_console;
182#endif
183
184#if defined(CONFIG_OF)
185static const struct of_device_id atmel_serial_dt_ids[] = {
186 { .compatible = "atmel,at91rm9200-usart" },
187 { .compatible = "atmel,at91sam9260-usart" },
188 { /* sentinel */ }
189};
190
191MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
192#endif
193
194static inline struct atmel_uart_port *
195to_atmel_uart_port(struct uart_port *uart)
196{
197 return container_of(uart, struct atmel_uart_port, uart);
198}
199
200#ifdef CONFIG_SERIAL_ATMEL_PDC
201static bool atmel_use_pdc_rx(struct uart_port *port)
202{
203 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
204
205 return atmel_port->use_pdc_rx;
206}
207
208static bool atmel_use_pdc_tx(struct uart_port *port)
209{
210 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
211
212 return atmel_port->use_pdc_tx;
213}
214#else
215static bool atmel_use_pdc_rx(struct uart_port *port)
216{
217 return false;
218}
219
220static bool atmel_use_pdc_tx(struct uart_port *port)
221{
222 return false;
223}
224#endif
225
226static bool atmel_use_dma_tx(struct uart_port *port)
227{
228 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
229
230 return atmel_port->use_dma_tx;
231}
232
233static bool atmel_use_dma_rx(struct uart_port *port)
234{
235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
236
237 return atmel_port->use_dma_rx;
238}
239
240/* Enable or disable the rs485 support */
241void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
242{
243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
244 unsigned int mode;
245 unsigned long flags;
246
247 spin_lock_irqsave(&port->lock, flags);
248
249 /* Disable interrupts */
250 UART_PUT_IDR(port, atmel_port->tx_done_mask);
251
252 mode = UART_GET_MR(port);
253
254 /* Resetting serial mode to RS232 (0x0) */
255 mode &= ~ATMEL_US_USMODE;
256
257 atmel_port->rs485 = *rs485conf;
258
259 if (rs485conf->flags & SER_RS485_ENABLED) {
260 dev_dbg(port->dev, "Setting UART to RS485\n");
261 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
262 if ((rs485conf->delay_rts_after_send) > 0)
263 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
264 mode |= ATMEL_US_USMODE_RS485;
265 } else {
266 dev_dbg(port->dev, "Setting UART to RS232\n");
267 if (atmel_use_pdc_tx(port))
268 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
269 ATMEL_US_TXBUFE;
270 else
271 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
272 }
273 UART_PUT_MR(port, mode);
274
275 /* Enable interrupts */
276 UART_PUT_IER(port, atmel_port->tx_done_mask);
277
278 spin_unlock_irqrestore(&port->lock, flags);
279
280}
281
282/*
283 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
284 */
285static u_int atmel_tx_empty(struct uart_port *port)
286{
287 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
288}
289
290/*
291 * Set state of the modem control output lines
292 */
293static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
294{
295 unsigned int control = 0;
296 unsigned int mode;
297 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
298
299 /*
300 * AT91RM9200 Errata #39: RTS0 is not internally connected
301 * to PA21. We need to drive the pin as a GPIO.
302 */
303 if (gpio_is_valid(atmel_port->rts_gpio)) {
304 if (mctrl & TIOCM_RTS)
305 gpio_set_value(atmel_port->rts_gpio, 0);
306 else
307 gpio_set_value(atmel_port->rts_gpio, 1);
308 }
309
310 if (mctrl & TIOCM_RTS)
311 control |= ATMEL_US_RTSEN;
312 else
313 control |= ATMEL_US_RTSDIS;
314
315 if (mctrl & TIOCM_DTR)
316 control |= ATMEL_US_DTREN;
317 else
318 control |= ATMEL_US_DTRDIS;
319
320 UART_PUT_CR(port, control);
321
322 /* Local loopback mode? */
323 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
324 if (mctrl & TIOCM_LOOP)
325 mode |= ATMEL_US_CHMODE_LOC_LOOP;
326 else
327 mode |= ATMEL_US_CHMODE_NORMAL;
328
329 /* Resetting serial mode to RS232 (0x0) */
330 mode &= ~ATMEL_US_USMODE;
331
332 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
333 dev_dbg(port->dev, "Setting UART to RS485\n");
334 if ((atmel_port->rs485.delay_rts_after_send) > 0)
335 UART_PUT_TTGR(port,
336 atmel_port->rs485.delay_rts_after_send);
337 mode |= ATMEL_US_USMODE_RS485;
338 } else {
339 dev_dbg(port->dev, "Setting UART to RS232\n");
340 }
341 UART_PUT_MR(port, mode);
342}
343
344/*
345 * Get state of the modem control input lines
346 */
347static u_int atmel_get_mctrl(struct uart_port *port)
348{
349 unsigned int status, ret = 0;
350
351 status = UART_GET_CSR(port);
352
353 /*
354 * The control signals are active low.
355 */
356 if (!(status & ATMEL_US_DCD))
357 ret |= TIOCM_CD;
358 if (!(status & ATMEL_US_CTS))
359 ret |= TIOCM_CTS;
360 if (!(status & ATMEL_US_DSR))
361 ret |= TIOCM_DSR;
362 if (!(status & ATMEL_US_RI))
363 ret |= TIOCM_RI;
364
365 return ret;
366}
367
368/*
369 * Stop transmitting.
370 */
371static void atmel_stop_tx(struct uart_port *port)
372{
373 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
374
375 if (atmel_use_pdc_tx(port)) {
376 /* disable PDC transmit */
377 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
378 }
379 /* Disable interrupts */
380 UART_PUT_IDR(port, atmel_port->tx_done_mask);
381
382 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
383 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
384 atmel_start_rx(port);
385}
386
387/*
388 * Start transmitting.
389 */
390static void atmel_start_tx(struct uart_port *port)
391{
392 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
393
394 if (atmel_use_pdc_tx(port)) {
395 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
396 /* The transmitter is already running. Yes, we
397 really need this.*/
398 return;
399
400 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
401 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
402 atmel_stop_rx(port);
403
404 /* re-enable PDC transmit */
405 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
406 }
407 /* Enable interrupts */
408 UART_PUT_IER(port, atmel_port->tx_done_mask);
409}
410
411/*
412 * start receiving - port is in process of being opened.
413 */
414static void atmel_start_rx(struct uart_port *port)
415{
416 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
417
418 UART_PUT_CR(port, ATMEL_US_RXEN);
419
420 if (atmel_use_pdc_rx(port)) {
421 /* enable PDC controller */
422 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
423 port->read_status_mask);
424 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
425 } else {
426 UART_PUT_IER(port, ATMEL_US_RXRDY);
427 }
428}
429
430/*
431 * Stop receiving - port is in process of being closed.
432 */
433static void atmel_stop_rx(struct uart_port *port)
434{
435 UART_PUT_CR(port, ATMEL_US_RXDIS);
436
437 if (atmel_use_pdc_rx(port)) {
438 /* disable PDC receive */
439 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
440 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
441 port->read_status_mask);
442 } else {
443 UART_PUT_IDR(port, ATMEL_US_RXRDY);
444 }
445}
446
447/*
448 * Enable modem status interrupts
449 */
450static void atmel_enable_ms(struct uart_port *port)
451{
452 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
453 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
454}
455
456/*
457 * Control the transmission of a break signal
458 */
459static void atmel_break_ctl(struct uart_port *port, int break_state)
460{
461 if (break_state != 0)
462 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
463 else
464 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
465}
466
467/*
468 * Stores the incoming character in the ring buffer
469 */
470static void
471atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
472 unsigned int ch)
473{
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
475 struct circ_buf *ring = &atmel_port->rx_ring;
476 struct atmel_uart_char *c;
477
478 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
479 /* Buffer overflow, ignore char */
480 return;
481
482 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
483 c->status = status;
484 c->ch = ch;
485
486 /* Make sure the character is stored before we update head. */
487 smp_wmb();
488
489 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
490}
491
492/*
493 * Deal with parity, framing and overrun errors.
494 */
495static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
496{
497 /* clear error */
498 UART_PUT_CR(port, ATMEL_US_RSTSTA);
499
500 if (status & ATMEL_US_RXBRK) {
501 /* ignore side-effect */
502 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
503 port->icount.brk++;
504 }
505 if (status & ATMEL_US_PARE)
506 port->icount.parity++;
507 if (status & ATMEL_US_FRAME)
508 port->icount.frame++;
509 if (status & ATMEL_US_OVRE)
510 port->icount.overrun++;
511}
512
513/*
514 * Characters received (called from interrupt handler)
515 */
516static void atmel_rx_chars(struct uart_port *port)
517{
518 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
519 unsigned int status, ch;
520
521 status = UART_GET_CSR(port);
522 while (status & ATMEL_US_RXRDY) {
523 ch = UART_GET_CHAR(port);
524
525 /*
526 * note that the error handling code is
527 * out of the main execution path
528 */
529 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
530 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
531 || atmel_port->break_active)) {
532
533 /* clear error */
534 UART_PUT_CR(port, ATMEL_US_RSTSTA);
535
536 if (status & ATMEL_US_RXBRK
537 && !atmel_port->break_active) {
538 atmel_port->break_active = 1;
539 UART_PUT_IER(port, ATMEL_US_RXBRK);
540 } else {
541 /*
542 * This is either the end-of-break
543 * condition or we've received at
544 * least one character without RXBRK
545 * being set. In both cases, the next
546 * RXBRK will indicate start-of-break.
547 */
548 UART_PUT_IDR(port, ATMEL_US_RXBRK);
549 status &= ~ATMEL_US_RXBRK;
550 atmel_port->break_active = 0;
551 }
552 }
553
554 atmel_buffer_rx_char(port, status, ch);
555 status = UART_GET_CSR(port);
556 }
557
558 tasklet_schedule(&atmel_port->tasklet);
559}
560
561/*
562 * Transmit characters (called from tasklet with TXRDY interrupt
563 * disabled)
564 */
565static void atmel_tx_chars(struct uart_port *port)
566{
567 struct circ_buf *xmit = &port->state->xmit;
568 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
569
570 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
571 UART_PUT_CHAR(port, port->x_char);
572 port->icount.tx++;
573 port->x_char = 0;
574 }
575 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
576 return;
577
578 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
579 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
580 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
581 port->icount.tx++;
582 if (uart_circ_empty(xmit))
583 break;
584 }
585
586 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
587 uart_write_wakeup(port);
588
589 if (!uart_circ_empty(xmit))
590 /* Enable interrupts */
591 UART_PUT_IER(port, atmel_port->tx_done_mask);
592}
593
594static void atmel_complete_tx_dma(void *arg)
595{
596 struct atmel_uart_port *atmel_port = arg;
597 struct uart_port *port = &atmel_port->uart;
598 struct circ_buf *xmit = &port->state->xmit;
599 struct dma_chan *chan = atmel_port->chan_tx;
600 unsigned long flags;
601
602 spin_lock_irqsave(&port->lock, flags);
603
604 if (chan)
605 dmaengine_terminate_all(chan);
606 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
607 xmit->tail &= UART_XMIT_SIZE - 1;
608
609 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
610
611 spin_lock_irq(&atmel_port->lock_tx);
612 async_tx_ack(atmel_port->desc_tx);
613 atmel_port->cookie_tx = -EINVAL;
614 atmel_port->desc_tx = NULL;
615 spin_unlock_irq(&atmel_port->lock_tx);
616
617 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
618 uart_write_wakeup(port);
619
620 /* Do we really need this? */
621 if (!uart_circ_empty(xmit))
622 tasklet_schedule(&atmel_port->tasklet);
623
624 spin_unlock_irqrestore(&port->lock, flags);
625}
626
627static void atmel_release_tx_dma(struct uart_port *port)
628{
629 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
630 struct dma_chan *chan = atmel_port->chan_tx;
631
632 if (chan) {
633 dmaengine_terminate_all(chan);
634 dma_release_channel(chan);
635 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
636 DMA_MEM_TO_DEV);
637 }
638
639 atmel_port->desc_tx = NULL;
640 atmel_port->chan_tx = NULL;
641 atmel_port->cookie_tx = -EINVAL;
642}
643
644/*
645 * Called from tasklet with TXRDY interrupt is disabled.
646 */
647static void atmel_tx_dma(struct uart_port *port)
648{
649 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
650 struct circ_buf *xmit = &port->state->xmit;
651 struct dma_chan *chan = atmel_port->chan_tx;
652 struct dma_async_tx_descriptor *desc;
653 struct scatterlist *sg = &atmel_port->sg_tx;
654
655 /* Make sure we have an idle channel */
656 if (atmel_port->desc_tx != NULL)
657 return;
658
659 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
660 /*
661 * DMA is idle now.
662 * Port xmit buffer is already mapped,
663 * and it is one page... Just adjust
664 * offsets and lengths. Since it is a circular buffer,
665 * we have to transmit till the end, and then the rest.
666 * Take the port lock to get a
667 * consistent xmit buffer state.
668 */
669 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
670 sg_dma_address(sg) = (sg_dma_address(sg) &
671 ~(UART_XMIT_SIZE - 1))
672 + sg->offset;
673 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
674 xmit->tail,
675 UART_XMIT_SIZE);
676 BUG_ON(!sg_dma_len(sg));
677
678 desc = dmaengine_prep_slave_sg(chan,
679 sg,
680 1,
681 DMA_MEM_TO_DEV,
682 DMA_PREP_INTERRUPT |
683 DMA_CTRL_ACK);
684 if (!desc) {
685 dev_err(port->dev, "Failed to send via dma!\n");
686 return;
687 }
688
689 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV);
690
691 atmel_port->desc_tx = desc;
692 desc->callback = atmel_complete_tx_dma;
693 desc->callback_param = atmel_port;
694 atmel_port->cookie_tx = dmaengine_submit(desc);
695
696 } else {
697 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
698 /* DMA done, stop TX, start RX for RS485 */
699 atmel_start_rx(port);
700 }
701 }
702
703 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
704 uart_write_wakeup(port);
705}
706
707static int atmel_prepare_tx_dma(struct uart_port *port)
708{
709 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
710 dma_cap_mask_t mask;
711 struct dma_slave_config config;
712 int ret, nent;
713
714 dma_cap_zero(mask);
715 dma_cap_set(DMA_SLAVE, mask);
716
717 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
718 if (atmel_port->chan_tx == NULL)
719 goto chan_err;
720 dev_info(port->dev, "using %s for tx DMA transfers\n",
721 dma_chan_name(atmel_port->chan_tx));
722
723 spin_lock_init(&atmel_port->lock_tx);
724 sg_init_table(&atmel_port->sg_tx, 1);
725 /* UART circular tx buffer is an aligned page. */
726 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
727 sg_set_page(&atmel_port->sg_tx,
728 virt_to_page(port->state->xmit.buf),
729 UART_XMIT_SIZE,
730 (int)port->state->xmit.buf & ~PAGE_MASK);
731 nent = dma_map_sg(port->dev,
732 &atmel_port->sg_tx,
733 1,
734 DMA_MEM_TO_DEV);
735
736 if (!nent) {
737 dev_dbg(port->dev, "need to release resource of dma\n");
738 goto chan_err;
739 } else {
740 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
741 sg_dma_len(&atmel_port->sg_tx),
742 port->state->xmit.buf,
743 sg_dma_address(&atmel_port->sg_tx));
744 }
745
746 /* Configure the slave DMA */
747 memset(&config, 0, sizeof(config));
748 config.direction = DMA_MEM_TO_DEV;
749 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
750 config.dst_addr = port->mapbase + ATMEL_US_THR;
751
752 ret = dmaengine_device_control(atmel_port->chan_tx,
753 DMA_SLAVE_CONFIG,
754 (unsigned long)&config);
755 if (ret) {
756 dev_err(port->dev, "DMA tx slave configuration failed\n");
757 goto chan_err;
758 }
759
760 return 0;
761
762chan_err:
763 dev_err(port->dev, "TX channel not available, switch to pio\n");
764 atmel_port->use_dma_tx = 0;
765 if (atmel_port->chan_tx)
766 atmel_release_tx_dma(port);
767 return -EINVAL;
768}
769
770static void atmel_flip_buffer_rx_dma(struct uart_port *port,
771 char *buf, size_t count)
772{
773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
774 struct tty_port *tport = &port->state->port;
775
776 dma_sync_sg_for_cpu(port->dev,
777 &atmel_port->sg_rx,
778 1,
779 DMA_DEV_TO_MEM);
780
781 tty_insert_flip_string(tport, buf, count);
782
783 dma_sync_sg_for_device(port->dev,
784 &atmel_port->sg_rx,
785 1,
786 DMA_DEV_TO_MEM);
787 /*
788 * Drop the lock here since it might end up calling
789 * uart_start(), which takes the lock.
790 */
791 spin_unlock(&port->lock);
792 tty_flip_buffer_push(tport);
793 spin_lock(&port->lock);
794}
795
796static void atmel_complete_rx_dma(void *arg)
797{
798 struct uart_port *port = arg;
799 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
800
801 tasklet_schedule(&atmel_port->tasklet);
802}
803
804static void atmel_release_rx_dma(struct uart_port *port)
805{
806 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
807 struct dma_chan *chan = atmel_port->chan_rx;
808
809 if (chan) {
810 dmaengine_terminate_all(chan);
811 dma_release_channel(chan);
812 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
813 DMA_DEV_TO_MEM);
814 }
815
816 atmel_port->desc_rx = NULL;
817 atmel_port->chan_rx = NULL;
818 atmel_port->cookie_rx = -EINVAL;
819}
820
821static void atmel_rx_from_dma(struct uart_port *port)
822{
823 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
824 struct circ_buf *ring = &atmel_port->rx_ring;
825 struct dma_chan *chan = atmel_port->chan_rx;
826 struct dma_tx_state state;
827 enum dma_status dmastat;
828 size_t pending, count;
829
830
831 /* Reset the UART timeout early so that we don't miss one */
832 UART_PUT_CR(port, ATMEL_US_STTTO);
833 dmastat = dmaengine_tx_status(chan,
834 atmel_port->cookie_rx,
835 &state);
836 /* Restart a new tasklet if DMA status is error */
837 if (dmastat == DMA_ERROR) {
838 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
839 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
840 tasklet_schedule(&atmel_port->tasklet);
841 return;
842 }
843 /* current transfer size should no larger than dma buffer */
844 pending = sg_dma_len(&atmel_port->sg_rx) - state.residue;
845 BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx));
846
847 /*
848 * This will take the chars we have so far,
849 * ring->head will record the transfer size, only new bytes come
850 * will insert into the framework.
851 */
852 if (pending > ring->head) {
853 count = pending - ring->head;
854
855 atmel_flip_buffer_rx_dma(port, ring->buf + ring->head, count);
856
857 ring->head += count;
858 if (ring->head == sg_dma_len(&atmel_port->sg_rx))
859 ring->head = 0;
860
861 port->icount.rx += count;
862 }
863
864 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
865}
866
867static int atmel_prepare_rx_dma(struct uart_port *port)
868{
869 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
870 struct dma_async_tx_descriptor *desc;
871 dma_cap_mask_t mask;
872 struct dma_slave_config config;
873 struct circ_buf *ring;
874 int ret, nent;
875
876 ring = &atmel_port->rx_ring;
877
878 dma_cap_zero(mask);
879 dma_cap_set(DMA_CYCLIC, mask);
880
881 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
882 if (atmel_port->chan_rx == NULL)
883 goto chan_err;
884 dev_info(port->dev, "using %s for rx DMA transfers\n",
885 dma_chan_name(atmel_port->chan_rx));
886
887 spin_lock_init(&atmel_port->lock_rx);
888 sg_init_table(&atmel_port->sg_rx, 1);
889 /* UART circular rx buffer is an aligned page. */
890 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
891 sg_set_page(&atmel_port->sg_rx,
892 virt_to_page(ring->buf),
893 ATMEL_SERIAL_RINGSIZE,
894 (int)ring->buf & ~PAGE_MASK);
895 nent = dma_map_sg(port->dev,
896 &atmel_port->sg_rx,
897 1,
898 DMA_DEV_TO_MEM);
899
900 if (!nent) {
901 dev_dbg(port->dev, "need to release resource of dma\n");
902 goto chan_err;
903 } else {
904 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
905 sg_dma_len(&atmel_port->sg_rx),
906 ring->buf,
907 sg_dma_address(&atmel_port->sg_rx));
908 }
909
910 /* Configure the slave DMA */
911 memset(&config, 0, sizeof(config));
912 config.direction = DMA_DEV_TO_MEM;
913 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
914 config.src_addr = port->mapbase + ATMEL_US_RHR;
915
916 ret = dmaengine_device_control(atmel_port->chan_rx,
917 DMA_SLAVE_CONFIG,
918 (unsigned long)&config);
919 if (ret) {
920 dev_err(port->dev, "DMA rx slave configuration failed\n");
921 goto chan_err;
922 }
923 /*
924 * Prepare a cyclic dma transfer, assign 2 descriptors,
925 * each one is half ring buffer size
926 */
927 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
928 sg_dma_address(&atmel_port->sg_rx),
929 sg_dma_len(&atmel_port->sg_rx),
930 sg_dma_len(&atmel_port->sg_rx)/2,
931 DMA_DEV_TO_MEM,
932 DMA_PREP_INTERRUPT);
933 desc->callback = atmel_complete_rx_dma;
934 desc->callback_param = port;
935 atmel_port->desc_rx = desc;
936 atmel_port->cookie_rx = dmaengine_submit(desc);
937
938 return 0;
939
940chan_err:
941 dev_err(port->dev, "RX channel not available, switch to pio\n");
942 atmel_port->use_dma_rx = 0;
943 if (atmel_port->chan_rx)
944 atmel_release_rx_dma(port);
945 return -EINVAL;
946}
947
948static void atmel_uart_timer_callback(unsigned long data)
949{
950 struct uart_port *port = (void *)data;
951 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
952
953 tasklet_schedule(&atmel_port->tasklet);
954 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
955}
956
957/*
958 * receive interrupt handler.
959 */
960static void
961atmel_handle_receive(struct uart_port *port, unsigned int pending)
962{
963 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
964
965 if (atmel_use_pdc_rx(port)) {
966 /*
967 * PDC receive. Just schedule the tasklet and let it
968 * figure out the details.
969 *
970 * TODO: We're not handling error flags correctly at
971 * the moment.
972 */
973 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
974 UART_PUT_IDR(port, (ATMEL_US_ENDRX
975 | ATMEL_US_TIMEOUT));
976 tasklet_schedule(&atmel_port->tasklet);
977 }
978
979 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
980 ATMEL_US_FRAME | ATMEL_US_PARE))
981 atmel_pdc_rxerr(port, pending);
982 }
983
984 if (atmel_use_dma_rx(port)) {
985 if (pending & ATMEL_US_TIMEOUT) {
986 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
987 tasklet_schedule(&atmel_port->tasklet);
988 }
989 }
990
991 /* Interrupt receive */
992 if (pending & ATMEL_US_RXRDY)
993 atmel_rx_chars(port);
994 else if (pending & ATMEL_US_RXBRK) {
995 /*
996 * End of break detected. If it came along with a
997 * character, atmel_rx_chars will handle it.
998 */
999 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1000 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1001 atmel_port->break_active = 0;
1002 }
1003}
1004
1005/*
1006 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1007 */
1008static void
1009atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1010{
1011 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1012
1013 if (pending & atmel_port->tx_done_mask) {
1014 /* Either PDC or interrupt transmission */
1015 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1016 tasklet_schedule(&atmel_port->tasklet);
1017 }
1018}
1019
1020/*
1021 * status flags interrupt handler.
1022 */
1023static void
1024atmel_handle_status(struct uart_port *port, unsigned int pending,
1025 unsigned int status)
1026{
1027 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1028
1029 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1030 | ATMEL_US_CTSIC)) {
1031 atmel_port->irq_status = status;
1032 tasklet_schedule(&atmel_port->tasklet);
1033 }
1034}
1035
1036/*
1037 * Interrupt handler
1038 */
1039static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1040{
1041 struct uart_port *port = dev_id;
1042 unsigned int status, pending, pass_counter = 0;
1043
1044 do {
1045 status = UART_GET_CSR(port);
1046 pending = status & UART_GET_IMR(port);
1047 if (!pending)
1048 break;
1049
1050 atmel_handle_receive(port, pending);
1051 atmel_handle_status(port, pending, status);
1052 atmel_handle_transmit(port, pending);
1053 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1054
1055 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1056}
1057
1058static void atmel_release_tx_pdc(struct uart_port *port)
1059{
1060 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1061 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1062
1063 dma_unmap_single(port->dev,
1064 pdc->dma_addr,
1065 pdc->dma_size,
1066 DMA_TO_DEVICE);
1067}
1068
1069/*
1070 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1071 */
1072static void atmel_tx_pdc(struct uart_port *port)
1073{
1074 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1075 struct circ_buf *xmit = &port->state->xmit;
1076 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1077 int count;
1078
1079 /* nothing left to transmit? */
1080 if (UART_GET_TCR(port))
1081 return;
1082
1083 xmit->tail += pdc->ofs;
1084 xmit->tail &= UART_XMIT_SIZE - 1;
1085
1086 port->icount.tx += pdc->ofs;
1087 pdc->ofs = 0;
1088
1089 /* more to transmit - setup next transfer */
1090
1091 /* disable PDC transmit */
1092 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1093
1094 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1095 dma_sync_single_for_device(port->dev,
1096 pdc->dma_addr,
1097 pdc->dma_size,
1098 DMA_TO_DEVICE);
1099
1100 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1101 pdc->ofs = count;
1102
1103 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1104 UART_PUT_TCR(port, count);
1105 /* re-enable PDC transmit */
1106 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1107 /* Enable interrupts */
1108 UART_PUT_IER(port, atmel_port->tx_done_mask);
1109 } else {
1110 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
1111 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1112 /* DMA done, stop TX, start RX for RS485 */
1113 atmel_start_rx(port);
1114 }
1115 }
1116
1117 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1118 uart_write_wakeup(port);
1119}
1120
1121static int atmel_prepare_tx_pdc(struct uart_port *port)
1122{
1123 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1124 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1125 struct circ_buf *xmit = &port->state->xmit;
1126
1127 pdc->buf = xmit->buf;
1128 pdc->dma_addr = dma_map_single(port->dev,
1129 pdc->buf,
1130 UART_XMIT_SIZE,
1131 DMA_TO_DEVICE);
1132 pdc->dma_size = UART_XMIT_SIZE;
1133 pdc->ofs = 0;
1134
1135 return 0;
1136}
1137
1138static void atmel_rx_from_ring(struct uart_port *port)
1139{
1140 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1141 struct circ_buf *ring = &atmel_port->rx_ring;
1142 unsigned int flg;
1143 unsigned int status;
1144
1145 while (ring->head != ring->tail) {
1146 struct atmel_uart_char c;
1147
1148 /* Make sure c is loaded after head. */
1149 smp_rmb();
1150
1151 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1152
1153 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1154
1155 port->icount.rx++;
1156 status = c.status;
1157 flg = TTY_NORMAL;
1158
1159 /*
1160 * note that the error handling code is
1161 * out of the main execution path
1162 */
1163 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1164 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1165 if (status & ATMEL_US_RXBRK) {
1166 /* ignore side-effect */
1167 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1168
1169 port->icount.brk++;
1170 if (uart_handle_break(port))
1171 continue;
1172 }
1173 if (status & ATMEL_US_PARE)
1174 port->icount.parity++;
1175 if (status & ATMEL_US_FRAME)
1176 port->icount.frame++;
1177 if (status & ATMEL_US_OVRE)
1178 port->icount.overrun++;
1179
1180 status &= port->read_status_mask;
1181
1182 if (status & ATMEL_US_RXBRK)
1183 flg = TTY_BREAK;
1184 else if (status & ATMEL_US_PARE)
1185 flg = TTY_PARITY;
1186 else if (status & ATMEL_US_FRAME)
1187 flg = TTY_FRAME;
1188 }
1189
1190
1191 if (uart_handle_sysrq_char(port, c.ch))
1192 continue;
1193
1194 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1195 }
1196
1197 /*
1198 * Drop the lock here since it might end up calling
1199 * uart_start(), which takes the lock.
1200 */
1201 spin_unlock(&port->lock);
1202 tty_flip_buffer_push(&port->state->port);
1203 spin_lock(&port->lock);
1204}
1205
1206static void atmel_release_rx_pdc(struct uart_port *port)
1207{
1208 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1209 int i;
1210
1211 for (i = 0; i < 2; i++) {
1212 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1213
1214 dma_unmap_single(port->dev,
1215 pdc->dma_addr,
1216 pdc->dma_size,
1217 DMA_FROM_DEVICE);
1218 kfree(pdc->buf);
1219 }
1220}
1221
1222static void atmel_rx_from_pdc(struct uart_port *port)
1223{
1224 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1225 struct tty_port *tport = &port->state->port;
1226 struct atmel_dma_buffer *pdc;
1227 int rx_idx = atmel_port->pdc_rx_idx;
1228 unsigned int head;
1229 unsigned int tail;
1230 unsigned int count;
1231
1232 do {
1233 /* Reset the UART timeout early so that we don't miss one */
1234 UART_PUT_CR(port, ATMEL_US_STTTO);
1235
1236 pdc = &atmel_port->pdc_rx[rx_idx];
1237 head = UART_GET_RPR(port) - pdc->dma_addr;
1238 tail = pdc->ofs;
1239
1240 /* If the PDC has switched buffers, RPR won't contain
1241 * any address within the current buffer. Since head
1242 * is unsigned, we just need a one-way comparison to
1243 * find out.
1244 *
1245 * In this case, we just need to consume the entire
1246 * buffer and resubmit it for DMA. This will clear the
1247 * ENDRX bit as well, so that we can safely re-enable
1248 * all interrupts below.
1249 */
1250 head = min(head, pdc->dma_size);
1251
1252 if (likely(head != tail)) {
1253 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1254 pdc->dma_size, DMA_FROM_DEVICE);
1255
1256 /*
1257 * head will only wrap around when we recycle
1258 * the DMA buffer, and when that happens, we
1259 * explicitly set tail to 0. So head will
1260 * always be greater than tail.
1261 */
1262 count = head - tail;
1263
1264 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1265 count);
1266
1267 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1268 pdc->dma_size, DMA_FROM_DEVICE);
1269
1270 port->icount.rx += count;
1271 pdc->ofs = head;
1272 }
1273
1274 /*
1275 * If the current buffer is full, we need to check if
1276 * the next one contains any additional data.
1277 */
1278 if (head >= pdc->dma_size) {
1279 pdc->ofs = 0;
1280 UART_PUT_RNPR(port, pdc->dma_addr);
1281 UART_PUT_RNCR(port, pdc->dma_size);
1282
1283 rx_idx = !rx_idx;
1284 atmel_port->pdc_rx_idx = rx_idx;
1285 }
1286 } while (head >= pdc->dma_size);
1287
1288 /*
1289 * Drop the lock here since it might end up calling
1290 * uart_start(), which takes the lock.
1291 */
1292 spin_unlock(&port->lock);
1293 tty_flip_buffer_push(tport);
1294 spin_lock(&port->lock);
1295
1296 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1297}
1298
1299static int atmel_prepare_rx_pdc(struct uart_port *port)
1300{
1301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1302 int i;
1303
1304 for (i = 0; i < 2; i++) {
1305 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1306
1307 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1308 if (pdc->buf == NULL) {
1309 if (i != 0) {
1310 dma_unmap_single(port->dev,
1311 atmel_port->pdc_rx[0].dma_addr,
1312 PDC_BUFFER_SIZE,
1313 DMA_FROM_DEVICE);
1314 kfree(atmel_port->pdc_rx[0].buf);
1315 }
1316 atmel_port->use_pdc_rx = 0;
1317 return -ENOMEM;
1318 }
1319 pdc->dma_addr = dma_map_single(port->dev,
1320 pdc->buf,
1321 PDC_BUFFER_SIZE,
1322 DMA_FROM_DEVICE);
1323 pdc->dma_size = PDC_BUFFER_SIZE;
1324 pdc->ofs = 0;
1325 }
1326
1327 atmel_port->pdc_rx_idx = 0;
1328
1329 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1330 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1331
1332 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1333 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1334
1335 return 0;
1336}
1337
1338/*
1339 * tasklet handling tty stuff outside the interrupt handler.
1340 */
1341static void atmel_tasklet_func(unsigned long data)
1342{
1343 struct uart_port *port = (struct uart_port *)data;
1344 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1345 unsigned int status;
1346 unsigned int status_change;
1347
1348 /* The interrupt handler does not take the lock */
1349 spin_lock(&port->lock);
1350
1351 atmel_port->schedule_tx(port);
1352
1353 status = atmel_port->irq_status;
1354 status_change = status ^ atmel_port->irq_status_prev;
1355
1356 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1357 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1358 /* TODO: All reads to CSR will clear these interrupts! */
1359 if (status_change & ATMEL_US_RI)
1360 port->icount.rng++;
1361 if (status_change & ATMEL_US_DSR)
1362 port->icount.dsr++;
1363 if (status_change & ATMEL_US_DCD)
1364 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1365 if (status_change & ATMEL_US_CTS)
1366 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1367
1368 wake_up_interruptible(&port->state->port.delta_msr_wait);
1369
1370 atmel_port->irq_status_prev = status;
1371 }
1372
1373 atmel_port->schedule_rx(port);
1374
1375 spin_unlock(&port->lock);
1376}
1377
1378static int atmel_init_property(struct atmel_uart_port *atmel_port,
1379 struct platform_device *pdev)
1380{
1381 struct device_node *np = pdev->dev.of_node;
1382 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1383
1384 if (np) {
1385 /* DMA/PDC usage specification */
1386 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1387 if (of_get_property(np, "dmas", NULL)) {
1388 atmel_port->use_dma_rx = true;
1389 atmel_port->use_pdc_rx = false;
1390 } else {
1391 atmel_port->use_dma_rx = false;
1392 atmel_port->use_pdc_rx = true;
1393 }
1394 } else {
1395 atmel_port->use_dma_rx = false;
1396 atmel_port->use_pdc_rx = false;
1397 }
1398
1399 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1400 if (of_get_property(np, "dmas", NULL)) {
1401 atmel_port->use_dma_tx = true;
1402 atmel_port->use_pdc_tx = false;
1403 } else {
1404 atmel_port->use_dma_tx = false;
1405 atmel_port->use_pdc_tx = true;
1406 }
1407 } else {
1408 atmel_port->use_dma_tx = false;
1409 atmel_port->use_pdc_tx = false;
1410 }
1411
1412 } else {
1413 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1414 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1415 atmel_port->use_dma_rx = false;
1416 atmel_port->use_dma_tx = false;
1417 }
1418
1419 return 0;
1420}
1421
1422static void atmel_init_rs485(struct atmel_uart_port *atmel_port,
1423 struct platform_device *pdev)
1424{
1425 struct device_node *np = pdev->dev.of_node;
1426 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1427
1428 if (np) {
1429 u32 rs485_delay[2];
1430 /* rs485 properties */
1431 if (of_property_read_u32_array(np, "rs485-rts-delay",
1432 rs485_delay, 2) == 0) {
1433 struct serial_rs485 *rs485conf = &atmel_port->rs485;
1434
1435 rs485conf->delay_rts_before_send = rs485_delay[0];
1436 rs485conf->delay_rts_after_send = rs485_delay[1];
1437 rs485conf->flags = 0;
1438
1439 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1440 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1441
1442 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1443 NULL))
1444 rs485conf->flags |= SER_RS485_ENABLED;
1445 }
1446 } else {
1447 atmel_port->rs485 = pdata->rs485;
1448 }
1449
1450}
1451
1452static void atmel_set_ops(struct uart_port *port)
1453{
1454 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1455
1456 if (atmel_use_dma_rx(port)) {
1457 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1458 atmel_port->schedule_rx = &atmel_rx_from_dma;
1459 atmel_port->release_rx = &atmel_release_rx_dma;
1460 } else if (atmel_use_pdc_rx(port)) {
1461 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1462 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1463 atmel_port->release_rx = &atmel_release_rx_pdc;
1464 } else {
1465 atmel_port->prepare_rx = NULL;
1466 atmel_port->schedule_rx = &atmel_rx_from_ring;
1467 atmel_port->release_rx = NULL;
1468 }
1469
1470 if (atmel_use_dma_tx(port)) {
1471 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1472 atmel_port->schedule_tx = &atmel_tx_dma;
1473 atmel_port->release_tx = &atmel_release_tx_dma;
1474 } else if (atmel_use_pdc_tx(port)) {
1475 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1476 atmel_port->schedule_tx = &atmel_tx_pdc;
1477 atmel_port->release_tx = &atmel_release_tx_pdc;
1478 } else {
1479 atmel_port->prepare_tx = NULL;
1480 atmel_port->schedule_tx = &atmel_tx_chars;
1481 atmel_port->release_tx = NULL;
1482 }
1483}
1484
1485/*
1486 * Get ip name usart or uart
1487 */
1488static void atmel_get_ip_name(struct uart_port *port)
1489{
1490 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1491 int name = UART_GET_IP_NAME(port);
1492 u32 version;
1493 int usart, uart;
1494 /* usart and uart ascii */
1495 usart = 0x55534152;
1496 uart = 0x44424755;
1497
1498 atmel_port->is_usart = false;
1499
1500 if (name == usart) {
1501 dev_dbg(port->dev, "This is usart\n");
1502 atmel_port->is_usart = true;
1503 } else if (name == uart) {
1504 dev_dbg(port->dev, "This is uart\n");
1505 atmel_port->is_usart = false;
1506 } else {
1507 /* fallback for older SoCs: use version field */
1508 version = UART_GET_IP_VERSION(port);
1509 switch (version) {
1510 case 0x302:
1511 case 0x10213:
1512 dev_dbg(port->dev, "This version is usart\n");
1513 atmel_port->is_usart = true;
1514 break;
1515 case 0x203:
1516 case 0x10202:
1517 dev_dbg(port->dev, "This version is uart\n");
1518 atmel_port->is_usart = false;
1519 break;
1520 default:
1521 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1522 }
1523 }
1524}
1525
1526/*
1527 * Perform initialization and enable port for reception
1528 */
1529static int atmel_startup(struct uart_port *port)
1530{
1531 struct platform_device *pdev = to_platform_device(port->dev);
1532 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1533 struct tty_struct *tty = port->state->port.tty;
1534 int retval;
1535
1536 /*
1537 * Ensure that no interrupts are enabled otherwise when
1538 * request_irq() is called we could get stuck trying to
1539 * handle an unexpected interrupt
1540 */
1541 UART_PUT_IDR(port, -1);
1542
1543 /*
1544 * Allocate the IRQ
1545 */
1546 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
1547 tty ? tty->name : "atmel_serial", port);
1548 if (retval) {
1549 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1550 return retval;
1551 }
1552
1553 /*
1554 * Initialize DMA (if necessary)
1555 */
1556 atmel_init_property(atmel_port, pdev);
1557
1558 if (atmel_port->prepare_rx) {
1559 retval = atmel_port->prepare_rx(port);
1560 if (retval < 0)
1561 atmel_set_ops(port);
1562 }
1563
1564 if (atmel_port->prepare_tx) {
1565 retval = atmel_port->prepare_tx(port);
1566 if (retval < 0)
1567 atmel_set_ops(port);
1568 }
1569
1570 /* Save current CSR for comparison in atmel_tasklet_func() */
1571 atmel_port->irq_status_prev = UART_GET_CSR(port);
1572 atmel_port->irq_status = atmel_port->irq_status_prev;
1573
1574 /*
1575 * Finally, enable the serial port
1576 */
1577 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1578 /* enable xmit & rcvr */
1579 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1580
1581 setup_timer(&atmel_port->uart_timer,
1582 atmel_uart_timer_callback,
1583 (unsigned long)port);
1584
1585 if (atmel_use_pdc_rx(port)) {
1586 /* set UART timeout */
1587 if (!atmel_port->is_usart) {
1588 mod_timer(&atmel_port->uart_timer,
1589 jiffies + uart_poll_timeout(port));
1590 /* set USART timeout */
1591 } else {
1592 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1593 UART_PUT_CR(port, ATMEL_US_STTTO);
1594
1595 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1596 }
1597 /* enable PDC controller */
1598 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
1599 } else if (atmel_use_dma_rx(port)) {
1600 /* set UART timeout */
1601 if (!atmel_port->is_usart) {
1602 mod_timer(&atmel_port->uart_timer,
1603 jiffies + uart_poll_timeout(port));
1604 /* set USART timeout */
1605 } else {
1606 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1607 UART_PUT_CR(port, ATMEL_US_STTTO);
1608
1609 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1610 }
1611 } else {
1612 /* enable receive only */
1613 UART_PUT_IER(port, ATMEL_US_RXRDY);
1614 }
1615
1616 return 0;
1617}
1618
1619/*
1620 * Disable the port
1621 */
1622static void atmel_shutdown(struct uart_port *port)
1623{
1624 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1625
1626 /*
1627 * Prevent any tasklets being scheduled during
1628 * cleanup
1629 */
1630 del_timer_sync(&atmel_port->uart_timer);
1631
1632 /*
1633 * Clear out any scheduled tasklets before
1634 * we destroy the buffers
1635 */
1636 tasklet_kill(&atmel_port->tasklet);
1637
1638 /*
1639 * Ensure everything is stopped and
1640 * disable all interrupts, port and break condition.
1641 */
1642 atmel_stop_rx(port);
1643 atmel_stop_tx(port);
1644
1645 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1646 UART_PUT_IDR(port, -1);
1647
1648
1649 /*
1650 * Shut-down the DMA.
1651 */
1652 if (atmel_port->release_rx)
1653 atmel_port->release_rx(port);
1654 if (atmel_port->release_tx)
1655 atmel_port->release_tx(port);
1656
1657 /*
1658 * Reset ring buffer pointers
1659 */
1660 atmel_port->rx_ring.head = 0;
1661 atmel_port->rx_ring.tail = 0;
1662
1663 /*
1664 * Free the interrupt
1665 */
1666 free_irq(port->irq, port);
1667}
1668
1669/*
1670 * Flush any TX data submitted for DMA. Called when the TX circular
1671 * buffer is reset.
1672 */
1673static void atmel_flush_buffer(struct uart_port *port)
1674{
1675 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1676
1677 if (atmel_use_pdc_tx(port)) {
1678 UART_PUT_TCR(port, 0);
1679 atmel_port->pdc_tx.ofs = 0;
1680 }
1681}
1682
1683/*
1684 * Power / Clock management.
1685 */
1686static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1687 unsigned int oldstate)
1688{
1689 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1690
1691 switch (state) {
1692 case 0:
1693 /*
1694 * Enable the peripheral clock for this serial port.
1695 * This is called on uart_open() or a resume event.
1696 */
1697 clk_prepare_enable(atmel_port->clk);
1698
1699 /* re-enable interrupts if we disabled some on suspend */
1700 UART_PUT_IER(port, atmel_port->backup_imr);
1701 break;
1702 case 3:
1703 /* Back up the interrupt mask and disable all interrupts */
1704 atmel_port->backup_imr = UART_GET_IMR(port);
1705 UART_PUT_IDR(port, -1);
1706
1707 /*
1708 * Disable the peripheral clock for this serial port.
1709 * This is called on uart_close() or a suspend event.
1710 */
1711 clk_disable_unprepare(atmel_port->clk);
1712 break;
1713 default:
1714 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1715 }
1716}
1717
1718/*
1719 * Change the port parameters
1720 */
1721static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1722 struct ktermios *old)
1723{
1724 unsigned long flags;
1725 unsigned int mode, imr, quot, baud;
1726 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1727
1728 /* Get current mode register */
1729 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1730 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1731 | ATMEL_US_USMODE);
1732
1733 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1734 quot = uart_get_divisor(port, baud);
1735
1736 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1737 quot /= 8;
1738 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1739 }
1740
1741 /* byte size */
1742 switch (termios->c_cflag & CSIZE) {
1743 case CS5:
1744 mode |= ATMEL_US_CHRL_5;
1745 break;
1746 case CS6:
1747 mode |= ATMEL_US_CHRL_6;
1748 break;
1749 case CS7:
1750 mode |= ATMEL_US_CHRL_7;
1751 break;
1752 default:
1753 mode |= ATMEL_US_CHRL_8;
1754 break;
1755 }
1756
1757 /* stop bits */
1758 if (termios->c_cflag & CSTOPB)
1759 mode |= ATMEL_US_NBSTOP_2;
1760
1761 /* parity */
1762 if (termios->c_cflag & PARENB) {
1763 /* Mark or Space parity */
1764 if (termios->c_cflag & CMSPAR) {
1765 if (termios->c_cflag & PARODD)
1766 mode |= ATMEL_US_PAR_MARK;
1767 else
1768 mode |= ATMEL_US_PAR_SPACE;
1769 } else if (termios->c_cflag & PARODD)
1770 mode |= ATMEL_US_PAR_ODD;
1771 else
1772 mode |= ATMEL_US_PAR_EVEN;
1773 } else
1774 mode |= ATMEL_US_PAR_NONE;
1775
1776 /* hardware handshake (RTS/CTS) */
1777 if (termios->c_cflag & CRTSCTS)
1778 mode |= ATMEL_US_USMODE_HWHS;
1779 else
1780 mode |= ATMEL_US_USMODE_NORMAL;
1781
1782 spin_lock_irqsave(&port->lock, flags);
1783
1784 port->read_status_mask = ATMEL_US_OVRE;
1785 if (termios->c_iflag & INPCK)
1786 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1787 if (termios->c_iflag & (BRKINT | PARMRK))
1788 port->read_status_mask |= ATMEL_US_RXBRK;
1789
1790 if (atmel_use_pdc_rx(port))
1791 /* need to enable error interrupts */
1792 UART_PUT_IER(port, port->read_status_mask);
1793
1794 /*
1795 * Characters to ignore
1796 */
1797 port->ignore_status_mask = 0;
1798 if (termios->c_iflag & IGNPAR)
1799 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1800 if (termios->c_iflag & IGNBRK) {
1801 port->ignore_status_mask |= ATMEL_US_RXBRK;
1802 /*
1803 * If we're ignoring parity and break indicators,
1804 * ignore overruns too (for real raw support).
1805 */
1806 if (termios->c_iflag & IGNPAR)
1807 port->ignore_status_mask |= ATMEL_US_OVRE;
1808 }
1809 /* TODO: Ignore all characters if CREAD is set.*/
1810
1811 /* update the per-port timeout */
1812 uart_update_timeout(port, termios->c_cflag, baud);
1813
1814 /*
1815 * save/disable interrupts. The tty layer will ensure that the
1816 * transmitter is empty if requested by the caller, so there's
1817 * no need to wait for it here.
1818 */
1819 imr = UART_GET_IMR(port);
1820 UART_PUT_IDR(port, -1);
1821
1822 /* disable receiver and transmitter */
1823 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1824
1825 /* Resetting serial mode to RS232 (0x0) */
1826 mode &= ~ATMEL_US_USMODE;
1827
1828 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
1829 if ((atmel_port->rs485.delay_rts_after_send) > 0)
1830 UART_PUT_TTGR(port,
1831 atmel_port->rs485.delay_rts_after_send);
1832 mode |= ATMEL_US_USMODE_RS485;
1833 }
1834
1835 /* set the parity, stop bits and data size */
1836 UART_PUT_MR(port, mode);
1837
1838 /* set the baud rate */
1839 UART_PUT_BRGR(port, quot);
1840 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1841 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1842
1843 /* restore interrupts */
1844 UART_PUT_IER(port, imr);
1845
1846 /* CTS flow-control and modem-status interrupts */
1847 if (UART_ENABLE_MS(port, termios->c_cflag))
1848 port->ops->enable_ms(port);
1849
1850 spin_unlock_irqrestore(&port->lock, flags);
1851}
1852
1853static void atmel_set_ldisc(struct uart_port *port, int new)
1854{
1855 if (new == N_PPS) {
1856 port->flags |= UPF_HARDPPS_CD;
1857 atmel_enable_ms(port);
1858 } else {
1859 port->flags &= ~UPF_HARDPPS_CD;
1860 }
1861}
1862
1863/*
1864 * Return string describing the specified port
1865 */
1866static const char *atmel_type(struct uart_port *port)
1867{
1868 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1869}
1870
1871/*
1872 * Release the memory region(s) being used by 'port'.
1873 */
1874static void atmel_release_port(struct uart_port *port)
1875{
1876 struct platform_device *pdev = to_platform_device(port->dev);
1877 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1878
1879 release_mem_region(port->mapbase, size);
1880
1881 if (port->flags & UPF_IOREMAP) {
1882 iounmap(port->membase);
1883 port->membase = NULL;
1884 }
1885}
1886
1887/*
1888 * Request the memory region(s) being used by 'port'.
1889 */
1890static int atmel_request_port(struct uart_port *port)
1891{
1892 struct platform_device *pdev = to_platform_device(port->dev);
1893 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1894
1895 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
1896 return -EBUSY;
1897
1898 if (port->flags & UPF_IOREMAP) {
1899 port->membase = ioremap(port->mapbase, size);
1900 if (port->membase == NULL) {
1901 release_mem_region(port->mapbase, size);
1902 return -ENOMEM;
1903 }
1904 }
1905
1906 return 0;
1907}
1908
1909/*
1910 * Configure/autoconfigure the port.
1911 */
1912static void atmel_config_port(struct uart_port *port, int flags)
1913{
1914 if (flags & UART_CONFIG_TYPE) {
1915 port->type = PORT_ATMEL;
1916 atmel_request_port(port);
1917 }
1918}
1919
1920/*
1921 * Verify the new serial_struct (for TIOCSSERIAL).
1922 */
1923static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1924{
1925 int ret = 0;
1926 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1927 ret = -EINVAL;
1928 if (port->irq != ser->irq)
1929 ret = -EINVAL;
1930 if (ser->io_type != SERIAL_IO_MEM)
1931 ret = -EINVAL;
1932 if (port->uartclk / 16 != ser->baud_base)
1933 ret = -EINVAL;
1934 if ((void *)port->mapbase != ser->iomem_base)
1935 ret = -EINVAL;
1936 if (port->iobase != ser->port)
1937 ret = -EINVAL;
1938 if (ser->hub6 != 0)
1939 ret = -EINVAL;
1940 return ret;
1941}
1942
1943#ifdef CONFIG_CONSOLE_POLL
1944static int atmel_poll_get_char(struct uart_port *port)
1945{
1946 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
1947 cpu_relax();
1948
1949 return UART_GET_CHAR(port);
1950}
1951
1952static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
1953{
1954 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1955 cpu_relax();
1956
1957 UART_PUT_CHAR(port, ch);
1958}
1959#endif
1960
1961static int
1962atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1963{
1964 struct serial_rs485 rs485conf;
1965
1966 switch (cmd) {
1967 case TIOCSRS485:
1968 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1969 sizeof(rs485conf)))
1970 return -EFAULT;
1971
1972 atmel_config_rs485(port, &rs485conf);
1973 break;
1974
1975 case TIOCGRS485:
1976 if (copy_to_user((struct serial_rs485 *) arg,
1977 &(to_atmel_uart_port(port)->rs485),
1978 sizeof(rs485conf)))
1979 return -EFAULT;
1980 break;
1981
1982 default:
1983 return -ENOIOCTLCMD;
1984 }
1985 return 0;
1986}
1987
1988
1989
1990static struct uart_ops atmel_pops = {
1991 .tx_empty = atmel_tx_empty,
1992 .set_mctrl = atmel_set_mctrl,
1993 .get_mctrl = atmel_get_mctrl,
1994 .stop_tx = atmel_stop_tx,
1995 .start_tx = atmel_start_tx,
1996 .stop_rx = atmel_stop_rx,
1997 .enable_ms = atmel_enable_ms,
1998 .break_ctl = atmel_break_ctl,
1999 .startup = atmel_startup,
2000 .shutdown = atmel_shutdown,
2001 .flush_buffer = atmel_flush_buffer,
2002 .set_termios = atmel_set_termios,
2003 .set_ldisc = atmel_set_ldisc,
2004 .type = atmel_type,
2005 .release_port = atmel_release_port,
2006 .request_port = atmel_request_port,
2007 .config_port = atmel_config_port,
2008 .verify_port = atmel_verify_port,
2009 .pm = atmel_serial_pm,
2010 .ioctl = atmel_ioctl,
2011#ifdef CONFIG_CONSOLE_POLL
2012 .poll_get_char = atmel_poll_get_char,
2013 .poll_put_char = atmel_poll_put_char,
2014#endif
2015};
2016
2017/*
2018 * Configure the port from the platform device resource info.
2019 */
2020static int atmel_init_port(struct atmel_uart_port *atmel_port,
2021 struct platform_device *pdev)
2022{
2023 int ret;
2024 struct uart_port *port = &atmel_port->uart;
2025 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2026
2027 if (!atmel_init_property(atmel_port, pdev))
2028 atmel_set_ops(port);
2029
2030 atmel_init_rs485(atmel_port, pdev);
2031
2032 port->iotype = UPIO_MEM;
2033 port->flags = UPF_BOOT_AUTOCONF;
2034 port->ops = &atmel_pops;
2035 port->fifosize = 1;
2036 port->dev = &pdev->dev;
2037 port->mapbase = pdev->resource[0].start;
2038 port->irq = pdev->resource[1].start;
2039
2040 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2041 (unsigned long)port);
2042
2043 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2044
2045 if (pdata && pdata->regs) {
2046 /* Already mapped by setup code */
2047 port->membase = pdata->regs;
2048 } else {
2049 port->flags |= UPF_IOREMAP;
2050 port->membase = NULL;
2051 }
2052
2053 /* for console, the clock could already be configured */
2054 if (!atmel_port->clk) {
2055 atmel_port->clk = clk_get(&pdev->dev, "usart");
2056 if (IS_ERR(atmel_port->clk)) {
2057 ret = PTR_ERR(atmel_port->clk);
2058 atmel_port->clk = NULL;
2059 return ret;
2060 }
2061 ret = clk_prepare_enable(atmel_port->clk);
2062 if (ret) {
2063 clk_put(atmel_port->clk);
2064 atmel_port->clk = NULL;
2065 return ret;
2066 }
2067 port->uartclk = clk_get_rate(atmel_port->clk);
2068 clk_disable_unprepare(atmel_port->clk);
2069 /* only enable clock when USART is in use */
2070 }
2071
2072 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2073 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
2074 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2075 else if (atmel_use_pdc_tx(port)) {
2076 port->fifosize = PDC_BUFFER_SIZE;
2077 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2078 } else {
2079 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2080 }
2081
2082 return 0;
2083}
2084
2085struct platform_device *atmel_default_console_device; /* the serial console device */
2086
2087#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2088static void atmel_console_putchar(struct uart_port *port, int ch)
2089{
2090 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2091 cpu_relax();
2092 UART_PUT_CHAR(port, ch);
2093}
2094
2095/*
2096 * Interrupts are disabled on entering
2097 */
2098static void atmel_console_write(struct console *co, const char *s, u_int count)
2099{
2100 struct uart_port *port = &atmel_ports[co->index].uart;
2101 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2102 unsigned int status, imr;
2103 unsigned int pdc_tx;
2104
2105 /*
2106 * First, save IMR and then disable interrupts
2107 */
2108 imr = UART_GET_IMR(port);
2109 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2110
2111 /* Store PDC transmit status and disable it */
2112 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2113 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2114
2115 uart_console_write(port, s, count, atmel_console_putchar);
2116
2117 /*
2118 * Finally, wait for transmitter to become empty
2119 * and restore IMR
2120 */
2121 do {
2122 status = UART_GET_CSR(port);
2123 } while (!(status & ATMEL_US_TXRDY));
2124
2125 /* Restore PDC transmit status */
2126 if (pdc_tx)
2127 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2128
2129 /* set interrupts back the way they were */
2130 UART_PUT_IER(port, imr);
2131}
2132
2133/*
2134 * If the port was already initialised (eg, by a boot loader),
2135 * try to determine the current setup.
2136 */
2137static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2138 int *parity, int *bits)
2139{
2140 unsigned int mr, quot;
2141
2142 /*
2143 * If the baud rate generator isn't running, the port wasn't
2144 * initialized by the boot loader.
2145 */
2146 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
2147 if (!quot)
2148 return;
2149
2150 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2151 if (mr == ATMEL_US_CHRL_8)
2152 *bits = 8;
2153 else
2154 *bits = 7;
2155
2156 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2157 if (mr == ATMEL_US_PAR_EVEN)
2158 *parity = 'e';
2159 else if (mr == ATMEL_US_PAR_ODD)
2160 *parity = 'o';
2161
2162 /*
2163 * The serial core only rounds down when matching this to a
2164 * supported baud rate. Make sure we don't end up slightly
2165 * lower than one of those, as it would make us fall through
2166 * to a much lower baud rate than we really want.
2167 */
2168 *baud = port->uartclk / (16 * (quot - 1));
2169}
2170
2171static int __init atmel_console_setup(struct console *co, char *options)
2172{
2173 int ret;
2174 struct uart_port *port = &atmel_ports[co->index].uart;
2175 int baud = 115200;
2176 int bits = 8;
2177 int parity = 'n';
2178 int flow = 'n';
2179
2180 if (port->membase == NULL) {
2181 /* Port not initialized yet - delay setup */
2182 return -ENODEV;
2183 }
2184
2185 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2186 if (ret)
2187 return ret;
2188
2189 UART_PUT_IDR(port, -1);
2190 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2191 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
2192
2193 if (options)
2194 uart_parse_options(options, &baud, &parity, &bits, &flow);
2195 else
2196 atmel_console_get_options(port, &baud, &parity, &bits);
2197
2198 return uart_set_options(port, co, baud, parity, bits, flow);
2199}
2200
2201static struct uart_driver atmel_uart;
2202
2203static struct console atmel_console = {
2204 .name = ATMEL_DEVICENAME,
2205 .write = atmel_console_write,
2206 .device = uart_console_device,
2207 .setup = atmel_console_setup,
2208 .flags = CON_PRINTBUFFER,
2209 .index = -1,
2210 .data = &atmel_uart,
2211};
2212
2213#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2214
2215/*
2216 * Early console initialization (before VM subsystem initialized).
2217 */
2218static int __init atmel_console_init(void)
2219{
2220 int ret;
2221 if (atmel_default_console_device) {
2222 struct atmel_uart_data *pdata =
2223 dev_get_platdata(&atmel_default_console_device->dev);
2224 int id = pdata->num;
2225 struct atmel_uart_port *port = &atmel_ports[id];
2226
2227 port->backup_imr = 0;
2228 port->uart.line = id;
2229
2230 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2231 ret = atmel_init_port(port, atmel_default_console_device);
2232 if (ret)
2233 return ret;
2234 register_console(&atmel_console);
2235 }
2236
2237 return 0;
2238}
2239
2240console_initcall(atmel_console_init);
2241
2242/*
2243 * Late console initialization.
2244 */
2245static int __init atmel_late_console_init(void)
2246{
2247 if (atmel_default_console_device
2248 && !(atmel_console.flags & CON_ENABLED))
2249 register_console(&atmel_console);
2250
2251 return 0;
2252}
2253
2254core_initcall(atmel_late_console_init);
2255
2256static inline bool atmel_is_console_port(struct uart_port *port)
2257{
2258 return port->cons && port->cons->index == port->line;
2259}
2260
2261#else
2262#define ATMEL_CONSOLE_DEVICE NULL
2263
2264static inline bool atmel_is_console_port(struct uart_port *port)
2265{
2266 return false;
2267}
2268#endif
2269
2270static struct uart_driver atmel_uart = {
2271 .owner = THIS_MODULE,
2272 .driver_name = "atmel_serial",
2273 .dev_name = ATMEL_DEVICENAME,
2274 .major = SERIAL_ATMEL_MAJOR,
2275 .minor = MINOR_START,
2276 .nr = ATMEL_MAX_UART,
2277 .cons = ATMEL_CONSOLE_DEVICE,
2278};
2279
2280#ifdef CONFIG_PM
2281static bool atmel_serial_clk_will_stop(void)
2282{
2283#ifdef CONFIG_ARCH_AT91
2284 return at91_suspend_entering_slow_clock();
2285#else
2286 return false;
2287#endif
2288}
2289
2290static int atmel_serial_suspend(struct platform_device *pdev,
2291 pm_message_t state)
2292{
2293 struct uart_port *port = platform_get_drvdata(pdev);
2294 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2295
2296 if (atmel_is_console_port(port) && console_suspend_enabled) {
2297 /* Drain the TX shifter */
2298 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2299 cpu_relax();
2300 }
2301
2302 /* we can not wake up if we're running on slow clock */
2303 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2304 if (atmel_serial_clk_will_stop())
2305 device_set_wakeup_enable(&pdev->dev, 0);
2306
2307 uart_suspend_port(&atmel_uart, port);
2308
2309 return 0;
2310}
2311
2312static int atmel_serial_resume(struct platform_device *pdev)
2313{
2314 struct uart_port *port = platform_get_drvdata(pdev);
2315 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2316
2317 uart_resume_port(&atmel_uart, port);
2318 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2319
2320 return 0;
2321}
2322#else
2323#define atmel_serial_suspend NULL
2324#define atmel_serial_resume NULL
2325#endif
2326
2327static int atmel_serial_probe(struct platform_device *pdev)
2328{
2329 struct atmel_uart_port *port;
2330 struct device_node *np = pdev->dev.of_node;
2331 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2332 void *data;
2333 int ret = -ENODEV;
2334
2335 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2336
2337 if (np)
2338 ret = of_alias_get_id(np, "serial");
2339 else
2340 if (pdata)
2341 ret = pdata->num;
2342
2343 if (ret < 0)
2344 /* port id not found in platform data nor device-tree aliases:
2345 * auto-enumerate it */
2346 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2347
2348 if (ret >= ATMEL_MAX_UART) {
2349 ret = -ENODEV;
2350 goto err;
2351 }
2352
2353 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2354 /* port already in use */
2355 ret = -EBUSY;
2356 goto err;
2357 }
2358
2359 port = &atmel_ports[ret];
2360 port->backup_imr = 0;
2361 port->uart.line = ret;
2362 port->rts_gpio = -EINVAL; /* Invalid, zero could be valid */
2363 if (pdata)
2364 port->rts_gpio = pdata->rts_gpio;
2365 else if (np)
2366 port->rts_gpio = of_get_named_gpio(np, "rts-gpios", 0);
2367
2368 if (gpio_is_valid(port->rts_gpio)) {
2369 ret = devm_gpio_request(&pdev->dev, port->rts_gpio, "RTS");
2370 if (ret) {
2371 dev_err(&pdev->dev, "error requesting RTS GPIO\n");
2372 goto err;
2373 }
2374 /* Default to 1 as RTS is active low */
2375 ret = gpio_direction_output(port->rts_gpio, 1);
2376 if (ret) {
2377 dev_err(&pdev->dev, "error setting up RTS GPIO\n");
2378 goto err;
2379 }
2380 }
2381
2382 ret = atmel_init_port(port, pdev);
2383 if (ret)
2384 goto err;
2385
2386 if (!atmel_use_pdc_rx(&port->uart)) {
2387 ret = -ENOMEM;
2388 data = kmalloc(sizeof(struct atmel_uart_char)
2389 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2390 if (!data)
2391 goto err_alloc_ring;
2392 port->rx_ring.buf = data;
2393 }
2394
2395 ret = uart_add_one_port(&atmel_uart, &port->uart);
2396 if (ret)
2397 goto err_add_port;
2398
2399#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2400 if (atmel_is_console_port(&port->uart)
2401 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2402 /*
2403 * The serial core enabled the clock for us, so undo
2404 * the clk_prepare_enable() in atmel_console_setup()
2405 */
2406 clk_disable_unprepare(port->clk);
2407 }
2408#endif
2409
2410 device_init_wakeup(&pdev->dev, 1);
2411 platform_set_drvdata(pdev, port);
2412
2413 if (port->rs485.flags & SER_RS485_ENABLED) {
2414 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2415 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2416 }
2417
2418 /*
2419 * Get port name of usart or uart
2420 */
2421 atmel_get_ip_name(&port->uart);
2422
2423 return 0;
2424
2425err_add_port:
2426 kfree(port->rx_ring.buf);
2427 port->rx_ring.buf = NULL;
2428err_alloc_ring:
2429 if (!atmel_is_console_port(&port->uart)) {
2430 clk_put(port->clk);
2431 port->clk = NULL;
2432 }
2433err:
2434 return ret;
2435}
2436
2437static int atmel_serial_remove(struct platform_device *pdev)
2438{
2439 struct uart_port *port = platform_get_drvdata(pdev);
2440 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2441 int ret = 0;
2442
2443 tasklet_kill(&atmel_port->tasklet);
2444
2445 device_init_wakeup(&pdev->dev, 0);
2446
2447 ret = uart_remove_one_port(&atmel_uart, port);
2448
2449 kfree(atmel_port->rx_ring.buf);
2450
2451 /* "port" is allocated statically, so we shouldn't free it */
2452
2453 clear_bit(port->line, atmel_ports_in_use);
2454
2455 clk_put(atmel_port->clk);
2456
2457 return ret;
2458}
2459
2460static struct platform_driver atmel_serial_driver = {
2461 .probe = atmel_serial_probe,
2462 .remove = atmel_serial_remove,
2463 .suspend = atmel_serial_suspend,
2464 .resume = atmel_serial_resume,
2465 .driver = {
2466 .name = "atmel_usart",
2467 .owner = THIS_MODULE,
2468 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2469 },
2470};
2471
2472static int __init atmel_serial_init(void)
2473{
2474 int ret;
2475
2476 ret = uart_register_driver(&atmel_uart);
2477 if (ret)
2478 return ret;
2479
2480 ret = platform_driver_register(&atmel_serial_driver);
2481 if (ret)
2482 uart_unregister_driver(&atmel_uart);
2483
2484 return ret;
2485}
2486
2487static void __exit atmel_serial_exit(void)
2488{
2489 platform_driver_unregister(&atmel_serial_driver);
2490 uart_unregister_driver(&atmel_uart);
2491}
2492
2493module_init(atmel_serial_init);
2494module_exit(atmel_serial_exit);
2495
2496MODULE_AUTHOR("Rick Bronson");
2497MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2498MODULE_LICENSE("GPL");
2499MODULE_ALIAS("platform:atmel_usart");