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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Core driver for the Synopsys DesignWare DMA Controller
4 *
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
7 * Copyright (C) 2013 Intel Corporation
8 */
9
10#include <linux/bitops.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/mm.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/pm_runtime.h>
23
24#include "../dmaengine.h"
25#include "internal.h"
26
27/*
28 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
29 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
30 * of which use ARM any more). See the "Databook" from Synopsys for
31 * information beyond what licensees probably provide.
32 */
33
34/* The set of bus widths supported by the DMA controller */
35#define DW_DMA_BUSWIDTHS \
36 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
37 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
38 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
39 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
40
41/*----------------------------------------------------------------------*/
42
43static struct device *chan2dev(struct dma_chan *chan)
44{
45 return &chan->dev->device;
46}
47
48static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
49{
50 return to_dw_desc(dwc->active_list.next);
51}
52
53static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
54{
55 struct dw_desc *desc = txd_to_dw_desc(tx);
56 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
57 dma_cookie_t cookie;
58 unsigned long flags;
59
60 spin_lock_irqsave(&dwc->lock, flags);
61 cookie = dma_cookie_assign(tx);
62
63 /*
64 * REVISIT: We should attempt to chain as many descriptors as
65 * possible, perhaps even appending to those already submitted
66 * for DMA. But this is hard to do in a race-free manner.
67 */
68
69 list_add_tail(&desc->desc_node, &dwc->queue);
70 spin_unlock_irqrestore(&dwc->lock, flags);
71 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n",
72 __func__, desc->txd.cookie);
73
74 return cookie;
75}
76
77static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
78{
79 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
80 struct dw_desc *desc;
81 dma_addr_t phys;
82
83 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys);
84 if (!desc)
85 return NULL;
86
87 dwc->descs_allocated++;
88 INIT_LIST_HEAD(&desc->tx_list);
89 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan);
90 desc->txd.tx_submit = dwc_tx_submit;
91 desc->txd.flags = DMA_CTRL_ACK;
92 desc->txd.phys = phys;
93 return desc;
94}
95
96static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
97{
98 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
99 struct dw_desc *child, *_next;
100
101 if (unlikely(!desc))
102 return;
103
104 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) {
105 list_del(&child->desc_node);
106 dma_pool_free(dw->desc_pool, child, child->txd.phys);
107 dwc->descs_allocated--;
108 }
109
110 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
111 dwc->descs_allocated--;
112}
113
114static void dwc_initialize(struct dw_dma_chan *dwc)
115{
116 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
117
118 dw->initialize_chan(dwc);
119
120 /* Enable interrupts */
121 channel_set_bit(dw, MASK.XFER, dwc->mask);
122 channel_set_bit(dw, MASK.ERROR, dwc->mask);
123}
124
125/*----------------------------------------------------------------------*/
126
127static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
128{
129 dev_err(chan2dev(&dwc->chan),
130 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
131 channel_readl(dwc, SAR),
132 channel_readl(dwc, DAR),
133 channel_readl(dwc, LLP),
134 channel_readl(dwc, CTL_HI),
135 channel_readl(dwc, CTL_LO));
136}
137
138static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
139{
140 channel_clear_bit(dw, CH_EN, dwc->mask);
141 while (dma_readl(dw, CH_EN) & dwc->mask)
142 cpu_relax();
143}
144
145/*----------------------------------------------------------------------*/
146
147/* Perform single block transfer */
148static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
149 struct dw_desc *desc)
150{
151 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
152 u32 ctllo;
153
154 /*
155 * Software emulation of LLP mode relies on interrupts to continue
156 * multi block transfer.
157 */
158 ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN;
159
160 channel_writel(dwc, SAR, lli_read(desc, sar));
161 channel_writel(dwc, DAR, lli_read(desc, dar));
162 channel_writel(dwc, CTL_LO, ctllo);
163 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi));
164 channel_set_bit(dw, CH_EN, dwc->mask);
165
166 /* Move pointer to next descriptor */
167 dwc->tx_node_active = dwc->tx_node_active->next;
168}
169
170/* Called with dwc->lock held and bh disabled */
171static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
172{
173 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
174 u8 lms = DWC_LLP_LMS(dwc->dws.m_master);
175 unsigned long was_soft_llp;
176
177 /* ASSERT: channel is idle */
178 if (dma_readl(dw, CH_EN) & dwc->mask) {
179 dev_err(chan2dev(&dwc->chan),
180 "%s: BUG: Attempted to start non-idle channel\n",
181 __func__);
182 dwc_dump_chan_regs(dwc);
183
184 /* The tasklet will hopefully advance the queue... */
185 return;
186 }
187
188 if (dwc->nollp) {
189 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
190 &dwc->flags);
191 if (was_soft_llp) {
192 dev_err(chan2dev(&dwc->chan),
193 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
194 return;
195 }
196
197 dwc_initialize(dwc);
198
199 first->residue = first->total_len;
200 dwc->tx_node_active = &first->tx_list;
201
202 /* Submit first block */
203 dwc_do_single_block(dwc, first);
204
205 return;
206 }
207
208 dwc_initialize(dwc);
209
210 channel_writel(dwc, LLP, first->txd.phys | lms);
211 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
212 channel_writel(dwc, CTL_HI, 0);
213 channel_set_bit(dw, CH_EN, dwc->mask);
214}
215
216static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
217{
218 struct dw_desc *desc;
219
220 if (list_empty(&dwc->queue))
221 return;
222
223 list_move(dwc->queue.next, &dwc->active_list);
224 desc = dwc_first_active(dwc);
225 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
226 dwc_dostart(dwc, desc);
227}
228
229/*----------------------------------------------------------------------*/
230
231static void
232dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
233 bool callback_required)
234{
235 struct dma_async_tx_descriptor *txd = &desc->txd;
236 struct dw_desc *child;
237 unsigned long flags;
238 struct dmaengine_desc_callback cb;
239
240 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
241
242 spin_lock_irqsave(&dwc->lock, flags);
243 dma_cookie_complete(txd);
244 if (callback_required)
245 dmaengine_desc_get_callback(txd, &cb);
246 else
247 memset(&cb, 0, sizeof(cb));
248
249 /* async_tx_ack */
250 list_for_each_entry(child, &desc->tx_list, desc_node)
251 async_tx_ack(&child->txd);
252 async_tx_ack(&desc->txd);
253 dwc_desc_put(dwc, desc);
254 spin_unlock_irqrestore(&dwc->lock, flags);
255
256 dmaengine_desc_callback_invoke(&cb, NULL);
257}
258
259static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
260{
261 struct dw_desc *desc, *_desc;
262 LIST_HEAD(list);
263 unsigned long flags;
264
265 spin_lock_irqsave(&dwc->lock, flags);
266 if (dma_readl(dw, CH_EN) & dwc->mask) {
267 dev_err(chan2dev(&dwc->chan),
268 "BUG: XFER bit set, but channel not idle!\n");
269
270 /* Try to continue after resetting the channel... */
271 dwc_chan_disable(dw, dwc);
272 }
273
274 /*
275 * Submit queued descriptors ASAP, i.e. before we go through
276 * the completed ones.
277 */
278 list_splice_init(&dwc->active_list, &list);
279 dwc_dostart_first_queued(dwc);
280
281 spin_unlock_irqrestore(&dwc->lock, flags);
282
283 list_for_each_entry_safe(desc, _desc, &list, desc_node)
284 dwc_descriptor_complete(dwc, desc, true);
285}
286
287/* Returns how many bytes were already received from source */
288static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
289{
290 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
291 u32 ctlhi = channel_readl(dwc, CTL_HI);
292 u32 ctllo = channel_readl(dwc, CTL_LO);
293
294 return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7);
295}
296
297static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
298{
299 dma_addr_t llp;
300 struct dw_desc *desc, *_desc;
301 struct dw_desc *child;
302 u32 status_xfer;
303 unsigned long flags;
304
305 spin_lock_irqsave(&dwc->lock, flags);
306 llp = channel_readl(dwc, LLP);
307 status_xfer = dma_readl(dw, RAW.XFER);
308
309 if (status_xfer & dwc->mask) {
310 /* Everything we've submitted is done */
311 dma_writel(dw, CLEAR.XFER, dwc->mask);
312
313 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
314 struct list_head *head, *active = dwc->tx_node_active;
315
316 /*
317 * We are inside first active descriptor.
318 * Otherwise something is really wrong.
319 */
320 desc = dwc_first_active(dwc);
321
322 head = &desc->tx_list;
323 if (active != head) {
324 /* Update residue to reflect last sent descriptor */
325 if (active == head->next)
326 desc->residue -= desc->len;
327 else
328 desc->residue -= to_dw_desc(active->prev)->len;
329
330 child = to_dw_desc(active);
331
332 /* Submit next block */
333 dwc_do_single_block(dwc, child);
334
335 spin_unlock_irqrestore(&dwc->lock, flags);
336 return;
337 }
338
339 /* We are done here */
340 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
341 }
342
343 spin_unlock_irqrestore(&dwc->lock, flags);
344
345 dwc_complete_all(dw, dwc);
346 return;
347 }
348
349 if (list_empty(&dwc->active_list)) {
350 spin_unlock_irqrestore(&dwc->lock, flags);
351 return;
352 }
353
354 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
355 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
356 spin_unlock_irqrestore(&dwc->lock, flags);
357 return;
358 }
359
360 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
361
362 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
363 /* Initial residue value */
364 desc->residue = desc->total_len;
365
366 /* Check first descriptors addr */
367 if (desc->txd.phys == DWC_LLP_LOC(llp)) {
368 spin_unlock_irqrestore(&dwc->lock, flags);
369 return;
370 }
371
372 /* Check first descriptors llp */
373 if (lli_read(desc, llp) == llp) {
374 /* This one is currently in progress */
375 desc->residue -= dwc_get_sent(dwc);
376 spin_unlock_irqrestore(&dwc->lock, flags);
377 return;
378 }
379
380 desc->residue -= desc->len;
381 list_for_each_entry(child, &desc->tx_list, desc_node) {
382 if (lli_read(child, llp) == llp) {
383 /* Currently in progress */
384 desc->residue -= dwc_get_sent(dwc);
385 spin_unlock_irqrestore(&dwc->lock, flags);
386 return;
387 }
388 desc->residue -= child->len;
389 }
390
391 /*
392 * No descriptors so far seem to be in progress, i.e.
393 * this one must be done.
394 */
395 spin_unlock_irqrestore(&dwc->lock, flags);
396 dwc_descriptor_complete(dwc, desc, true);
397 spin_lock_irqsave(&dwc->lock, flags);
398 }
399
400 dev_err(chan2dev(&dwc->chan),
401 "BUG: All descriptors done, but channel not idle!\n");
402
403 /* Try to continue after resetting the channel... */
404 dwc_chan_disable(dw, dwc);
405
406 dwc_dostart_first_queued(dwc);
407 spin_unlock_irqrestore(&dwc->lock, flags);
408}
409
410static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc)
411{
412 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
413 lli_read(desc, sar),
414 lli_read(desc, dar),
415 lli_read(desc, llp),
416 lli_read(desc, ctlhi),
417 lli_read(desc, ctllo));
418}
419
420static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
421{
422 struct dw_desc *bad_desc;
423 struct dw_desc *child;
424 unsigned long flags;
425
426 dwc_scan_descriptors(dw, dwc);
427
428 spin_lock_irqsave(&dwc->lock, flags);
429
430 /*
431 * The descriptor currently at the head of the active list is
432 * borked. Since we don't have any way to report errors, we'll
433 * just have to scream loudly and try to carry on.
434 */
435 bad_desc = dwc_first_active(dwc);
436 list_del_init(&bad_desc->desc_node);
437 list_move(dwc->queue.next, dwc->active_list.prev);
438
439 /* Clear the error flag and try to restart the controller */
440 dma_writel(dw, CLEAR.ERROR, dwc->mask);
441 if (!list_empty(&dwc->active_list))
442 dwc_dostart(dwc, dwc_first_active(dwc));
443
444 /*
445 * WARN may seem harsh, but since this only happens
446 * when someone submits a bad physical address in a
447 * descriptor, we should consider ourselves lucky that the
448 * controller flagged an error instead of scribbling over
449 * random memory locations.
450 */
451 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
452 " cookie: %d\n", bad_desc->txd.cookie);
453 dwc_dump_lli(dwc, bad_desc);
454 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
455 dwc_dump_lli(dwc, child);
456
457 spin_unlock_irqrestore(&dwc->lock, flags);
458
459 /* Pretend the descriptor completed successfully */
460 dwc_descriptor_complete(dwc, bad_desc, true);
461}
462
463static void dw_dma_tasklet(struct tasklet_struct *t)
464{
465 struct dw_dma *dw = from_tasklet(dw, t, tasklet);
466 struct dw_dma_chan *dwc;
467 u32 status_xfer;
468 u32 status_err;
469 unsigned int i;
470
471 status_xfer = dma_readl(dw, RAW.XFER);
472 status_err = dma_readl(dw, RAW.ERROR);
473
474 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
475
476 for (i = 0; i < dw->dma.chancnt; i++) {
477 dwc = &dw->chan[i];
478 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
479 dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n");
480 else if (status_err & (1 << i))
481 dwc_handle_error(dw, dwc);
482 else if (status_xfer & (1 << i))
483 dwc_scan_descriptors(dw, dwc);
484 }
485
486 /* Re-enable interrupts */
487 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
488 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
489}
490
491static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
492{
493 struct dw_dma *dw = dev_id;
494 u32 status;
495
496 /* Check if we have any interrupt from the DMAC which is not in use */
497 if (!dw->in_use)
498 return IRQ_NONE;
499
500 status = dma_readl(dw, STATUS_INT);
501 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
502
503 /* Check if we have any interrupt from the DMAC */
504 if (!status)
505 return IRQ_NONE;
506
507 /*
508 * Just disable the interrupts. We'll turn them back on in the
509 * softirq handler.
510 */
511 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
512 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
513 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
514
515 status = dma_readl(dw, STATUS_INT);
516 if (status) {
517 dev_err(dw->dma.dev,
518 "BUG: Unexpected interrupts pending: 0x%x\n",
519 status);
520
521 /* Try to recover */
522 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
523 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
524 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
525 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
526 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
527 }
528
529 tasklet_schedule(&dw->tasklet);
530
531 return IRQ_HANDLED;
532}
533
534/*----------------------------------------------------------------------*/
535
536static struct dma_async_tx_descriptor *
537dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
538 size_t len, unsigned long flags)
539{
540 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
541 struct dw_dma *dw = to_dw_dma(chan->device);
542 struct dw_desc *desc;
543 struct dw_desc *first;
544 struct dw_desc *prev;
545 size_t xfer_count;
546 size_t offset;
547 u8 m_master = dwc->dws.m_master;
548 unsigned int src_width;
549 unsigned int dst_width;
550 unsigned int data_width = dw->pdata->data_width[m_master];
551 u32 ctllo, ctlhi;
552 u8 lms = DWC_LLP_LMS(m_master);
553
554 dev_vdbg(chan2dev(chan),
555 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
556 &dest, &src, len, flags);
557
558 if (unlikely(!len)) {
559 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
560 return NULL;
561 }
562
563 dwc->direction = DMA_MEM_TO_MEM;
564
565 src_width = dst_width = __ffs(data_width | src | dest | len);
566
567 ctllo = dw->prepare_ctllo(dwc)
568 | DWC_CTLL_DST_WIDTH(dst_width)
569 | DWC_CTLL_SRC_WIDTH(src_width)
570 | DWC_CTLL_DST_INC
571 | DWC_CTLL_SRC_INC
572 | DWC_CTLL_FC_M2M;
573 prev = first = NULL;
574
575 for (offset = 0; offset < len; offset += xfer_count) {
576 desc = dwc_desc_get(dwc);
577 if (!desc)
578 goto err_desc_get;
579
580 ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count);
581
582 lli_write(desc, sar, src + offset);
583 lli_write(desc, dar, dest + offset);
584 lli_write(desc, ctllo, ctllo);
585 lli_write(desc, ctlhi, ctlhi);
586 desc->len = xfer_count;
587
588 if (!first) {
589 first = desc;
590 } else {
591 lli_write(prev, llp, desc->txd.phys | lms);
592 list_add_tail(&desc->desc_node, &first->tx_list);
593 }
594 prev = desc;
595 }
596
597 if (flags & DMA_PREP_INTERRUPT)
598 /* Trigger interrupt after last block */
599 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
600
601 prev->lli.llp = 0;
602 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
603 first->txd.flags = flags;
604 first->total_len = len;
605
606 return &first->txd;
607
608err_desc_get:
609 dwc_desc_put(dwc, first);
610 return NULL;
611}
612
613static struct dma_async_tx_descriptor *
614dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
615 unsigned int sg_len, enum dma_transfer_direction direction,
616 unsigned long flags, void *context)
617{
618 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
619 struct dw_dma *dw = to_dw_dma(chan->device);
620 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
621 struct dw_desc *prev;
622 struct dw_desc *first;
623 u32 ctllo, ctlhi;
624 u8 m_master = dwc->dws.m_master;
625 u8 lms = DWC_LLP_LMS(m_master);
626 dma_addr_t reg;
627 unsigned int reg_width;
628 unsigned int mem_width;
629 unsigned int data_width = dw->pdata->data_width[m_master];
630 unsigned int i;
631 struct scatterlist *sg;
632 size_t total_len = 0;
633
634 dev_vdbg(chan2dev(chan), "%s\n", __func__);
635
636 if (unlikely(!is_slave_direction(direction) || !sg_len))
637 return NULL;
638
639 dwc->direction = direction;
640
641 prev = first = NULL;
642
643 switch (direction) {
644 case DMA_MEM_TO_DEV:
645 reg_width = __ffs(sconfig->dst_addr_width);
646 reg = sconfig->dst_addr;
647 ctllo = dw->prepare_ctllo(dwc)
648 | DWC_CTLL_DST_WIDTH(reg_width)
649 | DWC_CTLL_DST_FIX
650 | DWC_CTLL_SRC_INC;
651
652 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
653 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
654
655 for_each_sg(sgl, sg, sg_len, i) {
656 struct dw_desc *desc;
657 u32 len, mem;
658 size_t dlen;
659
660 mem = sg_dma_address(sg);
661 len = sg_dma_len(sg);
662
663 mem_width = __ffs(data_width | mem | len);
664
665slave_sg_todev_fill_desc:
666 desc = dwc_desc_get(dwc);
667 if (!desc)
668 goto err_desc_get;
669
670 ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen);
671
672 lli_write(desc, sar, mem);
673 lli_write(desc, dar, reg);
674 lli_write(desc, ctlhi, ctlhi);
675 lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width));
676 desc->len = dlen;
677
678 if (!first) {
679 first = desc;
680 } else {
681 lli_write(prev, llp, desc->txd.phys | lms);
682 list_add_tail(&desc->desc_node, &first->tx_list);
683 }
684 prev = desc;
685
686 mem += dlen;
687 len -= dlen;
688 total_len += dlen;
689
690 if (len)
691 goto slave_sg_todev_fill_desc;
692 }
693 break;
694 case DMA_DEV_TO_MEM:
695 reg_width = __ffs(sconfig->src_addr_width);
696 reg = sconfig->src_addr;
697 ctllo = dw->prepare_ctllo(dwc)
698 | DWC_CTLL_SRC_WIDTH(reg_width)
699 | DWC_CTLL_DST_INC
700 | DWC_CTLL_SRC_FIX;
701
702 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
703 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
704
705 for_each_sg(sgl, sg, sg_len, i) {
706 struct dw_desc *desc;
707 u32 len, mem;
708 size_t dlen;
709
710 mem = sg_dma_address(sg);
711 len = sg_dma_len(sg);
712
713slave_sg_fromdev_fill_desc:
714 desc = dwc_desc_get(dwc);
715 if (!desc)
716 goto err_desc_get;
717
718 ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen);
719
720 lli_write(desc, sar, reg);
721 lli_write(desc, dar, mem);
722 lli_write(desc, ctlhi, ctlhi);
723 mem_width = __ffs(data_width | mem);
724 lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
725 desc->len = dlen;
726
727 if (!first) {
728 first = desc;
729 } else {
730 lli_write(prev, llp, desc->txd.phys | lms);
731 list_add_tail(&desc->desc_node, &first->tx_list);
732 }
733 prev = desc;
734
735 mem += dlen;
736 len -= dlen;
737 total_len += dlen;
738
739 if (len)
740 goto slave_sg_fromdev_fill_desc;
741 }
742 break;
743 default:
744 return NULL;
745 }
746
747 if (flags & DMA_PREP_INTERRUPT)
748 /* Trigger interrupt after last block */
749 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
750
751 prev->lli.llp = 0;
752 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
753 first->total_len = total_len;
754
755 return &first->txd;
756
757err_desc_get:
758 dev_err(chan2dev(chan),
759 "not enough descriptors available. Direction %d\n", direction);
760 dwc_desc_put(dwc, first);
761 return NULL;
762}
763
764bool dw_dma_filter(struct dma_chan *chan, void *param)
765{
766 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
767 struct dw_dma_slave *dws = param;
768
769 if (dws->dma_dev != chan->device->dev)
770 return false;
771
772 /* permit channels in accordance with the channels mask */
773 if (dws->channels && !(dws->channels & dwc->mask))
774 return false;
775
776 /* We have to copy data since dws can be temporary storage */
777 memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave));
778
779 return true;
780}
781EXPORT_SYMBOL_GPL(dw_dma_filter);
782
783static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
784{
785 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
786 struct dw_dma *dw = to_dw_dma(chan->device);
787
788 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
789
790 dwc->dma_sconfig.src_maxburst =
791 clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
792 dwc->dma_sconfig.dst_maxburst =
793 clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
794
795 dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst);
796 dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst);
797
798 return 0;
799}
800
801static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain)
802{
803 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
804 unsigned int count = 20; /* timeout iterations */
805
806 dw->suspend_chan(dwc, drain);
807
808 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
809 udelay(2);
810
811 set_bit(DW_DMA_IS_PAUSED, &dwc->flags);
812}
813
814static int dwc_pause(struct dma_chan *chan)
815{
816 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
817 unsigned long flags;
818
819 spin_lock_irqsave(&dwc->lock, flags);
820 dwc_chan_pause(dwc, false);
821 spin_unlock_irqrestore(&dwc->lock, flags);
822
823 return 0;
824}
825
826static inline void dwc_chan_resume(struct dw_dma_chan *dwc, bool drain)
827{
828 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
829
830 dw->resume_chan(dwc, drain);
831
832 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags);
833}
834
835static int dwc_resume(struct dma_chan *chan)
836{
837 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
838 unsigned long flags;
839
840 spin_lock_irqsave(&dwc->lock, flags);
841
842 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
843 dwc_chan_resume(dwc, false);
844
845 spin_unlock_irqrestore(&dwc->lock, flags);
846
847 return 0;
848}
849
850static int dwc_terminate_all(struct dma_chan *chan)
851{
852 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
853 struct dw_dma *dw = to_dw_dma(chan->device);
854 struct dw_desc *desc, *_desc;
855 unsigned long flags;
856 LIST_HEAD(list);
857
858 spin_lock_irqsave(&dwc->lock, flags);
859
860 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
861
862 dwc_chan_pause(dwc, true);
863
864 dwc_chan_disable(dw, dwc);
865
866 dwc_chan_resume(dwc, true);
867
868 /* active_list entries will end up before queued entries */
869 list_splice_init(&dwc->queue, &list);
870 list_splice_init(&dwc->active_list, &list);
871
872 spin_unlock_irqrestore(&dwc->lock, flags);
873
874 /* Flush all pending and queued descriptors */
875 list_for_each_entry_safe(desc, _desc, &list, desc_node)
876 dwc_descriptor_complete(dwc, desc, false);
877
878 return 0;
879}
880
881static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c)
882{
883 struct dw_desc *desc;
884
885 list_for_each_entry(desc, &dwc->active_list, desc_node)
886 if (desc->txd.cookie == c)
887 return desc;
888
889 return NULL;
890}
891
892static u32 dwc_get_residue_and_status(struct dw_dma_chan *dwc, dma_cookie_t cookie,
893 enum dma_status *status)
894{
895 struct dw_desc *desc;
896 unsigned long flags;
897 u32 residue;
898
899 spin_lock_irqsave(&dwc->lock, flags);
900
901 desc = dwc_find_desc(dwc, cookie);
902 if (desc) {
903 if (desc == dwc_first_active(dwc)) {
904 residue = desc->residue;
905 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
906 residue -= dwc_get_sent(dwc);
907 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
908 *status = DMA_PAUSED;
909 } else {
910 residue = desc->total_len;
911 }
912 } else {
913 residue = 0;
914 }
915
916 spin_unlock_irqrestore(&dwc->lock, flags);
917 return residue;
918}
919
920static enum dma_status
921dwc_tx_status(struct dma_chan *chan,
922 dma_cookie_t cookie,
923 struct dma_tx_state *txstate)
924{
925 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
926 enum dma_status ret;
927
928 ret = dma_cookie_status(chan, cookie, txstate);
929 if (ret == DMA_COMPLETE)
930 return ret;
931
932 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
933
934 ret = dma_cookie_status(chan, cookie, txstate);
935 if (ret == DMA_COMPLETE)
936 return ret;
937
938 dma_set_residue(txstate, dwc_get_residue_and_status(dwc, cookie, &ret));
939 return ret;
940}
941
942static void dwc_issue_pending(struct dma_chan *chan)
943{
944 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
945 unsigned long flags;
946
947 spin_lock_irqsave(&dwc->lock, flags);
948 if (list_empty(&dwc->active_list))
949 dwc_dostart_first_queued(dwc);
950 spin_unlock_irqrestore(&dwc->lock, flags);
951}
952
953/*----------------------------------------------------------------------*/
954
955void do_dw_dma_off(struct dw_dma *dw)
956{
957 dma_writel(dw, CFG, 0);
958
959 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
960 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
961 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
962 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
963 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
964
965 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
966 cpu_relax();
967}
968
969void do_dw_dma_on(struct dw_dma *dw)
970{
971 dma_writel(dw, CFG, DW_CFG_DMA_EN);
972}
973
974static int dwc_alloc_chan_resources(struct dma_chan *chan)
975{
976 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
977 struct dw_dma *dw = to_dw_dma(chan->device);
978
979 dev_vdbg(chan2dev(chan), "%s\n", __func__);
980
981 /* ASSERT: channel is idle */
982 if (dma_readl(dw, CH_EN) & dwc->mask) {
983 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
984 return -EIO;
985 }
986
987 dma_cookie_init(chan);
988
989 /*
990 * NOTE: some controllers may have additional features that we
991 * need to initialize here, like "scatter-gather" (which
992 * doesn't mean what you think it means), and status writeback.
993 */
994
995 /*
996 * We need controller-specific data to set up slave transfers.
997 */
998 if (chan->private && !dw_dma_filter(chan, chan->private)) {
999 dev_warn(chan2dev(chan), "Wrong controller-specific data\n");
1000 return -EINVAL;
1001 }
1002
1003 /* Enable controller here if needed */
1004 if (!dw->in_use)
1005 do_dw_dma_on(dw);
1006 dw->in_use |= dwc->mask;
1007
1008 return 0;
1009}
1010
1011static void dwc_free_chan_resources(struct dma_chan *chan)
1012{
1013 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1014 struct dw_dma *dw = to_dw_dma(chan->device);
1015 unsigned long flags;
1016
1017 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1018 dwc->descs_allocated);
1019
1020 /* ASSERT: channel is idle */
1021 BUG_ON(!list_empty(&dwc->active_list));
1022 BUG_ON(!list_empty(&dwc->queue));
1023 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1024
1025 spin_lock_irqsave(&dwc->lock, flags);
1026
1027 /* Clear custom channel configuration */
1028 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave));
1029
1030 /* Disable interrupts */
1031 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1032 channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1033 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1034
1035 spin_unlock_irqrestore(&dwc->lock, flags);
1036
1037 /* Disable controller in case it was a last user */
1038 dw->in_use &= ~dwc->mask;
1039 if (!dw->in_use)
1040 do_dw_dma_off(dw);
1041
1042 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1043}
1044
1045static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
1046{
1047 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1048
1049 caps->max_burst = dwc->max_burst;
1050
1051 /*
1052 * It might be crucial for some devices to have the hardware
1053 * accelerated multi-block transfers supported, aka LLPs in DW DMAC
1054 * notation. So if LLPs are supported then max_sg_burst is set to
1055 * zero which means unlimited number of SG entries can be handled in a
1056 * single DMA transaction, otherwise it's just one SG entry.
1057 */
1058 if (dwc->nollp)
1059 caps->max_sg_burst = 1;
1060 else
1061 caps->max_sg_burst = 0;
1062}
1063
1064int do_dma_probe(struct dw_dma_chip *chip)
1065{
1066 struct dw_dma *dw = chip->dw;
1067 struct dw_dma_platform_data *pdata;
1068 bool autocfg = false;
1069 unsigned int dw_params;
1070 unsigned int i;
1071 int err;
1072
1073 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
1074 if (!dw->pdata)
1075 return -ENOMEM;
1076
1077 dw->regs = chip->regs;
1078
1079 pm_runtime_get_sync(chip->dev);
1080
1081 if (!chip->pdata) {
1082 dw_params = dma_readl(dw, DW_PARAMS);
1083 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1084
1085 autocfg = dw_params >> DW_PARAMS_EN & 1;
1086 if (!autocfg) {
1087 err = -EINVAL;
1088 goto err_pdata;
1089 }
1090
1091 /* Reassign the platform data pointer */
1092 pdata = dw->pdata;
1093
1094 /* Get hardware configuration parameters */
1095 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1096 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1097 for (i = 0; i < pdata->nr_masters; i++) {
1098 pdata->data_width[i] =
1099 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3);
1100 }
1101 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
1102
1103 /* Fill platform data with the default values */
1104 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1105 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1106 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1107 err = -EINVAL;
1108 goto err_pdata;
1109 } else {
1110 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata));
1111
1112 /* Reassign the platform data pointer */
1113 pdata = dw->pdata;
1114 }
1115
1116 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1117 GFP_KERNEL);
1118 if (!dw->chan) {
1119 err = -ENOMEM;
1120 goto err_pdata;
1121 }
1122
1123 /* Calculate all channel mask before DMA setup */
1124 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1125
1126 /* Force dma off, just in case */
1127 dw->disable(dw);
1128
1129 /* Device and instance ID for IRQ and DMA pool */
1130 dw->set_device_name(dw, chip->id);
1131
1132 /* Create a pool of consistent memory blocks for hardware descriptors */
1133 dw->desc_pool = dmam_pool_create(dw->name, chip->dev,
1134 sizeof(struct dw_desc), 4, 0);
1135 if (!dw->desc_pool) {
1136 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1137 err = -ENOMEM;
1138 goto err_pdata;
1139 }
1140
1141 tasklet_setup(&dw->tasklet, dw_dma_tasklet);
1142
1143 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1144 dw->name, dw);
1145 if (err)
1146 goto err_pdata;
1147
1148 INIT_LIST_HEAD(&dw->dma.channels);
1149 for (i = 0; i < pdata->nr_channels; i++) {
1150 struct dw_dma_chan *dwc = &dw->chan[i];
1151
1152 dwc->chan.device = &dw->dma;
1153 dma_cookie_init(&dwc->chan);
1154 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1155 list_add_tail(&dwc->chan.device_node,
1156 &dw->dma.channels);
1157 else
1158 list_add(&dwc->chan.device_node, &dw->dma.channels);
1159
1160 /* 7 is highest priority & 0 is lowest. */
1161 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1162 dwc->priority = pdata->nr_channels - i - 1;
1163 else
1164 dwc->priority = i;
1165
1166 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1167 spin_lock_init(&dwc->lock);
1168 dwc->mask = 1 << i;
1169
1170 INIT_LIST_HEAD(&dwc->active_list);
1171 INIT_LIST_HEAD(&dwc->queue);
1172
1173 channel_clear_bit(dw, CH_EN, dwc->mask);
1174
1175 dwc->direction = DMA_TRANS_NONE;
1176
1177 /* Hardware configuration */
1178 if (autocfg) {
1179 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1180 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
1181 unsigned int dwc_params = readl(addr);
1182
1183 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1184 dwc_params);
1185
1186 /*
1187 * Decode maximum block size for given channel. The
1188 * stored 4 bit value represents blocks from 0x00 for 3
1189 * up to 0x0a for 4095.
1190 */
1191 dwc->block_size =
1192 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;
1193
1194 /*
1195 * According to the DW DMA databook the true scatter-
1196 * gether LLPs aren't available if either multi-block
1197 * config is disabled (CHx_MULTI_BLK_EN == 0) or the
1198 * LLP register is hard-coded to zeros
1199 * (CHx_HC_LLP == 1).
1200 */
1201 dwc->nollp =
1202 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0 ||
1203 (dwc_params >> DWC_PARAMS_HC_LLP & 0x1) == 1;
1204 dwc->max_burst =
1205 (0x4 << (dwc_params >> DWC_PARAMS_MSIZE & 0x7));
1206 } else {
1207 dwc->block_size = pdata->block_size;
1208 dwc->nollp = !pdata->multi_block[i];
1209 dwc->max_burst = pdata->max_burst[i] ?: DW_DMA_MAX_BURST;
1210 }
1211 }
1212
1213 /* Clear all interrupts on all channels. */
1214 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1215 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1216 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1217 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1218 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1219
1220 /* Set capabilities */
1221 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1222 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1223 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1224
1225 dw->dma.dev = chip->dev;
1226 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1227 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1228
1229 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1230 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1231
1232 dw->dma.device_caps = dwc_caps;
1233 dw->dma.device_config = dwc_config;
1234 dw->dma.device_pause = dwc_pause;
1235 dw->dma.device_resume = dwc_resume;
1236 dw->dma.device_terminate_all = dwc_terminate_all;
1237
1238 dw->dma.device_tx_status = dwc_tx_status;
1239 dw->dma.device_issue_pending = dwc_issue_pending;
1240
1241 /* DMA capabilities */
1242 dw->dma.min_burst = DW_DMA_MIN_BURST;
1243 dw->dma.max_burst = DW_DMA_MAX_BURST;
1244 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1245 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1246 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1247 BIT(DMA_MEM_TO_MEM);
1248 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1249
1250 /*
1251 * For now there is no hardware with non uniform maximum block size
1252 * across all of the device channels, so we set the maximum segment
1253 * size as the block size found for the very first channel.
1254 */
1255 dma_set_max_seg_size(dw->dma.dev, dw->chan[0].block_size);
1256
1257 err = dma_async_device_register(&dw->dma);
1258 if (err)
1259 goto err_dma_register;
1260
1261 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1262 pdata->nr_channels);
1263
1264 pm_runtime_put_sync_suspend(chip->dev);
1265
1266 return 0;
1267
1268err_dma_register:
1269 free_irq(chip->irq, dw);
1270err_pdata:
1271 pm_runtime_put_sync_suspend(chip->dev);
1272 return err;
1273}
1274
1275int do_dma_remove(struct dw_dma_chip *chip)
1276{
1277 struct dw_dma *dw = chip->dw;
1278 struct dw_dma_chan *dwc, *_dwc;
1279
1280 pm_runtime_get_sync(chip->dev);
1281
1282 do_dw_dma_off(dw);
1283 dma_async_device_unregister(&dw->dma);
1284
1285 free_irq(chip->irq, dw);
1286 tasklet_kill(&dw->tasklet);
1287
1288 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1289 chan.device_node) {
1290 list_del(&dwc->chan.device_node);
1291 channel_clear_bit(dw, CH_EN, dwc->mask);
1292 }
1293
1294 pm_runtime_put_sync_suspend(chip->dev);
1295 return 0;
1296}
1297
1298int do_dw_dma_disable(struct dw_dma_chip *chip)
1299{
1300 struct dw_dma *dw = chip->dw;
1301
1302 dw->disable(dw);
1303 return 0;
1304}
1305EXPORT_SYMBOL_GPL(do_dw_dma_disable);
1306
1307int do_dw_dma_enable(struct dw_dma_chip *chip)
1308{
1309 struct dw_dma *dw = chip->dw;
1310
1311 dw->enable(dw);
1312 return 0;
1313}
1314EXPORT_SYMBOL_GPL(do_dw_dma_enable);
1315
1316MODULE_LICENSE("GPL v2");
1317MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1318MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1319MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
1/*
2 * Core driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/bitops.h>
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
18#include <linux/dmapool.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/mm.h>
24#include <linux/module.h>
25#include <linux/slab.h>
26
27#include "../dmaengine.h"
28#include "internal.h"
29
30/*
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
35 *
36 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
38 */
39
40static inline bool is_request_line_unset(struct dw_dma_chan *dwc)
41{
42 return dwc->request_line == (typeof(dwc->request_line))~0;
43}
44
45static inline void dwc_set_masters(struct dw_dma_chan *dwc)
46{
47 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
48 struct dw_dma_slave *dws = dwc->chan.private;
49 unsigned char mmax = dw->nr_masters - 1;
50
51 if (!is_request_line_unset(dwc))
52 return;
53
54 dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws));
55 dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws));
56}
57
58#define DWC_DEFAULT_CTLLO(_chan) ({ \
59 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
60 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
61 bool _is_slave = is_slave_direction(_dwc->direction); \
62 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
63 DW_DMA_MSIZE_16; \
64 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
65 DW_DMA_MSIZE_16; \
66 \
67 (DWC_CTLL_DST_MSIZE(_dmsize) \
68 | DWC_CTLL_SRC_MSIZE(_smsize) \
69 | DWC_CTLL_LLP_D_EN \
70 | DWC_CTLL_LLP_S_EN \
71 | DWC_CTLL_DMS(_dwc->dst_master) \
72 | DWC_CTLL_SMS(_dwc->src_master)); \
73 })
74
75/*
76 * Number of descriptors to allocate for each channel. This should be
77 * made configurable somehow; preferably, the clients (at least the
78 * ones using slave transfers) should be able to give us a hint.
79 */
80#define NR_DESCS_PER_CHANNEL 64
81
82/*----------------------------------------------------------------------*/
83
84static struct device *chan2dev(struct dma_chan *chan)
85{
86 return &chan->dev->device;
87}
88
89static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
90{
91 return to_dw_desc(dwc->active_list.next);
92}
93
94static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
95{
96 struct dw_desc *desc, *_desc;
97 struct dw_desc *ret = NULL;
98 unsigned int i = 0;
99 unsigned long flags;
100
101 spin_lock_irqsave(&dwc->lock, flags);
102 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
103 i++;
104 if (async_tx_test_ack(&desc->txd)) {
105 list_del(&desc->desc_node);
106 ret = desc;
107 break;
108 }
109 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
110 }
111 spin_unlock_irqrestore(&dwc->lock, flags);
112
113 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
114
115 return ret;
116}
117
118/*
119 * Move a descriptor, including any children, to the free list.
120 * `desc' must not be on any lists.
121 */
122static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
123{
124 unsigned long flags;
125
126 if (desc) {
127 struct dw_desc *child;
128
129 spin_lock_irqsave(&dwc->lock, flags);
130 list_for_each_entry(child, &desc->tx_list, desc_node)
131 dev_vdbg(chan2dev(&dwc->chan),
132 "moving child desc %p to freelist\n",
133 child);
134 list_splice_init(&desc->tx_list, &dwc->free_list);
135 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
136 list_add(&desc->desc_node, &dwc->free_list);
137 spin_unlock_irqrestore(&dwc->lock, flags);
138 }
139}
140
141static void dwc_initialize(struct dw_dma_chan *dwc)
142{
143 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
144 struct dw_dma_slave *dws = dwc->chan.private;
145 u32 cfghi = DWC_CFGH_FIFO_MODE;
146 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
147
148 if (dwc->initialized == true)
149 return;
150
151 if (dws) {
152 /*
153 * We need controller-specific data to set up slave
154 * transfers.
155 */
156 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
157
158 cfghi = dws->cfg_hi;
159 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
160 } else {
161 if (dwc->direction == DMA_MEM_TO_DEV)
162 cfghi = DWC_CFGH_DST_PER(dwc->request_line);
163 else if (dwc->direction == DMA_DEV_TO_MEM)
164 cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
165 }
166
167 channel_writel(dwc, CFG_LO, cfglo);
168 channel_writel(dwc, CFG_HI, cfghi);
169
170 /* Enable interrupts */
171 channel_set_bit(dw, MASK.XFER, dwc->mask);
172 channel_set_bit(dw, MASK.ERROR, dwc->mask);
173
174 dwc->initialized = true;
175}
176
177/*----------------------------------------------------------------------*/
178
179static inline unsigned int dwc_fast_fls(unsigned long long v)
180{
181 /*
182 * We can be a lot more clever here, but this should take care
183 * of the most common optimization.
184 */
185 if (!(v & 7))
186 return 3;
187 else if (!(v & 3))
188 return 2;
189 else if (!(v & 1))
190 return 1;
191 return 0;
192}
193
194static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
195{
196 dev_err(chan2dev(&dwc->chan),
197 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
198 channel_readl(dwc, SAR),
199 channel_readl(dwc, DAR),
200 channel_readl(dwc, LLP),
201 channel_readl(dwc, CTL_HI),
202 channel_readl(dwc, CTL_LO));
203}
204
205static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
206{
207 channel_clear_bit(dw, CH_EN, dwc->mask);
208 while (dma_readl(dw, CH_EN) & dwc->mask)
209 cpu_relax();
210}
211
212/*----------------------------------------------------------------------*/
213
214/* Perform single block transfer */
215static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
216 struct dw_desc *desc)
217{
218 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
219 u32 ctllo;
220
221 /*
222 * Software emulation of LLP mode relies on interrupts to continue
223 * multi block transfer.
224 */
225 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
226
227 channel_writel(dwc, SAR, desc->lli.sar);
228 channel_writel(dwc, DAR, desc->lli.dar);
229 channel_writel(dwc, CTL_LO, ctllo);
230 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
231 channel_set_bit(dw, CH_EN, dwc->mask);
232
233 /* Move pointer to next descriptor */
234 dwc->tx_node_active = dwc->tx_node_active->next;
235}
236
237/* Called with dwc->lock held and bh disabled */
238static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
239{
240 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
241 unsigned long was_soft_llp;
242
243 /* ASSERT: channel is idle */
244 if (dma_readl(dw, CH_EN) & dwc->mask) {
245 dev_err(chan2dev(&dwc->chan),
246 "BUG: Attempted to start non-idle channel\n");
247 dwc_dump_chan_regs(dwc);
248
249 /* The tasklet will hopefully advance the queue... */
250 return;
251 }
252
253 if (dwc->nollp) {
254 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
255 &dwc->flags);
256 if (was_soft_llp) {
257 dev_err(chan2dev(&dwc->chan),
258 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
259 return;
260 }
261
262 dwc_initialize(dwc);
263
264 dwc->residue = first->total_len;
265 dwc->tx_node_active = &first->tx_list;
266
267 /* Submit first block */
268 dwc_do_single_block(dwc, first);
269
270 return;
271 }
272
273 dwc_initialize(dwc);
274
275 channel_writel(dwc, LLP, first->txd.phys);
276 channel_writel(dwc, CTL_LO,
277 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
278 channel_writel(dwc, CTL_HI, 0);
279 channel_set_bit(dw, CH_EN, dwc->mask);
280}
281
282/*----------------------------------------------------------------------*/
283
284static void
285dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
286 bool callback_required)
287{
288 dma_async_tx_callback callback = NULL;
289 void *param = NULL;
290 struct dma_async_tx_descriptor *txd = &desc->txd;
291 struct dw_desc *child;
292 unsigned long flags;
293
294 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
295
296 spin_lock_irqsave(&dwc->lock, flags);
297 dma_cookie_complete(txd);
298 if (callback_required) {
299 callback = txd->callback;
300 param = txd->callback_param;
301 }
302
303 /* async_tx_ack */
304 list_for_each_entry(child, &desc->tx_list, desc_node)
305 async_tx_ack(&child->txd);
306 async_tx_ack(&desc->txd);
307
308 list_splice_init(&desc->tx_list, &dwc->free_list);
309 list_move(&desc->desc_node, &dwc->free_list);
310
311 dma_descriptor_unmap(txd);
312 spin_unlock_irqrestore(&dwc->lock, flags);
313
314 if (callback)
315 callback(param);
316}
317
318static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
319{
320 struct dw_desc *desc, *_desc;
321 LIST_HEAD(list);
322 unsigned long flags;
323
324 spin_lock_irqsave(&dwc->lock, flags);
325 if (dma_readl(dw, CH_EN) & dwc->mask) {
326 dev_err(chan2dev(&dwc->chan),
327 "BUG: XFER bit set, but channel not idle!\n");
328
329 /* Try to continue after resetting the channel... */
330 dwc_chan_disable(dw, dwc);
331 }
332
333 /*
334 * Submit queued descriptors ASAP, i.e. before we go through
335 * the completed ones.
336 */
337 list_splice_init(&dwc->active_list, &list);
338 if (!list_empty(&dwc->queue)) {
339 list_move(dwc->queue.next, &dwc->active_list);
340 dwc_dostart(dwc, dwc_first_active(dwc));
341 }
342
343 spin_unlock_irqrestore(&dwc->lock, flags);
344
345 list_for_each_entry_safe(desc, _desc, &list, desc_node)
346 dwc_descriptor_complete(dwc, desc, true);
347}
348
349/* Returns how many bytes were already received from source */
350static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
351{
352 u32 ctlhi = channel_readl(dwc, CTL_HI);
353 u32 ctllo = channel_readl(dwc, CTL_LO);
354
355 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
356}
357
358static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
359{
360 dma_addr_t llp;
361 struct dw_desc *desc, *_desc;
362 struct dw_desc *child;
363 u32 status_xfer;
364 unsigned long flags;
365
366 spin_lock_irqsave(&dwc->lock, flags);
367 llp = channel_readl(dwc, LLP);
368 status_xfer = dma_readl(dw, RAW.XFER);
369
370 if (status_xfer & dwc->mask) {
371 /* Everything we've submitted is done */
372 dma_writel(dw, CLEAR.XFER, dwc->mask);
373
374 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
375 struct list_head *head, *active = dwc->tx_node_active;
376
377 /*
378 * We are inside first active descriptor.
379 * Otherwise something is really wrong.
380 */
381 desc = dwc_first_active(dwc);
382
383 head = &desc->tx_list;
384 if (active != head) {
385 /* Update desc to reflect last sent one */
386 if (active != head->next)
387 desc = to_dw_desc(active->prev);
388
389 dwc->residue -= desc->len;
390
391 child = to_dw_desc(active);
392
393 /* Submit next block */
394 dwc_do_single_block(dwc, child);
395
396 spin_unlock_irqrestore(&dwc->lock, flags);
397 return;
398 }
399
400 /* We are done here */
401 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
402 }
403
404 dwc->residue = 0;
405
406 spin_unlock_irqrestore(&dwc->lock, flags);
407
408 dwc_complete_all(dw, dwc);
409 return;
410 }
411
412 if (list_empty(&dwc->active_list)) {
413 dwc->residue = 0;
414 spin_unlock_irqrestore(&dwc->lock, flags);
415 return;
416 }
417
418 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
419 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
420 spin_unlock_irqrestore(&dwc->lock, flags);
421 return;
422 }
423
424 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
425
426 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
427 /* Initial residue value */
428 dwc->residue = desc->total_len;
429
430 /* Check first descriptors addr */
431 if (desc->txd.phys == llp) {
432 spin_unlock_irqrestore(&dwc->lock, flags);
433 return;
434 }
435
436 /* Check first descriptors llp */
437 if (desc->lli.llp == llp) {
438 /* This one is currently in progress */
439 dwc->residue -= dwc_get_sent(dwc);
440 spin_unlock_irqrestore(&dwc->lock, flags);
441 return;
442 }
443
444 dwc->residue -= desc->len;
445 list_for_each_entry(child, &desc->tx_list, desc_node) {
446 if (child->lli.llp == llp) {
447 /* Currently in progress */
448 dwc->residue -= dwc_get_sent(dwc);
449 spin_unlock_irqrestore(&dwc->lock, flags);
450 return;
451 }
452 dwc->residue -= child->len;
453 }
454
455 /*
456 * No descriptors so far seem to be in progress, i.e.
457 * this one must be done.
458 */
459 spin_unlock_irqrestore(&dwc->lock, flags);
460 dwc_descriptor_complete(dwc, desc, true);
461 spin_lock_irqsave(&dwc->lock, flags);
462 }
463
464 dev_err(chan2dev(&dwc->chan),
465 "BUG: All descriptors done, but channel not idle!\n");
466
467 /* Try to continue after resetting the channel... */
468 dwc_chan_disable(dw, dwc);
469
470 if (!list_empty(&dwc->queue)) {
471 list_move(dwc->queue.next, &dwc->active_list);
472 dwc_dostart(dwc, dwc_first_active(dwc));
473 }
474 spin_unlock_irqrestore(&dwc->lock, flags);
475}
476
477static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
478{
479 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
480 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
481}
482
483static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
484{
485 struct dw_desc *bad_desc;
486 struct dw_desc *child;
487 unsigned long flags;
488
489 dwc_scan_descriptors(dw, dwc);
490
491 spin_lock_irqsave(&dwc->lock, flags);
492
493 /*
494 * The descriptor currently at the head of the active list is
495 * borked. Since we don't have any way to report errors, we'll
496 * just have to scream loudly and try to carry on.
497 */
498 bad_desc = dwc_first_active(dwc);
499 list_del_init(&bad_desc->desc_node);
500 list_move(dwc->queue.next, dwc->active_list.prev);
501
502 /* Clear the error flag and try to restart the controller */
503 dma_writel(dw, CLEAR.ERROR, dwc->mask);
504 if (!list_empty(&dwc->active_list))
505 dwc_dostart(dwc, dwc_first_active(dwc));
506
507 /*
508 * WARN may seem harsh, but since this only happens
509 * when someone submits a bad physical address in a
510 * descriptor, we should consider ourselves lucky that the
511 * controller flagged an error instead of scribbling over
512 * random memory locations.
513 */
514 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
515 " cookie: %d\n", bad_desc->txd.cookie);
516 dwc_dump_lli(dwc, &bad_desc->lli);
517 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
518 dwc_dump_lli(dwc, &child->lli);
519
520 spin_unlock_irqrestore(&dwc->lock, flags);
521
522 /* Pretend the descriptor completed successfully */
523 dwc_descriptor_complete(dwc, bad_desc, true);
524}
525
526/* --------------------- Cyclic DMA API extensions -------------------- */
527
528dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
529{
530 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
531 return channel_readl(dwc, SAR);
532}
533EXPORT_SYMBOL(dw_dma_get_src_addr);
534
535dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
536{
537 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
538 return channel_readl(dwc, DAR);
539}
540EXPORT_SYMBOL(dw_dma_get_dst_addr);
541
542/* Called with dwc->lock held and all DMAC interrupts disabled */
543static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
544 u32 status_err, u32 status_xfer)
545{
546 unsigned long flags;
547
548 if (dwc->mask) {
549 void (*callback)(void *param);
550 void *callback_param;
551
552 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
553 channel_readl(dwc, LLP));
554
555 callback = dwc->cdesc->period_callback;
556 callback_param = dwc->cdesc->period_callback_param;
557
558 if (callback)
559 callback(callback_param);
560 }
561
562 /*
563 * Error and transfer complete are highly unlikely, and will most
564 * likely be due to a configuration error by the user.
565 */
566 if (unlikely(status_err & dwc->mask) ||
567 unlikely(status_xfer & dwc->mask)) {
568 int i;
569
570 dev_err(chan2dev(&dwc->chan),
571 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
572 status_xfer ? "xfer" : "error");
573
574 spin_lock_irqsave(&dwc->lock, flags);
575
576 dwc_dump_chan_regs(dwc);
577
578 dwc_chan_disable(dw, dwc);
579
580 /* Make sure DMA does not restart by loading a new list */
581 channel_writel(dwc, LLP, 0);
582 channel_writel(dwc, CTL_LO, 0);
583 channel_writel(dwc, CTL_HI, 0);
584
585 dma_writel(dw, CLEAR.ERROR, dwc->mask);
586 dma_writel(dw, CLEAR.XFER, dwc->mask);
587
588 for (i = 0; i < dwc->cdesc->periods; i++)
589 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
590
591 spin_unlock_irqrestore(&dwc->lock, flags);
592 }
593}
594
595/* ------------------------------------------------------------------------- */
596
597static void dw_dma_tasklet(unsigned long data)
598{
599 struct dw_dma *dw = (struct dw_dma *)data;
600 struct dw_dma_chan *dwc;
601 u32 status_xfer;
602 u32 status_err;
603 int i;
604
605 status_xfer = dma_readl(dw, RAW.XFER);
606 status_err = dma_readl(dw, RAW.ERROR);
607
608 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
609
610 for (i = 0; i < dw->dma.chancnt; i++) {
611 dwc = &dw->chan[i];
612 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
613 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
614 else if (status_err & (1 << i))
615 dwc_handle_error(dw, dwc);
616 else if (status_xfer & (1 << i))
617 dwc_scan_descriptors(dw, dwc);
618 }
619
620 /*
621 * Re-enable interrupts.
622 */
623 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
624 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
625}
626
627static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
628{
629 struct dw_dma *dw = dev_id;
630 u32 status = dma_readl(dw, STATUS_INT);
631
632 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
633
634 /* Check if we have any interrupt from the DMAC */
635 if (!status)
636 return IRQ_NONE;
637
638 /*
639 * Just disable the interrupts. We'll turn them back on in the
640 * softirq handler.
641 */
642 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
643 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
644
645 status = dma_readl(dw, STATUS_INT);
646 if (status) {
647 dev_err(dw->dma.dev,
648 "BUG: Unexpected interrupts pending: 0x%x\n",
649 status);
650
651 /* Try to recover */
652 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
653 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
654 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
655 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
656 }
657
658 tasklet_schedule(&dw->tasklet);
659
660 return IRQ_HANDLED;
661}
662
663/*----------------------------------------------------------------------*/
664
665static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
666{
667 struct dw_desc *desc = txd_to_dw_desc(tx);
668 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
669 dma_cookie_t cookie;
670 unsigned long flags;
671
672 spin_lock_irqsave(&dwc->lock, flags);
673 cookie = dma_cookie_assign(tx);
674
675 /*
676 * REVISIT: We should attempt to chain as many descriptors as
677 * possible, perhaps even appending to those already submitted
678 * for DMA. But this is hard to do in a race-free manner.
679 */
680 if (list_empty(&dwc->active_list)) {
681 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
682 desc->txd.cookie);
683 list_add_tail(&desc->desc_node, &dwc->active_list);
684 dwc_dostart(dwc, dwc_first_active(dwc));
685 } else {
686 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
687 desc->txd.cookie);
688
689 list_add_tail(&desc->desc_node, &dwc->queue);
690 }
691
692 spin_unlock_irqrestore(&dwc->lock, flags);
693
694 return cookie;
695}
696
697static struct dma_async_tx_descriptor *
698dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
699 size_t len, unsigned long flags)
700{
701 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
702 struct dw_dma *dw = to_dw_dma(chan->device);
703 struct dw_desc *desc;
704 struct dw_desc *first;
705 struct dw_desc *prev;
706 size_t xfer_count;
707 size_t offset;
708 unsigned int src_width;
709 unsigned int dst_width;
710 unsigned int data_width;
711 u32 ctllo;
712
713 dev_vdbg(chan2dev(chan),
714 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
715 &dest, &src, len, flags);
716
717 if (unlikely(!len)) {
718 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
719 return NULL;
720 }
721
722 dwc->direction = DMA_MEM_TO_MEM;
723
724 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
725 dw->data_width[dwc->dst_master]);
726
727 src_width = dst_width = min_t(unsigned int, data_width,
728 dwc_fast_fls(src | dest | len));
729
730 ctllo = DWC_DEFAULT_CTLLO(chan)
731 | DWC_CTLL_DST_WIDTH(dst_width)
732 | DWC_CTLL_SRC_WIDTH(src_width)
733 | DWC_CTLL_DST_INC
734 | DWC_CTLL_SRC_INC
735 | DWC_CTLL_FC_M2M;
736 prev = first = NULL;
737
738 for (offset = 0; offset < len; offset += xfer_count << src_width) {
739 xfer_count = min_t(size_t, (len - offset) >> src_width,
740 dwc->block_size);
741
742 desc = dwc_desc_get(dwc);
743 if (!desc)
744 goto err_desc_get;
745
746 desc->lli.sar = src + offset;
747 desc->lli.dar = dest + offset;
748 desc->lli.ctllo = ctllo;
749 desc->lli.ctlhi = xfer_count;
750 desc->len = xfer_count << src_width;
751
752 if (!first) {
753 first = desc;
754 } else {
755 prev->lli.llp = desc->txd.phys;
756 list_add_tail(&desc->desc_node,
757 &first->tx_list);
758 }
759 prev = desc;
760 }
761
762 if (flags & DMA_PREP_INTERRUPT)
763 /* Trigger interrupt after last block */
764 prev->lli.ctllo |= DWC_CTLL_INT_EN;
765
766 prev->lli.llp = 0;
767 first->txd.flags = flags;
768 first->total_len = len;
769
770 return &first->txd;
771
772err_desc_get:
773 dwc_desc_put(dwc, first);
774 return NULL;
775}
776
777static struct dma_async_tx_descriptor *
778dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
779 unsigned int sg_len, enum dma_transfer_direction direction,
780 unsigned long flags, void *context)
781{
782 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
783 struct dw_dma *dw = to_dw_dma(chan->device);
784 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
785 struct dw_desc *prev;
786 struct dw_desc *first;
787 u32 ctllo;
788 dma_addr_t reg;
789 unsigned int reg_width;
790 unsigned int mem_width;
791 unsigned int data_width;
792 unsigned int i;
793 struct scatterlist *sg;
794 size_t total_len = 0;
795
796 dev_vdbg(chan2dev(chan), "%s\n", __func__);
797
798 if (unlikely(!is_slave_direction(direction) || !sg_len))
799 return NULL;
800
801 dwc->direction = direction;
802
803 prev = first = NULL;
804
805 switch (direction) {
806 case DMA_MEM_TO_DEV:
807 reg_width = __fls(sconfig->dst_addr_width);
808 reg = sconfig->dst_addr;
809 ctllo = (DWC_DEFAULT_CTLLO(chan)
810 | DWC_CTLL_DST_WIDTH(reg_width)
811 | DWC_CTLL_DST_FIX
812 | DWC_CTLL_SRC_INC);
813
814 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
815 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
816
817 data_width = dw->data_width[dwc->src_master];
818
819 for_each_sg(sgl, sg, sg_len, i) {
820 struct dw_desc *desc;
821 u32 len, dlen, mem;
822
823 mem = sg_dma_address(sg);
824 len = sg_dma_len(sg);
825
826 mem_width = min_t(unsigned int,
827 data_width, dwc_fast_fls(mem | len));
828
829slave_sg_todev_fill_desc:
830 desc = dwc_desc_get(dwc);
831 if (!desc) {
832 dev_err(chan2dev(chan),
833 "not enough descriptors available\n");
834 goto err_desc_get;
835 }
836
837 desc->lli.sar = mem;
838 desc->lli.dar = reg;
839 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
840 if ((len >> mem_width) > dwc->block_size) {
841 dlen = dwc->block_size << mem_width;
842 mem += dlen;
843 len -= dlen;
844 } else {
845 dlen = len;
846 len = 0;
847 }
848
849 desc->lli.ctlhi = dlen >> mem_width;
850 desc->len = dlen;
851
852 if (!first) {
853 first = desc;
854 } else {
855 prev->lli.llp = desc->txd.phys;
856 list_add_tail(&desc->desc_node,
857 &first->tx_list);
858 }
859 prev = desc;
860 total_len += dlen;
861
862 if (len)
863 goto slave_sg_todev_fill_desc;
864 }
865 break;
866 case DMA_DEV_TO_MEM:
867 reg_width = __fls(sconfig->src_addr_width);
868 reg = sconfig->src_addr;
869 ctllo = (DWC_DEFAULT_CTLLO(chan)
870 | DWC_CTLL_SRC_WIDTH(reg_width)
871 | DWC_CTLL_DST_INC
872 | DWC_CTLL_SRC_FIX);
873
874 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
875 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
876
877 data_width = dw->data_width[dwc->dst_master];
878
879 for_each_sg(sgl, sg, sg_len, i) {
880 struct dw_desc *desc;
881 u32 len, dlen, mem;
882
883 mem = sg_dma_address(sg);
884 len = sg_dma_len(sg);
885
886 mem_width = min_t(unsigned int,
887 data_width, dwc_fast_fls(mem | len));
888
889slave_sg_fromdev_fill_desc:
890 desc = dwc_desc_get(dwc);
891 if (!desc) {
892 dev_err(chan2dev(chan),
893 "not enough descriptors available\n");
894 goto err_desc_get;
895 }
896
897 desc->lli.sar = reg;
898 desc->lli.dar = mem;
899 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
900 if ((len >> reg_width) > dwc->block_size) {
901 dlen = dwc->block_size << reg_width;
902 mem += dlen;
903 len -= dlen;
904 } else {
905 dlen = len;
906 len = 0;
907 }
908 desc->lli.ctlhi = dlen >> reg_width;
909 desc->len = dlen;
910
911 if (!first) {
912 first = desc;
913 } else {
914 prev->lli.llp = desc->txd.phys;
915 list_add_tail(&desc->desc_node,
916 &first->tx_list);
917 }
918 prev = desc;
919 total_len += dlen;
920
921 if (len)
922 goto slave_sg_fromdev_fill_desc;
923 }
924 break;
925 default:
926 return NULL;
927 }
928
929 if (flags & DMA_PREP_INTERRUPT)
930 /* Trigger interrupt after last block */
931 prev->lli.ctllo |= DWC_CTLL_INT_EN;
932
933 prev->lli.llp = 0;
934 first->total_len = total_len;
935
936 return &first->txd;
937
938err_desc_get:
939 dwc_desc_put(dwc, first);
940 return NULL;
941}
942
943/*
944 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
945 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
946 *
947 * NOTE: burst size 2 is not supported by controller.
948 *
949 * This can be done by finding least significant bit set: n & (n - 1)
950 */
951static inline void convert_burst(u32 *maxburst)
952{
953 if (*maxburst > 1)
954 *maxburst = fls(*maxburst) - 2;
955 else
956 *maxburst = 0;
957}
958
959static int
960set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
961{
962 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
963
964 /* Check if chan will be configured for slave transfers */
965 if (!is_slave_direction(sconfig->direction))
966 return -EINVAL;
967
968 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
969 dwc->direction = sconfig->direction;
970
971 /* Take the request line from slave_id member */
972 if (is_request_line_unset(dwc))
973 dwc->request_line = sconfig->slave_id;
974
975 convert_burst(&dwc->dma_sconfig.src_maxburst);
976 convert_burst(&dwc->dma_sconfig.dst_maxburst);
977
978 return 0;
979}
980
981static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
982{
983 u32 cfglo = channel_readl(dwc, CFG_LO);
984 unsigned int count = 20; /* timeout iterations */
985
986 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
987 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
988 udelay(2);
989
990 dwc->paused = true;
991}
992
993static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
994{
995 u32 cfglo = channel_readl(dwc, CFG_LO);
996
997 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
998
999 dwc->paused = false;
1000}
1001
1002static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1003 unsigned long arg)
1004{
1005 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1006 struct dw_dma *dw = to_dw_dma(chan->device);
1007 struct dw_desc *desc, *_desc;
1008 unsigned long flags;
1009 LIST_HEAD(list);
1010
1011 if (cmd == DMA_PAUSE) {
1012 spin_lock_irqsave(&dwc->lock, flags);
1013
1014 dwc_chan_pause(dwc);
1015
1016 spin_unlock_irqrestore(&dwc->lock, flags);
1017 } else if (cmd == DMA_RESUME) {
1018 if (!dwc->paused)
1019 return 0;
1020
1021 spin_lock_irqsave(&dwc->lock, flags);
1022
1023 dwc_chan_resume(dwc);
1024
1025 spin_unlock_irqrestore(&dwc->lock, flags);
1026 } else if (cmd == DMA_TERMINATE_ALL) {
1027 spin_lock_irqsave(&dwc->lock, flags);
1028
1029 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1030
1031 dwc_chan_disable(dw, dwc);
1032
1033 dwc_chan_resume(dwc);
1034
1035 /* active_list entries will end up before queued entries */
1036 list_splice_init(&dwc->queue, &list);
1037 list_splice_init(&dwc->active_list, &list);
1038
1039 spin_unlock_irqrestore(&dwc->lock, flags);
1040
1041 /* Flush all pending and queued descriptors */
1042 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1043 dwc_descriptor_complete(dwc, desc, false);
1044 } else if (cmd == DMA_SLAVE_CONFIG) {
1045 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1046 } else {
1047 return -ENXIO;
1048 }
1049
1050 return 0;
1051}
1052
1053static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1054{
1055 unsigned long flags;
1056 u32 residue;
1057
1058 spin_lock_irqsave(&dwc->lock, flags);
1059
1060 residue = dwc->residue;
1061 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1062 residue -= dwc_get_sent(dwc);
1063
1064 spin_unlock_irqrestore(&dwc->lock, flags);
1065 return residue;
1066}
1067
1068static enum dma_status
1069dwc_tx_status(struct dma_chan *chan,
1070 dma_cookie_t cookie,
1071 struct dma_tx_state *txstate)
1072{
1073 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1074 enum dma_status ret;
1075
1076 ret = dma_cookie_status(chan, cookie, txstate);
1077 if (ret == DMA_COMPLETE)
1078 return ret;
1079
1080 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1081
1082 ret = dma_cookie_status(chan, cookie, txstate);
1083 if (ret != DMA_COMPLETE)
1084 dma_set_residue(txstate, dwc_get_residue(dwc));
1085
1086 if (dwc->paused && ret == DMA_IN_PROGRESS)
1087 return DMA_PAUSED;
1088
1089 return ret;
1090}
1091
1092static void dwc_issue_pending(struct dma_chan *chan)
1093{
1094 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1095
1096 if (!list_empty(&dwc->queue))
1097 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1098}
1099
1100static int dwc_alloc_chan_resources(struct dma_chan *chan)
1101{
1102 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1103 struct dw_dma *dw = to_dw_dma(chan->device);
1104 struct dw_desc *desc;
1105 int i;
1106 unsigned long flags;
1107
1108 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1109
1110 /* ASSERT: channel is idle */
1111 if (dma_readl(dw, CH_EN) & dwc->mask) {
1112 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1113 return -EIO;
1114 }
1115
1116 dma_cookie_init(chan);
1117
1118 /*
1119 * NOTE: some controllers may have additional features that we
1120 * need to initialize here, like "scatter-gather" (which
1121 * doesn't mean what you think it means), and status writeback.
1122 */
1123
1124 dwc_set_masters(dwc);
1125
1126 spin_lock_irqsave(&dwc->lock, flags);
1127 i = dwc->descs_allocated;
1128 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1129 dma_addr_t phys;
1130
1131 spin_unlock_irqrestore(&dwc->lock, flags);
1132
1133 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1134 if (!desc)
1135 goto err_desc_alloc;
1136
1137 memset(desc, 0, sizeof(struct dw_desc));
1138
1139 INIT_LIST_HEAD(&desc->tx_list);
1140 dma_async_tx_descriptor_init(&desc->txd, chan);
1141 desc->txd.tx_submit = dwc_tx_submit;
1142 desc->txd.flags = DMA_CTRL_ACK;
1143 desc->txd.phys = phys;
1144
1145 dwc_desc_put(dwc, desc);
1146
1147 spin_lock_irqsave(&dwc->lock, flags);
1148 i = ++dwc->descs_allocated;
1149 }
1150
1151 spin_unlock_irqrestore(&dwc->lock, flags);
1152
1153 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1154
1155 return i;
1156
1157err_desc_alloc:
1158 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1159
1160 return i;
1161}
1162
1163static void dwc_free_chan_resources(struct dma_chan *chan)
1164{
1165 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1166 struct dw_dma *dw = to_dw_dma(chan->device);
1167 struct dw_desc *desc, *_desc;
1168 unsigned long flags;
1169 LIST_HEAD(list);
1170
1171 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1172 dwc->descs_allocated);
1173
1174 /* ASSERT: channel is idle */
1175 BUG_ON(!list_empty(&dwc->active_list));
1176 BUG_ON(!list_empty(&dwc->queue));
1177 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1178
1179 spin_lock_irqsave(&dwc->lock, flags);
1180 list_splice_init(&dwc->free_list, &list);
1181 dwc->descs_allocated = 0;
1182 dwc->initialized = false;
1183 dwc->request_line = ~0;
1184
1185 /* Disable interrupts */
1186 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1187 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1188
1189 spin_unlock_irqrestore(&dwc->lock, flags);
1190
1191 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1192 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1193 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1194 }
1195
1196 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1197}
1198
1199/* --------------------- Cyclic DMA API extensions -------------------- */
1200
1201/**
1202 * dw_dma_cyclic_start - start the cyclic DMA transfer
1203 * @chan: the DMA channel to start
1204 *
1205 * Must be called with soft interrupts disabled. Returns zero on success or
1206 * -errno on failure.
1207 */
1208int dw_dma_cyclic_start(struct dma_chan *chan)
1209{
1210 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1211 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1212 unsigned long flags;
1213
1214 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1215 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1216 return -ENODEV;
1217 }
1218
1219 spin_lock_irqsave(&dwc->lock, flags);
1220
1221 /* Assert channel is idle */
1222 if (dma_readl(dw, CH_EN) & dwc->mask) {
1223 dev_err(chan2dev(&dwc->chan),
1224 "BUG: Attempted to start non-idle channel\n");
1225 dwc_dump_chan_regs(dwc);
1226 spin_unlock_irqrestore(&dwc->lock, flags);
1227 return -EBUSY;
1228 }
1229
1230 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1231 dma_writel(dw, CLEAR.XFER, dwc->mask);
1232
1233 /* Setup DMAC channel registers */
1234 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1235 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1236 channel_writel(dwc, CTL_HI, 0);
1237
1238 channel_set_bit(dw, CH_EN, dwc->mask);
1239
1240 spin_unlock_irqrestore(&dwc->lock, flags);
1241
1242 return 0;
1243}
1244EXPORT_SYMBOL(dw_dma_cyclic_start);
1245
1246/**
1247 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1248 * @chan: the DMA channel to stop
1249 *
1250 * Must be called with soft interrupts disabled.
1251 */
1252void dw_dma_cyclic_stop(struct dma_chan *chan)
1253{
1254 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1255 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1256 unsigned long flags;
1257
1258 spin_lock_irqsave(&dwc->lock, flags);
1259
1260 dwc_chan_disable(dw, dwc);
1261
1262 spin_unlock_irqrestore(&dwc->lock, flags);
1263}
1264EXPORT_SYMBOL(dw_dma_cyclic_stop);
1265
1266/**
1267 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1268 * @chan: the DMA channel to prepare
1269 * @buf_addr: physical DMA address where the buffer starts
1270 * @buf_len: total number of bytes for the entire buffer
1271 * @period_len: number of bytes for each period
1272 * @direction: transfer direction, to or from device
1273 *
1274 * Must be called before trying to start the transfer. Returns a valid struct
1275 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1276 */
1277struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1278 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1279 enum dma_transfer_direction direction)
1280{
1281 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1282 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1283 struct dw_cyclic_desc *cdesc;
1284 struct dw_cyclic_desc *retval = NULL;
1285 struct dw_desc *desc;
1286 struct dw_desc *last = NULL;
1287 unsigned long was_cyclic;
1288 unsigned int reg_width;
1289 unsigned int periods;
1290 unsigned int i;
1291 unsigned long flags;
1292
1293 spin_lock_irqsave(&dwc->lock, flags);
1294 if (dwc->nollp) {
1295 spin_unlock_irqrestore(&dwc->lock, flags);
1296 dev_dbg(chan2dev(&dwc->chan),
1297 "channel doesn't support LLP transfers\n");
1298 return ERR_PTR(-EINVAL);
1299 }
1300
1301 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1302 spin_unlock_irqrestore(&dwc->lock, flags);
1303 dev_dbg(chan2dev(&dwc->chan),
1304 "queue and/or active list are not empty\n");
1305 return ERR_PTR(-EBUSY);
1306 }
1307
1308 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1309 spin_unlock_irqrestore(&dwc->lock, flags);
1310 if (was_cyclic) {
1311 dev_dbg(chan2dev(&dwc->chan),
1312 "channel already prepared for cyclic DMA\n");
1313 return ERR_PTR(-EBUSY);
1314 }
1315
1316 retval = ERR_PTR(-EINVAL);
1317
1318 if (unlikely(!is_slave_direction(direction)))
1319 goto out_err;
1320
1321 dwc->direction = direction;
1322
1323 if (direction == DMA_MEM_TO_DEV)
1324 reg_width = __ffs(sconfig->dst_addr_width);
1325 else
1326 reg_width = __ffs(sconfig->src_addr_width);
1327
1328 periods = buf_len / period_len;
1329
1330 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1331 if (period_len > (dwc->block_size << reg_width))
1332 goto out_err;
1333 if (unlikely(period_len & ((1 << reg_width) - 1)))
1334 goto out_err;
1335 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1336 goto out_err;
1337
1338 retval = ERR_PTR(-ENOMEM);
1339
1340 if (periods > NR_DESCS_PER_CHANNEL)
1341 goto out_err;
1342
1343 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1344 if (!cdesc)
1345 goto out_err;
1346
1347 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1348 if (!cdesc->desc)
1349 goto out_err_alloc;
1350
1351 for (i = 0; i < periods; i++) {
1352 desc = dwc_desc_get(dwc);
1353 if (!desc)
1354 goto out_err_desc_get;
1355
1356 switch (direction) {
1357 case DMA_MEM_TO_DEV:
1358 desc->lli.dar = sconfig->dst_addr;
1359 desc->lli.sar = buf_addr + (period_len * i);
1360 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1361 | DWC_CTLL_DST_WIDTH(reg_width)
1362 | DWC_CTLL_SRC_WIDTH(reg_width)
1363 | DWC_CTLL_DST_FIX
1364 | DWC_CTLL_SRC_INC
1365 | DWC_CTLL_INT_EN);
1366
1367 desc->lli.ctllo |= sconfig->device_fc ?
1368 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1369 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1370
1371 break;
1372 case DMA_DEV_TO_MEM:
1373 desc->lli.dar = buf_addr + (period_len * i);
1374 desc->lli.sar = sconfig->src_addr;
1375 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1376 | DWC_CTLL_SRC_WIDTH(reg_width)
1377 | DWC_CTLL_DST_WIDTH(reg_width)
1378 | DWC_CTLL_DST_INC
1379 | DWC_CTLL_SRC_FIX
1380 | DWC_CTLL_INT_EN);
1381
1382 desc->lli.ctllo |= sconfig->device_fc ?
1383 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1384 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1385
1386 break;
1387 default:
1388 break;
1389 }
1390
1391 desc->lli.ctlhi = (period_len >> reg_width);
1392 cdesc->desc[i] = desc;
1393
1394 if (last)
1395 last->lli.llp = desc->txd.phys;
1396
1397 last = desc;
1398 }
1399
1400 /* Let's make a cyclic list */
1401 last->lli.llp = cdesc->desc[0]->txd.phys;
1402
1403 dev_dbg(chan2dev(&dwc->chan),
1404 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1405 &buf_addr, buf_len, period_len, periods);
1406
1407 cdesc->periods = periods;
1408 dwc->cdesc = cdesc;
1409
1410 return cdesc;
1411
1412out_err_desc_get:
1413 while (i--)
1414 dwc_desc_put(dwc, cdesc->desc[i]);
1415out_err_alloc:
1416 kfree(cdesc);
1417out_err:
1418 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1419 return (struct dw_cyclic_desc *)retval;
1420}
1421EXPORT_SYMBOL(dw_dma_cyclic_prep);
1422
1423/**
1424 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1425 * @chan: the DMA channel to free
1426 */
1427void dw_dma_cyclic_free(struct dma_chan *chan)
1428{
1429 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1430 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1431 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1432 int i;
1433 unsigned long flags;
1434
1435 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1436
1437 if (!cdesc)
1438 return;
1439
1440 spin_lock_irqsave(&dwc->lock, flags);
1441
1442 dwc_chan_disable(dw, dwc);
1443
1444 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1445 dma_writel(dw, CLEAR.XFER, dwc->mask);
1446
1447 spin_unlock_irqrestore(&dwc->lock, flags);
1448
1449 for (i = 0; i < cdesc->periods; i++)
1450 dwc_desc_put(dwc, cdesc->desc[i]);
1451
1452 kfree(cdesc->desc);
1453 kfree(cdesc);
1454
1455 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1456}
1457EXPORT_SYMBOL(dw_dma_cyclic_free);
1458
1459/*----------------------------------------------------------------------*/
1460
1461static void dw_dma_off(struct dw_dma *dw)
1462{
1463 int i;
1464
1465 dma_writel(dw, CFG, 0);
1466
1467 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1468 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1469 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1470 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1471
1472 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1473 cpu_relax();
1474
1475 for (i = 0; i < dw->dma.chancnt; i++)
1476 dw->chan[i].initialized = false;
1477}
1478
1479int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1480{
1481 struct dw_dma *dw;
1482 bool autocfg;
1483 unsigned int dw_params;
1484 unsigned int nr_channels;
1485 unsigned int max_blk_size = 0;
1486 int err;
1487 int i;
1488
1489 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1490 if (!dw)
1491 return -ENOMEM;
1492
1493 dw->regs = chip->regs;
1494 chip->dw = dw;
1495
1496 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1497 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1498
1499 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1500
1501 if (!pdata && autocfg) {
1502 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1503 if (!pdata)
1504 return -ENOMEM;
1505
1506 /* Fill platform data with the default values */
1507 pdata->is_private = true;
1508 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1509 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1510 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1511 return -EINVAL;
1512
1513 if (autocfg)
1514 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1515 else
1516 nr_channels = pdata->nr_channels;
1517
1518 dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
1519 GFP_KERNEL);
1520 if (!dw->chan)
1521 return -ENOMEM;
1522
1523 dw->clk = devm_clk_get(chip->dev, "hclk");
1524 if (IS_ERR(dw->clk))
1525 return PTR_ERR(dw->clk);
1526 clk_prepare_enable(dw->clk);
1527
1528 /* Get hardware configuration parameters */
1529 if (autocfg) {
1530 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1531
1532 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1533 for (i = 0; i < dw->nr_masters; i++) {
1534 dw->data_width[i] =
1535 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1536 }
1537 } else {
1538 dw->nr_masters = pdata->nr_masters;
1539 memcpy(dw->data_width, pdata->data_width, 4);
1540 }
1541
1542 /* Calculate all channel mask before DMA setup */
1543 dw->all_chan_mask = (1 << nr_channels) - 1;
1544
1545 /* Force dma off, just in case */
1546 dw_dma_off(dw);
1547
1548 /* Disable BLOCK interrupts as well */
1549 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1550
1551 /* Create a pool of consistent memory blocks for hardware descriptors */
1552 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1553 sizeof(struct dw_desc), 4, 0);
1554 if (!dw->desc_pool) {
1555 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1556 return -ENOMEM;
1557 }
1558
1559 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1560
1561 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1562 "dw_dmac", dw);
1563 if (err)
1564 return err;
1565
1566 INIT_LIST_HEAD(&dw->dma.channels);
1567 for (i = 0; i < nr_channels; i++) {
1568 struct dw_dma_chan *dwc = &dw->chan[i];
1569 int r = nr_channels - i - 1;
1570
1571 dwc->chan.device = &dw->dma;
1572 dma_cookie_init(&dwc->chan);
1573 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1574 list_add_tail(&dwc->chan.device_node,
1575 &dw->dma.channels);
1576 else
1577 list_add(&dwc->chan.device_node, &dw->dma.channels);
1578
1579 /* 7 is highest priority & 0 is lowest. */
1580 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1581 dwc->priority = r;
1582 else
1583 dwc->priority = i;
1584
1585 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1586 spin_lock_init(&dwc->lock);
1587 dwc->mask = 1 << i;
1588
1589 INIT_LIST_HEAD(&dwc->active_list);
1590 INIT_LIST_HEAD(&dwc->queue);
1591 INIT_LIST_HEAD(&dwc->free_list);
1592
1593 channel_clear_bit(dw, CH_EN, dwc->mask);
1594
1595 dwc->direction = DMA_TRANS_NONE;
1596 dwc->request_line = ~0;
1597
1598 /* Hardware configuration */
1599 if (autocfg) {
1600 unsigned int dwc_params;
1601 void __iomem *addr = chip->regs + r * sizeof(u32);
1602
1603 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1604
1605 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1606 dwc_params);
1607
1608 /*
1609 * Decode maximum block size for given channel. The
1610 * stored 4 bit value represents blocks from 0x00 for 3
1611 * up to 0x0a for 4095.
1612 */
1613 dwc->block_size =
1614 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1615 dwc->nollp =
1616 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1617 } else {
1618 dwc->block_size = pdata->block_size;
1619
1620 /* Check if channel supports multi block transfer */
1621 channel_writel(dwc, LLP, 0xfffffffc);
1622 dwc->nollp =
1623 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1624 channel_writel(dwc, LLP, 0);
1625 }
1626 }
1627
1628 /* Clear all interrupts on all channels. */
1629 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1630 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1631 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1632 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1633 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1634
1635 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1636 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1637 if (pdata->is_private)
1638 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1639 dw->dma.dev = chip->dev;
1640 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1641 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1642
1643 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1644
1645 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1646 dw->dma.device_control = dwc_control;
1647
1648 dw->dma.device_tx_status = dwc_tx_status;
1649 dw->dma.device_issue_pending = dwc_issue_pending;
1650
1651 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1652
1653 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1654 nr_channels);
1655
1656 dma_async_device_register(&dw->dma);
1657
1658 return 0;
1659}
1660EXPORT_SYMBOL_GPL(dw_dma_probe);
1661
1662int dw_dma_remove(struct dw_dma_chip *chip)
1663{
1664 struct dw_dma *dw = chip->dw;
1665 struct dw_dma_chan *dwc, *_dwc;
1666
1667 dw_dma_off(dw);
1668 dma_async_device_unregister(&dw->dma);
1669
1670 free_irq(chip->irq, dw);
1671 tasklet_kill(&dw->tasklet);
1672
1673 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1674 chan.device_node) {
1675 list_del(&dwc->chan.device_node);
1676 channel_clear_bit(dw, CH_EN, dwc->mask);
1677 }
1678
1679 return 0;
1680}
1681EXPORT_SYMBOL_GPL(dw_dma_remove);
1682
1683void dw_dma_shutdown(struct dw_dma_chip *chip)
1684{
1685 struct dw_dma *dw = chip->dw;
1686
1687 dw_dma_off(dw);
1688 clk_disable_unprepare(dw->clk);
1689}
1690EXPORT_SYMBOL_GPL(dw_dma_shutdown);
1691
1692#ifdef CONFIG_PM_SLEEP
1693
1694int dw_dma_suspend(struct dw_dma_chip *chip)
1695{
1696 struct dw_dma *dw = chip->dw;
1697
1698 dw_dma_off(dw);
1699 clk_disable_unprepare(dw->clk);
1700
1701 return 0;
1702}
1703EXPORT_SYMBOL_GPL(dw_dma_suspend);
1704
1705int dw_dma_resume(struct dw_dma_chip *chip)
1706{
1707 struct dw_dma *dw = chip->dw;
1708
1709 clk_prepare_enable(dw->clk);
1710 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1711
1712 return 0;
1713}
1714EXPORT_SYMBOL_GPL(dw_dma_resume);
1715
1716#endif /* CONFIG_PM_SLEEP */
1717
1718MODULE_LICENSE("GPL v2");
1719MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1720MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1721MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");