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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Core driver for the Synopsys DesignWare DMA Controller
4 *
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
7 * Copyright (C) 2013 Intel Corporation
8 */
9
10#include <linux/bitops.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/mm.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/pm_runtime.h>
23
24#include "../dmaengine.h"
25#include "internal.h"
26
27/*
28 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
29 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
30 * of which use ARM any more). See the "Databook" from Synopsys for
31 * information beyond what licensees probably provide.
32 */
33
34/* The set of bus widths supported by the DMA controller */
35#define DW_DMA_BUSWIDTHS \
36 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
37 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
38 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
39 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
40
41/*----------------------------------------------------------------------*/
42
43static struct device *chan2dev(struct dma_chan *chan)
44{
45 return &chan->dev->device;
46}
47
48static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
49{
50 return to_dw_desc(dwc->active_list.next);
51}
52
53static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
54{
55 struct dw_desc *desc = txd_to_dw_desc(tx);
56 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
57 dma_cookie_t cookie;
58 unsigned long flags;
59
60 spin_lock_irqsave(&dwc->lock, flags);
61 cookie = dma_cookie_assign(tx);
62
63 /*
64 * REVISIT: We should attempt to chain as many descriptors as
65 * possible, perhaps even appending to those already submitted
66 * for DMA. But this is hard to do in a race-free manner.
67 */
68
69 list_add_tail(&desc->desc_node, &dwc->queue);
70 spin_unlock_irqrestore(&dwc->lock, flags);
71 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n",
72 __func__, desc->txd.cookie);
73
74 return cookie;
75}
76
77static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
78{
79 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
80 struct dw_desc *desc;
81 dma_addr_t phys;
82
83 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys);
84 if (!desc)
85 return NULL;
86
87 dwc->descs_allocated++;
88 INIT_LIST_HEAD(&desc->tx_list);
89 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan);
90 desc->txd.tx_submit = dwc_tx_submit;
91 desc->txd.flags = DMA_CTRL_ACK;
92 desc->txd.phys = phys;
93 return desc;
94}
95
96static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
97{
98 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
99 struct dw_desc *child, *_next;
100
101 if (unlikely(!desc))
102 return;
103
104 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) {
105 list_del(&child->desc_node);
106 dma_pool_free(dw->desc_pool, child, child->txd.phys);
107 dwc->descs_allocated--;
108 }
109
110 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
111 dwc->descs_allocated--;
112}
113
114static void dwc_initialize(struct dw_dma_chan *dwc)
115{
116 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
117
118 dw->initialize_chan(dwc);
119
120 /* Enable interrupts */
121 channel_set_bit(dw, MASK.XFER, dwc->mask);
122 channel_set_bit(dw, MASK.ERROR, dwc->mask);
123}
124
125/*----------------------------------------------------------------------*/
126
127static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
128{
129 dev_err(chan2dev(&dwc->chan),
130 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
131 channel_readl(dwc, SAR),
132 channel_readl(dwc, DAR),
133 channel_readl(dwc, LLP),
134 channel_readl(dwc, CTL_HI),
135 channel_readl(dwc, CTL_LO));
136}
137
138static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
139{
140 channel_clear_bit(dw, CH_EN, dwc->mask);
141 while (dma_readl(dw, CH_EN) & dwc->mask)
142 cpu_relax();
143}
144
145/*----------------------------------------------------------------------*/
146
147/* Perform single block transfer */
148static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
149 struct dw_desc *desc)
150{
151 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
152 u32 ctllo;
153
154 /*
155 * Software emulation of LLP mode relies on interrupts to continue
156 * multi block transfer.
157 */
158 ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN;
159
160 channel_writel(dwc, SAR, lli_read(desc, sar));
161 channel_writel(dwc, DAR, lli_read(desc, dar));
162 channel_writel(dwc, CTL_LO, ctllo);
163 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi));
164 channel_set_bit(dw, CH_EN, dwc->mask);
165
166 /* Move pointer to next descriptor */
167 dwc->tx_node_active = dwc->tx_node_active->next;
168}
169
170/* Called with dwc->lock held and bh disabled */
171static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
172{
173 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
174 u8 lms = DWC_LLP_LMS(dwc->dws.m_master);
175 unsigned long was_soft_llp;
176
177 /* ASSERT: channel is idle */
178 if (dma_readl(dw, CH_EN) & dwc->mask) {
179 dev_err(chan2dev(&dwc->chan),
180 "%s: BUG: Attempted to start non-idle channel\n",
181 __func__);
182 dwc_dump_chan_regs(dwc);
183
184 /* The tasklet will hopefully advance the queue... */
185 return;
186 }
187
188 if (dwc->nollp) {
189 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
190 &dwc->flags);
191 if (was_soft_llp) {
192 dev_err(chan2dev(&dwc->chan),
193 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
194 return;
195 }
196
197 dwc_initialize(dwc);
198
199 first->residue = first->total_len;
200 dwc->tx_node_active = &first->tx_list;
201
202 /* Submit first block */
203 dwc_do_single_block(dwc, first);
204
205 return;
206 }
207
208 dwc_initialize(dwc);
209
210 channel_writel(dwc, LLP, first->txd.phys | lms);
211 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
212 channel_writel(dwc, CTL_HI, 0);
213 channel_set_bit(dw, CH_EN, dwc->mask);
214}
215
216static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
217{
218 struct dw_desc *desc;
219
220 if (list_empty(&dwc->queue))
221 return;
222
223 list_move(dwc->queue.next, &dwc->active_list);
224 desc = dwc_first_active(dwc);
225 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
226 dwc_dostart(dwc, desc);
227}
228
229/*----------------------------------------------------------------------*/
230
231static void
232dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
233 bool callback_required)
234{
235 struct dma_async_tx_descriptor *txd = &desc->txd;
236 struct dw_desc *child;
237 unsigned long flags;
238 struct dmaengine_desc_callback cb;
239
240 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
241
242 spin_lock_irqsave(&dwc->lock, flags);
243 dma_cookie_complete(txd);
244 if (callback_required)
245 dmaengine_desc_get_callback(txd, &cb);
246 else
247 memset(&cb, 0, sizeof(cb));
248
249 /* async_tx_ack */
250 list_for_each_entry(child, &desc->tx_list, desc_node)
251 async_tx_ack(&child->txd);
252 async_tx_ack(&desc->txd);
253 dwc_desc_put(dwc, desc);
254 spin_unlock_irqrestore(&dwc->lock, flags);
255
256 dmaengine_desc_callback_invoke(&cb, NULL);
257}
258
259static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
260{
261 struct dw_desc *desc, *_desc;
262 LIST_HEAD(list);
263 unsigned long flags;
264
265 spin_lock_irqsave(&dwc->lock, flags);
266 if (dma_readl(dw, CH_EN) & dwc->mask) {
267 dev_err(chan2dev(&dwc->chan),
268 "BUG: XFER bit set, but channel not idle!\n");
269
270 /* Try to continue after resetting the channel... */
271 dwc_chan_disable(dw, dwc);
272 }
273
274 /*
275 * Submit queued descriptors ASAP, i.e. before we go through
276 * the completed ones.
277 */
278 list_splice_init(&dwc->active_list, &list);
279 dwc_dostart_first_queued(dwc);
280
281 spin_unlock_irqrestore(&dwc->lock, flags);
282
283 list_for_each_entry_safe(desc, _desc, &list, desc_node)
284 dwc_descriptor_complete(dwc, desc, true);
285}
286
287/* Returns how many bytes were already received from source */
288static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
289{
290 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
291 u32 ctlhi = channel_readl(dwc, CTL_HI);
292 u32 ctllo = channel_readl(dwc, CTL_LO);
293
294 return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7);
295}
296
297static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
298{
299 dma_addr_t llp;
300 struct dw_desc *desc, *_desc;
301 struct dw_desc *child;
302 u32 status_xfer;
303 unsigned long flags;
304
305 spin_lock_irqsave(&dwc->lock, flags);
306 llp = channel_readl(dwc, LLP);
307 status_xfer = dma_readl(dw, RAW.XFER);
308
309 if (status_xfer & dwc->mask) {
310 /* Everything we've submitted is done */
311 dma_writel(dw, CLEAR.XFER, dwc->mask);
312
313 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
314 struct list_head *head, *active = dwc->tx_node_active;
315
316 /*
317 * We are inside first active descriptor.
318 * Otherwise something is really wrong.
319 */
320 desc = dwc_first_active(dwc);
321
322 head = &desc->tx_list;
323 if (active != head) {
324 /* Update residue to reflect last sent descriptor */
325 if (active == head->next)
326 desc->residue -= desc->len;
327 else
328 desc->residue -= to_dw_desc(active->prev)->len;
329
330 child = to_dw_desc(active);
331
332 /* Submit next block */
333 dwc_do_single_block(dwc, child);
334
335 spin_unlock_irqrestore(&dwc->lock, flags);
336 return;
337 }
338
339 /* We are done here */
340 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
341 }
342
343 spin_unlock_irqrestore(&dwc->lock, flags);
344
345 dwc_complete_all(dw, dwc);
346 return;
347 }
348
349 if (list_empty(&dwc->active_list)) {
350 spin_unlock_irqrestore(&dwc->lock, flags);
351 return;
352 }
353
354 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
355 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
356 spin_unlock_irqrestore(&dwc->lock, flags);
357 return;
358 }
359
360 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
361
362 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
363 /* Initial residue value */
364 desc->residue = desc->total_len;
365
366 /* Check first descriptors addr */
367 if (desc->txd.phys == DWC_LLP_LOC(llp)) {
368 spin_unlock_irqrestore(&dwc->lock, flags);
369 return;
370 }
371
372 /* Check first descriptors llp */
373 if (lli_read(desc, llp) == llp) {
374 /* This one is currently in progress */
375 desc->residue -= dwc_get_sent(dwc);
376 spin_unlock_irqrestore(&dwc->lock, flags);
377 return;
378 }
379
380 desc->residue -= desc->len;
381 list_for_each_entry(child, &desc->tx_list, desc_node) {
382 if (lli_read(child, llp) == llp) {
383 /* Currently in progress */
384 desc->residue -= dwc_get_sent(dwc);
385 spin_unlock_irqrestore(&dwc->lock, flags);
386 return;
387 }
388 desc->residue -= child->len;
389 }
390
391 /*
392 * No descriptors so far seem to be in progress, i.e.
393 * this one must be done.
394 */
395 spin_unlock_irqrestore(&dwc->lock, flags);
396 dwc_descriptor_complete(dwc, desc, true);
397 spin_lock_irqsave(&dwc->lock, flags);
398 }
399
400 dev_err(chan2dev(&dwc->chan),
401 "BUG: All descriptors done, but channel not idle!\n");
402
403 /* Try to continue after resetting the channel... */
404 dwc_chan_disable(dw, dwc);
405
406 dwc_dostart_first_queued(dwc);
407 spin_unlock_irqrestore(&dwc->lock, flags);
408}
409
410static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc)
411{
412 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
413 lli_read(desc, sar),
414 lli_read(desc, dar),
415 lli_read(desc, llp),
416 lli_read(desc, ctlhi),
417 lli_read(desc, ctllo));
418}
419
420static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
421{
422 struct dw_desc *bad_desc;
423 struct dw_desc *child;
424 unsigned long flags;
425
426 dwc_scan_descriptors(dw, dwc);
427
428 spin_lock_irqsave(&dwc->lock, flags);
429
430 /*
431 * The descriptor currently at the head of the active list is
432 * borked. Since we don't have any way to report errors, we'll
433 * just have to scream loudly and try to carry on.
434 */
435 bad_desc = dwc_first_active(dwc);
436 list_del_init(&bad_desc->desc_node);
437 list_move(dwc->queue.next, dwc->active_list.prev);
438
439 /* Clear the error flag and try to restart the controller */
440 dma_writel(dw, CLEAR.ERROR, dwc->mask);
441 if (!list_empty(&dwc->active_list))
442 dwc_dostart(dwc, dwc_first_active(dwc));
443
444 /*
445 * WARN may seem harsh, but since this only happens
446 * when someone submits a bad physical address in a
447 * descriptor, we should consider ourselves lucky that the
448 * controller flagged an error instead of scribbling over
449 * random memory locations.
450 */
451 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
452 " cookie: %d\n", bad_desc->txd.cookie);
453 dwc_dump_lli(dwc, bad_desc);
454 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
455 dwc_dump_lli(dwc, child);
456
457 spin_unlock_irqrestore(&dwc->lock, flags);
458
459 /* Pretend the descriptor completed successfully */
460 dwc_descriptor_complete(dwc, bad_desc, true);
461}
462
463static void dw_dma_tasklet(struct tasklet_struct *t)
464{
465 struct dw_dma *dw = from_tasklet(dw, t, tasklet);
466 struct dw_dma_chan *dwc;
467 u32 status_xfer;
468 u32 status_err;
469 unsigned int i;
470
471 status_xfer = dma_readl(dw, RAW.XFER);
472 status_err = dma_readl(dw, RAW.ERROR);
473
474 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
475
476 for (i = 0; i < dw->dma.chancnt; i++) {
477 dwc = &dw->chan[i];
478 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
479 dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n");
480 else if (status_err & (1 << i))
481 dwc_handle_error(dw, dwc);
482 else if (status_xfer & (1 << i))
483 dwc_scan_descriptors(dw, dwc);
484 }
485
486 /* Re-enable interrupts */
487 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
488 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
489}
490
491static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
492{
493 struct dw_dma *dw = dev_id;
494 u32 status;
495
496 /* Check if we have any interrupt from the DMAC which is not in use */
497 if (!dw->in_use)
498 return IRQ_NONE;
499
500 status = dma_readl(dw, STATUS_INT);
501 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
502
503 /* Check if we have any interrupt from the DMAC */
504 if (!status)
505 return IRQ_NONE;
506
507 /*
508 * Just disable the interrupts. We'll turn them back on in the
509 * softirq handler.
510 */
511 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
512 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
513 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
514
515 status = dma_readl(dw, STATUS_INT);
516 if (status) {
517 dev_err(dw->dma.dev,
518 "BUG: Unexpected interrupts pending: 0x%x\n",
519 status);
520
521 /* Try to recover */
522 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
523 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
524 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
525 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
526 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
527 }
528
529 tasklet_schedule(&dw->tasklet);
530
531 return IRQ_HANDLED;
532}
533
534/*----------------------------------------------------------------------*/
535
536static struct dma_async_tx_descriptor *
537dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
538 size_t len, unsigned long flags)
539{
540 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
541 struct dw_dma *dw = to_dw_dma(chan->device);
542 struct dw_desc *desc;
543 struct dw_desc *first;
544 struct dw_desc *prev;
545 size_t xfer_count;
546 size_t offset;
547 u8 m_master = dwc->dws.m_master;
548 unsigned int src_width;
549 unsigned int dst_width;
550 unsigned int data_width = dw->pdata->data_width[m_master];
551 u32 ctllo, ctlhi;
552 u8 lms = DWC_LLP_LMS(m_master);
553
554 dev_vdbg(chan2dev(chan),
555 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
556 &dest, &src, len, flags);
557
558 if (unlikely(!len)) {
559 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
560 return NULL;
561 }
562
563 dwc->direction = DMA_MEM_TO_MEM;
564
565 src_width = dst_width = __ffs(data_width | src | dest | len);
566
567 ctllo = dw->prepare_ctllo(dwc)
568 | DWC_CTLL_DST_WIDTH(dst_width)
569 | DWC_CTLL_SRC_WIDTH(src_width)
570 | DWC_CTLL_DST_INC
571 | DWC_CTLL_SRC_INC
572 | DWC_CTLL_FC_M2M;
573 prev = first = NULL;
574
575 for (offset = 0; offset < len; offset += xfer_count) {
576 desc = dwc_desc_get(dwc);
577 if (!desc)
578 goto err_desc_get;
579
580 ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count);
581
582 lli_write(desc, sar, src + offset);
583 lli_write(desc, dar, dest + offset);
584 lli_write(desc, ctllo, ctllo);
585 lli_write(desc, ctlhi, ctlhi);
586 desc->len = xfer_count;
587
588 if (!first) {
589 first = desc;
590 } else {
591 lli_write(prev, llp, desc->txd.phys | lms);
592 list_add_tail(&desc->desc_node, &first->tx_list);
593 }
594 prev = desc;
595 }
596
597 if (flags & DMA_PREP_INTERRUPT)
598 /* Trigger interrupt after last block */
599 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
600
601 prev->lli.llp = 0;
602 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
603 first->txd.flags = flags;
604 first->total_len = len;
605
606 return &first->txd;
607
608err_desc_get:
609 dwc_desc_put(dwc, first);
610 return NULL;
611}
612
613static struct dma_async_tx_descriptor *
614dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
615 unsigned int sg_len, enum dma_transfer_direction direction,
616 unsigned long flags, void *context)
617{
618 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
619 struct dw_dma *dw = to_dw_dma(chan->device);
620 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
621 struct dw_desc *prev;
622 struct dw_desc *first;
623 u32 ctllo, ctlhi;
624 u8 m_master = dwc->dws.m_master;
625 u8 lms = DWC_LLP_LMS(m_master);
626 dma_addr_t reg;
627 unsigned int reg_width;
628 unsigned int mem_width;
629 unsigned int data_width = dw->pdata->data_width[m_master];
630 unsigned int i;
631 struct scatterlist *sg;
632 size_t total_len = 0;
633
634 dev_vdbg(chan2dev(chan), "%s\n", __func__);
635
636 if (unlikely(!is_slave_direction(direction) || !sg_len))
637 return NULL;
638
639 dwc->direction = direction;
640
641 prev = first = NULL;
642
643 switch (direction) {
644 case DMA_MEM_TO_DEV:
645 reg_width = __ffs(sconfig->dst_addr_width);
646 reg = sconfig->dst_addr;
647 ctllo = dw->prepare_ctllo(dwc)
648 | DWC_CTLL_DST_WIDTH(reg_width)
649 | DWC_CTLL_DST_FIX
650 | DWC_CTLL_SRC_INC;
651
652 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
653 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
654
655 for_each_sg(sgl, sg, sg_len, i) {
656 struct dw_desc *desc;
657 u32 len, mem;
658 size_t dlen;
659
660 mem = sg_dma_address(sg);
661 len = sg_dma_len(sg);
662
663 mem_width = __ffs(data_width | mem | len);
664
665slave_sg_todev_fill_desc:
666 desc = dwc_desc_get(dwc);
667 if (!desc)
668 goto err_desc_get;
669
670 ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen);
671
672 lli_write(desc, sar, mem);
673 lli_write(desc, dar, reg);
674 lli_write(desc, ctlhi, ctlhi);
675 lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width));
676 desc->len = dlen;
677
678 if (!first) {
679 first = desc;
680 } else {
681 lli_write(prev, llp, desc->txd.phys | lms);
682 list_add_tail(&desc->desc_node, &first->tx_list);
683 }
684 prev = desc;
685
686 mem += dlen;
687 len -= dlen;
688 total_len += dlen;
689
690 if (len)
691 goto slave_sg_todev_fill_desc;
692 }
693 break;
694 case DMA_DEV_TO_MEM:
695 reg_width = __ffs(sconfig->src_addr_width);
696 reg = sconfig->src_addr;
697 ctllo = dw->prepare_ctllo(dwc)
698 | DWC_CTLL_SRC_WIDTH(reg_width)
699 | DWC_CTLL_DST_INC
700 | DWC_CTLL_SRC_FIX;
701
702 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
703 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
704
705 for_each_sg(sgl, sg, sg_len, i) {
706 struct dw_desc *desc;
707 u32 len, mem;
708 size_t dlen;
709
710 mem = sg_dma_address(sg);
711 len = sg_dma_len(sg);
712
713slave_sg_fromdev_fill_desc:
714 desc = dwc_desc_get(dwc);
715 if (!desc)
716 goto err_desc_get;
717
718 ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen);
719
720 lli_write(desc, sar, reg);
721 lli_write(desc, dar, mem);
722 lli_write(desc, ctlhi, ctlhi);
723 mem_width = __ffs(data_width | mem);
724 lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
725 desc->len = dlen;
726
727 if (!first) {
728 first = desc;
729 } else {
730 lli_write(prev, llp, desc->txd.phys | lms);
731 list_add_tail(&desc->desc_node, &first->tx_list);
732 }
733 prev = desc;
734
735 mem += dlen;
736 len -= dlen;
737 total_len += dlen;
738
739 if (len)
740 goto slave_sg_fromdev_fill_desc;
741 }
742 break;
743 default:
744 return NULL;
745 }
746
747 if (flags & DMA_PREP_INTERRUPT)
748 /* Trigger interrupt after last block */
749 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
750
751 prev->lli.llp = 0;
752 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
753 first->total_len = total_len;
754
755 return &first->txd;
756
757err_desc_get:
758 dev_err(chan2dev(chan),
759 "not enough descriptors available. Direction %d\n", direction);
760 dwc_desc_put(dwc, first);
761 return NULL;
762}
763
764bool dw_dma_filter(struct dma_chan *chan, void *param)
765{
766 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
767 struct dw_dma_slave *dws = param;
768
769 if (dws->dma_dev != chan->device->dev)
770 return false;
771
772 /* permit channels in accordance with the channels mask */
773 if (dws->channels && !(dws->channels & dwc->mask))
774 return false;
775
776 /* We have to copy data since dws can be temporary storage */
777 memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave));
778
779 return true;
780}
781EXPORT_SYMBOL_GPL(dw_dma_filter);
782
783static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
784{
785 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
786 struct dw_dma *dw = to_dw_dma(chan->device);
787
788 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
789
790 dwc->dma_sconfig.src_maxburst =
791 clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
792 dwc->dma_sconfig.dst_maxburst =
793 clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
794
795 dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst);
796 dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst);
797
798 return 0;
799}
800
801static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain)
802{
803 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
804 unsigned int count = 20; /* timeout iterations */
805
806 dw->suspend_chan(dwc, drain);
807
808 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
809 udelay(2);
810
811 set_bit(DW_DMA_IS_PAUSED, &dwc->flags);
812}
813
814static int dwc_pause(struct dma_chan *chan)
815{
816 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
817 unsigned long flags;
818
819 spin_lock_irqsave(&dwc->lock, flags);
820 dwc_chan_pause(dwc, false);
821 spin_unlock_irqrestore(&dwc->lock, flags);
822
823 return 0;
824}
825
826static inline void dwc_chan_resume(struct dw_dma_chan *dwc, bool drain)
827{
828 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
829
830 dw->resume_chan(dwc, drain);
831
832 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags);
833}
834
835static int dwc_resume(struct dma_chan *chan)
836{
837 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
838 unsigned long flags;
839
840 spin_lock_irqsave(&dwc->lock, flags);
841
842 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
843 dwc_chan_resume(dwc, false);
844
845 spin_unlock_irqrestore(&dwc->lock, flags);
846
847 return 0;
848}
849
850static int dwc_terminate_all(struct dma_chan *chan)
851{
852 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
853 struct dw_dma *dw = to_dw_dma(chan->device);
854 struct dw_desc *desc, *_desc;
855 unsigned long flags;
856 LIST_HEAD(list);
857
858 spin_lock_irqsave(&dwc->lock, flags);
859
860 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
861
862 dwc_chan_pause(dwc, true);
863
864 dwc_chan_disable(dw, dwc);
865
866 dwc_chan_resume(dwc, true);
867
868 /* active_list entries will end up before queued entries */
869 list_splice_init(&dwc->queue, &list);
870 list_splice_init(&dwc->active_list, &list);
871
872 spin_unlock_irqrestore(&dwc->lock, flags);
873
874 /* Flush all pending and queued descriptors */
875 list_for_each_entry_safe(desc, _desc, &list, desc_node)
876 dwc_descriptor_complete(dwc, desc, false);
877
878 return 0;
879}
880
881static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c)
882{
883 struct dw_desc *desc;
884
885 list_for_each_entry(desc, &dwc->active_list, desc_node)
886 if (desc->txd.cookie == c)
887 return desc;
888
889 return NULL;
890}
891
892static u32 dwc_get_residue_and_status(struct dw_dma_chan *dwc, dma_cookie_t cookie,
893 enum dma_status *status)
894{
895 struct dw_desc *desc;
896 unsigned long flags;
897 u32 residue;
898
899 spin_lock_irqsave(&dwc->lock, flags);
900
901 desc = dwc_find_desc(dwc, cookie);
902 if (desc) {
903 if (desc == dwc_first_active(dwc)) {
904 residue = desc->residue;
905 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
906 residue -= dwc_get_sent(dwc);
907 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
908 *status = DMA_PAUSED;
909 } else {
910 residue = desc->total_len;
911 }
912 } else {
913 residue = 0;
914 }
915
916 spin_unlock_irqrestore(&dwc->lock, flags);
917 return residue;
918}
919
920static enum dma_status
921dwc_tx_status(struct dma_chan *chan,
922 dma_cookie_t cookie,
923 struct dma_tx_state *txstate)
924{
925 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
926 enum dma_status ret;
927
928 ret = dma_cookie_status(chan, cookie, txstate);
929 if (ret == DMA_COMPLETE)
930 return ret;
931
932 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
933
934 ret = dma_cookie_status(chan, cookie, txstate);
935 if (ret == DMA_COMPLETE)
936 return ret;
937
938 dma_set_residue(txstate, dwc_get_residue_and_status(dwc, cookie, &ret));
939 return ret;
940}
941
942static void dwc_issue_pending(struct dma_chan *chan)
943{
944 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
945 unsigned long flags;
946
947 spin_lock_irqsave(&dwc->lock, flags);
948 if (list_empty(&dwc->active_list))
949 dwc_dostart_first_queued(dwc);
950 spin_unlock_irqrestore(&dwc->lock, flags);
951}
952
953/*----------------------------------------------------------------------*/
954
955void do_dw_dma_off(struct dw_dma *dw)
956{
957 dma_writel(dw, CFG, 0);
958
959 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
960 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
961 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
962 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
963 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
964
965 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
966 cpu_relax();
967}
968
969void do_dw_dma_on(struct dw_dma *dw)
970{
971 dma_writel(dw, CFG, DW_CFG_DMA_EN);
972}
973
974static int dwc_alloc_chan_resources(struct dma_chan *chan)
975{
976 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
977 struct dw_dma *dw = to_dw_dma(chan->device);
978
979 dev_vdbg(chan2dev(chan), "%s\n", __func__);
980
981 /* ASSERT: channel is idle */
982 if (dma_readl(dw, CH_EN) & dwc->mask) {
983 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
984 return -EIO;
985 }
986
987 dma_cookie_init(chan);
988
989 /*
990 * NOTE: some controllers may have additional features that we
991 * need to initialize here, like "scatter-gather" (which
992 * doesn't mean what you think it means), and status writeback.
993 */
994
995 /*
996 * We need controller-specific data to set up slave transfers.
997 */
998 if (chan->private && !dw_dma_filter(chan, chan->private)) {
999 dev_warn(chan2dev(chan), "Wrong controller-specific data\n");
1000 return -EINVAL;
1001 }
1002
1003 /* Enable controller here if needed */
1004 if (!dw->in_use)
1005 do_dw_dma_on(dw);
1006 dw->in_use |= dwc->mask;
1007
1008 return 0;
1009}
1010
1011static void dwc_free_chan_resources(struct dma_chan *chan)
1012{
1013 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1014 struct dw_dma *dw = to_dw_dma(chan->device);
1015 unsigned long flags;
1016
1017 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1018 dwc->descs_allocated);
1019
1020 /* ASSERT: channel is idle */
1021 BUG_ON(!list_empty(&dwc->active_list));
1022 BUG_ON(!list_empty(&dwc->queue));
1023 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1024
1025 spin_lock_irqsave(&dwc->lock, flags);
1026
1027 /* Clear custom channel configuration */
1028 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave));
1029
1030 /* Disable interrupts */
1031 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1032 channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1033 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1034
1035 spin_unlock_irqrestore(&dwc->lock, flags);
1036
1037 /* Disable controller in case it was a last user */
1038 dw->in_use &= ~dwc->mask;
1039 if (!dw->in_use)
1040 do_dw_dma_off(dw);
1041
1042 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1043}
1044
1045static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
1046{
1047 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1048
1049 caps->max_burst = dwc->max_burst;
1050
1051 /*
1052 * It might be crucial for some devices to have the hardware
1053 * accelerated multi-block transfers supported, aka LLPs in DW DMAC
1054 * notation. So if LLPs are supported then max_sg_burst is set to
1055 * zero which means unlimited number of SG entries can be handled in a
1056 * single DMA transaction, otherwise it's just one SG entry.
1057 */
1058 if (dwc->nollp)
1059 caps->max_sg_burst = 1;
1060 else
1061 caps->max_sg_burst = 0;
1062}
1063
1064int do_dma_probe(struct dw_dma_chip *chip)
1065{
1066 struct dw_dma *dw = chip->dw;
1067 struct dw_dma_platform_data *pdata;
1068 bool autocfg = false;
1069 unsigned int dw_params;
1070 unsigned int i;
1071 int err;
1072
1073 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
1074 if (!dw->pdata)
1075 return -ENOMEM;
1076
1077 dw->regs = chip->regs;
1078
1079 pm_runtime_get_sync(chip->dev);
1080
1081 if (!chip->pdata) {
1082 dw_params = dma_readl(dw, DW_PARAMS);
1083 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1084
1085 autocfg = dw_params >> DW_PARAMS_EN & 1;
1086 if (!autocfg) {
1087 err = -EINVAL;
1088 goto err_pdata;
1089 }
1090
1091 /* Reassign the platform data pointer */
1092 pdata = dw->pdata;
1093
1094 /* Get hardware configuration parameters */
1095 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1096 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1097 for (i = 0; i < pdata->nr_masters; i++) {
1098 pdata->data_width[i] =
1099 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3);
1100 }
1101 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
1102
1103 /* Fill platform data with the default values */
1104 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1105 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1106 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1107 err = -EINVAL;
1108 goto err_pdata;
1109 } else {
1110 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata));
1111
1112 /* Reassign the platform data pointer */
1113 pdata = dw->pdata;
1114 }
1115
1116 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1117 GFP_KERNEL);
1118 if (!dw->chan) {
1119 err = -ENOMEM;
1120 goto err_pdata;
1121 }
1122
1123 /* Calculate all channel mask before DMA setup */
1124 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1125
1126 /* Force dma off, just in case */
1127 dw->disable(dw);
1128
1129 /* Device and instance ID for IRQ and DMA pool */
1130 dw->set_device_name(dw, chip->id);
1131
1132 /* Create a pool of consistent memory blocks for hardware descriptors */
1133 dw->desc_pool = dmam_pool_create(dw->name, chip->dev,
1134 sizeof(struct dw_desc), 4, 0);
1135 if (!dw->desc_pool) {
1136 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1137 err = -ENOMEM;
1138 goto err_pdata;
1139 }
1140
1141 tasklet_setup(&dw->tasklet, dw_dma_tasklet);
1142
1143 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1144 dw->name, dw);
1145 if (err)
1146 goto err_pdata;
1147
1148 INIT_LIST_HEAD(&dw->dma.channels);
1149 for (i = 0; i < pdata->nr_channels; i++) {
1150 struct dw_dma_chan *dwc = &dw->chan[i];
1151
1152 dwc->chan.device = &dw->dma;
1153 dma_cookie_init(&dwc->chan);
1154 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1155 list_add_tail(&dwc->chan.device_node,
1156 &dw->dma.channels);
1157 else
1158 list_add(&dwc->chan.device_node, &dw->dma.channels);
1159
1160 /* 7 is highest priority & 0 is lowest. */
1161 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1162 dwc->priority = pdata->nr_channels - i - 1;
1163 else
1164 dwc->priority = i;
1165
1166 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1167 spin_lock_init(&dwc->lock);
1168 dwc->mask = 1 << i;
1169
1170 INIT_LIST_HEAD(&dwc->active_list);
1171 INIT_LIST_HEAD(&dwc->queue);
1172
1173 channel_clear_bit(dw, CH_EN, dwc->mask);
1174
1175 dwc->direction = DMA_TRANS_NONE;
1176
1177 /* Hardware configuration */
1178 if (autocfg) {
1179 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1180 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
1181 unsigned int dwc_params = readl(addr);
1182
1183 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1184 dwc_params);
1185
1186 /*
1187 * Decode maximum block size for given channel. The
1188 * stored 4 bit value represents blocks from 0x00 for 3
1189 * up to 0x0a for 4095.
1190 */
1191 dwc->block_size =
1192 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;
1193
1194 /*
1195 * According to the DW DMA databook the true scatter-
1196 * gether LLPs aren't available if either multi-block
1197 * config is disabled (CHx_MULTI_BLK_EN == 0) or the
1198 * LLP register is hard-coded to zeros
1199 * (CHx_HC_LLP == 1).
1200 */
1201 dwc->nollp =
1202 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0 ||
1203 (dwc_params >> DWC_PARAMS_HC_LLP & 0x1) == 1;
1204 dwc->max_burst =
1205 (0x4 << (dwc_params >> DWC_PARAMS_MSIZE & 0x7));
1206 } else {
1207 dwc->block_size = pdata->block_size;
1208 dwc->nollp = !pdata->multi_block[i];
1209 dwc->max_burst = pdata->max_burst[i] ?: DW_DMA_MAX_BURST;
1210 }
1211 }
1212
1213 /* Clear all interrupts on all channels. */
1214 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1215 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1216 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1217 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1218 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1219
1220 /* Set capabilities */
1221 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1222 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1223 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1224
1225 dw->dma.dev = chip->dev;
1226 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1227 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1228
1229 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1230 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1231
1232 dw->dma.device_caps = dwc_caps;
1233 dw->dma.device_config = dwc_config;
1234 dw->dma.device_pause = dwc_pause;
1235 dw->dma.device_resume = dwc_resume;
1236 dw->dma.device_terminate_all = dwc_terminate_all;
1237
1238 dw->dma.device_tx_status = dwc_tx_status;
1239 dw->dma.device_issue_pending = dwc_issue_pending;
1240
1241 /* DMA capabilities */
1242 dw->dma.min_burst = DW_DMA_MIN_BURST;
1243 dw->dma.max_burst = DW_DMA_MAX_BURST;
1244 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1245 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1246 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1247 BIT(DMA_MEM_TO_MEM);
1248 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1249
1250 /*
1251 * For now there is no hardware with non uniform maximum block size
1252 * across all of the device channels, so we set the maximum segment
1253 * size as the block size found for the very first channel.
1254 */
1255 dma_set_max_seg_size(dw->dma.dev, dw->chan[0].block_size);
1256
1257 err = dma_async_device_register(&dw->dma);
1258 if (err)
1259 goto err_dma_register;
1260
1261 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1262 pdata->nr_channels);
1263
1264 pm_runtime_put_sync_suspend(chip->dev);
1265
1266 return 0;
1267
1268err_dma_register:
1269 free_irq(chip->irq, dw);
1270err_pdata:
1271 pm_runtime_put_sync_suspend(chip->dev);
1272 return err;
1273}
1274
1275int do_dma_remove(struct dw_dma_chip *chip)
1276{
1277 struct dw_dma *dw = chip->dw;
1278 struct dw_dma_chan *dwc, *_dwc;
1279
1280 pm_runtime_get_sync(chip->dev);
1281
1282 do_dw_dma_off(dw);
1283 dma_async_device_unregister(&dw->dma);
1284
1285 free_irq(chip->irq, dw);
1286 tasklet_kill(&dw->tasklet);
1287
1288 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1289 chan.device_node) {
1290 list_del(&dwc->chan.device_node);
1291 channel_clear_bit(dw, CH_EN, dwc->mask);
1292 }
1293
1294 pm_runtime_put_sync_suspend(chip->dev);
1295 return 0;
1296}
1297
1298int do_dw_dma_disable(struct dw_dma_chip *chip)
1299{
1300 struct dw_dma *dw = chip->dw;
1301
1302 dw->disable(dw);
1303 return 0;
1304}
1305EXPORT_SYMBOL_GPL(do_dw_dma_disable);
1306
1307int do_dw_dma_enable(struct dw_dma_chip *chip)
1308{
1309 struct dw_dma *dw = chip->dw;
1310
1311 dw->enable(dw);
1312 return 0;
1313}
1314EXPORT_SYMBOL_GPL(do_dw_dma_enable);
1315
1316MODULE_LICENSE("GPL v2");
1317MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1318MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1319MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
1/*
2 * Core driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/bitops.h>
14#include <linux/delay.h>
15#include <linux/dmaengine.h>
16#include <linux/dma-mapping.h>
17#include <linux/dmapool.h>
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/mm.h>
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
26
27#include "../dmaengine.h"
28#include "internal.h"
29
30/*
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
35 *
36 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
38 */
39
40#define DWC_DEFAULT_CTLLO(_chan) ({ \
41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
43 bool _is_slave = is_slave_direction(_dwc->direction); \
44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
45 DW_DMA_MSIZE_16; \
46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
47 DW_DMA_MSIZE_16; \
48 u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \
49 _dwc->dws.p_master : _dwc->dws.m_master; \
50 u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \
51 _dwc->dws.p_master : _dwc->dws.m_master; \
52 \
53 (DWC_CTLL_DST_MSIZE(_dmsize) \
54 | DWC_CTLL_SRC_MSIZE(_smsize) \
55 | DWC_CTLL_LLP_D_EN \
56 | DWC_CTLL_LLP_S_EN \
57 | DWC_CTLL_DMS(_dms) \
58 | DWC_CTLL_SMS(_sms)); \
59 })
60
61/* The set of bus widths supported by the DMA controller */
62#define DW_DMA_BUSWIDTHS \
63 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
64 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
65 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
66 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
67
68/*----------------------------------------------------------------------*/
69
70static struct device *chan2dev(struct dma_chan *chan)
71{
72 return &chan->dev->device;
73}
74
75static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
76{
77 return to_dw_desc(dwc->active_list.next);
78}
79
80static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
81{
82 struct dw_desc *desc = txd_to_dw_desc(tx);
83 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
84 dma_cookie_t cookie;
85 unsigned long flags;
86
87 spin_lock_irqsave(&dwc->lock, flags);
88 cookie = dma_cookie_assign(tx);
89
90 /*
91 * REVISIT: We should attempt to chain as many descriptors as
92 * possible, perhaps even appending to those already submitted
93 * for DMA. But this is hard to do in a race-free manner.
94 */
95
96 list_add_tail(&desc->desc_node, &dwc->queue);
97 spin_unlock_irqrestore(&dwc->lock, flags);
98 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n",
99 __func__, desc->txd.cookie);
100
101 return cookie;
102}
103
104static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
105{
106 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
107 struct dw_desc *desc;
108 dma_addr_t phys;
109
110 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys);
111 if (!desc)
112 return NULL;
113
114 dwc->descs_allocated++;
115 INIT_LIST_HEAD(&desc->tx_list);
116 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan);
117 desc->txd.tx_submit = dwc_tx_submit;
118 desc->txd.flags = DMA_CTRL_ACK;
119 desc->txd.phys = phys;
120 return desc;
121}
122
123static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
124{
125 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
126 struct dw_desc *child, *_next;
127
128 if (unlikely(!desc))
129 return;
130
131 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) {
132 list_del(&child->desc_node);
133 dma_pool_free(dw->desc_pool, child, child->txd.phys);
134 dwc->descs_allocated--;
135 }
136
137 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
138 dwc->descs_allocated--;
139}
140
141static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc)
142{
143 u32 cfghi = 0;
144 u32 cfglo = 0;
145
146 /* Set default burst alignment */
147 cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
148
149 /* Low 4 bits of the request lines */
150 cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
151 cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
152
153 /* Request line extension (2 bits) */
154 cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
155 cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
156
157 channel_writel(dwc, CFG_LO, cfglo);
158 channel_writel(dwc, CFG_HI, cfghi);
159}
160
161static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
162{
163 u32 cfghi = DWC_CFGH_FIFO_MODE;
164 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
165 bool hs_polarity = dwc->dws.hs_polarity;
166
167 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
168 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
169
170 /* Set polarity of handshake interface */
171 cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
172
173 channel_writel(dwc, CFG_LO, cfglo);
174 channel_writel(dwc, CFG_HI, cfghi);
175}
176
177static void dwc_initialize(struct dw_dma_chan *dwc)
178{
179 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
180
181 if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
182 return;
183
184 if (dw->pdata->is_idma32)
185 dwc_initialize_chan_idma32(dwc);
186 else
187 dwc_initialize_chan_dw(dwc);
188
189 /* Enable interrupts */
190 channel_set_bit(dw, MASK.XFER, dwc->mask);
191 channel_set_bit(dw, MASK.ERROR, dwc->mask);
192
193 set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
194}
195
196/*----------------------------------------------------------------------*/
197
198static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
199{
200 dev_err(chan2dev(&dwc->chan),
201 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
202 channel_readl(dwc, SAR),
203 channel_readl(dwc, DAR),
204 channel_readl(dwc, LLP),
205 channel_readl(dwc, CTL_HI),
206 channel_readl(dwc, CTL_LO));
207}
208
209static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
210{
211 channel_clear_bit(dw, CH_EN, dwc->mask);
212 while (dma_readl(dw, CH_EN) & dwc->mask)
213 cpu_relax();
214}
215
216static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes,
217 unsigned int width, size_t *len)
218{
219 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
220 u32 block;
221
222 /* Always in bytes for iDMA 32-bit */
223 if (dw->pdata->is_idma32)
224 width = 0;
225
226 if ((bytes >> width) > dwc->block_size) {
227 block = dwc->block_size;
228 *len = block << width;
229 } else {
230 block = bytes >> width;
231 *len = bytes;
232 }
233
234 return block;
235}
236
237static size_t block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
238{
239 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
240
241 if (dw->pdata->is_idma32)
242 return IDMA32C_CTLH_BLOCK_TS(block);
243
244 return DWC_CTLH_BLOCK_TS(block) << width;
245}
246
247/*----------------------------------------------------------------------*/
248
249/* Perform single block transfer */
250static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
251 struct dw_desc *desc)
252{
253 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
254 u32 ctllo;
255
256 /*
257 * Software emulation of LLP mode relies on interrupts to continue
258 * multi block transfer.
259 */
260 ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN;
261
262 channel_writel(dwc, SAR, lli_read(desc, sar));
263 channel_writel(dwc, DAR, lli_read(desc, dar));
264 channel_writel(dwc, CTL_LO, ctllo);
265 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi));
266 channel_set_bit(dw, CH_EN, dwc->mask);
267
268 /* Move pointer to next descriptor */
269 dwc->tx_node_active = dwc->tx_node_active->next;
270}
271
272/* Called with dwc->lock held and bh disabled */
273static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
274{
275 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
276 u8 lms = DWC_LLP_LMS(dwc->dws.m_master);
277 unsigned long was_soft_llp;
278
279 /* ASSERT: channel is idle */
280 if (dma_readl(dw, CH_EN) & dwc->mask) {
281 dev_err(chan2dev(&dwc->chan),
282 "%s: BUG: Attempted to start non-idle channel\n",
283 __func__);
284 dwc_dump_chan_regs(dwc);
285
286 /* The tasklet will hopefully advance the queue... */
287 return;
288 }
289
290 if (dwc->nollp) {
291 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
292 &dwc->flags);
293 if (was_soft_llp) {
294 dev_err(chan2dev(&dwc->chan),
295 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
296 return;
297 }
298
299 dwc_initialize(dwc);
300
301 first->residue = first->total_len;
302 dwc->tx_node_active = &first->tx_list;
303
304 /* Submit first block */
305 dwc_do_single_block(dwc, first);
306
307 return;
308 }
309
310 dwc_initialize(dwc);
311
312 channel_writel(dwc, LLP, first->txd.phys | lms);
313 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
314 channel_writel(dwc, CTL_HI, 0);
315 channel_set_bit(dw, CH_EN, dwc->mask);
316}
317
318static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
319{
320 struct dw_desc *desc;
321
322 if (list_empty(&dwc->queue))
323 return;
324
325 list_move(dwc->queue.next, &dwc->active_list);
326 desc = dwc_first_active(dwc);
327 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
328 dwc_dostart(dwc, desc);
329}
330
331/*----------------------------------------------------------------------*/
332
333static void
334dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
335 bool callback_required)
336{
337 struct dma_async_tx_descriptor *txd = &desc->txd;
338 struct dw_desc *child;
339 unsigned long flags;
340 struct dmaengine_desc_callback cb;
341
342 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
343
344 spin_lock_irqsave(&dwc->lock, flags);
345 dma_cookie_complete(txd);
346 if (callback_required)
347 dmaengine_desc_get_callback(txd, &cb);
348 else
349 memset(&cb, 0, sizeof(cb));
350
351 /* async_tx_ack */
352 list_for_each_entry(child, &desc->tx_list, desc_node)
353 async_tx_ack(&child->txd);
354 async_tx_ack(&desc->txd);
355 dwc_desc_put(dwc, desc);
356 spin_unlock_irqrestore(&dwc->lock, flags);
357
358 dmaengine_desc_callback_invoke(&cb, NULL);
359}
360
361static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
362{
363 struct dw_desc *desc, *_desc;
364 LIST_HEAD(list);
365 unsigned long flags;
366
367 spin_lock_irqsave(&dwc->lock, flags);
368 if (dma_readl(dw, CH_EN) & dwc->mask) {
369 dev_err(chan2dev(&dwc->chan),
370 "BUG: XFER bit set, but channel not idle!\n");
371
372 /* Try to continue after resetting the channel... */
373 dwc_chan_disable(dw, dwc);
374 }
375
376 /*
377 * Submit queued descriptors ASAP, i.e. before we go through
378 * the completed ones.
379 */
380 list_splice_init(&dwc->active_list, &list);
381 dwc_dostart_first_queued(dwc);
382
383 spin_unlock_irqrestore(&dwc->lock, flags);
384
385 list_for_each_entry_safe(desc, _desc, &list, desc_node)
386 dwc_descriptor_complete(dwc, desc, true);
387}
388
389/* Returns how many bytes were already received from source */
390static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
391{
392 u32 ctlhi = channel_readl(dwc, CTL_HI);
393 u32 ctllo = channel_readl(dwc, CTL_LO);
394
395 return block2bytes(dwc, ctlhi, ctllo >> 4 & 7);
396}
397
398static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
399{
400 dma_addr_t llp;
401 struct dw_desc *desc, *_desc;
402 struct dw_desc *child;
403 u32 status_xfer;
404 unsigned long flags;
405
406 spin_lock_irqsave(&dwc->lock, flags);
407 llp = channel_readl(dwc, LLP);
408 status_xfer = dma_readl(dw, RAW.XFER);
409
410 if (status_xfer & dwc->mask) {
411 /* Everything we've submitted is done */
412 dma_writel(dw, CLEAR.XFER, dwc->mask);
413
414 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
415 struct list_head *head, *active = dwc->tx_node_active;
416
417 /*
418 * We are inside first active descriptor.
419 * Otherwise something is really wrong.
420 */
421 desc = dwc_first_active(dwc);
422
423 head = &desc->tx_list;
424 if (active != head) {
425 /* Update residue to reflect last sent descriptor */
426 if (active == head->next)
427 desc->residue -= desc->len;
428 else
429 desc->residue -= to_dw_desc(active->prev)->len;
430
431 child = to_dw_desc(active);
432
433 /* Submit next block */
434 dwc_do_single_block(dwc, child);
435
436 spin_unlock_irqrestore(&dwc->lock, flags);
437 return;
438 }
439
440 /* We are done here */
441 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
442 }
443
444 spin_unlock_irqrestore(&dwc->lock, flags);
445
446 dwc_complete_all(dw, dwc);
447 return;
448 }
449
450 if (list_empty(&dwc->active_list)) {
451 spin_unlock_irqrestore(&dwc->lock, flags);
452 return;
453 }
454
455 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
456 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
457 spin_unlock_irqrestore(&dwc->lock, flags);
458 return;
459 }
460
461 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
462
463 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
464 /* Initial residue value */
465 desc->residue = desc->total_len;
466
467 /* Check first descriptors addr */
468 if (desc->txd.phys == DWC_LLP_LOC(llp)) {
469 spin_unlock_irqrestore(&dwc->lock, flags);
470 return;
471 }
472
473 /* Check first descriptors llp */
474 if (lli_read(desc, llp) == llp) {
475 /* This one is currently in progress */
476 desc->residue -= dwc_get_sent(dwc);
477 spin_unlock_irqrestore(&dwc->lock, flags);
478 return;
479 }
480
481 desc->residue -= desc->len;
482 list_for_each_entry(child, &desc->tx_list, desc_node) {
483 if (lli_read(child, llp) == llp) {
484 /* Currently in progress */
485 desc->residue -= dwc_get_sent(dwc);
486 spin_unlock_irqrestore(&dwc->lock, flags);
487 return;
488 }
489 desc->residue -= child->len;
490 }
491
492 /*
493 * No descriptors so far seem to be in progress, i.e.
494 * this one must be done.
495 */
496 spin_unlock_irqrestore(&dwc->lock, flags);
497 dwc_descriptor_complete(dwc, desc, true);
498 spin_lock_irqsave(&dwc->lock, flags);
499 }
500
501 dev_err(chan2dev(&dwc->chan),
502 "BUG: All descriptors done, but channel not idle!\n");
503
504 /* Try to continue after resetting the channel... */
505 dwc_chan_disable(dw, dwc);
506
507 dwc_dostart_first_queued(dwc);
508 spin_unlock_irqrestore(&dwc->lock, flags);
509}
510
511static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc)
512{
513 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
514 lli_read(desc, sar),
515 lli_read(desc, dar),
516 lli_read(desc, llp),
517 lli_read(desc, ctlhi),
518 lli_read(desc, ctllo));
519}
520
521static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
522{
523 struct dw_desc *bad_desc;
524 struct dw_desc *child;
525 unsigned long flags;
526
527 dwc_scan_descriptors(dw, dwc);
528
529 spin_lock_irqsave(&dwc->lock, flags);
530
531 /*
532 * The descriptor currently at the head of the active list is
533 * borked. Since we don't have any way to report errors, we'll
534 * just have to scream loudly and try to carry on.
535 */
536 bad_desc = dwc_first_active(dwc);
537 list_del_init(&bad_desc->desc_node);
538 list_move(dwc->queue.next, dwc->active_list.prev);
539
540 /* Clear the error flag and try to restart the controller */
541 dma_writel(dw, CLEAR.ERROR, dwc->mask);
542 if (!list_empty(&dwc->active_list))
543 dwc_dostart(dwc, dwc_first_active(dwc));
544
545 /*
546 * WARN may seem harsh, but since this only happens
547 * when someone submits a bad physical address in a
548 * descriptor, we should consider ourselves lucky that the
549 * controller flagged an error instead of scribbling over
550 * random memory locations.
551 */
552 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
553 " cookie: %d\n", bad_desc->txd.cookie);
554 dwc_dump_lli(dwc, bad_desc);
555 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
556 dwc_dump_lli(dwc, child);
557
558 spin_unlock_irqrestore(&dwc->lock, flags);
559
560 /* Pretend the descriptor completed successfully */
561 dwc_descriptor_complete(dwc, bad_desc, true);
562}
563
564static void dw_dma_tasklet(unsigned long data)
565{
566 struct dw_dma *dw = (struct dw_dma *)data;
567 struct dw_dma_chan *dwc;
568 u32 status_xfer;
569 u32 status_err;
570 unsigned int i;
571
572 status_xfer = dma_readl(dw, RAW.XFER);
573 status_err = dma_readl(dw, RAW.ERROR);
574
575 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
576
577 for (i = 0; i < dw->dma.chancnt; i++) {
578 dwc = &dw->chan[i];
579 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
580 dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n");
581 else if (status_err & (1 << i))
582 dwc_handle_error(dw, dwc);
583 else if (status_xfer & (1 << i))
584 dwc_scan_descriptors(dw, dwc);
585 }
586
587 /* Re-enable interrupts */
588 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
589 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
590}
591
592static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
593{
594 struct dw_dma *dw = dev_id;
595 u32 status;
596
597 /* Check if we have any interrupt from the DMAC which is not in use */
598 if (!dw->in_use)
599 return IRQ_NONE;
600
601 status = dma_readl(dw, STATUS_INT);
602 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
603
604 /* Check if we have any interrupt from the DMAC */
605 if (!status)
606 return IRQ_NONE;
607
608 /*
609 * Just disable the interrupts. We'll turn them back on in the
610 * softirq handler.
611 */
612 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
613 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
614 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
615
616 status = dma_readl(dw, STATUS_INT);
617 if (status) {
618 dev_err(dw->dma.dev,
619 "BUG: Unexpected interrupts pending: 0x%x\n",
620 status);
621
622 /* Try to recover */
623 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
624 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
625 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
626 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
627 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
628 }
629
630 tasklet_schedule(&dw->tasklet);
631
632 return IRQ_HANDLED;
633}
634
635/*----------------------------------------------------------------------*/
636
637static struct dma_async_tx_descriptor *
638dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
639 size_t len, unsigned long flags)
640{
641 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
642 struct dw_dma *dw = to_dw_dma(chan->device);
643 struct dw_desc *desc;
644 struct dw_desc *first;
645 struct dw_desc *prev;
646 size_t xfer_count;
647 size_t offset;
648 u8 m_master = dwc->dws.m_master;
649 unsigned int src_width;
650 unsigned int dst_width;
651 unsigned int data_width = dw->pdata->data_width[m_master];
652 u32 ctllo;
653 u8 lms = DWC_LLP_LMS(m_master);
654
655 dev_vdbg(chan2dev(chan),
656 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
657 &dest, &src, len, flags);
658
659 if (unlikely(!len)) {
660 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
661 return NULL;
662 }
663
664 dwc->direction = DMA_MEM_TO_MEM;
665
666 src_width = dst_width = __ffs(data_width | src | dest | len);
667
668 ctllo = DWC_DEFAULT_CTLLO(chan)
669 | DWC_CTLL_DST_WIDTH(dst_width)
670 | DWC_CTLL_SRC_WIDTH(src_width)
671 | DWC_CTLL_DST_INC
672 | DWC_CTLL_SRC_INC
673 | DWC_CTLL_FC_M2M;
674 prev = first = NULL;
675
676 for (offset = 0; offset < len; offset += xfer_count) {
677 desc = dwc_desc_get(dwc);
678 if (!desc)
679 goto err_desc_get;
680
681 lli_write(desc, sar, src + offset);
682 lli_write(desc, dar, dest + offset);
683 lli_write(desc, ctllo, ctllo);
684 lli_write(desc, ctlhi, bytes2block(dwc, len - offset, src_width, &xfer_count));
685 desc->len = xfer_count;
686
687 if (!first) {
688 first = desc;
689 } else {
690 lli_write(prev, llp, desc->txd.phys | lms);
691 list_add_tail(&desc->desc_node, &first->tx_list);
692 }
693 prev = desc;
694 }
695
696 if (flags & DMA_PREP_INTERRUPT)
697 /* Trigger interrupt after last block */
698 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
699
700 prev->lli.llp = 0;
701 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
702 first->txd.flags = flags;
703 first->total_len = len;
704
705 return &first->txd;
706
707err_desc_get:
708 dwc_desc_put(dwc, first);
709 return NULL;
710}
711
712static struct dma_async_tx_descriptor *
713dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
714 unsigned int sg_len, enum dma_transfer_direction direction,
715 unsigned long flags, void *context)
716{
717 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
718 struct dw_dma *dw = to_dw_dma(chan->device);
719 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
720 struct dw_desc *prev;
721 struct dw_desc *first;
722 u32 ctllo;
723 u8 m_master = dwc->dws.m_master;
724 u8 lms = DWC_LLP_LMS(m_master);
725 dma_addr_t reg;
726 unsigned int reg_width;
727 unsigned int mem_width;
728 unsigned int data_width = dw->pdata->data_width[m_master];
729 unsigned int i;
730 struct scatterlist *sg;
731 size_t total_len = 0;
732
733 dev_vdbg(chan2dev(chan), "%s\n", __func__);
734
735 if (unlikely(!is_slave_direction(direction) || !sg_len))
736 return NULL;
737
738 dwc->direction = direction;
739
740 prev = first = NULL;
741
742 switch (direction) {
743 case DMA_MEM_TO_DEV:
744 reg_width = __ffs(sconfig->dst_addr_width);
745 reg = sconfig->dst_addr;
746 ctllo = (DWC_DEFAULT_CTLLO(chan)
747 | DWC_CTLL_DST_WIDTH(reg_width)
748 | DWC_CTLL_DST_FIX
749 | DWC_CTLL_SRC_INC);
750
751 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
752 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
753
754 for_each_sg(sgl, sg, sg_len, i) {
755 struct dw_desc *desc;
756 u32 len, mem;
757 size_t dlen;
758
759 mem = sg_dma_address(sg);
760 len = sg_dma_len(sg);
761
762 mem_width = __ffs(data_width | mem | len);
763
764slave_sg_todev_fill_desc:
765 desc = dwc_desc_get(dwc);
766 if (!desc)
767 goto err_desc_get;
768
769 lli_write(desc, sar, mem);
770 lli_write(desc, dar, reg);
771 lli_write(desc, ctlhi, bytes2block(dwc, len, mem_width, &dlen));
772 lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width));
773 desc->len = dlen;
774
775 if (!first) {
776 first = desc;
777 } else {
778 lli_write(prev, llp, desc->txd.phys | lms);
779 list_add_tail(&desc->desc_node, &first->tx_list);
780 }
781 prev = desc;
782
783 mem += dlen;
784 len -= dlen;
785 total_len += dlen;
786
787 if (len)
788 goto slave_sg_todev_fill_desc;
789 }
790 break;
791 case DMA_DEV_TO_MEM:
792 reg_width = __ffs(sconfig->src_addr_width);
793 reg = sconfig->src_addr;
794 ctllo = (DWC_DEFAULT_CTLLO(chan)
795 | DWC_CTLL_SRC_WIDTH(reg_width)
796 | DWC_CTLL_DST_INC
797 | DWC_CTLL_SRC_FIX);
798
799 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
800 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
801
802 for_each_sg(sgl, sg, sg_len, i) {
803 struct dw_desc *desc;
804 u32 len, mem;
805 size_t dlen;
806
807 mem = sg_dma_address(sg);
808 len = sg_dma_len(sg);
809
810slave_sg_fromdev_fill_desc:
811 desc = dwc_desc_get(dwc);
812 if (!desc)
813 goto err_desc_get;
814
815 lli_write(desc, sar, reg);
816 lli_write(desc, dar, mem);
817 lli_write(desc, ctlhi, bytes2block(dwc, len, reg_width, &dlen));
818 mem_width = __ffs(data_width | mem | dlen);
819 lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
820 desc->len = dlen;
821
822 if (!first) {
823 first = desc;
824 } else {
825 lli_write(prev, llp, desc->txd.phys | lms);
826 list_add_tail(&desc->desc_node, &first->tx_list);
827 }
828 prev = desc;
829
830 mem += dlen;
831 len -= dlen;
832 total_len += dlen;
833
834 if (len)
835 goto slave_sg_fromdev_fill_desc;
836 }
837 break;
838 default:
839 return NULL;
840 }
841
842 if (flags & DMA_PREP_INTERRUPT)
843 /* Trigger interrupt after last block */
844 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
845
846 prev->lli.llp = 0;
847 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
848 first->total_len = total_len;
849
850 return &first->txd;
851
852err_desc_get:
853 dev_err(chan2dev(chan),
854 "not enough descriptors available. Direction %d\n", direction);
855 dwc_desc_put(dwc, first);
856 return NULL;
857}
858
859bool dw_dma_filter(struct dma_chan *chan, void *param)
860{
861 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
862 struct dw_dma_slave *dws = param;
863
864 if (dws->dma_dev != chan->device->dev)
865 return false;
866
867 /* We have to copy data since dws can be temporary storage */
868 memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave));
869
870 return true;
871}
872EXPORT_SYMBOL_GPL(dw_dma_filter);
873
874static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
875{
876 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
877 struct dma_slave_config *sc = &dwc->dma_sconfig;
878 struct dw_dma *dw = to_dw_dma(chan->device);
879 /*
880 * Fix sconfig's burst size according to dw_dmac. We need to convert
881 * them as:
882 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
883 *
884 * NOTE: burst size 2 is not supported by DesignWare controller.
885 * iDMA 32-bit supports it.
886 */
887 u32 s = dw->pdata->is_idma32 ? 1 : 2;
888
889 /* Check if chan will be configured for slave transfers */
890 if (!is_slave_direction(sconfig->direction))
891 return -EINVAL;
892
893 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
894 dwc->direction = sconfig->direction;
895
896 sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0;
897 sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0;
898
899 return 0;
900}
901
902static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain)
903{
904 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
905 unsigned int count = 20; /* timeout iterations */
906 u32 cfglo;
907
908 cfglo = channel_readl(dwc, CFG_LO);
909 if (dw->pdata->is_idma32) {
910 if (drain)
911 cfglo |= IDMA32C_CFGL_CH_DRAIN;
912 else
913 cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
914 }
915 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
916 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
917 udelay(2);
918
919 set_bit(DW_DMA_IS_PAUSED, &dwc->flags);
920}
921
922static int dwc_pause(struct dma_chan *chan)
923{
924 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
925 unsigned long flags;
926
927 spin_lock_irqsave(&dwc->lock, flags);
928 dwc_chan_pause(dwc, false);
929 spin_unlock_irqrestore(&dwc->lock, flags);
930
931 return 0;
932}
933
934static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
935{
936 u32 cfglo = channel_readl(dwc, CFG_LO);
937
938 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
939
940 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags);
941}
942
943static int dwc_resume(struct dma_chan *chan)
944{
945 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
946 unsigned long flags;
947
948 spin_lock_irqsave(&dwc->lock, flags);
949
950 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
951 dwc_chan_resume(dwc);
952
953 spin_unlock_irqrestore(&dwc->lock, flags);
954
955 return 0;
956}
957
958static int dwc_terminate_all(struct dma_chan *chan)
959{
960 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
961 struct dw_dma *dw = to_dw_dma(chan->device);
962 struct dw_desc *desc, *_desc;
963 unsigned long flags;
964 LIST_HEAD(list);
965
966 spin_lock_irqsave(&dwc->lock, flags);
967
968 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
969
970 dwc_chan_pause(dwc, true);
971
972 dwc_chan_disable(dw, dwc);
973
974 dwc_chan_resume(dwc);
975
976 /* active_list entries will end up before queued entries */
977 list_splice_init(&dwc->queue, &list);
978 list_splice_init(&dwc->active_list, &list);
979
980 spin_unlock_irqrestore(&dwc->lock, flags);
981
982 /* Flush all pending and queued descriptors */
983 list_for_each_entry_safe(desc, _desc, &list, desc_node)
984 dwc_descriptor_complete(dwc, desc, false);
985
986 return 0;
987}
988
989static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c)
990{
991 struct dw_desc *desc;
992
993 list_for_each_entry(desc, &dwc->active_list, desc_node)
994 if (desc->txd.cookie == c)
995 return desc;
996
997 return NULL;
998}
999
1000static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie)
1001{
1002 struct dw_desc *desc;
1003 unsigned long flags;
1004 u32 residue;
1005
1006 spin_lock_irqsave(&dwc->lock, flags);
1007
1008 desc = dwc_find_desc(dwc, cookie);
1009 if (desc) {
1010 if (desc == dwc_first_active(dwc)) {
1011 residue = desc->residue;
1012 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1013 residue -= dwc_get_sent(dwc);
1014 } else {
1015 residue = desc->total_len;
1016 }
1017 } else {
1018 residue = 0;
1019 }
1020
1021 spin_unlock_irqrestore(&dwc->lock, flags);
1022 return residue;
1023}
1024
1025static enum dma_status
1026dwc_tx_status(struct dma_chan *chan,
1027 dma_cookie_t cookie,
1028 struct dma_tx_state *txstate)
1029{
1030 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1031 enum dma_status ret;
1032
1033 ret = dma_cookie_status(chan, cookie, txstate);
1034 if (ret == DMA_COMPLETE)
1035 return ret;
1036
1037 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1038
1039 ret = dma_cookie_status(chan, cookie, txstate);
1040 if (ret == DMA_COMPLETE)
1041 return ret;
1042
1043 dma_set_residue(txstate, dwc_get_residue(dwc, cookie));
1044
1045 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS)
1046 return DMA_PAUSED;
1047
1048 return ret;
1049}
1050
1051static void dwc_issue_pending(struct dma_chan *chan)
1052{
1053 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1054 unsigned long flags;
1055
1056 spin_lock_irqsave(&dwc->lock, flags);
1057 if (list_empty(&dwc->active_list))
1058 dwc_dostart_first_queued(dwc);
1059 spin_unlock_irqrestore(&dwc->lock, flags);
1060}
1061
1062/*----------------------------------------------------------------------*/
1063
1064/*
1065 * Program FIFO size of channels.
1066 *
1067 * By default full FIFO (1024 bytes) is assigned to channel 0. Here we
1068 * slice FIFO on equal parts between channels.
1069 */
1070static void idma32_fifo_partition(struct dw_dma *dw)
1071{
1072 u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) |
1073 IDMA32C_FP_UPDATE;
1074 u64 fifo_partition = 0;
1075
1076 if (!dw->pdata->is_idma32)
1077 return;
1078
1079 /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
1080 fifo_partition |= value << 0;
1081
1082 /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
1083 fifo_partition |= value << 32;
1084
1085 /* Program FIFO Partition registers - 128 bytes for each channel */
1086 idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
1087 idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
1088}
1089
1090static void dw_dma_off(struct dw_dma *dw)
1091{
1092 unsigned int i;
1093
1094 dma_writel(dw, CFG, 0);
1095
1096 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1097 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1098 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1099 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1100 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1101
1102 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1103 cpu_relax();
1104
1105 for (i = 0; i < dw->dma.chancnt; i++)
1106 clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags);
1107}
1108
1109static void dw_dma_on(struct dw_dma *dw)
1110{
1111 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1112}
1113
1114static int dwc_alloc_chan_resources(struct dma_chan *chan)
1115{
1116 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1117 struct dw_dma *dw = to_dw_dma(chan->device);
1118
1119 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1120
1121 /* ASSERT: channel is idle */
1122 if (dma_readl(dw, CH_EN) & dwc->mask) {
1123 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1124 return -EIO;
1125 }
1126
1127 dma_cookie_init(chan);
1128
1129 /*
1130 * NOTE: some controllers may have additional features that we
1131 * need to initialize here, like "scatter-gather" (which
1132 * doesn't mean what you think it means), and status writeback.
1133 */
1134
1135 /*
1136 * We need controller-specific data to set up slave transfers.
1137 */
1138 if (chan->private && !dw_dma_filter(chan, chan->private)) {
1139 dev_warn(chan2dev(chan), "Wrong controller-specific data\n");
1140 return -EINVAL;
1141 }
1142
1143 /* Enable controller here if needed */
1144 if (!dw->in_use)
1145 dw_dma_on(dw);
1146 dw->in_use |= dwc->mask;
1147
1148 return 0;
1149}
1150
1151static void dwc_free_chan_resources(struct dma_chan *chan)
1152{
1153 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1154 struct dw_dma *dw = to_dw_dma(chan->device);
1155 unsigned long flags;
1156 LIST_HEAD(list);
1157
1158 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1159 dwc->descs_allocated);
1160
1161 /* ASSERT: channel is idle */
1162 BUG_ON(!list_empty(&dwc->active_list));
1163 BUG_ON(!list_empty(&dwc->queue));
1164 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1165
1166 spin_lock_irqsave(&dwc->lock, flags);
1167
1168 /* Clear custom channel configuration */
1169 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave));
1170
1171 clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
1172
1173 /* Disable interrupts */
1174 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1175 channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1176 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1177
1178 spin_unlock_irqrestore(&dwc->lock, flags);
1179
1180 /* Disable controller in case it was a last user */
1181 dw->in_use &= ~dwc->mask;
1182 if (!dw->in_use)
1183 dw_dma_off(dw);
1184
1185 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1186}
1187
1188int dw_dma_probe(struct dw_dma_chip *chip)
1189{
1190 struct dw_dma_platform_data *pdata;
1191 struct dw_dma *dw;
1192 bool autocfg = false;
1193 unsigned int dw_params;
1194 unsigned int i;
1195 int err;
1196
1197 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1198 if (!dw)
1199 return -ENOMEM;
1200
1201 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
1202 if (!dw->pdata)
1203 return -ENOMEM;
1204
1205 dw->regs = chip->regs;
1206 chip->dw = dw;
1207
1208 pm_runtime_get_sync(chip->dev);
1209
1210 if (!chip->pdata) {
1211 dw_params = dma_readl(dw, DW_PARAMS);
1212 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1213
1214 autocfg = dw_params >> DW_PARAMS_EN & 1;
1215 if (!autocfg) {
1216 err = -EINVAL;
1217 goto err_pdata;
1218 }
1219
1220 /* Reassign the platform data pointer */
1221 pdata = dw->pdata;
1222
1223 /* Get hardware configuration parameters */
1224 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1225 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1226 for (i = 0; i < pdata->nr_masters; i++) {
1227 pdata->data_width[i] =
1228 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3);
1229 }
1230 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
1231
1232 /* Fill platform data with the default values */
1233 pdata->is_private = true;
1234 pdata->is_memcpy = true;
1235 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1236 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1237 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1238 err = -EINVAL;
1239 goto err_pdata;
1240 } else {
1241 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata));
1242
1243 /* Reassign the platform data pointer */
1244 pdata = dw->pdata;
1245 }
1246
1247 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1248 GFP_KERNEL);
1249 if (!dw->chan) {
1250 err = -ENOMEM;
1251 goto err_pdata;
1252 }
1253
1254 /* Calculate all channel mask before DMA setup */
1255 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1256
1257 /* Force dma off, just in case */
1258 dw_dma_off(dw);
1259
1260 idma32_fifo_partition(dw);
1261
1262 /* Device and instance ID for IRQ and DMA pool */
1263 if (pdata->is_idma32)
1264 snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", chip->id);
1265 else
1266 snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", chip->id);
1267
1268 /* Create a pool of consistent memory blocks for hardware descriptors */
1269 dw->desc_pool = dmam_pool_create(dw->name, chip->dev,
1270 sizeof(struct dw_desc), 4, 0);
1271 if (!dw->desc_pool) {
1272 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1273 err = -ENOMEM;
1274 goto err_pdata;
1275 }
1276
1277 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1278
1279 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1280 dw->name, dw);
1281 if (err)
1282 goto err_pdata;
1283
1284 INIT_LIST_HEAD(&dw->dma.channels);
1285 for (i = 0; i < pdata->nr_channels; i++) {
1286 struct dw_dma_chan *dwc = &dw->chan[i];
1287
1288 dwc->chan.device = &dw->dma;
1289 dma_cookie_init(&dwc->chan);
1290 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1291 list_add_tail(&dwc->chan.device_node,
1292 &dw->dma.channels);
1293 else
1294 list_add(&dwc->chan.device_node, &dw->dma.channels);
1295
1296 /* 7 is highest priority & 0 is lowest. */
1297 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1298 dwc->priority = pdata->nr_channels - i - 1;
1299 else
1300 dwc->priority = i;
1301
1302 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1303 spin_lock_init(&dwc->lock);
1304 dwc->mask = 1 << i;
1305
1306 INIT_LIST_HEAD(&dwc->active_list);
1307 INIT_LIST_HEAD(&dwc->queue);
1308
1309 channel_clear_bit(dw, CH_EN, dwc->mask);
1310
1311 dwc->direction = DMA_TRANS_NONE;
1312
1313 /* Hardware configuration */
1314 if (autocfg) {
1315 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1316 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
1317 unsigned int dwc_params = readl(addr);
1318
1319 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1320 dwc_params);
1321
1322 /*
1323 * Decode maximum block size for given channel. The
1324 * stored 4 bit value represents blocks from 0x00 for 3
1325 * up to 0x0a for 4095.
1326 */
1327 dwc->block_size =
1328 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;
1329 dwc->nollp =
1330 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1331 } else {
1332 dwc->block_size = pdata->block_size;
1333 dwc->nollp = !pdata->multi_block[i];
1334 }
1335 }
1336
1337 /* Clear all interrupts on all channels. */
1338 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1339 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1340 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1341 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1342 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1343
1344 /* Set capabilities */
1345 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1346 if (pdata->is_private)
1347 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1348 if (pdata->is_memcpy)
1349 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1350
1351 dw->dma.dev = chip->dev;
1352 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1353 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1354
1355 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1356 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1357
1358 dw->dma.device_config = dwc_config;
1359 dw->dma.device_pause = dwc_pause;
1360 dw->dma.device_resume = dwc_resume;
1361 dw->dma.device_terminate_all = dwc_terminate_all;
1362
1363 dw->dma.device_tx_status = dwc_tx_status;
1364 dw->dma.device_issue_pending = dwc_issue_pending;
1365
1366 /* DMA capabilities */
1367 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1368 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1369 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1370 BIT(DMA_MEM_TO_MEM);
1371 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1372
1373 err = dma_async_device_register(&dw->dma);
1374 if (err)
1375 goto err_dma_register;
1376
1377 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1378 pdata->nr_channels);
1379
1380 pm_runtime_put_sync_suspend(chip->dev);
1381
1382 return 0;
1383
1384err_dma_register:
1385 free_irq(chip->irq, dw);
1386err_pdata:
1387 pm_runtime_put_sync_suspend(chip->dev);
1388 return err;
1389}
1390EXPORT_SYMBOL_GPL(dw_dma_probe);
1391
1392int dw_dma_remove(struct dw_dma_chip *chip)
1393{
1394 struct dw_dma *dw = chip->dw;
1395 struct dw_dma_chan *dwc, *_dwc;
1396
1397 pm_runtime_get_sync(chip->dev);
1398
1399 dw_dma_off(dw);
1400 dma_async_device_unregister(&dw->dma);
1401
1402 free_irq(chip->irq, dw);
1403 tasklet_kill(&dw->tasklet);
1404
1405 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1406 chan.device_node) {
1407 list_del(&dwc->chan.device_node);
1408 channel_clear_bit(dw, CH_EN, dwc->mask);
1409 }
1410
1411 pm_runtime_put_sync_suspend(chip->dev);
1412 return 0;
1413}
1414EXPORT_SYMBOL_GPL(dw_dma_remove);
1415
1416int dw_dma_disable(struct dw_dma_chip *chip)
1417{
1418 struct dw_dma *dw = chip->dw;
1419
1420 dw_dma_off(dw);
1421 return 0;
1422}
1423EXPORT_SYMBOL_GPL(dw_dma_disable);
1424
1425int dw_dma_enable(struct dw_dma_chip *chip)
1426{
1427 struct dw_dma *dw = chip->dw;
1428
1429 idma32_fifo_partition(dw);
1430
1431 dw_dma_on(dw);
1432 return 0;
1433}
1434EXPORT_SYMBOL_GPL(dw_dma_enable);
1435
1436MODULE_LICENSE("GPL v2");
1437MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1438MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1439MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");