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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7#ifndef __MIPS_ASM_MIPS_CPS_H__
8# error Please include asm/mips-cps.h rather than asm/mips-cm.h
9#endif
10
11#ifndef __MIPS_ASM_MIPS_CM_H__
12#define __MIPS_ASM_MIPS_CM_H__
13
14#include <linux/bitfield.h>
15#include <linux/bitops.h>
16#include <linux/errno.h>
17
18/* The base address of the CM GCR block */
19extern void __iomem *mips_gcr_base;
20
21/* The base address of the CM L2-only sync region */
22extern void __iomem *mips_cm_l2sync_base;
23
24/**
25 * __mips_cm_phys_base - retrieve the physical base address of the CM
26 *
27 * This function returns the physical base address of the Coherence Manager
28 * global control block, or 0 if no Coherence Manager is present. It provides
29 * a default implementation which reads the CMGCRBase register where available,
30 * and may be overridden by platforms which determine this address in a
31 * different way by defining a function with the same prototype except for the
32 * name mips_cm_phys_base (without underscores).
33 */
34extern phys_addr_t __mips_cm_phys_base(void);
35
36/*
37 * mips_cm_is64 - determine CM register width
38 *
39 * The CM register width is determined by the version of the CM, with CM3
40 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
41 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
42 * or vice-versa. This variable indicates the width of the memory accesses
43 * that the kernel will perform to GCRs, which may differ from the actual
44 * width of the GCRs.
45 *
46 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
47 */
48extern int mips_cm_is64;
49
50/**
51 * mips_cm_error_report - Report CM cache errors
52 */
53#ifdef CONFIG_MIPS_CM
54extern void mips_cm_error_report(void);
55#else
56static inline void mips_cm_error_report(void) {}
57#endif
58
59/**
60 * mips_cm_probe - probe for a Coherence Manager
61 *
62 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
63 * is successfully detected, else -errno.
64 */
65#ifdef CONFIG_MIPS_CM
66extern int mips_cm_probe(void);
67#else
68static inline int mips_cm_probe(void)
69{
70 return -ENODEV;
71}
72#endif
73
74/**
75 * mips_cm_present - determine whether a Coherence Manager is present
76 *
77 * Returns true if a CM is present in the system, else false.
78 */
79static inline bool mips_cm_present(void)
80{
81#ifdef CONFIG_MIPS_CM
82 return mips_gcr_base != NULL;
83#else
84 return false;
85#endif
86}
87
88/**
89 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
90 *
91 * Returns true if the system implements an L2-only sync region, else false.
92 */
93static inline bool mips_cm_has_l2sync(void)
94{
95#ifdef CONFIG_MIPS_CM
96 return mips_cm_l2sync_base != NULL;
97#else
98 return false;
99#endif
100}
101
102/* Offsets to register blocks from the CM base address */
103#define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */
104#define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */
105#define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */
106#define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */
107
108/* Total size of the CM memory mapped registers */
109#define MIPS_CM_GCR_SIZE 0x8000
110
111/* Size of the L2-only sync region */
112#define MIPS_CM_L2SYNC_SIZE 0x1000
113
114#define GCR_ACCESSOR_RO(sz, off, name) \
115 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
116 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
117
118#define GCR_ACCESSOR_RW(sz, off, name) \
119 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
120 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
121
122#define GCR_CX_ACCESSOR_RO(sz, off, name) \
123 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
124 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
125
126#define GCR_CX_ACCESSOR_RW(sz, off, name) \
127 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
128 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
129
130/* GCR_CONFIG - Information about the system */
131GCR_ACCESSOR_RO(64, 0x000, config)
132#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE BIT_ULL(43)
133#define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32)
134#define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
135#define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
136#define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
137
138/* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
139GCR_ACCESSOR_RW(64, 0x008, base)
140#define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)
141#define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
142#define CM_GCR_BASE_CMDEFTGT_MEM 0
143#define CM_GCR_BASE_CMDEFTGT_RESERVED 1
144#define CM_GCR_BASE_CMDEFTGT_IOCU0 2
145#define CM_GCR_BASE_CMDEFTGT_IOCU1 3
146
147/* GCR_ACCESS - Controls core/IOCU access to GCRs */
148GCR_ACCESSOR_RW(32, 0x020, access)
149#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
150
151/* GCR_REV - Indicates the Coherence Manager revision */
152GCR_ACCESSOR_RO(32, 0x030, rev)
153#define CM_GCR_REV_MAJOR GENMASK(15, 8)
154#define CM_GCR_REV_MINOR GENMASK(7, 0)
155
156#define CM_ENCODE_REV(major, minor) \
157 (FIELD_PREP(CM_GCR_REV_MAJOR, major) | \
158 FIELD_PREP(CM_GCR_REV_MINOR, minor))
159
160#define CM_REV_CM2 CM_ENCODE_REV(6, 0)
161#define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
162#define CM_REV_CM3 CM_ENCODE_REV(8, 0)
163#define CM_REV_CM3_5 CM_ENCODE_REV(9, 0)
164
165/* GCR_ERR_CONTROL - Control error checking logic */
166GCR_ACCESSOR_RW(32, 0x038, err_control)
167#define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
168#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
169
170/* GCR_ERR_MASK - Control which errors are reported as interrupts */
171GCR_ACCESSOR_RW(64, 0x040, error_mask)
172
173/* GCR_ERR_CAUSE - Indicates the type of error that occurred */
174GCR_ACCESSOR_RW(64, 0x048, error_cause)
175#define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
176#define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58)
177#define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
178
179/* GCR_ERR_ADDR - Indicates the address associated with an error */
180GCR_ACCESSOR_RW(64, 0x050, error_addr)
181
182/* GCR_ERR_MULT - Indicates when multiple errors have occurred */
183GCR_ACCESSOR_RW(64, 0x058, error_mult)
184#define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
185
186/* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
187GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
188#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12)
189#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0)
190
191/* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
192GCR_ACCESSOR_RW(64, 0x080, gic_base)
193#define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17)
194#define CM_GCR_GIC_BASE_GICEN BIT(0)
195
196/* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
197GCR_ACCESSOR_RW(64, 0x088, cpc_base)
198#define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15)
199#define CM_GCR_CPC_BASE_CPCEN BIT(0)
200
201/* GCR_REGn_BASE - Base addresses of CM address regions */
202GCR_ACCESSOR_RW(64, 0x090, reg0_base)
203GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
204GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
205GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
206#define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16)
207
208/* GCR_REGn_MASK - Size & destination of CM address regions */
209GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
210GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
211GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
212GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
213#define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)
214#define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5)
215#define CM_GCR_REGn_MASK_CCAOVREN BIT(4)
216#define CM_GCR_REGn_MASK_DROPL2 BIT(2)
217#define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0)
218#define CM_GCR_REGn_MASK_CMTGT_DISABLED 0x0
219#define CM_GCR_REGn_MASK_CMTGT_MEM 0x1
220#define CM_GCR_REGn_MASK_CMTGT_IOCU0 0x2
221#define CM_GCR_REGn_MASK_CMTGT_IOCU1 0x3
222
223/* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
224GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
225#define CM_GCR_GIC_STATUS_EX BIT(0)
226
227/* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
228GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
229#define CM_GCR_CPC_STATUS_EX BIT(0)
230
231/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
232GCR_ACCESSOR_RW(32, 0x130, l2_config)
233#define CM_GCR_L2_CONFIG_BYPASS BIT(20)
234#define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12)
235#define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8)
236#define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0)
237
238/* GCR_SYS_CONFIG2 - Further information about the system */
239GCR_ACCESSOR_RO(32, 0x150, sys_config2)
240#define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)
241
242/* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
243GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
244#define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)
245#define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8)
246#define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0)
247
248/* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
249GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
250#define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
251#define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)
252
253/* GCR_L2SM_COP - L2 cache op state machine control */
254GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
255#define CM_GCR_L2SM_COP_PRESENT BIT(31)
256#define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6)
257#define CM_GCR_L2SM_COP_RESULT_DONTCARE 0
258#define CM_GCR_L2SM_COP_RESULT_DONE_OK 1
259#define CM_GCR_L2SM_COP_RESULT_DONE_ERROR 2
260#define CM_GCR_L2SM_COP_RESULT_ABORT_OK 3
261#define CM_GCR_L2SM_COP_RESULT_ABORT_ERROR 4
262#define CM_GCR_L2SM_COP_RUNNING BIT(5)
263#define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2)
264#define CM_GCR_L2SM_COP_TYPE_IDX_WBINV 0
265#define CM_GCR_L2SM_COP_TYPE_IDX_STORETAG 1
266#define CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA 2
267#define CM_GCR_L2SM_COP_TYPE_HIT_INV 4
268#define CM_GCR_L2SM_COP_TYPE_HIT_WBINV 5
269#define CM_GCR_L2SM_COP_TYPE_HIT_WB 6
270#define CM_GCR_L2SM_COP_TYPE_FETCHLOCK 7
271#define CM_GCR_L2SM_COP_CMD GENMASK(1, 0)
272#define CM_GCR_L2SM_COP_CMD_START 1 /* only when idle */
273#define CM_GCR_L2SM_COP_CMD_ABORT 3 /* only when running */
274
275/* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
276GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
277#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48)
278#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6)
279
280/* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
281GCR_ACCESSOR_RW(64, 0x680, bev_base)
282
283/* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
284GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
285
286/* GCR_Cx_COHERENCE - Controls core coherence */
287GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
288#define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0)
289#define CM3_GCR_Cx_COHERENCE_COHEN BIT(0)
290
291/* GCR_Cx_CONFIG - Information about a core's configuration */
292GCR_CX_ACCESSOR_RO(32, 0x010, config)
293#define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10)
294#define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0)
295
296/* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
297GCR_CX_ACCESSOR_RW(32, 0x018, other)
298#define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16) /* CM < 3 */
299#define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */
300#define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */
301#define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24) /* CM >= 3.5 */
302#define CM_GCR_Cx_OTHER_BLOCK_LOCAL 0
303#define CM_GCR_Cx_OTHER_BLOCK_GLOBAL 1
304#define CM_GCR_Cx_OTHER_BLOCK_USER 2
305#define CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH 3
306#define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16) /* CM >= 3.5 */
307#define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8) /* CM >= 3 */
308#define CM_GCR_Cx_OTHER_CORE_CM 32
309#define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0) /* CM >= 3 */
310
311/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
312GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
313#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
314
315/* GCR_Cx_ID - Identify the current core */
316GCR_CX_ACCESSOR_RO(32, 0x028, id)
317#define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8)
318#define CM_GCR_Cx_ID_CORE GENMASK(7, 0)
319
320/* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
321GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
322#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31)
323#define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30)
324#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)
325#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)
326#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
327
328/**
329 * mips_cm_l2sync - perform an L2-only sync operation
330 *
331 * If an L2-only sync region is present in the system then this function
332 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
333 */
334static inline int mips_cm_l2sync(void)
335{
336 if (!mips_cm_has_l2sync())
337 return -ENODEV;
338
339 writel(0, mips_cm_l2sync_base);
340 return 0;
341}
342
343/**
344 * mips_cm_revision() - return CM revision
345 *
346 * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
347 * return value should be checked against the CM_REV_* macros.
348 */
349static inline int mips_cm_revision(void)
350{
351 if (!mips_cm_present())
352 return 0;
353
354 return read_gcr_rev();
355}
356
357/**
358 * mips_cm_max_vp_width() - return the width in bits of VP indices
359 *
360 * Return: the width, in bits, of VP indices in fields that combine core & VP
361 * indices.
362 */
363static inline unsigned int mips_cm_max_vp_width(void)
364{
365 extern int smp_num_siblings;
366
367 if (mips_cm_revision() >= CM_REV_CM3)
368 return FIELD_GET(CM_GCR_SYS_CONFIG2_MAXVPW,
369 read_gcr_sys_config2());
370
371 if (mips_cm_present()) {
372 /*
373 * We presume that all cores in the system will have the same
374 * number of VP(E)s, and if that ever changes then this will
375 * need revisiting.
376 */
377 return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, read_gcr_cl_config()) + 1;
378 }
379
380 if (IS_ENABLED(CONFIG_SMP))
381 return smp_num_siblings;
382
383 return 1;
384}
385
386/**
387 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
388 * @cpu: the CPU whose VP ID to calculate
389 *
390 * Hardware such as the GIC uses identifiers for VPs which may not match the
391 * CPU numbers used by Linux. This function calculates the hardware VP
392 * identifier corresponding to a given CPU.
393 *
394 * Return: the VP ID for the CPU.
395 */
396static inline unsigned int mips_cm_vp_id(unsigned int cpu)
397{
398 unsigned int core = cpu_core(&cpu_data[cpu]);
399 unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
400
401 return (core * mips_cm_max_vp_width()) + vp;
402}
403
404#ifdef CONFIG_MIPS_CM
405
406/**
407 * mips_cm_lock_other - lock access to redirect/other region
408 * @cluster: the other cluster to be accessed
409 * @core: the other core to be accessed
410 * @vp: the VP within the other core to be accessed
411 * @block: the register block to be accessed
412 *
413 * Configure the redirect/other region for the local core/VP (depending upon
414 * the CM revision) to target the specified @cluster, @core, @vp & register
415 * @block. Must be called before using the redirect/other region, and followed
416 * by a call to mips_cm_unlock_other() when access to the redirect/other region
417 * is complete.
418 *
419 * This function acquires a spinlock such that code between it &
420 * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
421 * reconfigure the redirect/other region, and cannot be interfered with by
422 * another VP in the core. As such calls to this function should not be nested.
423 */
424extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
425 unsigned int vp, unsigned int block);
426
427/**
428 * mips_cm_unlock_other - unlock access to redirect/other region
429 *
430 * Must be called after mips_cm_lock_other() once all required access to the
431 * redirect/other region has been completed.
432 */
433extern void mips_cm_unlock_other(void);
434
435#else /* !CONFIG_MIPS_CM */
436
437static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
438 unsigned int vp, unsigned int block) { }
439static inline void mips_cm_unlock_other(void) { }
440
441#endif /* !CONFIG_MIPS_CM */
442
443/**
444 * mips_cm_lock_other_cpu - lock access to redirect/other region
445 * @cpu: the other CPU whose register we want to access
446 *
447 * Configure the redirect/other region for the local core/VP (depending upon
448 * the CM revision) to target the specified @cpu & register @block. This is
449 * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
450 * for convenience.
451 */
452static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
453{
454 struct cpuinfo_mips *d = &cpu_data[cpu];
455
456 mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
457}
458
459#endif /* __MIPS_ASM_MIPS_CM_H__ */
1/*
2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __MIPS_ASM_MIPS_CM_H__
12#define __MIPS_ASM_MIPS_CM_H__
13
14#include <linux/io.h>
15#include <linux/types.h>
16
17/* The base address of the CM GCR block */
18extern void __iomem *mips_cm_base;
19
20/* The base address of the CM L2-only sync region */
21extern void __iomem *mips_cm_l2sync_base;
22
23/**
24 * __mips_cm_phys_base - retrieve the physical base address of the CM
25 *
26 * This function returns the physical base address of the Coherence Manager
27 * global control block, or 0 if no Coherence Manager is present. It provides
28 * a default implementation which reads the CMGCRBase register where available,
29 * and may be overriden by platforms which determine this address in a
30 * different way by defining a function with the same prototype except for the
31 * name mips_cm_phys_base (without underscores).
32 */
33extern phys_t __mips_cm_phys_base(void);
34
35/**
36 * mips_cm_probe - probe for a Coherence Manager
37 *
38 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
39 * is successfully detected, else -errno.
40 */
41#ifdef CONFIG_MIPS_CM
42extern int mips_cm_probe(void);
43#else
44static inline int mips_cm_probe(void)
45{
46 return -ENODEV;
47}
48#endif
49
50/**
51 * mips_cm_present - determine whether a Coherence Manager is present
52 *
53 * Returns true if a CM is present in the system, else false.
54 */
55static inline bool mips_cm_present(void)
56{
57#ifdef CONFIG_MIPS_CM
58 return mips_cm_base != NULL;
59#else
60 return false;
61#endif
62}
63
64/**
65 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
66 *
67 * Returns true if the system implements an L2-only sync region, else false.
68 */
69static inline bool mips_cm_has_l2sync(void)
70{
71#ifdef CONFIG_MIPS_CM
72 return mips_cm_l2sync_base != NULL;
73#else
74 return false;
75#endif
76}
77
78/* Offsets to register blocks from the CM base address */
79#define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */
80#define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */
81#define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */
82#define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */
83
84/* Total size of the CM memory mapped registers */
85#define MIPS_CM_GCR_SIZE 0x8000
86
87/* Size of the L2-only sync region */
88#define MIPS_CM_L2SYNC_SIZE 0x1000
89
90/* Macros to ease the creation of register access functions */
91#define BUILD_CM_R_(name, off) \
92static inline u32 *addr_gcr_##name(void) \
93{ \
94 return (u32 *)(mips_cm_base + (off)); \
95} \
96 \
97static inline u32 read_gcr_##name(void) \
98{ \
99 return __raw_readl(addr_gcr_##name()); \
100}
101
102#define BUILD_CM__W(name, off) \
103static inline void write_gcr_##name(u32 value) \
104{ \
105 __raw_writel(value, addr_gcr_##name()); \
106}
107
108#define BUILD_CM_RW(name, off) \
109 BUILD_CM_R_(name, off) \
110 BUILD_CM__W(name, off)
111
112#define BUILD_CM_Cx_R_(name, off) \
113 BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \
114 BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))
115
116#define BUILD_CM_Cx__W(name, off) \
117 BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \
118 BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))
119
120#define BUILD_CM_Cx_RW(name, off) \
121 BUILD_CM_Cx_R_(name, off) \
122 BUILD_CM_Cx__W(name, off)
123
124/* GCB register accessor functions */
125BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00)
126BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08)
127BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20)
128BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30)
129BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40)
130BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48)
131BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50)
132BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58)
133BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70)
134BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80)
135BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88)
136BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90)
137BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98)
138BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0)
139BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8)
140BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0)
141BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8)
142BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0)
143BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8)
144BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0)
145BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0)
146
147/* Core Local & Core Other register accessor functions */
148BUILD_CM_Cx_RW(reset_release, 0x00)
149BUILD_CM_Cx_RW(coherence, 0x08)
150BUILD_CM_Cx_R_(config, 0x10)
151BUILD_CM_Cx_RW(other, 0x18)
152BUILD_CM_Cx_RW(reset_base, 0x20)
153BUILD_CM_Cx_R_(id, 0x28)
154BUILD_CM_Cx_RW(reset_ext_base, 0x30)
155BUILD_CM_Cx_R_(tcid_0_priority, 0x40)
156BUILD_CM_Cx_R_(tcid_1_priority, 0x48)
157BUILD_CM_Cx_R_(tcid_2_priority, 0x50)
158BUILD_CM_Cx_R_(tcid_3_priority, 0x58)
159BUILD_CM_Cx_R_(tcid_4_priority, 0x60)
160BUILD_CM_Cx_R_(tcid_5_priority, 0x68)
161BUILD_CM_Cx_R_(tcid_6_priority, 0x70)
162BUILD_CM_Cx_R_(tcid_7_priority, 0x78)
163BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
164
165/* GCR_CONFIG register fields */
166#define CM_GCR_CONFIG_NUMIOCU_SHF 8
167#define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8)
168#define CM_GCR_CONFIG_PCORES_SHF 0
169#define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0)
170
171/* GCR_BASE register fields */
172#define CM_GCR_BASE_GCRBASE_SHF 15
173#define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15)
174#define CM_GCR_BASE_CMDEFTGT_SHF 0
175#define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0)
176#define CM_GCR_BASE_CMDEFTGT_DISABLED 0
177#define CM_GCR_BASE_CMDEFTGT_MEM 1
178#define CM_GCR_BASE_CMDEFTGT_IOCU0 2
179#define CM_GCR_BASE_CMDEFTGT_IOCU1 3
180
181/* GCR_ACCESS register fields */
182#define CM_GCR_ACCESS_ACCESSEN_SHF 0
183#define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0)
184
185/* GCR_REV register fields */
186#define CM_GCR_REV_MAJOR_SHF 8
187#define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8)
188#define CM_GCR_REV_MINOR_SHF 0
189#define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)
190
191/* GCR_ERROR_CAUSE register fields */
192#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27
193#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27)
194#define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0
195#define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0)
196
197/* GCR_ERROR_MULT register fields */
198#define CM_GCR_ERROR_MULT_ERR2ND_SHF 0
199#define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0)
200
201/* GCR_L2_ONLY_SYNC_BASE register fields */
202#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12
203#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12)
204#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0
205#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0)
206
207/* GCR_GIC_BASE register fields */
208#define CM_GCR_GIC_BASE_GICBASE_SHF 17
209#define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17)
210#define CM_GCR_GIC_BASE_GICEN_SHF 0
211#define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0)
212
213/* GCR_CPC_BASE register fields */
214#define CM_GCR_CPC_BASE_CPCBASE_SHF 17
215#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17)
216#define CM_GCR_CPC_BASE_CPCEN_SHF 0
217#define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0)
218
219/* GCR_REGn_BASE register fields */
220#define CM_GCR_REGn_BASE_BASEADDR_SHF 16
221#define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16)
222
223/* GCR_REGn_MASK register fields */
224#define CM_GCR_REGn_MASK_ADDRMASK_SHF 16
225#define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16)
226#define CM_GCR_REGn_MASK_CCAOVR_SHF 5
227#define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5)
228#define CM_GCR_REGn_MASK_CCAOVREN_SHF 4
229#define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4)
230#define CM_GCR_REGn_MASK_DROPL2_SHF 2
231#define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2)
232#define CM_GCR_REGn_MASK_CMTGT_SHF 0
233#define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0)
234#define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0)
235#define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0)
236#define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0)
237#define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0)
238
239/* GCR_GIC_STATUS register fields */
240#define CM_GCR_GIC_STATUS_EX_SHF 0
241#define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
242
243/* GCR_CPC_STATUS register fields */
244#define CM_GCR_CPC_STATUS_EX_SHF 0
245#define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
246
247/* GCR_Cx_COHERENCE register fields */
248#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0
249#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0)
250
251/* GCR_Cx_CONFIG register fields */
252#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10
253#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10)
254#define CM_GCR_Cx_CONFIG_PVPE_SHF 0
255#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0)
256
257/* GCR_Cx_OTHER register fields */
258#define CM_GCR_Cx_OTHER_CORENUM_SHF 16
259#define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16)
260
261/* GCR_Cx_RESET_BASE register fields */
262#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12
263#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12)
264
265/* GCR_Cx_RESET_EXT_BASE register fields */
266#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31
267#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31)
268#define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30
269#define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30)
270#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20
271#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20)
272#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1
273#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1)
274#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0
275#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0)
276
277/**
278 * mips_cm_numcores - return the number of cores present in the system
279 *
280 * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
281 * zero if no Coherence Manager is present.
282 */
283static inline unsigned mips_cm_numcores(void)
284{
285 if (!mips_cm_present())
286 return 0;
287
288 return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK)
289 >> CM_GCR_CONFIG_PCORES_SHF) + 1;
290}
291
292/**
293 * mips_cm_numiocu - return the number of IOCUs present in the system
294 *
295 * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
296 * if no Coherence Manager is present.
297 */
298static inline unsigned mips_cm_numiocu(void)
299{
300 if (!mips_cm_present())
301 return 0;
302
303 return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK)
304 >> CM_GCR_CONFIG_NUMIOCU_SHF;
305}
306
307/**
308 * mips_cm_l2sync - perform an L2-only sync operation
309 *
310 * If an L2-only sync region is present in the system then this function
311 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
312 */
313static inline int mips_cm_l2sync(void)
314{
315 if (!mips_cm_has_l2sync())
316 return -ENODEV;
317
318 writel(0, mips_cm_l2sync_base);
319 return 0;
320}
321
322#endif /* __MIPS_ASM_MIPS_CM_H__ */