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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Texas Instruments DSPS platforms "glue layer"
4 *
5 * Copyright (C) 2012, by Texas Instruments
6 *
7 * Based on the am35x "glue layer" code.
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * musb_dsps.c will be a common file for all the TI DSPS platforms
12 * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
13 * For now only ti81x is using this and in future davinci.c, am35x.c
14 * da8xx.c would be merged to this file after testing.
15 */
16
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/pm_runtime.h>
23#include <linux/module.h>
24#include <linux/usb/usb_phy_generic.h>
25#include <linux/platform_data/usb-omap.h>
26#include <linux/sizes.h>
27
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/usb/of.h>
31
32#include <linux/debugfs.h>
33
34#include "musb_core.h"
35
36static const struct of_device_id musb_dsps_of_match[];
37
38/*
39 * DSPS musb wrapper register offset.
40 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
41 * musb ips.
42 */
43struct dsps_musb_wrapper {
44 u16 revision;
45 u16 control;
46 u16 status;
47 u16 epintr_set;
48 u16 epintr_clear;
49 u16 epintr_status;
50 u16 coreintr_set;
51 u16 coreintr_clear;
52 u16 coreintr_status;
53 u16 phy_utmi;
54 u16 mode;
55 u16 tx_mode;
56 u16 rx_mode;
57
58 /* bit positions for control */
59 unsigned reset:5;
60
61 /* bit positions for interrupt */
62 unsigned usb_shift:5;
63 u32 usb_mask;
64 u32 usb_bitmap;
65 unsigned drvvbus:5;
66
67 unsigned txep_shift:5;
68 u32 txep_mask;
69 u32 txep_bitmap;
70
71 unsigned rxep_shift:5;
72 u32 rxep_mask;
73 u32 rxep_bitmap;
74
75 /* bit positions for phy_utmi */
76 unsigned otg_disable:5;
77
78 /* bit positions for mode */
79 unsigned iddig:5;
80 unsigned iddig_mux:5;
81 /* miscellaneous stuff */
82 unsigned poll_timeout;
83};
84
85/*
86 * register shadow for suspend
87 */
88struct dsps_context {
89 u32 control;
90 u32 epintr;
91 u32 coreintr;
92 u32 phy_utmi;
93 u32 mode;
94 u32 tx_mode;
95 u32 rx_mode;
96};
97
98/*
99 * DSPS glue structure.
100 */
101struct dsps_glue {
102 struct device *dev;
103 struct platform_device *musb; /* child musb pdev */
104 const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
105 int vbus_irq; /* optional vbus irq */
106 unsigned long last_timer; /* last timer data for each instance */
107 bool sw_babble_enabled;
108 void __iomem *usbss_base;
109
110 struct dsps_context context;
111 struct debugfs_regset32 regset;
112 struct dentry *dbgfs_root;
113};
114
115static const struct debugfs_reg32 dsps_musb_regs[] = {
116 { "revision", 0x00 },
117 { "control", 0x14 },
118 { "status", 0x18 },
119 { "eoi", 0x24 },
120 { "intr0_stat", 0x30 },
121 { "intr1_stat", 0x34 },
122 { "intr0_set", 0x38 },
123 { "intr1_set", 0x3c },
124 { "txmode", 0x70 },
125 { "rxmode", 0x74 },
126 { "autoreq", 0xd0 },
127 { "srpfixtime", 0xd4 },
128 { "tdown", 0xd8 },
129 { "phy_utmi", 0xe0 },
130 { "mode", 0xe8 },
131};
132
133static void dsps_mod_timer(struct dsps_glue *glue, int wait_ms)
134{
135 struct musb *musb = platform_get_drvdata(glue->musb);
136 int wait;
137
138 if (wait_ms < 0)
139 wait = msecs_to_jiffies(glue->wrp->poll_timeout);
140 else
141 wait = msecs_to_jiffies(wait_ms);
142
143 mod_timer(&musb->dev_timer, jiffies + wait);
144}
145
146/*
147 * If no vbus irq from the PMIC is configured, we need to poll VBUS status.
148 */
149static void dsps_mod_timer_optional(struct dsps_glue *glue)
150{
151 if (glue->vbus_irq)
152 return;
153
154 dsps_mod_timer(glue, -1);
155}
156
157/* USBSS / USB AM335x */
158#define USBSS_IRQ_STATUS 0x28
159#define USBSS_IRQ_ENABLER 0x2c
160#define USBSS_IRQ_CLEARR 0x30
161
162#define USBSS_IRQ_PD_COMP (1 << 2)
163
164/*
165 * dsps_musb_enable - enable interrupts
166 */
167static void dsps_musb_enable(struct musb *musb)
168{
169 struct device *dev = musb->controller;
170 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
171 const struct dsps_musb_wrapper *wrp = glue->wrp;
172 void __iomem *reg_base = musb->ctrl_base;
173 u32 epmask, coremask;
174
175 /* Workaround: setup IRQs through both register sets. */
176 epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
177 ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
178 coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
179
180 musb_writel(reg_base, wrp->epintr_set, epmask);
181 musb_writel(reg_base, wrp->coreintr_set, coremask);
182 /*
183 * start polling for runtime PM active and idle,
184 * and for ID change in dual-role idle mode.
185 */
186 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
187 dsps_mod_timer(glue, -1);
188}
189
190/*
191 * dsps_musb_disable - disable HDRC and flush interrupts
192 */
193static void dsps_musb_disable(struct musb *musb)
194{
195 struct device *dev = musb->controller;
196 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
197 const struct dsps_musb_wrapper *wrp = glue->wrp;
198 void __iomem *reg_base = musb->ctrl_base;
199
200 musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
201 musb_writel(reg_base, wrp->epintr_clear,
202 wrp->txep_bitmap | wrp->rxep_bitmap);
203 del_timer_sync(&musb->dev_timer);
204}
205
206/* Caller must take musb->lock */
207static int dsps_check_status(struct musb *musb, void *unused)
208{
209 void __iomem *mregs = musb->mregs;
210 struct device *dev = musb->controller;
211 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
212 const struct dsps_musb_wrapper *wrp = glue->wrp;
213 u8 devctl;
214 int skip_session = 0;
215
216 if (glue->vbus_irq)
217 del_timer(&musb->dev_timer);
218
219 /*
220 * We poll because DSPS IP's won't expose several OTG-critical
221 * status change events (from the transceiver) otherwise.
222 */
223 devctl = musb_readb(mregs, MUSB_DEVCTL);
224 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
225 usb_otg_state_string(musb->xceiv->otg->state));
226
227 switch (musb->xceiv->otg->state) {
228 case OTG_STATE_A_WAIT_VRISE:
229 if (musb->port_mode == MUSB_HOST) {
230 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
231 dsps_mod_timer_optional(glue);
232 break;
233 }
234 fallthrough;
235
236 case OTG_STATE_A_WAIT_BCON:
237 /* keep VBUS on for host-only mode */
238 if (musb->port_mode == MUSB_HOST) {
239 dsps_mod_timer_optional(glue);
240 break;
241 }
242 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
243 skip_session = 1;
244 fallthrough;
245
246 case OTG_STATE_A_IDLE:
247 case OTG_STATE_B_IDLE:
248 if (!glue->vbus_irq) {
249 if (devctl & MUSB_DEVCTL_BDEVICE) {
250 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
251 MUSB_DEV_MODE(musb);
252 } else {
253 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
254 MUSB_HST_MODE(musb);
255 }
256
257 if (musb->port_mode == MUSB_PERIPHERAL)
258 skip_session = 1;
259
260 if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
261 musb_writeb(mregs, MUSB_DEVCTL,
262 MUSB_DEVCTL_SESSION);
263 }
264 dsps_mod_timer_optional(glue);
265 break;
266 case OTG_STATE_A_WAIT_VFALL:
267 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
268 musb_writel(musb->ctrl_base, wrp->coreintr_set,
269 MUSB_INTR_VBUSERROR << wrp->usb_shift);
270 break;
271 default:
272 break;
273 }
274
275 return 0;
276}
277
278static void otg_timer(struct timer_list *t)
279{
280 struct musb *musb = from_timer(musb, t, dev_timer);
281 struct device *dev = musb->controller;
282 unsigned long flags;
283 int err;
284
285 err = pm_runtime_get(dev);
286 if ((err != -EINPROGRESS) && err < 0) {
287 dev_err(dev, "Poll could not pm_runtime_get: %i\n", err);
288 pm_runtime_put_noidle(dev);
289
290 return;
291 }
292
293 spin_lock_irqsave(&musb->lock, flags);
294 err = musb_queue_resume_work(musb, dsps_check_status, NULL);
295 if (err < 0)
296 dev_err(dev, "%s resume work: %i\n", __func__, err);
297 spin_unlock_irqrestore(&musb->lock, flags);
298 pm_runtime_mark_last_busy(dev);
299 pm_runtime_put_autosuspend(dev);
300}
301
302static void dsps_musb_clear_ep_rxintr(struct musb *musb, int epnum)
303{
304 u32 epintr;
305 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
306 const struct dsps_musb_wrapper *wrp = glue->wrp;
307
308 /* musb->lock might already been held */
309 epintr = (1 << epnum) << wrp->rxep_shift;
310 musb_writel(musb->ctrl_base, wrp->epintr_status, epintr);
311}
312
313static irqreturn_t dsps_interrupt(int irq, void *hci)
314{
315 struct musb *musb = hci;
316 void __iomem *reg_base = musb->ctrl_base;
317 struct device *dev = musb->controller;
318 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
319 const struct dsps_musb_wrapper *wrp = glue->wrp;
320 unsigned long flags;
321 irqreturn_t ret = IRQ_NONE;
322 u32 epintr, usbintr;
323
324 spin_lock_irqsave(&musb->lock, flags);
325
326 /* Get endpoint interrupts */
327 epintr = musb_readl(reg_base, wrp->epintr_status);
328 musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
329 musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
330
331 if (epintr)
332 musb_writel(reg_base, wrp->epintr_status, epintr);
333
334 /* Get usb core interrupts */
335 usbintr = musb_readl(reg_base, wrp->coreintr_status);
336 if (!usbintr && !epintr)
337 goto out;
338
339 musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
340 if (usbintr)
341 musb_writel(reg_base, wrp->coreintr_status, usbintr);
342
343 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
344 usbintr, epintr);
345
346 if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
347 int drvvbus = musb_readl(reg_base, wrp->status);
348 void __iomem *mregs = musb->mregs;
349 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
350 int err;
351
352 err = musb->int_usb & MUSB_INTR_VBUSERROR;
353 if (err) {
354 /*
355 * The Mentor core doesn't debounce VBUS as needed
356 * to cope with device connect current spikes. This
357 * means it's not uncommon for bus-powered devices
358 * to get VBUS errors during enumeration.
359 *
360 * This is a workaround, but newer RTL from Mentor
361 * seems to allow a better one: "re"-starting sessions
362 * without waiting for VBUS to stop registering in
363 * devctl.
364 */
365 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
366 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
367 dsps_mod_timer_optional(glue);
368 WARNING("VBUS error workaround (delay coming)\n");
369 } else if (drvvbus) {
370 MUSB_HST_MODE(musb);
371 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
372 dsps_mod_timer_optional(glue);
373 } else {
374 musb->is_active = 0;
375 MUSB_DEV_MODE(musb);
376 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
377 }
378
379 /* NOTE: this must complete power-on within 100 ms. */
380 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
381 drvvbus ? "on" : "off",
382 usb_otg_state_string(musb->xceiv->otg->state),
383 err ? " ERROR" : "",
384 devctl);
385 ret = IRQ_HANDLED;
386 }
387
388 if (musb->int_tx || musb->int_rx || musb->int_usb)
389 ret |= musb_interrupt(musb);
390
391 /* Poll for ID change and connect */
392 switch (musb->xceiv->otg->state) {
393 case OTG_STATE_B_IDLE:
394 case OTG_STATE_A_WAIT_BCON:
395 dsps_mod_timer_optional(glue);
396 break;
397 default:
398 break;
399 }
400
401out:
402 spin_unlock_irqrestore(&musb->lock, flags);
403
404 return ret;
405}
406
407static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue)
408{
409 struct dentry *root;
410 char buf[128];
411
412 sprintf(buf, "%s.dsps", dev_name(musb->controller));
413 root = debugfs_create_dir(buf, usb_debug_root);
414 glue->dbgfs_root = root;
415
416 glue->regset.regs = dsps_musb_regs;
417 glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs);
418 glue->regset.base = musb->ctrl_base;
419
420 debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset);
421 return 0;
422}
423
424static int dsps_musb_init(struct musb *musb)
425{
426 struct device *dev = musb->controller;
427 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
428 struct platform_device *parent = to_platform_device(dev->parent);
429 const struct dsps_musb_wrapper *wrp = glue->wrp;
430 void __iomem *reg_base;
431 struct resource *r;
432 u32 rev, val;
433 int ret;
434
435 r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
436 reg_base = devm_ioremap_resource(dev, r);
437 if (IS_ERR(reg_base))
438 return PTR_ERR(reg_base);
439 musb->ctrl_base = reg_base;
440
441 /* NOP driver needs change if supporting dual instance */
442 musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0);
443 if (IS_ERR(musb->xceiv))
444 return PTR_ERR(musb->xceiv);
445
446 musb->phy = devm_phy_get(dev->parent, "usb2-phy");
447
448 /* Returns zero if e.g. not clocked */
449 rev = musb_readl(reg_base, wrp->revision);
450 if (!rev)
451 return -ENODEV;
452
453 if (IS_ERR(musb->phy)) {
454 musb->phy = NULL;
455 } else {
456 ret = phy_init(musb->phy);
457 if (ret < 0)
458 return ret;
459 ret = phy_power_on(musb->phy);
460 if (ret) {
461 phy_exit(musb->phy);
462 return ret;
463 }
464 }
465
466 timer_setup(&musb->dev_timer, otg_timer, 0);
467
468 /* Reset the musb */
469 musb_writel(reg_base, wrp->control, (1 << wrp->reset));
470
471 musb->isr = dsps_interrupt;
472
473 /* reset the otgdisable bit, needed for host mode to work */
474 val = musb_readl(reg_base, wrp->phy_utmi);
475 val &= ~(1 << wrp->otg_disable);
476 musb_writel(musb->ctrl_base, wrp->phy_utmi, val);
477
478 /*
479 * Check whether the dsps version has babble control enabled.
480 * In latest silicon revision the babble control logic is enabled.
481 * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
482 * logic enabled.
483 */
484 val = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
485 if (val & MUSB_BABBLE_RCV_DISABLE) {
486 glue->sw_babble_enabled = true;
487 val |= MUSB_BABBLE_SW_SESSION_CTRL;
488 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
489 }
490
491 dsps_mod_timer(glue, -1);
492
493 return dsps_musb_dbg_init(musb, glue);
494}
495
496static int dsps_musb_exit(struct musb *musb)
497{
498 struct device *dev = musb->controller;
499 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
500
501 del_timer_sync(&musb->dev_timer);
502 phy_power_off(musb->phy);
503 phy_exit(musb->phy);
504 debugfs_remove_recursive(glue->dbgfs_root);
505
506 return 0;
507}
508
509static int dsps_musb_set_mode(struct musb *musb, u8 mode)
510{
511 struct device *dev = musb->controller;
512 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
513 const struct dsps_musb_wrapper *wrp = glue->wrp;
514 void __iomem *ctrl_base = musb->ctrl_base;
515 u32 reg;
516
517 reg = musb_readl(ctrl_base, wrp->mode);
518
519 switch (mode) {
520 case MUSB_HOST:
521 reg &= ~(1 << wrp->iddig);
522
523 /*
524 * if we're setting mode to host-only or device-only, we're
525 * going to ignore whatever the PHY sends us and just force
526 * ID pin status by SW
527 */
528 reg |= (1 << wrp->iddig_mux);
529
530 musb_writel(ctrl_base, wrp->mode, reg);
531 musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
532 break;
533 case MUSB_PERIPHERAL:
534 reg |= (1 << wrp->iddig);
535
536 /*
537 * if we're setting mode to host-only or device-only, we're
538 * going to ignore whatever the PHY sends us and just force
539 * ID pin status by SW
540 */
541 reg |= (1 << wrp->iddig_mux);
542
543 musb_writel(ctrl_base, wrp->mode, reg);
544 break;
545 case MUSB_OTG:
546 musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
547 break;
548 default:
549 dev_err(glue->dev, "unsupported mode %d\n", mode);
550 return -EINVAL;
551 }
552
553 return 0;
554}
555
556static bool dsps_sw_babble_control(struct musb *musb)
557{
558 u8 babble_ctl;
559 bool session_restart = false;
560
561 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
562 dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n",
563 babble_ctl);
564 /*
565 * check line monitor flag to check whether babble is
566 * due to noise
567 */
568 dev_dbg(musb->controller, "STUCK_J is %s\n",
569 babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset");
570
571 if (babble_ctl & MUSB_BABBLE_STUCK_J) {
572 int timeout = 10;
573
574 /*
575 * babble is due to noise, then set transmit idle (d7 bit)
576 * to resume normal operation
577 */
578 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
579 babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE;
580 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);
581
582 /* wait till line monitor flag cleared */
583 dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
584 do {
585 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
586 udelay(1);
587 } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--);
588
589 /* check whether stuck_at_j bit cleared */
590 if (babble_ctl & MUSB_BABBLE_STUCK_J) {
591 /*
592 * real babble condition has occurred
593 * restart the controller to start the
594 * session again
595 */
596 dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
597 babble_ctl);
598 session_restart = true;
599 }
600 } else {
601 session_restart = true;
602 }
603
604 return session_restart;
605}
606
607static int dsps_musb_recover(struct musb *musb)
608{
609 struct device *dev = musb->controller;
610 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
611 int session_restart = 0;
612
613 if (glue->sw_babble_enabled)
614 session_restart = dsps_sw_babble_control(musb);
615 else
616 session_restart = 1;
617
618 return session_restart ? 0 : -EPIPE;
619}
620
621/* Similar to am35x, dm81xx support only 32-bit read operation */
622static void dsps_read_fifo32(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
623{
624 void __iomem *fifo = hw_ep->fifo;
625
626 if (len >= 4) {
627 ioread32_rep(fifo, dst, len >> 2);
628 dst += len & ~0x03;
629 len &= 0x03;
630 }
631
632 /* Read any remaining 1 to 3 bytes */
633 if (len > 0) {
634 u32 val = musb_readl(fifo, 0);
635 memcpy(dst, &val, len);
636 }
637}
638
639#ifdef CONFIG_USB_TI_CPPI41_DMA
640static void dsps_dma_controller_callback(struct dma_controller *c)
641{
642 struct musb *musb = c->musb;
643 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
644 void __iomem *usbss_base = glue->usbss_base;
645 u32 status;
646
647 status = musb_readl(usbss_base, USBSS_IRQ_STATUS);
648 if (status & USBSS_IRQ_PD_COMP)
649 musb_writel(usbss_base, USBSS_IRQ_STATUS, USBSS_IRQ_PD_COMP);
650}
651
652static struct dma_controller *
653dsps_dma_controller_create(struct musb *musb, void __iomem *base)
654{
655 struct dma_controller *controller;
656 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
657 void __iomem *usbss_base = glue->usbss_base;
658
659 controller = cppi41_dma_controller_create(musb, base);
660 if (IS_ERR_OR_NULL(controller))
661 return controller;
662
663 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
664 controller->dma_callback = dsps_dma_controller_callback;
665
666 return controller;
667}
668
669#ifdef CONFIG_PM_SLEEP
670static void dsps_dma_controller_suspend(struct dsps_glue *glue)
671{
672 void __iomem *usbss_base = glue->usbss_base;
673
674 musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP);
675}
676
677static void dsps_dma_controller_resume(struct dsps_glue *glue)
678{
679 void __iomem *usbss_base = glue->usbss_base;
680
681 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
682}
683#endif
684#else /* CONFIG_USB_TI_CPPI41_DMA */
685#ifdef CONFIG_PM_SLEEP
686static void dsps_dma_controller_suspend(struct dsps_glue *glue) {}
687static void dsps_dma_controller_resume(struct dsps_glue *glue) {}
688#endif
689#endif /* CONFIG_USB_TI_CPPI41_DMA */
690
691static struct musb_platform_ops dsps_ops = {
692 .quirks = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP,
693 .init = dsps_musb_init,
694 .exit = dsps_musb_exit,
695
696#ifdef CONFIG_USB_TI_CPPI41_DMA
697 .dma_init = dsps_dma_controller_create,
698 .dma_exit = cppi41_dma_controller_destroy,
699#endif
700 .enable = dsps_musb_enable,
701 .disable = dsps_musb_disable,
702
703 .set_mode = dsps_musb_set_mode,
704 .recover = dsps_musb_recover,
705 .clear_ep_rxintr = dsps_musb_clear_ep_rxintr,
706};
707
708static u64 musb_dmamask = DMA_BIT_MASK(32);
709
710static int get_int_prop(struct device_node *dn, const char *s)
711{
712 int ret;
713 u32 val;
714
715 ret = of_property_read_u32(dn, s, &val);
716 if (ret)
717 return 0;
718 return val;
719}
720
721static int dsps_create_musb_pdev(struct dsps_glue *glue,
722 struct platform_device *parent)
723{
724 struct musb_hdrc_platform_data pdata;
725 struct resource resources[2];
726 struct resource *res;
727 struct device *dev = &parent->dev;
728 struct musb_hdrc_config *config;
729 struct platform_device *musb;
730 struct device_node *dn = parent->dev.of_node;
731 int ret, val;
732
733 memset(resources, 0, sizeof(resources));
734 res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc");
735 if (!res) {
736 dev_err(dev, "failed to get memory.\n");
737 return -EINVAL;
738 }
739 resources[0] = *res;
740
741 ret = platform_get_irq_byname(parent, "mc");
742 if (ret < 0)
743 return ret;
744
745 resources[1].start = ret;
746 resources[1].end = ret;
747 resources[1].flags = IORESOURCE_IRQ | irq_get_trigger_type(ret);
748 resources[1].name = "mc";
749
750 /* allocate the child platform device */
751 musb = platform_device_alloc("musb-hdrc",
752 (resources[0].start & 0xFFF) == 0x400 ? 0 : 1);
753 if (!musb) {
754 dev_err(dev, "failed to allocate musb device\n");
755 return -ENOMEM;
756 }
757
758 musb->dev.parent = dev;
759 musb->dev.dma_mask = &musb_dmamask;
760 musb->dev.coherent_dma_mask = musb_dmamask;
761 device_set_of_node_from_dev(&musb->dev, &parent->dev);
762
763 glue->musb = musb;
764
765 ret = platform_device_add_resources(musb, resources,
766 ARRAY_SIZE(resources));
767 if (ret) {
768 dev_err(dev, "failed to add resources\n");
769 goto err;
770 }
771
772 config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL);
773 if (!config) {
774 ret = -ENOMEM;
775 goto err;
776 }
777 pdata.config = config;
778 pdata.platform_ops = &dsps_ops;
779
780 config->num_eps = get_int_prop(dn, "mentor,num-eps");
781 config->ram_bits = get_int_prop(dn, "mentor,ram-bits");
782 config->host_port_deassert_reset_at_resume = 1;
783 pdata.mode = musb_get_mode(dev);
784 /* DT keeps this entry in mA, musb expects it as per USB spec */
785 pdata.power = get_int_prop(dn, "mentor,power") / 2;
786
787 ret = of_property_read_u32(dn, "mentor,multipoint", &val);
788 if (!ret && val)
789 config->multipoint = true;
790
791 config->maximum_speed = usb_get_maximum_speed(&parent->dev);
792 switch (config->maximum_speed) {
793 case USB_SPEED_LOW:
794 case USB_SPEED_FULL:
795 break;
796 case USB_SPEED_SUPER:
797 dev_warn(dev, "ignore incorrect maximum_speed "
798 "(super-speed) setting in dts");
799 fallthrough;
800 default:
801 config->maximum_speed = USB_SPEED_HIGH;
802 }
803
804 ret = platform_device_add_data(musb, &pdata, sizeof(pdata));
805 if (ret) {
806 dev_err(dev, "failed to add platform_data\n");
807 goto err;
808 }
809
810 ret = platform_device_add(musb);
811 if (ret) {
812 dev_err(dev, "failed to register musb device\n");
813 goto err;
814 }
815 return 0;
816
817err:
818 platform_device_put(musb);
819 return ret;
820}
821
822static irqreturn_t dsps_vbus_threaded_irq(int irq, void *priv)
823{
824 struct dsps_glue *glue = priv;
825 struct musb *musb = platform_get_drvdata(glue->musb);
826
827 if (!musb)
828 return IRQ_NONE;
829
830 dev_dbg(glue->dev, "VBUS interrupt\n");
831 dsps_mod_timer(glue, 0);
832
833 return IRQ_HANDLED;
834}
835
836static int dsps_setup_optional_vbus_irq(struct platform_device *pdev,
837 struct dsps_glue *glue)
838{
839 int error;
840
841 glue->vbus_irq = platform_get_irq_byname(pdev, "vbus");
842 if (glue->vbus_irq == -EPROBE_DEFER)
843 return -EPROBE_DEFER;
844
845 if (glue->vbus_irq <= 0) {
846 glue->vbus_irq = 0;
847 return 0;
848 }
849
850 error = devm_request_threaded_irq(glue->dev, glue->vbus_irq,
851 NULL, dsps_vbus_threaded_irq,
852 IRQF_SHARED,
853 "vbus", glue);
854 if (error) {
855 glue->vbus_irq = 0;
856 return error;
857 }
858 dev_dbg(glue->dev, "VBUS irq %i configured\n", glue->vbus_irq);
859
860 return 0;
861}
862
863static int dsps_probe(struct platform_device *pdev)
864{
865 const struct of_device_id *match;
866 const struct dsps_musb_wrapper *wrp;
867 struct dsps_glue *glue;
868 int ret;
869
870 if (!strcmp(pdev->name, "musb-hdrc"))
871 return -ENODEV;
872
873 match = of_match_node(musb_dsps_of_match, pdev->dev.of_node);
874 if (!match) {
875 dev_err(&pdev->dev, "fail to get matching of_match struct\n");
876 return -EINVAL;
877 }
878 wrp = match->data;
879
880 if (of_device_is_compatible(pdev->dev.of_node, "ti,musb-dm816"))
881 dsps_ops.read_fifo = dsps_read_fifo32;
882
883 /* allocate glue */
884 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
885 if (!glue)
886 return -ENOMEM;
887
888 glue->dev = &pdev->dev;
889 glue->wrp = wrp;
890 glue->usbss_base = of_iomap(pdev->dev.parent->of_node, 0);
891 if (!glue->usbss_base)
892 return -ENXIO;
893
894 platform_set_drvdata(pdev, glue);
895 pm_runtime_enable(&pdev->dev);
896 ret = dsps_create_musb_pdev(glue, pdev);
897 if (ret)
898 goto err;
899
900 if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) {
901 ret = dsps_setup_optional_vbus_irq(pdev, glue);
902 if (ret)
903 goto unregister_pdev;
904 }
905
906 return 0;
907
908unregister_pdev:
909 platform_device_unregister(glue->musb);
910err:
911 pm_runtime_disable(&pdev->dev);
912 iounmap(glue->usbss_base);
913 return ret;
914}
915
916static void dsps_remove(struct platform_device *pdev)
917{
918 struct dsps_glue *glue = platform_get_drvdata(pdev);
919
920 platform_device_unregister(glue->musb);
921
922 pm_runtime_disable(&pdev->dev);
923 iounmap(glue->usbss_base);
924}
925
926static const struct dsps_musb_wrapper am33xx_driver_data = {
927 .revision = 0x00,
928 .control = 0x14,
929 .status = 0x18,
930 .epintr_set = 0x38,
931 .epintr_clear = 0x40,
932 .epintr_status = 0x30,
933 .coreintr_set = 0x3c,
934 .coreintr_clear = 0x44,
935 .coreintr_status = 0x34,
936 .phy_utmi = 0xe0,
937 .mode = 0xe8,
938 .tx_mode = 0x70,
939 .rx_mode = 0x74,
940 .reset = 0,
941 .otg_disable = 21,
942 .iddig = 8,
943 .iddig_mux = 7,
944 .usb_shift = 0,
945 .usb_mask = 0x1ff,
946 .usb_bitmap = (0x1ff << 0),
947 .drvvbus = 8,
948 .txep_shift = 0,
949 .txep_mask = 0xffff,
950 .txep_bitmap = (0xffff << 0),
951 .rxep_shift = 16,
952 .rxep_mask = 0xfffe,
953 .rxep_bitmap = (0xfffe << 16),
954 .poll_timeout = 2000, /* ms */
955};
956
957static const struct of_device_id musb_dsps_of_match[] = {
958 { .compatible = "ti,musb-am33xx",
959 .data = &am33xx_driver_data, },
960 { .compatible = "ti,musb-dm816",
961 .data = &am33xx_driver_data, },
962 { },
963};
964MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
965
966#ifdef CONFIG_PM_SLEEP
967static int dsps_suspend(struct device *dev)
968{
969 struct dsps_glue *glue = dev_get_drvdata(dev);
970 const struct dsps_musb_wrapper *wrp = glue->wrp;
971 struct musb *musb = platform_get_drvdata(glue->musb);
972 void __iomem *mbase;
973 int ret;
974
975 if (!musb)
976 /* This can happen if the musb device is in -EPROBE_DEFER */
977 return 0;
978
979 ret = pm_runtime_get_sync(dev);
980 if (ret < 0) {
981 pm_runtime_put_noidle(dev);
982 return ret;
983 }
984
985 del_timer_sync(&musb->dev_timer);
986
987 mbase = musb->ctrl_base;
988 glue->context.control = musb_readl(mbase, wrp->control);
989 glue->context.epintr = musb_readl(mbase, wrp->epintr_set);
990 glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set);
991 glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi);
992 glue->context.mode = musb_readl(mbase, wrp->mode);
993 glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode);
994 glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode);
995
996 dsps_dma_controller_suspend(glue);
997
998 return 0;
999}
1000
1001static int dsps_resume(struct device *dev)
1002{
1003 struct dsps_glue *glue = dev_get_drvdata(dev);
1004 const struct dsps_musb_wrapper *wrp = glue->wrp;
1005 struct musb *musb = platform_get_drvdata(glue->musb);
1006 void __iomem *mbase;
1007
1008 if (!musb)
1009 return 0;
1010
1011 dsps_dma_controller_resume(glue);
1012
1013 mbase = musb->ctrl_base;
1014 musb_writel(mbase, wrp->control, glue->context.control);
1015 musb_writel(mbase, wrp->epintr_set, glue->context.epintr);
1016 musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
1017 musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
1018 musb_writel(mbase, wrp->mode, glue->context.mode);
1019 musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
1020 musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
1021 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
1022 musb->port_mode == MUSB_OTG)
1023 dsps_mod_timer(glue, -1);
1024
1025 pm_runtime_put(dev);
1026
1027 return 0;
1028}
1029#endif
1030
1031static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
1032
1033static struct platform_driver dsps_usbss_driver = {
1034 .probe = dsps_probe,
1035 .remove_new = dsps_remove,
1036 .driver = {
1037 .name = "musb-dsps",
1038 .pm = &dsps_pm_ops,
1039 .of_match_table = musb_dsps_of_match,
1040 },
1041};
1042
1043MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
1044MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
1045MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
1046MODULE_LICENSE("GPL v2");
1047
1048module_platform_driver(dsps_usbss_driver);
1/*
2 * Texas Instruments DSPS platforms "glue layer"
3 *
4 * Copyright (C) 2012, by Texas Instruments
5 *
6 * Based on the am35x "glue layer" code.
7 *
8 * This file is part of the Inventra Controller Driver for Linux.
9 *
10 * The Inventra Controller Driver for Linux is free software; you
11 * can redistribute it and/or modify it under the terms of the GNU
12 * General Public License version 2 as published by the Free Software
13 * Foundation.
14 *
15 * The Inventra Controller Driver for Linux is distributed in
16 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
17 * without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 * License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with The Inventra Controller Driver for Linux ; if not,
23 * write to the Free Software Foundation, Inc., 59 Temple Place,
24 * Suite 330, Boston, MA 02111-1307 USA
25 *
26 * musb_dsps.c will be a common file for all the TI DSPS platforms
27 * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
28 * For now only ti81x is using this and in future davinci.c, am35x.c
29 * da8xx.c would be merged to this file after testing.
30 */
31
32#include <linux/io.h>
33#include <linux/err.h>
34#include <linux/platform_device.h>
35#include <linux/dma-mapping.h>
36#include <linux/pm_runtime.h>
37#include <linux/module.h>
38#include <linux/usb/usb_phy_gen_xceiv.h>
39#include <linux/platform_data/usb-omap.h>
40#include <linux/sizes.h>
41
42#include <linux/of.h>
43#include <linux/of_device.h>
44#include <linux/of_address.h>
45#include <linux/of_irq.h>
46#include <linux/usb/of.h>
47
48#include <linux/debugfs.h>
49
50#include "musb_core.h"
51
52static const struct of_device_id musb_dsps_of_match[];
53
54/**
55 * avoid using musb_readx()/musb_writex() as glue layer should not be
56 * dependent on musb core layer symbols.
57 */
58static inline u8 dsps_readb(const void __iomem *addr, unsigned offset)
59 { return __raw_readb(addr + offset); }
60
61static inline u32 dsps_readl(const void __iomem *addr, unsigned offset)
62 { return __raw_readl(addr + offset); }
63
64static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data)
65 { __raw_writeb(data, addr + offset); }
66
67static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)
68 { __raw_writel(data, addr + offset); }
69
70/**
71 * DSPS musb wrapper register offset.
72 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
73 * musb ips.
74 */
75struct dsps_musb_wrapper {
76 u16 revision;
77 u16 control;
78 u16 status;
79 u16 epintr_set;
80 u16 epintr_clear;
81 u16 epintr_status;
82 u16 coreintr_set;
83 u16 coreintr_clear;
84 u16 coreintr_status;
85 u16 phy_utmi;
86 u16 mode;
87 u16 tx_mode;
88 u16 rx_mode;
89
90 /* bit positions for control */
91 unsigned reset:5;
92
93 /* bit positions for interrupt */
94 unsigned usb_shift:5;
95 u32 usb_mask;
96 u32 usb_bitmap;
97 unsigned drvvbus:5;
98
99 unsigned txep_shift:5;
100 u32 txep_mask;
101 u32 txep_bitmap;
102
103 unsigned rxep_shift:5;
104 u32 rxep_mask;
105 u32 rxep_bitmap;
106
107 /* bit positions for phy_utmi */
108 unsigned otg_disable:5;
109
110 /* bit positions for mode */
111 unsigned iddig:5;
112 unsigned iddig_mux:5;
113 /* miscellaneous stuff */
114 u8 poll_seconds;
115};
116
117/*
118 * register shadow for suspend
119 */
120struct dsps_context {
121 u32 control;
122 u32 epintr;
123 u32 coreintr;
124 u32 phy_utmi;
125 u32 mode;
126 u32 tx_mode;
127 u32 rx_mode;
128};
129
130/**
131 * DSPS glue structure.
132 */
133struct dsps_glue {
134 struct device *dev;
135 struct platform_device *musb; /* child musb pdev */
136 const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
137 struct timer_list timer; /* otg_workaround timer */
138 unsigned long last_timer; /* last timer data for each instance */
139
140 struct dsps_context context;
141 struct debugfs_regset32 regset;
142 struct dentry *dbgfs_root;
143};
144
145static const struct debugfs_reg32 dsps_musb_regs[] = {
146 { "revision", 0x00 },
147 { "control", 0x14 },
148 { "status", 0x18 },
149 { "eoi", 0x24 },
150 { "intr0_stat", 0x30 },
151 { "intr1_stat", 0x34 },
152 { "intr0_set", 0x38 },
153 { "intr1_set", 0x3c },
154 { "txmode", 0x70 },
155 { "rxmode", 0x74 },
156 { "autoreq", 0xd0 },
157 { "srpfixtime", 0xd4 },
158 { "tdown", 0xd8 },
159 { "phy_utmi", 0xe0 },
160 { "mode", 0xe8 },
161};
162
163static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout)
164{
165 struct device *dev = musb->controller;
166 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
167
168 if (timeout == 0)
169 timeout = jiffies + msecs_to_jiffies(3);
170
171 /* Never idle if active, or when VBUS timeout is not set as host */
172 if (musb->is_active || (musb->a_wait_bcon == 0 &&
173 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
174 dev_dbg(musb->controller, "%s active, deleting timer\n",
175 usb_otg_state_string(musb->xceiv->state));
176 del_timer(&glue->timer);
177 glue->last_timer = jiffies;
178 return;
179 }
180 if (musb->port_mode != MUSB_PORT_MODE_DUAL_ROLE)
181 return;
182
183 if (!musb->g.dev.driver)
184 return;
185
186 if (time_after(glue->last_timer, timeout) &&
187 timer_pending(&glue->timer)) {
188 dev_dbg(musb->controller,
189 "Longer idle timer already pending, ignoring...\n");
190 return;
191 }
192 glue->last_timer = timeout;
193
194 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
195 usb_otg_state_string(musb->xceiv->state),
196 jiffies_to_msecs(timeout - jiffies));
197 mod_timer(&glue->timer, timeout);
198}
199
200/**
201 * dsps_musb_enable - enable interrupts
202 */
203static void dsps_musb_enable(struct musb *musb)
204{
205 struct device *dev = musb->controller;
206 struct platform_device *pdev = to_platform_device(dev->parent);
207 struct dsps_glue *glue = platform_get_drvdata(pdev);
208 const struct dsps_musb_wrapper *wrp = glue->wrp;
209 void __iomem *reg_base = musb->ctrl_base;
210 u32 epmask, coremask;
211
212 /* Workaround: setup IRQs through both register sets. */
213 epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
214 ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
215 coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
216
217 dsps_writel(reg_base, wrp->epintr_set, epmask);
218 dsps_writel(reg_base, wrp->coreintr_set, coremask);
219 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
220 dsps_writel(reg_base, wrp->coreintr_set,
221 (1 << wrp->drvvbus) << wrp->usb_shift);
222 dsps_musb_try_idle(musb, 0);
223}
224
225/**
226 * dsps_musb_disable - disable HDRC and flush interrupts
227 */
228static void dsps_musb_disable(struct musb *musb)
229{
230 struct device *dev = musb->controller;
231 struct platform_device *pdev = to_platform_device(dev->parent);
232 struct dsps_glue *glue = platform_get_drvdata(pdev);
233 const struct dsps_musb_wrapper *wrp = glue->wrp;
234 void __iomem *reg_base = musb->ctrl_base;
235
236 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
237 dsps_writel(reg_base, wrp->epintr_clear,
238 wrp->txep_bitmap | wrp->rxep_bitmap);
239 dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
240}
241
242static void otg_timer(unsigned long _musb)
243{
244 struct musb *musb = (void *)_musb;
245 void __iomem *mregs = musb->mregs;
246 struct device *dev = musb->controller;
247 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
248 const struct dsps_musb_wrapper *wrp = glue->wrp;
249 u8 devctl;
250 unsigned long flags;
251 int skip_session = 0;
252
253 /*
254 * We poll because DSPS IP's won't expose several OTG-critical
255 * status change events (from the transceiver) otherwise.
256 */
257 devctl = dsps_readb(mregs, MUSB_DEVCTL);
258 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
259 usb_otg_state_string(musb->xceiv->state));
260
261 spin_lock_irqsave(&musb->lock, flags);
262 switch (musb->xceiv->state) {
263 case OTG_STATE_A_WAIT_BCON:
264 dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
265 skip_session = 1;
266 /* fall */
267
268 case OTG_STATE_A_IDLE:
269 case OTG_STATE_B_IDLE:
270 if (devctl & MUSB_DEVCTL_BDEVICE) {
271 musb->xceiv->state = OTG_STATE_B_IDLE;
272 MUSB_DEV_MODE(musb);
273 } else {
274 musb->xceiv->state = OTG_STATE_A_IDLE;
275 MUSB_HST_MODE(musb);
276 }
277 if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
278 dsps_writeb(mregs, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
279 mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
280 break;
281 case OTG_STATE_A_WAIT_VFALL:
282 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
283 dsps_writel(musb->ctrl_base, wrp->coreintr_set,
284 MUSB_INTR_VBUSERROR << wrp->usb_shift);
285 break;
286 default:
287 break;
288 }
289 spin_unlock_irqrestore(&musb->lock, flags);
290}
291
292static irqreturn_t dsps_interrupt(int irq, void *hci)
293{
294 struct musb *musb = hci;
295 void __iomem *reg_base = musb->ctrl_base;
296 struct device *dev = musb->controller;
297 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
298 const struct dsps_musb_wrapper *wrp = glue->wrp;
299 unsigned long flags;
300 irqreturn_t ret = IRQ_NONE;
301 u32 epintr, usbintr;
302
303 spin_lock_irqsave(&musb->lock, flags);
304
305 /* Get endpoint interrupts */
306 epintr = dsps_readl(reg_base, wrp->epintr_status);
307 musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
308 musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
309
310 if (epintr)
311 dsps_writel(reg_base, wrp->epintr_status, epintr);
312
313 /* Get usb core interrupts */
314 usbintr = dsps_readl(reg_base, wrp->coreintr_status);
315 if (!usbintr && !epintr)
316 goto out;
317
318 musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
319 if (usbintr)
320 dsps_writel(reg_base, wrp->coreintr_status, usbintr);
321
322 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
323 usbintr, epintr);
324 /*
325 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
326 * DSPS IP's missing ID change IRQ. We need an ID change IRQ to
327 * switch appropriately between halves of the OTG state machine.
328 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
329 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
330 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
331 */
332 if (is_host_active(musb) && usbintr & MUSB_INTR_BABBLE)
333 pr_info("CAUTION: musb: Babble Interrupt Occurred\n");
334
335 if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
336 int drvvbus = dsps_readl(reg_base, wrp->status);
337 void __iomem *mregs = musb->mregs;
338 u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);
339 int err;
340
341 err = musb->int_usb & MUSB_INTR_VBUSERROR;
342 if (err) {
343 /*
344 * The Mentor core doesn't debounce VBUS as needed
345 * to cope with device connect current spikes. This
346 * means it's not uncommon for bus-powered devices
347 * to get VBUS errors during enumeration.
348 *
349 * This is a workaround, but newer RTL from Mentor
350 * seems to allow a better one: "re"-starting sessions
351 * without waiting for VBUS to stop registering in
352 * devctl.
353 */
354 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
355 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
356 mod_timer(&glue->timer,
357 jiffies + wrp->poll_seconds * HZ);
358 WARNING("VBUS error workaround (delay coming)\n");
359 } else if (drvvbus) {
360 MUSB_HST_MODE(musb);
361 musb->xceiv->otg->default_a = 1;
362 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
363 del_timer(&glue->timer);
364 } else {
365 musb->is_active = 0;
366 MUSB_DEV_MODE(musb);
367 musb->xceiv->otg->default_a = 0;
368 musb->xceiv->state = OTG_STATE_B_IDLE;
369 }
370
371 /* NOTE: this must complete power-on within 100 ms. */
372 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
373 drvvbus ? "on" : "off",
374 usb_otg_state_string(musb->xceiv->state),
375 err ? " ERROR" : "",
376 devctl);
377 ret = IRQ_HANDLED;
378 }
379
380 if (musb->int_tx || musb->int_rx || musb->int_usb)
381 ret |= musb_interrupt(musb);
382
383 /* Poll for ID change in OTG port mode */
384 if (musb->xceiv->state == OTG_STATE_B_IDLE &&
385 musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
386 mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
387out:
388 spin_unlock_irqrestore(&musb->lock, flags);
389
390 return ret;
391}
392
393static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue)
394{
395 struct dentry *root;
396 struct dentry *file;
397 char buf[128];
398
399 sprintf(buf, "%s.dsps", dev_name(musb->controller));
400 root = debugfs_create_dir(buf, NULL);
401 if (!root)
402 return -ENOMEM;
403 glue->dbgfs_root = root;
404
405 glue->regset.regs = dsps_musb_regs;
406 glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs);
407 glue->regset.base = musb->ctrl_base;
408
409 file = debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset);
410 if (!file) {
411 debugfs_remove_recursive(root);
412 return -ENOMEM;
413 }
414 return 0;
415}
416
417static int dsps_musb_init(struct musb *musb)
418{
419 struct device *dev = musb->controller;
420 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
421 struct platform_device *parent = to_platform_device(dev->parent);
422 const struct dsps_musb_wrapper *wrp = glue->wrp;
423 void __iomem *reg_base;
424 struct resource *r;
425 u32 rev, val;
426 int ret;
427
428 r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
429 if (!r)
430 return -EINVAL;
431
432 reg_base = devm_ioremap_resource(dev, r);
433 if (IS_ERR(reg_base))
434 return PTR_ERR(reg_base);
435 musb->ctrl_base = reg_base;
436
437 /* NOP driver needs change if supporting dual instance */
438 musb->xceiv = devm_usb_get_phy_by_phandle(dev, "phys", 0);
439 if (IS_ERR(musb->xceiv))
440 return PTR_ERR(musb->xceiv);
441
442 /* Returns zero if e.g. not clocked */
443 rev = dsps_readl(reg_base, wrp->revision);
444 if (!rev)
445 return -ENODEV;
446
447 usb_phy_init(musb->xceiv);
448 setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
449
450 /* Reset the musb */
451 dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
452
453 musb->isr = dsps_interrupt;
454
455 /* reset the otgdisable bit, needed for host mode to work */
456 val = dsps_readl(reg_base, wrp->phy_utmi);
457 val &= ~(1 << wrp->otg_disable);
458 dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
459
460 ret = dsps_musb_dbg_init(musb, glue);
461 if (ret)
462 return ret;
463
464 return 0;
465}
466
467static int dsps_musb_exit(struct musb *musb)
468{
469 struct device *dev = musb->controller;
470 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
471
472 del_timer_sync(&glue->timer);
473 usb_phy_shutdown(musb->xceiv);
474 debugfs_remove_recursive(glue->dbgfs_root);
475
476 return 0;
477}
478
479static int dsps_musb_set_mode(struct musb *musb, u8 mode)
480{
481 struct device *dev = musb->controller;
482 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
483 const struct dsps_musb_wrapper *wrp = glue->wrp;
484 void __iomem *ctrl_base = musb->ctrl_base;
485 void __iomem *base = musb->mregs;
486 u32 reg;
487
488 reg = dsps_readl(base, wrp->mode);
489
490 switch (mode) {
491 case MUSB_HOST:
492 reg &= ~(1 << wrp->iddig);
493
494 /*
495 * if we're setting mode to host-only or device-only, we're
496 * going to ignore whatever the PHY sends us and just force
497 * ID pin status by SW
498 */
499 reg |= (1 << wrp->iddig_mux);
500
501 dsps_writel(base, wrp->mode, reg);
502 dsps_writel(ctrl_base, wrp->phy_utmi, 0x02);
503 break;
504 case MUSB_PERIPHERAL:
505 reg |= (1 << wrp->iddig);
506
507 /*
508 * if we're setting mode to host-only or device-only, we're
509 * going to ignore whatever the PHY sends us and just force
510 * ID pin status by SW
511 */
512 reg |= (1 << wrp->iddig_mux);
513
514 dsps_writel(base, wrp->mode, reg);
515 break;
516 case MUSB_OTG:
517 dsps_writel(base, wrp->phy_utmi, 0x02);
518 break;
519 default:
520 dev_err(glue->dev, "unsupported mode %d\n", mode);
521 return -EINVAL;
522 }
523
524 return 0;
525}
526
527static struct musb_platform_ops dsps_ops = {
528 .init = dsps_musb_init,
529 .exit = dsps_musb_exit,
530
531 .enable = dsps_musb_enable,
532 .disable = dsps_musb_disable,
533
534 .try_idle = dsps_musb_try_idle,
535 .set_mode = dsps_musb_set_mode,
536};
537
538static u64 musb_dmamask = DMA_BIT_MASK(32);
539
540static int get_int_prop(struct device_node *dn, const char *s)
541{
542 int ret;
543 u32 val;
544
545 ret = of_property_read_u32(dn, s, &val);
546 if (ret)
547 return 0;
548 return val;
549}
550
551static int get_musb_port_mode(struct device *dev)
552{
553 enum usb_dr_mode mode;
554
555 mode = of_usb_get_dr_mode(dev->of_node);
556 switch (mode) {
557 case USB_DR_MODE_HOST:
558 return MUSB_PORT_MODE_HOST;
559
560 case USB_DR_MODE_PERIPHERAL:
561 return MUSB_PORT_MODE_GADGET;
562
563 case USB_DR_MODE_UNKNOWN:
564 case USB_DR_MODE_OTG:
565 default:
566 return MUSB_PORT_MODE_DUAL_ROLE;
567 }
568}
569
570static int dsps_create_musb_pdev(struct dsps_glue *glue,
571 struct platform_device *parent)
572{
573 struct musb_hdrc_platform_data pdata;
574 struct resource resources[2];
575 struct resource *res;
576 struct device *dev = &parent->dev;
577 struct musb_hdrc_config *config;
578 struct platform_device *musb;
579 struct device_node *dn = parent->dev.of_node;
580 int ret;
581
582 memset(resources, 0, sizeof(resources));
583 res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc");
584 if (!res) {
585 dev_err(dev, "failed to get memory.\n");
586 return -EINVAL;
587 }
588 resources[0] = *res;
589
590 res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc");
591 if (!res) {
592 dev_err(dev, "failed to get irq.\n");
593 return -EINVAL;
594 }
595 resources[1] = *res;
596
597 /* allocate the child platform device */
598 musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
599 if (!musb) {
600 dev_err(dev, "failed to allocate musb device\n");
601 return -ENOMEM;
602 }
603
604 musb->dev.parent = dev;
605 musb->dev.dma_mask = &musb_dmamask;
606 musb->dev.coherent_dma_mask = musb_dmamask;
607 musb->dev.of_node = of_node_get(dn);
608
609 glue->musb = musb;
610
611 ret = platform_device_add_resources(musb, resources,
612 ARRAY_SIZE(resources));
613 if (ret) {
614 dev_err(dev, "failed to add resources\n");
615 goto err;
616 }
617
618 config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL);
619 if (!config) {
620 dev_err(dev, "failed to allocate musb hdrc config\n");
621 ret = -ENOMEM;
622 goto err;
623 }
624 pdata.config = config;
625 pdata.platform_ops = &dsps_ops;
626
627 config->num_eps = get_int_prop(dn, "mentor,num-eps");
628 config->ram_bits = get_int_prop(dn, "mentor,ram-bits");
629 config->host_port_deassert_reset_at_resume = 1;
630 pdata.mode = get_musb_port_mode(dev);
631 /* DT keeps this entry in mA, musb expects it as per USB spec */
632 pdata.power = get_int_prop(dn, "mentor,power") / 2;
633 config->multipoint = of_property_read_bool(dn, "mentor,multipoint");
634
635 ret = platform_device_add_data(musb, &pdata, sizeof(pdata));
636 if (ret) {
637 dev_err(dev, "failed to add platform_data\n");
638 goto err;
639 }
640
641 ret = platform_device_add(musb);
642 if (ret) {
643 dev_err(dev, "failed to register musb device\n");
644 goto err;
645 }
646 return 0;
647
648err:
649 platform_device_put(musb);
650 return ret;
651}
652
653static int dsps_probe(struct platform_device *pdev)
654{
655 const struct of_device_id *match;
656 const struct dsps_musb_wrapper *wrp;
657 struct dsps_glue *glue;
658 int ret;
659
660 if (!strcmp(pdev->name, "musb-hdrc"))
661 return -ENODEV;
662
663 match = of_match_node(musb_dsps_of_match, pdev->dev.of_node);
664 if (!match) {
665 dev_err(&pdev->dev, "fail to get matching of_match struct\n");
666 return -EINVAL;
667 }
668 wrp = match->data;
669
670 /* allocate glue */
671 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
672 if (!glue) {
673 dev_err(&pdev->dev, "unable to allocate glue memory\n");
674 return -ENOMEM;
675 }
676
677 glue->dev = &pdev->dev;
678 glue->wrp = wrp;
679
680 platform_set_drvdata(pdev, glue);
681 pm_runtime_enable(&pdev->dev);
682
683 ret = pm_runtime_get_sync(&pdev->dev);
684 if (ret < 0) {
685 dev_err(&pdev->dev, "pm_runtime_get_sync FAILED");
686 goto err2;
687 }
688
689 ret = dsps_create_musb_pdev(glue, pdev);
690 if (ret)
691 goto err3;
692
693 return 0;
694
695err3:
696 pm_runtime_put(&pdev->dev);
697err2:
698 pm_runtime_disable(&pdev->dev);
699 return ret;
700}
701
702static int dsps_remove(struct platform_device *pdev)
703{
704 struct dsps_glue *glue = platform_get_drvdata(pdev);
705
706 platform_device_unregister(glue->musb);
707
708 /* disable usbss clocks */
709 pm_runtime_put(&pdev->dev);
710 pm_runtime_disable(&pdev->dev);
711
712 return 0;
713}
714
715static const struct dsps_musb_wrapper am33xx_driver_data = {
716 .revision = 0x00,
717 .control = 0x14,
718 .status = 0x18,
719 .epintr_set = 0x38,
720 .epintr_clear = 0x40,
721 .epintr_status = 0x30,
722 .coreintr_set = 0x3c,
723 .coreintr_clear = 0x44,
724 .coreintr_status = 0x34,
725 .phy_utmi = 0xe0,
726 .mode = 0xe8,
727 .tx_mode = 0x70,
728 .rx_mode = 0x74,
729 .reset = 0,
730 .otg_disable = 21,
731 .iddig = 8,
732 .iddig_mux = 7,
733 .usb_shift = 0,
734 .usb_mask = 0x1ff,
735 .usb_bitmap = (0x1ff << 0),
736 .drvvbus = 8,
737 .txep_shift = 0,
738 .txep_mask = 0xffff,
739 .txep_bitmap = (0xffff << 0),
740 .rxep_shift = 16,
741 .rxep_mask = 0xfffe,
742 .rxep_bitmap = (0xfffe << 16),
743 .poll_seconds = 2,
744};
745
746static const struct of_device_id musb_dsps_of_match[] = {
747 { .compatible = "ti,musb-am33xx",
748 .data = (void *) &am33xx_driver_data, },
749 { },
750};
751MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
752
753#ifdef CONFIG_PM
754static int dsps_suspend(struct device *dev)
755{
756 struct dsps_glue *glue = dev_get_drvdata(dev);
757 const struct dsps_musb_wrapper *wrp = glue->wrp;
758 struct musb *musb = platform_get_drvdata(glue->musb);
759 void __iomem *mbase = musb->ctrl_base;
760
761 glue->context.control = dsps_readl(mbase, wrp->control);
762 glue->context.epintr = dsps_readl(mbase, wrp->epintr_set);
763 glue->context.coreintr = dsps_readl(mbase, wrp->coreintr_set);
764 glue->context.phy_utmi = dsps_readl(mbase, wrp->phy_utmi);
765 glue->context.mode = dsps_readl(mbase, wrp->mode);
766 glue->context.tx_mode = dsps_readl(mbase, wrp->tx_mode);
767 glue->context.rx_mode = dsps_readl(mbase, wrp->rx_mode);
768
769 return 0;
770}
771
772static int dsps_resume(struct device *dev)
773{
774 struct dsps_glue *glue = dev_get_drvdata(dev);
775 const struct dsps_musb_wrapper *wrp = glue->wrp;
776 struct musb *musb = platform_get_drvdata(glue->musb);
777 void __iomem *mbase = musb->ctrl_base;
778
779 dsps_writel(mbase, wrp->control, glue->context.control);
780 dsps_writel(mbase, wrp->epintr_set, glue->context.epintr);
781 dsps_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
782 dsps_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
783 dsps_writel(mbase, wrp->mode, glue->context.mode);
784 dsps_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
785 dsps_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
786
787 return 0;
788}
789#endif
790
791static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
792
793static struct platform_driver dsps_usbss_driver = {
794 .probe = dsps_probe,
795 .remove = dsps_remove,
796 .driver = {
797 .name = "musb-dsps",
798 .pm = &dsps_pm_ops,
799 .of_match_table = musb_dsps_of_match,
800 },
801};
802
803MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
804MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
805MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
806MODULE_LICENSE("GPL v2");
807
808module_platform_driver(dsps_usbss_driver);