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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/mfd/atmel-hlcdc.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pwm.h>
16#include <linux/regmap.h>
17
18#define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8)
19#define ATMEL_HLCDC_PWMCVAL(x) (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
20#define ATMEL_HLCDC_PWMPOL BIT(4)
21#define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0)
22#define ATMEL_HLCDC_PWMPS_MAX 0x6
23#define ATMEL_HLCDC_PWMPS(x) ((x) & ATMEL_HLCDC_PWMPS_MASK)
24
25struct atmel_hlcdc_pwm_errata {
26 bool slow_clk_erratum;
27 bool div1_clk_erratum;
28};
29
30struct atmel_hlcdc_pwm {
31 struct pwm_chip chip;
32 struct atmel_hlcdc *hlcdc;
33 struct clk *cur_clk;
34 const struct atmel_hlcdc_pwm_errata *errata;
35};
36
37static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
38{
39 return container_of(chip, struct atmel_hlcdc_pwm, chip);
40}
41
42static int atmel_hlcdc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
43 const struct pwm_state *state)
44{
45 struct atmel_hlcdc_pwm *atmel = to_atmel_hlcdc_pwm(chip);
46 struct atmel_hlcdc *hlcdc = atmel->hlcdc;
47 unsigned int status;
48 int ret;
49
50 if (state->enabled) {
51 struct clk *new_clk = hlcdc->slow_clk;
52 u64 pwmcval = state->duty_cycle * 256;
53 unsigned long clk_freq;
54 u64 clk_period_ns;
55 u32 pwmcfg;
56 int pres;
57
58 if (!atmel->errata || !atmel->errata->slow_clk_erratum) {
59 clk_freq = clk_get_rate(new_clk);
60 if (!clk_freq)
61 return -EINVAL;
62
63 clk_period_ns = (u64)NSEC_PER_SEC * 256;
64 do_div(clk_period_ns, clk_freq);
65 }
66
67 /* Errata: cannot use slow clk on some IP revisions */
68 if ((atmel->errata && atmel->errata->slow_clk_erratum) ||
69 clk_period_ns > state->period) {
70 new_clk = hlcdc->sys_clk;
71 clk_freq = clk_get_rate(new_clk);
72 if (!clk_freq)
73 return -EINVAL;
74
75 clk_period_ns = (u64)NSEC_PER_SEC * 256;
76 do_div(clk_period_ns, clk_freq);
77 }
78
79 for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
80 /* Errata: cannot divide by 1 on some IP revisions */
81 if (!pres && atmel->errata &&
82 atmel->errata->div1_clk_erratum)
83 continue;
84
85 if ((clk_period_ns << pres) >= state->period)
86 break;
87 }
88
89 if (pres > ATMEL_HLCDC_PWMPS_MAX)
90 return -EINVAL;
91
92 pwmcfg = ATMEL_HLCDC_PWMPS(pres);
93
94 if (new_clk != atmel->cur_clk) {
95 u32 gencfg = 0;
96 int ret;
97
98 ret = clk_prepare_enable(new_clk);
99 if (ret)
100 return ret;
101
102 clk_disable_unprepare(atmel->cur_clk);
103 atmel->cur_clk = new_clk;
104
105 if (new_clk == hlcdc->sys_clk)
106 gencfg = ATMEL_HLCDC_CLKPWMSEL;
107
108 ret = regmap_update_bits(hlcdc->regmap,
109 ATMEL_HLCDC_CFG(0),
110 ATMEL_HLCDC_CLKPWMSEL,
111 gencfg);
112 if (ret)
113 return ret;
114 }
115
116 do_div(pwmcval, state->period);
117
118 /*
119 * The PWM duty cycle is configurable from 0/256 to 255/256 of
120 * the period cycle. Hence we can't set a duty cycle occupying
121 * the whole period cycle if we're asked to.
122 * Set it to 255 if pwmcval is greater than 256.
123 */
124 if (pwmcval > 255)
125 pwmcval = 255;
126
127 pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
128
129 if (state->polarity == PWM_POLARITY_NORMAL)
130 pwmcfg |= ATMEL_HLCDC_PWMPOL;
131
132 ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
133 ATMEL_HLCDC_PWMCVAL_MASK |
134 ATMEL_HLCDC_PWMPS_MASK |
135 ATMEL_HLCDC_PWMPOL,
136 pwmcfg);
137 if (ret)
138 return ret;
139
140 ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN,
141 ATMEL_HLCDC_PWM);
142 if (ret)
143 return ret;
144
145 ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
146 status,
147 status & ATMEL_HLCDC_PWM,
148 10, 0);
149 if (ret)
150 return ret;
151 } else {
152 ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS,
153 ATMEL_HLCDC_PWM);
154 if (ret)
155 return ret;
156
157 ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
158 status,
159 !(status & ATMEL_HLCDC_PWM),
160 10, 0);
161 if (ret)
162 return ret;
163
164 clk_disable_unprepare(atmel->cur_clk);
165 atmel->cur_clk = NULL;
166 }
167
168 return 0;
169}
170
171static const struct pwm_ops atmel_hlcdc_pwm_ops = {
172 .apply = atmel_hlcdc_pwm_apply,
173};
174
175static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
176 .slow_clk_erratum = true,
177};
178
179static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
180 .div1_clk_erratum = true,
181};
182
183static int atmel_hlcdc_pwm_suspend(struct device *dev)
184{
185 struct atmel_hlcdc_pwm *atmel = dev_get_drvdata(dev);
186
187 /* Keep the periph clock enabled if the PWM is still running. */
188 if (pwm_is_enabled(&atmel->chip.pwms[0]))
189 clk_disable_unprepare(atmel->hlcdc->periph_clk);
190
191 return 0;
192}
193
194static int atmel_hlcdc_pwm_resume(struct device *dev)
195{
196 struct atmel_hlcdc_pwm *atmel = dev_get_drvdata(dev);
197 struct pwm_state state;
198 int ret;
199
200 pwm_get_state(&atmel->chip.pwms[0], &state);
201
202 /* Re-enable the periph clock it was stopped during suspend. */
203 if (!state.enabled) {
204 ret = clk_prepare_enable(atmel->hlcdc->periph_clk);
205 if (ret)
206 return ret;
207 }
208
209 return atmel_hlcdc_pwm_apply(&atmel->chip, &atmel->chip.pwms[0],
210 &state);
211}
212
213static DEFINE_SIMPLE_DEV_PM_OPS(atmel_hlcdc_pwm_pm_ops,
214 atmel_hlcdc_pwm_suspend, atmel_hlcdc_pwm_resume);
215
216static const struct of_device_id atmel_hlcdc_dt_ids[] = {
217 {
218 .compatible = "atmel,at91sam9n12-hlcdc",
219 /* 9n12 has same errata as 9x5 HLCDC PWM */
220 .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
221 },
222 {
223 .compatible = "atmel,at91sam9x5-hlcdc",
224 .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
225 },
226 {
227 .compatible = "atmel,sama5d2-hlcdc",
228 },
229 {
230 .compatible = "atmel,sama5d3-hlcdc",
231 .data = &atmel_hlcdc_pwm_sama5d3_errata,
232 },
233 {
234 .compatible = "atmel,sama5d4-hlcdc",
235 .data = &atmel_hlcdc_pwm_sama5d3_errata,
236 },
237 { .compatible = "microchip,sam9x60-hlcdc", },
238 { /* sentinel */ },
239};
240MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids);
241
242static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
243{
244 const struct of_device_id *match;
245 struct device *dev = &pdev->dev;
246 struct atmel_hlcdc_pwm *atmel;
247 struct atmel_hlcdc *hlcdc;
248 int ret;
249
250 hlcdc = dev_get_drvdata(dev->parent);
251
252 atmel = devm_kzalloc(dev, sizeof(*atmel), GFP_KERNEL);
253 if (!atmel)
254 return -ENOMEM;
255
256 ret = clk_prepare_enable(hlcdc->periph_clk);
257 if (ret)
258 return ret;
259
260 match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
261 if (match)
262 atmel->errata = match->data;
263
264 atmel->hlcdc = hlcdc;
265 atmel->chip.ops = &atmel_hlcdc_pwm_ops;
266 atmel->chip.dev = dev;
267 atmel->chip.npwm = 1;
268
269 ret = pwmchip_add(&atmel->chip);
270 if (ret) {
271 clk_disable_unprepare(hlcdc->periph_clk);
272 return ret;
273 }
274
275 platform_set_drvdata(pdev, atmel);
276
277 return 0;
278}
279
280static void atmel_hlcdc_pwm_remove(struct platform_device *pdev)
281{
282 struct atmel_hlcdc_pwm *atmel = platform_get_drvdata(pdev);
283
284 pwmchip_remove(&atmel->chip);
285
286 clk_disable_unprepare(atmel->hlcdc->periph_clk);
287}
288
289static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
290 { .compatible = "atmel,hlcdc-pwm" },
291 { /* sentinel */ },
292};
293
294static struct platform_driver atmel_hlcdc_pwm_driver = {
295 .driver = {
296 .name = "atmel-hlcdc-pwm",
297 .of_match_table = atmel_hlcdc_pwm_dt_ids,
298 .pm = pm_ptr(&atmel_hlcdc_pwm_pm_ops),
299 },
300 .probe = atmel_hlcdc_pwm_probe,
301 .remove_new = atmel_hlcdc_pwm_remove,
302};
303module_platform_driver(atmel_hlcdc_pwm_driver);
304
305MODULE_ALIAS("platform:atmel-hlcdc-pwm");
306MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
307MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
308MODULE_LICENSE("GPL v2");