Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/mfd/atmel-hlcdc.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pwm.h>
16#include <linux/regmap.h>
17
18#define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8)
19#define ATMEL_HLCDC_PWMCVAL(x) (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
20#define ATMEL_HLCDC_PWMPOL BIT(4)
21#define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0)
22#define ATMEL_HLCDC_PWMPS_MAX 0x6
23#define ATMEL_HLCDC_PWMPS(x) ((x) & ATMEL_HLCDC_PWMPS_MASK)
24
25struct atmel_hlcdc_pwm_errata {
26 bool slow_clk_erratum;
27 bool div1_clk_erratum;
28};
29
30struct atmel_hlcdc_pwm {
31 struct pwm_chip chip;
32 struct atmel_hlcdc *hlcdc;
33 struct clk *cur_clk;
34 const struct atmel_hlcdc_pwm_errata *errata;
35};
36
37static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
38{
39 return container_of(chip, struct atmel_hlcdc_pwm, chip);
40}
41
42static int atmel_hlcdc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
43 const struct pwm_state *state)
44{
45 struct atmel_hlcdc_pwm *atmel = to_atmel_hlcdc_pwm(chip);
46 struct atmel_hlcdc *hlcdc = atmel->hlcdc;
47 unsigned int status;
48 int ret;
49
50 if (state->enabled) {
51 struct clk *new_clk = hlcdc->slow_clk;
52 u64 pwmcval = state->duty_cycle * 256;
53 unsigned long clk_freq;
54 u64 clk_period_ns;
55 u32 pwmcfg;
56 int pres;
57
58 if (!atmel->errata || !atmel->errata->slow_clk_erratum) {
59 clk_freq = clk_get_rate(new_clk);
60 if (!clk_freq)
61 return -EINVAL;
62
63 clk_period_ns = (u64)NSEC_PER_SEC * 256;
64 do_div(clk_period_ns, clk_freq);
65 }
66
67 /* Errata: cannot use slow clk on some IP revisions */
68 if ((atmel->errata && atmel->errata->slow_clk_erratum) ||
69 clk_period_ns > state->period) {
70 new_clk = hlcdc->sys_clk;
71 clk_freq = clk_get_rate(new_clk);
72 if (!clk_freq)
73 return -EINVAL;
74
75 clk_period_ns = (u64)NSEC_PER_SEC * 256;
76 do_div(clk_period_ns, clk_freq);
77 }
78
79 for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
80 /* Errata: cannot divide by 1 on some IP revisions */
81 if (!pres && atmel->errata &&
82 atmel->errata->div1_clk_erratum)
83 continue;
84
85 if ((clk_period_ns << pres) >= state->period)
86 break;
87 }
88
89 if (pres > ATMEL_HLCDC_PWMPS_MAX)
90 return -EINVAL;
91
92 pwmcfg = ATMEL_HLCDC_PWMPS(pres);
93
94 if (new_clk != atmel->cur_clk) {
95 u32 gencfg = 0;
96 int ret;
97
98 ret = clk_prepare_enable(new_clk);
99 if (ret)
100 return ret;
101
102 clk_disable_unprepare(atmel->cur_clk);
103 atmel->cur_clk = new_clk;
104
105 if (new_clk == hlcdc->sys_clk)
106 gencfg = ATMEL_HLCDC_CLKPWMSEL;
107
108 ret = regmap_update_bits(hlcdc->regmap,
109 ATMEL_HLCDC_CFG(0),
110 ATMEL_HLCDC_CLKPWMSEL,
111 gencfg);
112 if (ret)
113 return ret;
114 }
115
116 do_div(pwmcval, state->period);
117
118 /*
119 * The PWM duty cycle is configurable from 0/256 to 255/256 of
120 * the period cycle. Hence we can't set a duty cycle occupying
121 * the whole period cycle if we're asked to.
122 * Set it to 255 if pwmcval is greater than 256.
123 */
124 if (pwmcval > 255)
125 pwmcval = 255;
126
127 pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
128
129 if (state->polarity == PWM_POLARITY_NORMAL)
130 pwmcfg |= ATMEL_HLCDC_PWMPOL;
131
132 ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
133 ATMEL_HLCDC_PWMCVAL_MASK |
134 ATMEL_HLCDC_PWMPS_MASK |
135 ATMEL_HLCDC_PWMPOL,
136 pwmcfg);
137 if (ret)
138 return ret;
139
140 ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN,
141 ATMEL_HLCDC_PWM);
142 if (ret)
143 return ret;
144
145 ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
146 status,
147 status & ATMEL_HLCDC_PWM,
148 10, 0);
149 if (ret)
150 return ret;
151 } else {
152 ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS,
153 ATMEL_HLCDC_PWM);
154 if (ret)
155 return ret;
156
157 ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
158 status,
159 !(status & ATMEL_HLCDC_PWM),
160 10, 0);
161 if (ret)
162 return ret;
163
164 clk_disable_unprepare(atmel->cur_clk);
165 atmel->cur_clk = NULL;
166 }
167
168 return 0;
169}
170
171static const struct pwm_ops atmel_hlcdc_pwm_ops = {
172 .apply = atmel_hlcdc_pwm_apply,
173};
174
175static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
176 .slow_clk_erratum = true,
177};
178
179static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
180 .div1_clk_erratum = true,
181};
182
183static int atmel_hlcdc_pwm_suspend(struct device *dev)
184{
185 struct atmel_hlcdc_pwm *atmel = dev_get_drvdata(dev);
186
187 /* Keep the periph clock enabled if the PWM is still running. */
188 if (pwm_is_enabled(&atmel->chip.pwms[0]))
189 clk_disable_unprepare(atmel->hlcdc->periph_clk);
190
191 return 0;
192}
193
194static int atmel_hlcdc_pwm_resume(struct device *dev)
195{
196 struct atmel_hlcdc_pwm *atmel = dev_get_drvdata(dev);
197 struct pwm_state state;
198 int ret;
199
200 pwm_get_state(&atmel->chip.pwms[0], &state);
201
202 /* Re-enable the periph clock it was stopped during suspend. */
203 if (!state.enabled) {
204 ret = clk_prepare_enable(atmel->hlcdc->periph_clk);
205 if (ret)
206 return ret;
207 }
208
209 return atmel_hlcdc_pwm_apply(&atmel->chip, &atmel->chip.pwms[0],
210 &state);
211}
212
213static DEFINE_SIMPLE_DEV_PM_OPS(atmel_hlcdc_pwm_pm_ops,
214 atmel_hlcdc_pwm_suspend, atmel_hlcdc_pwm_resume);
215
216static const struct of_device_id atmel_hlcdc_dt_ids[] = {
217 {
218 .compatible = "atmel,at91sam9n12-hlcdc",
219 /* 9n12 has same errata as 9x5 HLCDC PWM */
220 .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
221 },
222 {
223 .compatible = "atmel,at91sam9x5-hlcdc",
224 .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
225 },
226 {
227 .compatible = "atmel,sama5d2-hlcdc",
228 },
229 {
230 .compatible = "atmel,sama5d3-hlcdc",
231 .data = &atmel_hlcdc_pwm_sama5d3_errata,
232 },
233 {
234 .compatible = "atmel,sama5d4-hlcdc",
235 .data = &atmel_hlcdc_pwm_sama5d3_errata,
236 },
237 { .compatible = "microchip,sam9x60-hlcdc", },
238 { /* sentinel */ },
239};
240MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids);
241
242static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
243{
244 const struct of_device_id *match;
245 struct device *dev = &pdev->dev;
246 struct atmel_hlcdc_pwm *atmel;
247 struct atmel_hlcdc *hlcdc;
248 int ret;
249
250 hlcdc = dev_get_drvdata(dev->parent);
251
252 atmel = devm_kzalloc(dev, sizeof(*atmel), GFP_KERNEL);
253 if (!atmel)
254 return -ENOMEM;
255
256 ret = clk_prepare_enable(hlcdc->periph_clk);
257 if (ret)
258 return ret;
259
260 match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
261 if (match)
262 atmel->errata = match->data;
263
264 atmel->hlcdc = hlcdc;
265 atmel->chip.ops = &atmel_hlcdc_pwm_ops;
266 atmel->chip.dev = dev;
267 atmel->chip.npwm = 1;
268
269 ret = pwmchip_add(&atmel->chip);
270 if (ret) {
271 clk_disable_unprepare(hlcdc->periph_clk);
272 return ret;
273 }
274
275 platform_set_drvdata(pdev, atmel);
276
277 return 0;
278}
279
280static void atmel_hlcdc_pwm_remove(struct platform_device *pdev)
281{
282 struct atmel_hlcdc_pwm *atmel = platform_get_drvdata(pdev);
283
284 pwmchip_remove(&atmel->chip);
285
286 clk_disable_unprepare(atmel->hlcdc->periph_clk);
287}
288
289static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
290 { .compatible = "atmel,hlcdc-pwm" },
291 { /* sentinel */ },
292};
293
294static struct platform_driver atmel_hlcdc_pwm_driver = {
295 .driver = {
296 .name = "atmel-hlcdc-pwm",
297 .of_match_table = atmel_hlcdc_pwm_dt_ids,
298 .pm = pm_ptr(&atmel_hlcdc_pwm_pm_ops),
299 },
300 .probe = atmel_hlcdc_pwm_probe,
301 .remove_new = atmel_hlcdc_pwm_remove,
302};
303module_platform_driver(atmel_hlcdc_pwm_driver);
304
305MODULE_ALIAS("platform:atmel-hlcdc-pwm");
306MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
307MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
308MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2014 Free Electrons
3 * Copyright (C) 2014 Atmel
4 *
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/mfd/atmel-hlcdc.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/pwm.h>
26#include <linux/regmap.h>
27
28#define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8)
29#define ATMEL_HLCDC_PWMCVAL(x) (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
30#define ATMEL_HLCDC_PWMPOL BIT(4)
31#define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0)
32#define ATMEL_HLCDC_PWMPS_MAX 0x6
33#define ATMEL_HLCDC_PWMPS(x) ((x) & ATMEL_HLCDC_PWMPS_MASK)
34
35struct atmel_hlcdc_pwm_errata {
36 bool slow_clk_erratum;
37 bool div1_clk_erratum;
38};
39
40struct atmel_hlcdc_pwm {
41 struct pwm_chip chip;
42 struct atmel_hlcdc *hlcdc;
43 struct clk *cur_clk;
44 const struct atmel_hlcdc_pwm_errata *errata;
45};
46
47static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
48{
49 return container_of(chip, struct atmel_hlcdc_pwm, chip);
50}
51
52static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
53 struct pwm_device *pwm,
54 int duty_ns, int period_ns)
55{
56 struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
57 struct atmel_hlcdc *hlcdc = chip->hlcdc;
58 struct clk *new_clk = hlcdc->slow_clk;
59 u64 pwmcval = duty_ns * 256;
60 unsigned long clk_freq;
61 u64 clk_period_ns;
62 u32 pwmcfg;
63 int pres;
64
65 if (!chip->errata || !chip->errata->slow_clk_erratum) {
66 clk_freq = clk_get_rate(new_clk);
67 if (!clk_freq)
68 return -EINVAL;
69
70 clk_period_ns = (u64)NSEC_PER_SEC * 256;
71 do_div(clk_period_ns, clk_freq);
72 }
73
74 /* Errata: cannot use slow clk on some IP revisions */
75 if ((chip->errata && chip->errata->slow_clk_erratum) ||
76 clk_period_ns > period_ns) {
77 new_clk = hlcdc->sys_clk;
78 clk_freq = clk_get_rate(new_clk);
79 if (!clk_freq)
80 return -EINVAL;
81
82 clk_period_ns = (u64)NSEC_PER_SEC * 256;
83 do_div(clk_period_ns, clk_freq);
84 }
85
86 for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
87 /* Errata: cannot divide by 1 on some IP revisions */
88 if (!pres && chip->errata && chip->errata->div1_clk_erratum)
89 continue;
90
91 if ((clk_period_ns << pres) >= period_ns)
92 break;
93 }
94
95 if (pres > ATMEL_HLCDC_PWMPS_MAX)
96 return -EINVAL;
97
98 pwmcfg = ATMEL_HLCDC_PWMPS(pres);
99
100 if (new_clk != chip->cur_clk) {
101 u32 gencfg = 0;
102 int ret;
103
104 ret = clk_prepare_enable(new_clk);
105 if (ret)
106 return ret;
107
108 clk_disable_unprepare(chip->cur_clk);
109 chip->cur_clk = new_clk;
110
111 if (new_clk == hlcdc->sys_clk)
112 gencfg = ATMEL_HLCDC_CLKPWMSEL;
113
114 ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(0),
115 ATMEL_HLCDC_CLKPWMSEL, gencfg);
116 if (ret)
117 return ret;
118 }
119
120 do_div(pwmcval, period_ns);
121
122 /*
123 * The PWM duty cycle is configurable from 0/256 to 255/256 of the
124 * period cycle. Hence we can't set a duty cycle occupying the
125 * whole period cycle if we're asked to.
126 * Set it to 255 if pwmcval is greater than 256.
127 */
128 if (pwmcval > 255)
129 pwmcval = 255;
130
131 pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
132
133 return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
134 ATMEL_HLCDC_PWMCVAL_MASK |
135 ATMEL_HLCDC_PWMPS_MASK,
136 pwmcfg);
137}
138
139static int atmel_hlcdc_pwm_set_polarity(struct pwm_chip *c,
140 struct pwm_device *pwm,
141 enum pwm_polarity polarity)
142{
143 struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
144 struct atmel_hlcdc *hlcdc = chip->hlcdc;
145 u32 cfg = 0;
146
147 if (polarity == PWM_POLARITY_NORMAL)
148 cfg = ATMEL_HLCDC_PWMPOL;
149
150 return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
151 ATMEL_HLCDC_PWMPOL, cfg);
152}
153
154static int atmel_hlcdc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
155{
156 struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
157 struct atmel_hlcdc *hlcdc = chip->hlcdc;
158 u32 status;
159 int ret;
160
161 ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PWM);
162 if (ret)
163 return ret;
164
165 while (true) {
166 ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
167 if (ret)
168 return ret;
169
170 if ((status & ATMEL_HLCDC_PWM) != 0)
171 break;
172
173 usleep_range(1, 10);
174 }
175
176 return 0;
177}
178
179static void atmel_hlcdc_pwm_disable(struct pwm_chip *c,
180 struct pwm_device *pwm)
181{
182 struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
183 struct atmel_hlcdc *hlcdc = chip->hlcdc;
184 u32 status;
185 int ret;
186
187 ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PWM);
188 if (ret)
189 return;
190
191 while (true) {
192 ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
193 if (ret)
194 return;
195
196 if ((status & ATMEL_HLCDC_PWM) == 0)
197 break;
198
199 usleep_range(1, 10);
200 }
201}
202
203static const struct pwm_ops atmel_hlcdc_pwm_ops = {
204 .config = atmel_hlcdc_pwm_config,
205 .set_polarity = atmel_hlcdc_pwm_set_polarity,
206 .enable = atmel_hlcdc_pwm_enable,
207 .disable = atmel_hlcdc_pwm_disable,
208 .owner = THIS_MODULE,
209};
210
211static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
212 .slow_clk_erratum = true,
213};
214
215static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
216 .div1_clk_erratum = true,
217};
218
219static const struct of_device_id atmel_hlcdc_dt_ids[] = {
220 {
221 .compatible = "atmel,at91sam9n12-hlcdc",
222 /* 9n12 has same errata as 9x5 HLCDC PWM */
223 .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
224 },
225 {
226 .compatible = "atmel,at91sam9x5-hlcdc",
227 .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
228 },
229 {
230 .compatible = "atmel,sama5d2-hlcdc",
231 },
232 {
233 .compatible = "atmel,sama5d3-hlcdc",
234 .data = &atmel_hlcdc_pwm_sama5d3_errata,
235 },
236 {
237 .compatible = "atmel,sama5d4-hlcdc",
238 .data = &atmel_hlcdc_pwm_sama5d3_errata,
239 },
240 { /* sentinel */ },
241};
242MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids);
243
244static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
245{
246 const struct of_device_id *match;
247 struct device *dev = &pdev->dev;
248 struct atmel_hlcdc_pwm *chip;
249 struct atmel_hlcdc *hlcdc;
250 int ret;
251
252 hlcdc = dev_get_drvdata(dev->parent);
253
254 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
255 if (!chip)
256 return -ENOMEM;
257
258 ret = clk_prepare_enable(hlcdc->periph_clk);
259 if (ret)
260 return ret;
261
262 match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
263 if (match)
264 chip->errata = match->data;
265
266 chip->hlcdc = hlcdc;
267 chip->chip.ops = &atmel_hlcdc_pwm_ops;
268 chip->chip.dev = dev;
269 chip->chip.base = -1;
270 chip->chip.npwm = 1;
271 chip->chip.of_xlate = of_pwm_xlate_with_flags;
272 chip->chip.of_pwm_n_cells = 3;
273 chip->chip.can_sleep = 1;
274
275 ret = pwmchip_add(&chip->chip);
276 if (ret) {
277 clk_disable_unprepare(hlcdc->periph_clk);
278 return ret;
279 }
280
281 platform_set_drvdata(pdev, chip);
282
283 return 0;
284}
285
286static int atmel_hlcdc_pwm_remove(struct platform_device *pdev)
287{
288 struct atmel_hlcdc_pwm *chip = platform_get_drvdata(pdev);
289 int ret;
290
291 ret = pwmchip_remove(&chip->chip);
292 if (ret)
293 return ret;
294
295 clk_disable_unprepare(chip->hlcdc->periph_clk);
296
297 return 0;
298}
299
300static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
301 { .compatible = "atmel,hlcdc-pwm" },
302 { /* sentinel */ },
303};
304
305static struct platform_driver atmel_hlcdc_pwm_driver = {
306 .driver = {
307 .name = "atmel-hlcdc-pwm",
308 .of_match_table = atmel_hlcdc_pwm_dt_ids,
309 },
310 .probe = atmel_hlcdc_pwm_probe,
311 .remove = atmel_hlcdc_pwm_remove,
312};
313module_platform_driver(atmel_hlcdc_pwm_driver);
314
315MODULE_ALIAS("platform:atmel-hlcdc-pwm");
316MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
317MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
318MODULE_LICENSE("GPL v2");