1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *	Copyright (C) 2002 Motorola GSG-China
   4 *
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   5 * Author:
   6 *	Darius Augulis, Teltonika Inc.
   7 *
   8 * Desc.:
   9 *	Implementation of I2C Adapter/Algorithm Driver
  10 *	for I2C Bus integrated in Freescale i.MX/MXC processors
  11 *
  12 *	Derived from Motorola GSG China I2C example driver
  13 *
  14 *	Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  15 *	Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  16 *	Copyright (C) 2007 RightHand Technologies, Inc.
  17 *	Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  18 *
  19 *	Copyright 2013 Freescale Semiconductor, Inc.
  20 *	Copyright 2020 NXP
  21 *
  22 */
  23
  24#include <linux/acpi.h>
  25#include <linux/clk.h>
  26#include <linux/completion.h>
  27#include <linux/delay.h>
  28#include <linux/dma-mapping.h>
  29#include <linux/dmaengine.h>
  30#include <linux/dmapool.h>
  31#include <linux/err.h>
  32#include <linux/errno.h>
  33#include <linux/gpio/consumer.h>
  34#include <linux/i2c.h>
  35#include <linux/init.h>
  36#include <linux/interrupt.h>
  37#include <linux/io.h>
  38#include <linux/iopoll.h>
  39#include <linux/kernel.h>
  40#include <linux/spinlock.h>
  41#include <linux/hrtimer.h>
  42#include <linux/module.h>
  43#include <linux/of.h>
  44#include <linux/of_dma.h>
  45#include <linux/pinctrl/consumer.h>
  46#include <linux/platform_data/i2c-imx.h>
  47#include <linux/platform_device.h>
  48#include <linux/pm_runtime.h>
  49#include <linux/sched.h>
 
 
  50#include <linux/slab.h>
  51
 
 
 
 
 
 
 
  52/* This will be the driver name the kernel reports */
  53#define DRIVER_NAME "imx-i2c"
  54
  55#define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */
 
  56
  57/*
  58 * Enable DMA if transfer byte size is bigger than this threshold.
  59 * As the hardware request, it must bigger than 4 bytes.\
  60 * I have set '16' here, maybe it's not the best but I think it's
  61 * the appropriate.
  62 */
  63#define DMA_THRESHOLD	16
  64#define DMA_TIMEOUT	1000
  65
  66/* IMX I2C registers:
  67 * the I2C register offset is different between SoCs,
  68 * to provide support for all these chips, split the
  69 * register offset into a fixed base address and a
  70 * variable shift value, then the full register offset
  71 * will be calculated by
  72 * reg_off = ( reg_base_addr << reg_shift)
  73 */
  74#define IMX_I2C_IADR	0x00	/* i2c slave address */
  75#define IMX_I2C_IFDR	0x01	/* i2c frequency divider */
  76#define IMX_I2C_I2CR	0x02	/* i2c control */
  77#define IMX_I2C_I2SR	0x03	/* i2c status */
  78#define IMX_I2C_I2DR	0x04	/* i2c transfer data */
  79
  80/*
  81 * All of the layerscape series SoCs support IBIC register.
  82 */
  83#define IMX_I2C_IBIC	0x05    /* i2c bus interrupt config */
  84
  85#define IMX_I2C_REGSHIFT	2
  86#define VF610_I2C_REGSHIFT	0
  87
  88/* Bits of IMX I2C registers */
  89#define I2SR_RXAK	0x01
  90#define I2SR_IIF	0x02
  91#define I2SR_SRW	0x04
  92#define I2SR_IAL	0x10
  93#define I2SR_IBB	0x20
  94#define I2SR_IAAS	0x40
  95#define I2SR_ICF	0x80
  96#define I2CR_DMAEN	0x02
  97#define I2CR_RSTA	0x04
  98#define I2CR_TXAK	0x08
  99#define I2CR_MTX	0x10
 100#define I2CR_MSTA	0x20
 101#define I2CR_IIEN	0x40
 102#define I2CR_IEN	0x80
 103#define IBIC_BIIE	0x80 /* Bus idle interrupt enable */
 104
 105/* register bits different operating codes definition:
 106 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
 107 * - write zero to clear(w0c) INT flag on i.MX,
 108 * - but write one to clear(w1c) INT flag on Vybrid.
 109 * 2) I2CR: I2C module enable operation also differ between SoCs:
 110 * - set I2CR_IEN bit enable the module on i.MX,
 111 * - but clear I2CR_IEN bit enable the module on Vybrid.
 112 */
 113#define I2SR_CLR_OPCODE_W0C	0x0
 114#define I2SR_CLR_OPCODE_W1C	(I2SR_IAL | I2SR_IIF)
 115#define I2CR_IEN_OPCODE_0	0x0
 116#define I2CR_IEN_OPCODE_1	I2CR_IEN
 117
 118#define I2C_PM_TIMEOUT		10 /* ms */
 119
 120/*
 121 * sorted list of clock divider, register value pairs
 122 * taken from table 26-5, p.26-9, Freescale i.MX
 123 * Integrated Portable System Processor Reference Manual
 124 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 125 *
 126 * Duplicated divider values removed from list
 127 */
 128struct imx_i2c_clk_pair {
 129	u16	div;
 130	u16	val;
 131};
 132
 133static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 134	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
 135	{ 30,	0x00 },	{ 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
 136	{ 42,	0x03 }, { 44,	0x27 },	{ 48,	0x28 }, { 52,	0x05 },
 137	{ 56,	0x29 }, { 60,	0x06 }, { 64,	0x2A },	{ 72,	0x2B },
 138	{ 80,	0x2C }, { 88,	0x09 }, { 96,	0x2D }, { 104,	0x0A },
 139	{ 112,	0x2E }, { 128,	0x2F }, { 144,	0x0C }, { 160,	0x30 },
 140	{ 192,	0x31 },	{ 224,	0x32 }, { 240,	0x0F }, { 256,	0x33 },
 141	{ 288,	0x10 }, { 320,	0x34 },	{ 384,	0x35 }, { 448,	0x36 },
 142	{ 480,	0x13 }, { 512,	0x37 }, { 576,	0x14 },	{ 640,	0x38 },
 143	{ 768,	0x39 }, { 896,	0x3A }, { 960,	0x17 }, { 1024,	0x3B },
 144	{ 1152,	0x18 }, { 1280,	0x3C }, { 1536,	0x3D }, { 1792,	0x3E },
 145	{ 1920,	0x1B },	{ 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
 146	{ 3072,	0x1E }, { 3840,	0x1F }
 147};
 148
 149/* Vybrid VF610 clock divider, register value pairs */
 150static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 151	{ 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 152	{ 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 153	{ 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 154	{ 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 155	{ 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 156	{ 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 157	{ 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 158	{ 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 159	{ 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 160	{ 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 161	{ 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 162	{ 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 163	{ 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 164	{ 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 165	{ 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 166};
 167
 168enum imx_i2c_type {
 169	IMX1_I2C,
 170	IMX21_I2C,
 171	VF610_I2C,
 172};
 173
 174struct imx_i2c_hwdata {
 175	enum imx_i2c_type	devtype;
 176	unsigned int		regshift;
 177	struct imx_i2c_clk_pair	*clk_div;
 178	unsigned int		ndivs;
 179	unsigned int		i2sr_clr_opcode;
 180	unsigned int		i2cr_ien_opcode;
 181	/*
 182	 * Errata ERR007805 or e7805:
 183	 * I2C: When the I2C clock speed is configured for 400 kHz,
 184	 * the SCL low period violates the I2C spec of 1.3 uS min.
 185	 */
 186	bool			has_err007805;
 187};
 188
 189struct imx_i2c_dma {
 190	struct dma_chan		*chan_tx;
 191	struct dma_chan		*chan_rx;
 192	struct dma_chan		*chan_using;
 193	struct completion	cmd_complete;
 194	dma_addr_t		dma_buf;
 195	unsigned int		dma_len;
 196	enum dma_transfer_direction dma_transfer_dir;
 197	enum dma_data_direction dma_data_dir;
 198};
 199
 200struct imx_i2c_struct {
 201	struct i2c_adapter	adapter;
 
 202	struct clk		*clk;
 203	struct notifier_block	clk_change_nb;
 204	void __iomem		*base;
 
 205	wait_queue_head_t	queue;
 206	unsigned long		i2csr;
 207	unsigned int		disable_delay;
 208	int			stopped;
 209	unsigned int		ifdr; /* IMX_I2C_IFDR */
 210	unsigned int		cur_clk;
 211	unsigned int		bitrate;
 212	const struct imx_i2c_hwdata	*hwdata;
 213	struct i2c_bus_recovery_info rinfo;
 214
 215	struct pinctrl *pinctrl;
 216	struct pinctrl_state *pinctrl_pins_default;
 217	struct pinctrl_state *pinctrl_pins_gpio;
 218
 219	struct imx_i2c_dma	*dma;
 220	struct i2c_client	*slave;
 221	enum i2c_slave_event last_slave_event;
 222
 223	/* For checking slave events. */
 224	spinlock_t     slave_lock;
 225	struct hrtimer slave_timer;
 226};
 227
 228static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
 229	.devtype		= IMX1_I2C,
 230	.regshift		= IMX_I2C_REGSHIFT,
 231	.clk_div		= imx_i2c_clk_div,
 232	.ndivs			= ARRAY_SIZE(imx_i2c_clk_div),
 233	.i2sr_clr_opcode	= I2SR_CLR_OPCODE_W0C,
 234	.i2cr_ien_opcode	= I2CR_IEN_OPCODE_1,
 235
 236};
 237
 238static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
 239	.devtype		= IMX21_I2C,
 240	.regshift		= IMX_I2C_REGSHIFT,
 241	.clk_div		= imx_i2c_clk_div,
 242	.ndivs			= ARRAY_SIZE(imx_i2c_clk_div),
 243	.i2sr_clr_opcode	= I2SR_CLR_OPCODE_W0C,
 244	.i2cr_ien_opcode	= I2CR_IEN_OPCODE_1,
 245
 246};
 247
 248static const struct imx_i2c_hwdata imx6_i2c_hwdata = {
 249	.devtype		= IMX21_I2C,
 250	.regshift		= IMX_I2C_REGSHIFT,
 251	.clk_div		= imx_i2c_clk_div,
 252	.ndivs			= ARRAY_SIZE(imx_i2c_clk_div),
 253	.i2sr_clr_opcode	= I2SR_CLR_OPCODE_W0C,
 254	.i2cr_ien_opcode	= I2CR_IEN_OPCODE_1,
 255	.has_err007805		= true,
 256};
 257
 258static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 259	.devtype		= VF610_I2C,
 260	.regshift		= VF610_I2C_REGSHIFT,
 261	.clk_div		= vf610_i2c_clk_div,
 262	.ndivs			= ARRAY_SIZE(vf610_i2c_clk_div),
 263	.i2sr_clr_opcode	= I2SR_CLR_OPCODE_W1C,
 264	.i2cr_ien_opcode	= I2CR_IEN_OPCODE_0,
 265
 266};
 267
 268static const struct platform_device_id imx_i2c_devtype[] = {
 269	{
 270		.name = "imx1-i2c",
 271		.driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
 272	}, {
 273		.name = "imx21-i2c",
 274		.driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
 275	}, {
 276		/* sentinel */
 277	}
 278};
 279MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
 280
 281static const struct of_device_id i2c_imx_dt_ids[] = {
 282	{ .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 283	{ .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 284	{ .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, },
 285	{ .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, },
 286	{ .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, },
 287	{ .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, },
 288	{ .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, },
 289	{ .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, },
 290	{ .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, },
 291	{ .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, },
 292	{ .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },
 293	{ .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },
 294	{ .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 295	{ /* sentinel */ }
 296};
 297MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 298
 299static const struct acpi_device_id i2c_imx_acpi_ids[] = {
 300	{"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
 301	{ }
 302};
 303MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
 304
 305static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 306{
 307	return i2c_imx->hwdata->devtype == IMX1_I2C;
 308}
 309
 310static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)
 311{
 312	return i2c_imx->hwdata->devtype == VF610_I2C;
 313}
 314
 315static inline void imx_i2c_write_reg(unsigned int val,
 316		struct imx_i2c_struct *i2c_imx, unsigned int reg)
 317{
 318	writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 319}
 320
 321static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 322		unsigned int reg)
 323{
 324	return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 325}
 326
 327static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
 328{
 329	unsigned int temp;
 330
 331	/*
 332	 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
 333	 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
 334	 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
 335	 */
 336	temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
 337	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 338}
 339
 340/* Set up i2c controller register and i2c status register to default value. */
 341static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
 342{
 343	imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 344			  i2c_imx, IMX_I2C_I2CR);
 345	i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
 346}
 347
 348/* Functions for DMA support */
 349static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 350						dma_addr_t phy_addr)
 351{
 352	struct imx_i2c_dma *dma;
 353	struct dma_slave_config dma_sconfig;
 354	struct device *dev = &i2c_imx->adapter.dev;
 355	int ret;
 356
 357	dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 358	if (!dma)
 359		return;
 360
 361	dma->chan_tx = dma_request_chan(dev, "tx");
 362	if (IS_ERR(dma->chan_tx)) {
 363		ret = PTR_ERR(dma->chan_tx);
 364		if (ret != -ENODEV && ret != -EPROBE_DEFER)
 365			dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
 366		goto fail_al;
 367	}
 368
 369	dma_sconfig.dst_addr = phy_addr +
 370				(IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 371	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 372	dma_sconfig.dst_maxburst = 1;
 373	dma_sconfig.direction = DMA_MEM_TO_DEV;
 374	ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 375	if (ret < 0) {
 376		dev_err(dev, "can't configure tx channel (%d)\n", ret);
 377		goto fail_tx;
 378	}
 379
 380	dma->chan_rx = dma_request_chan(dev, "rx");
 381	if (IS_ERR(dma->chan_rx)) {
 382		ret = PTR_ERR(dma->chan_rx);
 383		if (ret != -ENODEV && ret != -EPROBE_DEFER)
 384			dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
 385		goto fail_tx;
 386	}
 387
 388	dma_sconfig.src_addr = phy_addr +
 389				(IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 390	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 391	dma_sconfig.src_maxburst = 1;
 392	dma_sconfig.direction = DMA_DEV_TO_MEM;
 393	ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 394	if (ret < 0) {
 395		dev_err(dev, "can't configure rx channel (%d)\n", ret);
 396		goto fail_rx;
 397	}
 398
 399	i2c_imx->dma = dma;
 400	init_completion(&dma->cmd_complete);
 401	dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 402		dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 403
 404	return;
 405
 406fail_rx:
 407	dma_release_channel(dma->chan_rx);
 408fail_tx:
 409	dma_release_channel(dma->chan_tx);
 410fail_al:
 411	devm_kfree(dev, dma);
 412}
 413
 414static void i2c_imx_dma_callback(void *arg)
 415{
 416	struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
 417	struct imx_i2c_dma *dma = i2c_imx->dma;
 418
 419	dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
 420			dma->dma_len, dma->dma_data_dir);
 421	complete(&dma->cmd_complete);
 422}
 423
 424static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
 425					struct i2c_msg *msgs)
 426{
 427	struct imx_i2c_dma *dma = i2c_imx->dma;
 428	struct dma_async_tx_descriptor *txdesc;
 429	struct device *dev = &i2c_imx->adapter.dev;
 430	struct device *chan_dev = dma->chan_using->device->dev;
 431
 432	dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
 433					dma->dma_len, dma->dma_data_dir);
 434	if (dma_mapping_error(chan_dev, dma->dma_buf)) {
 435		dev_err(dev, "DMA mapping failed\n");
 436		goto err_map;
 437	}
 438
 439	txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
 440					dma->dma_len, dma->dma_transfer_dir,
 441					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 442	if (!txdesc) {
 443		dev_err(dev, "Not able to get desc for DMA xfer\n");
 444		goto err_desc;
 445	}
 446
 447	reinit_completion(&dma->cmd_complete);
 448	txdesc->callback = i2c_imx_dma_callback;
 449	txdesc->callback_param = i2c_imx;
 450	if (dma_submit_error(dmaengine_submit(txdesc))) {
 451		dev_err(dev, "DMA submit failed\n");
 452		goto err_submit;
 453	}
 454
 455	dma_async_issue_pending(dma->chan_using);
 456	return 0;
 457
 458err_submit:
 459	dmaengine_terminate_sync(dma->chan_using);
 460err_desc:
 461	dma_unmap_single(chan_dev, dma->dma_buf,
 462			dma->dma_len, dma->dma_data_dir);
 463err_map:
 464	return -EINVAL;
 465}
 466
 467static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
 468{
 469	struct imx_i2c_dma *dma = i2c_imx->dma;
 470
 471	dma->dma_buf = 0;
 472	dma->dma_len = 0;
 473
 474	dma_release_channel(dma->chan_tx);
 475	dma->chan_tx = NULL;
 476
 477	dma_release_channel(dma->chan_rx);
 478	dma->chan_rx = NULL;
 479
 480	dma->chan_using = NULL;
 481}
 482
 483static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
 484{
 485	unsigned long orig_jiffies = jiffies;
 486	unsigned int temp;
 487
 488	while (1) {
 489		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 490
 491		/* check for arbitration lost */
 492		if (temp & I2SR_IAL) {
 493			i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 494			return -EAGAIN;
 495		}
 496
 497		if (for_busy && (temp & I2SR_IBB)) {
 498			i2c_imx->stopped = 0;
 499			break;
 500		}
 501		if (!for_busy && !(temp & I2SR_IBB)) {
 502			i2c_imx->stopped = 1;
 503			break;
 
 
 
 
 504		}
 505		if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 506			dev_dbg(&i2c_imx->adapter.dev,
 507				"<%s> I2C bus is busy\n", __func__);
 508			return -ETIMEDOUT;
 509		}
 510		if (atomic)
 511			udelay(100);
 512		else
 513			schedule();
 514	}
 515
 516	return 0;
 517}
 518
 519static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
 520{
 521	if (atomic) {
 522		void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
 523		unsigned int regval;
 524
 525		/*
 526		 * The formula for the poll timeout is documented in the RM
 527		 * Rev.5 on page 1878:
 528		 *     T_min = 10/F_scl
 529		 * Set the value hard as it is done for the non-atomic use-case.
 530		 * Use 10 kHz for the calculation since this is the minimum
 531		 * allowed SMBus frequency. Also add an offset of 100us since it
 532		 * turned out that the I2SR_IIF bit isn't set correctly within
 533		 * the minimum timeout in polling mode.
 534		 */
 535		readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
 536		i2c_imx->i2csr = regval;
 537		i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
 538	} else {
 539		wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 540	}
 541
 542	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 543		dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 544		return -ETIMEDOUT;
 545	}
 546
 547	/* check for arbitration lost */
 548	if (i2c_imx->i2csr & I2SR_IAL) {
 549		dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
 550		i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 551
 552		i2c_imx->i2csr = 0;
 553		return -EAGAIN;
 554	}
 555
 556	dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 557	i2c_imx->i2csr = 0;
 558	return 0;
 559}
 560
 561static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 562{
 563	if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 564		dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 565		return -ENXIO;  /* No ACK */
 566	}
 567
 568	dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 569	return 0;
 570}
 571
 572static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 573			    unsigned int i2c_clk_rate)
 574{
 575	struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 576	unsigned int div;
 577	int i;
 578
 579	if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) {
 580		dev_dbg(&i2c_imx->adapter.dev,
 581			"SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n",
 582			i2c_imx->bitrate);
 583		i2c_imx->bitrate = 384000;
 584	}
 585
 586	/* Divider value calculation */
 587	if (i2c_imx->cur_clk == i2c_clk_rate)
 588		return;
 589
 590	i2c_imx->cur_clk = i2c_clk_rate;
 591
 592	div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);
 593	if (div < i2c_clk_div[0].div)
 594		i = 0;
 595	else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 596		i = i2c_imx->hwdata->ndivs - 1;
 597	else
 598		for (i = 0; i2c_clk_div[i].div < div; i++)
 599			;
 600
 601	/* Store divider value */
 602	i2c_imx->ifdr = i2c_clk_div[i].val;
 603
 604	/*
 605	 * There dummy delay is calculated.
 606	 * It should be about one I2C clock period long.
 607	 * This delay is used in I2C bus disable function
 608	 * to fix chip hardware bug.
 609	 */
 610	i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,
 611					      i2c_clk_rate / 2);
 612
 613#ifdef CONFIG_I2C_DEBUG_BUS
 614	dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 615		i2c_clk_rate, div);
 616	dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 617		i2c_clk_div[i].val, i2c_clk_div[i].div);
 618#endif
 619}
 620
 621static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
 622				     unsigned long action, void *data)
 623{
 624	struct clk_notifier_data *ndata = data;
 625	struct imx_i2c_struct *i2c_imx = container_of(nb,
 626						      struct imx_i2c_struct,
 627						      clk_change_nb);
 628
 629	if (action & POST_RATE_CHANGE)
 630		i2c_imx_set_clk(i2c_imx, ndata->new_rate);
 631
 632	return NOTIFY_OK;
 633}
 634
 635static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
 636{
 637	unsigned int temp = 0;
 638	int result;
 639
 640	imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 
 
 
 641	/* Enable I2C controller */
 642	imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 643	imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 644
 645	/* Wait controller to be stable */
 646	if (atomic)
 647		udelay(50);
 648	else
 649		usleep_range(50, 150);
 650
 651	/* Start I2C transaction */
 652	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 653	temp |= I2CR_MSTA;
 654	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 655	result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
 656	if (result)
 657		return result;
 
 658
 659	temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 660	if (atomic)
 661		temp &= ~I2CR_IIEN; /* Disable interrupt */
 662
 663	temp &= ~I2CR_DMAEN;
 664	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 665	return result;
 666}
 667
 668static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
 669{
 670	unsigned int temp = 0;
 671
 672	if (!i2c_imx->stopped) {
 673		/* Stop I2C transaction */
 674		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 675		if (!(temp & I2CR_MSTA))
 676			i2c_imx->stopped = 1;
 677		temp &= ~(I2CR_MSTA | I2CR_MTX);
 678		if (i2c_imx->dma)
 679			temp &= ~I2CR_DMAEN;
 680		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 681	}
 682	if (is_imx1_i2c(i2c_imx)) {
 683		/*
 684		 * This delay caused by an i.MXL hardware bug.
 685		 * If no (or too short) delay, no "STOP" bit will be generated.
 686		 */
 687		udelay(i2c_imx->disable_delay);
 688	}
 689
 690	if (!i2c_imx->stopped)
 691		i2c_imx_bus_busy(i2c_imx, 0, atomic);
 692
 693	/* Disable I2C controller */
 694	temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 695	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 696}
 697
 698/*
 699 * Enable bus idle interrupts
 700 * Note: IBIC register will be cleared after disabled i2c module.
 701 * All of layerscape series SoCs support IBIC register.
 702 */
 703static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
 704{
 705	if (is_vf610_i2c(i2c_imx)) {
 706		unsigned int temp;
 707
 708		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
 709		temp |= IBIC_BIIE;
 710		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
 711	}
 712}
 713
 714static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx,
 715				enum i2c_slave_event event, u8 *val)
 716{
 717	i2c_slave_event(i2c_imx->slave, event, val);
 718	i2c_imx->last_slave_event = event;
 719}
 720
 721static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx)
 722{
 723	u8 val = 0;
 724
 725	while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {
 726		switch (i2c_imx->last_slave_event) {
 727		case I2C_SLAVE_READ_REQUESTED:
 728			i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED,
 729					    &val);
 730			break;
 731
 732		case I2C_SLAVE_WRITE_REQUESTED:
 733		case I2C_SLAVE_READ_PROCESSED:
 734		case I2C_SLAVE_WRITE_RECEIVED:
 735			i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val);
 736			break;
 737
 738		case I2C_SLAVE_STOP:
 739			break;
 740		}
 741	}
 742}
 743
 744/* Returns true if the timer should be restarted, false if not. */
 745static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx,
 746					unsigned int status, unsigned int ctl)
 747{
 748	u8 value = 0;
 749
 750	if (status & I2SR_IAL) { /* Arbitration lost */
 751		i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 752		if (!(status & I2SR_IAAS))
 753			return IRQ_HANDLED;
 754	}
 755
 756	if (!(status & I2SR_IBB)) {
 757		/* No master on the bus, that could mean a stop condition. */
 758		i2c_imx_slave_finish_op(i2c_imx);
 759		return IRQ_HANDLED;
 760	}
 761
 762	if (!(status & I2SR_ICF))
 763		/* Data transfer still in progress, ignore this. */
 764		goto out;
 765
 766	if (status & I2SR_IAAS) { /* Addressed as a slave */
 767		i2c_imx_slave_finish_op(i2c_imx);
 768		if (status & I2SR_SRW) { /* Master wants to read from us*/
 769			dev_dbg(&i2c_imx->adapter.dev, "read requested");
 770			i2c_imx_slave_event(i2c_imx,
 771					    I2C_SLAVE_READ_REQUESTED, &value);
 772
 773			/* Slave transmit */
 774			ctl |= I2CR_MTX;
 775			imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
 776
 777			/* Send data */
 778			imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
 779		} else { /* Master wants to write to us */
 780			dev_dbg(&i2c_imx->adapter.dev, "write requested");
 781			i2c_imx_slave_event(i2c_imx,
 782					    I2C_SLAVE_WRITE_REQUESTED, &value);
 783
 784			/* Slave receive */
 785			ctl &= ~I2CR_MTX;
 786			imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
 787			/* Dummy read */
 788			imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 789		}
 790	} else if (!(ctl & I2CR_MTX)) { /* Receive mode */
 791		value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 792		i2c_imx_slave_event(i2c_imx,
 793				    I2C_SLAVE_WRITE_RECEIVED, &value);
 794	} else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
 795		ctl |= I2CR_MTX;
 796		imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
 797
 798		i2c_imx_slave_event(i2c_imx,
 799				    I2C_SLAVE_READ_PROCESSED, &value);
 800
 801		imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
 802	} else { /* Transmit mode received NAK, operation is done */
 803		ctl &= ~I2CR_MTX;
 804		imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
 805		imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 806
 807		/* flag the last byte as processed */
 808		i2c_imx_slave_event(i2c_imx,
 809				    I2C_SLAVE_READ_PROCESSED, &value);
 810
 811		i2c_imx_slave_finish_op(i2c_imx);
 812		return IRQ_HANDLED;
 813	}
 814
 815out:
 816	/*
 817	 * No need to check the return value here.  If it returns 0 or
 818	 * 1, then everything is fine.  If it returns -1, then the
 819	 * timer is running in the handler.  This will still work,
 820	 * though it may be redone (or already have been done) by the
 821	 * timer function.
 822	 */
 823	hrtimer_try_to_cancel(&i2c_imx->slave_timer);
 824	hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);
 825	hrtimer_restart(&i2c_imx->slave_timer);
 826	return IRQ_HANDLED;
 827}
 828
 829static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t)
 830{
 831	struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct,
 832						      slave_timer);
 833	unsigned int ctl, status;
 834	unsigned long flags;
 835
 836	spin_lock_irqsave(&i2c_imx->slave_lock, flags);
 837	status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 838	ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 839	i2c_imx_slave_handle(i2c_imx, status, ctl);
 840	spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
 841	return HRTIMER_NORESTART;
 842}
 843
 844static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
 845{
 846	int temp;
 847
 848	/* Set slave addr. */
 849	imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
 850
 851	i2c_imx_reset_regs(i2c_imx);
 852
 853	/* Enable module */
 854	temp = i2c_imx->hwdata->i2cr_ien_opcode;
 855	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 856
 857	/* Enable interrupt from i2c module */
 858	temp |= I2CR_IIEN;
 859	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 860
 861	i2c_imx_enable_bus_idle(i2c_imx);
 862}
 863
 864static int i2c_imx_reg_slave(struct i2c_client *client)
 865{
 866	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
 867	int ret;
 868
 869	if (i2c_imx->slave)
 870		return -EBUSY;
 871
 872	i2c_imx->slave = client;
 873	i2c_imx->last_slave_event = I2C_SLAVE_STOP;
 874
 875	/* Resume */
 876	ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
 877	if (ret < 0) {
 878		dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
 879		return ret;
 880	}
 881
 882	i2c_imx_slave_init(i2c_imx);
 883
 884	return 0;
 885}
 886
 887static int i2c_imx_unreg_slave(struct i2c_client *client)
 888{
 889	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
 890	int ret;
 891
 892	if (!i2c_imx->slave)
 893		return -EINVAL;
 894
 895	/* Reset slave address. */
 896	imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
 897
 898	i2c_imx_reset_regs(i2c_imx);
 899
 900	i2c_imx->slave = NULL;
 901
 902	/* Suspend */
 903	ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
 904	if (ret < 0)
 905		dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
 906
 907	return ret;
 908}
 909
 910static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status)
 911{
 912	/* save status register */
 913	i2c_imx->i2csr = status;
 914	wake_up(&i2c_imx->queue);
 915
 916	return IRQ_HANDLED;
 917}
 918
 919static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 920{
 921	struct imx_i2c_struct *i2c_imx = dev_id;
 922	unsigned int ctl, status;
 923	unsigned long flags;
 924
 925	spin_lock_irqsave(&i2c_imx->slave_lock, flags);
 926	status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 927	ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 928
 929	if (status & I2SR_IIF) {
 930		i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
 931		if (i2c_imx->slave) {
 932			if (!(ctl & I2CR_MSTA)) {
 933				irqreturn_t ret;
 934
 935				ret = i2c_imx_slave_handle(i2c_imx,
 936							   status, ctl);
 937				spin_unlock_irqrestore(&i2c_imx->slave_lock,
 938						       flags);
 939				return ret;
 940			}
 941			i2c_imx_slave_finish_op(i2c_imx);
 942		}
 943		spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
 944		return i2c_imx_master_isr(i2c_imx, status);
 945	}
 946	spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
 947
 948	return IRQ_NONE;
 949}
 950
 951static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
 952					struct i2c_msg *msgs)
 953{
 954	int result;
 955	unsigned long time_left;
 956	unsigned int temp = 0;
 957	unsigned long orig_jiffies = jiffies;
 958	struct imx_i2c_dma *dma = i2c_imx->dma;
 959	struct device *dev = &i2c_imx->adapter.dev;
 960
 961	dma->chan_using = dma->chan_tx;
 962	dma->dma_transfer_dir = DMA_MEM_TO_DEV;
 963	dma->dma_data_dir = DMA_TO_DEVICE;
 964	dma->dma_len = msgs->len - 1;
 965	result = i2c_imx_dma_xfer(i2c_imx, msgs);
 966	if (result)
 967		return result;
 968
 969	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 970	temp |= I2CR_DMAEN;
 971	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 972
 973	/*
 974	 * Write slave address.
 975	 * The first byte must be transmitted by the CPU.
 976	 */
 977	imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 978	time_left = wait_for_completion_timeout(
 979				&i2c_imx->dma->cmd_complete,
 980				msecs_to_jiffies(DMA_TIMEOUT));
 981	if (time_left == 0) {
 982		dmaengine_terminate_sync(dma->chan_using);
 983		return -ETIMEDOUT;
 984	}
 985
 986	/* Waiting for transfer complete. */
 987	while (1) {
 988		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 989		if (temp & I2SR_ICF)
 990			break;
 991		if (time_after(jiffies, orig_jiffies +
 992				msecs_to_jiffies(DMA_TIMEOUT))) {
 993			dev_dbg(dev, "<%s> Timeout\n", __func__);
 994			return -ETIMEDOUT;
 995		}
 996		schedule();
 997	}
 998
 999	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1000	temp &= ~I2CR_DMAEN;
1001	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1002
1003	/* The last data byte must be transferred by the CPU. */
1004	imx_i2c_write_reg(msgs->buf[msgs->len-1],
1005				i2c_imx, IMX_I2C_I2DR);
1006	result = i2c_imx_trx_complete(i2c_imx, false);
1007	if (result)
1008		return result;
1009
1010	return i2c_imx_acked(i2c_imx);
1011}
1012
1013static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
1014			struct i2c_msg *msgs, bool is_lastmsg)
1015{
1016	int result;
1017	unsigned long time_left;
1018	unsigned int temp;
1019	unsigned long orig_jiffies = jiffies;
1020	struct imx_i2c_dma *dma = i2c_imx->dma;
1021	struct device *dev = &i2c_imx->adapter.dev;
1022
1023
1024	dma->chan_using = dma->chan_rx;
1025	dma->dma_transfer_dir = DMA_DEV_TO_MEM;
1026	dma->dma_data_dir = DMA_FROM_DEVICE;
1027	/* The last two data bytes must be transferred by the CPU. */
1028	dma->dma_len = msgs->len - 2;
1029	result = i2c_imx_dma_xfer(i2c_imx, msgs);
1030	if (result)
1031		return result;
1032
1033	time_left = wait_for_completion_timeout(
1034				&i2c_imx->dma->cmd_complete,
1035				msecs_to_jiffies(DMA_TIMEOUT));
1036	if (time_left == 0) {
1037		dmaengine_terminate_sync(dma->chan_using);
1038		return -ETIMEDOUT;
1039	}
1040
1041	/* waiting for transfer complete. */
1042	while (1) {
1043		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1044		if (temp & I2SR_ICF)
1045			break;
1046		if (time_after(jiffies, orig_jiffies +
1047				msecs_to_jiffies(DMA_TIMEOUT))) {
1048			dev_dbg(dev, "<%s> Timeout\n", __func__);
1049			return -ETIMEDOUT;
1050		}
1051		schedule();
1052	}
1053
1054	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1055	temp &= ~I2CR_DMAEN;
1056	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1057
1058	/* read n-1 byte data */
1059	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1060	temp |= I2CR_TXAK;
1061	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1062
1063	msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1064	/* read n byte data */
1065	result = i2c_imx_trx_complete(i2c_imx, false);
1066	if (result)
1067		return result;
1068
1069	if (is_lastmsg) {
1070		/*
1071		 * It must generate STOP before read I2DR to prevent
1072		 * controller from generating another clock cycle
1073		 */
1074		dev_dbg(dev, "<%s> clear MSTA\n", __func__);
1075		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1076		if (!(temp & I2CR_MSTA))
1077			i2c_imx->stopped = 1;
1078		temp &= ~(I2CR_MSTA | I2CR_MTX);
1079		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1080		if (!i2c_imx->stopped)
1081			i2c_imx_bus_busy(i2c_imx, 0, false);
1082	} else {
1083		/*
1084		 * For i2c master receiver repeat restart operation like:
1085		 * read -> repeat MSTA -> read/write
1086		 * The controller must set MTX before read the last byte in
1087		 * the first read operation, otherwise the first read cost
1088		 * one extra clock cycle.
1089		 */
1090		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1091		temp |= I2CR_MTX;
1092		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1093	}
1094	msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1095
1096	return 0;
1097}
1098
1099static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1100			 bool atomic)
1101{
1102	int i, result;
1103
1104	dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1105		__func__, i2c_8bit_addr_from_msg(msgs));
1106
1107	/* write slave address */
1108	imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1109	result = i2c_imx_trx_complete(i2c_imx, atomic);
1110	if (result)
1111		return result;
1112	result = i2c_imx_acked(i2c_imx);
1113	if (result)
1114		return result;
1115	dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
1116
1117	/* write data */
1118	for (i = 0; i < msgs->len; i++) {
1119		dev_dbg(&i2c_imx->adapter.dev,
1120			"<%s> write byte: B%d=0x%X\n",
1121			__func__, i, msgs->buf[i]);
1122		imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
1123		result = i2c_imx_trx_complete(i2c_imx, atomic);
1124		if (result)
1125			return result;
1126		result = i2c_imx_acked(i2c_imx);
1127		if (result)
1128			return result;
1129	}
1130	return 0;
1131}
1132
1133static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1134			bool is_lastmsg, bool atomic)
1135{
1136	int i, result;
1137	unsigned int temp;
1138	int block_data = msgs->flags & I2C_M_RECV_LEN;
1139	int use_dma = i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE &&
1140		msgs->len >= DMA_THRESHOLD && !block_data;
1141
1142	dev_dbg(&i2c_imx->adapter.dev,
1143		"<%s> write slave address: addr=0x%x\n",
1144		__func__, i2c_8bit_addr_from_msg(msgs));
1145
1146	/* write slave address */
1147	imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1148	result = i2c_imx_trx_complete(i2c_imx, atomic);
1149	if (result)
1150		return result;
1151	result = i2c_imx_acked(i2c_imx);
1152	if (result)
1153		return result;
1154
1155	dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
1156
1157	/* setup bus to read data */
1158	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1159	temp &= ~I2CR_MTX;
1160
1161	/*
1162	 * Reset the I2CR_TXAK flag initially for SMBus block read since the
1163	 * length is unknown
1164	 */
1165	if ((msgs->len - 1) || block_data)
1166		temp &= ~I2CR_TXAK;
1167	if (use_dma)
1168		temp |= I2CR_DMAEN;
1169	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1170	imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
1171
1172	dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1173
1174	if (use_dma)
1175		return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
1176
1177	/* read data */
1178	for (i = 0; i < msgs->len; i++) {
1179		u8 len = 0;
1180
1181		result = i2c_imx_trx_complete(i2c_imx, atomic);
1182		if (result)
1183			return result;
1184		/*
1185		 * First byte is the length of remaining packet
1186		 * in the SMBus block data read. Add it to
1187		 * msgs->len.
1188		 */
1189		if ((!i) && block_data) {
1190			len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1191			if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
1192				return -EPROTO;
1193			dev_dbg(&i2c_imx->adapter.dev,
1194				"<%s> read length: 0x%X\n",
1195				__func__, len);
1196			msgs->len += len;
1197		}
1198		if (i == (msgs->len - 1)) {
1199			if (is_lastmsg) {
1200				/*
1201				 * It must generate STOP before read I2DR to prevent
1202				 * controller from generating another clock cycle
1203				 */
1204				dev_dbg(&i2c_imx->adapter.dev,
1205					"<%s> clear MSTA\n", __func__);
1206				temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1207				if (!(temp & I2CR_MSTA))
1208					i2c_imx->stopped =  1;
1209				temp &= ~(I2CR_MSTA | I2CR_MTX);
1210				imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1211				if (!i2c_imx->stopped)
1212					i2c_imx_bus_busy(i2c_imx, 0, atomic);
1213			} else {
1214				/*
1215				 * For i2c master receiver repeat restart operation like:
1216				 * read -> repeat MSTA -> read/write
1217				 * The controller must set MTX before read the last byte in
1218				 * the first read operation, otherwise the first read cost
1219				 * one extra clock cycle.
1220				 */
1221				temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1222				temp |= I2CR_MTX;
1223				imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1224			}
1225		} else if (i == (msgs->len - 2)) {
1226			dev_dbg(&i2c_imx->adapter.dev,
1227				"<%s> set TXAK\n", __func__);
1228			temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1229			temp |= I2CR_TXAK;
1230			imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1231		}
1232		if ((!i) && block_data)
1233			msgs->buf[0] = len;
1234		else
1235			msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1236		dev_dbg(&i2c_imx->adapter.dev,
1237			"<%s> read byte: B%d=0x%X\n",
1238			__func__, i, msgs->buf[i]);
1239	}
1240	return 0;
1241}
1242
1243static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
1244			       struct i2c_msg *msgs, int num, bool atomic)
1245{
1246	unsigned int i, temp;
1247	int result;
1248	bool is_lastmsg = false;
1249	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1250
1251	/* Start I2C transfer */
1252	result = i2c_imx_start(i2c_imx, atomic);
1253	if (result) {
1254		/*
1255		 * Bus recovery uses gpiod_get_value_cansleep() which is not
1256		 * allowed within atomic context.
1257		 */
1258		if (!atomic && i2c_imx->adapter.bus_recovery_info) {
1259			i2c_recover_bus(&i2c_imx->adapter);
1260			result = i2c_imx_start(i2c_imx, atomic);
1261		}
1262	}
1263
 
 
1264	if (result)
1265		goto fail0;
1266
1267	/* read/write data */
1268	for (i = 0; i < num; i++) {
1269		if (i == num - 1)
1270			is_lastmsg = true;
1271
1272		if (i) {
1273			dev_dbg(&i2c_imx->adapter.dev,
1274				"<%s> repeated start\n", __func__);
1275			temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1276			temp |= I2CR_RSTA;
1277			imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1278			result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
1279			if (result)
1280				goto fail0;
1281		}
1282		dev_dbg(&i2c_imx->adapter.dev,
1283			"<%s> transfer message: %d\n", __func__, i);
1284		/* write/read data */
1285#ifdef CONFIG_I2C_DEBUG_BUS
1286		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1287		dev_dbg(&i2c_imx->adapter.dev,
1288			"<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
1289			__func__,
1290			(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
1291			(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
1292			(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
1293		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1294		dev_dbg(&i2c_imx->adapter.dev,
1295			"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
1296			__func__,
1297			(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
1298			(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
1299			(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
1300			(temp & I2SR_RXAK ? 1 : 0));
1301#endif
1302		if (msgs[i].flags & I2C_M_RD) {
1303			result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
1304		} else {
1305			if (!atomic &&
1306			    i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&
1307				msgs[i].flags & I2C_M_DMA_SAFE)
1308				result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
1309			else
1310				result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
1311		}
1312		if (result)
1313			goto fail0;
1314	}
1315
1316fail0:
1317	/* Stop I2C transfer */
1318	i2c_imx_stop(i2c_imx, atomic);
1319
1320	dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1321		(result < 0) ? "error" : "success msg",
1322			(result < 0) ? result : num);
1323	/* After data is transferred, switch to slave mode(as a receiver) */
1324	if (i2c_imx->slave)
1325		i2c_imx_slave_init(i2c_imx);
1326
1327	return (result < 0) ? result : num;
1328}
1329
1330static int i2c_imx_xfer(struct i2c_adapter *adapter,
1331			struct i2c_msg *msgs, int num)
1332{
1333	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1334	int result;
1335
1336	result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
1337	if (result < 0)
1338		return result;
1339
1340	result = i2c_imx_xfer_common(adapter, msgs, num, false);
1341
1342	pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1343	pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1344
1345	return result;
1346}
1347
1348static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1349			       struct i2c_msg *msgs, int num)
1350{
1351	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1352	int result;
1353
1354	result = clk_enable(i2c_imx->clk);
1355	if (result)
1356		return result;
1357
1358	result = i2c_imx_xfer_common(adapter, msgs, num, true);
1359
1360	clk_disable(i2c_imx->clk);
1361
1362	return result;
1363}
1364
1365static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1366{
1367	struct imx_i2c_struct *i2c_imx;
1368
1369	i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1370
1371	pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1372}
1373
1374static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1375{
1376	struct imx_i2c_struct *i2c_imx;
 
 
 
 
 
 
1377
1378	i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1379
1380	pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1381}
1382
1383/*
1384 * We switch SCL and SDA to their GPIO function and do some bitbanging
1385 * for bus recovery. These alternative pinmux settings can be
1386 * described in the device tree by a separate pinctrl state "gpio". If
1387 * this is missing this is not a big problem, the only implication is
1388 * that we can't do bus recovery.
1389 */
1390static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1391		struct platform_device *pdev)
1392{
1393	struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1394
1395	i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1396	if (!i2c_imx->pinctrl) {
1397		dev_info(&pdev->dev, "pinctrl unavailable, bus recovery not supported\n");
1398		return 0;
1399	}
1400	if (IS_ERR(i2c_imx->pinctrl)) {
1401		dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1402		return PTR_ERR(i2c_imx->pinctrl);
1403	}
1404
1405	i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1406			PINCTRL_STATE_DEFAULT);
1407	i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1408			"gpio");
1409	rinfo->sda_gpiod = devm_gpiod_get_optional(&pdev->dev, "sda", GPIOD_IN);
1410	rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1411
1412	if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1413	    PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1414		return -EPROBE_DEFER;
1415	} else if (IS_ERR(rinfo->sda_gpiod) ||
1416		   IS_ERR(rinfo->scl_gpiod) ||
1417		   IS_ERR(i2c_imx->pinctrl_pins_default) ||
1418		   IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1419		dev_dbg(&pdev->dev, "recovery information incomplete\n");
1420		return 0;
1421	}
1422
1423	dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1424		rinfo->sda_gpiod ? ",sda" : "");
1425
1426	rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1427	rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1428	rinfo->recover_bus = i2c_generic_scl_recovery;
1429	i2c_imx->adapter.bus_recovery_info = rinfo;
1430
1431	return 0;
1432}
1433
1434static u32 i2c_imx_func(struct i2c_adapter *adapter)
1435{
1436	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1437		| I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1438}
1439
1440static const struct i2c_algorithm i2c_imx_algo = {
1441	.master_xfer = i2c_imx_xfer,
1442	.master_xfer_atomic = i2c_imx_xfer_atomic,
1443	.functionality = i2c_imx_func,
1444	.reg_slave	= i2c_imx_reg_slave,
1445	.unreg_slave	= i2c_imx_unreg_slave,
1446};
1447
1448static int i2c_imx_probe(struct platform_device *pdev)
1449{
1450	struct imx_i2c_struct *i2c_imx;
1451	struct resource *res;
1452	struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1453	void __iomem *base;
1454	int irq, ret;
1455	dma_addr_t phy_addr;
1456	const struct imx_i2c_hwdata *match;
1457
1458	irq = platform_get_irq(pdev, 0);
1459	if (irq < 0)
1460		return irq;
 
 
 
1461
1462	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1463	if (IS_ERR(base))
1464		return PTR_ERR(base);
1465
1466	phy_addr = (dma_addr_t)res->start;
1467	i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1468	if (!i2c_imx)
1469		return -ENOMEM;
1470
1471	spin_lock_init(&i2c_imx->slave_lock);
1472	hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1473	i2c_imx->slave_timer.function = i2c_imx_slave_timeout;
1474
1475	match = device_get_match_data(&pdev->dev);
1476	if (match)
1477		i2c_imx->hwdata = match;
1478	else
1479		i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1480				platform_get_device_id(pdev)->driver_data;
1481
1482	/* Setup i2c_imx driver structure */
1483	strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1484	i2c_imx->adapter.owner		= THIS_MODULE;
1485	i2c_imx->adapter.algo		= &i2c_imx_algo;
1486	i2c_imx->adapter.dev.parent	= &pdev->dev;
1487	i2c_imx->adapter.nr		= pdev->id;
1488	i2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
1489	i2c_imx->base			= base;
1490	ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1491
1492	/* Get I2C clock */
1493	i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1494	if (IS_ERR(i2c_imx->clk))
1495		return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
1496				     "can't get I2C clock\n");
 
 
 
 
 
 
 
 
 
1497
1498	/* Init queue */
1499	init_waitqueue_head(&i2c_imx->queue);
1500
1501	/* Set up adapter data */
1502	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1503
1504	/* Set up platform driver data */
1505	platform_set_drvdata(pdev, i2c_imx);
1506
1507	pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1508	pm_runtime_use_autosuspend(&pdev->dev);
1509	pm_runtime_set_active(&pdev->dev);
1510	pm_runtime_enable(&pdev->dev);
1511
1512	ret = pm_runtime_get_sync(&pdev->dev);
1513	if (ret < 0)
1514		goto rpm_disable;
1515
1516	/* Request IRQ */
1517	ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED, pdev->name, i2c_imx);
1518	if (ret) {
1519		dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1520		goto rpm_disable;
1521	}
1522
1523	/* Set up clock divider */
1524	i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1525	ret = of_property_read_u32(pdev->dev.of_node,
1526				   "clock-frequency", &i2c_imx->bitrate);
1527	if (ret < 0 && pdata && pdata->bitrate)
1528		i2c_imx->bitrate = pdata->bitrate;
1529	i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1530	clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1531	i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1532
1533	i2c_imx_reset_regs(i2c_imx);
1534
1535	/* Init optional bus recovery function */
1536	ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1537	/* Give it another chance if pinctrl used is not ready yet */
1538	if (ret == -EPROBE_DEFER)
1539		goto clk_notifier_unregister;
1540
1541	/* Add I2C adapter */
1542	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1543	if (ret < 0)
1544		goto clk_notifier_unregister;
 
 
1545
1546	pm_runtime_mark_last_busy(&pdev->dev);
1547	pm_runtime_put_autosuspend(&pdev->dev);
1548
1549	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1550	dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
 
 
 
1551	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1552		i2c_imx->adapter.name);
1553	dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1554
1555	/* Init DMA config if supported */
1556	i2c_imx_dma_request(i2c_imx, phy_addr);
1557
1558	return 0;   /* Return OK */
1559
1560clk_notifier_unregister:
1561	clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1562	free_irq(irq, i2c_imx);
1563rpm_disable:
1564	pm_runtime_put_noidle(&pdev->dev);
1565	pm_runtime_disable(&pdev->dev);
1566	pm_runtime_set_suspended(&pdev->dev);
1567	pm_runtime_dont_use_autosuspend(&pdev->dev);
1568	return ret;
 
 
 
 
 
1569}
1570
1571static void i2c_imx_remove(struct platform_device *pdev)
1572{
1573	struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1574	int irq, ret;
1575
1576	ret = pm_runtime_get_sync(&pdev->dev);
1577
1578	hrtimer_cancel(&i2c_imx->slave_timer);
1579
1580	/* remove adapter */
1581	dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1582	i2c_del_adapter(&i2c_imx->adapter);
 
1583
1584	if (i2c_imx->dma)
1585		i2c_imx_dma_free(i2c_imx);
1586
1587	if (ret >= 0) {
1588		/* setup chip registers to defaults */
1589		imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1590		imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1591		imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1592		imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1593	}
1594
1595	clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1596	irq = platform_get_irq(pdev, 0);
1597	if (irq >= 0)
1598		free_irq(irq, i2c_imx);
1599
1600	pm_runtime_put_noidle(&pdev->dev);
1601	pm_runtime_disable(&pdev->dev);
1602}
1603
1604static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1605{
1606	struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1607
1608	clk_disable(i2c_imx->clk);
1609
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1610	return 0;
1611}
1612
1613static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1614{
1615	struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1616	int ret;
1617
1618	ret = clk_enable(i2c_imx->clk);
1619	if (ret)
1620		dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1621
1622	return ret;
1623}
1624
1625static const struct dev_pm_ops i2c_imx_pm_ops = {
1626	SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1627			   i2c_imx_runtime_resume, NULL)
1628};
1629
1630static struct platform_driver i2c_imx_driver = {
1631	.probe = i2c_imx_probe,
1632	.remove_new = i2c_imx_remove,
1633	.driver = {
1634		.name = DRIVER_NAME,
1635		.pm = &i2c_imx_pm_ops,
1636		.of_match_table = i2c_imx_dt_ids,
1637		.acpi_match_table = i2c_imx_acpi_ids,
1638	},
1639	.id_table = imx_i2c_devtype,
1640};
1641
1642static int __init i2c_adap_imx_init(void)
1643{
1644	return platform_driver_register(&i2c_imx_driver);
1645}
1646subsys_initcall(i2c_adap_imx_init);
1647
1648static void __exit i2c_adap_imx_exit(void)
1649{
1650	platform_driver_unregister(&i2c_imx_driver);
1651}
1652module_exit(i2c_adap_imx_exit);
1653
1654MODULE_LICENSE("GPL");
1655MODULE_AUTHOR("Darius Augulis");
1656MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1657MODULE_ALIAS("platform:" DRIVER_NAME);