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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2009 Samsung Electronics Co., Ltd.
4// Jaswinder Singh <jassi.brar@samsung.com>
5
6#include <linux/init.h>
7#include <linux/module.h>
8#include <linux/interrupt.h>
9#include <linux/delay.h>
10#include <linux/clk.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/spi/spi.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18
19#include <linux/platform_data/spi-s3c64xx.h>
20
21#define MAX_SPI_PORTS 12
22#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
23#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
24#define AUTOSUSPEND_TIMEOUT 2000
25
26/* Registers and bit-fields */
27
28#define S3C64XX_SPI_CH_CFG 0x00
29#define S3C64XX_SPI_CLK_CFG 0x04
30#define S3C64XX_SPI_MODE_CFG 0x08
31#define S3C64XX_SPI_CS_REG 0x0C
32#define S3C64XX_SPI_INT_EN 0x10
33#define S3C64XX_SPI_STATUS 0x14
34#define S3C64XX_SPI_TX_DATA 0x18
35#define S3C64XX_SPI_RX_DATA 0x1C
36#define S3C64XX_SPI_PACKET_CNT 0x20
37#define S3C64XX_SPI_PENDING_CLR 0x24
38#define S3C64XX_SPI_SWAP_CFG 0x28
39#define S3C64XX_SPI_FB_CLK 0x2C
40
41#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
42#define S3C64XX_SPI_CH_SW_RST (1<<5)
43#define S3C64XX_SPI_CH_SLAVE (1<<4)
44#define S3C64XX_SPI_CPOL_L (1<<3)
45#define S3C64XX_SPI_CPHA_B (1<<2)
46#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
47#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
48
49#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
50#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
51#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
52#define S3C64XX_SPI_PSR_MASK 0xff
53
54#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
55#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
56#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
57#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
58#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
59#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
60#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
61#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
62#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3)
63#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
64#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
65#define S3C64XX_SPI_MODE_4BURST (1<<0)
66
67#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4)
68#define S3C64XX_SPI_CS_AUTO (1<<1)
69#define S3C64XX_SPI_CS_SIG_INACT (1<<0)
70
71#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
72#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
73#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
74#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
75#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
76#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
77#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
78
79#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
80#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
81#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
82#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
83#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
84#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
85
86#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
87#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
88
89#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
90#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
91#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
92#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
93#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
94
95#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
96#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
97#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
98#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
99#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
100#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
101#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
102#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
103
104#define S3C64XX_SPI_FBCLK_MSK (3<<0)
105
106#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
107#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
108 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
109#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
110#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
111 FIFO_LVL_MASK(i))
112
113#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
114#define S3C64XX_SPI_TRAILCNT_OFF 19
115
116#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
117
118#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
119#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
120
121#define RXBUSY (1<<2)
122#define TXBUSY (1<<3)
123
124struct s3c64xx_spi_dma_data {
125 struct dma_chan *ch;
126 dma_cookie_t cookie;
127 enum dma_transfer_direction direction;
128};
129
130/**
131 * struct s3c64xx_spi_port_config - SPI Controller hardware info
132 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
133 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
134 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
135 * @clk_div: Internal clock divider
136 * @quirks: Bitmask of known quirks
137 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
138 * @clk_from_cmu: True, if the controller does not include a clock mux and
139 * prescaler unit.
140 * @clk_ioclk: True if clock is present on this device
141 * @has_loopback: True if loopback mode can be supported
142 *
143 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
144 * differ in some aspects such as the size of the fifo and spi bus clock
145 * setup. Such differences are specified to the driver using this structure
146 * which is provided as driver data to the driver.
147 */
148struct s3c64xx_spi_port_config {
149 int fifo_lvl_mask[MAX_SPI_PORTS];
150 int rx_lvl_offset;
151 int tx_st_done;
152 int quirks;
153 int clk_div;
154 bool high_speed;
155 bool clk_from_cmu;
156 bool clk_ioclk;
157 bool has_loopback;
158};
159
160/**
161 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
162 * @clk: Pointer to the spi clock.
163 * @src_clk: Pointer to the clock used to generate SPI signals.
164 * @ioclk: Pointer to the i/o clock between master and slave
165 * @pdev: Pointer to device's platform device data
166 * @master: Pointer to the SPI Protocol master.
167 * @cntrlr_info: Platform specific data for the controller this driver manages.
168 * @lock: Controller specific lock.
169 * @state: Set of FLAGS to indicate status.
170 * @sfr_start: BUS address of SPI controller regs.
171 * @regs: Pointer to ioremap'ed controller registers.
172 * @xfer_completion: To indicate completion of xfer task.
173 * @cur_mode: Stores the active configuration of the controller.
174 * @cur_bpw: Stores the active bits per word settings.
175 * @cur_speed: Current clock speed
176 * @rx_dma: Local receive DMA data (e.g. chan and direction)
177 * @tx_dma: Local transmit DMA data (e.g. chan and direction)
178 * @port_conf: Local SPI port configuartion data
179 * @port_id: Port identification number
180 */
181struct s3c64xx_spi_driver_data {
182 void __iomem *regs;
183 struct clk *clk;
184 struct clk *src_clk;
185 struct clk *ioclk;
186 struct platform_device *pdev;
187 struct spi_master *master;
188 struct s3c64xx_spi_info *cntrlr_info;
189 spinlock_t lock;
190 unsigned long sfr_start;
191 struct completion xfer_completion;
192 unsigned state;
193 unsigned cur_mode, cur_bpw;
194 unsigned cur_speed;
195 struct s3c64xx_spi_dma_data rx_dma;
196 struct s3c64xx_spi_dma_data tx_dma;
197 const struct s3c64xx_spi_port_config *port_conf;
198 unsigned int port_id;
199};
200
201static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
202{
203 void __iomem *regs = sdd->regs;
204 unsigned long loops;
205 u32 val;
206
207 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
208
209 val = readl(regs + S3C64XX_SPI_CH_CFG);
210 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
211 writel(val, regs + S3C64XX_SPI_CH_CFG);
212
213 val = readl(regs + S3C64XX_SPI_CH_CFG);
214 val |= S3C64XX_SPI_CH_SW_RST;
215 val &= ~S3C64XX_SPI_CH_HS_EN;
216 writel(val, regs + S3C64XX_SPI_CH_CFG);
217
218 /* Flush TxFIFO*/
219 loops = msecs_to_loops(1);
220 do {
221 val = readl(regs + S3C64XX_SPI_STATUS);
222 } while (TX_FIFO_LVL(val, sdd) && loops--);
223
224 if (loops == 0)
225 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
226
227 /* Flush RxFIFO*/
228 loops = msecs_to_loops(1);
229 do {
230 val = readl(regs + S3C64XX_SPI_STATUS);
231 if (RX_FIFO_LVL(val, sdd))
232 readl(regs + S3C64XX_SPI_RX_DATA);
233 else
234 break;
235 } while (loops--);
236
237 if (loops == 0)
238 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
239
240 val = readl(regs + S3C64XX_SPI_CH_CFG);
241 val &= ~S3C64XX_SPI_CH_SW_RST;
242 writel(val, regs + S3C64XX_SPI_CH_CFG);
243
244 val = readl(regs + S3C64XX_SPI_MODE_CFG);
245 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
246 writel(val, regs + S3C64XX_SPI_MODE_CFG);
247}
248
249static void s3c64xx_spi_dmacb(void *data)
250{
251 struct s3c64xx_spi_driver_data *sdd;
252 struct s3c64xx_spi_dma_data *dma = data;
253 unsigned long flags;
254
255 if (dma->direction == DMA_DEV_TO_MEM)
256 sdd = container_of(data,
257 struct s3c64xx_spi_driver_data, rx_dma);
258 else
259 sdd = container_of(data,
260 struct s3c64xx_spi_driver_data, tx_dma);
261
262 spin_lock_irqsave(&sdd->lock, flags);
263
264 if (dma->direction == DMA_DEV_TO_MEM) {
265 sdd->state &= ~RXBUSY;
266 if (!(sdd->state & TXBUSY))
267 complete(&sdd->xfer_completion);
268 } else {
269 sdd->state &= ~TXBUSY;
270 if (!(sdd->state & RXBUSY))
271 complete(&sdd->xfer_completion);
272 }
273
274 spin_unlock_irqrestore(&sdd->lock, flags);
275}
276
277static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
278 struct sg_table *sgt)
279{
280 struct s3c64xx_spi_driver_data *sdd;
281 struct dma_slave_config config;
282 struct dma_async_tx_descriptor *desc;
283 int ret;
284
285 memset(&config, 0, sizeof(config));
286
287 if (dma->direction == DMA_DEV_TO_MEM) {
288 sdd = container_of((void *)dma,
289 struct s3c64xx_spi_driver_data, rx_dma);
290 config.direction = dma->direction;
291 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
292 config.src_addr_width = sdd->cur_bpw / 8;
293 config.src_maxburst = 1;
294 dmaengine_slave_config(dma->ch, &config);
295 } else {
296 sdd = container_of((void *)dma,
297 struct s3c64xx_spi_driver_data, tx_dma);
298 config.direction = dma->direction;
299 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
300 config.dst_addr_width = sdd->cur_bpw / 8;
301 config.dst_maxburst = 1;
302 dmaengine_slave_config(dma->ch, &config);
303 }
304
305 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
306 dma->direction, DMA_PREP_INTERRUPT);
307 if (!desc) {
308 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
309 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
310 return -ENOMEM;
311 }
312
313 desc->callback = s3c64xx_spi_dmacb;
314 desc->callback_param = dma;
315
316 dma->cookie = dmaengine_submit(desc);
317 ret = dma_submit_error(dma->cookie);
318 if (ret) {
319 dev_err(&sdd->pdev->dev, "DMA submission failed");
320 return -EIO;
321 }
322
323 dma_async_issue_pending(dma->ch);
324 return 0;
325}
326
327static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
328{
329 struct s3c64xx_spi_driver_data *sdd =
330 spi_master_get_devdata(spi->master);
331
332 if (sdd->cntrlr_info->no_cs)
333 return;
334
335 if (enable) {
336 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
337 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
338 } else {
339 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
340
341 ssel |= (S3C64XX_SPI_CS_AUTO |
342 S3C64XX_SPI_CS_NSC_CNT_2);
343 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
344 }
345 } else {
346 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
347 writel(S3C64XX_SPI_CS_SIG_INACT,
348 sdd->regs + S3C64XX_SPI_CS_REG);
349 }
350}
351
352static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
353{
354 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
355
356 if (is_polling(sdd))
357 return 0;
358
359 /* Requests DMA channels */
360 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx");
361 if (IS_ERR(sdd->rx_dma.ch)) {
362 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n");
363 sdd->rx_dma.ch = NULL;
364 return 0;
365 }
366
367 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx");
368 if (IS_ERR(sdd->tx_dma.ch)) {
369 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n");
370 dma_release_channel(sdd->rx_dma.ch);
371 sdd->tx_dma.ch = NULL;
372 sdd->rx_dma.ch = NULL;
373 return 0;
374 }
375
376 spi->dma_rx = sdd->rx_dma.ch;
377 spi->dma_tx = sdd->tx_dma.ch;
378
379 return 0;
380}
381
382static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
383{
384 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
385
386 if (is_polling(sdd))
387 return 0;
388
389 /* Releases DMA channels if they are allocated */
390 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
391 dma_release_channel(sdd->rx_dma.ch);
392 dma_release_channel(sdd->tx_dma.ch);
393 sdd->rx_dma.ch = NULL;
394 sdd->tx_dma.ch = NULL;
395 }
396
397 return 0;
398}
399
400static bool s3c64xx_spi_can_dma(struct spi_master *master,
401 struct spi_device *spi,
402 struct spi_transfer *xfer)
403{
404 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
405
406 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
407 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
408 } else {
409 return false;
410 }
411
412}
413
414static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
415 struct spi_transfer *xfer, int dma_mode)
416{
417 void __iomem *regs = sdd->regs;
418 u32 modecfg, chcfg;
419 int ret = 0;
420
421 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
422 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
423
424 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
425 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
426
427 if (dma_mode) {
428 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
429 } else {
430 /* Always shift in data in FIFO, even if xfer is Tx only,
431 * this helps setting PCKT_CNT value for generating clocks
432 * as exactly needed.
433 */
434 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
435 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
436 | S3C64XX_SPI_PACKET_CNT_EN,
437 regs + S3C64XX_SPI_PACKET_CNT);
438 }
439
440 if (xfer->tx_buf != NULL) {
441 sdd->state |= TXBUSY;
442 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
443 if (dma_mode) {
444 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
445 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
446 } else {
447 switch (sdd->cur_bpw) {
448 case 32:
449 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
450 xfer->tx_buf, xfer->len / 4);
451 break;
452 case 16:
453 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
454 xfer->tx_buf, xfer->len / 2);
455 break;
456 default:
457 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
458 xfer->tx_buf, xfer->len);
459 break;
460 }
461 }
462 }
463
464 if (xfer->rx_buf != NULL) {
465 sdd->state |= RXBUSY;
466
467 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
468 && !(sdd->cur_mode & SPI_CPHA))
469 chcfg |= S3C64XX_SPI_CH_HS_EN;
470
471 if (dma_mode) {
472 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
473 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
474 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
475 | S3C64XX_SPI_PACKET_CNT_EN,
476 regs + S3C64XX_SPI_PACKET_CNT);
477 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
478 }
479 }
480
481 if (ret)
482 return ret;
483
484 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
485 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
486
487 return 0;
488}
489
490static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
491 int timeout_ms)
492{
493 void __iomem *regs = sdd->regs;
494 unsigned long val = 1;
495 u32 status;
496
497 /* max fifo depth available */
498 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
499
500 if (timeout_ms)
501 val = msecs_to_loops(timeout_ms);
502
503 do {
504 status = readl(regs + S3C64XX_SPI_STATUS);
505 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
506
507 /* return the actual received data length */
508 return RX_FIFO_LVL(status, sdd);
509}
510
511static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
512 struct spi_transfer *xfer)
513{
514 void __iomem *regs = sdd->regs;
515 unsigned long val;
516 u32 status;
517 int ms;
518
519 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
520 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
521 ms += 30; /* some tolerance */
522 ms = max(ms, 100); /* minimum timeout */
523
524 val = msecs_to_jiffies(ms) + 10;
525 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
526
527 /*
528 * If the previous xfer was completed within timeout, then
529 * proceed further else return -EIO.
530 * DmaTx returns after simply writing data in the FIFO,
531 * w/o waiting for real transmission on the bus to finish.
532 * DmaRx returns only after Dma read data from FIFO which
533 * needs bus transmission to finish, so we don't worry if
534 * Xfer involved Rx(with or without Tx).
535 */
536 if (val && !xfer->rx_buf) {
537 val = msecs_to_loops(10);
538 status = readl(regs + S3C64XX_SPI_STATUS);
539 while ((TX_FIFO_LVL(status, sdd)
540 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
541 && --val) {
542 cpu_relax();
543 status = readl(regs + S3C64XX_SPI_STATUS);
544 }
545
546 }
547
548 /* If timed out while checking rx/tx status return error */
549 if (!val)
550 return -EIO;
551
552 return 0;
553}
554
555static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
556 struct spi_transfer *xfer)
557{
558 void __iomem *regs = sdd->regs;
559 unsigned long val;
560 u32 status;
561 int loops;
562 u32 cpy_len;
563 u8 *buf;
564 int ms;
565
566 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
567 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
568 ms += 10; /* some tolerance */
569
570 val = msecs_to_loops(ms);
571 do {
572 status = readl(regs + S3C64XX_SPI_STATUS);
573 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
574
575 if (!val)
576 return -EIO;
577
578 /* If it was only Tx */
579 if (!xfer->rx_buf) {
580 sdd->state &= ~TXBUSY;
581 return 0;
582 }
583
584 /*
585 * If the receive length is bigger than the controller fifo
586 * size, calculate the loops and read the fifo as many times.
587 * loops = length / max fifo size (calculated by using the
588 * fifo mask).
589 * For any size less than the fifo size the below code is
590 * executed atleast once.
591 */
592 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
593 buf = xfer->rx_buf;
594 do {
595 /* wait for data to be received in the fifo */
596 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
597 (loops ? ms : 0));
598
599 switch (sdd->cur_bpw) {
600 case 32:
601 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
602 buf, cpy_len / 4);
603 break;
604 case 16:
605 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
606 buf, cpy_len / 2);
607 break;
608 default:
609 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
610 buf, cpy_len);
611 break;
612 }
613
614 buf = buf + cpy_len;
615 } while (loops--);
616 sdd->state &= ~RXBUSY;
617
618 return 0;
619}
620
621static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
622{
623 void __iomem *regs = sdd->regs;
624 int ret;
625 u32 val;
626 int div = sdd->port_conf->clk_div;
627
628 /* Disable Clock */
629 if (!sdd->port_conf->clk_from_cmu) {
630 val = readl(regs + S3C64XX_SPI_CLK_CFG);
631 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
632 writel(val, regs + S3C64XX_SPI_CLK_CFG);
633 }
634
635 /* Set Polarity and Phase */
636 val = readl(regs + S3C64XX_SPI_CH_CFG);
637 val &= ~(S3C64XX_SPI_CH_SLAVE |
638 S3C64XX_SPI_CPOL_L |
639 S3C64XX_SPI_CPHA_B);
640
641 if (sdd->cur_mode & SPI_CPOL)
642 val |= S3C64XX_SPI_CPOL_L;
643
644 if (sdd->cur_mode & SPI_CPHA)
645 val |= S3C64XX_SPI_CPHA_B;
646
647 writel(val, regs + S3C64XX_SPI_CH_CFG);
648
649 /* Set Channel & DMA Mode */
650 val = readl(regs + S3C64XX_SPI_MODE_CFG);
651 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
652 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
653
654 switch (sdd->cur_bpw) {
655 case 32:
656 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
657 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
658 break;
659 case 16:
660 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
661 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
662 break;
663 default:
664 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
665 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
666 break;
667 }
668
669 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback)
670 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK;
671
672 writel(val, regs + S3C64XX_SPI_MODE_CFG);
673
674 if (sdd->port_conf->clk_from_cmu) {
675 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div);
676 if (ret)
677 return ret;
678 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div;
679 } else {
680 /* Configure Clock */
681 val = readl(regs + S3C64XX_SPI_CLK_CFG);
682 val &= ~S3C64XX_SPI_PSR_MASK;
683 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1)
684 & S3C64XX_SPI_PSR_MASK);
685 writel(val, regs + S3C64XX_SPI_CLK_CFG);
686
687 /* Enable Clock */
688 val = readl(regs + S3C64XX_SPI_CLK_CFG);
689 val |= S3C64XX_SPI_ENCLK_ENABLE;
690 writel(val, regs + S3C64XX_SPI_CLK_CFG);
691 }
692
693 return 0;
694}
695
696#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
697
698static int s3c64xx_spi_prepare_message(struct spi_master *master,
699 struct spi_message *msg)
700{
701 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
702 struct spi_device *spi = msg->spi;
703 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
704
705 /* Configure feedback delay */
706 if (!cs)
707 /* No delay if not defined */
708 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
709 else
710 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
711
712 return 0;
713}
714
715static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
716{
717 struct spi_controller *ctlr = spi->controller;
718
719 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
720}
721
722static int s3c64xx_spi_transfer_one(struct spi_master *master,
723 struct spi_device *spi,
724 struct spi_transfer *xfer)
725{
726 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
727 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
728 const void *tx_buf = NULL;
729 void *rx_buf = NULL;
730 int target_len = 0, origin_len = 0;
731 int use_dma = 0;
732 int status;
733 u32 speed;
734 u8 bpw;
735 unsigned long flags;
736
737 reinit_completion(&sdd->xfer_completion);
738
739 /* Only BPW and Speed may change across transfers */
740 bpw = xfer->bits_per_word;
741 speed = xfer->speed_hz;
742
743 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
744 sdd->cur_bpw = bpw;
745 sdd->cur_speed = speed;
746 sdd->cur_mode = spi->mode;
747 status = s3c64xx_spi_config(sdd);
748 if (status)
749 return status;
750 }
751
752 if (!is_polling(sdd) && (xfer->len > fifo_len) &&
753 sdd->rx_dma.ch && sdd->tx_dma.ch) {
754 use_dma = 1;
755
756 } else if (xfer->len > fifo_len) {
757 tx_buf = xfer->tx_buf;
758 rx_buf = xfer->rx_buf;
759 origin_len = xfer->len;
760
761 target_len = xfer->len;
762 if (xfer->len > fifo_len)
763 xfer->len = fifo_len;
764 }
765
766 do {
767 spin_lock_irqsave(&sdd->lock, flags);
768
769 /* Pending only which is to be done */
770 sdd->state &= ~RXBUSY;
771 sdd->state &= ~TXBUSY;
772
773 /* Start the signals */
774 s3c64xx_spi_set_cs(spi, true);
775
776 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
777
778 spin_unlock_irqrestore(&sdd->lock, flags);
779
780 if (status) {
781 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
782 break;
783 }
784
785 if (use_dma)
786 status = s3c64xx_wait_for_dma(sdd, xfer);
787 else
788 status = s3c64xx_wait_for_pio(sdd, xfer);
789
790 if (status) {
791 dev_err(&spi->dev,
792 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
793 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
794 (sdd->state & RXBUSY) ? 'f' : 'p',
795 (sdd->state & TXBUSY) ? 'f' : 'p',
796 xfer->len, use_dma ? 1 : 0, status);
797
798 if (use_dma) {
799 struct dma_tx_state s;
800
801 if (xfer->tx_buf && (sdd->state & TXBUSY)) {
802 dmaengine_pause(sdd->tx_dma.ch);
803 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
804 dmaengine_terminate_all(sdd->tx_dma.ch);
805 dev_err(&spi->dev, "TX residue: %d\n", s.residue);
806
807 }
808 if (xfer->rx_buf && (sdd->state & RXBUSY)) {
809 dmaengine_pause(sdd->rx_dma.ch);
810 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
811 dmaengine_terminate_all(sdd->rx_dma.ch);
812 dev_err(&spi->dev, "RX residue: %d\n", s.residue);
813 }
814 }
815 } else {
816 s3c64xx_flush_fifo(sdd);
817 }
818 if (target_len > 0) {
819 target_len -= xfer->len;
820
821 if (xfer->tx_buf)
822 xfer->tx_buf += xfer->len;
823
824 if (xfer->rx_buf)
825 xfer->rx_buf += xfer->len;
826
827 if (target_len > fifo_len)
828 xfer->len = fifo_len;
829 else
830 xfer->len = target_len;
831 }
832 } while (target_len > 0);
833
834 if (origin_len) {
835 /* Restore original xfer buffers and length */
836 xfer->tx_buf = tx_buf;
837 xfer->rx_buf = rx_buf;
838 xfer->len = origin_len;
839 }
840
841 return status;
842}
843
844static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
845 struct spi_device *spi)
846{
847 struct s3c64xx_spi_csinfo *cs;
848 struct device_node *slave_np, *data_np = NULL;
849 u32 fb_delay = 0;
850
851 slave_np = spi->dev.of_node;
852 if (!slave_np) {
853 dev_err(&spi->dev, "device node not found\n");
854 return ERR_PTR(-EINVAL);
855 }
856
857 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
858 if (!cs)
859 return ERR_PTR(-ENOMEM);
860
861 data_np = of_get_child_by_name(slave_np, "controller-data");
862 if (!data_np) {
863 dev_info(&spi->dev, "feedback delay set to default (0)\n");
864 return cs;
865 }
866
867 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
868 cs->fb_delay = fb_delay;
869 of_node_put(data_np);
870 return cs;
871}
872
873/*
874 * Here we only check the validity of requested configuration
875 * and save the configuration in a local data-structure.
876 * The controller is actually configured only just before we
877 * get a message to transfer.
878 */
879static int s3c64xx_spi_setup(struct spi_device *spi)
880{
881 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
882 struct s3c64xx_spi_driver_data *sdd;
883 int err;
884 int div;
885
886 sdd = spi_master_get_devdata(spi->master);
887 if (spi->dev.of_node) {
888 cs = s3c64xx_get_slave_ctrldata(spi);
889 spi->controller_data = cs;
890 }
891
892 /* NULL is fine, we just avoid using the FB delay (=0) */
893 if (IS_ERR(cs)) {
894 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
895 return -ENODEV;
896 }
897
898 if (!spi_get_ctldata(spi))
899 spi_set_ctldata(spi, cs);
900
901 pm_runtime_get_sync(&sdd->pdev->dev);
902
903 div = sdd->port_conf->clk_div;
904
905 /* Check if we can provide the requested rate */
906 if (!sdd->port_conf->clk_from_cmu) {
907 u32 psr, speed;
908
909 /* Max possible */
910 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1);
911
912 if (spi->max_speed_hz > speed)
913 spi->max_speed_hz = speed;
914
915 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
916 psr &= S3C64XX_SPI_PSR_MASK;
917 if (psr == S3C64XX_SPI_PSR_MASK)
918 psr--;
919
920 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
921 if (spi->max_speed_hz < speed) {
922 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
923 psr++;
924 } else {
925 err = -EINVAL;
926 goto setup_exit;
927 }
928 }
929
930 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
931 if (spi->max_speed_hz >= speed) {
932 spi->max_speed_hz = speed;
933 } else {
934 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
935 spi->max_speed_hz);
936 err = -EINVAL;
937 goto setup_exit;
938 }
939 }
940
941 pm_runtime_mark_last_busy(&sdd->pdev->dev);
942 pm_runtime_put_autosuspend(&sdd->pdev->dev);
943 s3c64xx_spi_set_cs(spi, false);
944
945 return 0;
946
947setup_exit:
948 pm_runtime_mark_last_busy(&sdd->pdev->dev);
949 pm_runtime_put_autosuspend(&sdd->pdev->dev);
950 /* setup() returns with device de-selected */
951 s3c64xx_spi_set_cs(spi, false);
952
953 spi_set_ctldata(spi, NULL);
954
955 /* This was dynamically allocated on the DT path */
956 if (spi->dev.of_node)
957 kfree(cs);
958
959 return err;
960}
961
962static void s3c64xx_spi_cleanup(struct spi_device *spi)
963{
964 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
965
966 /* This was dynamically allocated on the DT path */
967 if (spi->dev.of_node)
968 kfree(cs);
969
970 spi_set_ctldata(spi, NULL);
971}
972
973static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
974{
975 struct s3c64xx_spi_driver_data *sdd = data;
976 struct spi_master *spi = sdd->master;
977 unsigned int val, clr = 0;
978
979 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
980
981 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
982 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
983 dev_err(&spi->dev, "RX overrun\n");
984 }
985 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
986 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
987 dev_err(&spi->dev, "RX underrun\n");
988 }
989 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
990 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
991 dev_err(&spi->dev, "TX overrun\n");
992 }
993 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
994 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
995 dev_err(&spi->dev, "TX underrun\n");
996 }
997
998 /* Clear the pending irq by setting and then clearing it */
999 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1000 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1001
1002 return IRQ_HANDLED;
1003}
1004
1005static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
1006{
1007 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1008 void __iomem *regs = sdd->regs;
1009 unsigned int val;
1010
1011 sdd->cur_speed = 0;
1012
1013 if (sci->no_cs)
1014 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
1015 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
1016 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
1017
1018 /* Disable Interrupts - we use Polling if not DMA mode */
1019 writel(0, regs + S3C64XX_SPI_INT_EN);
1020
1021 if (!sdd->port_conf->clk_from_cmu)
1022 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1023 regs + S3C64XX_SPI_CLK_CFG);
1024 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1025 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1026
1027 /* Clear any irq pending bits, should set and clear the bits */
1028 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1029 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1030 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1031 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1032 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1033 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1034
1035 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1036
1037 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1038 val &= ~S3C64XX_SPI_MODE_4BURST;
1039 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1040 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1041 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1042
1043 s3c64xx_flush_fifo(sdd);
1044}
1045
1046#ifdef CONFIG_OF
1047static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1048{
1049 struct s3c64xx_spi_info *sci;
1050 u32 temp;
1051
1052 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1053 if (!sci)
1054 return ERR_PTR(-ENOMEM);
1055
1056 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1057 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1058 sci->src_clk_nr = 0;
1059 } else {
1060 sci->src_clk_nr = temp;
1061 }
1062
1063 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1064 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1065 sci->num_cs = 1;
1066 } else {
1067 sci->num_cs = temp;
1068 }
1069
1070 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1071
1072 return sci;
1073}
1074#else
1075static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1076{
1077 return dev_get_platdata(dev);
1078}
1079#endif
1080
1081static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1082 struct platform_device *pdev)
1083{
1084#ifdef CONFIG_OF
1085 if (pdev->dev.of_node)
1086 return of_device_get_match_data(&pdev->dev);
1087#endif
1088 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1089}
1090
1091static int s3c64xx_spi_probe(struct platform_device *pdev)
1092{
1093 struct resource *mem_res;
1094 struct s3c64xx_spi_driver_data *sdd;
1095 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1096 struct spi_master *master;
1097 int ret, irq;
1098 char clk_name[16];
1099
1100 if (!sci && pdev->dev.of_node) {
1101 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1102 if (IS_ERR(sci))
1103 return PTR_ERR(sci);
1104 }
1105
1106 if (!sci) {
1107 dev_err(&pdev->dev, "platform_data missing!\n");
1108 return -ENODEV;
1109 }
1110
1111 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1112 if (mem_res == NULL) {
1113 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1114 return -ENXIO;
1115 }
1116
1117 irq = platform_get_irq(pdev, 0);
1118 if (irq < 0) {
1119 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1120 return irq;
1121 }
1122
1123 master = spi_alloc_master(&pdev->dev,
1124 sizeof(struct s3c64xx_spi_driver_data));
1125 if (master == NULL) {
1126 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1127 return -ENOMEM;
1128 }
1129
1130 platform_set_drvdata(pdev, master);
1131
1132 sdd = spi_master_get_devdata(master);
1133 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1134 sdd->master = master;
1135 sdd->cntrlr_info = sci;
1136 sdd->pdev = pdev;
1137 sdd->sfr_start = mem_res->start;
1138 if (pdev->dev.of_node) {
1139 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1140 if (ret < 0) {
1141 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1142 ret);
1143 goto err_deref_master;
1144 }
1145 sdd->port_id = ret;
1146 } else {
1147 sdd->port_id = pdev->id;
1148 }
1149
1150 sdd->cur_bpw = 8;
1151
1152 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1153 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1154
1155 master->dev.of_node = pdev->dev.of_node;
1156 master->bus_num = sdd->port_id;
1157 master->setup = s3c64xx_spi_setup;
1158 master->cleanup = s3c64xx_spi_cleanup;
1159 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1160 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1161 master->prepare_message = s3c64xx_spi_prepare_message;
1162 master->transfer_one = s3c64xx_spi_transfer_one;
1163 master->max_transfer_size = s3c64xx_spi_max_transfer_size;
1164 master->num_chipselect = sci->num_cs;
1165 master->use_gpio_descriptors = true;
1166 master->dma_alignment = 8;
1167 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1168 SPI_BPW_MASK(8);
1169 /* the spi->mode bits understood by this driver: */
1170 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1171 if (sdd->port_conf->has_loopback)
1172 master->mode_bits |= SPI_LOOP;
1173 master->auto_runtime_pm = true;
1174 if (!is_polling(sdd))
1175 master->can_dma = s3c64xx_spi_can_dma;
1176
1177 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1178 if (IS_ERR(sdd->regs)) {
1179 ret = PTR_ERR(sdd->regs);
1180 goto err_deref_master;
1181 }
1182
1183 if (sci->cfg_gpio && sci->cfg_gpio()) {
1184 dev_err(&pdev->dev, "Unable to config gpio\n");
1185 ret = -EBUSY;
1186 goto err_deref_master;
1187 }
1188
1189 /* Setup clocks */
1190 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1191 if (IS_ERR(sdd->clk)) {
1192 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1193 ret = PTR_ERR(sdd->clk);
1194 goto err_deref_master;
1195 }
1196
1197 ret = clk_prepare_enable(sdd->clk);
1198 if (ret) {
1199 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1200 goto err_deref_master;
1201 }
1202
1203 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1204 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1205 if (IS_ERR(sdd->src_clk)) {
1206 dev_err(&pdev->dev,
1207 "Unable to acquire clock '%s'\n", clk_name);
1208 ret = PTR_ERR(sdd->src_clk);
1209 goto err_disable_clk;
1210 }
1211
1212 ret = clk_prepare_enable(sdd->src_clk);
1213 if (ret) {
1214 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1215 goto err_disable_clk;
1216 }
1217
1218 if (sdd->port_conf->clk_ioclk) {
1219 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1220 if (IS_ERR(sdd->ioclk)) {
1221 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1222 ret = PTR_ERR(sdd->ioclk);
1223 goto err_disable_src_clk;
1224 }
1225
1226 ret = clk_prepare_enable(sdd->ioclk);
1227 if (ret) {
1228 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1229 goto err_disable_src_clk;
1230 }
1231 }
1232
1233 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1234 pm_runtime_use_autosuspend(&pdev->dev);
1235 pm_runtime_set_active(&pdev->dev);
1236 pm_runtime_enable(&pdev->dev);
1237 pm_runtime_get_sync(&pdev->dev);
1238
1239 /* Setup Deufult Mode */
1240 s3c64xx_spi_hwinit(sdd);
1241
1242 spin_lock_init(&sdd->lock);
1243 init_completion(&sdd->xfer_completion);
1244
1245 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1246 "spi-s3c64xx", sdd);
1247 if (ret != 0) {
1248 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1249 irq, ret);
1250 goto err_pm_put;
1251 }
1252
1253 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1254 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1255 sdd->regs + S3C64XX_SPI_INT_EN);
1256
1257 ret = devm_spi_register_master(&pdev->dev, master);
1258 if (ret != 0) {
1259 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1260 goto err_pm_put;
1261 }
1262
1263 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1264 sdd->port_id, master->num_chipselect);
1265 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1266 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1267
1268 pm_runtime_mark_last_busy(&pdev->dev);
1269 pm_runtime_put_autosuspend(&pdev->dev);
1270
1271 return 0;
1272
1273err_pm_put:
1274 pm_runtime_put_noidle(&pdev->dev);
1275 pm_runtime_disable(&pdev->dev);
1276 pm_runtime_set_suspended(&pdev->dev);
1277
1278 clk_disable_unprepare(sdd->ioclk);
1279err_disable_src_clk:
1280 clk_disable_unprepare(sdd->src_clk);
1281err_disable_clk:
1282 clk_disable_unprepare(sdd->clk);
1283err_deref_master:
1284 spi_master_put(master);
1285
1286 return ret;
1287}
1288
1289static int s3c64xx_spi_remove(struct platform_device *pdev)
1290{
1291 struct spi_master *master = platform_get_drvdata(pdev);
1292 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1293
1294 pm_runtime_get_sync(&pdev->dev);
1295
1296 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1297
1298 if (!is_polling(sdd)) {
1299 dma_release_channel(sdd->rx_dma.ch);
1300 dma_release_channel(sdd->tx_dma.ch);
1301 }
1302
1303 clk_disable_unprepare(sdd->ioclk);
1304
1305 clk_disable_unprepare(sdd->src_clk);
1306
1307 clk_disable_unprepare(sdd->clk);
1308
1309 pm_runtime_put_noidle(&pdev->dev);
1310 pm_runtime_disable(&pdev->dev);
1311 pm_runtime_set_suspended(&pdev->dev);
1312
1313 return 0;
1314}
1315
1316#ifdef CONFIG_PM_SLEEP
1317static int s3c64xx_spi_suspend(struct device *dev)
1318{
1319 struct spi_master *master = dev_get_drvdata(dev);
1320 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1321
1322 int ret = spi_master_suspend(master);
1323 if (ret)
1324 return ret;
1325
1326 ret = pm_runtime_force_suspend(dev);
1327 if (ret < 0)
1328 return ret;
1329
1330 sdd->cur_speed = 0; /* Output Clock is stopped */
1331
1332 return 0;
1333}
1334
1335static int s3c64xx_spi_resume(struct device *dev)
1336{
1337 struct spi_master *master = dev_get_drvdata(dev);
1338 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1339 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1340 int ret;
1341
1342 if (sci->cfg_gpio)
1343 sci->cfg_gpio();
1344
1345 ret = pm_runtime_force_resume(dev);
1346 if (ret < 0)
1347 return ret;
1348
1349 return spi_master_resume(master);
1350}
1351#endif /* CONFIG_PM_SLEEP */
1352
1353#ifdef CONFIG_PM
1354static int s3c64xx_spi_runtime_suspend(struct device *dev)
1355{
1356 struct spi_master *master = dev_get_drvdata(dev);
1357 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1358
1359 clk_disable_unprepare(sdd->clk);
1360 clk_disable_unprepare(sdd->src_clk);
1361 clk_disable_unprepare(sdd->ioclk);
1362
1363 return 0;
1364}
1365
1366static int s3c64xx_spi_runtime_resume(struct device *dev)
1367{
1368 struct spi_master *master = dev_get_drvdata(dev);
1369 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1370 int ret;
1371
1372 if (sdd->port_conf->clk_ioclk) {
1373 ret = clk_prepare_enable(sdd->ioclk);
1374 if (ret != 0)
1375 return ret;
1376 }
1377
1378 ret = clk_prepare_enable(sdd->src_clk);
1379 if (ret != 0)
1380 goto err_disable_ioclk;
1381
1382 ret = clk_prepare_enable(sdd->clk);
1383 if (ret != 0)
1384 goto err_disable_src_clk;
1385
1386 s3c64xx_spi_hwinit(sdd);
1387
1388 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1389 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1390 sdd->regs + S3C64XX_SPI_INT_EN);
1391
1392 return 0;
1393
1394err_disable_src_clk:
1395 clk_disable_unprepare(sdd->src_clk);
1396err_disable_ioclk:
1397 clk_disable_unprepare(sdd->ioclk);
1398
1399 return ret;
1400}
1401#endif /* CONFIG_PM */
1402
1403static const struct dev_pm_ops s3c64xx_spi_pm = {
1404 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1405 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1406 s3c64xx_spi_runtime_resume, NULL)
1407};
1408
1409static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1410 .fifo_lvl_mask = { 0x7f },
1411 .rx_lvl_offset = 13,
1412 .tx_st_done = 21,
1413 .clk_div = 2,
1414 .high_speed = true,
1415};
1416
1417static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1418 .fifo_lvl_mask = { 0x7f, 0x7F },
1419 .rx_lvl_offset = 13,
1420 .tx_st_done = 21,
1421 .clk_div = 2,
1422};
1423
1424static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1425 .fifo_lvl_mask = { 0x1ff, 0x7F },
1426 .rx_lvl_offset = 15,
1427 .tx_st_done = 25,
1428 .clk_div = 2,
1429 .high_speed = true,
1430};
1431
1432static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1433 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1434 .rx_lvl_offset = 15,
1435 .tx_st_done = 25,
1436 .clk_div = 2,
1437 .high_speed = true,
1438 .clk_from_cmu = true,
1439 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1440};
1441
1442static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1443 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1444 .rx_lvl_offset = 15,
1445 .tx_st_done = 25,
1446 .clk_div = 2,
1447 .high_speed = true,
1448 .clk_from_cmu = true,
1449 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1450};
1451
1452static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1453 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1454 .rx_lvl_offset = 15,
1455 .tx_st_done = 25,
1456 .clk_div = 2,
1457 .high_speed = true,
1458 .clk_from_cmu = true,
1459 .clk_ioclk = true,
1460 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1461};
1462
1463static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
1464 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
1465 0x7f, 0x7f, 0x7f, 0x7f},
1466 .rx_lvl_offset = 15,
1467 .tx_st_done = 25,
1468 .clk_div = 4,
1469 .high_speed = true,
1470 .clk_from_cmu = true,
1471 .clk_ioclk = true,
1472 .has_loopback = true,
1473 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1474};
1475
1476static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
1477 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
1478 .rx_lvl_offset = 15,
1479 .tx_st_done = 25,
1480 .clk_div = 2,
1481 .high_speed = true,
1482 .clk_from_cmu = true,
1483 .clk_ioclk = false,
1484 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1485};
1486
1487static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1488 {
1489 .name = "s3c2443-spi",
1490 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1491 }, {
1492 .name = "s3c6410-spi",
1493 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1494 },
1495 { },
1496};
1497
1498static const struct of_device_id s3c64xx_spi_dt_match[] = {
1499 { .compatible = "samsung,s3c2443-spi",
1500 .data = (void *)&s3c2443_spi_port_config,
1501 },
1502 { .compatible = "samsung,s3c6410-spi",
1503 .data = (void *)&s3c6410_spi_port_config,
1504 },
1505 { .compatible = "samsung,s5pv210-spi",
1506 .data = (void *)&s5pv210_spi_port_config,
1507 },
1508 { .compatible = "samsung,exynos4210-spi",
1509 .data = (void *)&exynos4_spi_port_config,
1510 },
1511 { .compatible = "samsung,exynos7-spi",
1512 .data = (void *)&exynos7_spi_port_config,
1513 },
1514 { .compatible = "samsung,exynos5433-spi",
1515 .data = (void *)&exynos5433_spi_port_config,
1516 },
1517 { .compatible = "samsung,exynosautov9-spi",
1518 .data = (void *)&exynosautov9_spi_port_config,
1519 },
1520 { .compatible = "tesla,fsd-spi",
1521 .data = (void *)&fsd_spi_port_config,
1522 },
1523 { },
1524};
1525MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1526
1527static struct platform_driver s3c64xx_spi_driver = {
1528 .driver = {
1529 .name = "s3c64xx-spi",
1530 .pm = &s3c64xx_spi_pm,
1531 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1532 },
1533 .probe = s3c64xx_spi_probe,
1534 .remove = s3c64xx_spi_remove,
1535 .id_table = s3c64xx_spi_driver_ids,
1536};
1537MODULE_ALIAS("platform:s3c64xx-spi");
1538
1539module_platform_driver(s3c64xx_spi_driver);
1540
1541MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1542MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1543MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2009 Samsung Electronics Co., Ltd.
4// Jaswinder Singh <jassi.brar@samsung.com>
5
6#include <linux/init.h>
7#include <linux/module.h>
8#include <linux/interrupt.h>
9#include <linux/delay.h>
10#include <linux/clk.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/spi/spi.h>
16#include <linux/of.h>
17
18#include <linux/platform_data/spi-s3c64xx.h>
19
20#define MAX_SPI_PORTS 12
21#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
22#define AUTOSUSPEND_TIMEOUT 2000
23
24/* Registers and bit-fields */
25
26#define S3C64XX_SPI_CH_CFG 0x00
27#define S3C64XX_SPI_CLK_CFG 0x04
28#define S3C64XX_SPI_MODE_CFG 0x08
29#define S3C64XX_SPI_CS_REG 0x0C
30#define S3C64XX_SPI_INT_EN 0x10
31#define S3C64XX_SPI_STATUS 0x14
32#define S3C64XX_SPI_TX_DATA 0x18
33#define S3C64XX_SPI_RX_DATA 0x1C
34#define S3C64XX_SPI_PACKET_CNT 0x20
35#define S3C64XX_SPI_PENDING_CLR 0x24
36#define S3C64XX_SPI_SWAP_CFG 0x28
37#define S3C64XX_SPI_FB_CLK 0x2C
38
39#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
40#define S3C64XX_SPI_CH_SW_RST (1<<5)
41#define S3C64XX_SPI_CH_SLAVE (1<<4)
42#define S3C64XX_SPI_CPOL_L (1<<3)
43#define S3C64XX_SPI_CPHA_B (1<<2)
44#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
45#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
46
47#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
48#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
49#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
50#define S3C64XX_SPI_PSR_MASK 0xff
51
52#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
53#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
54#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
55#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
56#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
57#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
58#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
59#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
60#define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11)
61#define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11
62#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3)
63#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
64#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
65#define S3C64XX_SPI_MODE_4BURST (1<<0)
66
67#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4)
68#define S3C64XX_SPI_CS_AUTO (1<<1)
69#define S3C64XX_SPI_CS_SIG_INACT (1<<0)
70
71#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
72#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
73#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
74#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
75#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
76#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
77#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
78
79#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
80#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
81#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
82#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
83#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
84#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
85
86#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
87#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
88
89#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
90#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
91#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
92#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
93#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
94
95#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
96#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
97#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
98#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
99#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
100#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
101#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
102#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
103
104#define S3C64XX_SPI_FBCLK_MSK (3<<0)
105
106#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
107#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
108 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
109#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
110#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
111 FIFO_LVL_MASK(i))
112
113#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
114#define S3C64XX_SPI_TRAILCNT_OFF 19
115
116#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
117
118#define S3C64XX_SPI_POLLING_SIZE 32
119
120#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
121#define is_polling(x) (x->cntrlr_info->polling)
122
123#define RXBUSY (1<<2)
124#define TXBUSY (1<<3)
125
126struct s3c64xx_spi_dma_data {
127 struct dma_chan *ch;
128 dma_cookie_t cookie;
129 enum dma_transfer_direction direction;
130};
131
132/**
133 * struct s3c64xx_spi_port_config - SPI Controller hardware info
134 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
135 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
136 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
137 * @clk_div: Internal clock divider
138 * @quirks: Bitmask of known quirks
139 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
140 * @clk_from_cmu: True, if the controller does not include a clock mux and
141 * prescaler unit.
142 * @clk_ioclk: True if clock is present on this device
143 * @has_loopback: True if loopback mode can be supported
144 *
145 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
146 * differ in some aspects such as the size of the fifo and spi bus clock
147 * setup. Such differences are specified to the driver using this structure
148 * which is provided as driver data to the driver.
149 */
150struct s3c64xx_spi_port_config {
151 int fifo_lvl_mask[MAX_SPI_PORTS];
152 int rx_lvl_offset;
153 int tx_st_done;
154 int quirks;
155 int clk_div;
156 bool high_speed;
157 bool clk_from_cmu;
158 bool clk_ioclk;
159 bool has_loopback;
160};
161
162/**
163 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164 * @clk: Pointer to the spi clock.
165 * @src_clk: Pointer to the clock used to generate SPI signals.
166 * @ioclk: Pointer to the i/o clock between host and target
167 * @pdev: Pointer to device's platform device data
168 * @host: Pointer to the SPI Protocol host.
169 * @cntrlr_info: Platform specific data for the controller this driver manages.
170 * @lock: Controller specific lock.
171 * @state: Set of FLAGS to indicate status.
172 * @sfr_start: BUS address of SPI controller regs.
173 * @regs: Pointer to ioremap'ed controller registers.
174 * @xfer_completion: To indicate completion of xfer task.
175 * @cur_mode: Stores the active configuration of the controller.
176 * @cur_bpw: Stores the active bits per word settings.
177 * @cur_speed: Current clock speed
178 * @rx_dma: Local receive DMA data (e.g. chan and direction)
179 * @tx_dma: Local transmit DMA data (e.g. chan and direction)
180 * @port_conf: Local SPI port configuartion data
181 * @port_id: Port identification number
182 */
183struct s3c64xx_spi_driver_data {
184 void __iomem *regs;
185 struct clk *clk;
186 struct clk *src_clk;
187 struct clk *ioclk;
188 struct platform_device *pdev;
189 struct spi_controller *host;
190 struct s3c64xx_spi_info *cntrlr_info;
191 spinlock_t lock;
192 unsigned long sfr_start;
193 struct completion xfer_completion;
194 unsigned state;
195 unsigned cur_mode, cur_bpw;
196 unsigned cur_speed;
197 struct s3c64xx_spi_dma_data rx_dma;
198 struct s3c64xx_spi_dma_data tx_dma;
199 const struct s3c64xx_spi_port_config *port_conf;
200 unsigned int port_id;
201};
202
203static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
204{
205 void __iomem *regs = sdd->regs;
206 unsigned long loops;
207 u32 val;
208
209 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
210
211 val = readl(regs + S3C64XX_SPI_CH_CFG);
212 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
213 writel(val, regs + S3C64XX_SPI_CH_CFG);
214
215 val = readl(regs + S3C64XX_SPI_CH_CFG);
216 val |= S3C64XX_SPI_CH_SW_RST;
217 val &= ~S3C64XX_SPI_CH_HS_EN;
218 writel(val, regs + S3C64XX_SPI_CH_CFG);
219
220 /* Flush TxFIFO*/
221 loops = msecs_to_loops(1);
222 do {
223 val = readl(regs + S3C64XX_SPI_STATUS);
224 } while (TX_FIFO_LVL(val, sdd) && loops--);
225
226 if (loops == 0)
227 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
228
229 /* Flush RxFIFO*/
230 loops = msecs_to_loops(1);
231 do {
232 val = readl(regs + S3C64XX_SPI_STATUS);
233 if (RX_FIFO_LVL(val, sdd))
234 readl(regs + S3C64XX_SPI_RX_DATA);
235 else
236 break;
237 } while (loops--);
238
239 if (loops == 0)
240 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
241
242 val = readl(regs + S3C64XX_SPI_CH_CFG);
243 val &= ~S3C64XX_SPI_CH_SW_RST;
244 writel(val, regs + S3C64XX_SPI_CH_CFG);
245
246 val = readl(regs + S3C64XX_SPI_MODE_CFG);
247 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
248 writel(val, regs + S3C64XX_SPI_MODE_CFG);
249}
250
251static void s3c64xx_spi_dmacb(void *data)
252{
253 struct s3c64xx_spi_driver_data *sdd;
254 struct s3c64xx_spi_dma_data *dma = data;
255 unsigned long flags;
256
257 if (dma->direction == DMA_DEV_TO_MEM)
258 sdd = container_of(data,
259 struct s3c64xx_spi_driver_data, rx_dma);
260 else
261 sdd = container_of(data,
262 struct s3c64xx_spi_driver_data, tx_dma);
263
264 spin_lock_irqsave(&sdd->lock, flags);
265
266 if (dma->direction == DMA_DEV_TO_MEM) {
267 sdd->state &= ~RXBUSY;
268 if (!(sdd->state & TXBUSY))
269 complete(&sdd->xfer_completion);
270 } else {
271 sdd->state &= ~TXBUSY;
272 if (!(sdd->state & RXBUSY))
273 complete(&sdd->xfer_completion);
274 }
275
276 spin_unlock_irqrestore(&sdd->lock, flags);
277}
278
279static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
280 struct sg_table *sgt)
281{
282 struct s3c64xx_spi_driver_data *sdd;
283 struct dma_slave_config config;
284 struct dma_async_tx_descriptor *desc;
285 int ret;
286
287 memset(&config, 0, sizeof(config));
288
289 if (dma->direction == DMA_DEV_TO_MEM) {
290 sdd = container_of((void *)dma,
291 struct s3c64xx_spi_driver_data, rx_dma);
292 config.direction = dma->direction;
293 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
294 config.src_addr_width = sdd->cur_bpw / 8;
295 config.src_maxburst = 1;
296 dmaengine_slave_config(dma->ch, &config);
297 } else {
298 sdd = container_of((void *)dma,
299 struct s3c64xx_spi_driver_data, tx_dma);
300 config.direction = dma->direction;
301 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
302 config.dst_addr_width = sdd->cur_bpw / 8;
303 config.dst_maxburst = 1;
304 dmaengine_slave_config(dma->ch, &config);
305 }
306
307 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
308 dma->direction, DMA_PREP_INTERRUPT);
309 if (!desc) {
310 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
311 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
312 return -ENOMEM;
313 }
314
315 desc->callback = s3c64xx_spi_dmacb;
316 desc->callback_param = dma;
317
318 dma->cookie = dmaengine_submit(desc);
319 ret = dma_submit_error(dma->cookie);
320 if (ret) {
321 dev_err(&sdd->pdev->dev, "DMA submission failed");
322 return -EIO;
323 }
324
325 dma_async_issue_pending(dma->ch);
326 return 0;
327}
328
329static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
330{
331 struct s3c64xx_spi_driver_data *sdd =
332 spi_controller_get_devdata(spi->controller);
333
334 if (sdd->cntrlr_info->no_cs)
335 return;
336
337 if (enable) {
338 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
339 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
340 } else {
341 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
342
343 ssel |= (S3C64XX_SPI_CS_AUTO |
344 S3C64XX_SPI_CS_NSC_CNT_2);
345 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
346 }
347 } else {
348 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
349 writel(S3C64XX_SPI_CS_SIG_INACT,
350 sdd->regs + S3C64XX_SPI_CS_REG);
351 }
352}
353
354static int s3c64xx_spi_prepare_transfer(struct spi_controller *spi)
355{
356 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
357
358 if (is_polling(sdd))
359 return 0;
360
361 /* Requests DMA channels */
362 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx");
363 if (IS_ERR(sdd->rx_dma.ch)) {
364 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n");
365 sdd->rx_dma.ch = NULL;
366 return 0;
367 }
368
369 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx");
370 if (IS_ERR(sdd->tx_dma.ch)) {
371 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n");
372 dma_release_channel(sdd->rx_dma.ch);
373 sdd->tx_dma.ch = NULL;
374 sdd->rx_dma.ch = NULL;
375 return 0;
376 }
377
378 spi->dma_rx = sdd->rx_dma.ch;
379 spi->dma_tx = sdd->tx_dma.ch;
380
381 return 0;
382}
383
384static int s3c64xx_spi_unprepare_transfer(struct spi_controller *spi)
385{
386 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
387
388 if (is_polling(sdd))
389 return 0;
390
391 /* Releases DMA channels if they are allocated */
392 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
393 dma_release_channel(sdd->rx_dma.ch);
394 dma_release_channel(sdd->tx_dma.ch);
395 sdd->rx_dma.ch = NULL;
396 sdd->tx_dma.ch = NULL;
397 }
398
399 return 0;
400}
401
402static bool s3c64xx_spi_can_dma(struct spi_controller *host,
403 struct spi_device *spi,
404 struct spi_transfer *xfer)
405{
406 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
407
408 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
409 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
410 } else {
411 return false;
412 }
413
414}
415
416static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
417 struct spi_transfer *xfer, int dma_mode)
418{
419 void __iomem *regs = sdd->regs;
420 u32 modecfg, chcfg;
421 int ret = 0;
422
423 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
424 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
425
426 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
427 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
428
429 if (dma_mode) {
430 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
431 } else {
432 /* Always shift in data in FIFO, even if xfer is Tx only,
433 * this helps setting PCKT_CNT value for generating clocks
434 * as exactly needed.
435 */
436 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
437 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
438 | S3C64XX_SPI_PACKET_CNT_EN,
439 regs + S3C64XX_SPI_PACKET_CNT);
440 }
441
442 if (xfer->tx_buf != NULL) {
443 sdd->state |= TXBUSY;
444 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
445 if (dma_mode) {
446 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
447 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
448 } else {
449 switch (sdd->cur_bpw) {
450 case 32:
451 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
452 xfer->tx_buf, xfer->len / 4);
453 break;
454 case 16:
455 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
456 xfer->tx_buf, xfer->len / 2);
457 break;
458 default:
459 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
460 xfer->tx_buf, xfer->len);
461 break;
462 }
463 }
464 }
465
466 if (xfer->rx_buf != NULL) {
467 sdd->state |= RXBUSY;
468
469 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
470 && !(sdd->cur_mode & SPI_CPHA))
471 chcfg |= S3C64XX_SPI_CH_HS_EN;
472
473 if (dma_mode) {
474 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
475 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
476 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
477 | S3C64XX_SPI_PACKET_CNT_EN,
478 regs + S3C64XX_SPI_PACKET_CNT);
479 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
480 }
481 }
482
483 if (ret)
484 return ret;
485
486 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
487 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
488
489 return 0;
490}
491
492static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
493 int timeout_ms)
494{
495 void __iomem *regs = sdd->regs;
496 unsigned long val = 1;
497 u32 status;
498
499 /* max fifo depth available */
500 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
501
502 if (timeout_ms)
503 val = msecs_to_loops(timeout_ms);
504
505 do {
506 status = readl(regs + S3C64XX_SPI_STATUS);
507 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
508
509 /* return the actual received data length */
510 return RX_FIFO_LVL(status, sdd);
511}
512
513static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
514 struct spi_transfer *xfer)
515{
516 void __iomem *regs = sdd->regs;
517 unsigned long val;
518 u32 status;
519 int ms;
520
521 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
522 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
523 ms += 30; /* some tolerance */
524 ms = max(ms, 100); /* minimum timeout */
525
526 val = msecs_to_jiffies(ms) + 10;
527 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
528
529 /*
530 * If the previous xfer was completed within timeout, then
531 * proceed further else return -EIO.
532 * DmaTx returns after simply writing data in the FIFO,
533 * w/o waiting for real transmission on the bus to finish.
534 * DmaRx returns only after Dma read data from FIFO which
535 * needs bus transmission to finish, so we don't worry if
536 * Xfer involved Rx(with or without Tx).
537 */
538 if (val && !xfer->rx_buf) {
539 val = msecs_to_loops(10);
540 status = readl(regs + S3C64XX_SPI_STATUS);
541 while ((TX_FIFO_LVL(status, sdd)
542 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
543 && --val) {
544 cpu_relax();
545 status = readl(regs + S3C64XX_SPI_STATUS);
546 }
547
548 }
549
550 /* If timed out while checking rx/tx status return error */
551 if (!val)
552 return -EIO;
553
554 return 0;
555}
556
557static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
558 struct spi_transfer *xfer, bool use_irq)
559{
560 void __iomem *regs = sdd->regs;
561 unsigned long val;
562 u32 status;
563 int loops;
564 u32 cpy_len;
565 u8 *buf;
566 int ms;
567 unsigned long time_us;
568
569 /* microsecs to xfer 'len' bytes @ 'cur_speed' */
570 time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed;
571 ms = (time_us / 1000);
572 ms += 10; /* some tolerance */
573
574 /* sleep during signal transfer time */
575 status = readl(regs + S3C64XX_SPI_STATUS);
576 if (RX_FIFO_LVL(status, sdd) < xfer->len)
577 usleep_range(time_us / 2, time_us);
578
579 if (use_irq) {
580 val = msecs_to_jiffies(ms);
581 if (!wait_for_completion_timeout(&sdd->xfer_completion, val))
582 return -EIO;
583 }
584
585 val = msecs_to_loops(ms);
586 do {
587 status = readl(regs + S3C64XX_SPI_STATUS);
588 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
589
590 if (!val)
591 return -EIO;
592
593 /* If it was only Tx */
594 if (!xfer->rx_buf) {
595 sdd->state &= ~TXBUSY;
596 return 0;
597 }
598
599 /*
600 * If the receive length is bigger than the controller fifo
601 * size, calculate the loops and read the fifo as many times.
602 * loops = length / max fifo size (calculated by using the
603 * fifo mask).
604 * For any size less than the fifo size the below code is
605 * executed atleast once.
606 */
607 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
608 buf = xfer->rx_buf;
609 do {
610 /* wait for data to be received in the fifo */
611 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
612 (loops ? ms : 0));
613
614 switch (sdd->cur_bpw) {
615 case 32:
616 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
617 buf, cpy_len / 4);
618 break;
619 case 16:
620 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
621 buf, cpy_len / 2);
622 break;
623 default:
624 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
625 buf, cpy_len);
626 break;
627 }
628
629 buf = buf + cpy_len;
630 } while (loops--);
631 sdd->state &= ~RXBUSY;
632
633 return 0;
634}
635
636static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
637{
638 void __iomem *regs = sdd->regs;
639 int ret;
640 u32 val;
641 int div = sdd->port_conf->clk_div;
642
643 /* Disable Clock */
644 if (!sdd->port_conf->clk_from_cmu) {
645 val = readl(regs + S3C64XX_SPI_CLK_CFG);
646 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
647 writel(val, regs + S3C64XX_SPI_CLK_CFG);
648 }
649
650 /* Set Polarity and Phase */
651 val = readl(regs + S3C64XX_SPI_CH_CFG);
652 val &= ~(S3C64XX_SPI_CH_SLAVE |
653 S3C64XX_SPI_CPOL_L |
654 S3C64XX_SPI_CPHA_B);
655
656 if (sdd->cur_mode & SPI_CPOL)
657 val |= S3C64XX_SPI_CPOL_L;
658
659 if (sdd->cur_mode & SPI_CPHA)
660 val |= S3C64XX_SPI_CPHA_B;
661
662 writel(val, regs + S3C64XX_SPI_CH_CFG);
663
664 /* Set Channel & DMA Mode */
665 val = readl(regs + S3C64XX_SPI_MODE_CFG);
666 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
667 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
668
669 switch (sdd->cur_bpw) {
670 case 32:
671 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
672 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
673 break;
674 case 16:
675 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
676 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
677 break;
678 default:
679 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
680 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
681 break;
682 }
683
684 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback)
685 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK;
686 else
687 val &= ~S3C64XX_SPI_MODE_SELF_LOOPBACK;
688
689 writel(val, regs + S3C64XX_SPI_MODE_CFG);
690
691 if (sdd->port_conf->clk_from_cmu) {
692 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div);
693 if (ret)
694 return ret;
695 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div;
696 } else {
697 /* Configure Clock */
698 val = readl(regs + S3C64XX_SPI_CLK_CFG);
699 val &= ~S3C64XX_SPI_PSR_MASK;
700 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1)
701 & S3C64XX_SPI_PSR_MASK);
702 writel(val, regs + S3C64XX_SPI_CLK_CFG);
703
704 /* Enable Clock */
705 val = readl(regs + S3C64XX_SPI_CLK_CFG);
706 val |= S3C64XX_SPI_ENCLK_ENABLE;
707 writel(val, regs + S3C64XX_SPI_CLK_CFG);
708 }
709
710 return 0;
711}
712
713#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
714
715static int s3c64xx_spi_prepare_message(struct spi_controller *host,
716 struct spi_message *msg)
717{
718 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
719 struct spi_device *spi = msg->spi;
720 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
721
722 /* Configure feedback delay */
723 if (!cs)
724 /* No delay if not defined */
725 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
726 else
727 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
728
729 return 0;
730}
731
732static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
733{
734 struct spi_controller *ctlr = spi->controller;
735
736 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
737}
738
739static int s3c64xx_spi_transfer_one(struct spi_controller *host,
740 struct spi_device *spi,
741 struct spi_transfer *xfer)
742{
743 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
744 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
745 const void *tx_buf = NULL;
746 void *rx_buf = NULL;
747 int target_len = 0, origin_len = 0;
748 int use_dma = 0;
749 bool use_irq = false;
750 int status;
751 u32 speed;
752 u8 bpw;
753 unsigned long flags;
754 u32 rdy_lv;
755 u32 val;
756
757 reinit_completion(&sdd->xfer_completion);
758
759 /* Only BPW and Speed may change across transfers */
760 bpw = xfer->bits_per_word;
761 speed = xfer->speed_hz;
762
763 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
764 sdd->cur_bpw = bpw;
765 sdd->cur_speed = speed;
766 sdd->cur_mode = spi->mode;
767 status = s3c64xx_spi_config(sdd);
768 if (status)
769 return status;
770 }
771
772 if (!is_polling(sdd) && (xfer->len > fifo_len) &&
773 sdd->rx_dma.ch && sdd->tx_dma.ch) {
774 use_dma = 1;
775
776 } else if (xfer->len >= fifo_len) {
777 tx_buf = xfer->tx_buf;
778 rx_buf = xfer->rx_buf;
779 origin_len = xfer->len;
780 target_len = xfer->len;
781 xfer->len = fifo_len - 1;
782 }
783
784 do {
785 /* transfer size is greater than 32, change to IRQ mode */
786 if (!use_dma && xfer->len > S3C64XX_SPI_POLLING_SIZE)
787 use_irq = true;
788
789 if (use_irq) {
790 reinit_completion(&sdd->xfer_completion);
791
792 rdy_lv = xfer->len;
793 /* Setup RDY_FIFO trigger Level
794 * RDY_LVL =
795 * fifo_lvl up to 64 byte -> N bytes
796 * 128 byte -> RDY_LVL * 2 bytes
797 * 256 byte -> RDY_LVL * 4 bytes
798 */
799 if (fifo_len == 128)
800 rdy_lv /= 2;
801 else if (fifo_len == 256)
802 rdy_lv /= 4;
803
804 val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG);
805 val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL;
806 val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT);
807 writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG);
808
809 /* Enable FIFO_RDY_EN IRQ */
810 val = readl(sdd->regs + S3C64XX_SPI_INT_EN);
811 writel((val | S3C64XX_SPI_INT_RX_FIFORDY_EN),
812 sdd->regs + S3C64XX_SPI_INT_EN);
813
814 }
815
816 spin_lock_irqsave(&sdd->lock, flags);
817
818 /* Pending only which is to be done */
819 sdd->state &= ~RXBUSY;
820 sdd->state &= ~TXBUSY;
821
822 /* Start the signals */
823 s3c64xx_spi_set_cs(spi, true);
824
825 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
826
827 spin_unlock_irqrestore(&sdd->lock, flags);
828
829 if (status) {
830 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
831 break;
832 }
833
834 if (use_dma)
835 status = s3c64xx_wait_for_dma(sdd, xfer);
836 else
837 status = s3c64xx_wait_for_pio(sdd, xfer, use_irq);
838
839 if (status) {
840 dev_err(&spi->dev,
841 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
842 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
843 (sdd->state & RXBUSY) ? 'f' : 'p',
844 (sdd->state & TXBUSY) ? 'f' : 'p',
845 xfer->len, use_dma ? 1 : 0, status);
846
847 if (use_dma) {
848 struct dma_tx_state s;
849
850 if (xfer->tx_buf && (sdd->state & TXBUSY)) {
851 dmaengine_pause(sdd->tx_dma.ch);
852 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
853 dmaengine_terminate_all(sdd->tx_dma.ch);
854 dev_err(&spi->dev, "TX residue: %d\n", s.residue);
855
856 }
857 if (xfer->rx_buf && (sdd->state & RXBUSY)) {
858 dmaengine_pause(sdd->rx_dma.ch);
859 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
860 dmaengine_terminate_all(sdd->rx_dma.ch);
861 dev_err(&spi->dev, "RX residue: %d\n", s.residue);
862 }
863 }
864 } else {
865 s3c64xx_flush_fifo(sdd);
866 }
867 if (target_len > 0) {
868 target_len -= xfer->len;
869
870 if (xfer->tx_buf)
871 xfer->tx_buf += xfer->len;
872
873 if (xfer->rx_buf)
874 xfer->rx_buf += xfer->len;
875
876 if (target_len >= fifo_len)
877 xfer->len = fifo_len - 1;
878 else
879 xfer->len = target_len;
880 }
881 } while (target_len > 0);
882
883 if (origin_len) {
884 /* Restore original xfer buffers and length */
885 xfer->tx_buf = tx_buf;
886 xfer->rx_buf = rx_buf;
887 xfer->len = origin_len;
888 }
889
890 return status;
891}
892
893static struct s3c64xx_spi_csinfo *s3c64xx_get_target_ctrldata(
894 struct spi_device *spi)
895{
896 struct s3c64xx_spi_csinfo *cs;
897 struct device_node *target_np, *data_np = NULL;
898 u32 fb_delay = 0;
899
900 target_np = spi->dev.of_node;
901 if (!target_np) {
902 dev_err(&spi->dev, "device node not found\n");
903 return ERR_PTR(-EINVAL);
904 }
905
906 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
907 if (!cs)
908 return ERR_PTR(-ENOMEM);
909
910 data_np = of_get_child_by_name(target_np, "controller-data");
911 if (!data_np) {
912 dev_info(&spi->dev, "feedback delay set to default (0)\n");
913 return cs;
914 }
915
916 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
917 cs->fb_delay = fb_delay;
918 of_node_put(data_np);
919 return cs;
920}
921
922/*
923 * Here we only check the validity of requested configuration
924 * and save the configuration in a local data-structure.
925 * The controller is actually configured only just before we
926 * get a message to transfer.
927 */
928static int s3c64xx_spi_setup(struct spi_device *spi)
929{
930 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
931 struct s3c64xx_spi_driver_data *sdd;
932 int err;
933 int div;
934
935 sdd = spi_controller_get_devdata(spi->controller);
936 if (spi->dev.of_node) {
937 cs = s3c64xx_get_target_ctrldata(spi);
938 spi->controller_data = cs;
939 }
940
941 /* NULL is fine, we just avoid using the FB delay (=0) */
942 if (IS_ERR(cs)) {
943 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0));
944 return -ENODEV;
945 }
946
947 if (!spi_get_ctldata(spi))
948 spi_set_ctldata(spi, cs);
949
950 pm_runtime_get_sync(&sdd->pdev->dev);
951
952 div = sdd->port_conf->clk_div;
953
954 /* Check if we can provide the requested rate */
955 if (!sdd->port_conf->clk_from_cmu) {
956 u32 psr, speed;
957
958 /* Max possible */
959 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1);
960
961 if (spi->max_speed_hz > speed)
962 spi->max_speed_hz = speed;
963
964 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
965 psr &= S3C64XX_SPI_PSR_MASK;
966 if (psr == S3C64XX_SPI_PSR_MASK)
967 psr--;
968
969 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
970 if (spi->max_speed_hz < speed) {
971 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
972 psr++;
973 } else {
974 err = -EINVAL;
975 goto setup_exit;
976 }
977 }
978
979 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
980 if (spi->max_speed_hz >= speed) {
981 spi->max_speed_hz = speed;
982 } else {
983 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
984 spi->max_speed_hz);
985 err = -EINVAL;
986 goto setup_exit;
987 }
988 }
989
990 pm_runtime_mark_last_busy(&sdd->pdev->dev);
991 pm_runtime_put_autosuspend(&sdd->pdev->dev);
992 s3c64xx_spi_set_cs(spi, false);
993
994 return 0;
995
996setup_exit:
997 pm_runtime_mark_last_busy(&sdd->pdev->dev);
998 pm_runtime_put_autosuspend(&sdd->pdev->dev);
999 /* setup() returns with device de-selected */
1000 s3c64xx_spi_set_cs(spi, false);
1001
1002 spi_set_ctldata(spi, NULL);
1003
1004 /* This was dynamically allocated on the DT path */
1005 if (spi->dev.of_node)
1006 kfree(cs);
1007
1008 return err;
1009}
1010
1011static void s3c64xx_spi_cleanup(struct spi_device *spi)
1012{
1013 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1014
1015 /* This was dynamically allocated on the DT path */
1016 if (spi->dev.of_node)
1017 kfree(cs);
1018
1019 spi_set_ctldata(spi, NULL);
1020}
1021
1022static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1023{
1024 struct s3c64xx_spi_driver_data *sdd = data;
1025 struct spi_controller *spi = sdd->host;
1026 unsigned int val, clr = 0;
1027
1028 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1029
1030 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1031 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1032 dev_err(&spi->dev, "RX overrun\n");
1033 }
1034 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1035 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1036 dev_err(&spi->dev, "RX underrun\n");
1037 }
1038 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1039 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1040 dev_err(&spi->dev, "TX overrun\n");
1041 }
1042 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1043 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1044 dev_err(&spi->dev, "TX underrun\n");
1045 }
1046
1047 if (val & S3C64XX_SPI_ST_RX_FIFORDY) {
1048 complete(&sdd->xfer_completion);
1049 /* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */
1050 val = readl(sdd->regs + S3C64XX_SPI_INT_EN);
1051 writel((val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN),
1052 sdd->regs + S3C64XX_SPI_INT_EN);
1053 }
1054
1055 /* Clear the pending irq by setting and then clearing it */
1056 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1057 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1058
1059 return IRQ_HANDLED;
1060}
1061
1062static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
1063{
1064 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1065 void __iomem *regs = sdd->regs;
1066 unsigned int val;
1067
1068 sdd->cur_speed = 0;
1069
1070 if (sci->no_cs)
1071 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
1072 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
1073 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
1074
1075 /* Disable Interrupts - we use Polling if not DMA mode */
1076 writel(0, regs + S3C64XX_SPI_INT_EN);
1077
1078 if (!sdd->port_conf->clk_from_cmu)
1079 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1080 regs + S3C64XX_SPI_CLK_CFG);
1081 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1082 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1083
1084 /* Clear any irq pending bits, should set and clear the bits */
1085 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1086 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1087 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1088 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1089 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1090 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1091
1092 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1093
1094 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1095 val &= ~S3C64XX_SPI_MODE_4BURST;
1096 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1097 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1098 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1099
1100 s3c64xx_flush_fifo(sdd);
1101}
1102
1103#ifdef CONFIG_OF
1104static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1105{
1106 struct s3c64xx_spi_info *sci;
1107 u32 temp;
1108
1109 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1110 if (!sci)
1111 return ERR_PTR(-ENOMEM);
1112
1113 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1114 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1115 sci->src_clk_nr = 0;
1116 } else {
1117 sci->src_clk_nr = temp;
1118 }
1119
1120 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1121 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1122 sci->num_cs = 1;
1123 } else {
1124 sci->num_cs = temp;
1125 }
1126
1127 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1128 sci->polling = !of_property_present(dev->of_node, "dmas");
1129
1130 return sci;
1131}
1132#else
1133static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1134{
1135 return dev_get_platdata(dev);
1136}
1137#endif
1138
1139static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1140 struct platform_device *pdev)
1141{
1142#ifdef CONFIG_OF
1143 if (pdev->dev.of_node)
1144 return of_device_get_match_data(&pdev->dev);
1145#endif
1146 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1147}
1148
1149static int s3c64xx_spi_probe(struct platform_device *pdev)
1150{
1151 struct resource *mem_res;
1152 struct s3c64xx_spi_driver_data *sdd;
1153 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1154 struct spi_controller *host;
1155 int ret, irq;
1156 char clk_name[16];
1157
1158 if (!sci && pdev->dev.of_node) {
1159 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1160 if (IS_ERR(sci))
1161 return PTR_ERR(sci);
1162 }
1163
1164 if (!sci)
1165 return dev_err_probe(&pdev->dev, -ENODEV,
1166 "Platform_data missing!\n");
1167
1168 irq = platform_get_irq(pdev, 0);
1169 if (irq < 0)
1170 return irq;
1171
1172 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd));
1173 if (!host)
1174 return dev_err_probe(&pdev->dev, -ENOMEM,
1175 "Unable to allocate SPI Host\n");
1176
1177 platform_set_drvdata(pdev, host);
1178
1179 sdd = spi_controller_get_devdata(host);
1180 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1181 sdd->host = host;
1182 sdd->cntrlr_info = sci;
1183 sdd->pdev = pdev;
1184 if (pdev->dev.of_node) {
1185 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1186 if (ret < 0)
1187 return dev_err_probe(&pdev->dev, ret,
1188 "Failed to get alias id\n");
1189 sdd->port_id = ret;
1190 } else {
1191 sdd->port_id = pdev->id;
1192 }
1193
1194 sdd->cur_bpw = 8;
1195
1196 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1197 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1198
1199 host->dev.of_node = pdev->dev.of_node;
1200 host->bus_num = sdd->port_id;
1201 host->setup = s3c64xx_spi_setup;
1202 host->cleanup = s3c64xx_spi_cleanup;
1203 host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1204 host->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1205 host->prepare_message = s3c64xx_spi_prepare_message;
1206 host->transfer_one = s3c64xx_spi_transfer_one;
1207 host->max_transfer_size = s3c64xx_spi_max_transfer_size;
1208 host->num_chipselect = sci->num_cs;
1209 host->use_gpio_descriptors = true;
1210 host->dma_alignment = 8;
1211 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1212 SPI_BPW_MASK(8);
1213 /* the spi->mode bits understood by this driver: */
1214 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1215 if (sdd->port_conf->has_loopback)
1216 host->mode_bits |= SPI_LOOP;
1217 host->auto_runtime_pm = true;
1218 if (!is_polling(sdd))
1219 host->can_dma = s3c64xx_spi_can_dma;
1220
1221 sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
1222 if (IS_ERR(sdd->regs))
1223 return PTR_ERR(sdd->regs);
1224 sdd->sfr_start = mem_res->start;
1225
1226 if (sci->cfg_gpio && sci->cfg_gpio())
1227 return dev_err_probe(&pdev->dev, -EBUSY,
1228 "Unable to config gpio\n");
1229
1230 /* Setup clocks */
1231 sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi");
1232 if (IS_ERR(sdd->clk))
1233 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk),
1234 "Unable to acquire clock 'spi'\n");
1235
1236 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1237 sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name);
1238 if (IS_ERR(sdd->src_clk))
1239 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk),
1240 "Unable to acquire clock '%s'\n",
1241 clk_name);
1242
1243 if (sdd->port_conf->clk_ioclk) {
1244 sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk");
1245 if (IS_ERR(sdd->ioclk))
1246 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk),
1247 "Unable to acquire 'ioclk'\n");
1248 }
1249
1250 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1251 pm_runtime_use_autosuspend(&pdev->dev);
1252 pm_runtime_set_active(&pdev->dev);
1253 pm_runtime_enable(&pdev->dev);
1254 pm_runtime_get_sync(&pdev->dev);
1255
1256 /* Setup Deufult Mode */
1257 s3c64xx_spi_hwinit(sdd);
1258
1259 spin_lock_init(&sdd->lock);
1260 init_completion(&sdd->xfer_completion);
1261
1262 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1263 "spi-s3c64xx", sdd);
1264 if (ret != 0) {
1265 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1266 irq, ret);
1267 goto err_pm_put;
1268 }
1269
1270 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1271 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1272 sdd->regs + S3C64XX_SPI_INT_EN);
1273
1274 ret = devm_spi_register_controller(&pdev->dev, host);
1275 if (ret != 0) {
1276 dev_err(&pdev->dev, "cannot register SPI host: %d\n", ret);
1277 goto err_pm_put;
1278 }
1279
1280 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n",
1281 sdd->port_id, host->num_chipselect);
1282 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1283 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1284
1285 pm_runtime_mark_last_busy(&pdev->dev);
1286 pm_runtime_put_autosuspend(&pdev->dev);
1287
1288 return 0;
1289
1290err_pm_put:
1291 pm_runtime_put_noidle(&pdev->dev);
1292 pm_runtime_disable(&pdev->dev);
1293 pm_runtime_set_suspended(&pdev->dev);
1294
1295 return ret;
1296}
1297
1298static void s3c64xx_spi_remove(struct platform_device *pdev)
1299{
1300 struct spi_controller *host = platform_get_drvdata(pdev);
1301 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1302
1303 pm_runtime_get_sync(&pdev->dev);
1304
1305 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1306
1307 if (!is_polling(sdd)) {
1308 dma_release_channel(sdd->rx_dma.ch);
1309 dma_release_channel(sdd->tx_dma.ch);
1310 }
1311
1312 pm_runtime_put_noidle(&pdev->dev);
1313 pm_runtime_disable(&pdev->dev);
1314 pm_runtime_set_suspended(&pdev->dev);
1315}
1316
1317#ifdef CONFIG_PM_SLEEP
1318static int s3c64xx_spi_suspend(struct device *dev)
1319{
1320 struct spi_controller *host = dev_get_drvdata(dev);
1321 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1322
1323 int ret = spi_controller_suspend(host);
1324 if (ret)
1325 return ret;
1326
1327 ret = pm_runtime_force_suspend(dev);
1328 if (ret < 0)
1329 return ret;
1330
1331 sdd->cur_speed = 0; /* Output Clock is stopped */
1332
1333 return 0;
1334}
1335
1336static int s3c64xx_spi_resume(struct device *dev)
1337{
1338 struct spi_controller *host = dev_get_drvdata(dev);
1339 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1340 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1341 int ret;
1342
1343 if (sci->cfg_gpio)
1344 sci->cfg_gpio();
1345
1346 ret = pm_runtime_force_resume(dev);
1347 if (ret < 0)
1348 return ret;
1349
1350 return spi_controller_resume(host);
1351}
1352#endif /* CONFIG_PM_SLEEP */
1353
1354#ifdef CONFIG_PM
1355static int s3c64xx_spi_runtime_suspend(struct device *dev)
1356{
1357 struct spi_controller *host = dev_get_drvdata(dev);
1358 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1359
1360 clk_disable_unprepare(sdd->clk);
1361 clk_disable_unprepare(sdd->src_clk);
1362 clk_disable_unprepare(sdd->ioclk);
1363
1364 return 0;
1365}
1366
1367static int s3c64xx_spi_runtime_resume(struct device *dev)
1368{
1369 struct spi_controller *host = dev_get_drvdata(dev);
1370 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1371 int ret;
1372
1373 if (sdd->port_conf->clk_ioclk) {
1374 ret = clk_prepare_enable(sdd->ioclk);
1375 if (ret != 0)
1376 return ret;
1377 }
1378
1379 ret = clk_prepare_enable(sdd->src_clk);
1380 if (ret != 0)
1381 goto err_disable_ioclk;
1382
1383 ret = clk_prepare_enable(sdd->clk);
1384 if (ret != 0)
1385 goto err_disable_src_clk;
1386
1387 s3c64xx_spi_hwinit(sdd);
1388
1389 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1390 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1391 sdd->regs + S3C64XX_SPI_INT_EN);
1392
1393 return 0;
1394
1395err_disable_src_clk:
1396 clk_disable_unprepare(sdd->src_clk);
1397err_disable_ioclk:
1398 clk_disable_unprepare(sdd->ioclk);
1399
1400 return ret;
1401}
1402#endif /* CONFIG_PM */
1403
1404static const struct dev_pm_ops s3c64xx_spi_pm = {
1405 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1406 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1407 s3c64xx_spi_runtime_resume, NULL)
1408};
1409
1410static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1411 .fifo_lvl_mask = { 0x7f },
1412 .rx_lvl_offset = 13,
1413 .tx_st_done = 21,
1414 .clk_div = 2,
1415 .high_speed = true,
1416};
1417
1418static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1419 .fifo_lvl_mask = { 0x7f, 0x7F },
1420 .rx_lvl_offset = 13,
1421 .tx_st_done = 21,
1422 .clk_div = 2,
1423};
1424
1425static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1426 .fifo_lvl_mask = { 0x1ff, 0x7F },
1427 .rx_lvl_offset = 15,
1428 .tx_st_done = 25,
1429 .clk_div = 2,
1430 .high_speed = true,
1431};
1432
1433static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1434 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1435 .rx_lvl_offset = 15,
1436 .tx_st_done = 25,
1437 .clk_div = 2,
1438 .high_speed = true,
1439 .clk_from_cmu = true,
1440 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1441};
1442
1443static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1444 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1445 .rx_lvl_offset = 15,
1446 .tx_st_done = 25,
1447 .clk_div = 2,
1448 .high_speed = true,
1449 .clk_from_cmu = true,
1450 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1451};
1452
1453static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1454 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1455 .rx_lvl_offset = 15,
1456 .tx_st_done = 25,
1457 .clk_div = 2,
1458 .high_speed = true,
1459 .clk_from_cmu = true,
1460 .clk_ioclk = true,
1461 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1462};
1463
1464static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
1465 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
1466 0x7f, 0x7f, 0x7f, 0x7f},
1467 .rx_lvl_offset = 15,
1468 .tx_st_done = 25,
1469 .clk_div = 4,
1470 .high_speed = true,
1471 .clk_from_cmu = true,
1472 .clk_ioclk = true,
1473 .has_loopback = true,
1474 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1475};
1476
1477static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
1478 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
1479 .rx_lvl_offset = 15,
1480 .tx_st_done = 25,
1481 .clk_div = 2,
1482 .high_speed = true,
1483 .clk_from_cmu = true,
1484 .clk_ioclk = false,
1485 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1486};
1487
1488static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1489 {
1490 .name = "s3c2443-spi",
1491 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1492 }, {
1493 .name = "s3c6410-spi",
1494 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1495 },
1496 { },
1497};
1498
1499static const struct of_device_id s3c64xx_spi_dt_match[] = {
1500 { .compatible = "samsung,s3c2443-spi",
1501 .data = (void *)&s3c2443_spi_port_config,
1502 },
1503 { .compatible = "samsung,s3c6410-spi",
1504 .data = (void *)&s3c6410_spi_port_config,
1505 },
1506 { .compatible = "samsung,s5pv210-spi",
1507 .data = (void *)&s5pv210_spi_port_config,
1508 },
1509 { .compatible = "samsung,exynos4210-spi",
1510 .data = (void *)&exynos4_spi_port_config,
1511 },
1512 { .compatible = "samsung,exynos7-spi",
1513 .data = (void *)&exynos7_spi_port_config,
1514 },
1515 { .compatible = "samsung,exynos5433-spi",
1516 .data = (void *)&exynos5433_spi_port_config,
1517 },
1518 { .compatible = "samsung,exynosautov9-spi",
1519 .data = (void *)&exynosautov9_spi_port_config,
1520 },
1521 { .compatible = "tesla,fsd-spi",
1522 .data = (void *)&fsd_spi_port_config,
1523 },
1524 { },
1525};
1526MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1527
1528static struct platform_driver s3c64xx_spi_driver = {
1529 .driver = {
1530 .name = "s3c64xx-spi",
1531 .pm = &s3c64xx_spi_pm,
1532 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1533 },
1534 .probe = s3c64xx_spi_probe,
1535 .remove_new = s3c64xx_spi_remove,
1536 .id_table = s3c64xx_spi_driver_ids,
1537};
1538MODULE_ALIAS("platform:s3c64xx-spi");
1539
1540module_platform_driver(s3c64xx_spi_driver);
1541
1542MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1543MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1544MODULE_LICENSE("GPL");