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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2009 Samsung Electronics Co., Ltd.
4// Jaswinder Singh <jassi.brar@samsung.com>
5
6#include <linux/init.h>
7#include <linux/module.h>
8#include <linux/interrupt.h>
9#include <linux/delay.h>
10#include <linux/clk.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/spi/spi.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18
19#include <linux/platform_data/spi-s3c64xx.h>
20
21#define MAX_SPI_PORTS 12
22#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
23#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
24#define AUTOSUSPEND_TIMEOUT 2000
25
26/* Registers and bit-fields */
27
28#define S3C64XX_SPI_CH_CFG 0x00
29#define S3C64XX_SPI_CLK_CFG 0x04
30#define S3C64XX_SPI_MODE_CFG 0x08
31#define S3C64XX_SPI_CS_REG 0x0C
32#define S3C64XX_SPI_INT_EN 0x10
33#define S3C64XX_SPI_STATUS 0x14
34#define S3C64XX_SPI_TX_DATA 0x18
35#define S3C64XX_SPI_RX_DATA 0x1C
36#define S3C64XX_SPI_PACKET_CNT 0x20
37#define S3C64XX_SPI_PENDING_CLR 0x24
38#define S3C64XX_SPI_SWAP_CFG 0x28
39#define S3C64XX_SPI_FB_CLK 0x2C
40
41#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
42#define S3C64XX_SPI_CH_SW_RST (1<<5)
43#define S3C64XX_SPI_CH_SLAVE (1<<4)
44#define S3C64XX_SPI_CPOL_L (1<<3)
45#define S3C64XX_SPI_CPHA_B (1<<2)
46#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
47#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
48
49#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
50#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
51#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
52#define S3C64XX_SPI_PSR_MASK 0xff
53
54#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
55#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
56#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
57#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
58#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
59#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
60#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
61#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
62#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3)
63#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
64#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
65#define S3C64XX_SPI_MODE_4BURST (1<<0)
66
67#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4)
68#define S3C64XX_SPI_CS_AUTO (1<<1)
69#define S3C64XX_SPI_CS_SIG_INACT (1<<0)
70
71#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
72#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
73#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
74#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
75#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
76#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
77#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
78
79#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
80#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
81#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
82#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
83#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
84#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
85
86#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
87#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
88
89#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
90#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
91#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
92#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
93#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
94
95#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
96#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
97#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
98#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
99#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
100#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
101#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
102#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
103
104#define S3C64XX_SPI_FBCLK_MSK (3<<0)
105
106#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
107#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
108 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
109#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
110#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
111 FIFO_LVL_MASK(i))
112
113#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
114#define S3C64XX_SPI_TRAILCNT_OFF 19
115
116#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
117
118#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
119#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
120
121#define RXBUSY (1<<2)
122#define TXBUSY (1<<3)
123
124struct s3c64xx_spi_dma_data {
125 struct dma_chan *ch;
126 dma_cookie_t cookie;
127 enum dma_transfer_direction direction;
128};
129
130/**
131 * struct s3c64xx_spi_port_config - SPI Controller hardware info
132 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
133 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
134 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
135 * @clk_div: Internal clock divider
136 * @quirks: Bitmask of known quirks
137 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
138 * @clk_from_cmu: True, if the controller does not include a clock mux and
139 * prescaler unit.
140 * @clk_ioclk: True if clock is present on this device
141 * @has_loopback: True if loopback mode can be supported
142 *
143 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
144 * differ in some aspects such as the size of the fifo and spi bus clock
145 * setup. Such differences are specified to the driver using this structure
146 * which is provided as driver data to the driver.
147 */
148struct s3c64xx_spi_port_config {
149 int fifo_lvl_mask[MAX_SPI_PORTS];
150 int rx_lvl_offset;
151 int tx_st_done;
152 int quirks;
153 int clk_div;
154 bool high_speed;
155 bool clk_from_cmu;
156 bool clk_ioclk;
157 bool has_loopback;
158};
159
160/**
161 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
162 * @clk: Pointer to the spi clock.
163 * @src_clk: Pointer to the clock used to generate SPI signals.
164 * @ioclk: Pointer to the i/o clock between master and slave
165 * @pdev: Pointer to device's platform device data
166 * @master: Pointer to the SPI Protocol master.
167 * @cntrlr_info: Platform specific data for the controller this driver manages.
168 * @lock: Controller specific lock.
169 * @state: Set of FLAGS to indicate status.
170 * @sfr_start: BUS address of SPI controller regs.
171 * @regs: Pointer to ioremap'ed controller registers.
172 * @xfer_completion: To indicate completion of xfer task.
173 * @cur_mode: Stores the active configuration of the controller.
174 * @cur_bpw: Stores the active bits per word settings.
175 * @cur_speed: Current clock speed
176 * @rx_dma: Local receive DMA data (e.g. chan and direction)
177 * @tx_dma: Local transmit DMA data (e.g. chan and direction)
178 * @port_conf: Local SPI port configuartion data
179 * @port_id: Port identification number
180 */
181struct s3c64xx_spi_driver_data {
182 void __iomem *regs;
183 struct clk *clk;
184 struct clk *src_clk;
185 struct clk *ioclk;
186 struct platform_device *pdev;
187 struct spi_master *master;
188 struct s3c64xx_spi_info *cntrlr_info;
189 spinlock_t lock;
190 unsigned long sfr_start;
191 struct completion xfer_completion;
192 unsigned state;
193 unsigned cur_mode, cur_bpw;
194 unsigned cur_speed;
195 struct s3c64xx_spi_dma_data rx_dma;
196 struct s3c64xx_spi_dma_data tx_dma;
197 const struct s3c64xx_spi_port_config *port_conf;
198 unsigned int port_id;
199};
200
201static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
202{
203 void __iomem *regs = sdd->regs;
204 unsigned long loops;
205 u32 val;
206
207 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
208
209 val = readl(regs + S3C64XX_SPI_CH_CFG);
210 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
211 writel(val, regs + S3C64XX_SPI_CH_CFG);
212
213 val = readl(regs + S3C64XX_SPI_CH_CFG);
214 val |= S3C64XX_SPI_CH_SW_RST;
215 val &= ~S3C64XX_SPI_CH_HS_EN;
216 writel(val, regs + S3C64XX_SPI_CH_CFG);
217
218 /* Flush TxFIFO*/
219 loops = msecs_to_loops(1);
220 do {
221 val = readl(regs + S3C64XX_SPI_STATUS);
222 } while (TX_FIFO_LVL(val, sdd) && loops--);
223
224 if (loops == 0)
225 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
226
227 /* Flush RxFIFO*/
228 loops = msecs_to_loops(1);
229 do {
230 val = readl(regs + S3C64XX_SPI_STATUS);
231 if (RX_FIFO_LVL(val, sdd))
232 readl(regs + S3C64XX_SPI_RX_DATA);
233 else
234 break;
235 } while (loops--);
236
237 if (loops == 0)
238 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
239
240 val = readl(regs + S3C64XX_SPI_CH_CFG);
241 val &= ~S3C64XX_SPI_CH_SW_RST;
242 writel(val, regs + S3C64XX_SPI_CH_CFG);
243
244 val = readl(regs + S3C64XX_SPI_MODE_CFG);
245 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
246 writel(val, regs + S3C64XX_SPI_MODE_CFG);
247}
248
249static void s3c64xx_spi_dmacb(void *data)
250{
251 struct s3c64xx_spi_driver_data *sdd;
252 struct s3c64xx_spi_dma_data *dma = data;
253 unsigned long flags;
254
255 if (dma->direction == DMA_DEV_TO_MEM)
256 sdd = container_of(data,
257 struct s3c64xx_spi_driver_data, rx_dma);
258 else
259 sdd = container_of(data,
260 struct s3c64xx_spi_driver_data, tx_dma);
261
262 spin_lock_irqsave(&sdd->lock, flags);
263
264 if (dma->direction == DMA_DEV_TO_MEM) {
265 sdd->state &= ~RXBUSY;
266 if (!(sdd->state & TXBUSY))
267 complete(&sdd->xfer_completion);
268 } else {
269 sdd->state &= ~TXBUSY;
270 if (!(sdd->state & RXBUSY))
271 complete(&sdd->xfer_completion);
272 }
273
274 spin_unlock_irqrestore(&sdd->lock, flags);
275}
276
277static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
278 struct sg_table *sgt)
279{
280 struct s3c64xx_spi_driver_data *sdd;
281 struct dma_slave_config config;
282 struct dma_async_tx_descriptor *desc;
283 int ret;
284
285 memset(&config, 0, sizeof(config));
286
287 if (dma->direction == DMA_DEV_TO_MEM) {
288 sdd = container_of((void *)dma,
289 struct s3c64xx_spi_driver_data, rx_dma);
290 config.direction = dma->direction;
291 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
292 config.src_addr_width = sdd->cur_bpw / 8;
293 config.src_maxburst = 1;
294 dmaengine_slave_config(dma->ch, &config);
295 } else {
296 sdd = container_of((void *)dma,
297 struct s3c64xx_spi_driver_data, tx_dma);
298 config.direction = dma->direction;
299 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
300 config.dst_addr_width = sdd->cur_bpw / 8;
301 config.dst_maxburst = 1;
302 dmaengine_slave_config(dma->ch, &config);
303 }
304
305 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
306 dma->direction, DMA_PREP_INTERRUPT);
307 if (!desc) {
308 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
309 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
310 return -ENOMEM;
311 }
312
313 desc->callback = s3c64xx_spi_dmacb;
314 desc->callback_param = dma;
315
316 dma->cookie = dmaengine_submit(desc);
317 ret = dma_submit_error(dma->cookie);
318 if (ret) {
319 dev_err(&sdd->pdev->dev, "DMA submission failed");
320 return -EIO;
321 }
322
323 dma_async_issue_pending(dma->ch);
324 return 0;
325}
326
327static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
328{
329 struct s3c64xx_spi_driver_data *sdd =
330 spi_master_get_devdata(spi->master);
331
332 if (sdd->cntrlr_info->no_cs)
333 return;
334
335 if (enable) {
336 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
337 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
338 } else {
339 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
340
341 ssel |= (S3C64XX_SPI_CS_AUTO |
342 S3C64XX_SPI_CS_NSC_CNT_2);
343 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
344 }
345 } else {
346 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
347 writel(S3C64XX_SPI_CS_SIG_INACT,
348 sdd->regs + S3C64XX_SPI_CS_REG);
349 }
350}
351
352static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
353{
354 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
355
356 if (is_polling(sdd))
357 return 0;
358
359 /* Requests DMA channels */
360 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx");
361 if (IS_ERR(sdd->rx_dma.ch)) {
362 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n");
363 sdd->rx_dma.ch = NULL;
364 return 0;
365 }
366
367 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx");
368 if (IS_ERR(sdd->tx_dma.ch)) {
369 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n");
370 dma_release_channel(sdd->rx_dma.ch);
371 sdd->tx_dma.ch = NULL;
372 sdd->rx_dma.ch = NULL;
373 return 0;
374 }
375
376 spi->dma_rx = sdd->rx_dma.ch;
377 spi->dma_tx = sdd->tx_dma.ch;
378
379 return 0;
380}
381
382static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
383{
384 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
385
386 if (is_polling(sdd))
387 return 0;
388
389 /* Releases DMA channels if they are allocated */
390 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
391 dma_release_channel(sdd->rx_dma.ch);
392 dma_release_channel(sdd->tx_dma.ch);
393 sdd->rx_dma.ch = NULL;
394 sdd->tx_dma.ch = NULL;
395 }
396
397 return 0;
398}
399
400static bool s3c64xx_spi_can_dma(struct spi_master *master,
401 struct spi_device *spi,
402 struct spi_transfer *xfer)
403{
404 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
405
406 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
407 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
408 } else {
409 return false;
410 }
411
412}
413
414static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
415 struct spi_transfer *xfer, int dma_mode)
416{
417 void __iomem *regs = sdd->regs;
418 u32 modecfg, chcfg;
419 int ret = 0;
420
421 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
422 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
423
424 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
425 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
426
427 if (dma_mode) {
428 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
429 } else {
430 /* Always shift in data in FIFO, even if xfer is Tx only,
431 * this helps setting PCKT_CNT value for generating clocks
432 * as exactly needed.
433 */
434 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
435 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
436 | S3C64XX_SPI_PACKET_CNT_EN,
437 regs + S3C64XX_SPI_PACKET_CNT);
438 }
439
440 if (xfer->tx_buf != NULL) {
441 sdd->state |= TXBUSY;
442 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
443 if (dma_mode) {
444 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
445 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
446 } else {
447 switch (sdd->cur_bpw) {
448 case 32:
449 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
450 xfer->tx_buf, xfer->len / 4);
451 break;
452 case 16:
453 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
454 xfer->tx_buf, xfer->len / 2);
455 break;
456 default:
457 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
458 xfer->tx_buf, xfer->len);
459 break;
460 }
461 }
462 }
463
464 if (xfer->rx_buf != NULL) {
465 sdd->state |= RXBUSY;
466
467 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
468 && !(sdd->cur_mode & SPI_CPHA))
469 chcfg |= S3C64XX_SPI_CH_HS_EN;
470
471 if (dma_mode) {
472 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
473 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
474 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
475 | S3C64XX_SPI_PACKET_CNT_EN,
476 regs + S3C64XX_SPI_PACKET_CNT);
477 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
478 }
479 }
480
481 if (ret)
482 return ret;
483
484 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
485 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
486
487 return 0;
488}
489
490static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
491 int timeout_ms)
492{
493 void __iomem *regs = sdd->regs;
494 unsigned long val = 1;
495 u32 status;
496
497 /* max fifo depth available */
498 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
499
500 if (timeout_ms)
501 val = msecs_to_loops(timeout_ms);
502
503 do {
504 status = readl(regs + S3C64XX_SPI_STATUS);
505 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
506
507 /* return the actual received data length */
508 return RX_FIFO_LVL(status, sdd);
509}
510
511static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
512 struct spi_transfer *xfer)
513{
514 void __iomem *regs = sdd->regs;
515 unsigned long val;
516 u32 status;
517 int ms;
518
519 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
520 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
521 ms += 30; /* some tolerance */
522 ms = max(ms, 100); /* minimum timeout */
523
524 val = msecs_to_jiffies(ms) + 10;
525 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
526
527 /*
528 * If the previous xfer was completed within timeout, then
529 * proceed further else return -EIO.
530 * DmaTx returns after simply writing data in the FIFO,
531 * w/o waiting for real transmission on the bus to finish.
532 * DmaRx returns only after Dma read data from FIFO which
533 * needs bus transmission to finish, so we don't worry if
534 * Xfer involved Rx(with or without Tx).
535 */
536 if (val && !xfer->rx_buf) {
537 val = msecs_to_loops(10);
538 status = readl(regs + S3C64XX_SPI_STATUS);
539 while ((TX_FIFO_LVL(status, sdd)
540 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
541 && --val) {
542 cpu_relax();
543 status = readl(regs + S3C64XX_SPI_STATUS);
544 }
545
546 }
547
548 /* If timed out while checking rx/tx status return error */
549 if (!val)
550 return -EIO;
551
552 return 0;
553}
554
555static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
556 struct spi_transfer *xfer)
557{
558 void __iomem *regs = sdd->regs;
559 unsigned long val;
560 u32 status;
561 int loops;
562 u32 cpy_len;
563 u8 *buf;
564 int ms;
565
566 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
567 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
568 ms += 10; /* some tolerance */
569
570 val = msecs_to_loops(ms);
571 do {
572 status = readl(regs + S3C64XX_SPI_STATUS);
573 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
574
575 if (!val)
576 return -EIO;
577
578 /* If it was only Tx */
579 if (!xfer->rx_buf) {
580 sdd->state &= ~TXBUSY;
581 return 0;
582 }
583
584 /*
585 * If the receive length is bigger than the controller fifo
586 * size, calculate the loops and read the fifo as many times.
587 * loops = length / max fifo size (calculated by using the
588 * fifo mask).
589 * For any size less than the fifo size the below code is
590 * executed atleast once.
591 */
592 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
593 buf = xfer->rx_buf;
594 do {
595 /* wait for data to be received in the fifo */
596 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
597 (loops ? ms : 0));
598
599 switch (sdd->cur_bpw) {
600 case 32:
601 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
602 buf, cpy_len / 4);
603 break;
604 case 16:
605 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
606 buf, cpy_len / 2);
607 break;
608 default:
609 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
610 buf, cpy_len);
611 break;
612 }
613
614 buf = buf + cpy_len;
615 } while (loops--);
616 sdd->state &= ~RXBUSY;
617
618 return 0;
619}
620
621static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
622{
623 void __iomem *regs = sdd->regs;
624 int ret;
625 u32 val;
626 int div = sdd->port_conf->clk_div;
627
628 /* Disable Clock */
629 if (!sdd->port_conf->clk_from_cmu) {
630 val = readl(regs + S3C64XX_SPI_CLK_CFG);
631 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
632 writel(val, regs + S3C64XX_SPI_CLK_CFG);
633 }
634
635 /* Set Polarity and Phase */
636 val = readl(regs + S3C64XX_SPI_CH_CFG);
637 val &= ~(S3C64XX_SPI_CH_SLAVE |
638 S3C64XX_SPI_CPOL_L |
639 S3C64XX_SPI_CPHA_B);
640
641 if (sdd->cur_mode & SPI_CPOL)
642 val |= S3C64XX_SPI_CPOL_L;
643
644 if (sdd->cur_mode & SPI_CPHA)
645 val |= S3C64XX_SPI_CPHA_B;
646
647 writel(val, regs + S3C64XX_SPI_CH_CFG);
648
649 /* Set Channel & DMA Mode */
650 val = readl(regs + S3C64XX_SPI_MODE_CFG);
651 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
652 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
653
654 switch (sdd->cur_bpw) {
655 case 32:
656 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
657 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
658 break;
659 case 16:
660 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
661 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
662 break;
663 default:
664 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
665 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
666 break;
667 }
668
669 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback)
670 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK;
671
672 writel(val, regs + S3C64XX_SPI_MODE_CFG);
673
674 if (sdd->port_conf->clk_from_cmu) {
675 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div);
676 if (ret)
677 return ret;
678 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div;
679 } else {
680 /* Configure Clock */
681 val = readl(regs + S3C64XX_SPI_CLK_CFG);
682 val &= ~S3C64XX_SPI_PSR_MASK;
683 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1)
684 & S3C64XX_SPI_PSR_MASK);
685 writel(val, regs + S3C64XX_SPI_CLK_CFG);
686
687 /* Enable Clock */
688 val = readl(regs + S3C64XX_SPI_CLK_CFG);
689 val |= S3C64XX_SPI_ENCLK_ENABLE;
690 writel(val, regs + S3C64XX_SPI_CLK_CFG);
691 }
692
693 return 0;
694}
695
696#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
697
698static int s3c64xx_spi_prepare_message(struct spi_master *master,
699 struct spi_message *msg)
700{
701 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
702 struct spi_device *spi = msg->spi;
703 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
704
705 /* Configure feedback delay */
706 if (!cs)
707 /* No delay if not defined */
708 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
709 else
710 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
711
712 return 0;
713}
714
715static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
716{
717 struct spi_controller *ctlr = spi->controller;
718
719 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
720}
721
722static int s3c64xx_spi_transfer_one(struct spi_master *master,
723 struct spi_device *spi,
724 struct spi_transfer *xfer)
725{
726 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
727 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
728 const void *tx_buf = NULL;
729 void *rx_buf = NULL;
730 int target_len = 0, origin_len = 0;
731 int use_dma = 0;
732 int status;
733 u32 speed;
734 u8 bpw;
735 unsigned long flags;
736
737 reinit_completion(&sdd->xfer_completion);
738
739 /* Only BPW and Speed may change across transfers */
740 bpw = xfer->bits_per_word;
741 speed = xfer->speed_hz;
742
743 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
744 sdd->cur_bpw = bpw;
745 sdd->cur_speed = speed;
746 sdd->cur_mode = spi->mode;
747 status = s3c64xx_spi_config(sdd);
748 if (status)
749 return status;
750 }
751
752 if (!is_polling(sdd) && (xfer->len > fifo_len) &&
753 sdd->rx_dma.ch && sdd->tx_dma.ch) {
754 use_dma = 1;
755
756 } else if (xfer->len > fifo_len) {
757 tx_buf = xfer->tx_buf;
758 rx_buf = xfer->rx_buf;
759 origin_len = xfer->len;
760
761 target_len = xfer->len;
762 if (xfer->len > fifo_len)
763 xfer->len = fifo_len;
764 }
765
766 do {
767 spin_lock_irqsave(&sdd->lock, flags);
768
769 /* Pending only which is to be done */
770 sdd->state &= ~RXBUSY;
771 sdd->state &= ~TXBUSY;
772
773 /* Start the signals */
774 s3c64xx_spi_set_cs(spi, true);
775
776 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
777
778 spin_unlock_irqrestore(&sdd->lock, flags);
779
780 if (status) {
781 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
782 break;
783 }
784
785 if (use_dma)
786 status = s3c64xx_wait_for_dma(sdd, xfer);
787 else
788 status = s3c64xx_wait_for_pio(sdd, xfer);
789
790 if (status) {
791 dev_err(&spi->dev,
792 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
793 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
794 (sdd->state & RXBUSY) ? 'f' : 'p',
795 (sdd->state & TXBUSY) ? 'f' : 'p',
796 xfer->len, use_dma ? 1 : 0, status);
797
798 if (use_dma) {
799 struct dma_tx_state s;
800
801 if (xfer->tx_buf && (sdd->state & TXBUSY)) {
802 dmaengine_pause(sdd->tx_dma.ch);
803 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
804 dmaengine_terminate_all(sdd->tx_dma.ch);
805 dev_err(&spi->dev, "TX residue: %d\n", s.residue);
806
807 }
808 if (xfer->rx_buf && (sdd->state & RXBUSY)) {
809 dmaengine_pause(sdd->rx_dma.ch);
810 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
811 dmaengine_terminate_all(sdd->rx_dma.ch);
812 dev_err(&spi->dev, "RX residue: %d\n", s.residue);
813 }
814 }
815 } else {
816 s3c64xx_flush_fifo(sdd);
817 }
818 if (target_len > 0) {
819 target_len -= xfer->len;
820
821 if (xfer->tx_buf)
822 xfer->tx_buf += xfer->len;
823
824 if (xfer->rx_buf)
825 xfer->rx_buf += xfer->len;
826
827 if (target_len > fifo_len)
828 xfer->len = fifo_len;
829 else
830 xfer->len = target_len;
831 }
832 } while (target_len > 0);
833
834 if (origin_len) {
835 /* Restore original xfer buffers and length */
836 xfer->tx_buf = tx_buf;
837 xfer->rx_buf = rx_buf;
838 xfer->len = origin_len;
839 }
840
841 return status;
842}
843
844static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
845 struct spi_device *spi)
846{
847 struct s3c64xx_spi_csinfo *cs;
848 struct device_node *slave_np, *data_np = NULL;
849 u32 fb_delay = 0;
850
851 slave_np = spi->dev.of_node;
852 if (!slave_np) {
853 dev_err(&spi->dev, "device node not found\n");
854 return ERR_PTR(-EINVAL);
855 }
856
857 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
858 if (!cs)
859 return ERR_PTR(-ENOMEM);
860
861 data_np = of_get_child_by_name(slave_np, "controller-data");
862 if (!data_np) {
863 dev_info(&spi->dev, "feedback delay set to default (0)\n");
864 return cs;
865 }
866
867 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
868 cs->fb_delay = fb_delay;
869 of_node_put(data_np);
870 return cs;
871}
872
873/*
874 * Here we only check the validity of requested configuration
875 * and save the configuration in a local data-structure.
876 * The controller is actually configured only just before we
877 * get a message to transfer.
878 */
879static int s3c64xx_spi_setup(struct spi_device *spi)
880{
881 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
882 struct s3c64xx_spi_driver_data *sdd;
883 int err;
884 int div;
885
886 sdd = spi_master_get_devdata(spi->master);
887 if (spi->dev.of_node) {
888 cs = s3c64xx_get_slave_ctrldata(spi);
889 spi->controller_data = cs;
890 }
891
892 /* NULL is fine, we just avoid using the FB delay (=0) */
893 if (IS_ERR(cs)) {
894 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
895 return -ENODEV;
896 }
897
898 if (!spi_get_ctldata(spi))
899 spi_set_ctldata(spi, cs);
900
901 pm_runtime_get_sync(&sdd->pdev->dev);
902
903 div = sdd->port_conf->clk_div;
904
905 /* Check if we can provide the requested rate */
906 if (!sdd->port_conf->clk_from_cmu) {
907 u32 psr, speed;
908
909 /* Max possible */
910 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1);
911
912 if (spi->max_speed_hz > speed)
913 spi->max_speed_hz = speed;
914
915 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
916 psr &= S3C64XX_SPI_PSR_MASK;
917 if (psr == S3C64XX_SPI_PSR_MASK)
918 psr--;
919
920 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
921 if (spi->max_speed_hz < speed) {
922 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
923 psr++;
924 } else {
925 err = -EINVAL;
926 goto setup_exit;
927 }
928 }
929
930 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
931 if (spi->max_speed_hz >= speed) {
932 spi->max_speed_hz = speed;
933 } else {
934 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
935 spi->max_speed_hz);
936 err = -EINVAL;
937 goto setup_exit;
938 }
939 }
940
941 pm_runtime_mark_last_busy(&sdd->pdev->dev);
942 pm_runtime_put_autosuspend(&sdd->pdev->dev);
943 s3c64xx_spi_set_cs(spi, false);
944
945 return 0;
946
947setup_exit:
948 pm_runtime_mark_last_busy(&sdd->pdev->dev);
949 pm_runtime_put_autosuspend(&sdd->pdev->dev);
950 /* setup() returns with device de-selected */
951 s3c64xx_spi_set_cs(spi, false);
952
953 spi_set_ctldata(spi, NULL);
954
955 /* This was dynamically allocated on the DT path */
956 if (spi->dev.of_node)
957 kfree(cs);
958
959 return err;
960}
961
962static void s3c64xx_spi_cleanup(struct spi_device *spi)
963{
964 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
965
966 /* This was dynamically allocated on the DT path */
967 if (spi->dev.of_node)
968 kfree(cs);
969
970 spi_set_ctldata(spi, NULL);
971}
972
973static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
974{
975 struct s3c64xx_spi_driver_data *sdd = data;
976 struct spi_master *spi = sdd->master;
977 unsigned int val, clr = 0;
978
979 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
980
981 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
982 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
983 dev_err(&spi->dev, "RX overrun\n");
984 }
985 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
986 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
987 dev_err(&spi->dev, "RX underrun\n");
988 }
989 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
990 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
991 dev_err(&spi->dev, "TX overrun\n");
992 }
993 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
994 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
995 dev_err(&spi->dev, "TX underrun\n");
996 }
997
998 /* Clear the pending irq by setting and then clearing it */
999 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1000 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1001
1002 return IRQ_HANDLED;
1003}
1004
1005static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
1006{
1007 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1008 void __iomem *regs = sdd->regs;
1009 unsigned int val;
1010
1011 sdd->cur_speed = 0;
1012
1013 if (sci->no_cs)
1014 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
1015 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
1016 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
1017
1018 /* Disable Interrupts - we use Polling if not DMA mode */
1019 writel(0, regs + S3C64XX_SPI_INT_EN);
1020
1021 if (!sdd->port_conf->clk_from_cmu)
1022 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1023 regs + S3C64XX_SPI_CLK_CFG);
1024 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1025 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1026
1027 /* Clear any irq pending bits, should set and clear the bits */
1028 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1029 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1030 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1031 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1032 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1033 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1034
1035 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1036
1037 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1038 val &= ~S3C64XX_SPI_MODE_4BURST;
1039 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1040 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1041 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1042
1043 s3c64xx_flush_fifo(sdd);
1044}
1045
1046#ifdef CONFIG_OF
1047static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1048{
1049 struct s3c64xx_spi_info *sci;
1050 u32 temp;
1051
1052 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1053 if (!sci)
1054 return ERR_PTR(-ENOMEM);
1055
1056 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1057 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1058 sci->src_clk_nr = 0;
1059 } else {
1060 sci->src_clk_nr = temp;
1061 }
1062
1063 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1064 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1065 sci->num_cs = 1;
1066 } else {
1067 sci->num_cs = temp;
1068 }
1069
1070 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1071
1072 return sci;
1073}
1074#else
1075static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1076{
1077 return dev_get_platdata(dev);
1078}
1079#endif
1080
1081static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1082 struct platform_device *pdev)
1083{
1084#ifdef CONFIG_OF
1085 if (pdev->dev.of_node)
1086 return of_device_get_match_data(&pdev->dev);
1087#endif
1088 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1089}
1090
1091static int s3c64xx_spi_probe(struct platform_device *pdev)
1092{
1093 struct resource *mem_res;
1094 struct s3c64xx_spi_driver_data *sdd;
1095 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1096 struct spi_master *master;
1097 int ret, irq;
1098 char clk_name[16];
1099
1100 if (!sci && pdev->dev.of_node) {
1101 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1102 if (IS_ERR(sci))
1103 return PTR_ERR(sci);
1104 }
1105
1106 if (!sci) {
1107 dev_err(&pdev->dev, "platform_data missing!\n");
1108 return -ENODEV;
1109 }
1110
1111 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1112 if (mem_res == NULL) {
1113 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1114 return -ENXIO;
1115 }
1116
1117 irq = platform_get_irq(pdev, 0);
1118 if (irq < 0) {
1119 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1120 return irq;
1121 }
1122
1123 master = spi_alloc_master(&pdev->dev,
1124 sizeof(struct s3c64xx_spi_driver_data));
1125 if (master == NULL) {
1126 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1127 return -ENOMEM;
1128 }
1129
1130 platform_set_drvdata(pdev, master);
1131
1132 sdd = spi_master_get_devdata(master);
1133 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1134 sdd->master = master;
1135 sdd->cntrlr_info = sci;
1136 sdd->pdev = pdev;
1137 sdd->sfr_start = mem_res->start;
1138 if (pdev->dev.of_node) {
1139 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1140 if (ret < 0) {
1141 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1142 ret);
1143 goto err_deref_master;
1144 }
1145 sdd->port_id = ret;
1146 } else {
1147 sdd->port_id = pdev->id;
1148 }
1149
1150 sdd->cur_bpw = 8;
1151
1152 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1153 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1154
1155 master->dev.of_node = pdev->dev.of_node;
1156 master->bus_num = sdd->port_id;
1157 master->setup = s3c64xx_spi_setup;
1158 master->cleanup = s3c64xx_spi_cleanup;
1159 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1160 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1161 master->prepare_message = s3c64xx_spi_prepare_message;
1162 master->transfer_one = s3c64xx_spi_transfer_one;
1163 master->max_transfer_size = s3c64xx_spi_max_transfer_size;
1164 master->num_chipselect = sci->num_cs;
1165 master->use_gpio_descriptors = true;
1166 master->dma_alignment = 8;
1167 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1168 SPI_BPW_MASK(8);
1169 /* the spi->mode bits understood by this driver: */
1170 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1171 if (sdd->port_conf->has_loopback)
1172 master->mode_bits |= SPI_LOOP;
1173 master->auto_runtime_pm = true;
1174 if (!is_polling(sdd))
1175 master->can_dma = s3c64xx_spi_can_dma;
1176
1177 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1178 if (IS_ERR(sdd->regs)) {
1179 ret = PTR_ERR(sdd->regs);
1180 goto err_deref_master;
1181 }
1182
1183 if (sci->cfg_gpio && sci->cfg_gpio()) {
1184 dev_err(&pdev->dev, "Unable to config gpio\n");
1185 ret = -EBUSY;
1186 goto err_deref_master;
1187 }
1188
1189 /* Setup clocks */
1190 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1191 if (IS_ERR(sdd->clk)) {
1192 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1193 ret = PTR_ERR(sdd->clk);
1194 goto err_deref_master;
1195 }
1196
1197 ret = clk_prepare_enable(sdd->clk);
1198 if (ret) {
1199 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1200 goto err_deref_master;
1201 }
1202
1203 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1204 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1205 if (IS_ERR(sdd->src_clk)) {
1206 dev_err(&pdev->dev,
1207 "Unable to acquire clock '%s'\n", clk_name);
1208 ret = PTR_ERR(sdd->src_clk);
1209 goto err_disable_clk;
1210 }
1211
1212 ret = clk_prepare_enable(sdd->src_clk);
1213 if (ret) {
1214 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1215 goto err_disable_clk;
1216 }
1217
1218 if (sdd->port_conf->clk_ioclk) {
1219 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1220 if (IS_ERR(sdd->ioclk)) {
1221 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1222 ret = PTR_ERR(sdd->ioclk);
1223 goto err_disable_src_clk;
1224 }
1225
1226 ret = clk_prepare_enable(sdd->ioclk);
1227 if (ret) {
1228 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1229 goto err_disable_src_clk;
1230 }
1231 }
1232
1233 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1234 pm_runtime_use_autosuspend(&pdev->dev);
1235 pm_runtime_set_active(&pdev->dev);
1236 pm_runtime_enable(&pdev->dev);
1237 pm_runtime_get_sync(&pdev->dev);
1238
1239 /* Setup Deufult Mode */
1240 s3c64xx_spi_hwinit(sdd);
1241
1242 spin_lock_init(&sdd->lock);
1243 init_completion(&sdd->xfer_completion);
1244
1245 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1246 "spi-s3c64xx", sdd);
1247 if (ret != 0) {
1248 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1249 irq, ret);
1250 goto err_pm_put;
1251 }
1252
1253 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1254 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1255 sdd->regs + S3C64XX_SPI_INT_EN);
1256
1257 ret = devm_spi_register_master(&pdev->dev, master);
1258 if (ret != 0) {
1259 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1260 goto err_pm_put;
1261 }
1262
1263 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1264 sdd->port_id, master->num_chipselect);
1265 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1266 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1267
1268 pm_runtime_mark_last_busy(&pdev->dev);
1269 pm_runtime_put_autosuspend(&pdev->dev);
1270
1271 return 0;
1272
1273err_pm_put:
1274 pm_runtime_put_noidle(&pdev->dev);
1275 pm_runtime_disable(&pdev->dev);
1276 pm_runtime_set_suspended(&pdev->dev);
1277
1278 clk_disable_unprepare(sdd->ioclk);
1279err_disable_src_clk:
1280 clk_disable_unprepare(sdd->src_clk);
1281err_disable_clk:
1282 clk_disable_unprepare(sdd->clk);
1283err_deref_master:
1284 spi_master_put(master);
1285
1286 return ret;
1287}
1288
1289static int s3c64xx_spi_remove(struct platform_device *pdev)
1290{
1291 struct spi_master *master = platform_get_drvdata(pdev);
1292 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1293
1294 pm_runtime_get_sync(&pdev->dev);
1295
1296 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1297
1298 if (!is_polling(sdd)) {
1299 dma_release_channel(sdd->rx_dma.ch);
1300 dma_release_channel(sdd->tx_dma.ch);
1301 }
1302
1303 clk_disable_unprepare(sdd->ioclk);
1304
1305 clk_disable_unprepare(sdd->src_clk);
1306
1307 clk_disable_unprepare(sdd->clk);
1308
1309 pm_runtime_put_noidle(&pdev->dev);
1310 pm_runtime_disable(&pdev->dev);
1311 pm_runtime_set_suspended(&pdev->dev);
1312
1313 return 0;
1314}
1315
1316#ifdef CONFIG_PM_SLEEP
1317static int s3c64xx_spi_suspend(struct device *dev)
1318{
1319 struct spi_master *master = dev_get_drvdata(dev);
1320 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1321
1322 int ret = spi_master_suspend(master);
1323 if (ret)
1324 return ret;
1325
1326 ret = pm_runtime_force_suspend(dev);
1327 if (ret < 0)
1328 return ret;
1329
1330 sdd->cur_speed = 0; /* Output Clock is stopped */
1331
1332 return 0;
1333}
1334
1335static int s3c64xx_spi_resume(struct device *dev)
1336{
1337 struct spi_master *master = dev_get_drvdata(dev);
1338 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1339 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1340 int ret;
1341
1342 if (sci->cfg_gpio)
1343 sci->cfg_gpio();
1344
1345 ret = pm_runtime_force_resume(dev);
1346 if (ret < 0)
1347 return ret;
1348
1349 return spi_master_resume(master);
1350}
1351#endif /* CONFIG_PM_SLEEP */
1352
1353#ifdef CONFIG_PM
1354static int s3c64xx_spi_runtime_suspend(struct device *dev)
1355{
1356 struct spi_master *master = dev_get_drvdata(dev);
1357 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1358
1359 clk_disable_unprepare(sdd->clk);
1360 clk_disable_unprepare(sdd->src_clk);
1361 clk_disable_unprepare(sdd->ioclk);
1362
1363 return 0;
1364}
1365
1366static int s3c64xx_spi_runtime_resume(struct device *dev)
1367{
1368 struct spi_master *master = dev_get_drvdata(dev);
1369 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1370 int ret;
1371
1372 if (sdd->port_conf->clk_ioclk) {
1373 ret = clk_prepare_enable(sdd->ioclk);
1374 if (ret != 0)
1375 return ret;
1376 }
1377
1378 ret = clk_prepare_enable(sdd->src_clk);
1379 if (ret != 0)
1380 goto err_disable_ioclk;
1381
1382 ret = clk_prepare_enable(sdd->clk);
1383 if (ret != 0)
1384 goto err_disable_src_clk;
1385
1386 s3c64xx_spi_hwinit(sdd);
1387
1388 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1389 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1390 sdd->regs + S3C64XX_SPI_INT_EN);
1391
1392 return 0;
1393
1394err_disable_src_clk:
1395 clk_disable_unprepare(sdd->src_clk);
1396err_disable_ioclk:
1397 clk_disable_unprepare(sdd->ioclk);
1398
1399 return ret;
1400}
1401#endif /* CONFIG_PM */
1402
1403static const struct dev_pm_ops s3c64xx_spi_pm = {
1404 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1405 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1406 s3c64xx_spi_runtime_resume, NULL)
1407};
1408
1409static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1410 .fifo_lvl_mask = { 0x7f },
1411 .rx_lvl_offset = 13,
1412 .tx_st_done = 21,
1413 .clk_div = 2,
1414 .high_speed = true,
1415};
1416
1417static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1418 .fifo_lvl_mask = { 0x7f, 0x7F },
1419 .rx_lvl_offset = 13,
1420 .tx_st_done = 21,
1421 .clk_div = 2,
1422};
1423
1424static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1425 .fifo_lvl_mask = { 0x1ff, 0x7F },
1426 .rx_lvl_offset = 15,
1427 .tx_st_done = 25,
1428 .clk_div = 2,
1429 .high_speed = true,
1430};
1431
1432static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1433 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1434 .rx_lvl_offset = 15,
1435 .tx_st_done = 25,
1436 .clk_div = 2,
1437 .high_speed = true,
1438 .clk_from_cmu = true,
1439 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1440};
1441
1442static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1443 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1444 .rx_lvl_offset = 15,
1445 .tx_st_done = 25,
1446 .clk_div = 2,
1447 .high_speed = true,
1448 .clk_from_cmu = true,
1449 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1450};
1451
1452static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1453 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1454 .rx_lvl_offset = 15,
1455 .tx_st_done = 25,
1456 .clk_div = 2,
1457 .high_speed = true,
1458 .clk_from_cmu = true,
1459 .clk_ioclk = true,
1460 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1461};
1462
1463static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
1464 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
1465 0x7f, 0x7f, 0x7f, 0x7f},
1466 .rx_lvl_offset = 15,
1467 .tx_st_done = 25,
1468 .clk_div = 4,
1469 .high_speed = true,
1470 .clk_from_cmu = true,
1471 .clk_ioclk = true,
1472 .has_loopback = true,
1473 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1474};
1475
1476static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
1477 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
1478 .rx_lvl_offset = 15,
1479 .tx_st_done = 25,
1480 .clk_div = 2,
1481 .high_speed = true,
1482 .clk_from_cmu = true,
1483 .clk_ioclk = false,
1484 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1485};
1486
1487static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1488 {
1489 .name = "s3c2443-spi",
1490 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1491 }, {
1492 .name = "s3c6410-spi",
1493 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1494 },
1495 { },
1496};
1497
1498static const struct of_device_id s3c64xx_spi_dt_match[] = {
1499 { .compatible = "samsung,s3c2443-spi",
1500 .data = (void *)&s3c2443_spi_port_config,
1501 },
1502 { .compatible = "samsung,s3c6410-spi",
1503 .data = (void *)&s3c6410_spi_port_config,
1504 },
1505 { .compatible = "samsung,s5pv210-spi",
1506 .data = (void *)&s5pv210_spi_port_config,
1507 },
1508 { .compatible = "samsung,exynos4210-spi",
1509 .data = (void *)&exynos4_spi_port_config,
1510 },
1511 { .compatible = "samsung,exynos7-spi",
1512 .data = (void *)&exynos7_spi_port_config,
1513 },
1514 { .compatible = "samsung,exynos5433-spi",
1515 .data = (void *)&exynos5433_spi_port_config,
1516 },
1517 { .compatible = "samsung,exynosautov9-spi",
1518 .data = (void *)&exynosautov9_spi_port_config,
1519 },
1520 { .compatible = "tesla,fsd-spi",
1521 .data = (void *)&fsd_spi_port_config,
1522 },
1523 { },
1524};
1525MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1526
1527static struct platform_driver s3c64xx_spi_driver = {
1528 .driver = {
1529 .name = "s3c64xx-spi",
1530 .pm = &s3c64xx_spi_pm,
1531 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1532 },
1533 .probe = s3c64xx_spi_probe,
1534 .remove = s3c64xx_spi_remove,
1535 .id_table = s3c64xx_spi_driver_ids,
1536};
1537MODULE_ALIAS("platform:s3c64xx-spi");
1538
1539module_platform_driver(s3c64xx_spi_driver);
1540
1541MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1542MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1543MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/workqueue.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/spi/spi.h>
30
31#include <mach/dma.h>
32#include <plat/s3c64xx-spi.h>
33
34/* Registers and bit-fields */
35
36#define S3C64XX_SPI_CH_CFG 0x00
37#define S3C64XX_SPI_CLK_CFG 0x04
38#define S3C64XX_SPI_MODE_CFG 0x08
39#define S3C64XX_SPI_SLAVE_SEL 0x0C
40#define S3C64XX_SPI_INT_EN 0x10
41#define S3C64XX_SPI_STATUS 0x14
42#define S3C64XX_SPI_TX_DATA 0x18
43#define S3C64XX_SPI_RX_DATA 0x1C
44#define S3C64XX_SPI_PACKET_CNT 0x20
45#define S3C64XX_SPI_PENDING_CLR 0x24
46#define S3C64XX_SPI_SWAP_CFG 0x28
47#define S3C64XX_SPI_FB_CLK 0x2C
48
49#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
50#define S3C64XX_SPI_CH_SW_RST (1<<5)
51#define S3C64XX_SPI_CH_SLAVE (1<<4)
52#define S3C64XX_SPI_CPOL_L (1<<3)
53#define S3C64XX_SPI_CPHA_B (1<<2)
54#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
55#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
56
57#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
58#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
59#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
60#define S3C64XX_SPI_PSR_MASK 0xff
61
62#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
63#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
64#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
65#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
66#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
67#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
68#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
69#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
70#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
71#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
72#define S3C64XX_SPI_MODE_4BURST (1<<0)
73
74#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
75#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
76
77#define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
78
79#define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
80 (c)->regs + S3C64XX_SPI_SLAVE_SEL)
81
82#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
83#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
84#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
85#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
86#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
87#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
88#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
89
90#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
91#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
92#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
93#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
94#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
95#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
96
97#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
98
99#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
100#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
101#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
102#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
103#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
104
105#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
106#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
107#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
108#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
109#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
110#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
111#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
112#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
113
114#define S3C64XX_SPI_FBCLK_MSK (3<<0)
115
116#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
117 (((i)->fifo_lvl_mask + 1))) \
118 ? 1 : 0)
119
120#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
121#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
122#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
123
124#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
125#define S3C64XX_SPI_TRAILCNT_OFF 19
126
127#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
128
129#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
130
131#define RXBUSY (1<<2)
132#define TXBUSY (1<<3)
133
134struct s3c64xx_spi_dma_data {
135 unsigned ch;
136 enum dma_data_direction direction;
137 enum dma_ch dmach;
138};
139
140/**
141 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
142 * @clk: Pointer to the spi clock.
143 * @src_clk: Pointer to the clock used to generate SPI signals.
144 * @master: Pointer to the SPI Protocol master.
145 * @cntrlr_info: Platform specific data for the controller this driver manages.
146 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
147 * @queue: To log SPI xfer requests.
148 * @lock: Controller specific lock.
149 * @state: Set of FLAGS to indicate status.
150 * @rx_dmach: Controller's DMA channel for Rx.
151 * @tx_dmach: Controller's DMA channel for Tx.
152 * @sfr_start: BUS address of SPI controller regs.
153 * @regs: Pointer to ioremap'ed controller registers.
154 * @irq: interrupt
155 * @xfer_completion: To indicate completion of xfer task.
156 * @cur_mode: Stores the active configuration of the controller.
157 * @cur_bpw: Stores the active bits per word settings.
158 * @cur_speed: Stores the active xfer clock speed.
159 */
160struct s3c64xx_spi_driver_data {
161 void __iomem *regs;
162 struct clk *clk;
163 struct clk *src_clk;
164 struct platform_device *pdev;
165 struct spi_master *master;
166 struct s3c64xx_spi_info *cntrlr_info;
167 struct spi_device *tgl_spi;
168 struct list_head queue;
169 spinlock_t lock;
170 unsigned long sfr_start;
171 struct completion xfer_completion;
172 unsigned state;
173 unsigned cur_mode, cur_bpw;
174 unsigned cur_speed;
175 struct s3c64xx_spi_dma_data rx_dma;
176 struct s3c64xx_spi_dma_data tx_dma;
177 struct samsung_dma_ops *ops;
178};
179
180static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
181 .name = "samsung-spi-dma",
182};
183
184static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
185{
186 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
187 void __iomem *regs = sdd->regs;
188 unsigned long loops;
189 u32 val;
190
191 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
192
193 val = readl(regs + S3C64XX_SPI_CH_CFG);
194 val |= S3C64XX_SPI_CH_SW_RST;
195 val &= ~S3C64XX_SPI_CH_HS_EN;
196 writel(val, regs + S3C64XX_SPI_CH_CFG);
197
198 /* Flush TxFIFO*/
199 loops = msecs_to_loops(1);
200 do {
201 val = readl(regs + S3C64XX_SPI_STATUS);
202 } while (TX_FIFO_LVL(val, sci) && loops--);
203
204 if (loops == 0)
205 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
206
207 /* Flush RxFIFO*/
208 loops = msecs_to_loops(1);
209 do {
210 val = readl(regs + S3C64XX_SPI_STATUS);
211 if (RX_FIFO_LVL(val, sci))
212 readl(regs + S3C64XX_SPI_RX_DATA);
213 else
214 break;
215 } while (loops--);
216
217 if (loops == 0)
218 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
219
220 val = readl(regs + S3C64XX_SPI_CH_CFG);
221 val &= ~S3C64XX_SPI_CH_SW_RST;
222 writel(val, regs + S3C64XX_SPI_CH_CFG);
223
224 val = readl(regs + S3C64XX_SPI_MODE_CFG);
225 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
226 writel(val, regs + S3C64XX_SPI_MODE_CFG);
227
228 val = readl(regs + S3C64XX_SPI_CH_CFG);
229 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
230 writel(val, regs + S3C64XX_SPI_CH_CFG);
231}
232
233static void s3c64xx_spi_dmacb(void *data)
234{
235 struct s3c64xx_spi_driver_data *sdd;
236 struct s3c64xx_spi_dma_data *dma = data;
237 unsigned long flags;
238
239 if (dma->direction == DMA_DEV_TO_MEM)
240 sdd = container_of(data,
241 struct s3c64xx_spi_driver_data, rx_dma);
242 else
243 sdd = container_of(data,
244 struct s3c64xx_spi_driver_data, tx_dma);
245
246 spin_lock_irqsave(&sdd->lock, flags);
247
248 if (dma->direction == DMA_DEV_TO_MEM) {
249 sdd->state &= ~RXBUSY;
250 if (!(sdd->state & TXBUSY))
251 complete(&sdd->xfer_completion);
252 } else {
253 sdd->state &= ~TXBUSY;
254 if (!(sdd->state & RXBUSY))
255 complete(&sdd->xfer_completion);
256 }
257
258 spin_unlock_irqrestore(&sdd->lock, flags);
259}
260
261static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
262 unsigned len, dma_addr_t buf)
263{
264 struct s3c64xx_spi_driver_data *sdd;
265 struct samsung_dma_prep_info info;
266
267 if (dma->direction == DMA_DEV_TO_MEM)
268 sdd = container_of((void *)dma,
269 struct s3c64xx_spi_driver_data, rx_dma);
270 else
271 sdd = container_of((void *)dma,
272 struct s3c64xx_spi_driver_data, tx_dma);
273
274 info.cap = DMA_SLAVE;
275 info.len = len;
276 info.fp = s3c64xx_spi_dmacb;
277 info.fp_param = dma;
278 info.direction = dma->direction;
279 info.buf = buf;
280
281 sdd->ops->prepare(dma->ch, &info);
282 sdd->ops->trigger(dma->ch);
283}
284
285static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
286{
287 struct samsung_dma_info info;
288
289 sdd->ops = samsung_dma_get_ops();
290
291 info.cap = DMA_SLAVE;
292 info.client = &s3c64xx_spi_dma_client;
293 info.width = sdd->cur_bpw / 8;
294
295 info.direction = sdd->rx_dma.direction;
296 info.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
297 sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &info);
298 info.direction = sdd->tx_dma.direction;
299 info.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
300 sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &info);
301
302 return 1;
303}
304
305static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
306 struct spi_device *spi,
307 struct spi_transfer *xfer, int dma_mode)
308{
309 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
310 void __iomem *regs = sdd->regs;
311 u32 modecfg, chcfg;
312
313 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
314 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
315
316 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
317 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
318
319 if (dma_mode) {
320 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
321 } else {
322 /* Always shift in data in FIFO, even if xfer is Tx only,
323 * this helps setting PCKT_CNT value for generating clocks
324 * as exactly needed.
325 */
326 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
327 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
328 | S3C64XX_SPI_PACKET_CNT_EN,
329 regs + S3C64XX_SPI_PACKET_CNT);
330 }
331
332 if (xfer->tx_buf != NULL) {
333 sdd->state |= TXBUSY;
334 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
335 if (dma_mode) {
336 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
337 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
338 } else {
339 switch (sdd->cur_bpw) {
340 case 32:
341 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
342 xfer->tx_buf, xfer->len / 4);
343 break;
344 case 16:
345 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
346 xfer->tx_buf, xfer->len / 2);
347 break;
348 default:
349 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
350 xfer->tx_buf, xfer->len);
351 break;
352 }
353 }
354 }
355
356 if (xfer->rx_buf != NULL) {
357 sdd->state |= RXBUSY;
358
359 if (sci->high_speed && sdd->cur_speed >= 30000000UL
360 && !(sdd->cur_mode & SPI_CPHA))
361 chcfg |= S3C64XX_SPI_CH_HS_EN;
362
363 if (dma_mode) {
364 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
365 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
366 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
367 | S3C64XX_SPI_PACKET_CNT_EN,
368 regs + S3C64XX_SPI_PACKET_CNT);
369 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
370 }
371 }
372
373 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
374 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
375}
376
377static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
378 struct spi_device *spi)
379{
380 struct s3c64xx_spi_csinfo *cs;
381
382 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
383 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
384 /* Deselect the last toggled device */
385 cs = sdd->tgl_spi->controller_data;
386 cs->set_level(cs->line,
387 spi->mode & SPI_CS_HIGH ? 0 : 1);
388 }
389 sdd->tgl_spi = NULL;
390 }
391
392 cs = spi->controller_data;
393 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
394}
395
396static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
397 struct spi_transfer *xfer, int dma_mode)
398{
399 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
400 void __iomem *regs = sdd->regs;
401 unsigned long val;
402 int ms;
403
404 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
405 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
406 ms += 10; /* some tolerance */
407
408 if (dma_mode) {
409 val = msecs_to_jiffies(ms) + 10;
410 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
411 } else {
412 u32 status;
413 val = msecs_to_loops(ms);
414 do {
415 status = readl(regs + S3C64XX_SPI_STATUS);
416 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
417 }
418
419 if (!val)
420 return -EIO;
421
422 if (dma_mode) {
423 u32 status;
424
425 /*
426 * DmaTx returns after simply writing data in the FIFO,
427 * w/o waiting for real transmission on the bus to finish.
428 * DmaRx returns only after Dma read data from FIFO which
429 * needs bus transmission to finish, so we don't worry if
430 * Xfer involved Rx(with or without Tx).
431 */
432 if (xfer->rx_buf == NULL) {
433 val = msecs_to_loops(10);
434 status = readl(regs + S3C64XX_SPI_STATUS);
435 while ((TX_FIFO_LVL(status, sci)
436 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
437 && --val) {
438 cpu_relax();
439 status = readl(regs + S3C64XX_SPI_STATUS);
440 }
441
442 if (!val)
443 return -EIO;
444 }
445 } else {
446 /* If it was only Tx */
447 if (xfer->rx_buf == NULL) {
448 sdd->state &= ~TXBUSY;
449 return 0;
450 }
451
452 switch (sdd->cur_bpw) {
453 case 32:
454 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
455 xfer->rx_buf, xfer->len / 4);
456 break;
457 case 16:
458 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
459 xfer->rx_buf, xfer->len / 2);
460 break;
461 default:
462 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
463 xfer->rx_buf, xfer->len);
464 break;
465 }
466 sdd->state &= ~RXBUSY;
467 }
468
469 return 0;
470}
471
472static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
473 struct spi_device *spi)
474{
475 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
476
477 if (sdd->tgl_spi == spi)
478 sdd->tgl_spi = NULL;
479
480 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
481}
482
483static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
484{
485 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
486 void __iomem *regs = sdd->regs;
487 u32 val;
488
489 /* Disable Clock */
490 if (sci->clk_from_cmu) {
491 clk_disable(sdd->src_clk);
492 } else {
493 val = readl(regs + S3C64XX_SPI_CLK_CFG);
494 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
495 writel(val, regs + S3C64XX_SPI_CLK_CFG);
496 }
497
498 /* Set Polarity and Phase */
499 val = readl(regs + S3C64XX_SPI_CH_CFG);
500 val &= ~(S3C64XX_SPI_CH_SLAVE |
501 S3C64XX_SPI_CPOL_L |
502 S3C64XX_SPI_CPHA_B);
503
504 if (sdd->cur_mode & SPI_CPOL)
505 val |= S3C64XX_SPI_CPOL_L;
506
507 if (sdd->cur_mode & SPI_CPHA)
508 val |= S3C64XX_SPI_CPHA_B;
509
510 writel(val, regs + S3C64XX_SPI_CH_CFG);
511
512 /* Set Channel & DMA Mode */
513 val = readl(regs + S3C64XX_SPI_MODE_CFG);
514 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
515 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
516
517 switch (sdd->cur_bpw) {
518 case 32:
519 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
520 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
521 break;
522 case 16:
523 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
524 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
525 break;
526 default:
527 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
528 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
529 break;
530 }
531
532 writel(val, regs + S3C64XX_SPI_MODE_CFG);
533
534 if (sci->clk_from_cmu) {
535 /* Configure Clock */
536 /* There is half-multiplier before the SPI */
537 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
538 /* Enable Clock */
539 clk_enable(sdd->src_clk);
540 } else {
541 /* Configure Clock */
542 val = readl(regs + S3C64XX_SPI_CLK_CFG);
543 val &= ~S3C64XX_SPI_PSR_MASK;
544 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
545 & S3C64XX_SPI_PSR_MASK);
546 writel(val, regs + S3C64XX_SPI_CLK_CFG);
547
548 /* Enable Clock */
549 val = readl(regs + S3C64XX_SPI_CLK_CFG);
550 val |= S3C64XX_SPI_ENCLK_ENABLE;
551 writel(val, regs + S3C64XX_SPI_CLK_CFG);
552 }
553}
554
555#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
556
557static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
558 struct spi_message *msg)
559{
560 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
561 struct device *dev = &sdd->pdev->dev;
562 struct spi_transfer *xfer;
563
564 if (msg->is_dma_mapped)
565 return 0;
566
567 /* First mark all xfer unmapped */
568 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
569 xfer->rx_dma = XFER_DMAADDR_INVALID;
570 xfer->tx_dma = XFER_DMAADDR_INVALID;
571 }
572
573 /* Map until end or first fail */
574 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
575
576 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
577 continue;
578
579 if (xfer->tx_buf != NULL) {
580 xfer->tx_dma = dma_map_single(dev,
581 (void *)xfer->tx_buf, xfer->len,
582 DMA_TO_DEVICE);
583 if (dma_mapping_error(dev, xfer->tx_dma)) {
584 dev_err(dev, "dma_map_single Tx failed\n");
585 xfer->tx_dma = XFER_DMAADDR_INVALID;
586 return -ENOMEM;
587 }
588 }
589
590 if (xfer->rx_buf != NULL) {
591 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
592 xfer->len, DMA_FROM_DEVICE);
593 if (dma_mapping_error(dev, xfer->rx_dma)) {
594 dev_err(dev, "dma_map_single Rx failed\n");
595 dma_unmap_single(dev, xfer->tx_dma,
596 xfer->len, DMA_TO_DEVICE);
597 xfer->tx_dma = XFER_DMAADDR_INVALID;
598 xfer->rx_dma = XFER_DMAADDR_INVALID;
599 return -ENOMEM;
600 }
601 }
602 }
603
604 return 0;
605}
606
607static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
608 struct spi_message *msg)
609{
610 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
611 struct device *dev = &sdd->pdev->dev;
612 struct spi_transfer *xfer;
613
614 if (msg->is_dma_mapped)
615 return;
616
617 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
618
619 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
620 continue;
621
622 if (xfer->rx_buf != NULL
623 && xfer->rx_dma != XFER_DMAADDR_INVALID)
624 dma_unmap_single(dev, xfer->rx_dma,
625 xfer->len, DMA_FROM_DEVICE);
626
627 if (xfer->tx_buf != NULL
628 && xfer->tx_dma != XFER_DMAADDR_INVALID)
629 dma_unmap_single(dev, xfer->tx_dma,
630 xfer->len, DMA_TO_DEVICE);
631 }
632}
633
634static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
635 struct spi_message *msg)
636{
637 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
638 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
639 struct spi_device *spi = msg->spi;
640 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
641 struct spi_transfer *xfer;
642 int status = 0, cs_toggle = 0;
643 u32 speed;
644 u8 bpw;
645
646 /* If Master's(controller) state differs from that needed by Slave */
647 if (sdd->cur_speed != spi->max_speed_hz
648 || sdd->cur_mode != spi->mode
649 || sdd->cur_bpw != spi->bits_per_word) {
650 sdd->cur_bpw = spi->bits_per_word;
651 sdd->cur_speed = spi->max_speed_hz;
652 sdd->cur_mode = spi->mode;
653 s3c64xx_spi_config(sdd);
654 }
655
656 /* Map all the transfers if needed */
657 if (s3c64xx_spi_map_mssg(sdd, msg)) {
658 dev_err(&spi->dev,
659 "Xfer: Unable to map message buffers!\n");
660 status = -ENOMEM;
661 goto out;
662 }
663
664 /* Configure feedback delay */
665 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
666
667 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
668
669 unsigned long flags;
670 int use_dma;
671
672 INIT_COMPLETION(sdd->xfer_completion);
673
674 /* Only BPW and Speed may change across transfers */
675 bpw = xfer->bits_per_word ? : spi->bits_per_word;
676 speed = xfer->speed_hz ? : spi->max_speed_hz;
677
678 if (xfer->len % (bpw / 8)) {
679 dev_err(&spi->dev,
680 "Xfer length(%u) not a multiple of word size(%u)\n",
681 xfer->len, bpw / 8);
682 status = -EIO;
683 goto out;
684 }
685
686 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
687 sdd->cur_bpw = bpw;
688 sdd->cur_speed = speed;
689 s3c64xx_spi_config(sdd);
690 }
691
692 /* Polling method for xfers not bigger than FIFO capacity */
693 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
694 use_dma = 0;
695 else
696 use_dma = 1;
697
698 spin_lock_irqsave(&sdd->lock, flags);
699
700 /* Pending only which is to be done */
701 sdd->state &= ~RXBUSY;
702 sdd->state &= ~TXBUSY;
703
704 enable_datapath(sdd, spi, xfer, use_dma);
705
706 /* Slave Select */
707 enable_cs(sdd, spi);
708
709 /* Start the signals */
710 S3C64XX_SPI_ACT(sdd);
711
712 spin_unlock_irqrestore(&sdd->lock, flags);
713
714 status = wait_for_xfer(sdd, xfer, use_dma);
715
716 /* Quiese the signals */
717 S3C64XX_SPI_DEACT(sdd);
718
719 if (status) {
720 dev_err(&spi->dev, "I/O Error: "
721 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
722 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
723 (sdd->state & RXBUSY) ? 'f' : 'p',
724 (sdd->state & TXBUSY) ? 'f' : 'p',
725 xfer->len);
726
727 if (use_dma) {
728 if (xfer->tx_buf != NULL
729 && (sdd->state & TXBUSY))
730 sdd->ops->stop(sdd->tx_dma.ch);
731 if (xfer->rx_buf != NULL
732 && (sdd->state & RXBUSY))
733 sdd->ops->stop(sdd->rx_dma.ch);
734 }
735
736 goto out;
737 }
738
739 if (xfer->delay_usecs)
740 udelay(xfer->delay_usecs);
741
742 if (xfer->cs_change) {
743 /* Hint that the next mssg is gonna be
744 for the same device */
745 if (list_is_last(&xfer->transfer_list,
746 &msg->transfers))
747 cs_toggle = 1;
748 else
749 disable_cs(sdd, spi);
750 }
751
752 msg->actual_length += xfer->len;
753
754 flush_fifo(sdd);
755 }
756
757out:
758 if (!cs_toggle || status)
759 disable_cs(sdd, spi);
760 else
761 sdd->tgl_spi = spi;
762
763 s3c64xx_spi_unmap_mssg(sdd, msg);
764
765 msg->status = status;
766
767 spi_finalize_current_message(master);
768
769 return 0;
770}
771
772static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
773{
774 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
775
776 /* Acquire DMA channels */
777 while (!acquire_dma(sdd))
778 msleep(10);
779
780 pm_runtime_get_sync(&sdd->pdev->dev);
781
782 return 0;
783}
784
785static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
786{
787 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
788
789 /* Free DMA channels */
790 sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
791 sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
792
793 pm_runtime_put(&sdd->pdev->dev);
794
795 return 0;
796}
797
798/*
799 * Here we only check the validity of requested configuration
800 * and save the configuration in a local data-structure.
801 * The controller is actually configured only just before we
802 * get a message to transfer.
803 */
804static int s3c64xx_spi_setup(struct spi_device *spi)
805{
806 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
807 struct s3c64xx_spi_driver_data *sdd;
808 struct s3c64xx_spi_info *sci;
809 struct spi_message *msg;
810 unsigned long flags;
811 int err = 0;
812
813 if (cs == NULL || cs->set_level == NULL) {
814 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
815 return -ENODEV;
816 }
817
818 sdd = spi_master_get_devdata(spi->master);
819 sci = sdd->cntrlr_info;
820
821 spin_lock_irqsave(&sdd->lock, flags);
822
823 list_for_each_entry(msg, &sdd->queue, queue) {
824 /* Is some mssg is already queued for this device */
825 if (msg->spi == spi) {
826 dev_err(&spi->dev,
827 "setup: attempt while mssg in queue!\n");
828 spin_unlock_irqrestore(&sdd->lock, flags);
829 return -EBUSY;
830 }
831 }
832
833 spin_unlock_irqrestore(&sdd->lock, flags);
834
835 if (spi->bits_per_word != 8
836 && spi->bits_per_word != 16
837 && spi->bits_per_word != 32) {
838 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
839 spi->bits_per_word);
840 err = -EINVAL;
841 goto setup_exit;
842 }
843
844 pm_runtime_get_sync(&sdd->pdev->dev);
845
846 /* Check if we can provide the requested rate */
847 if (!sci->clk_from_cmu) {
848 u32 psr, speed;
849
850 /* Max possible */
851 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
852
853 if (spi->max_speed_hz > speed)
854 spi->max_speed_hz = speed;
855
856 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
857 psr &= S3C64XX_SPI_PSR_MASK;
858 if (psr == S3C64XX_SPI_PSR_MASK)
859 psr--;
860
861 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
862 if (spi->max_speed_hz < speed) {
863 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
864 psr++;
865 } else {
866 err = -EINVAL;
867 goto setup_exit;
868 }
869 }
870
871 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
872 if (spi->max_speed_hz >= speed)
873 spi->max_speed_hz = speed;
874 else
875 err = -EINVAL;
876 }
877
878 pm_runtime_put(&sdd->pdev->dev);
879
880setup_exit:
881
882 /* setup() returns with device de-selected */
883 disable_cs(sdd, spi);
884
885 return err;
886}
887
888static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
889{
890 struct s3c64xx_spi_driver_data *sdd = data;
891 struct spi_master *spi = sdd->master;
892 unsigned int val;
893
894 val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
895
896 val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
897 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
898 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
899 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
900
901 writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
902
903 if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
904 dev_err(&spi->dev, "RX overrun\n");
905 if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
906 dev_err(&spi->dev, "RX underrun\n");
907 if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
908 dev_err(&spi->dev, "TX overrun\n");
909 if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
910 dev_err(&spi->dev, "TX underrun\n");
911
912 return IRQ_HANDLED;
913}
914
915static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
916{
917 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
918 void __iomem *regs = sdd->regs;
919 unsigned int val;
920
921 sdd->cur_speed = 0;
922
923 S3C64XX_SPI_DEACT(sdd);
924
925 /* Disable Interrupts - we use Polling if not DMA mode */
926 writel(0, regs + S3C64XX_SPI_INT_EN);
927
928 if (!sci->clk_from_cmu)
929 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
930 regs + S3C64XX_SPI_CLK_CFG);
931 writel(0, regs + S3C64XX_SPI_MODE_CFG);
932 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
933
934 /* Clear any irq pending bits */
935 writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
936 regs + S3C64XX_SPI_PENDING_CLR);
937
938 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
939
940 val = readl(regs + S3C64XX_SPI_MODE_CFG);
941 val &= ~S3C64XX_SPI_MODE_4BURST;
942 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
943 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
944 writel(val, regs + S3C64XX_SPI_MODE_CFG);
945
946 flush_fifo(sdd);
947}
948
949static int __init s3c64xx_spi_probe(struct platform_device *pdev)
950{
951 struct resource *mem_res, *dmatx_res, *dmarx_res;
952 struct s3c64xx_spi_driver_data *sdd;
953 struct s3c64xx_spi_info *sci;
954 struct spi_master *master;
955 int ret, irq;
956 char clk_name[16];
957
958 if (pdev->id < 0) {
959 dev_err(&pdev->dev,
960 "Invalid platform device id-%d\n", pdev->id);
961 return -ENODEV;
962 }
963
964 if (pdev->dev.platform_data == NULL) {
965 dev_err(&pdev->dev, "platform_data missing!\n");
966 return -ENODEV;
967 }
968
969 sci = pdev->dev.platform_data;
970
971 /* Check for availability of necessary resource */
972
973 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
974 if (dmatx_res == NULL) {
975 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
976 return -ENXIO;
977 }
978
979 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
980 if (dmarx_res == NULL) {
981 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
982 return -ENXIO;
983 }
984
985 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
986 if (mem_res == NULL) {
987 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
988 return -ENXIO;
989 }
990
991 irq = platform_get_irq(pdev, 0);
992 if (irq < 0) {
993 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
994 return irq;
995 }
996
997 master = spi_alloc_master(&pdev->dev,
998 sizeof(struct s3c64xx_spi_driver_data));
999 if (master == NULL) {
1000 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1001 return -ENOMEM;
1002 }
1003
1004 platform_set_drvdata(pdev, master);
1005
1006 sdd = spi_master_get_devdata(master);
1007 sdd->master = master;
1008 sdd->cntrlr_info = sci;
1009 sdd->pdev = pdev;
1010 sdd->sfr_start = mem_res->start;
1011 sdd->tx_dma.dmach = dmatx_res->start;
1012 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1013 sdd->rx_dma.dmach = dmarx_res->start;
1014 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1015
1016 sdd->cur_bpw = 8;
1017
1018 master->bus_num = pdev->id;
1019 master->setup = s3c64xx_spi_setup;
1020 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1021 master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1022 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1023 master->num_chipselect = sci->num_cs;
1024 master->dma_alignment = 8;
1025 /* the spi->mode bits understood by this driver: */
1026 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1027
1028 if (request_mem_region(mem_res->start,
1029 resource_size(mem_res), pdev->name) == NULL) {
1030 dev_err(&pdev->dev, "Req mem region failed\n");
1031 ret = -ENXIO;
1032 goto err0;
1033 }
1034
1035 sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
1036 if (sdd->regs == NULL) {
1037 dev_err(&pdev->dev, "Unable to remap IO\n");
1038 ret = -ENXIO;
1039 goto err1;
1040 }
1041
1042 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
1043 dev_err(&pdev->dev, "Unable to config gpio\n");
1044 ret = -EBUSY;
1045 goto err2;
1046 }
1047
1048 /* Setup clocks */
1049 sdd->clk = clk_get(&pdev->dev, "spi");
1050 if (IS_ERR(sdd->clk)) {
1051 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1052 ret = PTR_ERR(sdd->clk);
1053 goto err3;
1054 }
1055
1056 if (clk_enable(sdd->clk)) {
1057 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1058 ret = -EBUSY;
1059 goto err4;
1060 }
1061
1062 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1063 sdd->src_clk = clk_get(&pdev->dev, clk_name);
1064 if (IS_ERR(sdd->src_clk)) {
1065 dev_err(&pdev->dev,
1066 "Unable to acquire clock '%s'\n", clk_name);
1067 ret = PTR_ERR(sdd->src_clk);
1068 goto err5;
1069 }
1070
1071 if (clk_enable(sdd->src_clk)) {
1072 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1073 ret = -EBUSY;
1074 goto err6;
1075 }
1076
1077 /* Setup Deufult Mode */
1078 s3c64xx_spi_hwinit(sdd, pdev->id);
1079
1080 spin_lock_init(&sdd->lock);
1081 init_completion(&sdd->xfer_completion);
1082 INIT_LIST_HEAD(&sdd->queue);
1083
1084 ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd);
1085 if (ret != 0) {
1086 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1087 irq, ret);
1088 goto err7;
1089 }
1090
1091 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1092 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1093 sdd->regs + S3C64XX_SPI_INT_EN);
1094
1095 if (spi_register_master(master)) {
1096 dev_err(&pdev->dev, "cannot register SPI master\n");
1097 ret = -EBUSY;
1098 goto err8;
1099 }
1100
1101 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1102 "with %d Slaves attached\n",
1103 pdev->id, master->num_chipselect);
1104 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1105 mem_res->end, mem_res->start,
1106 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1107
1108 pm_runtime_enable(&pdev->dev);
1109
1110 return 0;
1111
1112err8:
1113 free_irq(irq, sdd);
1114err7:
1115 clk_disable(sdd->src_clk);
1116err6:
1117 clk_put(sdd->src_clk);
1118err5:
1119 clk_disable(sdd->clk);
1120err4:
1121 clk_put(sdd->clk);
1122err3:
1123err2:
1124 iounmap((void *) sdd->regs);
1125err1:
1126 release_mem_region(mem_res->start, resource_size(mem_res));
1127err0:
1128 platform_set_drvdata(pdev, NULL);
1129 spi_master_put(master);
1130
1131 return ret;
1132}
1133
1134static int s3c64xx_spi_remove(struct platform_device *pdev)
1135{
1136 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1137 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1138 struct resource *mem_res;
1139
1140 pm_runtime_disable(&pdev->dev);
1141
1142 spi_unregister_master(master);
1143
1144 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1145
1146 free_irq(platform_get_irq(pdev, 0), sdd);
1147
1148 clk_disable(sdd->src_clk);
1149 clk_put(sdd->src_clk);
1150
1151 clk_disable(sdd->clk);
1152 clk_put(sdd->clk);
1153
1154 iounmap((void *) sdd->regs);
1155
1156 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1157 if (mem_res != NULL)
1158 release_mem_region(mem_res->start, resource_size(mem_res));
1159
1160 platform_set_drvdata(pdev, NULL);
1161 spi_master_put(master);
1162
1163 return 0;
1164}
1165
1166#ifdef CONFIG_PM
1167static int s3c64xx_spi_suspend(struct device *dev)
1168{
1169 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1170 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1171
1172 spi_master_suspend(master);
1173
1174 /* Disable the clock */
1175 clk_disable(sdd->src_clk);
1176 clk_disable(sdd->clk);
1177
1178 sdd->cur_speed = 0; /* Output Clock is stopped */
1179
1180 return 0;
1181}
1182
1183static int s3c64xx_spi_resume(struct device *dev)
1184{
1185 struct platform_device *pdev = to_platform_device(dev);
1186 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1187 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1188 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1189
1190 sci->cfg_gpio(pdev);
1191
1192 /* Enable the clock */
1193 clk_enable(sdd->src_clk);
1194 clk_enable(sdd->clk);
1195
1196 s3c64xx_spi_hwinit(sdd, pdev->id);
1197
1198 spi_master_resume(master);
1199
1200 return 0;
1201}
1202#endif /* CONFIG_PM */
1203
1204#ifdef CONFIG_PM_RUNTIME
1205static int s3c64xx_spi_runtime_suspend(struct device *dev)
1206{
1207 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1208 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1209
1210 clk_disable(sdd->clk);
1211 clk_disable(sdd->src_clk);
1212
1213 return 0;
1214}
1215
1216static int s3c64xx_spi_runtime_resume(struct device *dev)
1217{
1218 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1219 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1220
1221 clk_enable(sdd->src_clk);
1222 clk_enable(sdd->clk);
1223
1224 return 0;
1225}
1226#endif /* CONFIG_PM_RUNTIME */
1227
1228static const struct dev_pm_ops s3c64xx_spi_pm = {
1229 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1230 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1231 s3c64xx_spi_runtime_resume, NULL)
1232};
1233
1234static struct platform_driver s3c64xx_spi_driver = {
1235 .driver = {
1236 .name = "s3c64xx-spi",
1237 .owner = THIS_MODULE,
1238 .pm = &s3c64xx_spi_pm,
1239 },
1240 .remove = s3c64xx_spi_remove,
1241};
1242MODULE_ALIAS("platform:s3c64xx-spi");
1243
1244static int __init s3c64xx_spi_init(void)
1245{
1246 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1247}
1248subsys_initcall(s3c64xx_spi_init);
1249
1250static void __exit s3c64xx_spi_exit(void)
1251{
1252 platform_driver_unregister(&s3c64xx_spi_driver);
1253}
1254module_exit(s3c64xx_spi_exit);
1255
1256MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1257MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1258MODULE_LICENSE("GPL");