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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8#ifndef _ASM_PGTABLE_H
9#define _ASM_PGTABLE_H
10
11#include <linux/mm_types.h>
12#include <linux/mmzone.h>
13#ifdef CONFIG_32BIT
14#include <asm/pgtable-32.h>
15#endif
16#ifdef CONFIG_64BIT
17#include <asm/pgtable-64.h>
18#endif
19
20#include <asm/cmpxchg.h>
21#include <asm/io.h>
22#include <asm/pgtable-bits.h>
23#include <asm/cpu-features.h>
24
25struct mm_struct;
26struct vm_area_struct;
27
28#define PAGE_SHARED vm_get_page_prot(VM_READ|VM_WRITE|VM_SHARED)
29
30#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
31 _PAGE_GLOBAL | _page_cachable_default)
32#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
33 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
34#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
35 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
36
37/*
38 * If _PAGE_NO_EXEC is not defined, we can't do page protection for
39 * execute, and consider it to be the same as read. Also, write
40 * permissions imply read permissions. This is the closest we can get
41 * by reasonable means..
42 */
43
44extern unsigned long _page_cachable_default;
45extern void __update_cache(unsigned long address, pte_t pte);
46
47/*
48 * ZERO_PAGE is a global shared page that is always zero; used
49 * for zero-mapped memory areas etc..
50 */
51
52extern unsigned long empty_zero_page;
53extern unsigned long zero_page_mask;
54
55#define ZERO_PAGE(vaddr) \
56 (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
57#define __HAVE_COLOR_ZERO_PAGE
58
59extern void paging_init(void);
60
61/*
62 * Conversion functions: convert a page and protection to a page entry,
63 * and a page entry and page directory to the page they refer to.
64 */
65#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd))
66
67static inline unsigned long pmd_pfn(pmd_t pmd)
68{
69 return pmd_val(pmd) >> _PFN_SHIFT;
70}
71
72#ifndef CONFIG_MIPS_HUGE_TLB_SUPPORT
73#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
74#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
75
76#define pmd_page_vaddr(pmd) pmd_val(pmd)
77
78#define htw_stop() \
79do { \
80 unsigned long __flags; \
81 \
82 if (cpu_has_htw) { \
83 local_irq_save(__flags); \
84 if(!raw_current_cpu_data.htw_seq++) { \
85 write_c0_pwctl(read_c0_pwctl() & \
86 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
87 back_to_back_c0_hazard(); \
88 } \
89 local_irq_restore(__flags); \
90 } \
91} while(0)
92
93#define htw_start() \
94do { \
95 unsigned long __flags; \
96 \
97 if (cpu_has_htw) { \
98 local_irq_save(__flags); \
99 if (!--raw_current_cpu_data.htw_seq) { \
100 write_c0_pwctl(read_c0_pwctl() | \
101 (1 << MIPS_PWCTL_PWEN_SHIFT)); \
102 back_to_back_c0_hazard(); \
103 } \
104 local_irq_restore(__flags); \
105 } \
106} while(0)
107
108static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
109 pte_t *ptep, pte_t pteval);
110
111#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
112
113#ifdef CONFIG_XPA
114# define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL))
115#else
116# define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
117#endif
118
119#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
120#define pte_no_exec(pte) ((pte).pte_low & _PAGE_NO_EXEC)
121
122static inline void set_pte(pte_t *ptep, pte_t pte)
123{
124 ptep->pte_high = pte.pte_high;
125 smp_wmb();
126 ptep->pte_low = pte.pte_low;
127
128#ifdef CONFIG_XPA
129 if (pte.pte_high & _PAGE_GLOBAL) {
130#else
131 if (pte.pte_low & _PAGE_GLOBAL) {
132#endif
133 pte_t *buddy = ptep_buddy(ptep);
134 /*
135 * Make sure the buddy is global too (if it's !none,
136 * it better already be global)
137 */
138 if (pte_none(*buddy)) {
139 if (!IS_ENABLED(CONFIG_XPA))
140 buddy->pte_low |= _PAGE_GLOBAL;
141 buddy->pte_high |= _PAGE_GLOBAL;
142 }
143 }
144}
145
146static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
147{
148 pte_t null = __pte(0);
149
150 htw_stop();
151 /* Preserve global status for the pair */
152 if (IS_ENABLED(CONFIG_XPA)) {
153 if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
154 null.pte_high = _PAGE_GLOBAL;
155 } else {
156 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
157 null.pte_low = null.pte_high = _PAGE_GLOBAL;
158 }
159
160 set_pte_at(mm, addr, ptep, null);
161 htw_start();
162}
163#else
164
165#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
166#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
167#define pte_no_exec(pte) (pte_val(pte) & _PAGE_NO_EXEC)
168
169/*
170 * Certain architectures need to do special things when pte's
171 * within a page table are directly modified. Thus, the following
172 * hook is made available.
173 */
174static inline void set_pte(pte_t *ptep, pte_t pteval)
175{
176 *ptep = pteval;
177#if !defined(CONFIG_CPU_R3K_TLB)
178 if (pte_val(pteval) & _PAGE_GLOBAL) {
179 pte_t *buddy = ptep_buddy(ptep);
180 /*
181 * Make sure the buddy is global too (if it's !none,
182 * it better already be global)
183 */
184# if defined(CONFIG_PHYS_ADDR_T_64BIT) && !defined(CONFIG_CPU_MIPS32)
185 cmpxchg64(&buddy->pte, 0, _PAGE_GLOBAL);
186# else
187 cmpxchg(&buddy->pte, 0, _PAGE_GLOBAL);
188# endif
189 }
190#endif
191}
192
193static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
194{
195 htw_stop();
196#if !defined(CONFIG_CPU_R3K_TLB)
197 /* Preserve global status for the pair */
198 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
199 set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
200 else
201#endif
202 set_pte_at(mm, addr, ptep, __pte(0));
203 htw_start();
204}
205#endif
206
207static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
208 pte_t *ptep, pte_t pteval)
209{
210
211 if (!pte_present(pteval))
212 goto cache_sync_done;
213
214 if (pte_present(*ptep) && (pte_pfn(*ptep) == pte_pfn(pteval)))
215 goto cache_sync_done;
216
217 __update_cache(addr, pteval);
218cache_sync_done:
219 set_pte(ptep, pteval);
220}
221
222/*
223 * (pmds are folded into puds so this doesn't get actually called,
224 * but the define is needed for a generic inline function.)
225 */
226#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
227
228#ifndef __PAGETABLE_PMD_FOLDED
229/*
230 * (puds are folded into pgds so this doesn't get actually called,
231 * but the define is needed for a generic inline function.)
232 */
233#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
234#endif
235
236#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
237#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1)
238#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
239
240/*
241 * We used to declare this array with size but gcc 3.3 and older are not able
242 * to find that this expression is a constant, so the size is dropped.
243 */
244extern pgd_t swapper_pg_dir[];
245
246/*
247 * Platform specific pte_special() and pte_mkspecial() definitions
248 * are required only when ARCH_HAS_PTE_SPECIAL is enabled.
249 */
250#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
251#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
252static inline int pte_special(pte_t pte)
253{
254 return pte.pte_low & _PAGE_SPECIAL;
255}
256
257static inline pte_t pte_mkspecial(pte_t pte)
258{
259 pte.pte_low |= _PAGE_SPECIAL;
260 return pte;
261}
262#else
263static inline int pte_special(pte_t pte)
264{
265 return pte_val(pte) & _PAGE_SPECIAL;
266}
267
268static inline pte_t pte_mkspecial(pte_t pte)
269{
270 pte_val(pte) |= _PAGE_SPECIAL;
271 return pte;
272}
273#endif
274#endif /* CONFIG_ARCH_HAS_PTE_SPECIAL */
275
276/*
277 * The following only work if pte_present() is true.
278 * Undefined behaviour if not..
279 */
280#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
281static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
282static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
283static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
284
285static inline pte_t pte_wrprotect(pte_t pte)
286{
287 pte.pte_low &= ~_PAGE_WRITE;
288 if (!IS_ENABLED(CONFIG_XPA))
289 pte.pte_low &= ~_PAGE_SILENT_WRITE;
290 pte.pte_high &= ~_PAGE_SILENT_WRITE;
291 return pte;
292}
293
294static inline pte_t pte_mkclean(pte_t pte)
295{
296 pte.pte_low &= ~_PAGE_MODIFIED;
297 if (!IS_ENABLED(CONFIG_XPA))
298 pte.pte_low &= ~_PAGE_SILENT_WRITE;
299 pte.pte_high &= ~_PAGE_SILENT_WRITE;
300 return pte;
301}
302
303static inline pte_t pte_mkold(pte_t pte)
304{
305 pte.pte_low &= ~_PAGE_ACCESSED;
306 if (!IS_ENABLED(CONFIG_XPA))
307 pte.pte_low &= ~_PAGE_SILENT_READ;
308 pte.pte_high &= ~_PAGE_SILENT_READ;
309 return pte;
310}
311
312static inline pte_t pte_mkwrite(pte_t pte)
313{
314 pte.pte_low |= _PAGE_WRITE;
315 if (pte.pte_low & _PAGE_MODIFIED) {
316 if (!IS_ENABLED(CONFIG_XPA))
317 pte.pte_low |= _PAGE_SILENT_WRITE;
318 pte.pte_high |= _PAGE_SILENT_WRITE;
319 }
320 return pte;
321}
322
323static inline pte_t pte_mkdirty(pte_t pte)
324{
325 pte.pte_low |= _PAGE_MODIFIED;
326 if (pte.pte_low & _PAGE_WRITE) {
327 if (!IS_ENABLED(CONFIG_XPA))
328 pte.pte_low |= _PAGE_SILENT_WRITE;
329 pte.pte_high |= _PAGE_SILENT_WRITE;
330 }
331 return pte;
332}
333
334static inline pte_t pte_mkyoung(pte_t pte)
335{
336 pte.pte_low |= _PAGE_ACCESSED;
337 if (!(pte.pte_low & _PAGE_NO_READ)) {
338 if (!IS_ENABLED(CONFIG_XPA))
339 pte.pte_low |= _PAGE_SILENT_READ;
340 pte.pte_high |= _PAGE_SILENT_READ;
341 }
342 return pte;
343}
344#else
345static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
346static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
347static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
348
349static inline pte_t pte_wrprotect(pte_t pte)
350{
351 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
352 return pte;
353}
354
355static inline pte_t pte_mkclean(pte_t pte)
356{
357 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
358 return pte;
359}
360
361static inline pte_t pte_mkold(pte_t pte)
362{
363 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
364 return pte;
365}
366
367static inline pte_t pte_mkwrite(pte_t pte)
368{
369 pte_val(pte) |= _PAGE_WRITE;
370 if (pte_val(pte) & _PAGE_MODIFIED)
371 pte_val(pte) |= _PAGE_SILENT_WRITE;
372 return pte;
373}
374
375static inline pte_t pte_mkdirty(pte_t pte)
376{
377 pte_val(pte) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
378 if (pte_val(pte) & _PAGE_WRITE)
379 pte_val(pte) |= _PAGE_SILENT_WRITE;
380 return pte;
381}
382
383static inline pte_t pte_mkyoung(pte_t pte)
384{
385 pte_val(pte) |= _PAGE_ACCESSED;
386 if (!(pte_val(pte) & _PAGE_NO_READ))
387 pte_val(pte) |= _PAGE_SILENT_READ;
388 return pte;
389}
390
391#define pte_sw_mkyoung pte_mkyoung
392
393#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
394static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
395
396static inline pte_t pte_mkhuge(pte_t pte)
397{
398 pte_val(pte) |= _PAGE_HUGE;
399 return pte;
400}
401
402#define pmd_write pmd_write
403static inline int pmd_write(pmd_t pmd)
404{
405 return !!(pmd_val(pmd) & _PAGE_WRITE);
406}
407
408static inline struct page *pmd_page(pmd_t pmd)
409{
410 if (pmd_val(pmd) & _PAGE_HUGE)
411 return pfn_to_page(pmd_pfn(pmd));
412
413 return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT);
414}
415#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
416
417#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
418static inline bool pte_soft_dirty(pte_t pte)
419{
420 return pte_val(pte) & _PAGE_SOFT_DIRTY;
421}
422#define pte_swp_soft_dirty pte_soft_dirty
423
424static inline pte_t pte_mksoft_dirty(pte_t pte)
425{
426 pte_val(pte) |= _PAGE_SOFT_DIRTY;
427 return pte;
428}
429#define pte_swp_mksoft_dirty pte_mksoft_dirty
430
431static inline pte_t pte_clear_soft_dirty(pte_t pte)
432{
433 pte_val(pte) &= ~(_PAGE_SOFT_DIRTY);
434 return pte;
435}
436#define pte_swp_clear_soft_dirty pte_clear_soft_dirty
437
438#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
439
440#endif
441
442/*
443 * Macro to make mark a page protection value as "uncacheable". Note
444 * that "protection" is really a misnomer here as the protection value
445 * contains the memory attribute bits, dirty bits, and various other
446 * bits as well.
447 */
448#define pgprot_noncached pgprot_noncached
449
450static inline pgprot_t pgprot_noncached(pgprot_t _prot)
451{
452 unsigned long prot = pgprot_val(_prot);
453
454 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
455
456 return __pgprot(prot);
457}
458
459#define pgprot_writecombine pgprot_writecombine
460
461static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
462{
463 unsigned long prot = pgprot_val(_prot);
464
465 /* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */
466 prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine;
467
468 return __pgprot(prot);
469}
470
471static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
472 unsigned long address)
473{
474}
475
476#define __HAVE_ARCH_PTE_SAME
477static inline int pte_same(pte_t pte_a, pte_t pte_b)
478{
479 return pte_val(pte_a) == pte_val(pte_b);
480}
481
482#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
483static inline int ptep_set_access_flags(struct vm_area_struct *vma,
484 unsigned long address, pte_t *ptep,
485 pte_t entry, int dirty)
486{
487 if (!pte_same(*ptep, entry))
488 set_pte_at(vma->vm_mm, address, ptep, entry);
489 /*
490 * update_mmu_cache will unconditionally execute, handling both
491 * the case that the PTE changed and the spurious fault case.
492 */
493 return true;
494}
495
496/*
497 * Conversion functions: convert a page and protection to a page entry,
498 * and a page entry and page directory to the page they refer to.
499 */
500#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
501
502#if defined(CONFIG_XPA)
503static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
504{
505 pte.pte_low &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
506 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
507 pte.pte_low |= pgprot_val(newprot) & ~_PFNX_MASK;
508 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
509 return pte;
510}
511#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
512static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
513{
514 pte.pte_low &= _PAGE_CHG_MASK;
515 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
516 pte.pte_low |= pgprot_val(newprot);
517 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
518 return pte;
519}
520#else
521static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
522{
523 pte_val(pte) &= _PAGE_CHG_MASK;
524 pte_val(pte) |= pgprot_val(newprot) & ~_PAGE_CHG_MASK;
525 if ((pte_val(pte) & _PAGE_ACCESSED) && !(pte_val(pte) & _PAGE_NO_READ))
526 pte_val(pte) |= _PAGE_SILENT_READ;
527 return pte;
528}
529#endif
530
531
532extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
533 pte_t pte);
534
535static inline void update_mmu_cache(struct vm_area_struct *vma,
536 unsigned long address, pte_t *ptep)
537{
538 pte_t pte = *ptep;
539 __update_tlb(vma, address, pte);
540}
541
542#define __HAVE_ARCH_UPDATE_MMU_TLB
543#define update_mmu_tlb update_mmu_cache
544
545static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
546 unsigned long address, pmd_t *pmdp)
547{
548 pte_t pte = *(pte_t *)pmdp;
549
550 __update_tlb(vma, address, pte);
551}
552
553/*
554 * Allow physical addresses to be fixed up to help 36-bit peripherals.
555 */
556#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
557phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size);
558int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
559 unsigned long pfn, unsigned long size, pgprot_t prot);
560#define io_remap_pfn_range io_remap_pfn_range
561#else
562#define fixup_bigphys_addr(addr, size) (addr)
563#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
564
565#ifdef CONFIG_TRANSPARENT_HUGEPAGE
566
567/* We don't have hardware dirty/accessed bits, generic_pmdp_establish is fine.*/
568#define pmdp_establish generic_pmdp_establish
569
570#define has_transparent_hugepage has_transparent_hugepage
571extern int has_transparent_hugepage(void);
572
573static inline int pmd_trans_huge(pmd_t pmd)
574{
575 return !!(pmd_val(pmd) & _PAGE_HUGE);
576}
577
578static inline pmd_t pmd_mkhuge(pmd_t pmd)
579{
580 pmd_val(pmd) |= _PAGE_HUGE;
581
582 return pmd;
583}
584
585extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
586 pmd_t *pmdp, pmd_t pmd);
587
588static inline pmd_t pmd_wrprotect(pmd_t pmd)
589{
590 pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
591 return pmd;
592}
593
594static inline pmd_t pmd_mkwrite(pmd_t pmd)
595{
596 pmd_val(pmd) |= _PAGE_WRITE;
597 if (pmd_val(pmd) & _PAGE_MODIFIED)
598 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
599
600 return pmd;
601}
602
603static inline int pmd_dirty(pmd_t pmd)
604{
605 return !!(pmd_val(pmd) & _PAGE_MODIFIED);
606}
607
608static inline pmd_t pmd_mkclean(pmd_t pmd)
609{
610 pmd_val(pmd) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
611 return pmd;
612}
613
614static inline pmd_t pmd_mkdirty(pmd_t pmd)
615{
616 pmd_val(pmd) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
617 if (pmd_val(pmd) & _PAGE_WRITE)
618 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
619
620 return pmd;
621}
622
623#define pmd_young pmd_young
624static inline int pmd_young(pmd_t pmd)
625{
626 return !!(pmd_val(pmd) & _PAGE_ACCESSED);
627}
628
629static inline pmd_t pmd_mkold(pmd_t pmd)
630{
631 pmd_val(pmd) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
632
633 return pmd;
634}
635
636static inline pmd_t pmd_mkyoung(pmd_t pmd)
637{
638 pmd_val(pmd) |= _PAGE_ACCESSED;
639
640 if (!(pmd_val(pmd) & _PAGE_NO_READ))
641 pmd_val(pmd) |= _PAGE_SILENT_READ;
642
643 return pmd;
644}
645
646#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
647static inline int pmd_soft_dirty(pmd_t pmd)
648{
649 return !!(pmd_val(pmd) & _PAGE_SOFT_DIRTY);
650}
651
652static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
653{
654 pmd_val(pmd) |= _PAGE_SOFT_DIRTY;
655 return pmd;
656}
657
658static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
659{
660 pmd_val(pmd) &= ~(_PAGE_SOFT_DIRTY);
661 return pmd;
662}
663
664#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
665
666/* Extern to avoid header file madness */
667extern pmd_t mk_pmd(struct page *page, pgprot_t prot);
668
669static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
670{
671 pmd_val(pmd) = (pmd_val(pmd) & (_PAGE_CHG_MASK | _PAGE_HUGE)) |
672 (pgprot_val(newprot) & ~_PAGE_CHG_MASK);
673 return pmd;
674}
675
676static inline pmd_t pmd_mkinvalid(pmd_t pmd)
677{
678 pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY);
679
680 return pmd;
681}
682
683/*
684 * The generic version pmdp_huge_get_and_clear uses a version of pmd_clear() with a
685 * different prototype.
686 */
687#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
688static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
689 unsigned long address, pmd_t *pmdp)
690{
691 pmd_t old = *pmdp;
692
693 pmd_clear(pmdp);
694
695 return old;
696}
697
698#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
699
700#ifdef _PAGE_HUGE
701#define pmd_leaf(pmd) ((pmd_val(pmd) & _PAGE_HUGE) != 0)
702#define pud_leaf(pud) ((pud_val(pud) & _PAGE_HUGE) != 0)
703#endif
704
705#define gup_fast_permitted(start, end) (!cpu_has_dc_aliases)
706
707/*
708 * We provide our own get_unmapped area to cope with the virtual aliasing
709 * constraints placed on us by the cache architecture.
710 */
711#define HAVE_ARCH_UNMAPPED_AREA
712#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
713
714#endif /* _ASM_PGTABLE_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8#ifndef _ASM_PGTABLE_H
9#define _ASM_PGTABLE_H
10
11#include <linux/mm_types.h>
12#include <linux/mmzone.h>
13#ifdef CONFIG_32BIT
14#include <asm/pgtable-32.h>
15#endif
16#ifdef CONFIG_64BIT
17#include <asm/pgtable-64.h>
18#endif
19
20#include <asm/cmpxchg.h>
21#include <asm/io.h>
22#include <asm/pgtable-bits.h>
23#include <asm/cpu-features.h>
24
25struct mm_struct;
26struct vm_area_struct;
27
28#define PAGE_SHARED vm_get_page_prot(VM_READ|VM_WRITE|VM_SHARED)
29
30#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
31 _PAGE_GLOBAL | _page_cachable_default)
32#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
33 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
34#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
35 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
36
37/*
38 * If _PAGE_NO_EXEC is not defined, we can't do page protection for
39 * execute, and consider it to be the same as read. Also, write
40 * permissions imply read permissions. This is the closest we can get
41 * by reasonable means..
42 */
43
44extern unsigned long _page_cachable_default;
45extern void __update_cache(unsigned long address, pte_t pte);
46
47/*
48 * ZERO_PAGE is a global shared page that is always zero; used
49 * for zero-mapped memory areas etc..
50 */
51
52extern unsigned long empty_zero_page;
53extern unsigned long zero_page_mask;
54
55#define ZERO_PAGE(vaddr) \
56 (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
57#define __HAVE_COLOR_ZERO_PAGE
58
59extern void paging_init(void);
60
61/*
62 * Conversion functions: convert a page and protection to a page entry,
63 * and a page entry and page directory to the page they refer to.
64 */
65#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd))
66
67static inline unsigned long pmd_pfn(pmd_t pmd)
68{
69 return pmd_val(pmd) >> PFN_PTE_SHIFT;
70}
71
72#ifndef CONFIG_MIPS_HUGE_TLB_SUPPORT
73#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
74#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
75
76#define pmd_page_vaddr(pmd) pmd_val(pmd)
77
78#define htw_stop() \
79do { \
80 unsigned long __flags; \
81 \
82 if (cpu_has_htw) { \
83 local_irq_save(__flags); \
84 if(!raw_current_cpu_data.htw_seq++) { \
85 write_c0_pwctl(read_c0_pwctl() & \
86 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
87 back_to_back_c0_hazard(); \
88 } \
89 local_irq_restore(__flags); \
90 } \
91} while(0)
92
93#define htw_start() \
94do { \
95 unsigned long __flags; \
96 \
97 if (cpu_has_htw) { \
98 local_irq_save(__flags); \
99 if (!--raw_current_cpu_data.htw_seq) { \
100 write_c0_pwctl(read_c0_pwctl() | \
101 (1 << MIPS_PWCTL_PWEN_SHIFT)); \
102 back_to_back_c0_hazard(); \
103 } \
104 local_irq_restore(__flags); \
105 } \
106} while(0)
107
108#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
109
110#ifdef CONFIG_XPA
111# define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL))
112#else
113# define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
114#endif
115
116#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
117#define pte_no_exec(pte) ((pte).pte_low & _PAGE_NO_EXEC)
118
119static inline void set_pte(pte_t *ptep, pte_t pte)
120{
121 ptep->pte_high = pte.pte_high;
122 smp_wmb();
123 ptep->pte_low = pte.pte_low;
124
125#ifdef CONFIG_XPA
126 if (pte.pte_high & _PAGE_GLOBAL) {
127#else
128 if (pte.pte_low & _PAGE_GLOBAL) {
129#endif
130 pte_t *buddy = ptep_buddy(ptep);
131 /*
132 * Make sure the buddy is global too (if it's !none,
133 * it better already be global)
134 */
135 if (pte_none(*buddy)) {
136 if (!IS_ENABLED(CONFIG_XPA))
137 buddy->pte_low |= _PAGE_GLOBAL;
138 buddy->pte_high |= _PAGE_GLOBAL;
139 }
140 }
141}
142
143static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
144{
145 pte_t null = __pte(0);
146
147 htw_stop();
148 /* Preserve global status for the pair */
149 if (IS_ENABLED(CONFIG_XPA)) {
150 if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
151 null.pte_high = _PAGE_GLOBAL;
152 } else {
153 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
154 null.pte_low = null.pte_high = _PAGE_GLOBAL;
155 }
156
157 set_pte(ptep, null);
158 htw_start();
159}
160#else
161
162#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
163#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
164#define pte_no_exec(pte) (pte_val(pte) & _PAGE_NO_EXEC)
165
166/*
167 * Certain architectures need to do special things when pte's
168 * within a page table are directly modified. Thus, the following
169 * hook is made available.
170 */
171static inline void set_pte(pte_t *ptep, pte_t pteval)
172{
173 *ptep = pteval;
174#if !defined(CONFIG_CPU_R3K_TLB)
175 if (pte_val(pteval) & _PAGE_GLOBAL) {
176 pte_t *buddy = ptep_buddy(ptep);
177 /*
178 * Make sure the buddy is global too (if it's !none,
179 * it better already be global)
180 */
181# if defined(CONFIG_PHYS_ADDR_T_64BIT) && !defined(CONFIG_CPU_MIPS32)
182 cmpxchg64(&buddy->pte, 0, _PAGE_GLOBAL);
183# else
184 cmpxchg(&buddy->pte, 0, _PAGE_GLOBAL);
185# endif
186 }
187#endif
188}
189
190static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
191{
192 htw_stop();
193#if !defined(CONFIG_CPU_R3K_TLB)
194 /* Preserve global status for the pair */
195 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
196 set_pte(ptep, __pte(_PAGE_GLOBAL));
197 else
198#endif
199 set_pte(ptep, __pte(0));
200 htw_start();
201}
202#endif
203
204static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
205 pte_t *ptep, pte_t pte, unsigned int nr)
206{
207 unsigned int i;
208 bool do_sync = false;
209
210 for (i = 0; i < nr; i++) {
211 if (!pte_present(pte))
212 continue;
213 if (pte_present(ptep[i]) &&
214 (pte_pfn(ptep[i]) == pte_pfn(pte)))
215 continue;
216 do_sync = true;
217 }
218
219 if (do_sync)
220 __update_cache(addr, pte);
221
222 for (;;) {
223 set_pte(ptep, pte);
224 if (--nr == 0)
225 break;
226 ptep++;
227 pte = __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT));
228 }
229}
230#define set_ptes set_ptes
231
232/*
233 * (pmds are folded into puds so this doesn't get actually called,
234 * but the define is needed for a generic inline function.)
235 */
236#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
237
238#ifndef __PAGETABLE_PMD_FOLDED
239/*
240 * (puds are folded into pgds so this doesn't get actually called,
241 * but the define is needed for a generic inline function.)
242 */
243#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
244#endif
245
246#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
247#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1)
248#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
249
250/*
251 * We used to declare this array with size but gcc 3.3 and older are not able
252 * to find that this expression is a constant, so the size is dropped.
253 */
254extern pgd_t swapper_pg_dir[];
255
256/*
257 * Platform specific pte_special() and pte_mkspecial() definitions
258 * are required only when ARCH_HAS_PTE_SPECIAL is enabled.
259 */
260#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
261#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
262static inline int pte_special(pte_t pte)
263{
264 return pte.pte_low & _PAGE_SPECIAL;
265}
266
267static inline pte_t pte_mkspecial(pte_t pte)
268{
269 pte.pte_low |= _PAGE_SPECIAL;
270 return pte;
271}
272#else
273static inline int pte_special(pte_t pte)
274{
275 return pte_val(pte) & _PAGE_SPECIAL;
276}
277
278static inline pte_t pte_mkspecial(pte_t pte)
279{
280 pte_val(pte) |= _PAGE_SPECIAL;
281 return pte;
282}
283#endif
284#endif /* CONFIG_ARCH_HAS_PTE_SPECIAL */
285
286/*
287 * The following only work if pte_present() is true.
288 * Undefined behaviour if not..
289 */
290#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
291static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
292static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
293static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
294
295static inline pte_t pte_wrprotect(pte_t pte)
296{
297 pte.pte_low &= ~_PAGE_WRITE;
298 if (!IS_ENABLED(CONFIG_XPA))
299 pte.pte_low &= ~_PAGE_SILENT_WRITE;
300 pte.pte_high &= ~_PAGE_SILENT_WRITE;
301 return pte;
302}
303
304static inline pte_t pte_mkclean(pte_t pte)
305{
306 pte.pte_low &= ~_PAGE_MODIFIED;
307 if (!IS_ENABLED(CONFIG_XPA))
308 pte.pte_low &= ~_PAGE_SILENT_WRITE;
309 pte.pte_high &= ~_PAGE_SILENT_WRITE;
310 return pte;
311}
312
313static inline pte_t pte_mkold(pte_t pte)
314{
315 pte.pte_low &= ~_PAGE_ACCESSED;
316 if (!IS_ENABLED(CONFIG_XPA))
317 pte.pte_low &= ~_PAGE_SILENT_READ;
318 pte.pte_high &= ~_PAGE_SILENT_READ;
319 return pte;
320}
321
322static inline pte_t pte_mkwrite_novma(pte_t pte)
323{
324 pte.pte_low |= _PAGE_WRITE;
325 if (pte.pte_low & _PAGE_MODIFIED) {
326 if (!IS_ENABLED(CONFIG_XPA))
327 pte.pte_low |= _PAGE_SILENT_WRITE;
328 pte.pte_high |= _PAGE_SILENT_WRITE;
329 }
330 return pte;
331}
332
333static inline pte_t pte_mkdirty(pte_t pte)
334{
335 pte.pte_low |= _PAGE_MODIFIED;
336 if (pte.pte_low & _PAGE_WRITE) {
337 if (!IS_ENABLED(CONFIG_XPA))
338 pte.pte_low |= _PAGE_SILENT_WRITE;
339 pte.pte_high |= _PAGE_SILENT_WRITE;
340 }
341 return pte;
342}
343
344static inline pte_t pte_mkyoung(pte_t pte)
345{
346 pte.pte_low |= _PAGE_ACCESSED;
347 if (!(pte.pte_low & _PAGE_NO_READ)) {
348 if (!IS_ENABLED(CONFIG_XPA))
349 pte.pte_low |= _PAGE_SILENT_READ;
350 pte.pte_high |= _PAGE_SILENT_READ;
351 }
352 return pte;
353}
354#else
355static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
356static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
357static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
358
359static inline pte_t pte_wrprotect(pte_t pte)
360{
361 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
362 return pte;
363}
364
365static inline pte_t pte_mkclean(pte_t pte)
366{
367 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
368 return pte;
369}
370
371static inline pte_t pte_mkold(pte_t pte)
372{
373 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
374 return pte;
375}
376
377static inline pte_t pte_mkwrite_novma(pte_t pte)
378{
379 pte_val(pte) |= _PAGE_WRITE;
380 if (pte_val(pte) & _PAGE_MODIFIED)
381 pte_val(pte) |= _PAGE_SILENT_WRITE;
382 return pte;
383}
384
385static inline pte_t pte_mkdirty(pte_t pte)
386{
387 pte_val(pte) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
388 if (pte_val(pte) & _PAGE_WRITE)
389 pte_val(pte) |= _PAGE_SILENT_WRITE;
390 return pte;
391}
392
393static inline pte_t pte_mkyoung(pte_t pte)
394{
395 pte_val(pte) |= _PAGE_ACCESSED;
396 if (!(pte_val(pte) & _PAGE_NO_READ))
397 pte_val(pte) |= _PAGE_SILENT_READ;
398 return pte;
399}
400
401#define pte_sw_mkyoung pte_mkyoung
402
403#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
404static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
405
406static inline pte_t pte_mkhuge(pte_t pte)
407{
408 pte_val(pte) |= _PAGE_HUGE;
409 return pte;
410}
411
412#define pmd_write pmd_write
413static inline int pmd_write(pmd_t pmd)
414{
415 return !!(pmd_val(pmd) & _PAGE_WRITE);
416}
417
418static inline struct page *pmd_page(pmd_t pmd)
419{
420 if (pmd_val(pmd) & _PAGE_HUGE)
421 return pfn_to_page(pmd_pfn(pmd));
422
423 return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT);
424}
425#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
426
427#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
428static inline bool pte_soft_dirty(pte_t pte)
429{
430 return pte_val(pte) & _PAGE_SOFT_DIRTY;
431}
432#define pte_swp_soft_dirty pte_soft_dirty
433
434static inline pte_t pte_mksoft_dirty(pte_t pte)
435{
436 pte_val(pte) |= _PAGE_SOFT_DIRTY;
437 return pte;
438}
439#define pte_swp_mksoft_dirty pte_mksoft_dirty
440
441static inline pte_t pte_clear_soft_dirty(pte_t pte)
442{
443 pte_val(pte) &= ~(_PAGE_SOFT_DIRTY);
444 return pte;
445}
446#define pte_swp_clear_soft_dirty pte_clear_soft_dirty
447
448#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
449
450#endif
451
452/*
453 * Macro to make mark a page protection value as "uncacheable". Note
454 * that "protection" is really a misnomer here as the protection value
455 * contains the memory attribute bits, dirty bits, and various other
456 * bits as well.
457 */
458#define pgprot_noncached pgprot_noncached
459
460static inline pgprot_t pgprot_noncached(pgprot_t _prot)
461{
462 unsigned long prot = pgprot_val(_prot);
463
464 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
465
466 return __pgprot(prot);
467}
468
469#define pgprot_writecombine pgprot_writecombine
470
471static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
472{
473 unsigned long prot = pgprot_val(_prot);
474
475 /* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */
476 prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine;
477
478 return __pgprot(prot);
479}
480
481static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
482 unsigned long address,
483 pte_t *ptep)
484{
485}
486
487#define __HAVE_ARCH_PTE_SAME
488static inline int pte_same(pte_t pte_a, pte_t pte_b)
489{
490 return pte_val(pte_a) == pte_val(pte_b);
491}
492
493#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
494static inline int ptep_set_access_flags(struct vm_area_struct *vma,
495 unsigned long address, pte_t *ptep,
496 pte_t entry, int dirty)
497{
498 if (!pte_same(*ptep, entry))
499 set_pte(ptep, entry);
500 /*
501 * update_mmu_cache will unconditionally execute, handling both
502 * the case that the PTE changed and the spurious fault case.
503 */
504 return true;
505}
506
507/*
508 * Conversion functions: convert a page and protection to a page entry,
509 * and a page entry and page directory to the page they refer to.
510 */
511#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
512
513#if defined(CONFIG_XPA)
514static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
515{
516 pte.pte_low &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
517 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
518 pte.pte_low |= pgprot_val(newprot) & ~_PFNX_MASK;
519 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
520 return pte;
521}
522#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
523static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
524{
525 pte.pte_low &= _PAGE_CHG_MASK;
526 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
527 pte.pte_low |= pgprot_val(newprot);
528 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
529 return pte;
530}
531#else
532static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
533{
534 pte_val(pte) &= _PAGE_CHG_MASK;
535 pte_val(pte) |= pgprot_val(newprot) & ~_PAGE_CHG_MASK;
536 if ((pte_val(pte) & _PAGE_ACCESSED) && !(pte_val(pte) & _PAGE_NO_READ))
537 pte_val(pte) |= _PAGE_SILENT_READ;
538 return pte;
539}
540#endif
541
542#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
543static inline int pte_swp_exclusive(pte_t pte)
544{
545 return pte.pte_low & _PAGE_SWP_EXCLUSIVE;
546}
547
548static inline pte_t pte_swp_mkexclusive(pte_t pte)
549{
550 pte.pte_low |= _PAGE_SWP_EXCLUSIVE;
551 return pte;
552}
553
554static inline pte_t pte_swp_clear_exclusive(pte_t pte)
555{
556 pte.pte_low &= ~_PAGE_SWP_EXCLUSIVE;
557 return pte;
558}
559#else
560static inline int pte_swp_exclusive(pte_t pte)
561{
562 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
563}
564
565static inline pte_t pte_swp_mkexclusive(pte_t pte)
566{
567 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
568 return pte;
569}
570
571static inline pte_t pte_swp_clear_exclusive(pte_t pte)
572{
573 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
574 return pte;
575}
576#endif
577
578extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
579 pte_t pte);
580
581static inline void update_mmu_cache_range(struct vm_fault *vmf,
582 struct vm_area_struct *vma, unsigned long address,
583 pte_t *ptep, unsigned int nr)
584{
585 for (;;) {
586 pte_t pte = *ptep;
587 __update_tlb(vma, address, pte);
588 if (--nr == 0)
589 break;
590 ptep++;
591 address += PAGE_SIZE;
592 }
593}
594#define update_mmu_cache(vma, address, ptep) \
595 update_mmu_cache_range(NULL, vma, address, ptep, 1)
596
597#define __HAVE_ARCH_UPDATE_MMU_TLB
598#define update_mmu_tlb update_mmu_cache
599
600static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
601 unsigned long address, pmd_t *pmdp)
602{
603 pte_t pte = *(pte_t *)pmdp;
604
605 __update_tlb(vma, address, pte);
606}
607
608/*
609 * Allow physical addresses to be fixed up to help 36-bit peripherals.
610 */
611#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
612phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size);
613int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
614 unsigned long pfn, unsigned long size, pgprot_t prot);
615#define io_remap_pfn_range io_remap_pfn_range
616#else
617#define fixup_bigphys_addr(addr, size) (addr)
618#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
619
620#ifdef CONFIG_TRANSPARENT_HUGEPAGE
621
622/* We don't have hardware dirty/accessed bits, generic_pmdp_establish is fine.*/
623#define pmdp_establish generic_pmdp_establish
624
625#define has_transparent_hugepage has_transparent_hugepage
626extern int has_transparent_hugepage(void);
627
628static inline int pmd_trans_huge(pmd_t pmd)
629{
630 return !!(pmd_val(pmd) & _PAGE_HUGE);
631}
632
633static inline pmd_t pmd_mkhuge(pmd_t pmd)
634{
635 pmd_val(pmd) |= _PAGE_HUGE;
636
637 return pmd;
638}
639
640extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
641 pmd_t *pmdp, pmd_t pmd);
642
643static inline pmd_t pmd_wrprotect(pmd_t pmd)
644{
645 pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
646 return pmd;
647}
648
649static inline pmd_t pmd_mkwrite_novma(pmd_t pmd)
650{
651 pmd_val(pmd) |= _PAGE_WRITE;
652 if (pmd_val(pmd) & _PAGE_MODIFIED)
653 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
654
655 return pmd;
656}
657
658#define pmd_dirty pmd_dirty
659static inline int pmd_dirty(pmd_t pmd)
660{
661 return !!(pmd_val(pmd) & _PAGE_MODIFIED);
662}
663
664static inline pmd_t pmd_mkclean(pmd_t pmd)
665{
666 pmd_val(pmd) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
667 return pmd;
668}
669
670static inline pmd_t pmd_mkdirty(pmd_t pmd)
671{
672 pmd_val(pmd) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
673 if (pmd_val(pmd) & _PAGE_WRITE)
674 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
675
676 return pmd;
677}
678
679#define pmd_young pmd_young
680static inline int pmd_young(pmd_t pmd)
681{
682 return !!(pmd_val(pmd) & _PAGE_ACCESSED);
683}
684
685static inline pmd_t pmd_mkold(pmd_t pmd)
686{
687 pmd_val(pmd) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
688
689 return pmd;
690}
691
692static inline pmd_t pmd_mkyoung(pmd_t pmd)
693{
694 pmd_val(pmd) |= _PAGE_ACCESSED;
695
696 if (!(pmd_val(pmd) & _PAGE_NO_READ))
697 pmd_val(pmd) |= _PAGE_SILENT_READ;
698
699 return pmd;
700}
701
702#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
703static inline int pmd_soft_dirty(pmd_t pmd)
704{
705 return !!(pmd_val(pmd) & _PAGE_SOFT_DIRTY);
706}
707
708static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
709{
710 pmd_val(pmd) |= _PAGE_SOFT_DIRTY;
711 return pmd;
712}
713
714static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
715{
716 pmd_val(pmd) &= ~(_PAGE_SOFT_DIRTY);
717 return pmd;
718}
719
720#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
721
722/* Extern to avoid header file madness */
723extern pmd_t mk_pmd(struct page *page, pgprot_t prot);
724
725static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
726{
727 pmd_val(pmd) = (pmd_val(pmd) & (_PAGE_CHG_MASK | _PAGE_HUGE)) |
728 (pgprot_val(newprot) & ~_PAGE_CHG_MASK);
729 return pmd;
730}
731
732static inline pmd_t pmd_mkinvalid(pmd_t pmd)
733{
734 pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY);
735
736 return pmd;
737}
738
739/*
740 * The generic version pmdp_huge_get_and_clear uses a version of pmd_clear() with a
741 * different prototype.
742 */
743#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
744static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
745 unsigned long address, pmd_t *pmdp)
746{
747 pmd_t old = *pmdp;
748
749 pmd_clear(pmdp);
750
751 return old;
752}
753
754#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
755
756#ifdef _PAGE_HUGE
757#define pmd_leaf(pmd) ((pmd_val(pmd) & _PAGE_HUGE) != 0)
758#define pud_leaf(pud) ((pud_val(pud) & _PAGE_HUGE) != 0)
759#endif
760
761#define gup_fast_permitted(start, end) (!cpu_has_dc_aliases)
762
763/*
764 * We provide our own get_unmapped area to cope with the virtual aliasing
765 * constraints placed on us by the cache architecture.
766 */
767#define HAVE_ARCH_UNMAPPED_AREA
768#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
769
770#endif /* _ASM_PGTABLE_H */