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1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21/* Code sharing between pci-quirks and xhci hcd */
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25/* max buffer size for trace and debug messages */
26#define XHCI_MSG_MAX 500
27
28/* xHCI PCI Configuration Registers */
29#define XHCI_SBRN_OFFSET (0x60)
30
31/* Max number of USB devices for any host controller - limit in section 6.1 */
32#define MAX_HC_SLOTS 256
33/* Section 5.3.3 - MaxPorts */
34#define MAX_HC_PORTS 127
35
36/*
37 * xHCI register interface.
38 * This corresponds to the eXtensible Host Controller Interface (xHCI)
39 * Revision 0.95 specification
40 */
41
42/**
43 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
44 * @hc_capbase: length of the capabilities register and HC version number
45 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
46 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
47 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
48 * @hcc_params: HCCPARAMS - Capability Parameters
49 * @db_off: DBOFF - Doorbell array offset
50 * @run_regs_off: RTSOFF - Runtime register space offset
51 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
52 */
53struct xhci_cap_regs {
54 __le32 hc_capbase;
55 __le32 hcs_params1;
56 __le32 hcs_params2;
57 __le32 hcs_params3;
58 __le32 hcc_params;
59 __le32 db_off;
60 __le32 run_regs_off;
61 __le32 hcc_params2; /* xhci 1.1 */
62 /* Reserved up to (CAPLENGTH - 0x1C) */
63};
64
65/* hc_capbase bitmasks */
66/* bits 7:0 - how long is the Capabilities register */
67#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
68/* bits 31:16 */
69#define HC_VERSION(p) (((p) >> 16) & 0xffff)
70
71/* HCSPARAMS1 - hcs_params1 - bitmasks */
72/* bits 0:7, Max Device Slots */
73#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
74#define HCS_SLOTS_MASK 0xff
75/* bits 8:18, Max Interrupters */
76#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
77/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
78#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
79
80/* HCSPARAMS2 - hcs_params2 - bitmasks */
81/* bits 0:3, frames or uframes that SW needs to queue transactions
82 * ahead of the HW to meet periodic deadlines */
83#define HCS_IST(p) (((p) >> 0) & 0xf)
84/* bits 4:7, max number of Event Ring segments */
85#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
86/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
87/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
88/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
89#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
90
91/* HCSPARAMS3 - hcs_params3 - bitmasks */
92/* bits 0:7, Max U1 to U0 latency for the roothub ports */
93#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
94/* bits 16:31, Max U2 to U0 latency for the roothub ports */
95#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
96
97/* HCCPARAMS - hcc_params - bitmasks */
98/* true: HC can use 64-bit address pointers */
99#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
100/* true: HC can do bandwidth negotiation */
101#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
102/* true: HC uses 64-byte Device Context structures
103 * FIXME 64-byte context structures aren't supported yet.
104 */
105#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
106/* true: HC has port power switches */
107#define HCC_PPC(p) ((p) & (1 << 3))
108/* true: HC has port indicators */
109#define HCS_INDICATOR(p) ((p) & (1 << 4))
110/* true: HC has Light HC Reset Capability */
111#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
112/* true: HC supports latency tolerance messaging */
113#define HCC_LTC(p) ((p) & (1 << 6))
114/* true: no secondary Stream ID Support */
115#define HCC_NSS(p) ((p) & (1 << 7))
116/* true: HC supports Stopped - Short Packet */
117#define HCC_SPC(p) ((p) & (1 << 9))
118/* true: HC has Contiguous Frame ID Capability */
119#define HCC_CFC(p) ((p) & (1 << 11))
120/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122/* Extended Capabilities pointer from PCI base - section 5.3.6 */
123#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
126
127/* db_off bitmask - bits 0:1 reserved */
128#define DBOFF_MASK (~0x3)
129
130/* run_regs_off bitmask - bits 0:4 reserved */
131#define RTSOFF_MASK (~0x1f)
132
133/* HCCPARAMS2 - hcc_params2 - bitmasks */
134/* true: HC supports U3 entry Capability */
135#define HCC2_U3C(p) ((p) & (1 << 0))
136/* true: HC supports Configure endpoint command Max exit latency too large */
137#define HCC2_CMC(p) ((p) & (1 << 1))
138/* true: HC supports Force Save context Capability */
139#define HCC2_FSC(p) ((p) & (1 << 2))
140/* true: HC supports Compliance Transition Capability */
141#define HCC2_CTC(p) ((p) & (1 << 3))
142/* true: HC support Large ESIT payload Capability > 48k */
143#define HCC2_LEC(p) ((p) & (1 << 4))
144/* true: HC support Configuration Information Capability */
145#define HCC2_CIC(p) ((p) & (1 << 5))
146/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
147#define HCC2_ETC(p) ((p) & (1 << 6))
148
149/* Number of registers per port */
150#define NUM_PORT_REGS 4
151
152#define PORTSC 0
153#define PORTPMSC 1
154#define PORTLI 2
155#define PORTHLPMC 3
156
157/**
158 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
159 * @command: USBCMD - xHC command register
160 * @status: USBSTS - xHC status register
161 * @page_size: This indicates the page size that the host controller
162 * supports. If bit n is set, the HC supports a page size
163 * of 2^(n+12), up to a 128MB page size.
164 * 4K is the minimum page size.
165 * @cmd_ring: CRP - 64-bit Command Ring Pointer
166 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
167 * @config_reg: CONFIG - Configure Register
168 * @port_status_base: PORTSCn - base address for Port Status and Control
169 * Each port has a Port Status and Control register,
170 * followed by a Port Power Management Status and Control
171 * register, a Port Link Info register, and a reserved
172 * register.
173 * @port_power_base: PORTPMSCn - base address for
174 * Port Power Management Status and Control
175 * @port_link_base: PORTLIn - base address for Port Link Info (current
176 * Link PM state and control) for USB 2.1 and USB 3.0
177 * devices.
178 */
179struct xhci_op_regs {
180 __le32 command;
181 __le32 status;
182 __le32 page_size;
183 __le32 reserved1;
184 __le32 reserved2;
185 __le32 dev_notification;
186 __le64 cmd_ring;
187 /* rsvd: offset 0x20-2F */
188 __le32 reserved3[4];
189 __le64 dcbaa_ptr;
190 __le32 config_reg;
191 /* rsvd: offset 0x3C-3FF */
192 __le32 reserved4[241];
193 /* port 1 registers, which serve as a base address for other ports */
194 __le32 port_status_base;
195 __le32 port_power_base;
196 __le32 port_link_base;
197 __le32 reserved5;
198 /* registers for ports 2-255 */
199 __le32 reserved6[NUM_PORT_REGS*254];
200};
201
202/* USBCMD - USB command - command bitmasks */
203/* start/stop HC execution - do not write unless HC is halted*/
204#define CMD_RUN XHCI_CMD_RUN
205/* Reset HC - resets internal HC state machine and all registers (except
206 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
207 * The xHCI driver must reinitialize the xHC after setting this bit.
208 */
209#define CMD_RESET (1 << 1)
210/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
211#define CMD_EIE XHCI_CMD_EIE
212/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
213#define CMD_HSEIE XHCI_CMD_HSEIE
214/* bits 4:6 are reserved (and should be preserved on writes). */
215/* light reset (port status stays unchanged) - reset completed when this is 0 */
216#define CMD_LRESET (1 << 7)
217/* host controller save/restore state. */
218#define CMD_CSS (1 << 8)
219#define CMD_CRS (1 << 9)
220/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
221#define CMD_EWE XHCI_CMD_EWE
222/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
223 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
224 * '0' means the xHC can power it off if all ports are in the disconnect,
225 * disabled, or powered-off state.
226 */
227#define CMD_PM_INDEX (1 << 11)
228/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
229#define CMD_ETE (1 << 14)
230/* bits 15:31 are reserved (and should be preserved on writes). */
231
232#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
233#define XHCI_RESET_SHORT_USEC (250 * 1000)
234
235/* IMAN - Interrupt Management Register */
236#define IMAN_IE (1 << 1)
237#define IMAN_IP (1 << 0)
238
239/* USBSTS - USB status - status bitmasks */
240/* HC not running - set to 1 when run/stop bit is cleared. */
241#define STS_HALT XHCI_STS_HALT
242/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
243#define STS_FATAL (1 << 2)
244/* event interrupt - clear this prior to clearing any IP flags in IR set*/
245#define STS_EINT (1 << 3)
246/* port change detect */
247#define STS_PORT (1 << 4)
248/* bits 5:7 reserved and zeroed */
249/* save state status - '1' means xHC is saving state */
250#define STS_SAVE (1 << 8)
251/* restore state status - '1' means xHC is restoring state */
252#define STS_RESTORE (1 << 9)
253/* true: save or restore error */
254#define STS_SRE (1 << 10)
255/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
256#define STS_CNR XHCI_STS_CNR
257/* true: internal Host Controller Error - SW needs to reset and reinitialize */
258#define STS_HCE (1 << 12)
259/* bits 13:31 reserved and should be preserved */
260
261/*
262 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
263 * Generate a device notification event when the HC sees a transaction with a
264 * notification type that matches a bit set in this bit field.
265 */
266#define DEV_NOTE_MASK (0xffff)
267#define ENABLE_DEV_NOTE(x) (1 << (x))
268/* Most of the device notification types should only be used for debug.
269 * SW does need to pay attention to function wake notifications.
270 */
271#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
272
273/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
274/* bit 0 is the command ring cycle state */
275/* stop ring operation after completion of the currently executing command */
276#define CMD_RING_PAUSE (1 << 1)
277/* stop ring immediately - abort the currently executing command */
278#define CMD_RING_ABORT (1 << 2)
279/* true: command ring is running */
280#define CMD_RING_RUNNING (1 << 3)
281/* bits 4:5 reserved and should be preserved */
282/* Command Ring pointer - bit mask for the lower 32 bits. */
283#define CMD_RING_RSVD_BITS (0x3f)
284
285/* CONFIG - Configure Register - config_reg bitmasks */
286/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
287#define MAX_DEVS(p) ((p) & 0xff)
288/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
289#define CONFIG_U3E (1 << 8)
290/* bit 9: Configuration Information Enable, xhci 1.1 */
291#define CONFIG_CIE (1 << 9)
292/* bits 10:31 - reserved and should be preserved */
293
294/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
295/* true: device connected */
296#define PORT_CONNECT (1 << 0)
297/* true: port enabled */
298#define PORT_PE (1 << 1)
299/* bit 2 reserved and zeroed */
300/* true: port has an over-current condition */
301#define PORT_OC (1 << 3)
302/* true: port reset signaling asserted */
303#define PORT_RESET (1 << 4)
304/* Port Link State - bits 5:8
305 * A read gives the current link PM state of the port,
306 * a write with Link State Write Strobe set sets the link state.
307 */
308#define PORT_PLS_MASK (0xf << 5)
309#define XDEV_U0 (0x0 << 5)
310#define XDEV_U1 (0x1 << 5)
311#define XDEV_U2 (0x2 << 5)
312#define XDEV_U3 (0x3 << 5)
313#define XDEV_DISABLED (0x4 << 5)
314#define XDEV_RXDETECT (0x5 << 5)
315#define XDEV_INACTIVE (0x6 << 5)
316#define XDEV_POLLING (0x7 << 5)
317#define XDEV_RECOVERY (0x8 << 5)
318#define XDEV_HOT_RESET (0x9 << 5)
319#define XDEV_COMP_MODE (0xa << 5)
320#define XDEV_TEST_MODE (0xb << 5)
321#define XDEV_RESUME (0xf << 5)
322
323/* true: port has power (see HCC_PPC) */
324#define PORT_POWER (1 << 9)
325/* bits 10:13 indicate device speed:
326 * 0 - undefined speed - port hasn't be initialized by a reset yet
327 * 1 - full speed
328 * 2 - low speed
329 * 3 - high speed
330 * 4 - super speed
331 * 5-15 reserved
332 */
333#define DEV_SPEED_MASK (0xf << 10)
334#define XDEV_FS (0x1 << 10)
335#define XDEV_LS (0x2 << 10)
336#define XDEV_HS (0x3 << 10)
337#define XDEV_SS (0x4 << 10)
338#define XDEV_SSP (0x5 << 10)
339#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
340#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
341#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
342#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
343#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
344#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
345#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
346#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
347
348/* Bits 20:23 in the Slot Context are the speed for the device */
349#define SLOT_SPEED_FS (XDEV_FS << 10)
350#define SLOT_SPEED_LS (XDEV_LS << 10)
351#define SLOT_SPEED_HS (XDEV_HS << 10)
352#define SLOT_SPEED_SS (XDEV_SS << 10)
353#define SLOT_SPEED_SSP (XDEV_SSP << 10)
354/* Port Indicator Control */
355#define PORT_LED_OFF (0 << 14)
356#define PORT_LED_AMBER (1 << 14)
357#define PORT_LED_GREEN (2 << 14)
358#define PORT_LED_MASK (3 << 14)
359/* Port Link State Write Strobe - set this when changing link state */
360#define PORT_LINK_STROBE (1 << 16)
361/* true: connect status change */
362#define PORT_CSC (1 << 17)
363/* true: port enable change */
364#define PORT_PEC (1 << 18)
365/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
366 * into an enabled state, and the device into the default state. A "warm" reset
367 * also resets the link, forcing the device through the link training sequence.
368 * SW can also look at the Port Reset register to see when warm reset is done.
369 */
370#define PORT_WRC (1 << 19)
371/* true: over-current change */
372#define PORT_OCC (1 << 20)
373/* true: reset change - 1 to 0 transition of PORT_RESET */
374#define PORT_RC (1 << 21)
375/* port link status change - set on some port link state transitions:
376 * Transition Reason
377 * ------------------------------------------------------------------------------
378 * - U3 to Resume Wakeup signaling from a device
379 * - Resume to Recovery to U0 USB 3.0 device resume
380 * - Resume to U0 USB 2.0 device resume
381 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
382 * - U3 to U0 Software resume of USB 2.0 device complete
383 * - U2 to U0 L1 resume of USB 2.1 device complete
384 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
385 * - U0 to disabled L1 entry error with USB 2.1 device
386 * - Any state to inactive Error on USB 3.0 port
387 */
388#define PORT_PLC (1 << 22)
389/* port configure error change - port failed to configure its link partner */
390#define PORT_CEC (1 << 23)
391#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
392 PORT_RC | PORT_PLC | PORT_CEC)
393
394
395/* Cold Attach Status - xHC can set this bit to report device attached during
396 * Sx state. Warm port reset should be perfomed to clear this bit and move port
397 * to connected state.
398 */
399#define PORT_CAS (1 << 24)
400/* wake on connect (enable) */
401#define PORT_WKCONN_E (1 << 25)
402/* wake on disconnect (enable) */
403#define PORT_WKDISC_E (1 << 26)
404/* wake on over-current (enable) */
405#define PORT_WKOC_E (1 << 27)
406/* bits 28:29 reserved */
407/* true: device is non-removable - for USB 3.0 roothub emulation */
408#define PORT_DEV_REMOVE (1 << 30)
409/* Initiate a warm port reset - complete when PORT_WRC is '1' */
410#define PORT_WR (1 << 31)
411
412/* We mark duplicate entries with -1 */
413#define DUPLICATE_ENTRY ((u8)(-1))
414
415/* Port Power Management Status and Control - port_power_base bitmasks */
416/* Inactivity timer value for transitions into U1, in microseconds.
417 * Timeout can be up to 127us. 0xFF means an infinite timeout.
418 */
419#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
420#define PORT_U1_TIMEOUT_MASK 0xff
421/* Inactivity timer value for transitions into U2 */
422#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
423#define PORT_U2_TIMEOUT_MASK (0xff << 8)
424/* Bits 24:31 for port testing */
425
426/* USB2 Protocol PORTSPMSC */
427#define PORT_L1S_MASK 7
428#define PORT_L1S_SUCCESS 1
429#define PORT_RWE (1 << 3)
430#define PORT_HIRD(p) (((p) & 0xf) << 4)
431#define PORT_HIRD_MASK (0xf << 4)
432#define PORT_L1DS_MASK (0xff << 8)
433#define PORT_L1DS(p) (((p) & 0xff) << 8)
434#define PORT_HLE (1 << 16)
435#define PORT_TEST_MODE_SHIFT 28
436
437/* USB3 Protocol PORTLI Port Link Information */
438#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
439#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
440
441/* USB2 Protocol PORTHLPMC */
442#define PORT_HIRDM(p)((p) & 3)
443#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
444#define PORT_BESLD(p)(((p) & 0xf) << 10)
445
446/* use 512 microseconds as USB2 LPM L1 default timeout. */
447#define XHCI_L1_TIMEOUT 512
448
449/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
451 * by other operating systems.
452 *
453 * XHCI 1.0 errata 8/14/12 Table 13 notes:
454 * "Software should choose xHC BESL/BESLD field values that do not violate a
455 * device's resume latency requirements,
456 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
457 * or not program values < '4' if BLC = '0' and a BESL device is attached.
458 */
459#define XHCI_DEFAULT_BESL 4
460
461/*
462 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
463 * to complete link training. usually link trainig completes much faster
464 * so check status 10 times with 36ms sleep in places we need to wait for
465 * polling to complete.
466 */
467#define XHCI_PORT_POLLING_LFPS_TIME 36
468
469/**
470 * struct xhci_intr_reg - Interrupt Register Set
471 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
472 * interrupts and check for pending interrupts.
473 * @irq_control: IMOD - Interrupt Moderation Register.
474 * Used to throttle interrupts.
475 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
476 * @erst_base: ERST base address.
477 * @erst_dequeue: Event ring dequeue pointer.
478 *
479 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
480 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
481 * multiple segments of the same size. The HC places events on the ring and
482 * "updates the Cycle bit in the TRBs to indicate to software the current
483 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
484 * updates the dequeue pointer.
485 */
486struct xhci_intr_reg {
487 __le32 irq_pending;
488 __le32 irq_control;
489 __le32 erst_size;
490 __le32 rsvd;
491 __le64 erst_base;
492 __le64 erst_dequeue;
493};
494
495/* irq_pending bitmasks */
496#define ER_IRQ_PENDING(p) ((p) & 0x1)
497/* bits 2:31 need to be preserved */
498/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
499#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
500#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
501#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
502
503/* irq_control bitmasks */
504/* Minimum interval between interrupts (in 250ns intervals). The interval
505 * between interrupts will be longer if there are no events on the event ring.
506 * Default is 4000 (1 ms).
507 */
508#define ER_IRQ_INTERVAL_MASK (0xffff)
509/* Counter used to count down the time to the next interrupt - HW use only */
510#define ER_IRQ_COUNTER_MASK (0xffff << 16)
511
512/* erst_size bitmasks */
513/* Preserve bits 16:31 of erst_size */
514#define ERST_SIZE_MASK (0xffff << 16)
515
516/* erst_dequeue bitmasks */
517/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
518 * where the current dequeue pointer lies. This is an optional HW hint.
519 */
520#define ERST_DESI_MASK (0x7)
521/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
522 * a work queue (or delayed service routine)?
523 */
524#define ERST_EHB (1 << 3)
525#define ERST_PTR_MASK (0xf)
526
527/**
528 * struct xhci_run_regs
529 * @microframe_index:
530 * MFINDEX - current microframe number
531 *
532 * Section 5.5 Host Controller Runtime Registers:
533 * "Software should read and write these registers using only Dword (32 bit)
534 * or larger accesses"
535 */
536struct xhci_run_regs {
537 __le32 microframe_index;
538 __le32 rsvd[7];
539 struct xhci_intr_reg ir_set[128];
540};
541
542/**
543 * struct doorbell_array
544 *
545 * Bits 0 - 7: Endpoint target
546 * Bits 8 - 15: RsvdZ
547 * Bits 16 - 31: Stream ID
548 *
549 * Section 5.6
550 */
551struct xhci_doorbell_array {
552 __le32 doorbell[256];
553};
554
555#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
556#define DB_VALUE_HOST 0x00000000
557
558/**
559 * struct xhci_protocol_caps
560 * @revision: major revision, minor revision, capability ID,
561 * and next capability pointer.
562 * @name_string: Four ASCII characters to say which spec this xHC
563 * follows, typically "USB ".
564 * @port_info: Port offset, count, and protocol-defined information.
565 */
566struct xhci_protocol_caps {
567 u32 revision;
568 u32 name_string;
569 u32 port_info;
570};
571
572#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
573#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
574#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
575#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
576#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
577
578#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
579#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
580#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
581#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
582#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
583#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
584
585#define PLT_MASK (0x03 << 6)
586#define PLT_SYM (0x00 << 6)
587#define PLT_ASYM_RX (0x02 << 6)
588#define PLT_ASYM_TX (0x03 << 6)
589
590/**
591 * struct xhci_container_ctx
592 * @type: Type of context. Used to calculated offsets to contained contexts.
593 * @size: Size of the context data
594 * @bytes: The raw context data given to HW
595 * @dma: dma address of the bytes
596 *
597 * Represents either a Device or Input context. Holds a pointer to the raw
598 * memory used for the context (bytes) and dma address of it (dma).
599 */
600struct xhci_container_ctx {
601 unsigned type;
602#define XHCI_CTX_TYPE_DEVICE 0x1
603#define XHCI_CTX_TYPE_INPUT 0x2
604
605 int size;
606
607 u8 *bytes;
608 dma_addr_t dma;
609};
610
611/**
612 * struct xhci_slot_ctx
613 * @dev_info: Route string, device speed, hub info, and last valid endpoint
614 * @dev_info2: Max exit latency for device number, root hub port number
615 * @tt_info: tt_info is used to construct split transaction tokens
616 * @dev_state: slot state and device address
617 *
618 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
619 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
620 * reserved at the end of the slot context for HC internal use.
621 */
622struct xhci_slot_ctx {
623 __le32 dev_info;
624 __le32 dev_info2;
625 __le32 tt_info;
626 __le32 dev_state;
627 /* offset 0x10 to 0x1f reserved for HC internal use */
628 __le32 reserved[4];
629};
630
631/* dev_info bitmasks */
632/* Route String - 0:19 */
633#define ROUTE_STRING_MASK (0xfffff)
634/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
635#define DEV_SPEED (0xf << 20)
636#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
637/* bit 24 reserved */
638/* Is this LS/FS device connected through a HS hub? - bit 25 */
639#define DEV_MTT (0x1 << 25)
640/* Set if the device is a hub - bit 26 */
641#define DEV_HUB (0x1 << 26)
642/* Index of the last valid endpoint context in this device context - 27:31 */
643#define LAST_CTX_MASK (0x1f << 27)
644#define LAST_CTX(p) ((p) << 27)
645#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
646#define SLOT_FLAG (1 << 0)
647#define EP0_FLAG (1 << 1)
648
649/* dev_info2 bitmasks */
650/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
651#define MAX_EXIT (0xffff)
652/* Root hub port number that is needed to access the USB device */
653#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
654#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
655/* Maximum number of ports under a hub device */
656#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
657#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
658
659/* tt_info bitmasks */
660/*
661 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
662 * The Slot ID of the hub that isolates the high speed signaling from
663 * this low or full-speed device. '0' if attached to root hub port.
664 */
665#define TT_SLOT (0xff)
666/*
667 * The number of the downstream facing port of the high-speed hub
668 * '0' if the device is not low or full speed.
669 */
670#define TT_PORT (0xff << 8)
671#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
672#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
673
674/* dev_state bitmasks */
675/* USB device address - assigned by the HC */
676#define DEV_ADDR_MASK (0xff)
677/* bits 8:26 reserved */
678/* Slot state */
679#define SLOT_STATE (0x1f << 27)
680#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
681
682#define SLOT_STATE_DISABLED 0
683#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
684#define SLOT_STATE_DEFAULT 1
685#define SLOT_STATE_ADDRESSED 2
686#define SLOT_STATE_CONFIGURED 3
687
688/**
689 * struct xhci_ep_ctx
690 * @ep_info: endpoint state, streams, mult, and interval information.
691 * @ep_info2: information on endpoint type, max packet size, max burst size,
692 * error count, and whether the HC will force an event for all
693 * transactions.
694 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
695 * defines one stream, this points to the endpoint transfer ring.
696 * Otherwise, it points to a stream context array, which has a
697 * ring pointer for each flow.
698 * @tx_info:
699 * Average TRB lengths for the endpoint ring and
700 * max payload within an Endpoint Service Interval Time (ESIT).
701 *
702 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
703 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
704 * reserved at the end of the endpoint context for HC internal use.
705 */
706struct xhci_ep_ctx {
707 __le32 ep_info;
708 __le32 ep_info2;
709 __le64 deq;
710 __le32 tx_info;
711 /* offset 0x14 - 0x1f reserved for HC internal use */
712 __le32 reserved[3];
713};
714
715/* ep_info bitmasks */
716/*
717 * Endpoint State - bits 0:2
718 * 0 - disabled
719 * 1 - running
720 * 2 - halted due to halt condition - ok to manipulate endpoint ring
721 * 3 - stopped
722 * 4 - TRB error
723 * 5-7 - reserved
724 */
725#define EP_STATE_MASK (0x7)
726#define EP_STATE_DISABLED 0
727#define EP_STATE_RUNNING 1
728#define EP_STATE_HALTED 2
729#define EP_STATE_STOPPED 3
730#define EP_STATE_ERROR 4
731#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
732
733/* Mult - Max number of burtst within an interval, in EP companion desc. */
734#define EP_MULT(p) (((p) & 0x3) << 8)
735#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
736/* bits 10:14 are Max Primary Streams */
737/* bit 15 is Linear Stream Array */
738/* Interval - period between requests to an endpoint - 125u increments. */
739#define EP_INTERVAL(p) (((p) & 0xff) << 16)
740#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
741#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
742#define EP_MAXPSTREAMS_MASK (0x1f << 10)
743#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
744#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
745/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
746#define EP_HAS_LSA (1 << 15)
747/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
748#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
749
750/* ep_info2 bitmasks */
751/*
752 * Force Event - generate transfer events for all TRBs for this endpoint
753 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
754 */
755#define FORCE_EVENT (0x1)
756#define ERROR_COUNT(p) (((p) & 0x3) << 1)
757#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
758#define EP_TYPE(p) ((p) << 3)
759#define ISOC_OUT_EP 1
760#define BULK_OUT_EP 2
761#define INT_OUT_EP 3
762#define CTRL_EP 4
763#define ISOC_IN_EP 5
764#define BULK_IN_EP 6
765#define INT_IN_EP 7
766/* bit 6 reserved */
767/* bit 7 is Host Initiate Disable - for disabling stream selection */
768#define MAX_BURST(p) (((p)&0xff) << 8)
769#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
770#define MAX_PACKET(p) (((p)&0xffff) << 16)
771#define MAX_PACKET_MASK (0xffff << 16)
772#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
773
774/* tx_info bitmasks */
775#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
776#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
777#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
778#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
779
780/* deq bitmasks */
781#define EP_CTX_CYCLE_MASK (1 << 0)
782#define SCTX_DEQ_MASK (~0xfL)
783
784
785/**
786 * struct xhci_input_control_context
787 * Input control context; see section 6.2.5.
788 *
789 * @drop_context: set the bit of the endpoint context you want to disable
790 * @add_context: set the bit of the endpoint context you want to enable
791 */
792struct xhci_input_control_ctx {
793 __le32 drop_flags;
794 __le32 add_flags;
795 __le32 rsvd2[6];
796};
797
798#define EP_IS_ADDED(ctrl_ctx, i) \
799 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
800#define EP_IS_DROPPED(ctrl_ctx, i) \
801 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
802
803/* Represents everything that is needed to issue a command on the command ring.
804 * It's useful to pre-allocate these for commands that cannot fail due to
805 * out-of-memory errors, like freeing streams.
806 */
807struct xhci_command {
808 /* Input context for changing device state */
809 struct xhci_container_ctx *in_ctx;
810 u32 status;
811 int slot_id;
812 /* If completion is null, no one is waiting on this command
813 * and the structure can be freed after the command completes.
814 */
815 struct completion *completion;
816 union xhci_trb *command_trb;
817 struct list_head cmd_list;
818};
819
820/* drop context bitmasks */
821#define DROP_EP(x) (0x1 << x)
822/* add context bitmasks */
823#define ADD_EP(x) (0x1 << x)
824
825struct xhci_stream_ctx {
826 /* 64-bit stream ring address, cycle state, and stream type */
827 __le64 stream_ring;
828 /* offset 0x14 - 0x1f reserved for HC internal use */
829 __le32 reserved[2];
830};
831
832/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
833#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
834/* Secondary stream array type, dequeue pointer is to a transfer ring */
835#define SCT_SEC_TR 0
836/* Primary stream array type, dequeue pointer is to a transfer ring */
837#define SCT_PRI_TR 1
838/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
839#define SCT_SSA_8 2
840#define SCT_SSA_16 3
841#define SCT_SSA_32 4
842#define SCT_SSA_64 5
843#define SCT_SSA_128 6
844#define SCT_SSA_256 7
845
846/* Assume no secondary streams for now */
847struct xhci_stream_info {
848 struct xhci_ring **stream_rings;
849 /* Number of streams, including stream 0 (which drivers can't use) */
850 unsigned int num_streams;
851 /* The stream context array may be bigger than
852 * the number of streams the driver asked for
853 */
854 struct xhci_stream_ctx *stream_ctx_array;
855 unsigned int num_stream_ctxs;
856 dma_addr_t ctx_array_dma;
857 /* For mapping physical TRB addresses to segments in stream rings */
858 struct radix_tree_root trb_address_map;
859 struct xhci_command *free_streams_command;
860};
861
862#define SMALL_STREAM_ARRAY_SIZE 256
863#define MEDIUM_STREAM_ARRAY_SIZE 1024
864
865/* Some Intel xHCI host controllers need software to keep track of the bus
866 * bandwidth. Keep track of endpoint info here. Each root port is allocated
867 * the full bus bandwidth. We must also treat TTs (including each port under a
868 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
869 * (DMI) also limits the total bandwidth (across all domains) that can be used.
870 */
871struct xhci_bw_info {
872 /* ep_interval is zero-based */
873 unsigned int ep_interval;
874 /* mult and num_packets are one-based */
875 unsigned int mult;
876 unsigned int num_packets;
877 unsigned int max_packet_size;
878 unsigned int max_esit_payload;
879 unsigned int type;
880};
881
882/* "Block" sizes in bytes the hardware uses for different device speeds.
883 * The logic in this part of the hardware limits the number of bits the hardware
884 * can use, so must represent bandwidth in a less precise manner to mimic what
885 * the scheduler hardware computes.
886 */
887#define FS_BLOCK 1
888#define HS_BLOCK 4
889#define SS_BLOCK 16
890#define DMI_BLOCK 32
891
892/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
893 * with each byte transferred. SuperSpeed devices have an initial overhead to
894 * set up bursts. These are in blocks, see above. LS overhead has already been
895 * translated into FS blocks.
896 */
897#define DMI_OVERHEAD 8
898#define DMI_OVERHEAD_BURST 4
899#define SS_OVERHEAD 8
900#define SS_OVERHEAD_BURST 32
901#define HS_OVERHEAD 26
902#define FS_OVERHEAD 20
903#define LS_OVERHEAD 128
904/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
905 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
906 * of overhead associated with split transfers crossing microframe boundaries.
907 * 31 blocks is pure protocol overhead.
908 */
909#define TT_HS_OVERHEAD (31 + 94)
910#define TT_DMI_OVERHEAD (25 + 12)
911
912/* Bandwidth limits in blocks */
913#define FS_BW_LIMIT 1285
914#define TT_BW_LIMIT 1320
915#define HS_BW_LIMIT 1607
916#define SS_BW_LIMIT_IN 3906
917#define DMI_BW_LIMIT_IN 3906
918#define SS_BW_LIMIT_OUT 3906
919#define DMI_BW_LIMIT_OUT 3906
920
921/* Percentage of bus bandwidth reserved for non-periodic transfers */
922#define FS_BW_RESERVED 10
923#define HS_BW_RESERVED 20
924#define SS_BW_RESERVED 10
925
926struct xhci_virt_ep {
927 struct xhci_virt_device *vdev; /* parent */
928 unsigned int ep_index;
929 struct xhci_ring *ring;
930 /* Related to endpoints that are configured to use stream IDs only */
931 struct xhci_stream_info *stream_info;
932 /* Temporary storage in case the configure endpoint command fails and we
933 * have to restore the device state to the previous state
934 */
935 struct xhci_ring *new_ring;
936 unsigned int err_count;
937 unsigned int ep_state;
938#define SET_DEQ_PENDING (1 << 0)
939#define EP_HALTED (1 << 1) /* For stall handling */
940#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
941/* Transitioning the endpoint to using streams, don't enqueue URBs */
942#define EP_GETTING_STREAMS (1 << 3)
943#define EP_HAS_STREAMS (1 << 4)
944/* Transitioning the endpoint to not using streams, don't enqueue URBs */
945#define EP_GETTING_NO_STREAMS (1 << 5)
946#define EP_HARD_CLEAR_TOGGLE (1 << 6)
947#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
948/* usb_hub_clear_tt_buffer is in progress */
949#define EP_CLEARING_TT (1 << 8)
950 /* ---- Related to URB cancellation ---- */
951 struct list_head cancelled_td_list;
952 struct xhci_hcd *xhci;
953 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
954 * command. We'll need to update the ring's dequeue segment and dequeue
955 * pointer after the command completes.
956 */
957 struct xhci_segment *queued_deq_seg;
958 union xhci_trb *queued_deq_ptr;
959 /*
960 * Sometimes the xHC can not process isochronous endpoint ring quickly
961 * enough, and it will miss some isoc tds on the ring and generate
962 * a Missed Service Error Event.
963 * Set skip flag when receive a Missed Service Error Event and
964 * process the missed tds on the endpoint ring.
965 */
966 bool skip;
967 /* Bandwidth checking storage */
968 struct xhci_bw_info bw_info;
969 struct list_head bw_endpoint_list;
970 /* Isoch Frame ID checking storage */
971 int next_frame_id;
972 /* Use new Isoch TRB layout needed for extended TBC support */
973 bool use_extended_tbc;
974};
975
976enum xhci_overhead_type {
977 LS_OVERHEAD_TYPE = 0,
978 FS_OVERHEAD_TYPE,
979 HS_OVERHEAD_TYPE,
980};
981
982struct xhci_interval_bw {
983 unsigned int num_packets;
984 /* Sorted by max packet size.
985 * Head of the list is the greatest max packet size.
986 */
987 struct list_head endpoints;
988 /* How many endpoints of each speed are present. */
989 unsigned int overhead[3];
990};
991
992#define XHCI_MAX_INTERVAL 16
993
994struct xhci_interval_bw_table {
995 unsigned int interval0_esit_payload;
996 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
997 /* Includes reserved bandwidth for async endpoints */
998 unsigned int bw_used;
999 unsigned int ss_bw_in;
1000 unsigned int ss_bw_out;
1001};
1002
1003#define EP_CTX_PER_DEV 31
1004
1005struct xhci_virt_device {
1006 int slot_id;
1007 struct usb_device *udev;
1008 /*
1009 * Commands to the hardware are passed an "input context" that
1010 * tells the hardware what to change in its data structures.
1011 * The hardware will return changes in an "output context" that
1012 * software must allocate for the hardware. We need to keep
1013 * track of input and output contexts separately because
1014 * these commands might fail and we don't trust the hardware.
1015 */
1016 struct xhci_container_ctx *out_ctx;
1017 /* Used for addressing devices and configuration changes */
1018 struct xhci_container_ctx *in_ctx;
1019 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1020 u8 fake_port;
1021 u8 real_port;
1022 struct xhci_interval_bw_table *bw_table;
1023 struct xhci_tt_bw_info *tt_info;
1024 /*
1025 * flags for state tracking based on events and issued commands.
1026 * Software can not rely on states from output contexts because of
1027 * latency between events and xHC updating output context values.
1028 * See xhci 1.1 section 4.8.3 for more details
1029 */
1030 unsigned long flags;
1031#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1032
1033 /* The current max exit latency for the enabled USB3 link states. */
1034 u16 current_mel;
1035 /* Used for the debugfs interfaces. */
1036 void *debugfs_private;
1037};
1038
1039/*
1040 * For each roothub, keep track of the bandwidth information for each periodic
1041 * interval.
1042 *
1043 * If a high speed hub is attached to the roothub, each TT associated with that
1044 * hub is a separate bandwidth domain. The interval information for the
1045 * endpoints on the devices under that TT will appear in the TT structure.
1046 */
1047struct xhci_root_port_bw_info {
1048 struct list_head tts;
1049 unsigned int num_active_tts;
1050 struct xhci_interval_bw_table bw_table;
1051};
1052
1053struct xhci_tt_bw_info {
1054 struct list_head tt_list;
1055 int slot_id;
1056 int ttport;
1057 struct xhci_interval_bw_table bw_table;
1058 int active_eps;
1059};
1060
1061
1062/**
1063 * struct xhci_device_context_array
1064 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1065 */
1066struct xhci_device_context_array {
1067 /* 64-bit device addresses; we only write 32-bit addresses */
1068 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1069 /* private xHCD pointers */
1070 dma_addr_t dma;
1071};
1072/* TODO: write function to set the 64-bit device DMA address */
1073/*
1074 * TODO: change this to be dynamically sized at HC mem init time since the HC
1075 * might not be able to handle the maximum number of devices possible.
1076 */
1077
1078
1079struct xhci_transfer_event {
1080 /* 64-bit buffer address, or immediate data */
1081 __le64 buffer;
1082 __le32 transfer_len;
1083 /* This field is interpreted differently based on the type of TRB */
1084 __le32 flags;
1085};
1086
1087/* Transfer event TRB length bit mask */
1088/* bits 0:23 */
1089#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1090
1091/** Transfer Event bit fields **/
1092#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1093
1094/* Completion Code - only applicable for some types of TRBs */
1095#define COMP_CODE_MASK (0xff << 24)
1096#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1097#define COMP_INVALID 0
1098#define COMP_SUCCESS 1
1099#define COMP_DATA_BUFFER_ERROR 2
1100#define COMP_BABBLE_DETECTED_ERROR 3
1101#define COMP_USB_TRANSACTION_ERROR 4
1102#define COMP_TRB_ERROR 5
1103#define COMP_STALL_ERROR 6
1104#define COMP_RESOURCE_ERROR 7
1105#define COMP_BANDWIDTH_ERROR 8
1106#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1107#define COMP_INVALID_STREAM_TYPE_ERROR 10
1108#define COMP_SLOT_NOT_ENABLED_ERROR 11
1109#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1110#define COMP_SHORT_PACKET 13
1111#define COMP_RING_UNDERRUN 14
1112#define COMP_RING_OVERRUN 15
1113#define COMP_VF_EVENT_RING_FULL_ERROR 16
1114#define COMP_PARAMETER_ERROR 17
1115#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1116#define COMP_CONTEXT_STATE_ERROR 19
1117#define COMP_NO_PING_RESPONSE_ERROR 20
1118#define COMP_EVENT_RING_FULL_ERROR 21
1119#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1120#define COMP_MISSED_SERVICE_ERROR 23
1121#define COMP_COMMAND_RING_STOPPED 24
1122#define COMP_COMMAND_ABORTED 25
1123#define COMP_STOPPED 26
1124#define COMP_STOPPED_LENGTH_INVALID 27
1125#define COMP_STOPPED_SHORT_PACKET 28
1126#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1127#define COMP_ISOCH_BUFFER_OVERRUN 31
1128#define COMP_EVENT_LOST_ERROR 32
1129#define COMP_UNDEFINED_ERROR 33
1130#define COMP_INVALID_STREAM_ID_ERROR 34
1131#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1132#define COMP_SPLIT_TRANSACTION_ERROR 36
1133
1134static inline const char *xhci_trb_comp_code_string(u8 status)
1135{
1136 switch (status) {
1137 case COMP_INVALID:
1138 return "Invalid";
1139 case COMP_SUCCESS:
1140 return "Success";
1141 case COMP_DATA_BUFFER_ERROR:
1142 return "Data Buffer Error";
1143 case COMP_BABBLE_DETECTED_ERROR:
1144 return "Babble Detected";
1145 case COMP_USB_TRANSACTION_ERROR:
1146 return "USB Transaction Error";
1147 case COMP_TRB_ERROR:
1148 return "TRB Error";
1149 case COMP_STALL_ERROR:
1150 return "Stall Error";
1151 case COMP_RESOURCE_ERROR:
1152 return "Resource Error";
1153 case COMP_BANDWIDTH_ERROR:
1154 return "Bandwidth Error";
1155 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1156 return "No Slots Available Error";
1157 case COMP_INVALID_STREAM_TYPE_ERROR:
1158 return "Invalid Stream Type Error";
1159 case COMP_SLOT_NOT_ENABLED_ERROR:
1160 return "Slot Not Enabled Error";
1161 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1162 return "Endpoint Not Enabled Error";
1163 case COMP_SHORT_PACKET:
1164 return "Short Packet";
1165 case COMP_RING_UNDERRUN:
1166 return "Ring Underrun";
1167 case COMP_RING_OVERRUN:
1168 return "Ring Overrun";
1169 case COMP_VF_EVENT_RING_FULL_ERROR:
1170 return "VF Event Ring Full Error";
1171 case COMP_PARAMETER_ERROR:
1172 return "Parameter Error";
1173 case COMP_BANDWIDTH_OVERRUN_ERROR:
1174 return "Bandwidth Overrun Error";
1175 case COMP_CONTEXT_STATE_ERROR:
1176 return "Context State Error";
1177 case COMP_NO_PING_RESPONSE_ERROR:
1178 return "No Ping Response Error";
1179 case COMP_EVENT_RING_FULL_ERROR:
1180 return "Event Ring Full Error";
1181 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1182 return "Incompatible Device Error";
1183 case COMP_MISSED_SERVICE_ERROR:
1184 return "Missed Service Error";
1185 case COMP_COMMAND_RING_STOPPED:
1186 return "Command Ring Stopped";
1187 case COMP_COMMAND_ABORTED:
1188 return "Command Aborted";
1189 case COMP_STOPPED:
1190 return "Stopped";
1191 case COMP_STOPPED_LENGTH_INVALID:
1192 return "Stopped - Length Invalid";
1193 case COMP_STOPPED_SHORT_PACKET:
1194 return "Stopped - Short Packet";
1195 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1196 return "Max Exit Latency Too Large Error";
1197 case COMP_ISOCH_BUFFER_OVERRUN:
1198 return "Isoch Buffer Overrun";
1199 case COMP_EVENT_LOST_ERROR:
1200 return "Event Lost Error";
1201 case COMP_UNDEFINED_ERROR:
1202 return "Undefined Error";
1203 case COMP_INVALID_STREAM_ID_ERROR:
1204 return "Invalid Stream ID Error";
1205 case COMP_SECONDARY_BANDWIDTH_ERROR:
1206 return "Secondary Bandwidth Error";
1207 case COMP_SPLIT_TRANSACTION_ERROR:
1208 return "Split Transaction Error";
1209 default:
1210 return "Unknown!!";
1211 }
1212}
1213
1214struct xhci_link_trb {
1215 /* 64-bit segment pointer*/
1216 __le64 segment_ptr;
1217 __le32 intr_target;
1218 __le32 control;
1219};
1220
1221/* control bitfields */
1222#define LINK_TOGGLE (0x1<<1)
1223
1224/* Command completion event TRB */
1225struct xhci_event_cmd {
1226 /* Pointer to command TRB, or the value passed by the event data trb */
1227 __le64 cmd_trb;
1228 __le32 status;
1229 __le32 flags;
1230};
1231
1232/* flags bitmasks */
1233
1234/* Address device - disable SetAddress */
1235#define TRB_BSR (1<<9)
1236
1237/* Configure Endpoint - Deconfigure */
1238#define TRB_DC (1<<9)
1239
1240/* Stop Ring - Transfer State Preserve */
1241#define TRB_TSP (1<<9)
1242
1243enum xhci_ep_reset_type {
1244 EP_HARD_RESET,
1245 EP_SOFT_RESET,
1246};
1247
1248/* Force Event */
1249#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1250#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1251
1252/* Set Latency Tolerance Value */
1253#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1254
1255/* Get Port Bandwidth */
1256#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1257
1258/* Force Header */
1259#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1260#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1261
1262enum xhci_setup_dev {
1263 SETUP_CONTEXT_ONLY,
1264 SETUP_CONTEXT_ADDRESS,
1265};
1266
1267/* bits 16:23 are the virtual function ID */
1268/* bits 24:31 are the slot ID */
1269#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1270#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1271
1272/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1273#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1274#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1275
1276#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1277#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1278#define LAST_EP_INDEX 30
1279
1280/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1281#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1282#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1283#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1284
1285/* Link TRB specific fields */
1286#define TRB_TC (1<<1)
1287
1288/* Port Status Change Event TRB fields */
1289/* Port ID - bits 31:24 */
1290#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1291
1292#define EVENT_DATA (1 << 2)
1293
1294/* Normal TRB fields */
1295/* transfer_len bitmasks - bits 0:16 */
1296#define TRB_LEN(p) ((p) & 0x1ffff)
1297/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1298#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1299#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1300/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1301#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1302/* Interrupter Target - which MSI-X vector to target the completion event at */
1303#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1304#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1305/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1306#define TRB_TBC(p) (((p) & 0x3) << 7)
1307#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1308
1309/* Cycle bit - indicates TRB ownership by HC or HCD */
1310#define TRB_CYCLE (1<<0)
1311/*
1312 * Force next event data TRB to be evaluated before task switch.
1313 * Used to pass OS data back after a TD completes.
1314 */
1315#define TRB_ENT (1<<1)
1316/* Interrupt on short packet */
1317#define TRB_ISP (1<<2)
1318/* Set PCIe no snoop attribute */
1319#define TRB_NO_SNOOP (1<<3)
1320/* Chain multiple TRBs into a TD */
1321#define TRB_CHAIN (1<<4)
1322/* Interrupt on completion */
1323#define TRB_IOC (1<<5)
1324/* The buffer pointer contains immediate data */
1325#define TRB_IDT (1<<6)
1326/* TDs smaller than this might use IDT */
1327#define TRB_IDT_MAX_SIZE 8
1328
1329/* Block Event Interrupt */
1330#define TRB_BEI (1<<9)
1331
1332/* Control transfer TRB specific fields */
1333#define TRB_DIR_IN (1<<16)
1334#define TRB_TX_TYPE(p) ((p) << 16)
1335#define TRB_DATA_OUT 2
1336#define TRB_DATA_IN 3
1337
1338/* Isochronous TRB specific fields */
1339#define TRB_SIA (1<<31)
1340#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1341
1342/* TRB cache size for xHC with TRB cache */
1343#define TRB_CACHE_SIZE_HS 8
1344#define TRB_CACHE_SIZE_SS 16
1345
1346struct xhci_generic_trb {
1347 __le32 field[4];
1348};
1349
1350union xhci_trb {
1351 struct xhci_link_trb link;
1352 struct xhci_transfer_event trans_event;
1353 struct xhci_event_cmd event_cmd;
1354 struct xhci_generic_trb generic;
1355};
1356
1357/* TRB bit mask */
1358#define TRB_TYPE_BITMASK (0xfc00)
1359#define TRB_TYPE(p) ((p) << 10)
1360#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1361/* TRB type IDs */
1362/* bulk, interrupt, isoc scatter/gather, and control data stage */
1363#define TRB_NORMAL 1
1364/* setup stage for control transfers */
1365#define TRB_SETUP 2
1366/* data stage for control transfers */
1367#define TRB_DATA 3
1368/* status stage for control transfers */
1369#define TRB_STATUS 4
1370/* isoc transfers */
1371#define TRB_ISOC 5
1372/* TRB for linking ring segments */
1373#define TRB_LINK 6
1374#define TRB_EVENT_DATA 7
1375/* Transfer Ring No-op (not for the command ring) */
1376#define TRB_TR_NOOP 8
1377/* Command TRBs */
1378/* Enable Slot Command */
1379#define TRB_ENABLE_SLOT 9
1380/* Disable Slot Command */
1381#define TRB_DISABLE_SLOT 10
1382/* Address Device Command */
1383#define TRB_ADDR_DEV 11
1384/* Configure Endpoint Command */
1385#define TRB_CONFIG_EP 12
1386/* Evaluate Context Command */
1387#define TRB_EVAL_CONTEXT 13
1388/* Reset Endpoint Command */
1389#define TRB_RESET_EP 14
1390/* Stop Transfer Ring Command */
1391#define TRB_STOP_RING 15
1392/* Set Transfer Ring Dequeue Pointer Command */
1393#define TRB_SET_DEQ 16
1394/* Reset Device Command */
1395#define TRB_RESET_DEV 17
1396/* Force Event Command (opt) */
1397#define TRB_FORCE_EVENT 18
1398/* Negotiate Bandwidth Command (opt) */
1399#define TRB_NEG_BANDWIDTH 19
1400/* Set Latency Tolerance Value Command (opt) */
1401#define TRB_SET_LT 20
1402/* Get port bandwidth Command */
1403#define TRB_GET_BW 21
1404/* Force Header Command - generate a transaction or link management packet */
1405#define TRB_FORCE_HEADER 22
1406/* No-op Command - not for transfer rings */
1407#define TRB_CMD_NOOP 23
1408/* TRB IDs 24-31 reserved */
1409/* Event TRBS */
1410/* Transfer Event */
1411#define TRB_TRANSFER 32
1412/* Command Completion Event */
1413#define TRB_COMPLETION 33
1414/* Port Status Change Event */
1415#define TRB_PORT_STATUS 34
1416/* Bandwidth Request Event (opt) */
1417#define TRB_BANDWIDTH_EVENT 35
1418/* Doorbell Event (opt) */
1419#define TRB_DOORBELL 36
1420/* Host Controller Event */
1421#define TRB_HC_EVENT 37
1422/* Device Notification Event - device sent function wake notification */
1423#define TRB_DEV_NOTE 38
1424/* MFINDEX Wrap Event - microframe counter wrapped */
1425#define TRB_MFINDEX_WRAP 39
1426/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1427#define TRB_VENDOR_DEFINED_LOW 48
1428/* Nec vendor-specific command completion event. */
1429#define TRB_NEC_CMD_COMP 48
1430/* Get NEC firmware revision. */
1431#define TRB_NEC_GET_FW 49
1432
1433static inline const char *xhci_trb_type_string(u8 type)
1434{
1435 switch (type) {
1436 case TRB_NORMAL:
1437 return "Normal";
1438 case TRB_SETUP:
1439 return "Setup Stage";
1440 case TRB_DATA:
1441 return "Data Stage";
1442 case TRB_STATUS:
1443 return "Status Stage";
1444 case TRB_ISOC:
1445 return "Isoch";
1446 case TRB_LINK:
1447 return "Link";
1448 case TRB_EVENT_DATA:
1449 return "Event Data";
1450 case TRB_TR_NOOP:
1451 return "No-Op";
1452 case TRB_ENABLE_SLOT:
1453 return "Enable Slot Command";
1454 case TRB_DISABLE_SLOT:
1455 return "Disable Slot Command";
1456 case TRB_ADDR_DEV:
1457 return "Address Device Command";
1458 case TRB_CONFIG_EP:
1459 return "Configure Endpoint Command";
1460 case TRB_EVAL_CONTEXT:
1461 return "Evaluate Context Command";
1462 case TRB_RESET_EP:
1463 return "Reset Endpoint Command";
1464 case TRB_STOP_RING:
1465 return "Stop Ring Command";
1466 case TRB_SET_DEQ:
1467 return "Set TR Dequeue Pointer Command";
1468 case TRB_RESET_DEV:
1469 return "Reset Device Command";
1470 case TRB_FORCE_EVENT:
1471 return "Force Event Command";
1472 case TRB_NEG_BANDWIDTH:
1473 return "Negotiate Bandwidth Command";
1474 case TRB_SET_LT:
1475 return "Set Latency Tolerance Value Command";
1476 case TRB_GET_BW:
1477 return "Get Port Bandwidth Command";
1478 case TRB_FORCE_HEADER:
1479 return "Force Header Command";
1480 case TRB_CMD_NOOP:
1481 return "No-Op Command";
1482 case TRB_TRANSFER:
1483 return "Transfer Event";
1484 case TRB_COMPLETION:
1485 return "Command Completion Event";
1486 case TRB_PORT_STATUS:
1487 return "Port Status Change Event";
1488 case TRB_BANDWIDTH_EVENT:
1489 return "Bandwidth Request Event";
1490 case TRB_DOORBELL:
1491 return "Doorbell Event";
1492 case TRB_HC_EVENT:
1493 return "Host Controller Event";
1494 case TRB_DEV_NOTE:
1495 return "Device Notification Event";
1496 case TRB_MFINDEX_WRAP:
1497 return "MFINDEX Wrap Event";
1498 case TRB_NEC_CMD_COMP:
1499 return "NEC Command Completion Event";
1500 case TRB_NEC_GET_FW:
1501 return "NET Get Firmware Revision Command";
1502 default:
1503 return "UNKNOWN";
1504 }
1505}
1506
1507#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1508/* Above, but for __le32 types -- can avoid work by swapping constants: */
1509#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1510 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1511#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1512 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1513
1514#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1515#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1516
1517/*
1518 * TRBS_PER_SEGMENT must be a multiple of 4,
1519 * since the command ring is 64-byte aligned.
1520 * It must also be greater than 16.
1521 */
1522#define TRBS_PER_SEGMENT 256
1523/* Allow two commands + a link TRB, along with any reserved command TRBs */
1524#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1525#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1526#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1527/* TRB buffer pointers can't cross 64KB boundaries */
1528#define TRB_MAX_BUFF_SHIFT 16
1529#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1530/* How much data is left before the 64KB boundary? */
1531#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1532 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1533#define MAX_SOFT_RETRY 3
1534/*
1535 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1536 * XHCI_AVOID_BEI quirk is in use.
1537 */
1538#define AVOID_BEI_INTERVAL_MIN 8
1539#define AVOID_BEI_INTERVAL_MAX 32
1540
1541struct xhci_segment {
1542 union xhci_trb *trbs;
1543 /* private to HCD */
1544 struct xhci_segment *next;
1545 dma_addr_t dma;
1546 /* Max packet sized bounce buffer for td-fragmant alignment */
1547 dma_addr_t bounce_dma;
1548 void *bounce_buf;
1549 unsigned int bounce_offs;
1550 unsigned int bounce_len;
1551};
1552
1553enum xhci_cancelled_td_status {
1554 TD_DIRTY = 0,
1555 TD_HALTED,
1556 TD_CLEARING_CACHE,
1557 TD_CLEARED,
1558};
1559
1560struct xhci_td {
1561 struct list_head td_list;
1562 struct list_head cancelled_td_list;
1563 int status;
1564 enum xhci_cancelled_td_status cancel_status;
1565 struct urb *urb;
1566 struct xhci_segment *start_seg;
1567 union xhci_trb *first_trb;
1568 union xhci_trb *last_trb;
1569 struct xhci_segment *last_trb_seg;
1570 struct xhci_segment *bounce_seg;
1571 /* actual_length of the URB has already been set */
1572 bool urb_length_set;
1573 unsigned int num_trbs;
1574};
1575
1576/* xHCI command default timeout value */
1577#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1578
1579/* command descriptor */
1580struct xhci_cd {
1581 struct xhci_command *command;
1582 union xhci_trb *cmd_trb;
1583};
1584
1585enum xhci_ring_type {
1586 TYPE_CTRL = 0,
1587 TYPE_ISOC,
1588 TYPE_BULK,
1589 TYPE_INTR,
1590 TYPE_STREAM,
1591 TYPE_COMMAND,
1592 TYPE_EVENT,
1593};
1594
1595static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1596{
1597 switch (type) {
1598 case TYPE_CTRL:
1599 return "CTRL";
1600 case TYPE_ISOC:
1601 return "ISOC";
1602 case TYPE_BULK:
1603 return "BULK";
1604 case TYPE_INTR:
1605 return "INTR";
1606 case TYPE_STREAM:
1607 return "STREAM";
1608 case TYPE_COMMAND:
1609 return "CMD";
1610 case TYPE_EVENT:
1611 return "EVENT";
1612 }
1613
1614 return "UNKNOWN";
1615}
1616
1617struct xhci_ring {
1618 struct xhci_segment *first_seg;
1619 struct xhci_segment *last_seg;
1620 union xhci_trb *enqueue;
1621 struct xhci_segment *enq_seg;
1622 union xhci_trb *dequeue;
1623 struct xhci_segment *deq_seg;
1624 struct list_head td_list;
1625 /*
1626 * Write the cycle state into the TRB cycle field to give ownership of
1627 * the TRB to the host controller (if we are the producer), or to check
1628 * if we own the TRB (if we are the consumer). See section 4.9.1.
1629 */
1630 u32 cycle_state;
1631 unsigned int stream_id;
1632 unsigned int num_segs;
1633 unsigned int num_trbs_free;
1634 unsigned int num_trbs_free_temp;
1635 unsigned int bounce_buf_len;
1636 enum xhci_ring_type type;
1637 bool last_td_was_short;
1638 struct radix_tree_root *trb_address_map;
1639};
1640
1641struct xhci_erst_entry {
1642 /* 64-bit event ring segment address */
1643 __le64 seg_addr;
1644 __le32 seg_size;
1645 /* Set to zero */
1646 __le32 rsvd;
1647};
1648
1649struct xhci_erst {
1650 struct xhci_erst_entry *entries;
1651 unsigned int num_entries;
1652 /* xhci->event_ring keeps track of segment dma addresses */
1653 dma_addr_t erst_dma_addr;
1654 /* Num entries the ERST can contain */
1655 unsigned int erst_size;
1656};
1657
1658struct xhci_scratchpad {
1659 u64 *sp_array;
1660 dma_addr_t sp_dma;
1661 void **sp_buffers;
1662};
1663
1664struct urb_priv {
1665 int num_tds;
1666 int num_tds_done;
1667 struct xhci_td td[];
1668};
1669
1670/*
1671 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1672 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1673 * meaning 64 ring segments.
1674 * Initial allocated size of the ERST, in number of entries */
1675#define ERST_NUM_SEGS 1
1676/* Poll every 60 seconds */
1677#define POLL_TIMEOUT 60
1678/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1679#define XHCI_STOP_EP_CMD_TIMEOUT 5
1680/* XXX: Make these module parameters */
1681
1682struct s3_save {
1683 u32 command;
1684 u32 dev_nt;
1685 u64 dcbaa_ptr;
1686 u32 config_reg;
1687 u32 irq_pending;
1688 u32 irq_control;
1689 u32 erst_size;
1690 u64 erst_base;
1691 u64 erst_dequeue;
1692};
1693
1694/* Use for lpm */
1695struct dev_info {
1696 u32 dev_id;
1697 struct list_head list;
1698};
1699
1700struct xhci_bus_state {
1701 unsigned long bus_suspended;
1702 unsigned long next_statechange;
1703
1704 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1705 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1706 u32 port_c_suspend;
1707 u32 suspended_ports;
1708 u32 port_remote_wakeup;
1709 unsigned long resume_done[USB_MAXCHILDREN];
1710 /* which ports have started to resume */
1711 unsigned long resuming_ports;
1712 /* Which ports are waiting on RExit to U0 transition. */
1713 unsigned long rexit_ports;
1714 struct completion rexit_done[USB_MAXCHILDREN];
1715 struct completion u3exit_done[USB_MAXCHILDREN];
1716};
1717
1718
1719/*
1720 * It can take up to 20 ms to transition from RExit to U0 on the
1721 * Intel Lynx Point LP xHCI host.
1722 */
1723#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1724struct xhci_port_cap {
1725 u32 *psi; /* array of protocol speed ID entries */
1726 u8 psi_count;
1727 u8 psi_uid_count;
1728 u8 maj_rev;
1729 u8 min_rev;
1730};
1731
1732struct xhci_port {
1733 __le32 __iomem *addr;
1734 int hw_portnum;
1735 int hcd_portnum;
1736 struct xhci_hub *rhub;
1737 struct xhci_port_cap *port_cap;
1738 unsigned int lpm_incapable:1;
1739};
1740
1741struct xhci_hub {
1742 struct xhci_port **ports;
1743 unsigned int num_ports;
1744 struct usb_hcd *hcd;
1745 /* keep track of bus suspend info */
1746 struct xhci_bus_state bus_state;
1747 /* supported prococol extended capabiliy values */
1748 u8 maj_rev;
1749 u8 min_rev;
1750};
1751
1752/* There is one xhci_hcd structure per controller */
1753struct xhci_hcd {
1754 struct usb_hcd *main_hcd;
1755 struct usb_hcd *shared_hcd;
1756 /* glue to PCI and HCD framework */
1757 struct xhci_cap_regs __iomem *cap_regs;
1758 struct xhci_op_regs __iomem *op_regs;
1759 struct xhci_run_regs __iomem *run_regs;
1760 struct xhci_doorbell_array __iomem *dba;
1761 /* Our HCD's current interrupter register set */
1762 struct xhci_intr_reg __iomem *ir_set;
1763
1764 /* Cached register copies of read-only HC data */
1765 __u32 hcs_params1;
1766 __u32 hcs_params2;
1767 __u32 hcs_params3;
1768 __u32 hcc_params;
1769 __u32 hcc_params2;
1770
1771 spinlock_t lock;
1772
1773 /* packed release number */
1774 u8 sbrn;
1775 u16 hci_version;
1776 u8 max_slots;
1777 u8 max_interrupters;
1778 u8 max_ports;
1779 u8 isoc_threshold;
1780 /* imod_interval in ns (I * 250ns) */
1781 u32 imod_interval;
1782 u32 isoc_bei_interval;
1783 int event_ring_max;
1784 /* 4KB min, 128MB max */
1785 int page_size;
1786 /* Valid values are 12 to 20, inclusive */
1787 int page_shift;
1788 /* msi-x vectors */
1789 int msix_count;
1790 /* optional clocks */
1791 struct clk *clk;
1792 struct clk *reg_clk;
1793 /* optional reset controller */
1794 struct reset_control *reset;
1795 /* data structures */
1796 struct xhci_device_context_array *dcbaa;
1797 struct xhci_ring *cmd_ring;
1798 unsigned int cmd_ring_state;
1799#define CMD_RING_STATE_RUNNING (1 << 0)
1800#define CMD_RING_STATE_ABORTED (1 << 1)
1801#define CMD_RING_STATE_STOPPED (1 << 2)
1802 struct list_head cmd_list;
1803 unsigned int cmd_ring_reserved_trbs;
1804 struct delayed_work cmd_timer;
1805 struct completion cmd_ring_stop_completion;
1806 struct xhci_command *current_cmd;
1807 struct xhci_ring *event_ring;
1808 struct xhci_erst erst;
1809 /* Scratchpad */
1810 struct xhci_scratchpad *scratchpad;
1811
1812 /* slot enabling and address device helpers */
1813 /* these are not thread safe so use mutex */
1814 struct mutex mutex;
1815 /* Internal mirror of the HW's dcbaa */
1816 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1817 /* For keeping track of bandwidth domains per roothub. */
1818 struct xhci_root_port_bw_info *rh_bw;
1819
1820 /* DMA pools */
1821 struct dma_pool *device_pool;
1822 struct dma_pool *segment_pool;
1823 struct dma_pool *small_streams_pool;
1824 struct dma_pool *medium_streams_pool;
1825
1826 /* Host controller watchdog timer structures */
1827 unsigned int xhc_state;
1828 unsigned long run_graceperiod;
1829 struct s3_save s3;
1830/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1831 *
1832 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1833 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1834 * that sees this status (other than the timer that set it) should stop touching
1835 * hardware immediately. Interrupt handlers should return immediately when
1836 * they see this status (any time they drop and re-acquire xhci->lock).
1837 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1838 * putting the TD on the canceled list, etc.
1839 *
1840 * There are no reports of xHCI host controllers that display this issue.
1841 */
1842#define XHCI_STATE_DYING (1 << 0)
1843#define XHCI_STATE_HALTED (1 << 1)
1844#define XHCI_STATE_REMOVING (1 << 2)
1845 unsigned long long quirks;
1846#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1847#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1848#define XHCI_NEC_HOST BIT_ULL(2)
1849#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1850#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1851/*
1852 * Certain Intel host controllers have a limit to the number of endpoint
1853 * contexts they can handle. Ideally, they would signal that they can't handle
1854 * anymore endpoint contexts by returning a Resource Error for the Configure
1855 * Endpoint command, but they don't. Instead they expect software to keep track
1856 * of the number of active endpoints for them, across configure endpoint
1857 * commands, reset device commands, disable slot commands, and address device
1858 * commands.
1859 */
1860#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1861#define XHCI_BROKEN_MSI BIT_ULL(6)
1862#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1863#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1864#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1865#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1866#define XHCI_LPM_SUPPORT BIT_ULL(11)
1867#define XHCI_INTEL_HOST BIT_ULL(12)
1868#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1869#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1870#define XHCI_AVOID_BEI BIT_ULL(15)
1871#define XHCI_PLAT BIT_ULL(16)
1872#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1873#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1874/* For controllers with a broken beyond repair streams implementation */
1875#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1876#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1877#define XHCI_MTK_HOST BIT_ULL(21)
1878#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1879#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1880#define XHCI_MISSING_CAS BIT_ULL(24)
1881/* For controller with a broken Port Disable implementation */
1882#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1883#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1884#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1885#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1886#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1887#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1888#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1889#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1890#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1891#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1892#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1893#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1894#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1895#define XHCI_DISABLE_SPARSE BIT_ULL(38)
1896#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1897#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1898#define XHCI_BROKEN_D3COLD BIT_ULL(41)
1899#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1900#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1901#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1902
1903 unsigned int num_active_eps;
1904 unsigned int limit_active_eps;
1905 struct xhci_port *hw_ports;
1906 struct xhci_hub usb2_rhub;
1907 struct xhci_hub usb3_rhub;
1908 /* support xHCI 1.0 spec USB2 hardware LPM */
1909 unsigned hw_lpm_support:1;
1910 /* Broken Suspend flag for SNPS Suspend resume issue */
1911 unsigned broken_suspend:1;
1912 /* Indicates that omitting hcd is supported if root hub has no ports */
1913 unsigned allow_single_roothub:1;
1914 /* cached usb2 extened protocol capabilites */
1915 u32 *ext_caps;
1916 unsigned int num_ext_caps;
1917 /* cached extended protocol port capabilities */
1918 struct xhci_port_cap *port_caps;
1919 unsigned int num_port_caps;
1920 /* Compliance Mode Recovery Data */
1921 struct timer_list comp_mode_recovery_timer;
1922 u32 port_status_u0;
1923 u16 test_mode;
1924/* Compliance Mode Timer Triggered every 2 seconds */
1925#define COMP_MODE_RCVRY_MSECS 2000
1926
1927 struct dentry *debugfs_root;
1928 struct dentry *debugfs_slots;
1929 struct list_head regset_list;
1930
1931 void *dbc;
1932 /* platform-specific data -- must come last */
1933 unsigned long priv[] __aligned(sizeof(s64));
1934};
1935
1936/* Platform specific overrides to generic XHCI hc_driver ops */
1937struct xhci_driver_overrides {
1938 size_t extra_priv_size;
1939 int (*reset)(struct usb_hcd *hcd);
1940 int (*start)(struct usb_hcd *hcd);
1941 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1942 struct usb_host_endpoint *ep);
1943 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1944 struct usb_host_endpoint *ep);
1945 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1946 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1947 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1948 struct usb_tt *tt, gfp_t mem_flags);
1949};
1950
1951#define XHCI_CFC_DELAY 10
1952
1953/* convert between an HCD pointer and the corresponding EHCI_HCD */
1954static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1955{
1956 struct usb_hcd *primary_hcd;
1957
1958 if (usb_hcd_is_primary_hcd(hcd))
1959 primary_hcd = hcd;
1960 else
1961 primary_hcd = hcd->primary_hcd;
1962
1963 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1964}
1965
1966static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1967{
1968 return xhci->main_hcd;
1969}
1970
1971static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1972{
1973 if (xhci->shared_hcd)
1974 return xhci->shared_hcd;
1975
1976 if (!xhci->usb2_rhub.num_ports)
1977 return xhci->main_hcd;
1978
1979 return NULL;
1980}
1981
1982static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1983{
1984 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1985
1986 return hcd == xhci_get_usb3_hcd(xhci);
1987}
1988
1989static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1990{
1991 return xhci->allow_single_roothub &&
1992 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1993}
1994
1995#define xhci_dbg(xhci, fmt, args...) \
1996 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1997#define xhci_err(xhci, fmt, args...) \
1998 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1999#define xhci_warn(xhci, fmt, args...) \
2000 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2001#define xhci_warn_ratelimited(xhci, fmt, args...) \
2002 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2003#define xhci_info(xhci, fmt, args...) \
2004 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2005
2006/*
2007 * Registers should always be accessed with double word or quad word accesses.
2008 *
2009 * Some xHCI implementations may support 64-bit address pointers. Registers
2010 * with 64-bit address pointers should be written to with dword accesses by
2011 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
2012 * xHCI implementations that do not support 64-bit address pointers will ignore
2013 * the high dword, and write order is irrelevant.
2014 */
2015static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
2016 __le64 __iomem *regs)
2017{
2018 return lo_hi_readq(regs);
2019}
2020static inline void xhci_write_64(struct xhci_hcd *xhci,
2021 const u64 val, __le64 __iomem *regs)
2022{
2023 lo_hi_writeq(val, regs);
2024}
2025
2026static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
2027{
2028 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
2029}
2030
2031/* xHCI debugging */
2032char *xhci_get_slot_state(struct xhci_hcd *xhci,
2033 struct xhci_container_ctx *ctx);
2034void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2035 const char *fmt, ...);
2036
2037/* xHCI memory management */
2038void xhci_mem_cleanup(struct xhci_hcd *xhci);
2039int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2040void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2041int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2042int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2043void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2044 struct usb_device *udev);
2045unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2046unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2047void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2048void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2049 struct xhci_virt_device *virt_dev,
2050 int old_active_eps);
2051void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2052void xhci_update_bw_info(struct xhci_hcd *xhci,
2053 struct xhci_container_ctx *in_ctx,
2054 struct xhci_input_control_ctx *ctrl_ctx,
2055 struct xhci_virt_device *virt_dev);
2056void xhci_endpoint_copy(struct xhci_hcd *xhci,
2057 struct xhci_container_ctx *in_ctx,
2058 struct xhci_container_ctx *out_ctx,
2059 unsigned int ep_index);
2060void xhci_slot_copy(struct xhci_hcd *xhci,
2061 struct xhci_container_ctx *in_ctx,
2062 struct xhci_container_ctx *out_ctx);
2063int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2064 struct usb_device *udev, struct usb_host_endpoint *ep,
2065 gfp_t mem_flags);
2066struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2067 unsigned int num_segs, unsigned int cycle_state,
2068 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2069void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2070int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2071 unsigned int num_trbs, gfp_t flags);
2072int xhci_alloc_erst(struct xhci_hcd *xhci,
2073 struct xhci_ring *evt_ring,
2074 struct xhci_erst *erst,
2075 gfp_t flags);
2076void xhci_initialize_ring_info(struct xhci_ring *ring,
2077 unsigned int cycle_state);
2078void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2079void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2080 struct xhci_virt_device *virt_dev,
2081 unsigned int ep_index);
2082struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2083 unsigned int num_stream_ctxs,
2084 unsigned int num_streams,
2085 unsigned int max_packet, gfp_t flags);
2086void xhci_free_stream_info(struct xhci_hcd *xhci,
2087 struct xhci_stream_info *stream_info);
2088void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2089 struct xhci_ep_ctx *ep_ctx,
2090 struct xhci_stream_info *stream_info);
2091void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2092 struct xhci_virt_ep *ep);
2093void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2094 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2095struct xhci_ring *xhci_dma_to_transfer_ring(
2096 struct xhci_virt_ep *ep,
2097 u64 address);
2098struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2099 bool allocate_completion, gfp_t mem_flags);
2100struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2101 bool allocate_completion, gfp_t mem_flags);
2102void xhci_urb_free_priv(struct urb_priv *urb_priv);
2103void xhci_free_command(struct xhci_hcd *xhci,
2104 struct xhci_command *command);
2105struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2106 int type, gfp_t flags);
2107void xhci_free_container_ctx(struct xhci_hcd *xhci,
2108 struct xhci_container_ctx *ctx);
2109
2110/* xHCI host controller glue */
2111typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2112int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2113void xhci_quiesce(struct xhci_hcd *xhci);
2114int xhci_halt(struct xhci_hcd *xhci);
2115int xhci_start(struct xhci_hcd *xhci);
2116int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2117int xhci_run(struct usb_hcd *hcd);
2118int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2119void xhci_shutdown(struct usb_hcd *hcd);
2120void xhci_init_driver(struct hc_driver *drv,
2121 const struct xhci_driver_overrides *over);
2122int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2123 struct usb_host_endpoint *ep);
2124int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2125 struct usb_host_endpoint *ep);
2126int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2127void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2128int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2129 struct usb_tt *tt, gfp_t mem_flags);
2130int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2131int xhci_ext_cap_init(struct xhci_hcd *xhci);
2132
2133int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2134int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2135
2136irqreturn_t xhci_irq(struct usb_hcd *hcd);
2137irqreturn_t xhci_msi_irq(int irq, void *hcd);
2138int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2139int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2140 struct xhci_virt_device *virt_dev,
2141 struct usb_device *hdev,
2142 struct usb_tt *tt, gfp_t mem_flags);
2143
2144/* xHCI ring, segment, TRB, and TD functions */
2145dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2146struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2147 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2148 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2149int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2150void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2151int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2152 u32 trb_type, u32 slot_id);
2153int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2154 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2155int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2156 u32 field1, u32 field2, u32 field3, u32 field4);
2157int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2158 int slot_id, unsigned int ep_index, int suspend);
2159int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2160 int slot_id, unsigned int ep_index);
2161int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2162 int slot_id, unsigned int ep_index);
2163int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2164 int slot_id, unsigned int ep_index);
2165int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2166 struct urb *urb, int slot_id, unsigned int ep_index);
2167int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2168 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2169 bool command_must_succeed);
2170int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2171 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2172int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2173 int slot_id, unsigned int ep_index,
2174 enum xhci_ep_reset_type reset_type);
2175int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2176 u32 slot_id);
2177void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2178 unsigned int ep_index, unsigned int stream_id,
2179 struct xhci_td *td);
2180void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2181void xhci_handle_command_timeout(struct work_struct *work);
2182
2183void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2184 unsigned int ep_index, unsigned int stream_id);
2185void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2186 unsigned int slot_id,
2187 unsigned int ep_index);
2188void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2189void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2190unsigned int count_trbs(u64 addr, u64 len);
2191
2192/* xHCI roothub code */
2193void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2194 u32 link_state);
2195void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2196 u32 port_bit);
2197int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2198 char *buf, u16 wLength);
2199int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2200int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2201struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2202
2203void xhci_hc_died(struct xhci_hcd *xhci);
2204
2205#ifdef CONFIG_PM
2206int xhci_bus_suspend(struct usb_hcd *hcd);
2207int xhci_bus_resume(struct usb_hcd *hcd);
2208unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2209#else
2210#define xhci_bus_suspend NULL
2211#define xhci_bus_resume NULL
2212#define xhci_get_resuming_ports NULL
2213#endif /* CONFIG_PM */
2214
2215u32 xhci_port_state_to_neutral(u32 state);
2216int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2217 u16 port);
2218void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2219
2220/* xHCI contexts */
2221struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2222struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2223struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2224
2225struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2226 unsigned int slot_id, unsigned int ep_index,
2227 unsigned int stream_id);
2228
2229static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2230 struct urb *urb)
2231{
2232 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2233 xhci_get_endpoint_index(&urb->ep->desc),
2234 urb->stream_id);
2235}
2236
2237/*
2238 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2239 * them anyways as we where unable to find a device that matches the
2240 * constraints.
2241 */
2242static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2243{
2244 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2245 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2246 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2247 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2248 !urb->num_sgs)
2249 return true;
2250
2251 return false;
2252}
2253
2254static inline char *xhci_slot_state_string(u32 state)
2255{
2256 switch (state) {
2257 case SLOT_STATE_ENABLED:
2258 return "enabled/disabled";
2259 case SLOT_STATE_DEFAULT:
2260 return "default";
2261 case SLOT_STATE_ADDRESSED:
2262 return "addressed";
2263 case SLOT_STATE_CONFIGURED:
2264 return "configured";
2265 default:
2266 return "reserved";
2267 }
2268}
2269
2270static inline const char *xhci_decode_trb(char *str, size_t size,
2271 u32 field0, u32 field1, u32 field2, u32 field3)
2272{
2273 int type = TRB_FIELD_TO_TYPE(field3);
2274
2275 switch (type) {
2276 case TRB_LINK:
2277 snprintf(str, size,
2278 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2279 field1, field0, GET_INTR_TARGET(field2),
2280 xhci_trb_type_string(type),
2281 field3 & TRB_IOC ? 'I' : 'i',
2282 field3 & TRB_CHAIN ? 'C' : 'c',
2283 field3 & TRB_TC ? 'T' : 't',
2284 field3 & TRB_CYCLE ? 'C' : 'c');
2285 break;
2286 case TRB_TRANSFER:
2287 case TRB_COMPLETION:
2288 case TRB_PORT_STATUS:
2289 case TRB_BANDWIDTH_EVENT:
2290 case TRB_DOORBELL:
2291 case TRB_HC_EVENT:
2292 case TRB_DEV_NOTE:
2293 case TRB_MFINDEX_WRAP:
2294 snprintf(str, size,
2295 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2296 field1, field0,
2297 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2298 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2299 /* Macro decrements 1, maybe it shouldn't?!? */
2300 TRB_TO_EP_INDEX(field3) + 1,
2301 xhci_trb_type_string(type),
2302 field3 & EVENT_DATA ? 'E' : 'e',
2303 field3 & TRB_CYCLE ? 'C' : 'c');
2304
2305 break;
2306 case TRB_SETUP:
2307 snprintf(str, size,
2308 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2309 field0 & 0xff,
2310 (field0 & 0xff00) >> 8,
2311 (field0 & 0xff000000) >> 24,
2312 (field0 & 0xff0000) >> 16,
2313 (field1 & 0xff00) >> 8,
2314 field1 & 0xff,
2315 (field1 & 0xff000000) >> 16 |
2316 (field1 & 0xff0000) >> 16,
2317 TRB_LEN(field2), GET_TD_SIZE(field2),
2318 GET_INTR_TARGET(field2),
2319 xhci_trb_type_string(type),
2320 field3 & TRB_IDT ? 'I' : 'i',
2321 field3 & TRB_IOC ? 'I' : 'i',
2322 field3 & TRB_CYCLE ? 'C' : 'c');
2323 break;
2324 case TRB_DATA:
2325 snprintf(str, size,
2326 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2327 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2328 GET_INTR_TARGET(field2),
2329 xhci_trb_type_string(type),
2330 field3 & TRB_IDT ? 'I' : 'i',
2331 field3 & TRB_IOC ? 'I' : 'i',
2332 field3 & TRB_CHAIN ? 'C' : 'c',
2333 field3 & TRB_NO_SNOOP ? 'S' : 's',
2334 field3 & TRB_ISP ? 'I' : 'i',
2335 field3 & TRB_ENT ? 'E' : 'e',
2336 field3 & TRB_CYCLE ? 'C' : 'c');
2337 break;
2338 case TRB_STATUS:
2339 snprintf(str, size,
2340 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2341 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2342 GET_INTR_TARGET(field2),
2343 xhci_trb_type_string(type),
2344 field3 & TRB_IOC ? 'I' : 'i',
2345 field3 & TRB_CHAIN ? 'C' : 'c',
2346 field3 & TRB_ENT ? 'E' : 'e',
2347 field3 & TRB_CYCLE ? 'C' : 'c');
2348 break;
2349 case TRB_NORMAL:
2350 case TRB_ISOC:
2351 case TRB_EVENT_DATA:
2352 case TRB_TR_NOOP:
2353 snprintf(str, size,
2354 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2355 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2356 GET_INTR_TARGET(field2),
2357 xhci_trb_type_string(type),
2358 field3 & TRB_BEI ? 'B' : 'b',
2359 field3 & TRB_IDT ? 'I' : 'i',
2360 field3 & TRB_IOC ? 'I' : 'i',
2361 field3 & TRB_CHAIN ? 'C' : 'c',
2362 field3 & TRB_NO_SNOOP ? 'S' : 's',
2363 field3 & TRB_ISP ? 'I' : 'i',
2364 field3 & TRB_ENT ? 'E' : 'e',
2365 field3 & TRB_CYCLE ? 'C' : 'c');
2366 break;
2367
2368 case TRB_CMD_NOOP:
2369 case TRB_ENABLE_SLOT:
2370 snprintf(str, size,
2371 "%s: flags %c",
2372 xhci_trb_type_string(type),
2373 field3 & TRB_CYCLE ? 'C' : 'c');
2374 break;
2375 case TRB_DISABLE_SLOT:
2376 case TRB_NEG_BANDWIDTH:
2377 snprintf(str, size,
2378 "%s: slot %d flags %c",
2379 xhci_trb_type_string(type),
2380 TRB_TO_SLOT_ID(field3),
2381 field3 & TRB_CYCLE ? 'C' : 'c');
2382 break;
2383 case TRB_ADDR_DEV:
2384 snprintf(str, size,
2385 "%s: ctx %08x%08x slot %d flags %c:%c",
2386 xhci_trb_type_string(type),
2387 field1, field0,
2388 TRB_TO_SLOT_ID(field3),
2389 field3 & TRB_BSR ? 'B' : 'b',
2390 field3 & TRB_CYCLE ? 'C' : 'c');
2391 break;
2392 case TRB_CONFIG_EP:
2393 snprintf(str, size,
2394 "%s: ctx %08x%08x slot %d flags %c:%c",
2395 xhci_trb_type_string(type),
2396 field1, field0,
2397 TRB_TO_SLOT_ID(field3),
2398 field3 & TRB_DC ? 'D' : 'd',
2399 field3 & TRB_CYCLE ? 'C' : 'c');
2400 break;
2401 case TRB_EVAL_CONTEXT:
2402 snprintf(str, size,
2403 "%s: ctx %08x%08x slot %d flags %c",
2404 xhci_trb_type_string(type),
2405 field1, field0,
2406 TRB_TO_SLOT_ID(field3),
2407 field3 & TRB_CYCLE ? 'C' : 'c');
2408 break;
2409 case TRB_RESET_EP:
2410 snprintf(str, size,
2411 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2412 xhci_trb_type_string(type),
2413 field1, field0,
2414 TRB_TO_SLOT_ID(field3),
2415 /* Macro decrements 1, maybe it shouldn't?!? */
2416 TRB_TO_EP_INDEX(field3) + 1,
2417 field3 & TRB_TSP ? 'T' : 't',
2418 field3 & TRB_CYCLE ? 'C' : 'c');
2419 break;
2420 case TRB_STOP_RING:
2421 snprintf(str, size,
2422 "%s: slot %d sp %d ep %d flags %c",
2423 xhci_trb_type_string(type),
2424 TRB_TO_SLOT_ID(field3),
2425 TRB_TO_SUSPEND_PORT(field3),
2426 /* Macro decrements 1, maybe it shouldn't?!? */
2427 TRB_TO_EP_INDEX(field3) + 1,
2428 field3 & TRB_CYCLE ? 'C' : 'c');
2429 break;
2430 case TRB_SET_DEQ:
2431 snprintf(str, size,
2432 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2433 xhci_trb_type_string(type),
2434 field1, field0,
2435 TRB_TO_STREAM_ID(field2),
2436 TRB_TO_SLOT_ID(field3),
2437 /* Macro decrements 1, maybe it shouldn't?!? */
2438 TRB_TO_EP_INDEX(field3) + 1,
2439 field3 & TRB_CYCLE ? 'C' : 'c');
2440 break;
2441 case TRB_RESET_DEV:
2442 snprintf(str, size,
2443 "%s: slot %d flags %c",
2444 xhci_trb_type_string(type),
2445 TRB_TO_SLOT_ID(field3),
2446 field3 & TRB_CYCLE ? 'C' : 'c');
2447 break;
2448 case TRB_FORCE_EVENT:
2449 snprintf(str, size,
2450 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2451 xhci_trb_type_string(type),
2452 field1, field0,
2453 TRB_TO_VF_INTR_TARGET(field2),
2454 TRB_TO_VF_ID(field3),
2455 field3 & TRB_CYCLE ? 'C' : 'c');
2456 break;
2457 case TRB_SET_LT:
2458 snprintf(str, size,
2459 "%s: belt %d flags %c",
2460 xhci_trb_type_string(type),
2461 TRB_TO_BELT(field3),
2462 field3 & TRB_CYCLE ? 'C' : 'c');
2463 break;
2464 case TRB_GET_BW:
2465 snprintf(str, size,
2466 "%s: ctx %08x%08x slot %d speed %d flags %c",
2467 xhci_trb_type_string(type),
2468 field1, field0,
2469 TRB_TO_SLOT_ID(field3),
2470 TRB_TO_DEV_SPEED(field3),
2471 field3 & TRB_CYCLE ? 'C' : 'c');
2472 break;
2473 case TRB_FORCE_HEADER:
2474 snprintf(str, size,
2475 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2476 xhci_trb_type_string(type),
2477 field2, field1, field0 & 0xffffffe0,
2478 TRB_TO_PACKET_TYPE(field0),
2479 TRB_TO_ROOTHUB_PORT(field3),
2480 field3 & TRB_CYCLE ? 'C' : 'c');
2481 break;
2482 default:
2483 snprintf(str, size,
2484 "type '%s' -> raw %08x %08x %08x %08x",
2485 xhci_trb_type_string(type),
2486 field0, field1, field2, field3);
2487 }
2488
2489 return str;
2490}
2491
2492static inline const char *xhci_decode_ctrl_ctx(char *str,
2493 unsigned long drop, unsigned long add)
2494{
2495 unsigned int bit;
2496 int ret = 0;
2497
2498 str[0] = '\0';
2499
2500 if (drop) {
2501 ret = sprintf(str, "Drop:");
2502 for_each_set_bit(bit, &drop, 32)
2503 ret += sprintf(str + ret, " %d%s",
2504 bit / 2,
2505 bit % 2 ? "in":"out");
2506 ret += sprintf(str + ret, ", ");
2507 }
2508
2509 if (add) {
2510 ret += sprintf(str + ret, "Add:%s%s",
2511 (add & SLOT_FLAG) ? " slot":"",
2512 (add & EP0_FLAG) ? " ep0":"");
2513 add &= ~(SLOT_FLAG | EP0_FLAG);
2514 for_each_set_bit(bit, &add, 32)
2515 ret += sprintf(str + ret, " %d%s",
2516 bit / 2,
2517 bit % 2 ? "in":"out");
2518 }
2519 return str;
2520}
2521
2522static inline const char *xhci_decode_slot_context(char *str,
2523 u32 info, u32 info2, u32 tt_info, u32 state)
2524{
2525 u32 speed;
2526 u32 hub;
2527 u32 mtt;
2528 int ret = 0;
2529
2530 speed = info & DEV_SPEED;
2531 hub = info & DEV_HUB;
2532 mtt = info & DEV_MTT;
2533
2534 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2535 info & ROUTE_STRING_MASK,
2536 ({ char *s;
2537 switch (speed) {
2538 case SLOT_SPEED_FS:
2539 s = "full-speed";
2540 break;
2541 case SLOT_SPEED_LS:
2542 s = "low-speed";
2543 break;
2544 case SLOT_SPEED_HS:
2545 s = "high-speed";
2546 break;
2547 case SLOT_SPEED_SS:
2548 s = "super-speed";
2549 break;
2550 case SLOT_SPEED_SSP:
2551 s = "super-speed plus";
2552 break;
2553 default:
2554 s = "UNKNOWN speed";
2555 } s; }),
2556 mtt ? " multi-TT" : "",
2557 hub ? " Hub" : "",
2558 (info & LAST_CTX_MASK) >> 27,
2559 info2 & MAX_EXIT,
2560 DEVINFO_TO_ROOT_HUB_PORT(info2),
2561 DEVINFO_TO_MAX_PORTS(info2));
2562
2563 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2564 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2565 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2566 state & DEV_ADDR_MASK,
2567 xhci_slot_state_string(GET_SLOT_STATE(state)));
2568
2569 return str;
2570}
2571
2572
2573static inline const char *xhci_portsc_link_state_string(u32 portsc)
2574{
2575 switch (portsc & PORT_PLS_MASK) {
2576 case XDEV_U0:
2577 return "U0";
2578 case XDEV_U1:
2579 return "U1";
2580 case XDEV_U2:
2581 return "U2";
2582 case XDEV_U3:
2583 return "U3";
2584 case XDEV_DISABLED:
2585 return "Disabled";
2586 case XDEV_RXDETECT:
2587 return "RxDetect";
2588 case XDEV_INACTIVE:
2589 return "Inactive";
2590 case XDEV_POLLING:
2591 return "Polling";
2592 case XDEV_RECOVERY:
2593 return "Recovery";
2594 case XDEV_HOT_RESET:
2595 return "Hot Reset";
2596 case XDEV_COMP_MODE:
2597 return "Compliance mode";
2598 case XDEV_TEST_MODE:
2599 return "Test mode";
2600 case XDEV_RESUME:
2601 return "Resume";
2602 default:
2603 break;
2604 }
2605 return "Unknown";
2606}
2607
2608static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2609{
2610 int ret;
2611
2612 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2613 portsc & PORT_POWER ? "Powered" : "Powered-off",
2614 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2615 portsc & PORT_PE ? "Enabled" : "Disabled",
2616 xhci_portsc_link_state_string(portsc),
2617 DEV_PORT_SPEED(portsc));
2618
2619 if (portsc & PORT_OC)
2620 ret += sprintf(str + ret, "OverCurrent ");
2621 if (portsc & PORT_RESET)
2622 ret += sprintf(str + ret, "In-Reset ");
2623
2624 ret += sprintf(str + ret, "Change: ");
2625 if (portsc & PORT_CSC)
2626 ret += sprintf(str + ret, "CSC ");
2627 if (portsc & PORT_PEC)
2628 ret += sprintf(str + ret, "PEC ");
2629 if (portsc & PORT_WRC)
2630 ret += sprintf(str + ret, "WRC ");
2631 if (portsc & PORT_OCC)
2632 ret += sprintf(str + ret, "OCC ");
2633 if (portsc & PORT_RC)
2634 ret += sprintf(str + ret, "PRC ");
2635 if (portsc & PORT_PLC)
2636 ret += sprintf(str + ret, "PLC ");
2637 if (portsc & PORT_CEC)
2638 ret += sprintf(str + ret, "CEC ");
2639 if (portsc & PORT_CAS)
2640 ret += sprintf(str + ret, "CAS ");
2641
2642 ret += sprintf(str + ret, "Wake: ");
2643 if (portsc & PORT_WKCONN_E)
2644 ret += sprintf(str + ret, "WCE ");
2645 if (portsc & PORT_WKDISC_E)
2646 ret += sprintf(str + ret, "WDE ");
2647 if (portsc & PORT_WKOC_E)
2648 ret += sprintf(str + ret, "WOE ");
2649
2650 return str;
2651}
2652
2653static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2654{
2655 int ret = 0;
2656
2657 ret = sprintf(str, " 0x%08x", usbsts);
2658
2659 if (usbsts == ~(u32)0)
2660 return str;
2661
2662 if (usbsts & STS_HALT)
2663 ret += sprintf(str + ret, " HCHalted");
2664 if (usbsts & STS_FATAL)
2665 ret += sprintf(str + ret, " HSE");
2666 if (usbsts & STS_EINT)
2667 ret += sprintf(str + ret, " EINT");
2668 if (usbsts & STS_PORT)
2669 ret += sprintf(str + ret, " PCD");
2670 if (usbsts & STS_SAVE)
2671 ret += sprintf(str + ret, " SSS");
2672 if (usbsts & STS_RESTORE)
2673 ret += sprintf(str + ret, " RSS");
2674 if (usbsts & STS_SRE)
2675 ret += sprintf(str + ret, " SRE");
2676 if (usbsts & STS_CNR)
2677 ret += sprintf(str + ret, " CNR");
2678 if (usbsts & STS_HCE)
2679 ret += sprintf(str + ret, " HCE");
2680
2681 return str;
2682}
2683
2684static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2685{
2686 u8 ep;
2687 u16 stream;
2688 int ret;
2689
2690 ep = (doorbell & 0xff);
2691 stream = doorbell >> 16;
2692
2693 if (slot == 0) {
2694 sprintf(str, "Command Ring %d", doorbell);
2695 return str;
2696 }
2697 ret = sprintf(str, "Slot %d ", slot);
2698 if (ep > 0 && ep < 32)
2699 ret = sprintf(str + ret, "ep%d%s",
2700 ep / 2,
2701 ep % 2 ? "in" : "out");
2702 else if (ep == 0 || ep < 248)
2703 ret = sprintf(str + ret, "Reserved %d", ep);
2704 else
2705 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2706 if (stream)
2707 ret = sprintf(str + ret, " Stream %d", stream);
2708
2709 return str;
2710}
2711
2712static inline const char *xhci_ep_state_string(u8 state)
2713{
2714 switch (state) {
2715 case EP_STATE_DISABLED:
2716 return "disabled";
2717 case EP_STATE_RUNNING:
2718 return "running";
2719 case EP_STATE_HALTED:
2720 return "halted";
2721 case EP_STATE_STOPPED:
2722 return "stopped";
2723 case EP_STATE_ERROR:
2724 return "error";
2725 default:
2726 return "INVALID";
2727 }
2728}
2729
2730static inline const char *xhci_ep_type_string(u8 type)
2731{
2732 switch (type) {
2733 case ISOC_OUT_EP:
2734 return "Isoc OUT";
2735 case BULK_OUT_EP:
2736 return "Bulk OUT";
2737 case INT_OUT_EP:
2738 return "Int OUT";
2739 case CTRL_EP:
2740 return "Ctrl";
2741 case ISOC_IN_EP:
2742 return "Isoc IN";
2743 case BULK_IN_EP:
2744 return "Bulk IN";
2745 case INT_IN_EP:
2746 return "Int IN";
2747 default:
2748 return "INVALID";
2749 }
2750}
2751
2752static inline const char *xhci_decode_ep_context(char *str, u32 info,
2753 u32 info2, u64 deq, u32 tx_info)
2754{
2755 int ret;
2756
2757 u32 esit;
2758 u16 maxp;
2759 u16 avg;
2760
2761 u8 max_pstr;
2762 u8 ep_state;
2763 u8 interval;
2764 u8 ep_type;
2765 u8 burst;
2766 u8 cerr;
2767 u8 mult;
2768
2769 bool lsa;
2770 bool hid;
2771
2772 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2773 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2774
2775 ep_state = info & EP_STATE_MASK;
2776 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2777 interval = CTX_TO_EP_INTERVAL(info);
2778 mult = CTX_TO_EP_MULT(info) + 1;
2779 lsa = !!(info & EP_HAS_LSA);
2780
2781 cerr = (info2 & (3 << 1)) >> 1;
2782 ep_type = CTX_TO_EP_TYPE(info2);
2783 hid = !!(info2 & (1 << 7));
2784 burst = CTX_TO_MAX_BURST(info2);
2785 maxp = MAX_PACKET_DECODED(info2);
2786
2787 avg = EP_AVG_TRB_LENGTH(tx_info);
2788
2789 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2790 xhci_ep_state_string(ep_state), mult,
2791 max_pstr, lsa ? "LSA " : "");
2792
2793 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2794 (1 << interval) * 125, esit, cerr);
2795
2796 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2797 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2798 burst, maxp, deq);
2799
2800 ret += sprintf(str + ret, "avg trb len %d", avg);
2801
2802 return str;
2803}
2804
2805#endif /* __LINUX_XHCI_HCD_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20#include <linux/io-64-nonatomic-hi-lo.h>
21
22/* Code sharing between pci-quirks and xhci hcd */
23#include "xhci-ext-caps.h"
24#include "pci-quirks.h"
25
26#include "xhci-port.h"
27#include "xhci-caps.h"
28
29/* max buffer size for trace and debug messages */
30#define XHCI_MSG_MAX 500
31
32/* xHCI PCI Configuration Registers */
33#define XHCI_SBRN_OFFSET (0x60)
34
35/* Max number of USB devices for any host controller - limit in section 6.1 */
36#define MAX_HC_SLOTS 256
37/* Section 5.3.3 - MaxPorts */
38#define MAX_HC_PORTS 127
39
40/*
41 * xHCI register interface.
42 * This corresponds to the eXtensible Host Controller Interface (xHCI)
43 * Revision 0.95 specification
44 */
45
46/**
47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
48 * @hc_capbase: length of the capabilities register and HC version number
49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
52 * @hcc_params: HCCPARAMS - Capability Parameters
53 * @db_off: DBOFF - Doorbell array offset
54 * @run_regs_off: RTSOFF - Runtime register space offset
55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
56 */
57struct xhci_cap_regs {
58 __le32 hc_capbase;
59 __le32 hcs_params1;
60 __le32 hcs_params2;
61 __le32 hcs_params3;
62 __le32 hcc_params;
63 __le32 db_off;
64 __le32 run_regs_off;
65 __le32 hcc_params2; /* xhci 1.1 */
66 /* Reserved up to (CAPLENGTH - 0x1C) */
67};
68
69/* Number of registers per port */
70#define NUM_PORT_REGS 4
71
72#define PORTSC 0
73#define PORTPMSC 1
74#define PORTLI 2
75#define PORTHLPMC 3
76
77/**
78 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
79 * @command: USBCMD - xHC command register
80 * @status: USBSTS - xHC status register
81 * @page_size: This indicates the page size that the host controller
82 * supports. If bit n is set, the HC supports a page size
83 * of 2^(n+12), up to a 128MB page size.
84 * 4K is the minimum page size.
85 * @cmd_ring: CRP - 64-bit Command Ring Pointer
86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
87 * @config_reg: CONFIG - Configure Register
88 * @port_status_base: PORTSCn - base address for Port Status and Control
89 * Each port has a Port Status and Control register,
90 * followed by a Port Power Management Status and Control
91 * register, a Port Link Info register, and a reserved
92 * register.
93 * @port_power_base: PORTPMSCn - base address for
94 * Port Power Management Status and Control
95 * @port_link_base: PORTLIn - base address for Port Link Info (current
96 * Link PM state and control) for USB 2.1 and USB 3.0
97 * devices.
98 */
99struct xhci_op_regs {
100 __le32 command;
101 __le32 status;
102 __le32 page_size;
103 __le32 reserved1;
104 __le32 reserved2;
105 __le32 dev_notification;
106 __le64 cmd_ring;
107 /* rsvd: offset 0x20-2F */
108 __le32 reserved3[4];
109 __le64 dcbaa_ptr;
110 __le32 config_reg;
111 /* rsvd: offset 0x3C-3FF */
112 __le32 reserved4[241];
113 /* port 1 registers, which serve as a base address for other ports */
114 __le32 port_status_base;
115 __le32 port_power_base;
116 __le32 port_link_base;
117 __le32 reserved5;
118 /* registers for ports 2-255 */
119 __le32 reserved6[NUM_PORT_REGS*254];
120};
121
122/* USBCMD - USB command - command bitmasks */
123/* start/stop HC execution - do not write unless HC is halted*/
124#define CMD_RUN XHCI_CMD_RUN
125/* Reset HC - resets internal HC state machine and all registers (except
126 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
127 * The xHCI driver must reinitialize the xHC after setting this bit.
128 */
129#define CMD_RESET (1 << 1)
130/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
131#define CMD_EIE XHCI_CMD_EIE
132/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
133#define CMD_HSEIE XHCI_CMD_HSEIE
134/* bits 4:6 are reserved (and should be preserved on writes). */
135/* light reset (port status stays unchanged) - reset completed when this is 0 */
136#define CMD_LRESET (1 << 7)
137/* host controller save/restore state. */
138#define CMD_CSS (1 << 8)
139#define CMD_CRS (1 << 9)
140/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
141#define CMD_EWE XHCI_CMD_EWE
142/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
144 * '0' means the xHC can power it off if all ports are in the disconnect,
145 * disabled, or powered-off state.
146 */
147#define CMD_PM_INDEX (1 << 11)
148/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
149#define CMD_ETE (1 << 14)
150/* bits 15:31 are reserved (and should be preserved on writes). */
151
152#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
153#define XHCI_RESET_SHORT_USEC (250 * 1000)
154
155/* IMAN - Interrupt Management Register */
156#define IMAN_IE (1 << 1)
157#define IMAN_IP (1 << 0)
158
159/* USBSTS - USB status - status bitmasks */
160/* HC not running - set to 1 when run/stop bit is cleared. */
161#define STS_HALT XHCI_STS_HALT
162/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
163#define STS_FATAL (1 << 2)
164/* event interrupt - clear this prior to clearing any IP flags in IR set*/
165#define STS_EINT (1 << 3)
166/* port change detect */
167#define STS_PORT (1 << 4)
168/* bits 5:7 reserved and zeroed */
169/* save state status - '1' means xHC is saving state */
170#define STS_SAVE (1 << 8)
171/* restore state status - '1' means xHC is restoring state */
172#define STS_RESTORE (1 << 9)
173/* true: save or restore error */
174#define STS_SRE (1 << 10)
175/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
176#define STS_CNR XHCI_STS_CNR
177/* true: internal Host Controller Error - SW needs to reset and reinitialize */
178#define STS_HCE (1 << 12)
179/* bits 13:31 reserved and should be preserved */
180
181/*
182 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
183 * Generate a device notification event when the HC sees a transaction with a
184 * notification type that matches a bit set in this bit field.
185 */
186#define DEV_NOTE_MASK (0xffff)
187#define ENABLE_DEV_NOTE(x) (1 << (x))
188/* Most of the device notification types should only be used for debug.
189 * SW does need to pay attention to function wake notifications.
190 */
191#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
192
193/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
194/* bit 0 is the command ring cycle state */
195/* stop ring operation after completion of the currently executing command */
196#define CMD_RING_PAUSE (1 << 1)
197/* stop ring immediately - abort the currently executing command */
198#define CMD_RING_ABORT (1 << 2)
199/* true: command ring is running */
200#define CMD_RING_RUNNING (1 << 3)
201/* bits 4:5 reserved and should be preserved */
202/* Command Ring pointer - bit mask for the lower 32 bits. */
203#define CMD_RING_RSVD_BITS (0x3f)
204
205/* CONFIG - Configure Register - config_reg bitmasks */
206/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
207#define MAX_DEVS(p) ((p) & 0xff)
208/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
209#define CONFIG_U3E (1 << 8)
210/* bit 9: Configuration Information Enable, xhci 1.1 */
211#define CONFIG_CIE (1 << 9)
212/* bits 10:31 - reserved and should be preserved */
213
214/**
215 * struct xhci_intr_reg - Interrupt Register Set
216 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
217 * interrupts and check for pending interrupts.
218 * @irq_control: IMOD - Interrupt Moderation Register.
219 * Used to throttle interrupts.
220 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
221 * @erst_base: ERST base address.
222 * @erst_dequeue: Event ring dequeue pointer.
223 *
224 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
225 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
226 * multiple segments of the same size. The HC places events on the ring and
227 * "updates the Cycle bit in the TRBs to indicate to software the current
228 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
229 * updates the dequeue pointer.
230 */
231struct xhci_intr_reg {
232 __le32 irq_pending;
233 __le32 irq_control;
234 __le32 erst_size;
235 __le32 rsvd;
236 __le64 erst_base;
237 __le64 erst_dequeue;
238};
239
240/* irq_pending bitmasks */
241#define ER_IRQ_PENDING(p) ((p) & 0x1)
242/* bits 2:31 need to be preserved */
243/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
244#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
245#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
246#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
247
248/* irq_control bitmasks */
249/* Minimum interval between interrupts (in 250ns intervals). The interval
250 * between interrupts will be longer if there are no events on the event ring.
251 * Default is 4000 (1 ms).
252 */
253#define ER_IRQ_INTERVAL_MASK (0xffff)
254/* Counter used to count down the time to the next interrupt - HW use only */
255#define ER_IRQ_COUNTER_MASK (0xffff << 16)
256
257/* erst_size bitmasks */
258/* Preserve bits 16:31 of erst_size */
259#define ERST_SIZE_MASK (0xffff << 16)
260
261/* erst_base bitmasks */
262#define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
263
264/* erst_dequeue bitmasks */
265/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
266 * where the current dequeue pointer lies. This is an optional HW hint.
267 */
268#define ERST_DESI_MASK (0x7)
269/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
270 * a work queue (or delayed service routine)?
271 */
272#define ERST_EHB (1 << 3)
273#define ERST_PTR_MASK (GENMASK_ULL(63, 4))
274
275/**
276 * struct xhci_run_regs
277 * @microframe_index:
278 * MFINDEX - current microframe number
279 *
280 * Section 5.5 Host Controller Runtime Registers:
281 * "Software should read and write these registers using only Dword (32 bit)
282 * or larger accesses"
283 */
284struct xhci_run_regs {
285 __le32 microframe_index;
286 __le32 rsvd[7];
287 struct xhci_intr_reg ir_set[128];
288};
289
290/**
291 * struct doorbell_array
292 *
293 * Bits 0 - 7: Endpoint target
294 * Bits 8 - 15: RsvdZ
295 * Bits 16 - 31: Stream ID
296 *
297 * Section 5.6
298 */
299struct xhci_doorbell_array {
300 __le32 doorbell[256];
301};
302
303#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
304#define DB_VALUE_HOST 0x00000000
305
306#define PLT_MASK (0x03 << 6)
307#define PLT_SYM (0x00 << 6)
308#define PLT_ASYM_RX (0x02 << 6)
309#define PLT_ASYM_TX (0x03 << 6)
310
311/**
312 * struct xhci_container_ctx
313 * @type: Type of context. Used to calculated offsets to contained contexts.
314 * @size: Size of the context data
315 * @bytes: The raw context data given to HW
316 * @dma: dma address of the bytes
317 *
318 * Represents either a Device or Input context. Holds a pointer to the raw
319 * memory used for the context (bytes) and dma address of it (dma).
320 */
321struct xhci_container_ctx {
322 unsigned type;
323#define XHCI_CTX_TYPE_DEVICE 0x1
324#define XHCI_CTX_TYPE_INPUT 0x2
325
326 int size;
327
328 u8 *bytes;
329 dma_addr_t dma;
330};
331
332/**
333 * struct xhci_slot_ctx
334 * @dev_info: Route string, device speed, hub info, and last valid endpoint
335 * @dev_info2: Max exit latency for device number, root hub port number
336 * @tt_info: tt_info is used to construct split transaction tokens
337 * @dev_state: slot state and device address
338 *
339 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
340 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
341 * reserved at the end of the slot context for HC internal use.
342 */
343struct xhci_slot_ctx {
344 __le32 dev_info;
345 __le32 dev_info2;
346 __le32 tt_info;
347 __le32 dev_state;
348 /* offset 0x10 to 0x1f reserved for HC internal use */
349 __le32 reserved[4];
350};
351
352/* dev_info bitmasks */
353/* Route String - 0:19 */
354#define ROUTE_STRING_MASK (0xfffff)
355/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
356#define DEV_SPEED (0xf << 20)
357#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
358/* bit 24 reserved */
359/* Is this LS/FS device connected through a HS hub? - bit 25 */
360#define DEV_MTT (0x1 << 25)
361/* Set if the device is a hub - bit 26 */
362#define DEV_HUB (0x1 << 26)
363/* Index of the last valid endpoint context in this device context - 27:31 */
364#define LAST_CTX_MASK (0x1f << 27)
365#define LAST_CTX(p) ((p) << 27)
366#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
367#define SLOT_FLAG (1 << 0)
368#define EP0_FLAG (1 << 1)
369
370/* dev_info2 bitmasks */
371/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
372#define MAX_EXIT (0xffff)
373/* Root hub port number that is needed to access the USB device */
374#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
375#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
376/* Maximum number of ports under a hub device */
377#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
378#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
379
380/* tt_info bitmasks */
381/*
382 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
383 * The Slot ID of the hub that isolates the high speed signaling from
384 * this low or full-speed device. '0' if attached to root hub port.
385 */
386#define TT_SLOT (0xff)
387/*
388 * The number of the downstream facing port of the high-speed hub
389 * '0' if the device is not low or full speed.
390 */
391#define TT_PORT (0xff << 8)
392#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
393#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
394
395/* dev_state bitmasks */
396/* USB device address - assigned by the HC */
397#define DEV_ADDR_MASK (0xff)
398/* bits 8:26 reserved */
399/* Slot state */
400#define SLOT_STATE (0x1f << 27)
401#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
402
403#define SLOT_STATE_DISABLED 0
404#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
405#define SLOT_STATE_DEFAULT 1
406#define SLOT_STATE_ADDRESSED 2
407#define SLOT_STATE_CONFIGURED 3
408
409/**
410 * struct xhci_ep_ctx
411 * @ep_info: endpoint state, streams, mult, and interval information.
412 * @ep_info2: information on endpoint type, max packet size, max burst size,
413 * error count, and whether the HC will force an event for all
414 * transactions.
415 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
416 * defines one stream, this points to the endpoint transfer ring.
417 * Otherwise, it points to a stream context array, which has a
418 * ring pointer for each flow.
419 * @tx_info:
420 * Average TRB lengths for the endpoint ring and
421 * max payload within an Endpoint Service Interval Time (ESIT).
422 *
423 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
424 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
425 * reserved at the end of the endpoint context for HC internal use.
426 */
427struct xhci_ep_ctx {
428 __le32 ep_info;
429 __le32 ep_info2;
430 __le64 deq;
431 __le32 tx_info;
432 /* offset 0x14 - 0x1f reserved for HC internal use */
433 __le32 reserved[3];
434};
435
436/* ep_info bitmasks */
437/*
438 * Endpoint State - bits 0:2
439 * 0 - disabled
440 * 1 - running
441 * 2 - halted due to halt condition - ok to manipulate endpoint ring
442 * 3 - stopped
443 * 4 - TRB error
444 * 5-7 - reserved
445 */
446#define EP_STATE_MASK (0x7)
447#define EP_STATE_DISABLED 0
448#define EP_STATE_RUNNING 1
449#define EP_STATE_HALTED 2
450#define EP_STATE_STOPPED 3
451#define EP_STATE_ERROR 4
452#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
453
454/* Mult - Max number of burtst within an interval, in EP companion desc. */
455#define EP_MULT(p) (((p) & 0x3) << 8)
456#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
457/* bits 10:14 are Max Primary Streams */
458/* bit 15 is Linear Stream Array */
459/* Interval - period between requests to an endpoint - 125u increments. */
460#define EP_INTERVAL(p) (((p) & 0xff) << 16)
461#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
462#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
463#define EP_MAXPSTREAMS_MASK (0x1f << 10)
464#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
465#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
466/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
467#define EP_HAS_LSA (1 << 15)
468/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
469#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
470
471/* ep_info2 bitmasks */
472/*
473 * Force Event - generate transfer events for all TRBs for this endpoint
474 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
475 */
476#define FORCE_EVENT (0x1)
477#define ERROR_COUNT(p) (((p) & 0x3) << 1)
478#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
479#define EP_TYPE(p) ((p) << 3)
480#define ISOC_OUT_EP 1
481#define BULK_OUT_EP 2
482#define INT_OUT_EP 3
483#define CTRL_EP 4
484#define ISOC_IN_EP 5
485#define BULK_IN_EP 6
486#define INT_IN_EP 7
487/* bit 6 reserved */
488/* bit 7 is Host Initiate Disable - for disabling stream selection */
489#define MAX_BURST(p) (((p)&0xff) << 8)
490#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
491#define MAX_PACKET(p) (((p)&0xffff) << 16)
492#define MAX_PACKET_MASK (0xffff << 16)
493#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
494
495/* tx_info bitmasks */
496#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
497#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
498#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
499#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
500
501/* deq bitmasks */
502#define EP_CTX_CYCLE_MASK (1 << 0)
503#define SCTX_DEQ_MASK (~0xfL)
504
505
506/**
507 * struct xhci_input_control_context
508 * Input control context; see section 6.2.5.
509 *
510 * @drop_context: set the bit of the endpoint context you want to disable
511 * @add_context: set the bit of the endpoint context you want to enable
512 */
513struct xhci_input_control_ctx {
514 __le32 drop_flags;
515 __le32 add_flags;
516 __le32 rsvd2[6];
517};
518
519#define EP_IS_ADDED(ctrl_ctx, i) \
520 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
521#define EP_IS_DROPPED(ctrl_ctx, i) \
522 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
523
524/* Represents everything that is needed to issue a command on the command ring.
525 * It's useful to pre-allocate these for commands that cannot fail due to
526 * out-of-memory errors, like freeing streams.
527 */
528struct xhci_command {
529 /* Input context for changing device state */
530 struct xhci_container_ctx *in_ctx;
531 u32 status;
532 int slot_id;
533 /* If completion is null, no one is waiting on this command
534 * and the structure can be freed after the command completes.
535 */
536 struct completion *completion;
537 union xhci_trb *command_trb;
538 struct list_head cmd_list;
539 /* xHCI command response timeout in milliseconds */
540 unsigned int timeout_ms;
541};
542
543/* drop context bitmasks */
544#define DROP_EP(x) (0x1 << x)
545/* add context bitmasks */
546#define ADD_EP(x) (0x1 << x)
547
548struct xhci_stream_ctx {
549 /* 64-bit stream ring address, cycle state, and stream type */
550 __le64 stream_ring;
551 /* offset 0x14 - 0x1f reserved for HC internal use */
552 __le32 reserved[2];
553};
554
555/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
556#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
557#define CTX_TO_SCT(p) (((p) >> 1) & 0x7)
558/* Secondary stream array type, dequeue pointer is to a transfer ring */
559#define SCT_SEC_TR 0
560/* Primary stream array type, dequeue pointer is to a transfer ring */
561#define SCT_PRI_TR 1
562/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
563#define SCT_SSA_8 2
564#define SCT_SSA_16 3
565#define SCT_SSA_32 4
566#define SCT_SSA_64 5
567#define SCT_SSA_128 6
568#define SCT_SSA_256 7
569
570/* Assume no secondary streams for now */
571struct xhci_stream_info {
572 struct xhci_ring **stream_rings;
573 /* Number of streams, including stream 0 (which drivers can't use) */
574 unsigned int num_streams;
575 /* The stream context array may be bigger than
576 * the number of streams the driver asked for
577 */
578 struct xhci_stream_ctx *stream_ctx_array;
579 unsigned int num_stream_ctxs;
580 dma_addr_t ctx_array_dma;
581 /* For mapping physical TRB addresses to segments in stream rings */
582 struct radix_tree_root trb_address_map;
583 struct xhci_command *free_streams_command;
584};
585
586#define SMALL_STREAM_ARRAY_SIZE 256
587#define MEDIUM_STREAM_ARRAY_SIZE 1024
588
589/* Some Intel xHCI host controllers need software to keep track of the bus
590 * bandwidth. Keep track of endpoint info here. Each root port is allocated
591 * the full bus bandwidth. We must also treat TTs (including each port under a
592 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
593 * (DMI) also limits the total bandwidth (across all domains) that can be used.
594 */
595struct xhci_bw_info {
596 /* ep_interval is zero-based */
597 unsigned int ep_interval;
598 /* mult and num_packets are one-based */
599 unsigned int mult;
600 unsigned int num_packets;
601 unsigned int max_packet_size;
602 unsigned int max_esit_payload;
603 unsigned int type;
604};
605
606/* "Block" sizes in bytes the hardware uses for different device speeds.
607 * The logic in this part of the hardware limits the number of bits the hardware
608 * can use, so must represent bandwidth in a less precise manner to mimic what
609 * the scheduler hardware computes.
610 */
611#define FS_BLOCK 1
612#define HS_BLOCK 4
613#define SS_BLOCK 16
614#define DMI_BLOCK 32
615
616/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
617 * with each byte transferred. SuperSpeed devices have an initial overhead to
618 * set up bursts. These are in blocks, see above. LS overhead has already been
619 * translated into FS blocks.
620 */
621#define DMI_OVERHEAD 8
622#define DMI_OVERHEAD_BURST 4
623#define SS_OVERHEAD 8
624#define SS_OVERHEAD_BURST 32
625#define HS_OVERHEAD 26
626#define FS_OVERHEAD 20
627#define LS_OVERHEAD 128
628/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
629 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
630 * of overhead associated with split transfers crossing microframe boundaries.
631 * 31 blocks is pure protocol overhead.
632 */
633#define TT_HS_OVERHEAD (31 + 94)
634#define TT_DMI_OVERHEAD (25 + 12)
635
636/* Bandwidth limits in blocks */
637#define FS_BW_LIMIT 1285
638#define TT_BW_LIMIT 1320
639#define HS_BW_LIMIT 1607
640#define SS_BW_LIMIT_IN 3906
641#define DMI_BW_LIMIT_IN 3906
642#define SS_BW_LIMIT_OUT 3906
643#define DMI_BW_LIMIT_OUT 3906
644
645/* Percentage of bus bandwidth reserved for non-periodic transfers */
646#define FS_BW_RESERVED 10
647#define HS_BW_RESERVED 20
648#define SS_BW_RESERVED 10
649
650struct xhci_virt_ep {
651 struct xhci_virt_device *vdev; /* parent */
652 unsigned int ep_index;
653 struct xhci_ring *ring;
654 /* Related to endpoints that are configured to use stream IDs only */
655 struct xhci_stream_info *stream_info;
656 /* Temporary storage in case the configure endpoint command fails and we
657 * have to restore the device state to the previous state
658 */
659 struct xhci_ring *new_ring;
660 unsigned int err_count;
661 unsigned int ep_state;
662#define SET_DEQ_PENDING (1 << 0)
663#define EP_HALTED (1 << 1) /* For stall handling */
664#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
665/* Transitioning the endpoint to using streams, don't enqueue URBs */
666#define EP_GETTING_STREAMS (1 << 3)
667#define EP_HAS_STREAMS (1 << 4)
668/* Transitioning the endpoint to not using streams, don't enqueue URBs */
669#define EP_GETTING_NO_STREAMS (1 << 5)
670#define EP_HARD_CLEAR_TOGGLE (1 << 6)
671#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
672/* usb_hub_clear_tt_buffer is in progress */
673#define EP_CLEARING_TT (1 << 8)
674 /* ---- Related to URB cancellation ---- */
675 struct list_head cancelled_td_list;
676 struct xhci_hcd *xhci;
677 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
678 * command. We'll need to update the ring's dequeue segment and dequeue
679 * pointer after the command completes.
680 */
681 struct xhci_segment *queued_deq_seg;
682 union xhci_trb *queued_deq_ptr;
683 /*
684 * Sometimes the xHC can not process isochronous endpoint ring quickly
685 * enough, and it will miss some isoc tds on the ring and generate
686 * a Missed Service Error Event.
687 * Set skip flag when receive a Missed Service Error Event and
688 * process the missed tds on the endpoint ring.
689 */
690 bool skip;
691 /* Bandwidth checking storage */
692 struct xhci_bw_info bw_info;
693 struct list_head bw_endpoint_list;
694 unsigned long stop_time;
695 /* Isoch Frame ID checking storage */
696 int next_frame_id;
697 /* Use new Isoch TRB layout needed for extended TBC support */
698 bool use_extended_tbc;
699};
700
701enum xhci_overhead_type {
702 LS_OVERHEAD_TYPE = 0,
703 FS_OVERHEAD_TYPE,
704 HS_OVERHEAD_TYPE,
705};
706
707struct xhci_interval_bw {
708 unsigned int num_packets;
709 /* Sorted by max packet size.
710 * Head of the list is the greatest max packet size.
711 */
712 struct list_head endpoints;
713 /* How many endpoints of each speed are present. */
714 unsigned int overhead[3];
715};
716
717#define XHCI_MAX_INTERVAL 16
718
719struct xhci_interval_bw_table {
720 unsigned int interval0_esit_payload;
721 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
722 /* Includes reserved bandwidth for async endpoints */
723 unsigned int bw_used;
724 unsigned int ss_bw_in;
725 unsigned int ss_bw_out;
726};
727
728#define EP_CTX_PER_DEV 31
729
730struct xhci_virt_device {
731 int slot_id;
732 struct usb_device *udev;
733 /*
734 * Commands to the hardware are passed an "input context" that
735 * tells the hardware what to change in its data structures.
736 * The hardware will return changes in an "output context" that
737 * software must allocate for the hardware. We need to keep
738 * track of input and output contexts separately because
739 * these commands might fail and we don't trust the hardware.
740 */
741 struct xhci_container_ctx *out_ctx;
742 /* Used for addressing devices and configuration changes */
743 struct xhci_container_ctx *in_ctx;
744 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
745 struct xhci_port *rhub_port;
746 struct xhci_interval_bw_table *bw_table;
747 struct xhci_tt_bw_info *tt_info;
748 /*
749 * flags for state tracking based on events and issued commands.
750 * Software can not rely on states from output contexts because of
751 * latency between events and xHC updating output context values.
752 * See xhci 1.1 section 4.8.3 for more details
753 */
754 unsigned long flags;
755#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
756
757 /* The current max exit latency for the enabled USB3 link states. */
758 u16 current_mel;
759 /* Used for the debugfs interfaces. */
760 void *debugfs_private;
761};
762
763/*
764 * For each roothub, keep track of the bandwidth information for each periodic
765 * interval.
766 *
767 * If a high speed hub is attached to the roothub, each TT associated with that
768 * hub is a separate bandwidth domain. The interval information for the
769 * endpoints on the devices under that TT will appear in the TT structure.
770 */
771struct xhci_root_port_bw_info {
772 struct list_head tts;
773 unsigned int num_active_tts;
774 struct xhci_interval_bw_table bw_table;
775};
776
777struct xhci_tt_bw_info {
778 struct list_head tt_list;
779 int slot_id;
780 int ttport;
781 struct xhci_interval_bw_table bw_table;
782 int active_eps;
783};
784
785
786/**
787 * struct xhci_device_context_array
788 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
789 */
790struct xhci_device_context_array {
791 /* 64-bit device addresses; we only write 32-bit addresses */
792 __le64 dev_context_ptrs[MAX_HC_SLOTS];
793 /* private xHCD pointers */
794 dma_addr_t dma;
795};
796/* TODO: write function to set the 64-bit device DMA address */
797/*
798 * TODO: change this to be dynamically sized at HC mem init time since the HC
799 * might not be able to handle the maximum number of devices possible.
800 */
801
802
803struct xhci_transfer_event {
804 /* 64-bit buffer address, or immediate data */
805 __le64 buffer;
806 __le32 transfer_len;
807 /* This field is interpreted differently based on the type of TRB */
808 __le32 flags;
809};
810
811/* Transfer event flags bitfield, also for select command completion events */
812#define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff)
813#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
814
815#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */
816#define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16)
817
818#define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */
819#define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
820
821/* Transfer event TRB length bit mask */
822#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
823
824/* Completion Code - only applicable for some types of TRBs */
825#define COMP_CODE_MASK (0xff << 24)
826#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
827#define COMP_INVALID 0
828#define COMP_SUCCESS 1
829#define COMP_DATA_BUFFER_ERROR 2
830#define COMP_BABBLE_DETECTED_ERROR 3
831#define COMP_USB_TRANSACTION_ERROR 4
832#define COMP_TRB_ERROR 5
833#define COMP_STALL_ERROR 6
834#define COMP_RESOURCE_ERROR 7
835#define COMP_BANDWIDTH_ERROR 8
836#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
837#define COMP_INVALID_STREAM_TYPE_ERROR 10
838#define COMP_SLOT_NOT_ENABLED_ERROR 11
839#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
840#define COMP_SHORT_PACKET 13
841#define COMP_RING_UNDERRUN 14
842#define COMP_RING_OVERRUN 15
843#define COMP_VF_EVENT_RING_FULL_ERROR 16
844#define COMP_PARAMETER_ERROR 17
845#define COMP_BANDWIDTH_OVERRUN_ERROR 18
846#define COMP_CONTEXT_STATE_ERROR 19
847#define COMP_NO_PING_RESPONSE_ERROR 20
848#define COMP_EVENT_RING_FULL_ERROR 21
849#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
850#define COMP_MISSED_SERVICE_ERROR 23
851#define COMP_COMMAND_RING_STOPPED 24
852#define COMP_COMMAND_ABORTED 25
853#define COMP_STOPPED 26
854#define COMP_STOPPED_LENGTH_INVALID 27
855#define COMP_STOPPED_SHORT_PACKET 28
856#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
857#define COMP_ISOCH_BUFFER_OVERRUN 31
858#define COMP_EVENT_LOST_ERROR 32
859#define COMP_UNDEFINED_ERROR 33
860#define COMP_INVALID_STREAM_ID_ERROR 34
861#define COMP_SECONDARY_BANDWIDTH_ERROR 35
862#define COMP_SPLIT_TRANSACTION_ERROR 36
863
864static inline const char *xhci_trb_comp_code_string(u8 status)
865{
866 switch (status) {
867 case COMP_INVALID:
868 return "Invalid";
869 case COMP_SUCCESS:
870 return "Success";
871 case COMP_DATA_BUFFER_ERROR:
872 return "Data Buffer Error";
873 case COMP_BABBLE_DETECTED_ERROR:
874 return "Babble Detected";
875 case COMP_USB_TRANSACTION_ERROR:
876 return "USB Transaction Error";
877 case COMP_TRB_ERROR:
878 return "TRB Error";
879 case COMP_STALL_ERROR:
880 return "Stall Error";
881 case COMP_RESOURCE_ERROR:
882 return "Resource Error";
883 case COMP_BANDWIDTH_ERROR:
884 return "Bandwidth Error";
885 case COMP_NO_SLOTS_AVAILABLE_ERROR:
886 return "No Slots Available Error";
887 case COMP_INVALID_STREAM_TYPE_ERROR:
888 return "Invalid Stream Type Error";
889 case COMP_SLOT_NOT_ENABLED_ERROR:
890 return "Slot Not Enabled Error";
891 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
892 return "Endpoint Not Enabled Error";
893 case COMP_SHORT_PACKET:
894 return "Short Packet";
895 case COMP_RING_UNDERRUN:
896 return "Ring Underrun";
897 case COMP_RING_OVERRUN:
898 return "Ring Overrun";
899 case COMP_VF_EVENT_RING_FULL_ERROR:
900 return "VF Event Ring Full Error";
901 case COMP_PARAMETER_ERROR:
902 return "Parameter Error";
903 case COMP_BANDWIDTH_OVERRUN_ERROR:
904 return "Bandwidth Overrun Error";
905 case COMP_CONTEXT_STATE_ERROR:
906 return "Context State Error";
907 case COMP_NO_PING_RESPONSE_ERROR:
908 return "No Ping Response Error";
909 case COMP_EVENT_RING_FULL_ERROR:
910 return "Event Ring Full Error";
911 case COMP_INCOMPATIBLE_DEVICE_ERROR:
912 return "Incompatible Device Error";
913 case COMP_MISSED_SERVICE_ERROR:
914 return "Missed Service Error";
915 case COMP_COMMAND_RING_STOPPED:
916 return "Command Ring Stopped";
917 case COMP_COMMAND_ABORTED:
918 return "Command Aborted";
919 case COMP_STOPPED:
920 return "Stopped";
921 case COMP_STOPPED_LENGTH_INVALID:
922 return "Stopped - Length Invalid";
923 case COMP_STOPPED_SHORT_PACKET:
924 return "Stopped - Short Packet";
925 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
926 return "Max Exit Latency Too Large Error";
927 case COMP_ISOCH_BUFFER_OVERRUN:
928 return "Isoch Buffer Overrun";
929 case COMP_EVENT_LOST_ERROR:
930 return "Event Lost Error";
931 case COMP_UNDEFINED_ERROR:
932 return "Undefined Error";
933 case COMP_INVALID_STREAM_ID_ERROR:
934 return "Invalid Stream ID Error";
935 case COMP_SECONDARY_BANDWIDTH_ERROR:
936 return "Secondary Bandwidth Error";
937 case COMP_SPLIT_TRANSACTION_ERROR:
938 return "Split Transaction Error";
939 default:
940 return "Unknown!!";
941 }
942}
943
944struct xhci_link_trb {
945 /* 64-bit segment pointer*/
946 __le64 segment_ptr;
947 __le32 intr_target;
948 __le32 control;
949};
950
951/* control bitfields */
952#define LINK_TOGGLE (0x1<<1)
953
954/* Command completion event TRB */
955struct xhci_event_cmd {
956 /* Pointer to command TRB, or the value passed by the event data trb */
957 __le64 cmd_trb;
958 __le32 status;
959 __le32 flags;
960};
961
962/* Address device - disable SetAddress */
963#define TRB_BSR (1<<9)
964
965/* Configure Endpoint - Deconfigure */
966#define TRB_DC (1<<9)
967
968/* Stop Ring - Transfer State Preserve */
969#define TRB_TSP (1<<9)
970
971enum xhci_ep_reset_type {
972 EP_HARD_RESET,
973 EP_SOFT_RESET,
974};
975
976/* Force Event */
977#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
978#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
979
980/* Set Latency Tolerance Value */
981#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
982
983/* Get Port Bandwidth */
984#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
985
986/* Force Header */
987#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
988#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
989
990enum xhci_setup_dev {
991 SETUP_CONTEXT_ONLY,
992 SETUP_CONTEXT_ADDRESS,
993};
994
995/* bits 16:23 are the virtual function ID */
996/* bits 24:31 are the slot ID */
997
998/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
999#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1000#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1001#define LAST_EP_INDEX 30
1002
1003/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1004#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1005#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1006#define SCT_FOR_TRB(p) (((p) & 0x7) << 1)
1007
1008/* Link TRB specific fields */
1009#define TRB_TC (1<<1)
1010
1011/* Port Status Change Event TRB fields */
1012/* Port ID - bits 31:24 */
1013#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1014
1015#define EVENT_DATA (1 << 2)
1016
1017/* Normal TRB fields */
1018/* transfer_len bitmasks - bits 0:16 */
1019#define TRB_LEN(p) ((p) & 0x1ffff)
1020/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1021#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1022#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1023/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1024#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1025/* Interrupter Target - which MSI-X vector to target the completion event at */
1026#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1027#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1028
1029/* Cycle bit - indicates TRB ownership by HC or HCD */
1030#define TRB_CYCLE (1<<0)
1031/*
1032 * Force next event data TRB to be evaluated before task switch.
1033 * Used to pass OS data back after a TD completes.
1034 */
1035#define TRB_ENT (1<<1)
1036/* Interrupt on short packet */
1037#define TRB_ISP (1<<2)
1038/* Set PCIe no snoop attribute */
1039#define TRB_NO_SNOOP (1<<3)
1040/* Chain multiple TRBs into a TD */
1041#define TRB_CHAIN (1<<4)
1042/* Interrupt on completion */
1043#define TRB_IOC (1<<5)
1044/* The buffer pointer contains immediate data */
1045#define TRB_IDT (1<<6)
1046/* TDs smaller than this might use IDT */
1047#define TRB_IDT_MAX_SIZE 8
1048
1049/* Block Event Interrupt */
1050#define TRB_BEI (1<<9)
1051
1052/* Control transfer TRB specific fields */
1053#define TRB_DIR_IN (1<<16)
1054#define TRB_TX_TYPE(p) ((p) << 16)
1055#define TRB_DATA_OUT 2
1056#define TRB_DATA_IN 3
1057
1058/* Isochronous TRB specific fields */
1059#define TRB_SIA (1<<31)
1060#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1061#define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff)
1062/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1063#define TRB_TBC(p) (((p) & 0x3) << 7)
1064#define GET_TBC(p) (((p) >> 7) & 0x3)
1065#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1066#define GET_TLBPC(p) (((p) >> 16) & 0xf)
1067
1068/* TRB cache size for xHC with TRB cache */
1069#define TRB_CACHE_SIZE_HS 8
1070#define TRB_CACHE_SIZE_SS 16
1071
1072struct xhci_generic_trb {
1073 __le32 field[4];
1074};
1075
1076union xhci_trb {
1077 struct xhci_link_trb link;
1078 struct xhci_transfer_event trans_event;
1079 struct xhci_event_cmd event_cmd;
1080 struct xhci_generic_trb generic;
1081};
1082
1083/* TRB bit mask */
1084#define TRB_TYPE_BITMASK (0xfc00)
1085#define TRB_TYPE(p) ((p) << 10)
1086#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1087/* TRB type IDs */
1088/* bulk, interrupt, isoc scatter/gather, and control data stage */
1089#define TRB_NORMAL 1
1090/* setup stage for control transfers */
1091#define TRB_SETUP 2
1092/* data stage for control transfers */
1093#define TRB_DATA 3
1094/* status stage for control transfers */
1095#define TRB_STATUS 4
1096/* isoc transfers */
1097#define TRB_ISOC 5
1098/* TRB for linking ring segments */
1099#define TRB_LINK 6
1100#define TRB_EVENT_DATA 7
1101/* Transfer Ring No-op (not for the command ring) */
1102#define TRB_TR_NOOP 8
1103/* Command TRBs */
1104/* Enable Slot Command */
1105#define TRB_ENABLE_SLOT 9
1106/* Disable Slot Command */
1107#define TRB_DISABLE_SLOT 10
1108/* Address Device Command */
1109#define TRB_ADDR_DEV 11
1110/* Configure Endpoint Command */
1111#define TRB_CONFIG_EP 12
1112/* Evaluate Context Command */
1113#define TRB_EVAL_CONTEXT 13
1114/* Reset Endpoint Command */
1115#define TRB_RESET_EP 14
1116/* Stop Transfer Ring Command */
1117#define TRB_STOP_RING 15
1118/* Set Transfer Ring Dequeue Pointer Command */
1119#define TRB_SET_DEQ 16
1120/* Reset Device Command */
1121#define TRB_RESET_DEV 17
1122/* Force Event Command (opt) */
1123#define TRB_FORCE_EVENT 18
1124/* Negotiate Bandwidth Command (opt) */
1125#define TRB_NEG_BANDWIDTH 19
1126/* Set Latency Tolerance Value Command (opt) */
1127#define TRB_SET_LT 20
1128/* Get port bandwidth Command */
1129#define TRB_GET_BW 21
1130/* Force Header Command - generate a transaction or link management packet */
1131#define TRB_FORCE_HEADER 22
1132/* No-op Command - not for transfer rings */
1133#define TRB_CMD_NOOP 23
1134/* TRB IDs 24-31 reserved */
1135/* Event TRBS */
1136/* Transfer Event */
1137#define TRB_TRANSFER 32
1138/* Command Completion Event */
1139#define TRB_COMPLETION 33
1140/* Port Status Change Event */
1141#define TRB_PORT_STATUS 34
1142/* Bandwidth Request Event (opt) */
1143#define TRB_BANDWIDTH_EVENT 35
1144/* Doorbell Event (opt) */
1145#define TRB_DOORBELL 36
1146/* Host Controller Event */
1147#define TRB_HC_EVENT 37
1148/* Device Notification Event - device sent function wake notification */
1149#define TRB_DEV_NOTE 38
1150/* MFINDEX Wrap Event - microframe counter wrapped */
1151#define TRB_MFINDEX_WRAP 39
1152/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1153#define TRB_VENDOR_DEFINED_LOW 48
1154/* Nec vendor-specific command completion event. */
1155#define TRB_NEC_CMD_COMP 48
1156/* Get NEC firmware revision. */
1157#define TRB_NEC_GET_FW 49
1158
1159static inline const char *xhci_trb_type_string(u8 type)
1160{
1161 switch (type) {
1162 case TRB_NORMAL:
1163 return "Normal";
1164 case TRB_SETUP:
1165 return "Setup Stage";
1166 case TRB_DATA:
1167 return "Data Stage";
1168 case TRB_STATUS:
1169 return "Status Stage";
1170 case TRB_ISOC:
1171 return "Isoch";
1172 case TRB_LINK:
1173 return "Link";
1174 case TRB_EVENT_DATA:
1175 return "Event Data";
1176 case TRB_TR_NOOP:
1177 return "No-Op";
1178 case TRB_ENABLE_SLOT:
1179 return "Enable Slot Command";
1180 case TRB_DISABLE_SLOT:
1181 return "Disable Slot Command";
1182 case TRB_ADDR_DEV:
1183 return "Address Device Command";
1184 case TRB_CONFIG_EP:
1185 return "Configure Endpoint Command";
1186 case TRB_EVAL_CONTEXT:
1187 return "Evaluate Context Command";
1188 case TRB_RESET_EP:
1189 return "Reset Endpoint Command";
1190 case TRB_STOP_RING:
1191 return "Stop Ring Command";
1192 case TRB_SET_DEQ:
1193 return "Set TR Dequeue Pointer Command";
1194 case TRB_RESET_DEV:
1195 return "Reset Device Command";
1196 case TRB_FORCE_EVENT:
1197 return "Force Event Command";
1198 case TRB_NEG_BANDWIDTH:
1199 return "Negotiate Bandwidth Command";
1200 case TRB_SET_LT:
1201 return "Set Latency Tolerance Value Command";
1202 case TRB_GET_BW:
1203 return "Get Port Bandwidth Command";
1204 case TRB_FORCE_HEADER:
1205 return "Force Header Command";
1206 case TRB_CMD_NOOP:
1207 return "No-Op Command";
1208 case TRB_TRANSFER:
1209 return "Transfer Event";
1210 case TRB_COMPLETION:
1211 return "Command Completion Event";
1212 case TRB_PORT_STATUS:
1213 return "Port Status Change Event";
1214 case TRB_BANDWIDTH_EVENT:
1215 return "Bandwidth Request Event";
1216 case TRB_DOORBELL:
1217 return "Doorbell Event";
1218 case TRB_HC_EVENT:
1219 return "Host Controller Event";
1220 case TRB_DEV_NOTE:
1221 return "Device Notification Event";
1222 case TRB_MFINDEX_WRAP:
1223 return "MFINDEX Wrap Event";
1224 case TRB_NEC_CMD_COMP:
1225 return "NEC Command Completion Event";
1226 case TRB_NEC_GET_FW:
1227 return "NET Get Firmware Revision Command";
1228 default:
1229 return "UNKNOWN";
1230 }
1231}
1232
1233#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1234/* Above, but for __le32 types -- can avoid work by swapping constants: */
1235#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1236 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1237#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1238 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1239
1240#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1241#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1242
1243/*
1244 * TRBS_PER_SEGMENT must be a multiple of 4,
1245 * since the command ring is 64-byte aligned.
1246 * It must also be greater than 16.
1247 */
1248#define TRBS_PER_SEGMENT 256
1249/* Allow two commands + a link TRB, along with any reserved command TRBs */
1250#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1251#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1252#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1253/* TRB buffer pointers can't cross 64KB boundaries */
1254#define TRB_MAX_BUFF_SHIFT 16
1255#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1256/* How much data is left before the 64KB boundary? */
1257#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1258 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1259#define MAX_SOFT_RETRY 3
1260/*
1261 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1262 * XHCI_AVOID_BEI quirk is in use.
1263 */
1264#define AVOID_BEI_INTERVAL_MIN 8
1265#define AVOID_BEI_INTERVAL_MAX 32
1266
1267#define xhci_for_each_ring_seg(head, seg) \
1268 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL))
1269
1270struct xhci_segment {
1271 union xhci_trb *trbs;
1272 /* private to HCD */
1273 struct xhci_segment *next;
1274 unsigned int num;
1275 dma_addr_t dma;
1276 /* Max packet sized bounce buffer for td-fragmant alignment */
1277 dma_addr_t bounce_dma;
1278 void *bounce_buf;
1279 unsigned int bounce_offs;
1280 unsigned int bounce_len;
1281};
1282
1283enum xhci_cancelled_td_status {
1284 TD_DIRTY = 0,
1285 TD_HALTED,
1286 TD_CLEARING_CACHE,
1287 TD_CLEARING_CACHE_DEFERRED,
1288 TD_CLEARED,
1289};
1290
1291struct xhci_td {
1292 struct list_head td_list;
1293 struct list_head cancelled_td_list;
1294 int status;
1295 enum xhci_cancelled_td_status cancel_status;
1296 struct urb *urb;
1297 struct xhci_segment *start_seg;
1298 union xhci_trb *start_trb;
1299 struct xhci_segment *end_seg;
1300 union xhci_trb *end_trb;
1301 struct xhci_segment *bounce_seg;
1302 /* actual_length of the URB has already been set */
1303 bool urb_length_set;
1304 bool error_mid_td;
1305};
1306
1307/*
1308 * xHCI command default timeout value in milliseconds.
1309 * USB 3.2 spec, section 9.2.6.1
1310 */
1311#define XHCI_CMD_DEFAULT_TIMEOUT 5000
1312
1313/* command descriptor */
1314struct xhci_cd {
1315 struct xhci_command *command;
1316 union xhci_trb *cmd_trb;
1317};
1318
1319enum xhci_ring_type {
1320 TYPE_CTRL = 0,
1321 TYPE_ISOC,
1322 TYPE_BULK,
1323 TYPE_INTR,
1324 TYPE_STREAM,
1325 TYPE_COMMAND,
1326 TYPE_EVENT,
1327};
1328
1329static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1330{
1331 switch (type) {
1332 case TYPE_CTRL:
1333 return "CTRL";
1334 case TYPE_ISOC:
1335 return "ISOC";
1336 case TYPE_BULK:
1337 return "BULK";
1338 case TYPE_INTR:
1339 return "INTR";
1340 case TYPE_STREAM:
1341 return "STREAM";
1342 case TYPE_COMMAND:
1343 return "CMD";
1344 case TYPE_EVENT:
1345 return "EVENT";
1346 }
1347
1348 return "UNKNOWN";
1349}
1350
1351struct xhci_ring {
1352 struct xhci_segment *first_seg;
1353 struct xhci_segment *last_seg;
1354 union xhci_trb *enqueue;
1355 struct xhci_segment *enq_seg;
1356 union xhci_trb *dequeue;
1357 struct xhci_segment *deq_seg;
1358 struct list_head td_list;
1359 /*
1360 * Write the cycle state into the TRB cycle field to give ownership of
1361 * the TRB to the host controller (if we are the producer), or to check
1362 * if we own the TRB (if we are the consumer). See section 4.9.1.
1363 */
1364 u32 cycle_state;
1365 unsigned int stream_id;
1366 unsigned int num_segs;
1367 unsigned int num_trbs_free; /* used only by xhci DbC */
1368 unsigned int bounce_buf_len;
1369 enum xhci_ring_type type;
1370 bool last_td_was_short;
1371 struct radix_tree_root *trb_address_map;
1372};
1373
1374struct xhci_erst_entry {
1375 /* 64-bit event ring segment address */
1376 __le64 seg_addr;
1377 __le32 seg_size;
1378 /* Set to zero */
1379 __le32 rsvd;
1380};
1381
1382struct xhci_erst {
1383 struct xhci_erst_entry *entries;
1384 unsigned int num_entries;
1385 /* xhci->event_ring keeps track of segment dma addresses */
1386 dma_addr_t erst_dma_addr;
1387};
1388
1389struct xhci_scratchpad {
1390 u64 *sp_array;
1391 dma_addr_t sp_dma;
1392 void **sp_buffers;
1393};
1394
1395struct urb_priv {
1396 int num_tds;
1397 int num_tds_done;
1398 struct xhci_td td[] __counted_by(num_tds);
1399};
1400
1401/* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */
1402#define ERST_DEFAULT_SEGS 2
1403/* Poll every 60 seconds */
1404#define POLL_TIMEOUT 60
1405/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1406#define XHCI_STOP_EP_CMD_TIMEOUT 5
1407/* XXX: Make these module parameters */
1408
1409struct s3_save {
1410 u32 command;
1411 u32 dev_nt;
1412 u64 dcbaa_ptr;
1413 u32 config_reg;
1414};
1415
1416/* Use for lpm */
1417struct dev_info {
1418 u32 dev_id;
1419 struct list_head list;
1420};
1421
1422struct xhci_bus_state {
1423 unsigned long bus_suspended;
1424 unsigned long next_statechange;
1425
1426 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1427 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1428 u32 port_c_suspend;
1429 u32 suspended_ports;
1430 u32 port_remote_wakeup;
1431 /* which ports have started to resume */
1432 unsigned long resuming_ports;
1433};
1434
1435struct xhci_interrupter {
1436 struct xhci_ring *event_ring;
1437 struct xhci_erst erst;
1438 struct xhci_intr_reg __iomem *ir_set;
1439 unsigned int intr_num;
1440 bool ip_autoclear;
1441 u32 isoc_bei_interval;
1442 /* For interrupter registers save and restore over suspend/resume */
1443 u32 s3_irq_pending;
1444 u32 s3_irq_control;
1445 u32 s3_erst_size;
1446 u64 s3_erst_base;
1447 u64 s3_erst_dequeue;
1448};
1449/*
1450 * It can take up to 20 ms to transition from RExit to U0 on the
1451 * Intel Lynx Point LP xHCI host.
1452 */
1453#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1454struct xhci_port_cap {
1455 u32 *psi; /* array of protocol speed ID entries */
1456 u8 psi_count;
1457 u8 psi_uid_count;
1458 u8 maj_rev;
1459 u8 min_rev;
1460 u32 protocol_caps;
1461};
1462
1463struct xhci_port {
1464 __le32 __iomem *addr;
1465 int hw_portnum;
1466 int hcd_portnum;
1467 struct xhci_hub *rhub;
1468 struct xhci_port_cap *port_cap;
1469 unsigned int lpm_incapable:1;
1470 unsigned long resume_timestamp;
1471 bool rexit_active;
1472 /* Slot ID is the index of the device directly connected to the port */
1473 int slot_id;
1474 struct completion rexit_done;
1475 struct completion u3exit_done;
1476};
1477
1478struct xhci_hub {
1479 struct xhci_port **ports;
1480 unsigned int num_ports;
1481 struct usb_hcd *hcd;
1482 /* keep track of bus suspend info */
1483 struct xhci_bus_state bus_state;
1484 /* supported prococol extended capabiliy values */
1485 u8 maj_rev;
1486 u8 min_rev;
1487};
1488
1489/* There is one xhci_hcd structure per controller */
1490struct xhci_hcd {
1491 struct usb_hcd *main_hcd;
1492 struct usb_hcd *shared_hcd;
1493 /* glue to PCI and HCD framework */
1494 struct xhci_cap_regs __iomem *cap_regs;
1495 struct xhci_op_regs __iomem *op_regs;
1496 struct xhci_run_regs __iomem *run_regs;
1497 struct xhci_doorbell_array __iomem *dba;
1498
1499 /* Cached register copies of read-only HC data */
1500 __u32 hcs_params1;
1501 __u32 hcs_params2;
1502 __u32 hcs_params3;
1503 __u32 hcc_params;
1504 __u32 hcc_params2;
1505
1506 spinlock_t lock;
1507
1508 /* packed release number */
1509 u16 hci_version;
1510 u16 max_interrupters;
1511 /* imod_interval in ns (I * 250ns) */
1512 u32 imod_interval;
1513 /* 4KB min, 128MB max */
1514 int page_size;
1515 /* Valid values are 12 to 20, inclusive */
1516 int page_shift;
1517 /* MSI-X/MSI vectors */
1518 int nvecs;
1519 /* optional clocks */
1520 struct clk *clk;
1521 struct clk *reg_clk;
1522 /* optional reset controller */
1523 struct reset_control *reset;
1524 /* data structures */
1525 struct xhci_device_context_array *dcbaa;
1526 struct xhci_interrupter **interrupters;
1527 struct xhci_ring *cmd_ring;
1528 unsigned int cmd_ring_state;
1529#define CMD_RING_STATE_RUNNING (1 << 0)
1530#define CMD_RING_STATE_ABORTED (1 << 1)
1531#define CMD_RING_STATE_STOPPED (1 << 2)
1532 struct list_head cmd_list;
1533 unsigned int cmd_ring_reserved_trbs;
1534 struct delayed_work cmd_timer;
1535 struct completion cmd_ring_stop_completion;
1536 struct xhci_command *current_cmd;
1537
1538 /* Scratchpad */
1539 struct xhci_scratchpad *scratchpad;
1540
1541 /* slot enabling and address device helpers */
1542 /* these are not thread safe so use mutex */
1543 struct mutex mutex;
1544 /* Internal mirror of the HW's dcbaa */
1545 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1546 /* For keeping track of bandwidth domains per roothub. */
1547 struct xhci_root_port_bw_info *rh_bw;
1548
1549 /* DMA pools */
1550 struct dma_pool *device_pool;
1551 struct dma_pool *segment_pool;
1552 struct dma_pool *small_streams_pool;
1553 struct dma_pool *medium_streams_pool;
1554
1555 /* Host controller watchdog timer structures */
1556 unsigned int xhc_state;
1557 unsigned long run_graceperiod;
1558 struct s3_save s3;
1559/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1560 *
1561 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1562 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1563 * that sees this status (other than the timer that set it) should stop touching
1564 * hardware immediately. Interrupt handlers should return immediately when
1565 * they see this status (any time they drop and re-acquire xhci->lock).
1566 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1567 * putting the TD on the canceled list, etc.
1568 *
1569 * There are no reports of xHCI host controllers that display this issue.
1570 */
1571#define XHCI_STATE_DYING (1 << 0)
1572#define XHCI_STATE_HALTED (1 << 1)
1573#define XHCI_STATE_REMOVING (1 << 2)
1574 unsigned long long quirks;
1575#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1576#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1577#define XHCI_NEC_HOST BIT_ULL(2)
1578#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1579#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1580/*
1581 * Certain Intel host controllers have a limit to the number of endpoint
1582 * contexts they can handle. Ideally, they would signal that they can't handle
1583 * anymore endpoint contexts by returning a Resource Error for the Configure
1584 * Endpoint command, but they don't. Instead they expect software to keep track
1585 * of the number of active endpoints for them, across configure endpoint
1586 * commands, reset device commands, disable slot commands, and address device
1587 * commands.
1588 */
1589#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1590#define XHCI_BROKEN_MSI BIT_ULL(6)
1591#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1592#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1593#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1594#define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */
1595#define XHCI_LPM_SUPPORT BIT_ULL(11)
1596#define XHCI_INTEL_HOST BIT_ULL(12)
1597#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1598#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1599#define XHCI_AVOID_BEI BIT_ULL(15)
1600#define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1601#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1602#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1603/* For controllers with a broken beyond repair streams implementation */
1604#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1605#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1606#define XHCI_MTK_HOST BIT_ULL(21)
1607#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1608#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1609#define XHCI_MISSING_CAS BIT_ULL(24)
1610/* For controller with a broken Port Disable implementation */
1611#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1612#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1613#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1614#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1615#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1616#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1617#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1618#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1619#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1620#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1621#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1622/* Reserved. It was XHCI_RENESAS_FW_QUIRK */
1623#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1624#define XHCI_DISABLE_SPARSE BIT_ULL(38)
1625#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1626#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1627#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1628#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1629#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1630#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1631#define XHCI_TRB_OVERFETCH BIT_ULL(45)
1632#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1633#define XHCI_WRITE_64_HI_LO BIT_ULL(47)
1634#define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48)
1635#define XHCI_ETRON_HOST BIT_ULL(49)
1636
1637 unsigned int num_active_eps;
1638 unsigned int limit_active_eps;
1639 struct xhci_port *hw_ports;
1640 struct xhci_hub usb2_rhub;
1641 struct xhci_hub usb3_rhub;
1642 /* support xHCI 1.0 spec USB2 hardware LPM */
1643 unsigned hw_lpm_support:1;
1644 /* Broken Suspend flag for SNPS Suspend resume issue */
1645 unsigned broken_suspend:1;
1646 /* Indicates that omitting hcd is supported if root hub has no ports */
1647 unsigned allow_single_roothub:1;
1648 /* cached extended protocol port capabilities */
1649 struct xhci_port_cap *port_caps;
1650 unsigned int num_port_caps;
1651 /* Compliance Mode Recovery Data */
1652 struct timer_list comp_mode_recovery_timer;
1653 u32 port_status_u0;
1654 u16 test_mode;
1655/* Compliance Mode Timer Triggered every 2 seconds */
1656#define COMP_MODE_RCVRY_MSECS 2000
1657
1658 struct dentry *debugfs_root;
1659 struct dentry *debugfs_slots;
1660 struct list_head regset_list;
1661
1662 void *dbc;
1663 /* platform-specific data -- must come last */
1664 unsigned long priv[] __aligned(sizeof(s64));
1665};
1666
1667/* Platform specific overrides to generic XHCI hc_driver ops */
1668struct xhci_driver_overrides {
1669 size_t extra_priv_size;
1670 int (*reset)(struct usb_hcd *hcd);
1671 int (*start)(struct usb_hcd *hcd);
1672 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1673 struct usb_host_endpoint *ep);
1674 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1675 struct usb_host_endpoint *ep);
1676 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1677 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1678 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1679 struct usb_tt *tt, gfp_t mem_flags);
1680 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1681 u16 wIndex, char *buf, u16 wLength);
1682};
1683
1684#define XHCI_CFC_DELAY 10
1685
1686/* convert between an HCD pointer and the corresponding EHCI_HCD */
1687static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1688{
1689 struct usb_hcd *primary_hcd;
1690
1691 if (usb_hcd_is_primary_hcd(hcd))
1692 primary_hcd = hcd;
1693 else
1694 primary_hcd = hcd->primary_hcd;
1695
1696 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1697}
1698
1699static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1700{
1701 return xhci->main_hcd;
1702}
1703
1704static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1705{
1706 if (xhci->shared_hcd)
1707 return xhci->shared_hcd;
1708
1709 if (!xhci->usb2_rhub.num_ports)
1710 return xhci->main_hcd;
1711
1712 return NULL;
1713}
1714
1715static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1716{
1717 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1718
1719 return hcd == xhci_get_usb3_hcd(xhci);
1720}
1721
1722static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1723{
1724 return xhci->allow_single_roothub &&
1725 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1726}
1727
1728#define xhci_dbg(xhci, fmt, args...) \
1729 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1730#define xhci_err(xhci, fmt, args...) \
1731 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1732#define xhci_warn(xhci, fmt, args...) \
1733 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1734#define xhci_info(xhci, fmt, args...) \
1735 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1736
1737/*
1738 * Registers should always be accessed with double word or quad word accesses.
1739 *
1740 * Some xHCI implementations may support 64-bit address pointers. Registers
1741 * with 64-bit address pointers should be written to with dword accesses by
1742 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1743 * xHCI implementations that do not support 64-bit address pointers will ignore
1744 * the high dword, and write order is irrelevant.
1745 */
1746static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1747 __le64 __iomem *regs)
1748{
1749 return lo_hi_readq(regs);
1750}
1751static inline void xhci_write_64(struct xhci_hcd *xhci,
1752 const u64 val, __le64 __iomem *regs)
1753{
1754 lo_hi_writeq(val, regs);
1755}
1756
1757
1758/* Link TRB chain should always be set on 0.95 hosts, and AMD 0.96 ISOC rings */
1759static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type)
1760{
1761 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) ||
1762 (type == TYPE_ISOC && (xhci->quirks & XHCI_AMD_0x96_HOST));
1763}
1764
1765/* xHCI debugging */
1766char *xhci_get_slot_state(struct xhci_hcd *xhci,
1767 struct xhci_container_ctx *ctx);
1768void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1769 const char *fmt, ...);
1770
1771/* xHCI memory management */
1772void xhci_mem_cleanup(struct xhci_hcd *xhci);
1773int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1774void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1775int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1776int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1777void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1778 struct usb_device *udev);
1779unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1780unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1781void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1782void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1783 struct xhci_virt_device *virt_dev,
1784 int old_active_eps);
1785void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1786void xhci_update_bw_info(struct xhci_hcd *xhci,
1787 struct xhci_container_ctx *in_ctx,
1788 struct xhci_input_control_ctx *ctrl_ctx,
1789 struct xhci_virt_device *virt_dev);
1790void xhci_endpoint_copy(struct xhci_hcd *xhci,
1791 struct xhci_container_ctx *in_ctx,
1792 struct xhci_container_ctx *out_ctx,
1793 unsigned int ep_index);
1794void xhci_slot_copy(struct xhci_hcd *xhci,
1795 struct xhci_container_ctx *in_ctx,
1796 struct xhci_container_ctx *out_ctx);
1797int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1798 struct usb_device *udev, struct usb_host_endpoint *ep,
1799 gfp_t mem_flags);
1800struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs,
1801 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1802void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1803int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1804 unsigned int num_trbs, gfp_t flags);
1805void xhci_initialize_ring_info(struct xhci_ring *ring);
1806void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1807 struct xhci_virt_device *virt_dev,
1808 unsigned int ep_index);
1809struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1810 unsigned int num_stream_ctxs,
1811 unsigned int num_streams,
1812 unsigned int max_packet, gfp_t flags);
1813void xhci_free_stream_info(struct xhci_hcd *xhci,
1814 struct xhci_stream_info *stream_info);
1815void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1816 struct xhci_ep_ctx *ep_ctx,
1817 struct xhci_stream_info *stream_info);
1818void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1819 struct xhci_virt_ep *ep);
1820void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1821 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1822struct xhci_ring *xhci_dma_to_transfer_ring(
1823 struct xhci_virt_ep *ep,
1824 u64 address);
1825struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1826 bool allocate_completion, gfp_t mem_flags);
1827struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1828 bool allocate_completion, gfp_t mem_flags);
1829void xhci_urb_free_priv(struct urb_priv *urb_priv);
1830void xhci_free_command(struct xhci_hcd *xhci,
1831 struct xhci_command *command);
1832struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
1833 int type, gfp_t flags);
1834void xhci_free_container_ctx(struct xhci_hcd *xhci,
1835 struct xhci_container_ctx *ctx);
1836struct xhci_interrupter *
1837xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs,
1838 u32 imod_interval);
1839void xhci_remove_secondary_interrupter(struct usb_hcd
1840 *hcd, struct xhci_interrupter *ir);
1841
1842/* xHCI host controller glue */
1843typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1844int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
1845int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
1846 u32 mask, u32 done, int usec, unsigned int exit_state);
1847void xhci_quiesce(struct xhci_hcd *xhci);
1848int xhci_halt(struct xhci_hcd *xhci);
1849int xhci_start(struct xhci_hcd *xhci);
1850int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
1851int xhci_run(struct usb_hcd *hcd);
1852int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1853void xhci_shutdown(struct usb_hcd *hcd);
1854void xhci_stop(struct usb_hcd *hcd);
1855void xhci_init_driver(struct hc_driver *drv,
1856 const struct xhci_driver_overrides *over);
1857int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1858 struct usb_host_endpoint *ep);
1859int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1860 struct usb_host_endpoint *ep);
1861int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1862void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1863int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1864 struct usb_tt *tt, gfp_t mem_flags);
1865int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
1866int xhci_ext_cap_init(struct xhci_hcd *xhci);
1867
1868int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1869int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
1870
1871irqreturn_t xhci_irq(struct usb_hcd *hcd);
1872irqreturn_t xhci_msi_irq(int irq, void *hcd);
1873int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1874int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1875 struct xhci_virt_device *virt_dev,
1876 struct usb_device *hdev,
1877 struct usb_tt *tt, gfp_t mem_flags);
1878int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
1879 u32 imod_interval);
1880
1881/* xHCI ring, segment, TRB, and TD functions */
1882dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1883struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, struct xhci_td *td,
1884 dma_addr_t suspect_dma, bool debug);
1885int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1886void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1887int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1888 u32 trb_type, u32 slot_id);
1889int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1890 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1891int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1892 u32 field1, u32 field2, u32 field3, u32 field4);
1893int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1894 int slot_id, unsigned int ep_index, int suspend);
1895int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1896 int slot_id, unsigned int ep_index);
1897int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1898 int slot_id, unsigned int ep_index);
1899int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1900 int slot_id, unsigned int ep_index);
1901int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1902 struct urb *urb, int slot_id, unsigned int ep_index);
1903int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1904 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1905 bool command_must_succeed);
1906int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1907 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1908int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1909 int slot_id, unsigned int ep_index,
1910 enum xhci_ep_reset_type reset_type);
1911int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1912 u32 slot_id);
1913void xhci_handle_command_timeout(struct work_struct *work);
1914
1915void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1916 unsigned int ep_index, unsigned int stream_id);
1917void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
1918 unsigned int slot_id,
1919 unsigned int ep_index);
1920void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1921void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
1922unsigned int count_trbs(u64 addr, u64 len);
1923int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
1924 int suspend, gfp_t gfp_flags);
1925void xhci_process_cancelled_tds(struct xhci_virt_ep *ep);
1926
1927/* xHCI roothub code */
1928void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
1929 u32 link_state);
1930void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
1931 u32 port_bit);
1932int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1933 char *buf, u16 wLength);
1934int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1935int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1936struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
1937enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci,
1938 struct xhci_port *port);
1939void xhci_hc_died(struct xhci_hcd *xhci);
1940
1941#ifdef CONFIG_PM
1942int xhci_bus_suspend(struct usb_hcd *hcd);
1943int xhci_bus_resume(struct usb_hcd *hcd);
1944unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
1945#else
1946#define xhci_bus_suspend NULL
1947#define xhci_bus_resume NULL
1948#define xhci_get_resuming_ports NULL
1949#endif /* CONFIG_PM */
1950
1951u32 xhci_port_state_to_neutral(u32 state);
1952void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1953
1954/* xHCI contexts */
1955struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1956struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1957struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1958
1959struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1960 unsigned int slot_id, unsigned int ep_index,
1961 unsigned int stream_id);
1962
1963static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1964 struct urb *urb)
1965{
1966 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
1967 xhci_get_endpoint_index(&urb->ep->desc),
1968 urb->stream_id);
1969}
1970
1971/*
1972 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
1973 * them anyways as we where unable to find a device that matches the
1974 * constraints.
1975 */
1976static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
1977{
1978 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
1979 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
1980 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
1981 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
1982 !urb->num_sgs)
1983 return true;
1984
1985 return false;
1986}
1987
1988static inline char *xhci_slot_state_string(u32 state)
1989{
1990 switch (state) {
1991 case SLOT_STATE_ENABLED:
1992 return "enabled/disabled";
1993 case SLOT_STATE_DEFAULT:
1994 return "default";
1995 case SLOT_STATE_ADDRESSED:
1996 return "addressed";
1997 case SLOT_STATE_CONFIGURED:
1998 return "configured";
1999 default:
2000 return "reserved";
2001 }
2002}
2003
2004static inline const char *xhci_decode_trb(char *str, size_t size,
2005 u32 field0, u32 field1, u32 field2, u32 field3)
2006{
2007 int type = TRB_FIELD_TO_TYPE(field3);
2008
2009 switch (type) {
2010 case TRB_LINK:
2011 snprintf(str, size,
2012 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2013 field1, field0, GET_INTR_TARGET(field2),
2014 xhci_trb_type_string(type),
2015 field3 & TRB_IOC ? 'I' : 'i',
2016 field3 & TRB_CHAIN ? 'C' : 'c',
2017 field3 & TRB_TC ? 'T' : 't',
2018 field3 & TRB_CYCLE ? 'C' : 'c');
2019 break;
2020 case TRB_TRANSFER:
2021 case TRB_COMPLETION:
2022 case TRB_PORT_STATUS:
2023 case TRB_BANDWIDTH_EVENT:
2024 case TRB_DOORBELL:
2025 case TRB_HC_EVENT:
2026 case TRB_DEV_NOTE:
2027 case TRB_MFINDEX_WRAP:
2028 snprintf(str, size,
2029 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2030 field1, field0,
2031 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2032 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2033 TRB_TO_EP_ID(field3),
2034 xhci_trb_type_string(type),
2035 field3 & EVENT_DATA ? 'E' : 'e',
2036 field3 & TRB_CYCLE ? 'C' : 'c');
2037
2038 break;
2039 case TRB_SETUP:
2040 snprintf(str, size,
2041 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2042 field0 & 0xff,
2043 (field0 & 0xff00) >> 8,
2044 (field0 & 0xff000000) >> 24,
2045 (field0 & 0xff0000) >> 16,
2046 (field1 & 0xff00) >> 8,
2047 field1 & 0xff,
2048 (field1 & 0xff000000) >> 16 |
2049 (field1 & 0xff0000) >> 16,
2050 TRB_LEN(field2), GET_TD_SIZE(field2),
2051 GET_INTR_TARGET(field2),
2052 xhci_trb_type_string(type),
2053 field3 & TRB_IDT ? 'I' : 'i',
2054 field3 & TRB_IOC ? 'I' : 'i',
2055 field3 & TRB_CYCLE ? 'C' : 'c');
2056 break;
2057 case TRB_DATA:
2058 snprintf(str, size,
2059 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2060 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2061 GET_INTR_TARGET(field2),
2062 xhci_trb_type_string(type),
2063 field3 & TRB_IDT ? 'I' : 'i',
2064 field3 & TRB_IOC ? 'I' : 'i',
2065 field3 & TRB_CHAIN ? 'C' : 'c',
2066 field3 & TRB_NO_SNOOP ? 'S' : 's',
2067 field3 & TRB_ISP ? 'I' : 'i',
2068 field3 & TRB_ENT ? 'E' : 'e',
2069 field3 & TRB_CYCLE ? 'C' : 'c');
2070 break;
2071 case TRB_STATUS:
2072 snprintf(str, size,
2073 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2074 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2075 GET_INTR_TARGET(field2),
2076 xhci_trb_type_string(type),
2077 field3 & TRB_IOC ? 'I' : 'i',
2078 field3 & TRB_CHAIN ? 'C' : 'c',
2079 field3 & TRB_ENT ? 'E' : 'e',
2080 field3 & TRB_CYCLE ? 'C' : 'c');
2081 break;
2082 case TRB_NORMAL:
2083 case TRB_EVENT_DATA:
2084 case TRB_TR_NOOP:
2085 snprintf(str, size,
2086 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2087 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2088 GET_INTR_TARGET(field2),
2089 xhci_trb_type_string(type),
2090 field3 & TRB_BEI ? 'B' : 'b',
2091 field3 & TRB_IDT ? 'I' : 'i',
2092 field3 & TRB_IOC ? 'I' : 'i',
2093 field3 & TRB_CHAIN ? 'C' : 'c',
2094 field3 & TRB_NO_SNOOP ? 'S' : 's',
2095 field3 & TRB_ISP ? 'I' : 'i',
2096 field3 & TRB_ENT ? 'E' : 'e',
2097 field3 & TRB_CYCLE ? 'C' : 'c');
2098 break;
2099 case TRB_ISOC:
2100 snprintf(str, size,
2101 "Buffer %08x%08x length %d TD size/TBC %d intr %d type '%s' TBC %u TLBPC %u frame_id %u flags %c:%c:%c:%c:%c:%c:%c:%c:%c",
2102 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2103 GET_INTR_TARGET(field2),
2104 xhci_trb_type_string(type),
2105 GET_TBC(field3),
2106 GET_TLBPC(field3),
2107 GET_FRAME_ID(field3),
2108 field3 & TRB_SIA ? 'S' : 's',
2109 field3 & TRB_BEI ? 'B' : 'b',
2110 field3 & TRB_IDT ? 'I' : 'i',
2111 field3 & TRB_IOC ? 'I' : 'i',
2112 field3 & TRB_CHAIN ? 'C' : 'c',
2113 field3 & TRB_NO_SNOOP ? 'S' : 's',
2114 field3 & TRB_ISP ? 'I' : 'i',
2115 field3 & TRB_ENT ? 'E' : 'e',
2116 field3 & TRB_CYCLE ? 'C' : 'c');
2117 break;
2118 case TRB_CMD_NOOP:
2119 case TRB_ENABLE_SLOT:
2120 snprintf(str, size,
2121 "%s: flags %c",
2122 xhci_trb_type_string(type),
2123 field3 & TRB_CYCLE ? 'C' : 'c');
2124 break;
2125 case TRB_DISABLE_SLOT:
2126 case TRB_NEG_BANDWIDTH:
2127 snprintf(str, size,
2128 "%s: slot %d flags %c",
2129 xhci_trb_type_string(type),
2130 TRB_TO_SLOT_ID(field3),
2131 field3 & TRB_CYCLE ? 'C' : 'c');
2132 break;
2133 case TRB_ADDR_DEV:
2134 snprintf(str, size,
2135 "%s: ctx %08x%08x slot %d flags %c:%c",
2136 xhci_trb_type_string(type),
2137 field1, field0,
2138 TRB_TO_SLOT_ID(field3),
2139 field3 & TRB_BSR ? 'B' : 'b',
2140 field3 & TRB_CYCLE ? 'C' : 'c');
2141 break;
2142 case TRB_CONFIG_EP:
2143 snprintf(str, size,
2144 "%s: ctx %08x%08x slot %d flags %c:%c",
2145 xhci_trb_type_string(type),
2146 field1, field0,
2147 TRB_TO_SLOT_ID(field3),
2148 field3 & TRB_DC ? 'D' : 'd',
2149 field3 & TRB_CYCLE ? 'C' : 'c');
2150 break;
2151 case TRB_EVAL_CONTEXT:
2152 snprintf(str, size,
2153 "%s: ctx %08x%08x slot %d flags %c",
2154 xhci_trb_type_string(type),
2155 field1, field0,
2156 TRB_TO_SLOT_ID(field3),
2157 field3 & TRB_CYCLE ? 'C' : 'c');
2158 break;
2159 case TRB_RESET_EP:
2160 snprintf(str, size,
2161 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2162 xhci_trb_type_string(type),
2163 field1, field0,
2164 TRB_TO_SLOT_ID(field3),
2165 TRB_TO_EP_ID(field3),
2166 field3 & TRB_TSP ? 'T' : 't',
2167 field3 & TRB_CYCLE ? 'C' : 'c');
2168 break;
2169 case TRB_STOP_RING:
2170 snprintf(str, size,
2171 "%s: slot %d sp %d ep %d flags %c",
2172 xhci_trb_type_string(type),
2173 TRB_TO_SLOT_ID(field3),
2174 TRB_TO_SUSPEND_PORT(field3),
2175 TRB_TO_EP_ID(field3),
2176 field3 & TRB_CYCLE ? 'C' : 'c');
2177 break;
2178 case TRB_SET_DEQ:
2179 snprintf(str, size,
2180 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2181 xhci_trb_type_string(type),
2182 field1, field0,
2183 TRB_TO_STREAM_ID(field2),
2184 TRB_TO_SLOT_ID(field3),
2185 TRB_TO_EP_ID(field3),
2186 field3 & TRB_CYCLE ? 'C' : 'c');
2187 break;
2188 case TRB_RESET_DEV:
2189 snprintf(str, size,
2190 "%s: slot %d flags %c",
2191 xhci_trb_type_string(type),
2192 TRB_TO_SLOT_ID(field3),
2193 field3 & TRB_CYCLE ? 'C' : 'c');
2194 break;
2195 case TRB_FORCE_EVENT:
2196 snprintf(str, size,
2197 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2198 xhci_trb_type_string(type),
2199 field1, field0,
2200 TRB_TO_VF_INTR_TARGET(field2),
2201 TRB_TO_VF_ID(field3),
2202 field3 & TRB_CYCLE ? 'C' : 'c');
2203 break;
2204 case TRB_SET_LT:
2205 snprintf(str, size,
2206 "%s: belt %d flags %c",
2207 xhci_trb_type_string(type),
2208 TRB_TO_BELT(field3),
2209 field3 & TRB_CYCLE ? 'C' : 'c');
2210 break;
2211 case TRB_GET_BW:
2212 snprintf(str, size,
2213 "%s: ctx %08x%08x slot %d speed %d flags %c",
2214 xhci_trb_type_string(type),
2215 field1, field0,
2216 TRB_TO_SLOT_ID(field3),
2217 TRB_TO_DEV_SPEED(field3),
2218 field3 & TRB_CYCLE ? 'C' : 'c');
2219 break;
2220 case TRB_FORCE_HEADER:
2221 snprintf(str, size,
2222 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2223 xhci_trb_type_string(type),
2224 field2, field1, field0 & 0xffffffe0,
2225 TRB_TO_PACKET_TYPE(field0),
2226 TRB_TO_ROOTHUB_PORT(field3),
2227 field3 & TRB_CYCLE ? 'C' : 'c');
2228 break;
2229 default:
2230 snprintf(str, size,
2231 "type '%s' -> raw %08x %08x %08x %08x",
2232 xhci_trb_type_string(type),
2233 field0, field1, field2, field3);
2234 }
2235
2236 return str;
2237}
2238
2239static inline const char *xhci_decode_ctrl_ctx(char *str,
2240 unsigned long drop, unsigned long add)
2241{
2242 unsigned int bit;
2243 int ret = 0;
2244
2245 str[0] = '\0';
2246
2247 if (drop) {
2248 ret = sprintf(str, "Drop:");
2249 for_each_set_bit(bit, &drop, 32)
2250 ret += sprintf(str + ret, " %d%s",
2251 bit / 2,
2252 bit % 2 ? "in":"out");
2253 ret += sprintf(str + ret, ", ");
2254 }
2255
2256 if (add) {
2257 ret += sprintf(str + ret, "Add:%s%s",
2258 (add & SLOT_FLAG) ? " slot":"",
2259 (add & EP0_FLAG) ? " ep0":"");
2260 add &= ~(SLOT_FLAG | EP0_FLAG);
2261 for_each_set_bit(bit, &add, 32)
2262 ret += sprintf(str + ret, " %d%s",
2263 bit / 2,
2264 bit % 2 ? "in":"out");
2265 }
2266 return str;
2267}
2268
2269static inline const char *xhci_decode_slot_context(char *str,
2270 u32 info, u32 info2, u32 tt_info, u32 state)
2271{
2272 u32 speed;
2273 u32 hub;
2274 u32 mtt;
2275 int ret = 0;
2276
2277 speed = info & DEV_SPEED;
2278 hub = info & DEV_HUB;
2279 mtt = info & DEV_MTT;
2280
2281 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2282 info & ROUTE_STRING_MASK,
2283 ({ char *s;
2284 switch (speed) {
2285 case SLOT_SPEED_FS:
2286 s = "full-speed";
2287 break;
2288 case SLOT_SPEED_LS:
2289 s = "low-speed";
2290 break;
2291 case SLOT_SPEED_HS:
2292 s = "high-speed";
2293 break;
2294 case SLOT_SPEED_SS:
2295 s = "super-speed";
2296 break;
2297 case SLOT_SPEED_SSP:
2298 s = "super-speed plus";
2299 break;
2300 default:
2301 s = "UNKNOWN speed";
2302 } s; }),
2303 mtt ? " multi-TT" : "",
2304 hub ? " Hub" : "",
2305 (info & LAST_CTX_MASK) >> 27,
2306 info2 & MAX_EXIT,
2307 DEVINFO_TO_ROOT_HUB_PORT(info2),
2308 DEVINFO_TO_MAX_PORTS(info2));
2309
2310 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2311 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2312 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2313 state & DEV_ADDR_MASK,
2314 xhci_slot_state_string(GET_SLOT_STATE(state)));
2315
2316 return str;
2317}
2318
2319
2320static inline const char *xhci_portsc_link_state_string(u32 portsc)
2321{
2322 switch (portsc & PORT_PLS_MASK) {
2323 case XDEV_U0:
2324 return "U0";
2325 case XDEV_U1:
2326 return "U1";
2327 case XDEV_U2:
2328 return "U2";
2329 case XDEV_U3:
2330 return "U3";
2331 case XDEV_DISABLED:
2332 return "Disabled";
2333 case XDEV_RXDETECT:
2334 return "RxDetect";
2335 case XDEV_INACTIVE:
2336 return "Inactive";
2337 case XDEV_POLLING:
2338 return "Polling";
2339 case XDEV_RECOVERY:
2340 return "Recovery";
2341 case XDEV_HOT_RESET:
2342 return "Hot Reset";
2343 case XDEV_COMP_MODE:
2344 return "Compliance mode";
2345 case XDEV_TEST_MODE:
2346 return "Test mode";
2347 case XDEV_RESUME:
2348 return "Resume";
2349 default:
2350 break;
2351 }
2352 return "Unknown";
2353}
2354
2355static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2356{
2357 int ret;
2358
2359 ret = sprintf(str, "0x%08x ", portsc);
2360
2361 if (portsc == ~(u32)0)
2362 return str;
2363
2364 ret += sprintf(str + ret, "%s %s %s Link:%s PortSpeed:%d ",
2365 portsc & PORT_POWER ? "Powered" : "Powered-off",
2366 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2367 portsc & PORT_PE ? "Enabled" : "Disabled",
2368 xhci_portsc_link_state_string(portsc),
2369 DEV_PORT_SPEED(portsc));
2370
2371 if (portsc & PORT_OC)
2372 ret += sprintf(str + ret, "OverCurrent ");
2373 if (portsc & PORT_RESET)
2374 ret += sprintf(str + ret, "In-Reset ");
2375
2376 ret += sprintf(str + ret, "Change: ");
2377 if (portsc & PORT_CSC)
2378 ret += sprintf(str + ret, "CSC ");
2379 if (portsc & PORT_PEC)
2380 ret += sprintf(str + ret, "PEC ");
2381 if (portsc & PORT_WRC)
2382 ret += sprintf(str + ret, "WRC ");
2383 if (portsc & PORT_OCC)
2384 ret += sprintf(str + ret, "OCC ");
2385 if (portsc & PORT_RC)
2386 ret += sprintf(str + ret, "PRC ");
2387 if (portsc & PORT_PLC)
2388 ret += sprintf(str + ret, "PLC ");
2389 if (portsc & PORT_CEC)
2390 ret += sprintf(str + ret, "CEC ");
2391 if (portsc & PORT_CAS)
2392 ret += sprintf(str + ret, "CAS ");
2393
2394 ret += sprintf(str + ret, "Wake: ");
2395 if (portsc & PORT_WKCONN_E)
2396 ret += sprintf(str + ret, "WCE ");
2397 if (portsc & PORT_WKDISC_E)
2398 ret += sprintf(str + ret, "WDE ");
2399 if (portsc & PORT_WKOC_E)
2400 ret += sprintf(str + ret, "WOE ");
2401
2402 return str;
2403}
2404
2405static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2406{
2407 int ret = 0;
2408
2409 ret = sprintf(str, " 0x%08x", usbsts);
2410
2411 if (usbsts == ~(u32)0)
2412 return str;
2413
2414 if (usbsts & STS_HALT)
2415 ret += sprintf(str + ret, " HCHalted");
2416 if (usbsts & STS_FATAL)
2417 ret += sprintf(str + ret, " HSE");
2418 if (usbsts & STS_EINT)
2419 ret += sprintf(str + ret, " EINT");
2420 if (usbsts & STS_PORT)
2421 ret += sprintf(str + ret, " PCD");
2422 if (usbsts & STS_SAVE)
2423 ret += sprintf(str + ret, " SSS");
2424 if (usbsts & STS_RESTORE)
2425 ret += sprintf(str + ret, " RSS");
2426 if (usbsts & STS_SRE)
2427 ret += sprintf(str + ret, " SRE");
2428 if (usbsts & STS_CNR)
2429 ret += sprintf(str + ret, " CNR");
2430 if (usbsts & STS_HCE)
2431 ret += sprintf(str + ret, " HCE");
2432
2433 return str;
2434}
2435
2436static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2437{
2438 u8 ep;
2439 u16 stream;
2440 int ret;
2441
2442 ep = (doorbell & 0xff);
2443 stream = doorbell >> 16;
2444
2445 if (slot == 0) {
2446 sprintf(str, "Command Ring %d", doorbell);
2447 return str;
2448 }
2449 ret = sprintf(str, "Slot %d ", slot);
2450 if (ep > 0 && ep < 32)
2451 ret = sprintf(str + ret, "ep%d%s",
2452 ep / 2,
2453 ep % 2 ? "in" : "out");
2454 else if (ep == 0 || ep < 248)
2455 ret = sprintf(str + ret, "Reserved %d", ep);
2456 else
2457 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2458 if (stream)
2459 ret = sprintf(str + ret, " Stream %d", stream);
2460
2461 return str;
2462}
2463
2464static inline const char *xhci_ep_state_string(u8 state)
2465{
2466 switch (state) {
2467 case EP_STATE_DISABLED:
2468 return "disabled";
2469 case EP_STATE_RUNNING:
2470 return "running";
2471 case EP_STATE_HALTED:
2472 return "halted";
2473 case EP_STATE_STOPPED:
2474 return "stopped";
2475 case EP_STATE_ERROR:
2476 return "error";
2477 default:
2478 return "INVALID";
2479 }
2480}
2481
2482static inline const char *xhci_ep_type_string(u8 type)
2483{
2484 switch (type) {
2485 case ISOC_OUT_EP:
2486 return "Isoc OUT";
2487 case BULK_OUT_EP:
2488 return "Bulk OUT";
2489 case INT_OUT_EP:
2490 return "Int OUT";
2491 case CTRL_EP:
2492 return "Ctrl";
2493 case ISOC_IN_EP:
2494 return "Isoc IN";
2495 case BULK_IN_EP:
2496 return "Bulk IN";
2497 case INT_IN_EP:
2498 return "Int IN";
2499 default:
2500 return "INVALID";
2501 }
2502}
2503
2504static inline const char *xhci_decode_ep_context(char *str, u32 info,
2505 u32 info2, u64 deq, u32 tx_info)
2506{
2507 int ret;
2508
2509 u32 esit;
2510 u16 maxp;
2511 u16 avg;
2512
2513 u8 max_pstr;
2514 u8 ep_state;
2515 u8 interval;
2516 u8 ep_type;
2517 u8 burst;
2518 u8 cerr;
2519 u8 mult;
2520
2521 bool lsa;
2522 bool hid;
2523
2524 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2525 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2526
2527 ep_state = info & EP_STATE_MASK;
2528 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2529 interval = CTX_TO_EP_INTERVAL(info);
2530 mult = CTX_TO_EP_MULT(info) + 1;
2531 lsa = !!(info & EP_HAS_LSA);
2532
2533 cerr = (info2 & (3 << 1)) >> 1;
2534 ep_type = CTX_TO_EP_TYPE(info2);
2535 hid = !!(info2 & (1 << 7));
2536 burst = CTX_TO_MAX_BURST(info2);
2537 maxp = MAX_PACKET_DECODED(info2);
2538
2539 avg = EP_AVG_TRB_LENGTH(tx_info);
2540
2541 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2542 xhci_ep_state_string(ep_state), mult,
2543 max_pstr, lsa ? "LSA " : "");
2544
2545 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2546 (1 << interval) * 125, esit, cerr);
2547
2548 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2549 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2550 burst, maxp, deq);
2551
2552 ret += sprintf(str + ret, "avg trb len %d", avg);
2553
2554 return str;
2555}
2556
2557#endif /* __LINUX_XHCI_HCD_H */