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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
5 *
6 * derived from arch/x86/kvm/x86.c
7 *
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
10 */
11
12#include <linux/kvm_host.h>
13#include <linux/export.h>
14#include <linux/vmalloc.h>
15#include <linux/uaccess.h>
16#include <linux/sched/stat.h>
17
18#include <asm/processor.h>
19#include <asm/user.h>
20#include <asm/fpu/xstate.h>
21#include <asm/sgx.h>
22#include <asm/cpuid.h>
23#include "cpuid.h"
24#include "lapic.h"
25#include "mmu.h"
26#include "trace.h"
27#include "pmu.h"
28
29/*
30 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
31 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
32 */
33u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
34EXPORT_SYMBOL_GPL(kvm_cpu_caps);
35
36u32 xstate_required_size(u64 xstate_bv, bool compacted)
37{
38 int feature_bit = 0;
39 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
40
41 xstate_bv &= XFEATURE_MASK_EXTEND;
42 while (xstate_bv) {
43 if (xstate_bv & 0x1) {
44 u32 eax, ebx, ecx, edx, offset;
45 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
46 /* ECX[1]: 64B alignment in compacted form */
47 if (compacted)
48 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret;
49 else
50 offset = ebx;
51 ret = max(ret, offset + eax);
52 }
53
54 xstate_bv >>= 1;
55 feature_bit++;
56 }
57
58 return ret;
59}
60
61/*
62 * This one is tied to SSB in the user API, and not
63 * visible in /proc/cpuinfo.
64 */
65#define KVM_X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
66
67#define F feature_bit
68
69/* Scattered Flag - For features that are scattered by cpufeatures.h. */
70#define SF(name) \
71({ \
72 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \
73 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \
74})
75
76/*
77 * Magic value used by KVM when querying userspace-provided CPUID entries and
78 * doesn't care about the CPIUD index because the index of the function in
79 * question is not significant. Note, this magic value must have at least one
80 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find()
81 * to avoid false positives when processing guest CPUID input.
82 */
83#define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull
84
85static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
86 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index)
87{
88 struct kvm_cpuid_entry2 *e;
89 int i;
90
91 for (i = 0; i < nent; i++) {
92 e = &entries[i];
93
94 if (e->function != function)
95 continue;
96
97 /*
98 * If the index isn't significant, use the first entry with a
99 * matching function. It's userspace's responsibilty to not
100 * provide "duplicate" entries in all cases.
101 */
102 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)
103 return e;
104
105
106 /*
107 * Similarly, use the first matching entry if KVM is doing a
108 * lookup (as opposed to emulating CPUID) for a function that's
109 * architecturally defined as not having a significant index.
110 */
111 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) {
112 /*
113 * Direct lookups from KVM should not diverge from what
114 * KVM defines internally (the architectural behavior).
115 */
116 WARN_ON_ONCE(cpuid_function_is_indexed(function));
117 return e;
118 }
119 }
120
121 return NULL;
122}
123
124static int kvm_check_cpuid(struct kvm_vcpu *vcpu,
125 struct kvm_cpuid_entry2 *entries,
126 int nent)
127{
128 struct kvm_cpuid_entry2 *best;
129 u64 xfeatures;
130
131 /*
132 * The existing code assumes virtual address is 48-bit or 57-bit in the
133 * canonical address checks; exit if it is ever changed.
134 */
135 best = cpuid_entry2_find(entries, nent, 0x80000008,
136 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
137 if (best) {
138 int vaddr_bits = (best->eax & 0xff00) >> 8;
139
140 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
141 return -EINVAL;
142 }
143
144 /*
145 * Exposing dynamic xfeatures to the guest requires additional
146 * enabling in the FPU, e.g. to expand the guest XSAVE state size.
147 */
148 best = cpuid_entry2_find(entries, nent, 0xd, 0);
149 if (!best)
150 return 0;
151
152 xfeatures = best->eax | ((u64)best->edx << 32);
153 xfeatures &= XFEATURE_MASK_USER_DYNAMIC;
154 if (!xfeatures)
155 return 0;
156
157 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures);
158}
159
160/* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */
161static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
162 int nent)
163{
164 struct kvm_cpuid_entry2 *orig;
165 int i;
166
167 if (nent != vcpu->arch.cpuid_nent)
168 return -EINVAL;
169
170 for (i = 0; i < nent; i++) {
171 orig = &vcpu->arch.cpuid_entries[i];
172 if (e2[i].function != orig->function ||
173 e2[i].index != orig->index ||
174 e2[i].flags != orig->flags ||
175 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx ||
176 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx)
177 return -EINVAL;
178 }
179
180 return 0;
181}
182
183static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu)
184{
185 u32 function;
186 struct kvm_cpuid_entry2 *entry;
187
188 vcpu->arch.kvm_cpuid_base = 0;
189
190 for_each_possible_hypervisor_cpuid_base(function) {
191 entry = kvm_find_cpuid_entry(vcpu, function);
192
193 if (entry) {
194 u32 signature[3];
195
196 signature[0] = entry->ebx;
197 signature[1] = entry->ecx;
198 signature[2] = entry->edx;
199
200 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE));
201 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) {
202 vcpu->arch.kvm_cpuid_base = function;
203 break;
204 }
205 }
206 }
207}
208
209static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu,
210 struct kvm_cpuid_entry2 *entries, int nent)
211{
212 u32 base = vcpu->arch.kvm_cpuid_base;
213
214 if (!base)
215 return NULL;
216
217 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES,
218 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
219}
220
221static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu)
222{
223 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries,
224 vcpu->arch.cpuid_nent);
225}
226
227void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
228{
229 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu);
230
231 /*
232 * save the feature bitmap to avoid cpuid lookup for every PV
233 * operation
234 */
235 if (best)
236 vcpu->arch.pv_cpuid.features = best->eax;
237}
238
239/*
240 * Calculate guest's supported XCR0 taking into account guest CPUID data and
241 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0).
242 */
243static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
244{
245 struct kvm_cpuid_entry2 *best;
246
247 best = cpuid_entry2_find(entries, nent, 0xd, 0);
248 if (!best)
249 return 0;
250
251 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0;
252}
253
254static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
255 int nent)
256{
257 struct kvm_cpuid_entry2 *best;
258 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent);
259
260 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
261 if (best) {
262 /* Update OSXSAVE bit */
263 if (boot_cpu_has(X86_FEATURE_XSAVE))
264 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
265 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
266
267 cpuid_entry_change(best, X86_FEATURE_APIC,
268 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
269 }
270
271 best = cpuid_entry2_find(entries, nent, 7, 0);
272 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
273 cpuid_entry_change(best, X86_FEATURE_OSPKE,
274 kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
275
276 best = cpuid_entry2_find(entries, nent, 0xD, 0);
277 if (best)
278 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
279
280 best = cpuid_entry2_find(entries, nent, 0xD, 1);
281 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
282 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
283 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
284
285 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent);
286 if (kvm_hlt_in_guest(vcpu->kvm) && best &&
287 (best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
288 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
289
290 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
291 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
292 if (best)
293 cpuid_entry_change(best, X86_FEATURE_MWAIT,
294 vcpu->arch.ia32_misc_enable_msr &
295 MSR_IA32_MISC_ENABLE_MWAIT);
296 }
297
298 /*
299 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate
300 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's
301 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO
302 * at the time of EENTER, thus adjust the allowed XFRM by the guest's
303 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to
304 * '1' even on CPUs that don't support XSAVE.
305 */
306 best = cpuid_entry2_find(entries, nent, 0x12, 0x1);
307 if (best) {
308 best->ecx &= guest_supported_xcr0 & 0xffffffff;
309 best->edx &= guest_supported_xcr0 >> 32;
310 best->ecx |= XFEATURE_MASK_FPSSE;
311 }
312}
313
314void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
315{
316 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
317}
318EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime);
319
320static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent)
321{
322 struct kvm_cpuid_entry2 *entry;
323
324 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE,
325 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
326 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX;
327}
328
329static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
330{
331 struct kvm_lapic *apic = vcpu->arch.apic;
332 struct kvm_cpuid_entry2 *best;
333
334 best = kvm_find_cpuid_entry(vcpu, 1);
335 if (best && apic) {
336 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
337 apic->lapic_timer.timer_mode_mask = 3 << 17;
338 else
339 apic->lapic_timer.timer_mode_mask = 1 << 17;
340
341 kvm_apic_set_version(vcpu);
342 }
343
344 vcpu->arch.guest_supported_xcr0 =
345 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
346
347 /*
348 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
349 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
350 * supported by the host.
351 */
352 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 |
353 XFEATURE_MASK_FPSSE;
354
355 kvm_update_pv_runtime(vcpu);
356
357 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
358 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
359
360 kvm_pmu_refresh(vcpu);
361 vcpu->arch.cr4_guest_rsvd_bits =
362 __cr4_reserved_bits(guest_cpuid_has, vcpu);
363
364 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries,
365 vcpu->arch.cpuid_nent));
366
367 /* Invoke the vendor callback only after the above state is updated. */
368 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu);
369
370 /*
371 * Except for the MMU, which needs to do its thing any vendor specific
372 * adjustments to the reserved GPA bits.
373 */
374 kvm_mmu_after_set_cpuid(vcpu);
375}
376
377int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
378{
379 struct kvm_cpuid_entry2 *best;
380
381 best = kvm_find_cpuid_entry(vcpu, 0x80000000);
382 if (!best || best->eax < 0x80000008)
383 goto not_found;
384 best = kvm_find_cpuid_entry(vcpu, 0x80000008);
385 if (best)
386 return best->eax & 0xff;
387not_found:
388 return 36;
389}
390
391/*
392 * This "raw" version returns the reserved GPA bits without any adjustments for
393 * encryption technologies that usurp bits. The raw mask should be used if and
394 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs.
395 */
396u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu)
397{
398 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
399}
400
401static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
402 int nent)
403{
404 int r;
405
406 __kvm_update_cpuid_runtime(vcpu, e2, nent);
407
408 /*
409 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
410 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
411 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
412 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with
413 * the core vCPU model on the fly. It would've been better to forbid any
414 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately
415 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do
416 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check
417 * whether the supplied CPUID data is equal to what's already set.
418 */
419 if (vcpu->arch.last_vmentry_cpu != -1) {
420 r = kvm_cpuid_check_equal(vcpu, e2, nent);
421 if (r)
422 return r;
423
424 kvfree(e2);
425 return 0;
426 }
427
428 if (kvm_cpuid_has_hyperv(e2, nent)) {
429 r = kvm_hv_vcpu_init(vcpu);
430 if (r)
431 return r;
432 }
433
434 r = kvm_check_cpuid(vcpu, e2, nent);
435 if (r)
436 return r;
437
438 kvfree(vcpu->arch.cpuid_entries);
439 vcpu->arch.cpuid_entries = e2;
440 vcpu->arch.cpuid_nent = nent;
441
442 kvm_update_kvm_cpuid_base(vcpu);
443 kvm_vcpu_after_set_cpuid(vcpu);
444
445 return 0;
446}
447
448/* when an old userspace process fills a new kernel module */
449int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
450 struct kvm_cpuid *cpuid,
451 struct kvm_cpuid_entry __user *entries)
452{
453 int r, i;
454 struct kvm_cpuid_entry *e = NULL;
455 struct kvm_cpuid_entry2 *e2 = NULL;
456
457 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
458 return -E2BIG;
459
460 if (cpuid->nent) {
461 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent));
462 if (IS_ERR(e))
463 return PTR_ERR(e);
464
465 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
466 if (!e2) {
467 r = -ENOMEM;
468 goto out_free_cpuid;
469 }
470 }
471 for (i = 0; i < cpuid->nent; i++) {
472 e2[i].function = e[i].function;
473 e2[i].eax = e[i].eax;
474 e2[i].ebx = e[i].ebx;
475 e2[i].ecx = e[i].ecx;
476 e2[i].edx = e[i].edx;
477 e2[i].index = 0;
478 e2[i].flags = 0;
479 e2[i].padding[0] = 0;
480 e2[i].padding[1] = 0;
481 e2[i].padding[2] = 0;
482 }
483
484 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
485 if (r)
486 kvfree(e2);
487
488out_free_cpuid:
489 kvfree(e);
490
491 return r;
492}
493
494int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
495 struct kvm_cpuid2 *cpuid,
496 struct kvm_cpuid_entry2 __user *entries)
497{
498 struct kvm_cpuid_entry2 *e2 = NULL;
499 int r;
500
501 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
502 return -E2BIG;
503
504 if (cpuid->nent) {
505 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent));
506 if (IS_ERR(e2))
507 return PTR_ERR(e2);
508 }
509
510 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
511 if (r)
512 kvfree(e2);
513
514 return r;
515}
516
517int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
518 struct kvm_cpuid2 *cpuid,
519 struct kvm_cpuid_entry2 __user *entries)
520{
521 int r;
522
523 r = -E2BIG;
524 if (cpuid->nent < vcpu->arch.cpuid_nent)
525 goto out;
526 r = -EFAULT;
527 if (copy_to_user(entries, vcpu->arch.cpuid_entries,
528 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
529 goto out;
530 return 0;
531
532out:
533 cpuid->nent = vcpu->arch.cpuid_nent;
534 return r;
535}
536
537/* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */
538static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf)
539{
540 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
541 struct kvm_cpuid_entry2 entry;
542
543 reverse_cpuid_check(leaf);
544
545 cpuid_count(cpuid.function, cpuid.index,
546 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
547
548 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
549}
550
551static __always_inline
552void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask)
553{
554 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */
555 BUILD_BUG_ON(leaf < NCAPINTS);
556
557 kvm_cpu_caps[leaf] = mask;
558
559 __kvm_cpu_cap_mask(leaf);
560}
561
562static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
563{
564 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */
565 BUILD_BUG_ON(leaf >= NCAPINTS);
566
567 kvm_cpu_caps[leaf] &= mask;
568
569 __kvm_cpu_cap_mask(leaf);
570}
571
572void kvm_set_cpu_caps(void)
573{
574#ifdef CONFIG_X86_64
575 unsigned int f_gbpages = F(GBPAGES);
576 unsigned int f_lm = F(LM);
577 unsigned int f_xfd = F(XFD);
578#else
579 unsigned int f_gbpages = 0;
580 unsigned int f_lm = 0;
581 unsigned int f_xfd = 0;
582#endif
583 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
584
585 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) >
586 sizeof(boot_cpu_data.x86_capability));
587
588 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
589 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
590
591 kvm_cpu_cap_mask(CPUID_1_ECX,
592 /*
593 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
594 * advertised to guests via CPUID!
595 */
596 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
597 0 /* DS-CPL, VMX, SMX, EST */ |
598 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
599 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
600 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
601 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
602 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
603 F(F16C) | F(RDRAND)
604 );
605 /* KVM emulates x2apic in software irrespective of host support. */
606 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
607
608 kvm_cpu_cap_mask(CPUID_1_EDX,
609 F(FPU) | F(VME) | F(DE) | F(PSE) |
610 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
611 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
612 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
613 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
614 0 /* Reserved, DS, ACPI */ | F(MMX) |
615 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
616 0 /* HTT, TM, Reserved, PBE */
617 );
618
619 kvm_cpu_cap_mask(CPUID_7_0_EBX,
620 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
621 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
622 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
623 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
624 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
625 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
626 F(AVX512VL));
627
628 kvm_cpu_cap_mask(CPUID_7_ECX,
629 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
630 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
631 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
632 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
633 F(SGX_LC) | F(BUS_LOCK_DETECT)
634 );
635 /* Set LA57 based on hardware capability. */
636 if (cpuid_ecx(7) & F(LA57))
637 kvm_cpu_cap_set(X86_FEATURE_LA57);
638
639 /*
640 * PKU not yet implemented for shadow paging and requires OSPKE
641 * to be set on the host. Clear it if that is not the case
642 */
643 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
644 kvm_cpu_cap_clear(X86_FEATURE_PKU);
645
646 kvm_cpu_cap_mask(CPUID_7_EDX,
647 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
648 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
649 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
650 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
651 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16)
652 );
653
654 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
655 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
656 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
657
658 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
659 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
660 if (boot_cpu_has(X86_FEATURE_STIBP))
661 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
662 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
663 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
664
665 kvm_cpu_cap_mask(CPUID_7_1_EAX,
666 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16) |
667 F(AVX_IFMA)
668 );
669
670 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,
671 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI)
672 );
673
674 kvm_cpu_cap_mask(CPUID_D_1_EAX,
675 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
676 );
677
678 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX,
679 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA)
680 );
681
682 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
683 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
684 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
685 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
686 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
687 F(TOPOEXT) | 0 /* PERFCTR_CORE */
688 );
689
690 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
691 F(FPU) | F(VME) | F(DE) | F(PSE) |
692 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
693 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
694 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
695 F(PAT) | F(PSE36) | 0 /* Reserved */ |
696 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
697 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
698 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
699 );
700
701 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
702 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
703
704 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
705 F(CLZERO) | F(XSAVEERPTR) |
706 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
707 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
708 __feature_bit(KVM_X86_FEATURE_AMD_PSFD)
709 );
710
711 /*
712 * AMD has separate bits for each SPEC_CTRL bit.
713 * arch/x86/kernel/cpu/bugs.c is kind enough to
714 * record that in cpufeatures so use them.
715 */
716 if (boot_cpu_has(X86_FEATURE_IBPB))
717 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
718 if (boot_cpu_has(X86_FEATURE_IBRS))
719 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
720 if (boot_cpu_has(X86_FEATURE_STIBP))
721 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
722 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
723 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
724 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
725 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
726 /*
727 * The preference is to use SPEC CTRL MSR instead of the
728 * VIRT_SPEC MSR.
729 */
730 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
731 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
732 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
733
734 /*
735 * Hide all SVM features by default, SVM will set the cap bits for
736 * features it emulates and/or exposes for L1.
737 */
738 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
739
740 kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
741 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
742 F(SME_COHERENT));
743
744 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
745 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
746 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
747 F(PMM) | F(PMM_EN)
748 );
749
750 /*
751 * Hide RDTSCP and RDPID if either feature is reported as supported but
752 * probing MSR_TSC_AUX failed. This is purely a sanity check and
753 * should never happen, but the guest will likely crash if RDTSCP or
754 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
755 * the past. For example, the sanity check may fire if this instance of
756 * KVM is running as L1 on top of an older, broken KVM.
757 */
758 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) ||
759 kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
760 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
761 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
762 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
763 }
764}
765EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
766
767struct kvm_cpuid_array {
768 struct kvm_cpuid_entry2 *entries;
769 int maxnent;
770 int nent;
771};
772
773static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array)
774{
775 if (array->nent >= array->maxnent)
776 return NULL;
777
778 return &array->entries[array->nent++];
779}
780
781static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
782 u32 function, u32 index)
783{
784 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array);
785
786 if (!entry)
787 return NULL;
788
789 memset(entry, 0, sizeof(*entry));
790 entry->function = function;
791 entry->index = index;
792 switch (function & 0xC0000000) {
793 case 0x40000000:
794 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */
795 return entry;
796
797 case 0x80000000:
798 /*
799 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which
800 * would result in out-of-bounds calls to do_host_cpuid.
801 */
802 {
803 static int max_cpuid_80000000;
804 if (!READ_ONCE(max_cpuid_80000000))
805 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000));
806 if (function > READ_ONCE(max_cpuid_80000000))
807 return entry;
808 }
809 break;
810
811 default:
812 break;
813 }
814
815 cpuid_count(entry->function, entry->index,
816 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
817
818 if (cpuid_function_is_indexed(function))
819 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
820
821 return entry;
822}
823
824static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
825{
826 struct kvm_cpuid_entry2 *entry;
827
828 if (array->nent >= array->maxnent)
829 return -E2BIG;
830
831 entry = &array->entries[array->nent];
832 entry->function = func;
833 entry->index = 0;
834 entry->flags = 0;
835
836 switch (func) {
837 case 0:
838 entry->eax = 7;
839 ++array->nent;
840 break;
841 case 1:
842 entry->ecx = F(MOVBE);
843 ++array->nent;
844 break;
845 case 7:
846 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
847 entry->eax = 0;
848 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
849 entry->ecx = F(RDPID);
850 ++array->nent;
851 break;
852 default:
853 break;
854 }
855
856 return 0;
857}
858
859static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
860{
861 struct kvm_cpuid_entry2 *entry;
862 int r, i, max_idx;
863
864 /* all calls to cpuid_count() should be made on the same cpu */
865 get_cpu();
866
867 r = -E2BIG;
868
869 entry = do_host_cpuid(array, function, 0);
870 if (!entry)
871 goto out;
872
873 switch (function) {
874 case 0:
875 /* Limited to the highest leaf implemented in KVM. */
876 entry->eax = min(entry->eax, 0x1fU);
877 break;
878 case 1:
879 cpuid_entry_override(entry, CPUID_1_EDX);
880 cpuid_entry_override(entry, CPUID_1_ECX);
881 break;
882 case 2:
883 /*
884 * On ancient CPUs, function 2 entries are STATEFUL. That is,
885 * CPUID(function=2, index=0) may return different results each
886 * time, with the least-significant byte in EAX enumerating the
887 * number of times software should do CPUID(2, 0).
888 *
889 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
890 * idiotic. Intel's SDM states that EAX & 0xff "will always
891 * return 01H. Software should ignore this value and not
892 * interpret it as an informational descriptor", while AMD's
893 * APM states that CPUID(2) is reserved.
894 *
895 * WARN if a frankenstein CPU that supports virtualization and
896 * a stateful CPUID.0x2 is encountered.
897 */
898 WARN_ON_ONCE((entry->eax & 0xff) > 1);
899 break;
900 /* functions 4 and 0x8000001d have additional index. */
901 case 4:
902 case 0x8000001d:
903 /*
904 * Read entries until the cache type in the previous entry is
905 * zero, i.e. indicates an invalid entry.
906 */
907 for (i = 1; entry->eax & 0x1f; ++i) {
908 entry = do_host_cpuid(array, function, i);
909 if (!entry)
910 goto out;
911 }
912 break;
913 case 6: /* Thermal management */
914 entry->eax = 0x4; /* allow ARAT */
915 entry->ebx = 0;
916 entry->ecx = 0;
917 entry->edx = 0;
918 break;
919 /* function 7 has additional index. */
920 case 7:
921 entry->eax = min(entry->eax, 1u);
922 cpuid_entry_override(entry, CPUID_7_0_EBX);
923 cpuid_entry_override(entry, CPUID_7_ECX);
924 cpuid_entry_override(entry, CPUID_7_EDX);
925
926 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
927 if (entry->eax == 1) {
928 entry = do_host_cpuid(array, function, 1);
929 if (!entry)
930 goto out;
931
932 cpuid_entry_override(entry, CPUID_7_1_EAX);
933 cpuid_entry_override(entry, CPUID_7_1_EDX);
934 entry->ebx = 0;
935 entry->ecx = 0;
936 }
937 break;
938 case 0xa: { /* Architectural Performance Monitoring */
939 union cpuid10_eax eax;
940 union cpuid10_edx edx;
941
942 if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
943 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
944 break;
945 }
946
947 eax.split.version_id = kvm_pmu_cap.version;
948 eax.split.num_counters = kvm_pmu_cap.num_counters_gp;
949 eax.split.bit_width = kvm_pmu_cap.bit_width_gp;
950 eax.split.mask_length = kvm_pmu_cap.events_mask_len;
951 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed;
952 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
953
954 if (kvm_pmu_cap.version)
955 edx.split.anythread_deprecated = 1;
956 edx.split.reserved1 = 0;
957 edx.split.reserved2 = 0;
958
959 entry->eax = eax.full;
960 entry->ebx = kvm_pmu_cap.events_mask;
961 entry->ecx = 0;
962 entry->edx = edx.full;
963 break;
964 }
965 case 0x1f:
966 case 0xb:
967 /*
968 * No topology; a valid topology is indicated by the presence
969 * of subleaf 1.
970 */
971 entry->eax = entry->ebx = entry->ecx = 0;
972 break;
973 case 0xd: {
974 u64 permitted_xcr0 = kvm_caps.supported_xcr0 & xstate_get_guest_group_perm();
975 u64 permitted_xss = kvm_caps.supported_xss;
976
977 entry->eax &= permitted_xcr0;
978 entry->ebx = xstate_required_size(permitted_xcr0, false);
979 entry->ecx = entry->ebx;
980 entry->edx &= permitted_xcr0 >> 32;
981 if (!permitted_xcr0)
982 break;
983
984 entry = do_host_cpuid(array, function, 1);
985 if (!entry)
986 goto out;
987
988 cpuid_entry_override(entry, CPUID_D_1_EAX);
989 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
990 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss,
991 true);
992 else {
993 WARN_ON_ONCE(permitted_xss != 0);
994 entry->ebx = 0;
995 }
996 entry->ecx &= permitted_xss;
997 entry->edx &= permitted_xss >> 32;
998
999 for (i = 2; i < 64; ++i) {
1000 bool s_state;
1001 if (permitted_xcr0 & BIT_ULL(i))
1002 s_state = false;
1003 else if (permitted_xss & BIT_ULL(i))
1004 s_state = true;
1005 else
1006 continue;
1007
1008 entry = do_host_cpuid(array, function, i);
1009 if (!entry)
1010 goto out;
1011
1012 /*
1013 * The supported check above should have filtered out
1014 * invalid sub-leafs. Only valid sub-leafs should
1015 * reach this point, and they should have a non-zero
1016 * save state size. Furthermore, check whether the
1017 * processor agrees with permitted_xcr0/permitted_xss
1018 * on whether this is an XCR0- or IA32_XSS-managed area.
1019 */
1020 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
1021 --array->nent;
1022 continue;
1023 }
1024
1025 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
1026 entry->ecx &= ~BIT_ULL(2);
1027 entry->edx = 0;
1028 }
1029 break;
1030 }
1031 case 0x12:
1032 /* Intel SGX */
1033 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) {
1034 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1035 break;
1036 }
1037
1038 /*
1039 * Index 0: Sub-features, MISCSELECT (a.k.a extended features)
1040 * and max enclave sizes. The SGX sub-features and MISCSELECT
1041 * are restricted by kernel and KVM capabilities (like most
1042 * feature flags), while enclave size is unrestricted.
1043 */
1044 cpuid_entry_override(entry, CPUID_12_EAX);
1045 entry->ebx &= SGX_MISC_EXINFO;
1046
1047 entry = do_host_cpuid(array, function, 1);
1048 if (!entry)
1049 goto out;
1050
1051 /*
1052 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la
1053 * feature flags. Advertise all supported flags, including
1054 * privileged attributes that require explicit opt-in from
1055 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is
1056 * expected to derive it from supported XCR0.
1057 */
1058 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK;
1059 entry->ebx &= 0;
1060 break;
1061 /* Intel PT */
1062 case 0x14:
1063 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
1064 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1065 break;
1066 }
1067
1068 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1069 if (!do_host_cpuid(array, function, i))
1070 goto out;
1071 }
1072 break;
1073 /* Intel AMX TILE */
1074 case 0x1d:
1075 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1076 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1077 break;
1078 }
1079
1080 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1081 if (!do_host_cpuid(array, function, i))
1082 goto out;
1083 }
1084 break;
1085 case 0x1e: /* TMUL information */
1086 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1087 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1088 break;
1089 }
1090 break;
1091 case KVM_CPUID_SIGNATURE: {
1092 const u32 *sigptr = (const u32 *)KVM_SIGNATURE;
1093 entry->eax = KVM_CPUID_FEATURES;
1094 entry->ebx = sigptr[0];
1095 entry->ecx = sigptr[1];
1096 entry->edx = sigptr[2];
1097 break;
1098 }
1099 case KVM_CPUID_FEATURES:
1100 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1101 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1102 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1103 (1 << KVM_FEATURE_ASYNC_PF) |
1104 (1 << KVM_FEATURE_PV_EOI) |
1105 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
1106 (1 << KVM_FEATURE_PV_UNHALT) |
1107 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
1108 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
1109 (1 << KVM_FEATURE_PV_SEND_IPI) |
1110 (1 << KVM_FEATURE_POLL_CONTROL) |
1111 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
1112 (1 << KVM_FEATURE_ASYNC_PF_INT);
1113
1114 if (sched_info_on())
1115 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
1116
1117 entry->ebx = 0;
1118 entry->ecx = 0;
1119 entry->edx = 0;
1120 break;
1121 case 0x80000000:
1122 entry->eax = min(entry->eax, 0x80000021);
1123 /*
1124 * Serializing LFENCE is reported in a multitude of ways, and
1125 * NullSegClearsBase is not reported in CPUID on Zen2; help
1126 * userspace by providing the CPUID leaf ourselves.
1127 *
1128 * However, only do it if the host has CPUID leaf 0x8000001d.
1129 * QEMU thinks that it can query the host blindly for that
1130 * CPUID leaf if KVM reports that it supports 0x8000001d or
1131 * above. The processor merrily returns values from the
1132 * highest Intel leaf which QEMU tries to use as the guest's
1133 * 0x8000001d. Even worse, this can result in an infinite
1134 * loop if said highest leaf has no subleaves indexed by ECX.
1135 */
1136 if (entry->eax >= 0x8000001d &&
1137 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
1138 || !static_cpu_has_bug(X86_BUG_NULL_SEG)))
1139 entry->eax = max(entry->eax, 0x80000021);
1140 break;
1141 case 0x80000001:
1142 entry->ebx &= ~GENMASK(27, 16);
1143 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
1144 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
1145 break;
1146 case 0x80000006:
1147 /* Drop reserved bits, pass host L2 cache and TLB info. */
1148 entry->edx &= ~GENMASK(17, 16);
1149 break;
1150 case 0x80000007: /* Advanced power management */
1151 /* invariant TSC is CPUID.80000007H:EDX[8] */
1152 entry->edx &= (1 << 8);
1153 /* mask against host */
1154 entry->edx &= boot_cpu_data.x86_power;
1155 entry->eax = entry->ebx = entry->ecx = 0;
1156 break;
1157 case 0x80000008: {
1158 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
1159 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
1160 unsigned phys_as = entry->eax & 0xff;
1161
1162 /*
1163 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
1164 * the guest operates in the same PA space as the host, i.e.
1165 * reductions in MAXPHYADDR for memory encryption affect shadow
1166 * paging, too.
1167 *
1168 * If TDP is enabled but an explicit guest MAXPHYADDR is not
1169 * provided, use the raw bare metal MAXPHYADDR as reductions to
1170 * the HPAs do not affect GPAs.
1171 */
1172 if (!tdp_enabled)
1173 g_phys_as = boot_cpu_data.x86_phys_bits;
1174 else if (!g_phys_as)
1175 g_phys_as = phys_as;
1176
1177 entry->eax = g_phys_as | (virt_as << 8);
1178 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));
1179 entry->edx = 0;
1180 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
1181 break;
1182 }
1183 case 0x8000000A:
1184 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
1185 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1186 break;
1187 }
1188 entry->eax = 1; /* SVM revision 1 */
1189 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
1190 ASID emulation to nested SVM */
1191 entry->ecx = 0; /* Reserved */
1192 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
1193 break;
1194 case 0x80000019:
1195 entry->ecx = entry->edx = 0;
1196 break;
1197 case 0x8000001a:
1198 entry->eax &= GENMASK(2, 0);
1199 entry->ebx = entry->ecx = entry->edx = 0;
1200 break;
1201 case 0x8000001e:
1202 /* Do not return host topology information. */
1203 entry->eax = entry->ebx = entry->ecx = 0;
1204 entry->edx = 0; /* reserved */
1205 break;
1206 case 0x8000001F:
1207 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
1208 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1209 } else {
1210 cpuid_entry_override(entry, CPUID_8000_001F_EAX);
1211 /* Clear NumVMPL since KVM does not support VMPL. */
1212 entry->ebx &= ~GENMASK(31, 12);
1213 /*
1214 * Enumerate '0' for "PA bits reduction", the adjusted
1215 * MAXPHYADDR is enumerated directly (see 0x80000008).
1216 */
1217 entry->ebx &= ~GENMASK(11, 6);
1218 }
1219 break;
1220 case 0x80000020:
1221 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1222 break;
1223 case 0x80000021:
1224 entry->ebx = entry->ecx = entry->edx = 0;
1225 /*
1226 * Pass down these bits:
1227 * EAX 0 NNDBP, Processor ignores nested data breakpoints
1228 * EAX 2 LAS, LFENCE always serializing
1229 * EAX 6 NSCB, Null selector clear base
1230 *
1231 * Other defined bits are for MSRs that KVM does not expose:
1232 * EAX 3 SPCL, SMM page configuration lock
1233 * EAX 13 PCMSR, Prefetch control MSR
1234 *
1235 * KVM doesn't support SMM_CTL.
1236 * EAX 9 SMM_CTL MSR is not supported
1237 */
1238 entry->eax &= BIT(0) | BIT(2) | BIT(6);
1239 entry->eax |= BIT(9);
1240 if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
1241 entry->eax |= BIT(2);
1242 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
1243 entry->eax |= BIT(6);
1244 break;
1245 /*Add support for Centaur's CPUID instruction*/
1246 case 0xC0000000:
1247 /*Just support up to 0xC0000004 now*/
1248 entry->eax = min(entry->eax, 0xC0000004);
1249 break;
1250 case 0xC0000001:
1251 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
1252 break;
1253 case 3: /* Processor serial number */
1254 case 5: /* MONITOR/MWAIT */
1255 case 0xC0000002:
1256 case 0xC0000003:
1257 case 0xC0000004:
1258 default:
1259 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1260 break;
1261 }
1262
1263 r = 0;
1264
1265out:
1266 put_cpu();
1267
1268 return r;
1269}
1270
1271static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1272 unsigned int type)
1273{
1274 if (type == KVM_GET_EMULATED_CPUID)
1275 return __do_cpuid_func_emulated(array, func);
1276
1277 return __do_cpuid_func(array, func);
1278}
1279
1280#define CENTAUR_CPUID_SIGNATURE 0xC0000000
1281
1282static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1283 unsigned int type)
1284{
1285 u32 limit;
1286 int r;
1287
1288 if (func == CENTAUR_CPUID_SIGNATURE &&
1289 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
1290 return 0;
1291
1292 r = do_cpuid_func(array, func, type);
1293 if (r)
1294 return r;
1295
1296 limit = array->entries[array->nent - 1].eax;
1297 for (func = func + 1; func <= limit; ++func) {
1298 r = do_cpuid_func(array, func, type);
1299 if (r)
1300 break;
1301 }
1302
1303 return r;
1304}
1305
1306static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
1307 __u32 num_entries, unsigned int ioctl_type)
1308{
1309 int i;
1310 __u32 pad[3];
1311
1312 if (ioctl_type != KVM_GET_EMULATED_CPUID)
1313 return false;
1314
1315 /*
1316 * We want to make sure that ->padding is being passed clean from
1317 * userspace in case we want to use it for something in the future.
1318 *
1319 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
1320 * have to give ourselves satisfied only with the emulated side. /me
1321 * sheds a tear.
1322 */
1323 for (i = 0; i < num_entries; i++) {
1324 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
1325 return true;
1326
1327 if (pad[0] || pad[1] || pad[2])
1328 return true;
1329 }
1330 return false;
1331}
1332
1333int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
1334 struct kvm_cpuid_entry2 __user *entries,
1335 unsigned int type)
1336{
1337 static const u32 funcs[] = {
1338 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
1339 };
1340
1341 struct kvm_cpuid_array array = {
1342 .nent = 0,
1343 };
1344 int r, i;
1345
1346 if (cpuid->nent < 1)
1347 return -E2BIG;
1348 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1349 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1350
1351 if (sanity_check_entries(entries, cpuid->nent, type))
1352 return -EINVAL;
1353
1354 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL);
1355 if (!array.entries)
1356 return -ENOMEM;
1357
1358 array.maxnent = cpuid->nent;
1359
1360 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
1361 r = get_cpuid_func(&array, funcs[i], type);
1362 if (r)
1363 goto out_free;
1364 }
1365 cpuid->nent = array.nent;
1366
1367 if (copy_to_user(entries, array.entries,
1368 array.nent * sizeof(struct kvm_cpuid_entry2)))
1369 r = -EFAULT;
1370
1371out_free:
1372 kvfree(array.entries);
1373 return r;
1374}
1375
1376struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu,
1377 u32 function, u32 index)
1378{
1379 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1380 function, index);
1381}
1382EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index);
1383
1384struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
1385 u32 function)
1386{
1387 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1388 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
1389}
1390EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
1391
1392/*
1393 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
1394 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
1395 * returns all zeroes for any undefined leaf, whether or not the leaf is in
1396 * range. Centaur/VIA follows Intel semantics.
1397 *
1398 * A leaf is considered out-of-range if its function is higher than the maximum
1399 * supported leaf of its associated class or if its associated class does not
1400 * exist.
1401 *
1402 * There are three primary classes to be considered, with their respective
1403 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
1404 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
1405 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
1406 *
1407 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
1408 * - Hypervisor: 0x40000000 - 0x4fffffff
1409 * - Extended: 0x80000000 - 0xbfffffff
1410 * - Centaur: 0xc0000000 - 0xcfffffff
1411 *
1412 * The Hypervisor class is further subdivided into sub-classes that each act as
1413 * their own independent class associated with a 0x100 byte range. E.g. if Qemu
1414 * is advertising support for both HyperV and KVM, the resulting Hypervisor
1415 * CPUID sub-classes are:
1416 *
1417 * - HyperV: 0x40000000 - 0x400000ff
1418 * - KVM: 0x40000100 - 0x400001ff
1419 */
1420static struct kvm_cpuid_entry2 *
1421get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
1422{
1423 struct kvm_cpuid_entry2 *basic, *class;
1424 u32 function = *fn_ptr;
1425
1426 basic = kvm_find_cpuid_entry(vcpu, 0);
1427 if (!basic)
1428 return NULL;
1429
1430 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
1431 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
1432 return NULL;
1433
1434 if (function >= 0x40000000 && function <= 0x4fffffff)
1435 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00);
1436 else if (function >= 0xc0000000)
1437 class = kvm_find_cpuid_entry(vcpu, 0xc0000000);
1438 else
1439 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000);
1440
1441 if (class && function <= class->eax)
1442 return NULL;
1443
1444 /*
1445 * Leaf specific adjustments are also applied when redirecting to the
1446 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1447 * entry for CPUID.0xb.index (see below), then the output value for EDX
1448 * needs to be pulled from CPUID.0xb.1.
1449 */
1450 *fn_ptr = basic->eax;
1451
1452 /*
1453 * The class does not exist or the requested function is out of range;
1454 * the effective CPUID entry is the max basic leaf. Note, the index of
1455 * the original requested leaf is observed!
1456 */
1457 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index);
1458}
1459
1460bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1461 u32 *ecx, u32 *edx, bool exact_only)
1462{
1463 u32 orig_function = *eax, function = *eax, index = *ecx;
1464 struct kvm_cpuid_entry2 *entry;
1465 bool exact, used_max_basic = false;
1466
1467 entry = kvm_find_cpuid_entry_index(vcpu, function, index);
1468 exact = !!entry;
1469
1470 if (!entry && !exact_only) {
1471 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1472 used_max_basic = !!entry;
1473 }
1474
1475 if (entry) {
1476 *eax = entry->eax;
1477 *ebx = entry->ebx;
1478 *ecx = entry->ecx;
1479 *edx = entry->edx;
1480 if (function == 7 && index == 0) {
1481 u64 data;
1482 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1483 (data & TSX_CTRL_CPUID_CLEAR))
1484 *ebx &= ~(F(RTM) | F(HLE));
1485 }
1486 } else {
1487 *eax = *ebx = *ecx = *edx = 0;
1488 /*
1489 * When leaf 0BH or 1FH is defined, CL is pass-through
1490 * and EDX is always the x2APIC ID, even for undefined
1491 * subleaves. Index 1 will exist iff the leaf is
1492 * implemented, so we pass through CL iff leaf 1
1493 * exists. EDX can be copied from any existing index.
1494 */
1495 if (function == 0xb || function == 0x1f) {
1496 entry = kvm_find_cpuid_entry_index(vcpu, function, 1);
1497 if (entry) {
1498 *ecx = index & 0xff;
1499 *edx = entry->edx;
1500 }
1501 }
1502 }
1503 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1504 used_max_basic);
1505 return exact;
1506}
1507EXPORT_SYMBOL_GPL(kvm_cpuid);
1508
1509int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1510{
1511 u32 eax, ebx, ecx, edx;
1512
1513 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1514 return 1;
1515
1516 eax = kvm_rax_read(vcpu);
1517 ecx = kvm_rcx_read(vcpu);
1518 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1519 kvm_rax_write(vcpu, eax);
1520 kvm_rbx_write(vcpu, ebx);
1521 kvm_rcx_write(vcpu, ecx);
1522 kvm_rdx_write(vcpu, edx);
1523 return kvm_skip_emulated_instruction(vcpu);
1524}
1525EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
5 *
6 * derived from arch/x86/kvm/x86.c
7 *
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
10 */
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/kvm_host.h>
14#include "linux/lockdep.h"
15#include <linux/export.h>
16#include <linux/vmalloc.h>
17#include <linux/uaccess.h>
18#include <linux/sched/stat.h>
19
20#include <asm/processor.h>
21#include <asm/user.h>
22#include <asm/fpu/xstate.h>
23#include <asm/sgx.h>
24#include <asm/cpuid.h>
25#include "cpuid.h"
26#include "lapic.h"
27#include "mmu.h"
28#include "trace.h"
29#include "pmu.h"
30#include "xen.h"
31
32/*
33 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
34 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
35 */
36u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
37EXPORT_SYMBOL_GPL(kvm_cpu_caps);
38
39struct cpuid_xstate_sizes {
40 u32 eax;
41 u32 ebx;
42 u32 ecx;
43};
44
45static struct cpuid_xstate_sizes xstate_sizes[XFEATURE_MAX] __ro_after_init;
46
47void __init kvm_init_xstate_sizes(void)
48{
49 u32 ign;
50 int i;
51
52 for (i = XFEATURE_YMM; i < ARRAY_SIZE(xstate_sizes); i++) {
53 struct cpuid_xstate_sizes *xs = &xstate_sizes[i];
54
55 cpuid_count(0xD, i, &xs->eax, &xs->ebx, &xs->ecx, &ign);
56 }
57}
58
59u32 xstate_required_size(u64 xstate_bv, bool compacted)
60{
61 int feature_bit = 0;
62 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
63
64 xstate_bv &= XFEATURE_MASK_EXTEND;
65 while (xstate_bv) {
66 if (xstate_bv & 0x1) {
67 struct cpuid_xstate_sizes *xs = &xstate_sizes[feature_bit];
68 u32 offset;
69
70 /* ECX[1]: 64B alignment in compacted form */
71 if (compacted)
72 offset = (xs->ecx & 0x2) ? ALIGN(ret, 64) : ret;
73 else
74 offset = xs->ebx;
75 ret = max(ret, offset + xs->eax);
76 }
77
78 xstate_bv >>= 1;
79 feature_bit++;
80 }
81
82 return ret;
83}
84
85#define F feature_bit
86
87/* Scattered Flag - For features that are scattered by cpufeatures.h. */
88#define SF(name) \
89({ \
90 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \
91 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \
92})
93
94/*
95 * Magic value used by KVM when querying userspace-provided CPUID entries and
96 * doesn't care about the CPIUD index because the index of the function in
97 * question is not significant. Note, this magic value must have at least one
98 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find()
99 * to avoid false positives when processing guest CPUID input.
100 */
101#define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull
102
103static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
104 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index)
105{
106 struct kvm_cpuid_entry2 *e;
107 int i;
108
109 /*
110 * KVM has a semi-arbitrary rule that querying the guest's CPUID model
111 * with IRQs disabled is disallowed. The CPUID model can legitimately
112 * have over one hundred entries, i.e. the lookup is slow, and IRQs are
113 * typically disabled in KVM only when KVM is in a performance critical
114 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break
115 * if this rule is violated, this assertion is purely to flag potential
116 * performance issues. If this fires, consider moving the lookup out
117 * of the hotpath, e.g. by caching information during CPUID updates.
118 */
119 lockdep_assert_irqs_enabled();
120
121 for (i = 0; i < nent; i++) {
122 e = &entries[i];
123
124 if (e->function != function)
125 continue;
126
127 /*
128 * If the index isn't significant, use the first entry with a
129 * matching function. It's userspace's responsibility to not
130 * provide "duplicate" entries in all cases.
131 */
132 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)
133 return e;
134
135
136 /*
137 * Similarly, use the first matching entry if KVM is doing a
138 * lookup (as opposed to emulating CPUID) for a function that's
139 * architecturally defined as not having a significant index.
140 */
141 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) {
142 /*
143 * Direct lookups from KVM should not diverge from what
144 * KVM defines internally (the architectural behavior).
145 */
146 WARN_ON_ONCE(cpuid_function_is_indexed(function));
147 return e;
148 }
149 }
150
151 return NULL;
152}
153
154static int kvm_check_cpuid(struct kvm_vcpu *vcpu,
155 struct kvm_cpuid_entry2 *entries,
156 int nent)
157{
158 struct kvm_cpuid_entry2 *best;
159 u64 xfeatures;
160
161 /*
162 * The existing code assumes virtual address is 48-bit or 57-bit in the
163 * canonical address checks; exit if it is ever changed.
164 */
165 best = cpuid_entry2_find(entries, nent, 0x80000008,
166 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
167 if (best) {
168 int vaddr_bits = (best->eax & 0xff00) >> 8;
169
170 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
171 return -EINVAL;
172 }
173
174 /*
175 * Exposing dynamic xfeatures to the guest requires additional
176 * enabling in the FPU, e.g. to expand the guest XSAVE state size.
177 */
178 best = cpuid_entry2_find(entries, nent, 0xd, 0);
179 if (!best)
180 return 0;
181
182 xfeatures = best->eax | ((u64)best->edx << 32);
183 xfeatures &= XFEATURE_MASK_USER_DYNAMIC;
184 if (!xfeatures)
185 return 0;
186
187 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures);
188}
189
190/* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */
191static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
192 int nent)
193{
194 struct kvm_cpuid_entry2 *orig;
195 int i;
196
197 if (nent != vcpu->arch.cpuid_nent)
198 return -EINVAL;
199
200 for (i = 0; i < nent; i++) {
201 orig = &vcpu->arch.cpuid_entries[i];
202 if (e2[i].function != orig->function ||
203 e2[i].index != orig->index ||
204 e2[i].flags != orig->flags ||
205 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx ||
206 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx)
207 return -EINVAL;
208 }
209
210 return 0;
211}
212
213static struct kvm_hypervisor_cpuid __kvm_get_hypervisor_cpuid(struct kvm_cpuid_entry2 *entries,
214 int nent, const char *sig)
215{
216 struct kvm_hypervisor_cpuid cpuid = {};
217 struct kvm_cpuid_entry2 *entry;
218 u32 base;
219
220 for_each_possible_hypervisor_cpuid_base(base) {
221 entry = cpuid_entry2_find(entries, nent, base, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
222
223 if (entry) {
224 u32 signature[3];
225
226 signature[0] = entry->ebx;
227 signature[1] = entry->ecx;
228 signature[2] = entry->edx;
229
230 if (!memcmp(signature, sig, sizeof(signature))) {
231 cpuid.base = base;
232 cpuid.limit = entry->eax;
233 break;
234 }
235 }
236 }
237
238 return cpuid;
239}
240
241static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu,
242 const char *sig)
243{
244 return __kvm_get_hypervisor_cpuid(vcpu->arch.cpuid_entries,
245 vcpu->arch.cpuid_nent, sig);
246}
247
248static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_cpuid_entry2 *entries,
249 int nent, u32 kvm_cpuid_base)
250{
251 return cpuid_entry2_find(entries, nent, kvm_cpuid_base | KVM_CPUID_FEATURES,
252 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
253}
254
255static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu)
256{
257 u32 base = vcpu->arch.kvm_cpuid.base;
258
259 if (!base)
260 return NULL;
261
262 return __kvm_find_kvm_cpuid_features(vcpu->arch.cpuid_entries,
263 vcpu->arch.cpuid_nent, base);
264}
265
266void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
267{
268 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu);
269
270 /*
271 * save the feature bitmap to avoid cpuid lookup for every PV
272 * operation
273 */
274 if (best)
275 vcpu->arch.pv_cpuid.features = best->eax;
276}
277
278/*
279 * Calculate guest's supported XCR0 taking into account guest CPUID data and
280 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0).
281 */
282static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
283{
284 struct kvm_cpuid_entry2 *best;
285
286 best = cpuid_entry2_find(entries, nent, 0xd, 0);
287 if (!best)
288 return 0;
289
290 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0;
291}
292
293static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
294 int nent)
295{
296 struct kvm_cpuid_entry2 *best;
297 struct kvm_hypervisor_cpuid kvm_cpuid;
298
299 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
300 if (best) {
301 /* Update OSXSAVE bit */
302 if (boot_cpu_has(X86_FEATURE_XSAVE))
303 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
304 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE));
305
306 cpuid_entry_change(best, X86_FEATURE_APIC,
307 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
308 }
309
310 best = cpuid_entry2_find(entries, nent, 7, 0);
311 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
312 cpuid_entry_change(best, X86_FEATURE_OSPKE,
313 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE));
314
315 best = cpuid_entry2_find(entries, nent, 0xD, 0);
316 if (best)
317 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
318
319 best = cpuid_entry2_find(entries, nent, 0xD, 1);
320 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
321 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
322 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
323
324 kvm_cpuid = __kvm_get_hypervisor_cpuid(entries, nent, KVM_SIGNATURE);
325 if (kvm_cpuid.base) {
326 best = __kvm_find_kvm_cpuid_features(entries, nent, kvm_cpuid.base);
327 if (kvm_hlt_in_guest(vcpu->kvm) && best)
328 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
329 }
330
331 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
332 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
333 if (best)
334 cpuid_entry_change(best, X86_FEATURE_MWAIT,
335 vcpu->arch.ia32_misc_enable_msr &
336 MSR_IA32_MISC_ENABLE_MWAIT);
337 }
338}
339
340void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
341{
342 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
343}
344EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime);
345
346static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent)
347{
348#ifdef CONFIG_KVM_HYPERV
349 struct kvm_cpuid_entry2 *entry;
350
351 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE,
352 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
353 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX;
354#else
355 return false;
356#endif
357}
358
359static bool guest_cpuid_is_amd_or_hygon(struct kvm_vcpu *vcpu)
360{
361 struct kvm_cpuid_entry2 *entry;
362
363 entry = kvm_find_cpuid_entry(vcpu, 0);
364 if (!entry)
365 return false;
366
367 return is_guest_vendor_amd(entry->ebx, entry->ecx, entry->edx) ||
368 is_guest_vendor_hygon(entry->ebx, entry->ecx, entry->edx);
369}
370
371static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
372{
373 struct kvm_lapic *apic = vcpu->arch.apic;
374 struct kvm_cpuid_entry2 *best;
375 bool allow_gbpages;
376
377 BUILD_BUG_ON(KVM_NR_GOVERNED_FEATURES > KVM_MAX_NR_GOVERNED_FEATURES);
378 bitmap_zero(vcpu->arch.governed_features.enabled,
379 KVM_MAX_NR_GOVERNED_FEATURES);
380
381 /*
382 * If TDP is enabled, let the guest use GBPAGES if they're supported in
383 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
384 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
385 * walk for performance and complexity reasons. Not to mention KVM
386 * _can't_ solve the problem because GVA->GPA walks aren't visible to
387 * KVM once a TDP translation is installed. Mimic hardware behavior so
388 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
389 * If TDP is disabled, honor *only* guest CPUID as KVM has full control
390 * and can install smaller shadow pages if the host lacks 1GiB support.
391 */
392 allow_gbpages = tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) :
393 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES);
394 if (allow_gbpages)
395 kvm_governed_feature_set(vcpu, X86_FEATURE_GBPAGES);
396
397 best = kvm_find_cpuid_entry(vcpu, 1);
398 if (best && apic) {
399 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
400 apic->lapic_timer.timer_mode_mask = 3 << 17;
401 else
402 apic->lapic_timer.timer_mode_mask = 1 << 17;
403
404 kvm_apic_set_version(vcpu);
405 }
406
407 vcpu->arch.guest_supported_xcr0 =
408 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
409
410 kvm_update_pv_runtime(vcpu);
411
412 vcpu->arch.is_amd_compatible = guest_cpuid_is_amd_or_hygon(vcpu);
413 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
414 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
415
416 kvm_pmu_refresh(vcpu);
417 vcpu->arch.cr4_guest_rsvd_bits =
418 __cr4_reserved_bits(guest_cpuid_has, vcpu);
419
420 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries,
421 vcpu->arch.cpuid_nent));
422
423 /* Invoke the vendor callback only after the above state is updated. */
424 kvm_x86_call(vcpu_after_set_cpuid)(vcpu);
425
426 /*
427 * Except for the MMU, which needs to do its thing any vendor specific
428 * adjustments to the reserved GPA bits.
429 */
430 kvm_mmu_after_set_cpuid(vcpu);
431}
432
433int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
434{
435 struct kvm_cpuid_entry2 *best;
436
437 best = kvm_find_cpuid_entry(vcpu, 0x80000000);
438 if (!best || best->eax < 0x80000008)
439 goto not_found;
440 best = kvm_find_cpuid_entry(vcpu, 0x80000008);
441 if (best)
442 return best->eax & 0xff;
443not_found:
444 return 36;
445}
446
447/*
448 * This "raw" version returns the reserved GPA bits without any adjustments for
449 * encryption technologies that usurp bits. The raw mask should be used if and
450 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs.
451 */
452u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu)
453{
454 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
455}
456
457static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
458 int nent)
459{
460 int r;
461
462 __kvm_update_cpuid_runtime(vcpu, e2, nent);
463
464 /*
465 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
466 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
467 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
468 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with
469 * the core vCPU model on the fly. It would've been better to forbid any
470 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately
471 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do
472 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check
473 * whether the supplied CPUID data is equal to what's already set.
474 */
475 if (kvm_vcpu_has_run(vcpu)) {
476 r = kvm_cpuid_check_equal(vcpu, e2, nent);
477 if (r)
478 return r;
479
480 kvfree(e2);
481 return 0;
482 }
483
484#ifdef CONFIG_KVM_HYPERV
485 if (kvm_cpuid_has_hyperv(e2, nent)) {
486 r = kvm_hv_vcpu_init(vcpu);
487 if (r)
488 return r;
489 }
490#endif
491
492 r = kvm_check_cpuid(vcpu, e2, nent);
493 if (r)
494 return r;
495
496 kvfree(vcpu->arch.cpuid_entries);
497 vcpu->arch.cpuid_entries = e2;
498 vcpu->arch.cpuid_nent = nent;
499
500 vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE);
501#ifdef CONFIG_KVM_XEN
502 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE);
503#endif
504 kvm_vcpu_after_set_cpuid(vcpu);
505
506 return 0;
507}
508
509/* when an old userspace process fills a new kernel module */
510int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
511 struct kvm_cpuid *cpuid,
512 struct kvm_cpuid_entry __user *entries)
513{
514 int r, i;
515 struct kvm_cpuid_entry *e = NULL;
516 struct kvm_cpuid_entry2 *e2 = NULL;
517
518 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
519 return -E2BIG;
520
521 if (cpuid->nent) {
522 e = vmemdup_array_user(entries, cpuid->nent, sizeof(*e));
523 if (IS_ERR(e))
524 return PTR_ERR(e);
525
526 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
527 if (!e2) {
528 r = -ENOMEM;
529 goto out_free_cpuid;
530 }
531 }
532 for (i = 0; i < cpuid->nent; i++) {
533 e2[i].function = e[i].function;
534 e2[i].eax = e[i].eax;
535 e2[i].ebx = e[i].ebx;
536 e2[i].ecx = e[i].ecx;
537 e2[i].edx = e[i].edx;
538 e2[i].index = 0;
539 e2[i].flags = 0;
540 e2[i].padding[0] = 0;
541 e2[i].padding[1] = 0;
542 e2[i].padding[2] = 0;
543 }
544
545 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
546 if (r)
547 kvfree(e2);
548
549out_free_cpuid:
550 kvfree(e);
551
552 return r;
553}
554
555int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
556 struct kvm_cpuid2 *cpuid,
557 struct kvm_cpuid_entry2 __user *entries)
558{
559 struct kvm_cpuid_entry2 *e2 = NULL;
560 int r;
561
562 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
563 return -E2BIG;
564
565 if (cpuid->nent) {
566 e2 = vmemdup_array_user(entries, cpuid->nent, sizeof(*e2));
567 if (IS_ERR(e2))
568 return PTR_ERR(e2);
569 }
570
571 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
572 if (r)
573 kvfree(e2);
574
575 return r;
576}
577
578int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
579 struct kvm_cpuid2 *cpuid,
580 struct kvm_cpuid_entry2 __user *entries)
581{
582 if (cpuid->nent < vcpu->arch.cpuid_nent)
583 return -E2BIG;
584
585 if (copy_to_user(entries, vcpu->arch.cpuid_entries,
586 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
587 return -EFAULT;
588
589 cpuid->nent = vcpu->arch.cpuid_nent;
590 return 0;
591}
592
593/* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */
594static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf)
595{
596 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
597 struct kvm_cpuid_entry2 entry;
598
599 reverse_cpuid_check(leaf);
600
601 cpuid_count(cpuid.function, cpuid.index,
602 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
603
604 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
605}
606
607static __always_inline
608void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask)
609{
610 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */
611 BUILD_BUG_ON(leaf < NCAPINTS);
612
613 kvm_cpu_caps[leaf] = mask;
614
615 __kvm_cpu_cap_mask(leaf);
616}
617
618static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
619{
620 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */
621 BUILD_BUG_ON(leaf >= NCAPINTS);
622
623 kvm_cpu_caps[leaf] &= mask;
624
625 __kvm_cpu_cap_mask(leaf);
626}
627
628void kvm_set_cpu_caps(void)
629{
630#ifdef CONFIG_X86_64
631 unsigned int f_gbpages = F(GBPAGES);
632 unsigned int f_lm = F(LM);
633 unsigned int f_xfd = F(XFD);
634#else
635 unsigned int f_gbpages = 0;
636 unsigned int f_lm = 0;
637 unsigned int f_xfd = 0;
638#endif
639 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
640
641 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) >
642 sizeof(boot_cpu_data.x86_capability));
643
644 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
645 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
646
647 kvm_cpu_cap_mask(CPUID_1_ECX,
648 /*
649 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
650 * advertised to guests via CPUID!
651 */
652 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
653 0 /* DS-CPL, VMX, SMX, EST */ |
654 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
655 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
656 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
657 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
658 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
659 F(F16C) | F(RDRAND)
660 );
661 /* KVM emulates x2apic in software irrespective of host support. */
662 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
663
664 kvm_cpu_cap_mask(CPUID_1_EDX,
665 F(FPU) | F(VME) | F(DE) | F(PSE) |
666 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
667 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
668 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
669 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
670 0 /* Reserved, DS, ACPI */ | F(MMX) |
671 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
672 0 /* HTT, TM, Reserved, PBE */
673 );
674
675 kvm_cpu_cap_mask(CPUID_7_0_EBX,
676 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
677 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
678 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
679 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
680 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
681 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
682 F(AVX512VL));
683
684 kvm_cpu_cap_mask(CPUID_7_ECX,
685 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
686 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
687 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
688 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
689 F(SGX_LC) | F(BUS_LOCK_DETECT)
690 );
691 /* Set LA57 based on hardware capability. */
692 if (cpuid_ecx(7) & F(LA57))
693 kvm_cpu_cap_set(X86_FEATURE_LA57);
694
695 /*
696 * PKU not yet implemented for shadow paging and requires OSPKE
697 * to be set on the host. Clear it if that is not the case
698 */
699 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
700 kvm_cpu_cap_clear(X86_FEATURE_PKU);
701
702 kvm_cpu_cap_mask(CPUID_7_EDX,
703 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
704 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
705 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
706 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
707 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D)
708 );
709
710 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
711 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
712 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
713
714 if (boot_cpu_has(X86_FEATURE_AMD_IBPB_RET) &&
715 boot_cpu_has(X86_FEATURE_AMD_IBPB) &&
716 boot_cpu_has(X86_FEATURE_AMD_IBRS))
717 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
718 if (boot_cpu_has(X86_FEATURE_STIBP))
719 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
720 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
721 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
722
723 kvm_cpu_cap_mask(CPUID_7_1_EAX,
724 F(SHA512) | F(SM3) | F(SM4) | F(AVX_VNNI) | F(AVX512_BF16) |
725 F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) | F(AMX_FP16) |
726 F(AVX_IFMA) | F(LAM)
727 );
728
729 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,
730 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(AMX_COMPLEX) |
731 F(AVX_VNNI_INT16) | F(PREFETCHITI) | F(AVX10)
732 );
733
734 kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX,
735 F(INTEL_PSFD) | F(IPRED_CTRL) | F(RRSBA_CTRL) | F(DDPD_U) |
736 F(BHI_CTRL) | F(MCDT_NO)
737 );
738
739 kvm_cpu_cap_mask(CPUID_D_1_EAX,
740 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
741 );
742
743 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX,
744 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA)
745 );
746
747 kvm_cpu_cap_init_kvm_defined(CPUID_24_0_EBX,
748 F(AVX10_128) | F(AVX10_256) | F(AVX10_512)
749 );
750
751 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
752 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
753 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
754 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
755 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
756 F(TOPOEXT) | 0 /* PERFCTR_CORE */
757 );
758
759 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
760 F(FPU) | F(VME) | F(DE) | F(PSE) |
761 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
762 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
763 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
764 F(PAT) | F(PSE36) | 0 /* Reserved */ |
765 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
766 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
767 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
768 );
769
770 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
771 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
772
773 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX,
774 SF(CONSTANT_TSC)
775 );
776
777 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
778 F(CLZERO) | F(XSAVEERPTR) |
779 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
780 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
781 F(AMD_PSFD) | F(AMD_IBPB_RET)
782 );
783
784 /*
785 * AMD has separate bits for each SPEC_CTRL bit.
786 * arch/x86/kernel/cpu/bugs.c is kind enough to
787 * record that in cpufeatures so use them.
788 */
789 if (boot_cpu_has(X86_FEATURE_IBPB)) {
790 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
791 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
792 !boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB))
793 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET);
794 }
795 if (boot_cpu_has(X86_FEATURE_IBRS))
796 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
797 if (boot_cpu_has(X86_FEATURE_STIBP))
798 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
799 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
800 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
801 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
802 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
803 /*
804 * The preference is to use SPEC CTRL MSR instead of the
805 * VIRT_SPEC MSR.
806 */
807 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
808 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
809 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
810
811 /*
812 * Hide all SVM features by default, SVM will set the cap bits for
813 * features it emulates and/or exposes for L1.
814 */
815 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
816
817 kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
818 0 /* SME */ | 0 /* SEV */ | 0 /* VM_PAGE_FLUSH */ | 0 /* SEV_ES */ |
819 F(SME_COHERENT));
820
821 kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
822 F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
823 F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
824 F(WRMSR_XX_BASE_NS)
825 );
826
827 kvm_cpu_cap_check_and_set(X86_FEATURE_SBPB);
828 kvm_cpu_cap_check_and_set(X86_FEATURE_IBPB_BRTYPE);
829 kvm_cpu_cap_check_and_set(X86_FEATURE_SRSO_NO);
830
831 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX,
832 F(PERFMON_V2)
833 );
834
835 /*
836 * Synthesize "LFENCE is serializing" into the AMD-defined entry in
837 * KVM's supported CPUID if the feature is reported as supported by the
838 * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long
839 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most
840 * CPUs that support SSE2. On CPUs that don't support AMD's leaf,
841 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing
842 * the mask with the raw host CPUID, and reporting support in AMD's
843 * leaf can make it easier for userspace to detect the feature.
844 */
845 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
846 kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC);
847 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
848 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE);
849 kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR);
850
851 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
852 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
853 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
854 F(PMM) | F(PMM_EN)
855 );
856
857 /*
858 * Hide RDTSCP and RDPID if either feature is reported as supported but
859 * probing MSR_TSC_AUX failed. This is purely a sanity check and
860 * should never happen, but the guest will likely crash if RDTSCP or
861 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
862 * the past. For example, the sanity check may fire if this instance of
863 * KVM is running as L1 on top of an older, broken KVM.
864 */
865 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) ||
866 kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
867 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
868 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
869 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
870 }
871}
872EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
873
874struct kvm_cpuid_array {
875 struct kvm_cpuid_entry2 *entries;
876 int maxnent;
877 int nent;
878};
879
880static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array)
881{
882 if (array->nent >= array->maxnent)
883 return NULL;
884
885 return &array->entries[array->nent++];
886}
887
888static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
889 u32 function, u32 index)
890{
891 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array);
892
893 if (!entry)
894 return NULL;
895
896 memset(entry, 0, sizeof(*entry));
897 entry->function = function;
898 entry->index = index;
899 switch (function & 0xC0000000) {
900 case 0x40000000:
901 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */
902 return entry;
903
904 case 0x80000000:
905 /*
906 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which
907 * would result in out-of-bounds calls to do_host_cpuid.
908 */
909 {
910 static int max_cpuid_80000000;
911 if (!READ_ONCE(max_cpuid_80000000))
912 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000));
913 if (function > READ_ONCE(max_cpuid_80000000))
914 return entry;
915 }
916 break;
917
918 default:
919 break;
920 }
921
922 cpuid_count(entry->function, entry->index,
923 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
924
925 if (cpuid_function_is_indexed(function))
926 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
927
928 return entry;
929}
930
931static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
932{
933 struct kvm_cpuid_entry2 *entry;
934
935 if (array->nent >= array->maxnent)
936 return -E2BIG;
937
938 entry = &array->entries[array->nent];
939 entry->function = func;
940 entry->index = 0;
941 entry->flags = 0;
942
943 switch (func) {
944 case 0:
945 entry->eax = 7;
946 ++array->nent;
947 break;
948 case 1:
949 entry->ecx = F(MOVBE);
950 ++array->nent;
951 break;
952 case 7:
953 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
954 entry->eax = 0;
955 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
956 entry->ecx = F(RDPID);
957 ++array->nent;
958 break;
959 default:
960 break;
961 }
962
963 return 0;
964}
965
966static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
967{
968 struct kvm_cpuid_entry2 *entry;
969 int r, i, max_idx;
970
971 /* all calls to cpuid_count() should be made on the same cpu */
972 get_cpu();
973
974 r = -E2BIG;
975
976 entry = do_host_cpuid(array, function, 0);
977 if (!entry)
978 goto out;
979
980 switch (function) {
981 case 0:
982 /* Limited to the highest leaf implemented in KVM. */
983 entry->eax = min(entry->eax, 0x24U);
984 break;
985 case 1:
986 cpuid_entry_override(entry, CPUID_1_EDX);
987 cpuid_entry_override(entry, CPUID_1_ECX);
988 break;
989 case 2:
990 /*
991 * On ancient CPUs, function 2 entries are STATEFUL. That is,
992 * CPUID(function=2, index=0) may return different results each
993 * time, with the least-significant byte in EAX enumerating the
994 * number of times software should do CPUID(2, 0).
995 *
996 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
997 * idiotic. Intel's SDM states that EAX & 0xff "will always
998 * return 01H. Software should ignore this value and not
999 * interpret it as an informational descriptor", while AMD's
1000 * APM states that CPUID(2) is reserved.
1001 *
1002 * WARN if a frankenstein CPU that supports virtualization and
1003 * a stateful CPUID.0x2 is encountered.
1004 */
1005 WARN_ON_ONCE((entry->eax & 0xff) > 1);
1006 break;
1007 /* functions 4 and 0x8000001d have additional index. */
1008 case 4:
1009 case 0x8000001d:
1010 /*
1011 * Read entries until the cache type in the previous entry is
1012 * zero, i.e. indicates an invalid entry.
1013 */
1014 for (i = 1; entry->eax & 0x1f; ++i) {
1015 entry = do_host_cpuid(array, function, i);
1016 if (!entry)
1017 goto out;
1018 }
1019 break;
1020 case 6: /* Thermal management */
1021 entry->eax = 0x4; /* allow ARAT */
1022 entry->ebx = 0;
1023 entry->ecx = 0;
1024 entry->edx = 0;
1025 break;
1026 /* function 7 has additional index. */
1027 case 7:
1028 max_idx = entry->eax = min(entry->eax, 2u);
1029 cpuid_entry_override(entry, CPUID_7_0_EBX);
1030 cpuid_entry_override(entry, CPUID_7_ECX);
1031 cpuid_entry_override(entry, CPUID_7_EDX);
1032
1033 /* KVM only supports up to 0x7.2, capped above via min(). */
1034 if (max_idx >= 1) {
1035 entry = do_host_cpuid(array, function, 1);
1036 if (!entry)
1037 goto out;
1038
1039 cpuid_entry_override(entry, CPUID_7_1_EAX);
1040 cpuid_entry_override(entry, CPUID_7_1_EDX);
1041 entry->ebx = 0;
1042 entry->ecx = 0;
1043 }
1044 if (max_idx >= 2) {
1045 entry = do_host_cpuid(array, function, 2);
1046 if (!entry)
1047 goto out;
1048
1049 cpuid_entry_override(entry, CPUID_7_2_EDX);
1050 entry->ecx = 0;
1051 entry->ebx = 0;
1052 entry->eax = 0;
1053 }
1054 break;
1055 case 0xa: { /* Architectural Performance Monitoring */
1056 union cpuid10_eax eax;
1057 union cpuid10_edx edx;
1058
1059 if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
1060 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1061 break;
1062 }
1063
1064 eax.split.version_id = kvm_pmu_cap.version;
1065 eax.split.num_counters = kvm_pmu_cap.num_counters_gp;
1066 eax.split.bit_width = kvm_pmu_cap.bit_width_gp;
1067 eax.split.mask_length = kvm_pmu_cap.events_mask_len;
1068 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed;
1069 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
1070
1071 if (kvm_pmu_cap.version)
1072 edx.split.anythread_deprecated = 1;
1073 edx.split.reserved1 = 0;
1074 edx.split.reserved2 = 0;
1075
1076 entry->eax = eax.full;
1077 entry->ebx = kvm_pmu_cap.events_mask;
1078 entry->ecx = 0;
1079 entry->edx = edx.full;
1080 break;
1081 }
1082 case 0x1f:
1083 case 0xb:
1084 /*
1085 * No topology; a valid topology is indicated by the presence
1086 * of subleaf 1.
1087 */
1088 entry->eax = entry->ebx = entry->ecx = 0;
1089 break;
1090 case 0xd: {
1091 u64 permitted_xcr0 = kvm_get_filtered_xcr0();
1092 u64 permitted_xss = kvm_caps.supported_xss;
1093
1094 entry->eax &= permitted_xcr0;
1095 entry->ebx = xstate_required_size(permitted_xcr0, false);
1096 entry->ecx = entry->ebx;
1097 entry->edx &= permitted_xcr0 >> 32;
1098 if (!permitted_xcr0)
1099 break;
1100
1101 entry = do_host_cpuid(array, function, 1);
1102 if (!entry)
1103 goto out;
1104
1105 cpuid_entry_override(entry, CPUID_D_1_EAX);
1106 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
1107 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss,
1108 true);
1109 else {
1110 WARN_ON_ONCE(permitted_xss != 0);
1111 entry->ebx = 0;
1112 }
1113 entry->ecx &= permitted_xss;
1114 entry->edx &= permitted_xss >> 32;
1115
1116 for (i = 2; i < 64; ++i) {
1117 bool s_state;
1118 if (permitted_xcr0 & BIT_ULL(i))
1119 s_state = false;
1120 else if (permitted_xss & BIT_ULL(i))
1121 s_state = true;
1122 else
1123 continue;
1124
1125 entry = do_host_cpuid(array, function, i);
1126 if (!entry)
1127 goto out;
1128
1129 /*
1130 * The supported check above should have filtered out
1131 * invalid sub-leafs. Only valid sub-leafs should
1132 * reach this point, and they should have a non-zero
1133 * save state size. Furthermore, check whether the
1134 * processor agrees with permitted_xcr0/permitted_xss
1135 * on whether this is an XCR0- or IA32_XSS-managed area.
1136 */
1137 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
1138 --array->nent;
1139 continue;
1140 }
1141
1142 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
1143 entry->ecx &= ~BIT_ULL(2);
1144 entry->edx = 0;
1145 }
1146 break;
1147 }
1148 case 0x12:
1149 /* Intel SGX */
1150 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) {
1151 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1152 break;
1153 }
1154
1155 /*
1156 * Index 0: Sub-features, MISCSELECT (a.k.a extended features)
1157 * and max enclave sizes. The SGX sub-features and MISCSELECT
1158 * are restricted by kernel and KVM capabilities (like most
1159 * feature flags), while enclave size is unrestricted.
1160 */
1161 cpuid_entry_override(entry, CPUID_12_EAX);
1162 entry->ebx &= SGX_MISC_EXINFO;
1163
1164 entry = do_host_cpuid(array, function, 1);
1165 if (!entry)
1166 goto out;
1167
1168 /*
1169 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la
1170 * feature flags. Advertise all supported flags, including
1171 * privileged attributes that require explicit opt-in from
1172 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is
1173 * expected to derive it from supported XCR0.
1174 */
1175 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK;
1176 entry->ebx &= 0;
1177 break;
1178 /* Intel PT */
1179 case 0x14:
1180 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
1181 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1182 break;
1183 }
1184
1185 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1186 if (!do_host_cpuid(array, function, i))
1187 goto out;
1188 }
1189 break;
1190 /* Intel AMX TILE */
1191 case 0x1d:
1192 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1193 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1194 break;
1195 }
1196
1197 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1198 if (!do_host_cpuid(array, function, i))
1199 goto out;
1200 }
1201 break;
1202 case 0x1e: /* TMUL information */
1203 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1204 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1205 break;
1206 }
1207 break;
1208 case 0x24: {
1209 u8 avx10_version;
1210
1211 if (!kvm_cpu_cap_has(X86_FEATURE_AVX10)) {
1212 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1213 break;
1214 }
1215
1216 /*
1217 * The AVX10 version is encoded in EBX[7:0]. Note, the version
1218 * is guaranteed to be >=1 if AVX10 is supported. Note #2, the
1219 * version needs to be captured before overriding EBX features!
1220 */
1221 avx10_version = min_t(u8, entry->ebx & 0xff, 1);
1222 cpuid_entry_override(entry, CPUID_24_0_EBX);
1223 entry->ebx |= avx10_version;
1224
1225 entry->eax = 0;
1226 entry->ecx = 0;
1227 entry->edx = 0;
1228 break;
1229 }
1230 case KVM_CPUID_SIGNATURE: {
1231 const u32 *sigptr = (const u32 *)KVM_SIGNATURE;
1232 entry->eax = KVM_CPUID_FEATURES;
1233 entry->ebx = sigptr[0];
1234 entry->ecx = sigptr[1];
1235 entry->edx = sigptr[2];
1236 break;
1237 }
1238 case KVM_CPUID_FEATURES:
1239 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1240 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1241 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1242 (1 << KVM_FEATURE_ASYNC_PF) |
1243 (1 << KVM_FEATURE_PV_EOI) |
1244 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
1245 (1 << KVM_FEATURE_PV_UNHALT) |
1246 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
1247 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
1248 (1 << KVM_FEATURE_PV_SEND_IPI) |
1249 (1 << KVM_FEATURE_POLL_CONTROL) |
1250 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
1251 (1 << KVM_FEATURE_ASYNC_PF_INT);
1252
1253 if (sched_info_on())
1254 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
1255
1256 entry->ebx = 0;
1257 entry->ecx = 0;
1258 entry->edx = 0;
1259 break;
1260 case 0x80000000:
1261 entry->eax = min(entry->eax, 0x80000022);
1262 /*
1263 * Serializing LFENCE is reported in a multitude of ways, and
1264 * NullSegClearsBase is not reported in CPUID on Zen2; help
1265 * userspace by providing the CPUID leaf ourselves.
1266 *
1267 * However, only do it if the host has CPUID leaf 0x8000001d.
1268 * QEMU thinks that it can query the host blindly for that
1269 * CPUID leaf if KVM reports that it supports 0x8000001d or
1270 * above. The processor merrily returns values from the
1271 * highest Intel leaf which QEMU tries to use as the guest's
1272 * 0x8000001d. Even worse, this can result in an infinite
1273 * loop if said highest leaf has no subleaves indexed by ECX.
1274 */
1275 if (entry->eax >= 0x8000001d &&
1276 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
1277 || !static_cpu_has_bug(X86_BUG_NULL_SEG)))
1278 entry->eax = max(entry->eax, 0x80000021);
1279 break;
1280 case 0x80000001:
1281 entry->ebx &= ~GENMASK(27, 16);
1282 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
1283 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
1284 break;
1285 case 0x80000005:
1286 /* Pass host L1 cache and TLB info. */
1287 break;
1288 case 0x80000006:
1289 /* Drop reserved bits, pass host L2 cache and TLB info. */
1290 entry->edx &= ~GENMASK(17, 16);
1291 break;
1292 case 0x80000007: /* Advanced power management */
1293 cpuid_entry_override(entry, CPUID_8000_0007_EDX);
1294
1295 /* mask against host */
1296 entry->edx &= boot_cpu_data.x86_power;
1297 entry->eax = entry->ebx = entry->ecx = 0;
1298 break;
1299 case 0x80000008: {
1300 /*
1301 * GuestPhysAddrSize (EAX[23:16]) is intended for software
1302 * use.
1303 *
1304 * KVM's ABI is to report the effective MAXPHYADDR for the
1305 * guest in PhysAddrSize (phys_as), and the maximum
1306 * *addressable* GPA in GuestPhysAddrSize (g_phys_as).
1307 *
1308 * GuestPhysAddrSize is valid if and only if TDP is enabled,
1309 * in which case the max GPA that can be addressed by KVM may
1310 * be less than the max GPA that can be legally generated by
1311 * the guest, e.g. if MAXPHYADDR>48 but the CPU doesn't
1312 * support 5-level TDP.
1313 */
1314 unsigned int virt_as = max((entry->eax >> 8) & 0xff, 48U);
1315 unsigned int phys_as, g_phys_as;
1316
1317 /*
1318 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
1319 * the guest operates in the same PA space as the host, i.e.
1320 * reductions in MAXPHYADDR for memory encryption affect shadow
1321 * paging, too.
1322 *
1323 * If TDP is enabled, use the raw bare metal MAXPHYADDR as
1324 * reductions to the HPAs do not affect GPAs. The max
1325 * addressable GPA is the same as the max effective GPA, except
1326 * that it's capped at 48 bits if 5-level TDP isn't supported
1327 * (hardware processes bits 51:48 only when walking the fifth
1328 * level page table).
1329 */
1330 if (!tdp_enabled) {
1331 phys_as = boot_cpu_data.x86_phys_bits;
1332 g_phys_as = 0;
1333 } else {
1334 phys_as = entry->eax & 0xff;
1335 g_phys_as = phys_as;
1336 if (kvm_mmu_get_max_tdp_level() < 5)
1337 g_phys_as = min(g_phys_as, 48);
1338 }
1339
1340 entry->eax = phys_as | (virt_as << 8) | (g_phys_as << 16);
1341 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));
1342 entry->edx = 0;
1343 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
1344 break;
1345 }
1346 case 0x8000000A:
1347 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
1348 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1349 break;
1350 }
1351 entry->eax = 1; /* SVM revision 1 */
1352 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
1353 ASID emulation to nested SVM */
1354 entry->ecx = 0; /* Reserved */
1355 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
1356 break;
1357 case 0x80000019:
1358 entry->ecx = entry->edx = 0;
1359 break;
1360 case 0x8000001a:
1361 entry->eax &= GENMASK(2, 0);
1362 entry->ebx = entry->ecx = entry->edx = 0;
1363 break;
1364 case 0x8000001e:
1365 /* Do not return host topology information. */
1366 entry->eax = entry->ebx = entry->ecx = 0;
1367 entry->edx = 0; /* reserved */
1368 break;
1369 case 0x8000001F:
1370 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
1371 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1372 } else {
1373 cpuid_entry_override(entry, CPUID_8000_001F_EAX);
1374 /* Clear NumVMPL since KVM does not support VMPL. */
1375 entry->ebx &= ~GENMASK(31, 12);
1376 /*
1377 * Enumerate '0' for "PA bits reduction", the adjusted
1378 * MAXPHYADDR is enumerated directly (see 0x80000008).
1379 */
1380 entry->ebx &= ~GENMASK(11, 6);
1381 }
1382 break;
1383 case 0x80000020:
1384 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1385 break;
1386 case 0x80000021:
1387 entry->ebx = entry->ecx = entry->edx = 0;
1388 cpuid_entry_override(entry, CPUID_8000_0021_EAX);
1389 break;
1390 /* AMD Extended Performance Monitoring and Debug */
1391 case 0x80000022: {
1392 union cpuid_0x80000022_ebx ebx;
1393
1394 entry->ecx = entry->edx = 0;
1395 if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) {
1396 entry->eax = entry->ebx = 0;
1397 break;
1398 }
1399
1400 cpuid_entry_override(entry, CPUID_8000_0022_EAX);
1401
1402 if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
1403 ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp;
1404 else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE))
1405 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE;
1406 else
1407 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS;
1408
1409 entry->ebx = ebx.full;
1410 break;
1411 }
1412 /*Add support for Centaur's CPUID instruction*/
1413 case 0xC0000000:
1414 /*Just support up to 0xC0000004 now*/
1415 entry->eax = min(entry->eax, 0xC0000004);
1416 break;
1417 case 0xC0000001:
1418 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
1419 break;
1420 case 3: /* Processor serial number */
1421 case 5: /* MONITOR/MWAIT */
1422 case 0xC0000002:
1423 case 0xC0000003:
1424 case 0xC0000004:
1425 default:
1426 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1427 break;
1428 }
1429
1430 r = 0;
1431
1432out:
1433 put_cpu();
1434
1435 return r;
1436}
1437
1438static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1439 unsigned int type)
1440{
1441 if (type == KVM_GET_EMULATED_CPUID)
1442 return __do_cpuid_func_emulated(array, func);
1443
1444 return __do_cpuid_func(array, func);
1445}
1446
1447#define CENTAUR_CPUID_SIGNATURE 0xC0000000
1448
1449static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1450 unsigned int type)
1451{
1452 u32 limit;
1453 int r;
1454
1455 if (func == CENTAUR_CPUID_SIGNATURE &&
1456 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
1457 return 0;
1458
1459 r = do_cpuid_func(array, func, type);
1460 if (r)
1461 return r;
1462
1463 limit = array->entries[array->nent - 1].eax;
1464 for (func = func + 1; func <= limit; ++func) {
1465 r = do_cpuid_func(array, func, type);
1466 if (r)
1467 break;
1468 }
1469
1470 return r;
1471}
1472
1473static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
1474 __u32 num_entries, unsigned int ioctl_type)
1475{
1476 int i;
1477 __u32 pad[3];
1478
1479 if (ioctl_type != KVM_GET_EMULATED_CPUID)
1480 return false;
1481
1482 /*
1483 * We want to make sure that ->padding is being passed clean from
1484 * userspace in case we want to use it for something in the future.
1485 *
1486 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
1487 * have to give ourselves satisfied only with the emulated side. /me
1488 * sheds a tear.
1489 */
1490 for (i = 0; i < num_entries; i++) {
1491 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
1492 return true;
1493
1494 if (pad[0] || pad[1] || pad[2])
1495 return true;
1496 }
1497 return false;
1498}
1499
1500int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
1501 struct kvm_cpuid_entry2 __user *entries,
1502 unsigned int type)
1503{
1504 static const u32 funcs[] = {
1505 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
1506 };
1507
1508 struct kvm_cpuid_array array = {
1509 .nent = 0,
1510 };
1511 int r, i;
1512
1513 if (cpuid->nent < 1)
1514 return -E2BIG;
1515 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1516 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1517
1518 if (sanity_check_entries(entries, cpuid->nent, type))
1519 return -EINVAL;
1520
1521 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL);
1522 if (!array.entries)
1523 return -ENOMEM;
1524
1525 array.maxnent = cpuid->nent;
1526
1527 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
1528 r = get_cpuid_func(&array, funcs[i], type);
1529 if (r)
1530 goto out_free;
1531 }
1532 cpuid->nent = array.nent;
1533
1534 if (copy_to_user(entries, array.entries,
1535 array.nent * sizeof(struct kvm_cpuid_entry2)))
1536 r = -EFAULT;
1537
1538out_free:
1539 kvfree(array.entries);
1540 return r;
1541}
1542
1543struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu,
1544 u32 function, u32 index)
1545{
1546 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1547 function, index);
1548}
1549EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index);
1550
1551struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
1552 u32 function)
1553{
1554 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1555 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
1556}
1557EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
1558
1559/*
1560 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
1561 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
1562 * returns all zeroes for any undefined leaf, whether or not the leaf is in
1563 * range. Centaur/VIA follows Intel semantics.
1564 *
1565 * A leaf is considered out-of-range if its function is higher than the maximum
1566 * supported leaf of its associated class or if its associated class does not
1567 * exist.
1568 *
1569 * There are three primary classes to be considered, with their respective
1570 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
1571 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
1572 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
1573 *
1574 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
1575 * - Hypervisor: 0x40000000 - 0x4fffffff
1576 * - Extended: 0x80000000 - 0xbfffffff
1577 * - Centaur: 0xc0000000 - 0xcfffffff
1578 *
1579 * The Hypervisor class is further subdivided into sub-classes that each act as
1580 * their own independent class associated with a 0x100 byte range. E.g. if Qemu
1581 * is advertising support for both HyperV and KVM, the resulting Hypervisor
1582 * CPUID sub-classes are:
1583 *
1584 * - HyperV: 0x40000000 - 0x400000ff
1585 * - KVM: 0x40000100 - 0x400001ff
1586 */
1587static struct kvm_cpuid_entry2 *
1588get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
1589{
1590 struct kvm_cpuid_entry2 *basic, *class;
1591 u32 function = *fn_ptr;
1592
1593 basic = kvm_find_cpuid_entry(vcpu, 0);
1594 if (!basic)
1595 return NULL;
1596
1597 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
1598 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
1599 return NULL;
1600
1601 if (function >= 0x40000000 && function <= 0x4fffffff)
1602 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00);
1603 else if (function >= 0xc0000000)
1604 class = kvm_find_cpuid_entry(vcpu, 0xc0000000);
1605 else
1606 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000);
1607
1608 if (class && function <= class->eax)
1609 return NULL;
1610
1611 /*
1612 * Leaf specific adjustments are also applied when redirecting to the
1613 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1614 * entry for CPUID.0xb.index (see below), then the output value for EDX
1615 * needs to be pulled from CPUID.0xb.1.
1616 */
1617 *fn_ptr = basic->eax;
1618
1619 /*
1620 * The class does not exist or the requested function is out of range;
1621 * the effective CPUID entry is the max basic leaf. Note, the index of
1622 * the original requested leaf is observed!
1623 */
1624 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index);
1625}
1626
1627bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1628 u32 *ecx, u32 *edx, bool exact_only)
1629{
1630 u32 orig_function = *eax, function = *eax, index = *ecx;
1631 struct kvm_cpuid_entry2 *entry;
1632 bool exact, used_max_basic = false;
1633
1634 entry = kvm_find_cpuid_entry_index(vcpu, function, index);
1635 exact = !!entry;
1636
1637 if (!entry && !exact_only) {
1638 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1639 used_max_basic = !!entry;
1640 }
1641
1642 if (entry) {
1643 *eax = entry->eax;
1644 *ebx = entry->ebx;
1645 *ecx = entry->ecx;
1646 *edx = entry->edx;
1647 if (function == 7 && index == 0) {
1648 u64 data;
1649 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1650 (data & TSX_CTRL_CPUID_CLEAR))
1651 *ebx &= ~(F(RTM) | F(HLE));
1652 } else if (function == 0x80000007) {
1653 if (kvm_hv_invtsc_suppressed(vcpu))
1654 *edx &= ~SF(CONSTANT_TSC);
1655 }
1656 } else {
1657 *eax = *ebx = *ecx = *edx = 0;
1658 /*
1659 * When leaf 0BH or 1FH is defined, CL is pass-through
1660 * and EDX is always the x2APIC ID, even for undefined
1661 * subleaves. Index 1 will exist iff the leaf is
1662 * implemented, so we pass through CL iff leaf 1
1663 * exists. EDX can be copied from any existing index.
1664 */
1665 if (function == 0xb || function == 0x1f) {
1666 entry = kvm_find_cpuid_entry_index(vcpu, function, 1);
1667 if (entry) {
1668 *ecx = index & 0xff;
1669 *edx = entry->edx;
1670 }
1671 }
1672 }
1673 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1674 used_max_basic);
1675 return exact;
1676}
1677EXPORT_SYMBOL_GPL(kvm_cpuid);
1678
1679int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1680{
1681 u32 eax, ebx, ecx, edx;
1682
1683 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1684 return 1;
1685
1686 eax = kvm_rax_read(vcpu);
1687 ecx = kvm_rcx_read(vcpu);
1688 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1689 kvm_rax_write(vcpu, eax);
1690 kvm_rbx_write(vcpu, ebx);
1691 kvm_rcx_write(vcpu, ecx);
1692 kvm_rdx_write(vcpu, edx);
1693 return kvm_skip_emulated_instruction(vcpu);
1694}
1695EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);