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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2009 Samsung Electronics Co., Ltd.
4// Jaswinder Singh <jassi.brar@samsung.com>
5
6#include <linux/init.h>
7#include <linux/module.h>
8#include <linux/interrupt.h>
9#include <linux/delay.h>
10#include <linux/clk.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/spi/spi.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18
19#include <linux/platform_data/spi-s3c64xx.h>
20
21#define MAX_SPI_PORTS 12
22#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
23#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
24#define AUTOSUSPEND_TIMEOUT 2000
25
26/* Registers and bit-fields */
27
28#define S3C64XX_SPI_CH_CFG 0x00
29#define S3C64XX_SPI_CLK_CFG 0x04
30#define S3C64XX_SPI_MODE_CFG 0x08
31#define S3C64XX_SPI_CS_REG 0x0C
32#define S3C64XX_SPI_INT_EN 0x10
33#define S3C64XX_SPI_STATUS 0x14
34#define S3C64XX_SPI_TX_DATA 0x18
35#define S3C64XX_SPI_RX_DATA 0x1C
36#define S3C64XX_SPI_PACKET_CNT 0x20
37#define S3C64XX_SPI_PENDING_CLR 0x24
38#define S3C64XX_SPI_SWAP_CFG 0x28
39#define S3C64XX_SPI_FB_CLK 0x2C
40
41#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
42#define S3C64XX_SPI_CH_SW_RST (1<<5)
43#define S3C64XX_SPI_CH_SLAVE (1<<4)
44#define S3C64XX_SPI_CPOL_L (1<<3)
45#define S3C64XX_SPI_CPHA_B (1<<2)
46#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
47#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
48
49#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
50#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
51#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
52#define S3C64XX_SPI_PSR_MASK 0xff
53
54#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
55#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
56#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
57#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
58#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
59#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
60#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
61#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
62#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3)
63#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
64#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
65#define S3C64XX_SPI_MODE_4BURST (1<<0)
66
67#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4)
68#define S3C64XX_SPI_CS_AUTO (1<<1)
69#define S3C64XX_SPI_CS_SIG_INACT (1<<0)
70
71#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
72#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
73#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
74#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
75#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
76#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
77#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
78
79#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
80#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
81#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
82#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
83#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
84#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
85
86#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
87#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
88
89#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
90#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
91#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
92#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
93#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
94
95#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
96#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
97#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
98#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
99#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
100#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
101#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
102#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
103
104#define S3C64XX_SPI_FBCLK_MSK (3<<0)
105
106#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
107#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
108 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
109#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
110#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
111 FIFO_LVL_MASK(i))
112
113#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
114#define S3C64XX_SPI_TRAILCNT_OFF 19
115
116#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
117
118#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
119#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
120
121#define RXBUSY (1<<2)
122#define TXBUSY (1<<3)
123
124struct s3c64xx_spi_dma_data {
125 struct dma_chan *ch;
126 dma_cookie_t cookie;
127 enum dma_transfer_direction direction;
128};
129
130/**
131 * struct s3c64xx_spi_port_config - SPI Controller hardware info
132 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
133 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
134 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
135 * @clk_div: Internal clock divider
136 * @quirks: Bitmask of known quirks
137 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
138 * @clk_from_cmu: True, if the controller does not include a clock mux and
139 * prescaler unit.
140 * @clk_ioclk: True if clock is present on this device
141 * @has_loopback: True if loopback mode can be supported
142 *
143 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
144 * differ in some aspects such as the size of the fifo and spi bus clock
145 * setup. Such differences are specified to the driver using this structure
146 * which is provided as driver data to the driver.
147 */
148struct s3c64xx_spi_port_config {
149 int fifo_lvl_mask[MAX_SPI_PORTS];
150 int rx_lvl_offset;
151 int tx_st_done;
152 int quirks;
153 int clk_div;
154 bool high_speed;
155 bool clk_from_cmu;
156 bool clk_ioclk;
157 bool has_loopback;
158};
159
160/**
161 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
162 * @clk: Pointer to the spi clock.
163 * @src_clk: Pointer to the clock used to generate SPI signals.
164 * @ioclk: Pointer to the i/o clock between master and slave
165 * @pdev: Pointer to device's platform device data
166 * @master: Pointer to the SPI Protocol master.
167 * @cntrlr_info: Platform specific data for the controller this driver manages.
168 * @lock: Controller specific lock.
169 * @state: Set of FLAGS to indicate status.
170 * @sfr_start: BUS address of SPI controller regs.
171 * @regs: Pointer to ioremap'ed controller registers.
172 * @xfer_completion: To indicate completion of xfer task.
173 * @cur_mode: Stores the active configuration of the controller.
174 * @cur_bpw: Stores the active bits per word settings.
175 * @cur_speed: Current clock speed
176 * @rx_dma: Local receive DMA data (e.g. chan and direction)
177 * @tx_dma: Local transmit DMA data (e.g. chan and direction)
178 * @port_conf: Local SPI port configuartion data
179 * @port_id: Port identification number
180 */
181struct s3c64xx_spi_driver_data {
182 void __iomem *regs;
183 struct clk *clk;
184 struct clk *src_clk;
185 struct clk *ioclk;
186 struct platform_device *pdev;
187 struct spi_master *master;
188 struct s3c64xx_spi_info *cntrlr_info;
189 spinlock_t lock;
190 unsigned long sfr_start;
191 struct completion xfer_completion;
192 unsigned state;
193 unsigned cur_mode, cur_bpw;
194 unsigned cur_speed;
195 struct s3c64xx_spi_dma_data rx_dma;
196 struct s3c64xx_spi_dma_data tx_dma;
197 const struct s3c64xx_spi_port_config *port_conf;
198 unsigned int port_id;
199};
200
201static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
202{
203 void __iomem *regs = sdd->regs;
204 unsigned long loops;
205 u32 val;
206
207 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
208
209 val = readl(regs + S3C64XX_SPI_CH_CFG);
210 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
211 writel(val, regs + S3C64XX_SPI_CH_CFG);
212
213 val = readl(regs + S3C64XX_SPI_CH_CFG);
214 val |= S3C64XX_SPI_CH_SW_RST;
215 val &= ~S3C64XX_SPI_CH_HS_EN;
216 writel(val, regs + S3C64XX_SPI_CH_CFG);
217
218 /* Flush TxFIFO*/
219 loops = msecs_to_loops(1);
220 do {
221 val = readl(regs + S3C64XX_SPI_STATUS);
222 } while (TX_FIFO_LVL(val, sdd) && loops--);
223
224 if (loops == 0)
225 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
226
227 /* Flush RxFIFO*/
228 loops = msecs_to_loops(1);
229 do {
230 val = readl(regs + S3C64XX_SPI_STATUS);
231 if (RX_FIFO_LVL(val, sdd))
232 readl(regs + S3C64XX_SPI_RX_DATA);
233 else
234 break;
235 } while (loops--);
236
237 if (loops == 0)
238 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
239
240 val = readl(regs + S3C64XX_SPI_CH_CFG);
241 val &= ~S3C64XX_SPI_CH_SW_RST;
242 writel(val, regs + S3C64XX_SPI_CH_CFG);
243
244 val = readl(regs + S3C64XX_SPI_MODE_CFG);
245 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
246 writel(val, regs + S3C64XX_SPI_MODE_CFG);
247}
248
249static void s3c64xx_spi_dmacb(void *data)
250{
251 struct s3c64xx_spi_driver_data *sdd;
252 struct s3c64xx_spi_dma_data *dma = data;
253 unsigned long flags;
254
255 if (dma->direction == DMA_DEV_TO_MEM)
256 sdd = container_of(data,
257 struct s3c64xx_spi_driver_data, rx_dma);
258 else
259 sdd = container_of(data,
260 struct s3c64xx_spi_driver_data, tx_dma);
261
262 spin_lock_irqsave(&sdd->lock, flags);
263
264 if (dma->direction == DMA_DEV_TO_MEM) {
265 sdd->state &= ~RXBUSY;
266 if (!(sdd->state & TXBUSY))
267 complete(&sdd->xfer_completion);
268 } else {
269 sdd->state &= ~TXBUSY;
270 if (!(sdd->state & RXBUSY))
271 complete(&sdd->xfer_completion);
272 }
273
274 spin_unlock_irqrestore(&sdd->lock, flags);
275}
276
277static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
278 struct sg_table *sgt)
279{
280 struct s3c64xx_spi_driver_data *sdd;
281 struct dma_slave_config config;
282 struct dma_async_tx_descriptor *desc;
283 int ret;
284
285 memset(&config, 0, sizeof(config));
286
287 if (dma->direction == DMA_DEV_TO_MEM) {
288 sdd = container_of((void *)dma,
289 struct s3c64xx_spi_driver_data, rx_dma);
290 config.direction = dma->direction;
291 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
292 config.src_addr_width = sdd->cur_bpw / 8;
293 config.src_maxburst = 1;
294 dmaengine_slave_config(dma->ch, &config);
295 } else {
296 sdd = container_of((void *)dma,
297 struct s3c64xx_spi_driver_data, tx_dma);
298 config.direction = dma->direction;
299 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
300 config.dst_addr_width = sdd->cur_bpw / 8;
301 config.dst_maxburst = 1;
302 dmaengine_slave_config(dma->ch, &config);
303 }
304
305 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
306 dma->direction, DMA_PREP_INTERRUPT);
307 if (!desc) {
308 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
309 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
310 return -ENOMEM;
311 }
312
313 desc->callback = s3c64xx_spi_dmacb;
314 desc->callback_param = dma;
315
316 dma->cookie = dmaengine_submit(desc);
317 ret = dma_submit_error(dma->cookie);
318 if (ret) {
319 dev_err(&sdd->pdev->dev, "DMA submission failed");
320 return -EIO;
321 }
322
323 dma_async_issue_pending(dma->ch);
324 return 0;
325}
326
327static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
328{
329 struct s3c64xx_spi_driver_data *sdd =
330 spi_master_get_devdata(spi->master);
331
332 if (sdd->cntrlr_info->no_cs)
333 return;
334
335 if (enable) {
336 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
337 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
338 } else {
339 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
340
341 ssel |= (S3C64XX_SPI_CS_AUTO |
342 S3C64XX_SPI_CS_NSC_CNT_2);
343 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
344 }
345 } else {
346 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
347 writel(S3C64XX_SPI_CS_SIG_INACT,
348 sdd->regs + S3C64XX_SPI_CS_REG);
349 }
350}
351
352static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
353{
354 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
355
356 if (is_polling(sdd))
357 return 0;
358
359 /* Requests DMA channels */
360 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx");
361 if (IS_ERR(sdd->rx_dma.ch)) {
362 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n");
363 sdd->rx_dma.ch = NULL;
364 return 0;
365 }
366
367 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx");
368 if (IS_ERR(sdd->tx_dma.ch)) {
369 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n");
370 dma_release_channel(sdd->rx_dma.ch);
371 sdd->tx_dma.ch = NULL;
372 sdd->rx_dma.ch = NULL;
373 return 0;
374 }
375
376 spi->dma_rx = sdd->rx_dma.ch;
377 spi->dma_tx = sdd->tx_dma.ch;
378
379 return 0;
380}
381
382static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
383{
384 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
385
386 if (is_polling(sdd))
387 return 0;
388
389 /* Releases DMA channels if they are allocated */
390 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
391 dma_release_channel(sdd->rx_dma.ch);
392 dma_release_channel(sdd->tx_dma.ch);
393 sdd->rx_dma.ch = NULL;
394 sdd->tx_dma.ch = NULL;
395 }
396
397 return 0;
398}
399
400static bool s3c64xx_spi_can_dma(struct spi_master *master,
401 struct spi_device *spi,
402 struct spi_transfer *xfer)
403{
404 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
405
406 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
407 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
408 } else {
409 return false;
410 }
411
412}
413
414static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
415 struct spi_transfer *xfer, int dma_mode)
416{
417 void __iomem *regs = sdd->regs;
418 u32 modecfg, chcfg;
419 int ret = 0;
420
421 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
422 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
423
424 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
425 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
426
427 if (dma_mode) {
428 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
429 } else {
430 /* Always shift in data in FIFO, even if xfer is Tx only,
431 * this helps setting PCKT_CNT value for generating clocks
432 * as exactly needed.
433 */
434 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
435 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
436 | S3C64XX_SPI_PACKET_CNT_EN,
437 regs + S3C64XX_SPI_PACKET_CNT);
438 }
439
440 if (xfer->tx_buf != NULL) {
441 sdd->state |= TXBUSY;
442 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
443 if (dma_mode) {
444 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
445 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
446 } else {
447 switch (sdd->cur_bpw) {
448 case 32:
449 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
450 xfer->tx_buf, xfer->len / 4);
451 break;
452 case 16:
453 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
454 xfer->tx_buf, xfer->len / 2);
455 break;
456 default:
457 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
458 xfer->tx_buf, xfer->len);
459 break;
460 }
461 }
462 }
463
464 if (xfer->rx_buf != NULL) {
465 sdd->state |= RXBUSY;
466
467 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
468 && !(sdd->cur_mode & SPI_CPHA))
469 chcfg |= S3C64XX_SPI_CH_HS_EN;
470
471 if (dma_mode) {
472 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
473 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
474 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
475 | S3C64XX_SPI_PACKET_CNT_EN,
476 regs + S3C64XX_SPI_PACKET_CNT);
477 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
478 }
479 }
480
481 if (ret)
482 return ret;
483
484 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
485 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
486
487 return 0;
488}
489
490static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
491 int timeout_ms)
492{
493 void __iomem *regs = sdd->regs;
494 unsigned long val = 1;
495 u32 status;
496
497 /* max fifo depth available */
498 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
499
500 if (timeout_ms)
501 val = msecs_to_loops(timeout_ms);
502
503 do {
504 status = readl(regs + S3C64XX_SPI_STATUS);
505 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
506
507 /* return the actual received data length */
508 return RX_FIFO_LVL(status, sdd);
509}
510
511static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
512 struct spi_transfer *xfer)
513{
514 void __iomem *regs = sdd->regs;
515 unsigned long val;
516 u32 status;
517 int ms;
518
519 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
520 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
521 ms += 30; /* some tolerance */
522 ms = max(ms, 100); /* minimum timeout */
523
524 val = msecs_to_jiffies(ms) + 10;
525 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
526
527 /*
528 * If the previous xfer was completed within timeout, then
529 * proceed further else return -EIO.
530 * DmaTx returns after simply writing data in the FIFO,
531 * w/o waiting for real transmission on the bus to finish.
532 * DmaRx returns only after Dma read data from FIFO which
533 * needs bus transmission to finish, so we don't worry if
534 * Xfer involved Rx(with or without Tx).
535 */
536 if (val && !xfer->rx_buf) {
537 val = msecs_to_loops(10);
538 status = readl(regs + S3C64XX_SPI_STATUS);
539 while ((TX_FIFO_LVL(status, sdd)
540 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
541 && --val) {
542 cpu_relax();
543 status = readl(regs + S3C64XX_SPI_STATUS);
544 }
545
546 }
547
548 /* If timed out while checking rx/tx status return error */
549 if (!val)
550 return -EIO;
551
552 return 0;
553}
554
555static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
556 struct spi_transfer *xfer)
557{
558 void __iomem *regs = sdd->regs;
559 unsigned long val;
560 u32 status;
561 int loops;
562 u32 cpy_len;
563 u8 *buf;
564 int ms;
565
566 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
567 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
568 ms += 10; /* some tolerance */
569
570 val = msecs_to_loops(ms);
571 do {
572 status = readl(regs + S3C64XX_SPI_STATUS);
573 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
574
575 if (!val)
576 return -EIO;
577
578 /* If it was only Tx */
579 if (!xfer->rx_buf) {
580 sdd->state &= ~TXBUSY;
581 return 0;
582 }
583
584 /*
585 * If the receive length is bigger than the controller fifo
586 * size, calculate the loops and read the fifo as many times.
587 * loops = length / max fifo size (calculated by using the
588 * fifo mask).
589 * For any size less than the fifo size the below code is
590 * executed atleast once.
591 */
592 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
593 buf = xfer->rx_buf;
594 do {
595 /* wait for data to be received in the fifo */
596 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
597 (loops ? ms : 0));
598
599 switch (sdd->cur_bpw) {
600 case 32:
601 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
602 buf, cpy_len / 4);
603 break;
604 case 16:
605 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
606 buf, cpy_len / 2);
607 break;
608 default:
609 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
610 buf, cpy_len);
611 break;
612 }
613
614 buf = buf + cpy_len;
615 } while (loops--);
616 sdd->state &= ~RXBUSY;
617
618 return 0;
619}
620
621static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
622{
623 void __iomem *regs = sdd->regs;
624 int ret;
625 u32 val;
626 int div = sdd->port_conf->clk_div;
627
628 /* Disable Clock */
629 if (!sdd->port_conf->clk_from_cmu) {
630 val = readl(regs + S3C64XX_SPI_CLK_CFG);
631 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
632 writel(val, regs + S3C64XX_SPI_CLK_CFG);
633 }
634
635 /* Set Polarity and Phase */
636 val = readl(regs + S3C64XX_SPI_CH_CFG);
637 val &= ~(S3C64XX_SPI_CH_SLAVE |
638 S3C64XX_SPI_CPOL_L |
639 S3C64XX_SPI_CPHA_B);
640
641 if (sdd->cur_mode & SPI_CPOL)
642 val |= S3C64XX_SPI_CPOL_L;
643
644 if (sdd->cur_mode & SPI_CPHA)
645 val |= S3C64XX_SPI_CPHA_B;
646
647 writel(val, regs + S3C64XX_SPI_CH_CFG);
648
649 /* Set Channel & DMA Mode */
650 val = readl(regs + S3C64XX_SPI_MODE_CFG);
651 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
652 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
653
654 switch (sdd->cur_bpw) {
655 case 32:
656 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
657 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
658 break;
659 case 16:
660 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
661 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
662 break;
663 default:
664 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
665 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
666 break;
667 }
668
669 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback)
670 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK;
671
672 writel(val, regs + S3C64XX_SPI_MODE_CFG);
673
674 if (sdd->port_conf->clk_from_cmu) {
675 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div);
676 if (ret)
677 return ret;
678 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div;
679 } else {
680 /* Configure Clock */
681 val = readl(regs + S3C64XX_SPI_CLK_CFG);
682 val &= ~S3C64XX_SPI_PSR_MASK;
683 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1)
684 & S3C64XX_SPI_PSR_MASK);
685 writel(val, regs + S3C64XX_SPI_CLK_CFG);
686
687 /* Enable Clock */
688 val = readl(regs + S3C64XX_SPI_CLK_CFG);
689 val |= S3C64XX_SPI_ENCLK_ENABLE;
690 writel(val, regs + S3C64XX_SPI_CLK_CFG);
691 }
692
693 return 0;
694}
695
696#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
697
698static int s3c64xx_spi_prepare_message(struct spi_master *master,
699 struct spi_message *msg)
700{
701 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
702 struct spi_device *spi = msg->spi;
703 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
704
705 /* Configure feedback delay */
706 if (!cs)
707 /* No delay if not defined */
708 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
709 else
710 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
711
712 return 0;
713}
714
715static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
716{
717 struct spi_controller *ctlr = spi->controller;
718
719 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
720}
721
722static int s3c64xx_spi_transfer_one(struct spi_master *master,
723 struct spi_device *spi,
724 struct spi_transfer *xfer)
725{
726 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
727 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
728 const void *tx_buf = NULL;
729 void *rx_buf = NULL;
730 int target_len = 0, origin_len = 0;
731 int use_dma = 0;
732 int status;
733 u32 speed;
734 u8 bpw;
735 unsigned long flags;
736
737 reinit_completion(&sdd->xfer_completion);
738
739 /* Only BPW and Speed may change across transfers */
740 bpw = xfer->bits_per_word;
741 speed = xfer->speed_hz;
742
743 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
744 sdd->cur_bpw = bpw;
745 sdd->cur_speed = speed;
746 sdd->cur_mode = spi->mode;
747 status = s3c64xx_spi_config(sdd);
748 if (status)
749 return status;
750 }
751
752 if (!is_polling(sdd) && (xfer->len > fifo_len) &&
753 sdd->rx_dma.ch && sdd->tx_dma.ch) {
754 use_dma = 1;
755
756 } else if (xfer->len > fifo_len) {
757 tx_buf = xfer->tx_buf;
758 rx_buf = xfer->rx_buf;
759 origin_len = xfer->len;
760
761 target_len = xfer->len;
762 if (xfer->len > fifo_len)
763 xfer->len = fifo_len;
764 }
765
766 do {
767 spin_lock_irqsave(&sdd->lock, flags);
768
769 /* Pending only which is to be done */
770 sdd->state &= ~RXBUSY;
771 sdd->state &= ~TXBUSY;
772
773 /* Start the signals */
774 s3c64xx_spi_set_cs(spi, true);
775
776 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
777
778 spin_unlock_irqrestore(&sdd->lock, flags);
779
780 if (status) {
781 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
782 break;
783 }
784
785 if (use_dma)
786 status = s3c64xx_wait_for_dma(sdd, xfer);
787 else
788 status = s3c64xx_wait_for_pio(sdd, xfer);
789
790 if (status) {
791 dev_err(&spi->dev,
792 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
793 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
794 (sdd->state & RXBUSY) ? 'f' : 'p',
795 (sdd->state & TXBUSY) ? 'f' : 'p',
796 xfer->len, use_dma ? 1 : 0, status);
797
798 if (use_dma) {
799 struct dma_tx_state s;
800
801 if (xfer->tx_buf && (sdd->state & TXBUSY)) {
802 dmaengine_pause(sdd->tx_dma.ch);
803 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
804 dmaengine_terminate_all(sdd->tx_dma.ch);
805 dev_err(&spi->dev, "TX residue: %d\n", s.residue);
806
807 }
808 if (xfer->rx_buf && (sdd->state & RXBUSY)) {
809 dmaengine_pause(sdd->rx_dma.ch);
810 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
811 dmaengine_terminate_all(sdd->rx_dma.ch);
812 dev_err(&spi->dev, "RX residue: %d\n", s.residue);
813 }
814 }
815 } else {
816 s3c64xx_flush_fifo(sdd);
817 }
818 if (target_len > 0) {
819 target_len -= xfer->len;
820
821 if (xfer->tx_buf)
822 xfer->tx_buf += xfer->len;
823
824 if (xfer->rx_buf)
825 xfer->rx_buf += xfer->len;
826
827 if (target_len > fifo_len)
828 xfer->len = fifo_len;
829 else
830 xfer->len = target_len;
831 }
832 } while (target_len > 0);
833
834 if (origin_len) {
835 /* Restore original xfer buffers and length */
836 xfer->tx_buf = tx_buf;
837 xfer->rx_buf = rx_buf;
838 xfer->len = origin_len;
839 }
840
841 return status;
842}
843
844static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
845 struct spi_device *spi)
846{
847 struct s3c64xx_spi_csinfo *cs;
848 struct device_node *slave_np, *data_np = NULL;
849 u32 fb_delay = 0;
850
851 slave_np = spi->dev.of_node;
852 if (!slave_np) {
853 dev_err(&spi->dev, "device node not found\n");
854 return ERR_PTR(-EINVAL);
855 }
856
857 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
858 if (!cs)
859 return ERR_PTR(-ENOMEM);
860
861 data_np = of_get_child_by_name(slave_np, "controller-data");
862 if (!data_np) {
863 dev_info(&spi->dev, "feedback delay set to default (0)\n");
864 return cs;
865 }
866
867 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
868 cs->fb_delay = fb_delay;
869 of_node_put(data_np);
870 return cs;
871}
872
873/*
874 * Here we only check the validity of requested configuration
875 * and save the configuration in a local data-structure.
876 * The controller is actually configured only just before we
877 * get a message to transfer.
878 */
879static int s3c64xx_spi_setup(struct spi_device *spi)
880{
881 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
882 struct s3c64xx_spi_driver_data *sdd;
883 int err;
884 int div;
885
886 sdd = spi_master_get_devdata(spi->master);
887 if (spi->dev.of_node) {
888 cs = s3c64xx_get_slave_ctrldata(spi);
889 spi->controller_data = cs;
890 }
891
892 /* NULL is fine, we just avoid using the FB delay (=0) */
893 if (IS_ERR(cs)) {
894 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
895 return -ENODEV;
896 }
897
898 if (!spi_get_ctldata(spi))
899 spi_set_ctldata(spi, cs);
900
901 pm_runtime_get_sync(&sdd->pdev->dev);
902
903 div = sdd->port_conf->clk_div;
904
905 /* Check if we can provide the requested rate */
906 if (!sdd->port_conf->clk_from_cmu) {
907 u32 psr, speed;
908
909 /* Max possible */
910 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1);
911
912 if (spi->max_speed_hz > speed)
913 spi->max_speed_hz = speed;
914
915 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
916 psr &= S3C64XX_SPI_PSR_MASK;
917 if (psr == S3C64XX_SPI_PSR_MASK)
918 psr--;
919
920 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
921 if (spi->max_speed_hz < speed) {
922 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
923 psr++;
924 } else {
925 err = -EINVAL;
926 goto setup_exit;
927 }
928 }
929
930 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
931 if (spi->max_speed_hz >= speed) {
932 spi->max_speed_hz = speed;
933 } else {
934 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
935 spi->max_speed_hz);
936 err = -EINVAL;
937 goto setup_exit;
938 }
939 }
940
941 pm_runtime_mark_last_busy(&sdd->pdev->dev);
942 pm_runtime_put_autosuspend(&sdd->pdev->dev);
943 s3c64xx_spi_set_cs(spi, false);
944
945 return 0;
946
947setup_exit:
948 pm_runtime_mark_last_busy(&sdd->pdev->dev);
949 pm_runtime_put_autosuspend(&sdd->pdev->dev);
950 /* setup() returns with device de-selected */
951 s3c64xx_spi_set_cs(spi, false);
952
953 spi_set_ctldata(spi, NULL);
954
955 /* This was dynamically allocated on the DT path */
956 if (spi->dev.of_node)
957 kfree(cs);
958
959 return err;
960}
961
962static void s3c64xx_spi_cleanup(struct spi_device *spi)
963{
964 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
965
966 /* This was dynamically allocated on the DT path */
967 if (spi->dev.of_node)
968 kfree(cs);
969
970 spi_set_ctldata(spi, NULL);
971}
972
973static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
974{
975 struct s3c64xx_spi_driver_data *sdd = data;
976 struct spi_master *spi = sdd->master;
977 unsigned int val, clr = 0;
978
979 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
980
981 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
982 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
983 dev_err(&spi->dev, "RX overrun\n");
984 }
985 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
986 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
987 dev_err(&spi->dev, "RX underrun\n");
988 }
989 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
990 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
991 dev_err(&spi->dev, "TX overrun\n");
992 }
993 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
994 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
995 dev_err(&spi->dev, "TX underrun\n");
996 }
997
998 /* Clear the pending irq by setting and then clearing it */
999 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1000 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1001
1002 return IRQ_HANDLED;
1003}
1004
1005static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
1006{
1007 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1008 void __iomem *regs = sdd->regs;
1009 unsigned int val;
1010
1011 sdd->cur_speed = 0;
1012
1013 if (sci->no_cs)
1014 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
1015 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
1016 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
1017
1018 /* Disable Interrupts - we use Polling if not DMA mode */
1019 writel(0, regs + S3C64XX_SPI_INT_EN);
1020
1021 if (!sdd->port_conf->clk_from_cmu)
1022 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1023 regs + S3C64XX_SPI_CLK_CFG);
1024 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1025 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1026
1027 /* Clear any irq pending bits, should set and clear the bits */
1028 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1029 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1030 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1031 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1032 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1033 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1034
1035 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1036
1037 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1038 val &= ~S3C64XX_SPI_MODE_4BURST;
1039 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1040 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1041 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1042
1043 s3c64xx_flush_fifo(sdd);
1044}
1045
1046#ifdef CONFIG_OF
1047static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1048{
1049 struct s3c64xx_spi_info *sci;
1050 u32 temp;
1051
1052 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1053 if (!sci)
1054 return ERR_PTR(-ENOMEM);
1055
1056 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1057 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1058 sci->src_clk_nr = 0;
1059 } else {
1060 sci->src_clk_nr = temp;
1061 }
1062
1063 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1064 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1065 sci->num_cs = 1;
1066 } else {
1067 sci->num_cs = temp;
1068 }
1069
1070 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1071
1072 return sci;
1073}
1074#else
1075static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1076{
1077 return dev_get_platdata(dev);
1078}
1079#endif
1080
1081static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1082 struct platform_device *pdev)
1083{
1084#ifdef CONFIG_OF
1085 if (pdev->dev.of_node)
1086 return of_device_get_match_data(&pdev->dev);
1087#endif
1088 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1089}
1090
1091static int s3c64xx_spi_probe(struct platform_device *pdev)
1092{
1093 struct resource *mem_res;
1094 struct s3c64xx_spi_driver_data *sdd;
1095 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1096 struct spi_master *master;
1097 int ret, irq;
1098 char clk_name[16];
1099
1100 if (!sci && pdev->dev.of_node) {
1101 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1102 if (IS_ERR(sci))
1103 return PTR_ERR(sci);
1104 }
1105
1106 if (!sci) {
1107 dev_err(&pdev->dev, "platform_data missing!\n");
1108 return -ENODEV;
1109 }
1110
1111 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1112 if (mem_res == NULL) {
1113 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1114 return -ENXIO;
1115 }
1116
1117 irq = platform_get_irq(pdev, 0);
1118 if (irq < 0) {
1119 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1120 return irq;
1121 }
1122
1123 master = spi_alloc_master(&pdev->dev,
1124 sizeof(struct s3c64xx_spi_driver_data));
1125 if (master == NULL) {
1126 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1127 return -ENOMEM;
1128 }
1129
1130 platform_set_drvdata(pdev, master);
1131
1132 sdd = spi_master_get_devdata(master);
1133 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1134 sdd->master = master;
1135 sdd->cntrlr_info = sci;
1136 sdd->pdev = pdev;
1137 sdd->sfr_start = mem_res->start;
1138 if (pdev->dev.of_node) {
1139 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1140 if (ret < 0) {
1141 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1142 ret);
1143 goto err_deref_master;
1144 }
1145 sdd->port_id = ret;
1146 } else {
1147 sdd->port_id = pdev->id;
1148 }
1149
1150 sdd->cur_bpw = 8;
1151
1152 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1153 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1154
1155 master->dev.of_node = pdev->dev.of_node;
1156 master->bus_num = sdd->port_id;
1157 master->setup = s3c64xx_spi_setup;
1158 master->cleanup = s3c64xx_spi_cleanup;
1159 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1160 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1161 master->prepare_message = s3c64xx_spi_prepare_message;
1162 master->transfer_one = s3c64xx_spi_transfer_one;
1163 master->max_transfer_size = s3c64xx_spi_max_transfer_size;
1164 master->num_chipselect = sci->num_cs;
1165 master->use_gpio_descriptors = true;
1166 master->dma_alignment = 8;
1167 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1168 SPI_BPW_MASK(8);
1169 /* the spi->mode bits understood by this driver: */
1170 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1171 if (sdd->port_conf->has_loopback)
1172 master->mode_bits |= SPI_LOOP;
1173 master->auto_runtime_pm = true;
1174 if (!is_polling(sdd))
1175 master->can_dma = s3c64xx_spi_can_dma;
1176
1177 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1178 if (IS_ERR(sdd->regs)) {
1179 ret = PTR_ERR(sdd->regs);
1180 goto err_deref_master;
1181 }
1182
1183 if (sci->cfg_gpio && sci->cfg_gpio()) {
1184 dev_err(&pdev->dev, "Unable to config gpio\n");
1185 ret = -EBUSY;
1186 goto err_deref_master;
1187 }
1188
1189 /* Setup clocks */
1190 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1191 if (IS_ERR(sdd->clk)) {
1192 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1193 ret = PTR_ERR(sdd->clk);
1194 goto err_deref_master;
1195 }
1196
1197 ret = clk_prepare_enable(sdd->clk);
1198 if (ret) {
1199 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1200 goto err_deref_master;
1201 }
1202
1203 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1204 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1205 if (IS_ERR(sdd->src_clk)) {
1206 dev_err(&pdev->dev,
1207 "Unable to acquire clock '%s'\n", clk_name);
1208 ret = PTR_ERR(sdd->src_clk);
1209 goto err_disable_clk;
1210 }
1211
1212 ret = clk_prepare_enable(sdd->src_clk);
1213 if (ret) {
1214 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1215 goto err_disable_clk;
1216 }
1217
1218 if (sdd->port_conf->clk_ioclk) {
1219 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1220 if (IS_ERR(sdd->ioclk)) {
1221 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1222 ret = PTR_ERR(sdd->ioclk);
1223 goto err_disable_src_clk;
1224 }
1225
1226 ret = clk_prepare_enable(sdd->ioclk);
1227 if (ret) {
1228 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1229 goto err_disable_src_clk;
1230 }
1231 }
1232
1233 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1234 pm_runtime_use_autosuspend(&pdev->dev);
1235 pm_runtime_set_active(&pdev->dev);
1236 pm_runtime_enable(&pdev->dev);
1237 pm_runtime_get_sync(&pdev->dev);
1238
1239 /* Setup Deufult Mode */
1240 s3c64xx_spi_hwinit(sdd);
1241
1242 spin_lock_init(&sdd->lock);
1243 init_completion(&sdd->xfer_completion);
1244
1245 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1246 "spi-s3c64xx", sdd);
1247 if (ret != 0) {
1248 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1249 irq, ret);
1250 goto err_pm_put;
1251 }
1252
1253 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1254 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1255 sdd->regs + S3C64XX_SPI_INT_EN);
1256
1257 ret = devm_spi_register_master(&pdev->dev, master);
1258 if (ret != 0) {
1259 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1260 goto err_pm_put;
1261 }
1262
1263 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1264 sdd->port_id, master->num_chipselect);
1265 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1266 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1267
1268 pm_runtime_mark_last_busy(&pdev->dev);
1269 pm_runtime_put_autosuspend(&pdev->dev);
1270
1271 return 0;
1272
1273err_pm_put:
1274 pm_runtime_put_noidle(&pdev->dev);
1275 pm_runtime_disable(&pdev->dev);
1276 pm_runtime_set_suspended(&pdev->dev);
1277
1278 clk_disable_unprepare(sdd->ioclk);
1279err_disable_src_clk:
1280 clk_disable_unprepare(sdd->src_clk);
1281err_disable_clk:
1282 clk_disable_unprepare(sdd->clk);
1283err_deref_master:
1284 spi_master_put(master);
1285
1286 return ret;
1287}
1288
1289static int s3c64xx_spi_remove(struct platform_device *pdev)
1290{
1291 struct spi_master *master = platform_get_drvdata(pdev);
1292 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1293
1294 pm_runtime_get_sync(&pdev->dev);
1295
1296 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1297
1298 if (!is_polling(sdd)) {
1299 dma_release_channel(sdd->rx_dma.ch);
1300 dma_release_channel(sdd->tx_dma.ch);
1301 }
1302
1303 clk_disable_unprepare(sdd->ioclk);
1304
1305 clk_disable_unprepare(sdd->src_clk);
1306
1307 clk_disable_unprepare(sdd->clk);
1308
1309 pm_runtime_put_noidle(&pdev->dev);
1310 pm_runtime_disable(&pdev->dev);
1311 pm_runtime_set_suspended(&pdev->dev);
1312
1313 return 0;
1314}
1315
1316#ifdef CONFIG_PM_SLEEP
1317static int s3c64xx_spi_suspend(struct device *dev)
1318{
1319 struct spi_master *master = dev_get_drvdata(dev);
1320 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1321
1322 int ret = spi_master_suspend(master);
1323 if (ret)
1324 return ret;
1325
1326 ret = pm_runtime_force_suspend(dev);
1327 if (ret < 0)
1328 return ret;
1329
1330 sdd->cur_speed = 0; /* Output Clock is stopped */
1331
1332 return 0;
1333}
1334
1335static int s3c64xx_spi_resume(struct device *dev)
1336{
1337 struct spi_master *master = dev_get_drvdata(dev);
1338 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1339 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1340 int ret;
1341
1342 if (sci->cfg_gpio)
1343 sci->cfg_gpio();
1344
1345 ret = pm_runtime_force_resume(dev);
1346 if (ret < 0)
1347 return ret;
1348
1349 return spi_master_resume(master);
1350}
1351#endif /* CONFIG_PM_SLEEP */
1352
1353#ifdef CONFIG_PM
1354static int s3c64xx_spi_runtime_suspend(struct device *dev)
1355{
1356 struct spi_master *master = dev_get_drvdata(dev);
1357 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1358
1359 clk_disable_unprepare(sdd->clk);
1360 clk_disable_unprepare(sdd->src_clk);
1361 clk_disable_unprepare(sdd->ioclk);
1362
1363 return 0;
1364}
1365
1366static int s3c64xx_spi_runtime_resume(struct device *dev)
1367{
1368 struct spi_master *master = dev_get_drvdata(dev);
1369 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1370 int ret;
1371
1372 if (sdd->port_conf->clk_ioclk) {
1373 ret = clk_prepare_enable(sdd->ioclk);
1374 if (ret != 0)
1375 return ret;
1376 }
1377
1378 ret = clk_prepare_enable(sdd->src_clk);
1379 if (ret != 0)
1380 goto err_disable_ioclk;
1381
1382 ret = clk_prepare_enable(sdd->clk);
1383 if (ret != 0)
1384 goto err_disable_src_clk;
1385
1386 s3c64xx_spi_hwinit(sdd);
1387
1388 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1389 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1390 sdd->regs + S3C64XX_SPI_INT_EN);
1391
1392 return 0;
1393
1394err_disable_src_clk:
1395 clk_disable_unprepare(sdd->src_clk);
1396err_disable_ioclk:
1397 clk_disable_unprepare(sdd->ioclk);
1398
1399 return ret;
1400}
1401#endif /* CONFIG_PM */
1402
1403static const struct dev_pm_ops s3c64xx_spi_pm = {
1404 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1405 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1406 s3c64xx_spi_runtime_resume, NULL)
1407};
1408
1409static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1410 .fifo_lvl_mask = { 0x7f },
1411 .rx_lvl_offset = 13,
1412 .tx_st_done = 21,
1413 .clk_div = 2,
1414 .high_speed = true,
1415};
1416
1417static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1418 .fifo_lvl_mask = { 0x7f, 0x7F },
1419 .rx_lvl_offset = 13,
1420 .tx_st_done = 21,
1421 .clk_div = 2,
1422};
1423
1424static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1425 .fifo_lvl_mask = { 0x1ff, 0x7F },
1426 .rx_lvl_offset = 15,
1427 .tx_st_done = 25,
1428 .clk_div = 2,
1429 .high_speed = true,
1430};
1431
1432static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1433 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1434 .rx_lvl_offset = 15,
1435 .tx_st_done = 25,
1436 .clk_div = 2,
1437 .high_speed = true,
1438 .clk_from_cmu = true,
1439 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1440};
1441
1442static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1443 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1444 .rx_lvl_offset = 15,
1445 .tx_st_done = 25,
1446 .clk_div = 2,
1447 .high_speed = true,
1448 .clk_from_cmu = true,
1449 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1450};
1451
1452static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1453 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1454 .rx_lvl_offset = 15,
1455 .tx_st_done = 25,
1456 .clk_div = 2,
1457 .high_speed = true,
1458 .clk_from_cmu = true,
1459 .clk_ioclk = true,
1460 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1461};
1462
1463static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
1464 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
1465 0x7f, 0x7f, 0x7f, 0x7f},
1466 .rx_lvl_offset = 15,
1467 .tx_st_done = 25,
1468 .clk_div = 4,
1469 .high_speed = true,
1470 .clk_from_cmu = true,
1471 .clk_ioclk = true,
1472 .has_loopback = true,
1473 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1474};
1475
1476static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
1477 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
1478 .rx_lvl_offset = 15,
1479 .tx_st_done = 25,
1480 .clk_div = 2,
1481 .high_speed = true,
1482 .clk_from_cmu = true,
1483 .clk_ioclk = false,
1484 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1485};
1486
1487static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1488 {
1489 .name = "s3c2443-spi",
1490 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1491 }, {
1492 .name = "s3c6410-spi",
1493 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1494 },
1495 { },
1496};
1497
1498static const struct of_device_id s3c64xx_spi_dt_match[] = {
1499 { .compatible = "samsung,s3c2443-spi",
1500 .data = (void *)&s3c2443_spi_port_config,
1501 },
1502 { .compatible = "samsung,s3c6410-spi",
1503 .data = (void *)&s3c6410_spi_port_config,
1504 },
1505 { .compatible = "samsung,s5pv210-spi",
1506 .data = (void *)&s5pv210_spi_port_config,
1507 },
1508 { .compatible = "samsung,exynos4210-spi",
1509 .data = (void *)&exynos4_spi_port_config,
1510 },
1511 { .compatible = "samsung,exynos7-spi",
1512 .data = (void *)&exynos7_spi_port_config,
1513 },
1514 { .compatible = "samsung,exynos5433-spi",
1515 .data = (void *)&exynos5433_spi_port_config,
1516 },
1517 { .compatible = "samsung,exynosautov9-spi",
1518 .data = (void *)&exynosautov9_spi_port_config,
1519 },
1520 { .compatible = "tesla,fsd-spi",
1521 .data = (void *)&fsd_spi_port_config,
1522 },
1523 { },
1524};
1525MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1526
1527static struct platform_driver s3c64xx_spi_driver = {
1528 .driver = {
1529 .name = "s3c64xx-spi",
1530 .pm = &s3c64xx_spi_pm,
1531 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1532 },
1533 .probe = s3c64xx_spi_probe,
1534 .remove = s3c64xx_spi_remove,
1535 .id_table = s3c64xx_spi_driver_ids,
1536};
1537MODULE_ALIAS("platform:s3c64xx-spi");
1538
1539module_platform_driver(s3c64xx_spi_driver);
1540
1541MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1542MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1543MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2009 Samsung Electronics Co., Ltd.
4// Jaswinder Singh <jassi.brar@samsung.com>
5
6#include <linux/init.h>
7#include <linux/module.h>
8#include <linux/interrupt.h>
9#include <linux/delay.h>
10#include <linux/clk.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/spi/spi.h>
16#include <linux/gpio.h>
17#include <linux/of.h>
18#include <linux/of_gpio.h>
19
20#include <linux/platform_data/spi-s3c64xx.h>
21
22#define MAX_SPI_PORTS 6
23#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
24#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
25#define AUTOSUSPEND_TIMEOUT 2000
26
27/* Registers and bit-fields */
28
29#define S3C64XX_SPI_CH_CFG 0x00
30#define S3C64XX_SPI_CLK_CFG 0x04
31#define S3C64XX_SPI_MODE_CFG 0x08
32#define S3C64XX_SPI_SLAVE_SEL 0x0C
33#define S3C64XX_SPI_INT_EN 0x10
34#define S3C64XX_SPI_STATUS 0x14
35#define S3C64XX_SPI_TX_DATA 0x18
36#define S3C64XX_SPI_RX_DATA 0x1C
37#define S3C64XX_SPI_PACKET_CNT 0x20
38#define S3C64XX_SPI_PENDING_CLR 0x24
39#define S3C64XX_SPI_SWAP_CFG 0x28
40#define S3C64XX_SPI_FB_CLK 0x2C
41
42#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
43#define S3C64XX_SPI_CH_SW_RST (1<<5)
44#define S3C64XX_SPI_CH_SLAVE (1<<4)
45#define S3C64XX_SPI_CPOL_L (1<<3)
46#define S3C64XX_SPI_CPHA_B (1<<2)
47#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
48#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
49
50#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
51#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
52#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
53#define S3C64XX_SPI_PSR_MASK 0xff
54
55#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
56#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
57#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
58#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
59#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
60#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
61#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
62#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
63#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
64#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
65#define S3C64XX_SPI_MODE_4BURST (1<<0)
66
67#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
68#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
69#define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4)
70
71#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
72#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
73#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
74#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
75#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
76#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
77#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
78
79#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
80#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
81#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
82#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
83#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
84#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
85
86#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
87
88#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
89#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
90#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
91#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
92#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
93
94#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
95#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
96#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
97#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
98#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
99#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
100#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
101#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
102
103#define S3C64XX_SPI_FBCLK_MSK (3<<0)
104
105#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
106#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
107 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
108#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
109#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
110 FIFO_LVL_MASK(i))
111
112#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
113#define S3C64XX_SPI_TRAILCNT_OFF 19
114
115#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
116
117#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
118#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
119
120#define RXBUSY (1<<2)
121#define TXBUSY (1<<3)
122
123struct s3c64xx_spi_dma_data {
124 struct dma_chan *ch;
125 enum dma_transfer_direction direction;
126};
127
128/**
129 * struct s3c64xx_spi_info - SPI Controller hardware info
130 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
131 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
132 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
133 * @quirks: Bitmask of known quirks
134 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
135 * @clk_from_cmu: True, if the controller does not include a clock mux and
136 * prescaler unit.
137 * @clk_ioclk: True if clock is present on this device
138 *
139 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
140 * differ in some aspects such as the size of the fifo and spi bus clock
141 * setup. Such differences are specified to the driver using this structure
142 * which is provided as driver data to the driver.
143 */
144struct s3c64xx_spi_port_config {
145 int fifo_lvl_mask[MAX_SPI_PORTS];
146 int rx_lvl_offset;
147 int tx_st_done;
148 int quirks;
149 bool high_speed;
150 bool clk_from_cmu;
151 bool clk_ioclk;
152};
153
154/**
155 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
156 * @clk: Pointer to the spi clock.
157 * @src_clk: Pointer to the clock used to generate SPI signals.
158 * @ioclk: Pointer to the i/o clock between master and slave
159 * @pdev: Pointer to device's platform device data
160 * @master: Pointer to the SPI Protocol master.
161 * @cntrlr_info: Platform specific data for the controller this driver manages.
162 * @lock: Controller specific lock.
163 * @state: Set of FLAGS to indicate status.
164 * @rx_dmach: Controller's DMA channel for Rx.
165 * @tx_dmach: Controller's DMA channel for Tx.
166 * @sfr_start: BUS address of SPI controller regs.
167 * @regs: Pointer to ioremap'ed controller registers.
168 * @irq: interrupt
169 * @xfer_completion: To indicate completion of xfer task.
170 * @cur_mode: Stores the active configuration of the controller.
171 * @cur_bpw: Stores the active bits per word settings.
172 * @cur_speed: Current clock speed
173 * @rx_dma: Local receive DMA data (e.g. chan and direction)
174 * @tx_dma: Local transmit DMA data (e.g. chan and direction)
175 * @port_conf: Local SPI port configuartion data
176 * @port_id: Port identification number
177 */
178struct s3c64xx_spi_driver_data {
179 void __iomem *regs;
180 struct clk *clk;
181 struct clk *src_clk;
182 struct clk *ioclk;
183 struct platform_device *pdev;
184 struct spi_master *master;
185 struct s3c64xx_spi_info *cntrlr_info;
186 spinlock_t lock;
187 unsigned long sfr_start;
188 struct completion xfer_completion;
189 unsigned state;
190 unsigned cur_mode, cur_bpw;
191 unsigned cur_speed;
192 struct s3c64xx_spi_dma_data rx_dma;
193 struct s3c64xx_spi_dma_data tx_dma;
194 struct s3c64xx_spi_port_config *port_conf;
195 unsigned int port_id;
196};
197
198static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
199{
200 void __iomem *regs = sdd->regs;
201 unsigned long loops;
202 u32 val;
203
204 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
205
206 val = readl(regs + S3C64XX_SPI_CH_CFG);
207 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
208 writel(val, regs + S3C64XX_SPI_CH_CFG);
209
210 val = readl(regs + S3C64XX_SPI_CH_CFG);
211 val |= S3C64XX_SPI_CH_SW_RST;
212 val &= ~S3C64XX_SPI_CH_HS_EN;
213 writel(val, regs + S3C64XX_SPI_CH_CFG);
214
215 /* Flush TxFIFO*/
216 loops = msecs_to_loops(1);
217 do {
218 val = readl(regs + S3C64XX_SPI_STATUS);
219 } while (TX_FIFO_LVL(val, sdd) && loops--);
220
221 if (loops == 0)
222 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
223
224 /* Flush RxFIFO*/
225 loops = msecs_to_loops(1);
226 do {
227 val = readl(regs + S3C64XX_SPI_STATUS);
228 if (RX_FIFO_LVL(val, sdd))
229 readl(regs + S3C64XX_SPI_RX_DATA);
230 else
231 break;
232 } while (loops--);
233
234 if (loops == 0)
235 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
236
237 val = readl(regs + S3C64XX_SPI_CH_CFG);
238 val &= ~S3C64XX_SPI_CH_SW_RST;
239 writel(val, regs + S3C64XX_SPI_CH_CFG);
240
241 val = readl(regs + S3C64XX_SPI_MODE_CFG);
242 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
243 writel(val, regs + S3C64XX_SPI_MODE_CFG);
244}
245
246static void s3c64xx_spi_dmacb(void *data)
247{
248 struct s3c64xx_spi_driver_data *sdd;
249 struct s3c64xx_spi_dma_data *dma = data;
250 unsigned long flags;
251
252 if (dma->direction == DMA_DEV_TO_MEM)
253 sdd = container_of(data,
254 struct s3c64xx_spi_driver_data, rx_dma);
255 else
256 sdd = container_of(data,
257 struct s3c64xx_spi_driver_data, tx_dma);
258
259 spin_lock_irqsave(&sdd->lock, flags);
260
261 if (dma->direction == DMA_DEV_TO_MEM) {
262 sdd->state &= ~RXBUSY;
263 if (!(sdd->state & TXBUSY))
264 complete(&sdd->xfer_completion);
265 } else {
266 sdd->state &= ~TXBUSY;
267 if (!(sdd->state & RXBUSY))
268 complete(&sdd->xfer_completion);
269 }
270
271 spin_unlock_irqrestore(&sdd->lock, flags);
272}
273
274static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
275 struct sg_table *sgt)
276{
277 struct s3c64xx_spi_driver_data *sdd;
278 struct dma_slave_config config;
279 struct dma_async_tx_descriptor *desc;
280
281 memset(&config, 0, sizeof(config));
282
283 if (dma->direction == DMA_DEV_TO_MEM) {
284 sdd = container_of((void *)dma,
285 struct s3c64xx_spi_driver_data, rx_dma);
286 config.direction = dma->direction;
287 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
288 config.src_addr_width = sdd->cur_bpw / 8;
289 config.src_maxburst = 1;
290 dmaengine_slave_config(dma->ch, &config);
291 } else {
292 sdd = container_of((void *)dma,
293 struct s3c64xx_spi_driver_data, tx_dma);
294 config.direction = dma->direction;
295 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
296 config.dst_addr_width = sdd->cur_bpw / 8;
297 config.dst_maxburst = 1;
298 dmaengine_slave_config(dma->ch, &config);
299 }
300
301 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
302 dma->direction, DMA_PREP_INTERRUPT);
303
304 desc->callback = s3c64xx_spi_dmacb;
305 desc->callback_param = dma;
306
307 dmaengine_submit(desc);
308 dma_async_issue_pending(dma->ch);
309}
310
311static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
312{
313 struct s3c64xx_spi_driver_data *sdd =
314 spi_master_get_devdata(spi->master);
315
316 if (sdd->cntrlr_info->no_cs)
317 return;
318
319 if (enable) {
320 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
321 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
322 } else {
323 u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
324
325 ssel |= (S3C64XX_SPI_SLAVE_AUTO |
326 S3C64XX_SPI_SLAVE_NSC_CNT_2);
327 writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
328 }
329 } else {
330 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
331 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
332 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
333 }
334}
335
336static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
337{
338 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
339
340 if (is_polling(sdd))
341 return 0;
342
343 spi->dma_rx = sdd->rx_dma.ch;
344 spi->dma_tx = sdd->tx_dma.ch;
345
346 return 0;
347}
348
349static bool s3c64xx_spi_can_dma(struct spi_master *master,
350 struct spi_device *spi,
351 struct spi_transfer *xfer)
352{
353 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
354
355 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
356}
357
358static void s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
359 struct spi_transfer *xfer, int dma_mode)
360{
361 void __iomem *regs = sdd->regs;
362 u32 modecfg, chcfg;
363
364 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
365 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
366
367 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
368 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
369
370 if (dma_mode) {
371 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
372 } else {
373 /* Always shift in data in FIFO, even if xfer is Tx only,
374 * this helps setting PCKT_CNT value for generating clocks
375 * as exactly needed.
376 */
377 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
378 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
379 | S3C64XX_SPI_PACKET_CNT_EN,
380 regs + S3C64XX_SPI_PACKET_CNT);
381 }
382
383 if (xfer->tx_buf != NULL) {
384 sdd->state |= TXBUSY;
385 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
386 if (dma_mode) {
387 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
388 prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
389 } else {
390 switch (sdd->cur_bpw) {
391 case 32:
392 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
393 xfer->tx_buf, xfer->len / 4);
394 break;
395 case 16:
396 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
397 xfer->tx_buf, xfer->len / 2);
398 break;
399 default:
400 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
401 xfer->tx_buf, xfer->len);
402 break;
403 }
404 }
405 }
406
407 if (xfer->rx_buf != NULL) {
408 sdd->state |= RXBUSY;
409
410 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
411 && !(sdd->cur_mode & SPI_CPHA))
412 chcfg |= S3C64XX_SPI_CH_HS_EN;
413
414 if (dma_mode) {
415 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
416 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
417 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
418 | S3C64XX_SPI_PACKET_CNT_EN,
419 regs + S3C64XX_SPI_PACKET_CNT);
420 prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
421 }
422 }
423
424 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
425 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
426}
427
428static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
429 int timeout_ms)
430{
431 void __iomem *regs = sdd->regs;
432 unsigned long val = 1;
433 u32 status;
434
435 /* max fifo depth available */
436 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
437
438 if (timeout_ms)
439 val = msecs_to_loops(timeout_ms);
440
441 do {
442 status = readl(regs + S3C64XX_SPI_STATUS);
443 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
444
445 /* return the actual received data length */
446 return RX_FIFO_LVL(status, sdd);
447}
448
449static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
450 struct spi_transfer *xfer)
451{
452 void __iomem *regs = sdd->regs;
453 unsigned long val;
454 u32 status;
455 int ms;
456
457 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
458 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
459 ms += 10; /* some tolerance */
460
461 val = msecs_to_jiffies(ms) + 10;
462 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
463
464 /*
465 * If the previous xfer was completed within timeout, then
466 * proceed further else return -EIO.
467 * DmaTx returns after simply writing data in the FIFO,
468 * w/o waiting for real transmission on the bus to finish.
469 * DmaRx returns only after Dma read data from FIFO which
470 * needs bus transmission to finish, so we don't worry if
471 * Xfer involved Rx(with or without Tx).
472 */
473 if (val && !xfer->rx_buf) {
474 val = msecs_to_loops(10);
475 status = readl(regs + S3C64XX_SPI_STATUS);
476 while ((TX_FIFO_LVL(status, sdd)
477 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
478 && --val) {
479 cpu_relax();
480 status = readl(regs + S3C64XX_SPI_STATUS);
481 }
482
483 }
484
485 /* If timed out while checking rx/tx status return error */
486 if (!val)
487 return -EIO;
488
489 return 0;
490}
491
492static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
493 struct spi_transfer *xfer)
494{
495 void __iomem *regs = sdd->regs;
496 unsigned long val;
497 u32 status;
498 int loops;
499 u32 cpy_len;
500 u8 *buf;
501 int ms;
502
503 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
504 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
505 ms += 10; /* some tolerance */
506
507 val = msecs_to_loops(ms);
508 do {
509 status = readl(regs + S3C64XX_SPI_STATUS);
510 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
511
512 if (!val)
513 return -EIO;
514
515 /* If it was only Tx */
516 if (!xfer->rx_buf) {
517 sdd->state &= ~TXBUSY;
518 return 0;
519 }
520
521 /*
522 * If the receive length is bigger than the controller fifo
523 * size, calculate the loops and read the fifo as many times.
524 * loops = length / max fifo size (calculated by using the
525 * fifo mask).
526 * For any size less than the fifo size the below code is
527 * executed atleast once.
528 */
529 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
530 buf = xfer->rx_buf;
531 do {
532 /* wait for data to be received in the fifo */
533 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
534 (loops ? ms : 0));
535
536 switch (sdd->cur_bpw) {
537 case 32:
538 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
539 buf, cpy_len / 4);
540 break;
541 case 16:
542 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
543 buf, cpy_len / 2);
544 break;
545 default:
546 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
547 buf, cpy_len);
548 break;
549 }
550
551 buf = buf + cpy_len;
552 } while (loops--);
553 sdd->state &= ~RXBUSY;
554
555 return 0;
556}
557
558static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
559{
560 void __iomem *regs = sdd->regs;
561 u32 val;
562
563 /* Disable Clock */
564 if (!sdd->port_conf->clk_from_cmu) {
565 val = readl(regs + S3C64XX_SPI_CLK_CFG);
566 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
567 writel(val, regs + S3C64XX_SPI_CLK_CFG);
568 }
569
570 /* Set Polarity and Phase */
571 val = readl(regs + S3C64XX_SPI_CH_CFG);
572 val &= ~(S3C64XX_SPI_CH_SLAVE |
573 S3C64XX_SPI_CPOL_L |
574 S3C64XX_SPI_CPHA_B);
575
576 if (sdd->cur_mode & SPI_CPOL)
577 val |= S3C64XX_SPI_CPOL_L;
578
579 if (sdd->cur_mode & SPI_CPHA)
580 val |= S3C64XX_SPI_CPHA_B;
581
582 writel(val, regs + S3C64XX_SPI_CH_CFG);
583
584 /* Set Channel & DMA Mode */
585 val = readl(regs + S3C64XX_SPI_MODE_CFG);
586 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
587 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
588
589 switch (sdd->cur_bpw) {
590 case 32:
591 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
592 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
593 break;
594 case 16:
595 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
596 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
597 break;
598 default:
599 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
600 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
601 break;
602 }
603
604 writel(val, regs + S3C64XX_SPI_MODE_CFG);
605
606 if (sdd->port_conf->clk_from_cmu) {
607 /* The src_clk clock is divided internally by 2 */
608 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
609 } else {
610 /* Configure Clock */
611 val = readl(regs + S3C64XX_SPI_CLK_CFG);
612 val &= ~S3C64XX_SPI_PSR_MASK;
613 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
614 & S3C64XX_SPI_PSR_MASK);
615 writel(val, regs + S3C64XX_SPI_CLK_CFG);
616
617 /* Enable Clock */
618 val = readl(regs + S3C64XX_SPI_CLK_CFG);
619 val |= S3C64XX_SPI_ENCLK_ENABLE;
620 writel(val, regs + S3C64XX_SPI_CLK_CFG);
621 }
622}
623
624#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
625
626static int s3c64xx_spi_prepare_message(struct spi_master *master,
627 struct spi_message *msg)
628{
629 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
630 struct spi_device *spi = msg->spi;
631 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
632
633 /* Configure feedback delay */
634 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
635
636 return 0;
637}
638
639static int s3c64xx_spi_transfer_one(struct spi_master *master,
640 struct spi_device *spi,
641 struct spi_transfer *xfer)
642{
643 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
644 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
645 const void *tx_buf = NULL;
646 void *rx_buf = NULL;
647 int target_len = 0, origin_len = 0;
648 int use_dma = 0;
649 int status;
650 u32 speed;
651 u8 bpw;
652 unsigned long flags;
653
654 reinit_completion(&sdd->xfer_completion);
655
656 /* Only BPW and Speed may change across transfers */
657 bpw = xfer->bits_per_word;
658 speed = xfer->speed_hz;
659
660 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
661 sdd->cur_bpw = bpw;
662 sdd->cur_speed = speed;
663 sdd->cur_mode = spi->mode;
664 s3c64xx_spi_config(sdd);
665 }
666
667 if (!is_polling(sdd) && (xfer->len > fifo_len) &&
668 sdd->rx_dma.ch && sdd->tx_dma.ch) {
669 use_dma = 1;
670
671 } else if (is_polling(sdd) && xfer->len > fifo_len) {
672 tx_buf = xfer->tx_buf;
673 rx_buf = xfer->rx_buf;
674 origin_len = xfer->len;
675
676 target_len = xfer->len;
677 if (xfer->len > fifo_len)
678 xfer->len = fifo_len;
679 }
680
681 do {
682 spin_lock_irqsave(&sdd->lock, flags);
683
684 /* Pending only which is to be done */
685 sdd->state &= ~RXBUSY;
686 sdd->state &= ~TXBUSY;
687
688 s3c64xx_enable_datapath(sdd, xfer, use_dma);
689
690 /* Start the signals */
691 s3c64xx_spi_set_cs(spi, true);
692
693 spin_unlock_irqrestore(&sdd->lock, flags);
694
695 if (use_dma)
696 status = s3c64xx_wait_for_dma(sdd, xfer);
697 else
698 status = s3c64xx_wait_for_pio(sdd, xfer);
699
700 if (status) {
701 dev_err(&spi->dev,
702 "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
703 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
704 (sdd->state & RXBUSY) ? 'f' : 'p',
705 (sdd->state & TXBUSY) ? 'f' : 'p',
706 xfer->len);
707
708 if (use_dma) {
709 if (xfer->tx_buf && (sdd->state & TXBUSY))
710 dmaengine_terminate_all(sdd->tx_dma.ch);
711 if (xfer->rx_buf && (sdd->state & RXBUSY))
712 dmaengine_terminate_all(sdd->rx_dma.ch);
713 }
714 } else {
715 s3c64xx_flush_fifo(sdd);
716 }
717 if (target_len > 0) {
718 target_len -= xfer->len;
719
720 if (xfer->tx_buf)
721 xfer->tx_buf += xfer->len;
722
723 if (xfer->rx_buf)
724 xfer->rx_buf += xfer->len;
725
726 if (target_len > fifo_len)
727 xfer->len = fifo_len;
728 else
729 xfer->len = target_len;
730 }
731 } while (target_len > 0);
732
733 if (origin_len) {
734 /* Restore original xfer buffers and length */
735 xfer->tx_buf = tx_buf;
736 xfer->rx_buf = rx_buf;
737 xfer->len = origin_len;
738 }
739
740 return status;
741}
742
743static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
744 struct spi_device *spi)
745{
746 struct s3c64xx_spi_csinfo *cs;
747 struct device_node *slave_np, *data_np = NULL;
748 u32 fb_delay = 0;
749
750 slave_np = spi->dev.of_node;
751 if (!slave_np) {
752 dev_err(&spi->dev, "device node not found\n");
753 return ERR_PTR(-EINVAL);
754 }
755
756 data_np = of_get_child_by_name(slave_np, "controller-data");
757 if (!data_np) {
758 dev_err(&spi->dev, "child node 'controller-data' not found\n");
759 return ERR_PTR(-EINVAL);
760 }
761
762 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
763 if (!cs) {
764 of_node_put(data_np);
765 return ERR_PTR(-ENOMEM);
766 }
767
768 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
769 cs->fb_delay = fb_delay;
770 of_node_put(data_np);
771 return cs;
772}
773
774/*
775 * Here we only check the validity of requested configuration
776 * and save the configuration in a local data-structure.
777 * The controller is actually configured only just before we
778 * get a message to transfer.
779 */
780static int s3c64xx_spi_setup(struct spi_device *spi)
781{
782 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
783 struct s3c64xx_spi_driver_data *sdd;
784 int err;
785
786 sdd = spi_master_get_devdata(spi->master);
787 if (spi->dev.of_node) {
788 cs = s3c64xx_get_slave_ctrldata(spi);
789 spi->controller_data = cs;
790 } else if (cs) {
791 /* On non-DT platforms the SPI core will set spi->cs_gpio
792 * to -ENOENT. The GPIO pin used to drive the chip select
793 * is defined by using platform data so spi->cs_gpio value
794 * has to be override to have the proper GPIO pin number.
795 */
796 spi->cs_gpio = cs->line;
797 }
798
799 if (IS_ERR_OR_NULL(cs)) {
800 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
801 return -ENODEV;
802 }
803
804 if (!spi_get_ctldata(spi)) {
805 if (gpio_is_valid(spi->cs_gpio)) {
806 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
807 dev_name(&spi->dev));
808 if (err) {
809 dev_err(&spi->dev,
810 "Failed to get /CS gpio [%d]: %d\n",
811 spi->cs_gpio, err);
812 goto err_gpio_req;
813 }
814 }
815
816 spi_set_ctldata(spi, cs);
817 }
818
819 pm_runtime_get_sync(&sdd->pdev->dev);
820
821 /* Check if we can provide the requested rate */
822 if (!sdd->port_conf->clk_from_cmu) {
823 u32 psr, speed;
824
825 /* Max possible */
826 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
827
828 if (spi->max_speed_hz > speed)
829 spi->max_speed_hz = speed;
830
831 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
832 psr &= S3C64XX_SPI_PSR_MASK;
833 if (psr == S3C64XX_SPI_PSR_MASK)
834 psr--;
835
836 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
837 if (spi->max_speed_hz < speed) {
838 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
839 psr++;
840 } else {
841 err = -EINVAL;
842 goto setup_exit;
843 }
844 }
845
846 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
847 if (spi->max_speed_hz >= speed) {
848 spi->max_speed_hz = speed;
849 } else {
850 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
851 spi->max_speed_hz);
852 err = -EINVAL;
853 goto setup_exit;
854 }
855 }
856
857 pm_runtime_mark_last_busy(&sdd->pdev->dev);
858 pm_runtime_put_autosuspend(&sdd->pdev->dev);
859 s3c64xx_spi_set_cs(spi, false);
860
861 return 0;
862
863setup_exit:
864 pm_runtime_mark_last_busy(&sdd->pdev->dev);
865 pm_runtime_put_autosuspend(&sdd->pdev->dev);
866 /* setup() returns with device de-selected */
867 s3c64xx_spi_set_cs(spi, false);
868
869 if (gpio_is_valid(spi->cs_gpio))
870 gpio_free(spi->cs_gpio);
871 spi_set_ctldata(spi, NULL);
872
873err_gpio_req:
874 if (spi->dev.of_node)
875 kfree(cs);
876
877 return err;
878}
879
880static void s3c64xx_spi_cleanup(struct spi_device *spi)
881{
882 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
883
884 if (gpio_is_valid(spi->cs_gpio)) {
885 gpio_free(spi->cs_gpio);
886 if (spi->dev.of_node)
887 kfree(cs);
888 else {
889 /* On non-DT platforms, the SPI core sets
890 * spi->cs_gpio to -ENOENT and .setup()
891 * overrides it with the GPIO pin value
892 * passed using platform data.
893 */
894 spi->cs_gpio = -ENOENT;
895 }
896 }
897
898 spi_set_ctldata(spi, NULL);
899}
900
901static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
902{
903 struct s3c64xx_spi_driver_data *sdd = data;
904 struct spi_master *spi = sdd->master;
905 unsigned int val, clr = 0;
906
907 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
908
909 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
910 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
911 dev_err(&spi->dev, "RX overrun\n");
912 }
913 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
914 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
915 dev_err(&spi->dev, "RX underrun\n");
916 }
917 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
918 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
919 dev_err(&spi->dev, "TX overrun\n");
920 }
921 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
922 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
923 dev_err(&spi->dev, "TX underrun\n");
924 }
925
926 /* Clear the pending irq by setting and then clearing it */
927 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
928 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
929
930 return IRQ_HANDLED;
931}
932
933static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
934{
935 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
936 void __iomem *regs = sdd->regs;
937 unsigned int val;
938
939 sdd->cur_speed = 0;
940
941 if (sci->no_cs)
942 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
943 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
944 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
945
946 /* Disable Interrupts - we use Polling if not DMA mode */
947 writel(0, regs + S3C64XX_SPI_INT_EN);
948
949 if (!sdd->port_conf->clk_from_cmu)
950 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
951 regs + S3C64XX_SPI_CLK_CFG);
952 writel(0, regs + S3C64XX_SPI_MODE_CFG);
953 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
954
955 /* Clear any irq pending bits, should set and clear the bits */
956 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
957 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
958 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
959 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
960 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
961 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
962
963 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
964
965 val = readl(regs + S3C64XX_SPI_MODE_CFG);
966 val &= ~S3C64XX_SPI_MODE_4BURST;
967 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
968 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
969 writel(val, regs + S3C64XX_SPI_MODE_CFG);
970
971 s3c64xx_flush_fifo(sdd);
972}
973
974#ifdef CONFIG_OF
975static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
976{
977 struct s3c64xx_spi_info *sci;
978 u32 temp;
979
980 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
981 if (!sci)
982 return ERR_PTR(-ENOMEM);
983
984 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
985 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
986 sci->src_clk_nr = 0;
987 } else {
988 sci->src_clk_nr = temp;
989 }
990
991 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
992 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
993 sci->num_cs = 1;
994 } else {
995 sci->num_cs = temp;
996 }
997
998 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
999
1000 return sci;
1001}
1002#else
1003static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1004{
1005 return dev_get_platdata(dev);
1006}
1007#endif
1008
1009static const struct of_device_id s3c64xx_spi_dt_match[];
1010
1011static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1012 struct platform_device *pdev)
1013{
1014#ifdef CONFIG_OF
1015 if (pdev->dev.of_node) {
1016 const struct of_device_id *match;
1017 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1018 return (struct s3c64xx_spi_port_config *)match->data;
1019 }
1020#endif
1021 return (struct s3c64xx_spi_port_config *)
1022 platform_get_device_id(pdev)->driver_data;
1023}
1024
1025static int s3c64xx_spi_probe(struct platform_device *pdev)
1026{
1027 struct resource *mem_res;
1028 struct s3c64xx_spi_driver_data *sdd;
1029 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1030 struct spi_master *master;
1031 int ret, irq;
1032 char clk_name[16];
1033
1034 if (!sci && pdev->dev.of_node) {
1035 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1036 if (IS_ERR(sci))
1037 return PTR_ERR(sci);
1038 }
1039
1040 if (!sci) {
1041 dev_err(&pdev->dev, "platform_data missing!\n");
1042 return -ENODEV;
1043 }
1044
1045 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046 if (mem_res == NULL) {
1047 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1048 return -ENXIO;
1049 }
1050
1051 irq = platform_get_irq(pdev, 0);
1052 if (irq < 0) {
1053 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1054 return irq;
1055 }
1056
1057 master = spi_alloc_master(&pdev->dev,
1058 sizeof(struct s3c64xx_spi_driver_data));
1059 if (master == NULL) {
1060 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1061 return -ENOMEM;
1062 }
1063
1064 platform_set_drvdata(pdev, master);
1065
1066 sdd = spi_master_get_devdata(master);
1067 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1068 sdd->master = master;
1069 sdd->cntrlr_info = sci;
1070 sdd->pdev = pdev;
1071 sdd->sfr_start = mem_res->start;
1072 if (pdev->dev.of_node) {
1073 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1074 if (ret < 0) {
1075 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1076 ret);
1077 goto err_deref_master;
1078 }
1079 sdd->port_id = ret;
1080 } else {
1081 sdd->port_id = pdev->id;
1082 }
1083
1084 sdd->cur_bpw = 8;
1085
1086 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1087 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1088
1089 master->dev.of_node = pdev->dev.of_node;
1090 master->bus_num = sdd->port_id;
1091 master->setup = s3c64xx_spi_setup;
1092 master->cleanup = s3c64xx_spi_cleanup;
1093 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1094 master->prepare_message = s3c64xx_spi_prepare_message;
1095 master->transfer_one = s3c64xx_spi_transfer_one;
1096 master->num_chipselect = sci->num_cs;
1097 master->dma_alignment = 8;
1098 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1099 SPI_BPW_MASK(8);
1100 /* the spi->mode bits understood by this driver: */
1101 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1102 master->auto_runtime_pm = true;
1103 if (!is_polling(sdd))
1104 master->can_dma = s3c64xx_spi_can_dma;
1105
1106 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1107 if (IS_ERR(sdd->regs)) {
1108 ret = PTR_ERR(sdd->regs);
1109 goto err_deref_master;
1110 }
1111
1112 if (sci->cfg_gpio && sci->cfg_gpio()) {
1113 dev_err(&pdev->dev, "Unable to config gpio\n");
1114 ret = -EBUSY;
1115 goto err_deref_master;
1116 }
1117
1118 /* Setup clocks */
1119 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1120 if (IS_ERR(sdd->clk)) {
1121 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1122 ret = PTR_ERR(sdd->clk);
1123 goto err_deref_master;
1124 }
1125
1126 ret = clk_prepare_enable(sdd->clk);
1127 if (ret) {
1128 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1129 goto err_deref_master;
1130 }
1131
1132 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1133 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1134 if (IS_ERR(sdd->src_clk)) {
1135 dev_err(&pdev->dev,
1136 "Unable to acquire clock '%s'\n", clk_name);
1137 ret = PTR_ERR(sdd->src_clk);
1138 goto err_disable_clk;
1139 }
1140
1141 ret = clk_prepare_enable(sdd->src_clk);
1142 if (ret) {
1143 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1144 goto err_disable_clk;
1145 }
1146
1147 if (sdd->port_conf->clk_ioclk) {
1148 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1149 if (IS_ERR(sdd->ioclk)) {
1150 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1151 ret = PTR_ERR(sdd->ioclk);
1152 goto err_disable_src_clk;
1153 }
1154
1155 ret = clk_prepare_enable(sdd->ioclk);
1156 if (ret) {
1157 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1158 goto err_disable_src_clk;
1159 }
1160 }
1161
1162 if (!is_polling(sdd)) {
1163 /* Acquire DMA channels */
1164 sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx");
1165 if (IS_ERR(sdd->rx_dma.ch)) {
1166 dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1167 ret = PTR_ERR(sdd->rx_dma.ch);
1168 goto err_disable_io_clk;
1169 }
1170 sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx");
1171 if (IS_ERR(sdd->tx_dma.ch)) {
1172 dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1173 ret = PTR_ERR(sdd->tx_dma.ch);
1174 goto err_release_rx_dma;
1175 }
1176 }
1177
1178 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1179 pm_runtime_use_autosuspend(&pdev->dev);
1180 pm_runtime_set_active(&pdev->dev);
1181 pm_runtime_enable(&pdev->dev);
1182 pm_runtime_get_sync(&pdev->dev);
1183
1184 /* Setup Deufult Mode */
1185 s3c64xx_spi_hwinit(sdd);
1186
1187 spin_lock_init(&sdd->lock);
1188 init_completion(&sdd->xfer_completion);
1189
1190 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1191 "spi-s3c64xx", sdd);
1192 if (ret != 0) {
1193 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1194 irq, ret);
1195 goto err_pm_put;
1196 }
1197
1198 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1199 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1200 sdd->regs + S3C64XX_SPI_INT_EN);
1201
1202 ret = devm_spi_register_master(&pdev->dev, master);
1203 if (ret != 0) {
1204 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1205 goto err_pm_put;
1206 }
1207
1208 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1209 sdd->port_id, master->num_chipselect);
1210 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1211 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1212
1213 pm_runtime_mark_last_busy(&pdev->dev);
1214 pm_runtime_put_autosuspend(&pdev->dev);
1215
1216 return 0;
1217
1218err_pm_put:
1219 pm_runtime_put_noidle(&pdev->dev);
1220 pm_runtime_disable(&pdev->dev);
1221 pm_runtime_set_suspended(&pdev->dev);
1222
1223 if (!is_polling(sdd))
1224 dma_release_channel(sdd->tx_dma.ch);
1225err_release_rx_dma:
1226 if (!is_polling(sdd))
1227 dma_release_channel(sdd->rx_dma.ch);
1228err_disable_io_clk:
1229 clk_disable_unprepare(sdd->ioclk);
1230err_disable_src_clk:
1231 clk_disable_unprepare(sdd->src_clk);
1232err_disable_clk:
1233 clk_disable_unprepare(sdd->clk);
1234err_deref_master:
1235 spi_master_put(master);
1236
1237 return ret;
1238}
1239
1240static int s3c64xx_spi_remove(struct platform_device *pdev)
1241{
1242 struct spi_master *master = platform_get_drvdata(pdev);
1243 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1244
1245 pm_runtime_get_sync(&pdev->dev);
1246
1247 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1248
1249 if (!is_polling(sdd)) {
1250 dma_release_channel(sdd->rx_dma.ch);
1251 dma_release_channel(sdd->tx_dma.ch);
1252 }
1253
1254 clk_disable_unprepare(sdd->ioclk);
1255
1256 clk_disable_unprepare(sdd->src_clk);
1257
1258 clk_disable_unprepare(sdd->clk);
1259
1260 pm_runtime_put_noidle(&pdev->dev);
1261 pm_runtime_disable(&pdev->dev);
1262 pm_runtime_set_suspended(&pdev->dev);
1263
1264 return 0;
1265}
1266
1267#ifdef CONFIG_PM_SLEEP
1268static int s3c64xx_spi_suspend(struct device *dev)
1269{
1270 struct spi_master *master = dev_get_drvdata(dev);
1271 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1272
1273 int ret = spi_master_suspend(master);
1274 if (ret)
1275 return ret;
1276
1277 ret = pm_runtime_force_suspend(dev);
1278 if (ret < 0)
1279 return ret;
1280
1281 sdd->cur_speed = 0; /* Output Clock is stopped */
1282
1283 return 0;
1284}
1285
1286static int s3c64xx_spi_resume(struct device *dev)
1287{
1288 struct spi_master *master = dev_get_drvdata(dev);
1289 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1290 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1291 int ret;
1292
1293 if (sci->cfg_gpio)
1294 sci->cfg_gpio();
1295
1296 ret = pm_runtime_force_resume(dev);
1297 if (ret < 0)
1298 return ret;
1299
1300 return spi_master_resume(master);
1301}
1302#endif /* CONFIG_PM_SLEEP */
1303
1304#ifdef CONFIG_PM
1305static int s3c64xx_spi_runtime_suspend(struct device *dev)
1306{
1307 struct spi_master *master = dev_get_drvdata(dev);
1308 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1309
1310 clk_disable_unprepare(sdd->clk);
1311 clk_disable_unprepare(sdd->src_clk);
1312 clk_disable_unprepare(sdd->ioclk);
1313
1314 return 0;
1315}
1316
1317static int s3c64xx_spi_runtime_resume(struct device *dev)
1318{
1319 struct spi_master *master = dev_get_drvdata(dev);
1320 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1321 int ret;
1322
1323 if (sdd->port_conf->clk_ioclk) {
1324 ret = clk_prepare_enable(sdd->ioclk);
1325 if (ret != 0)
1326 return ret;
1327 }
1328
1329 ret = clk_prepare_enable(sdd->src_clk);
1330 if (ret != 0)
1331 goto err_disable_ioclk;
1332
1333 ret = clk_prepare_enable(sdd->clk);
1334 if (ret != 0)
1335 goto err_disable_src_clk;
1336
1337 s3c64xx_spi_hwinit(sdd);
1338
1339 return 0;
1340
1341err_disable_src_clk:
1342 clk_disable_unprepare(sdd->src_clk);
1343err_disable_ioclk:
1344 clk_disable_unprepare(sdd->ioclk);
1345
1346 return ret;
1347}
1348#endif /* CONFIG_PM */
1349
1350static const struct dev_pm_ops s3c64xx_spi_pm = {
1351 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1352 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1353 s3c64xx_spi_runtime_resume, NULL)
1354};
1355
1356static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1357 .fifo_lvl_mask = { 0x7f },
1358 .rx_lvl_offset = 13,
1359 .tx_st_done = 21,
1360 .high_speed = true,
1361};
1362
1363static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1364 .fifo_lvl_mask = { 0x7f, 0x7F },
1365 .rx_lvl_offset = 13,
1366 .tx_st_done = 21,
1367};
1368
1369static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1370 .fifo_lvl_mask = { 0x1ff, 0x7F },
1371 .rx_lvl_offset = 15,
1372 .tx_st_done = 25,
1373 .high_speed = true,
1374};
1375
1376static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1377 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1378 .rx_lvl_offset = 15,
1379 .tx_st_done = 25,
1380 .high_speed = true,
1381 .clk_from_cmu = true,
1382};
1383
1384static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1385 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1386 .rx_lvl_offset = 15,
1387 .tx_st_done = 25,
1388 .high_speed = true,
1389 .clk_from_cmu = true,
1390 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1391};
1392
1393static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1394 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1395 .rx_lvl_offset = 15,
1396 .tx_st_done = 25,
1397 .high_speed = true,
1398 .clk_from_cmu = true,
1399 .clk_ioclk = true,
1400 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1401};
1402
1403static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1404 {
1405 .name = "s3c2443-spi",
1406 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1407 }, {
1408 .name = "s3c6410-spi",
1409 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1410 },
1411 { },
1412};
1413
1414static const struct of_device_id s3c64xx_spi_dt_match[] = {
1415 { .compatible = "samsung,s3c2443-spi",
1416 .data = (void *)&s3c2443_spi_port_config,
1417 },
1418 { .compatible = "samsung,s3c6410-spi",
1419 .data = (void *)&s3c6410_spi_port_config,
1420 },
1421 { .compatible = "samsung,s5pv210-spi",
1422 .data = (void *)&s5pv210_spi_port_config,
1423 },
1424 { .compatible = "samsung,exynos4210-spi",
1425 .data = (void *)&exynos4_spi_port_config,
1426 },
1427 { .compatible = "samsung,exynos7-spi",
1428 .data = (void *)&exynos7_spi_port_config,
1429 },
1430 { .compatible = "samsung,exynos5433-spi",
1431 .data = (void *)&exynos5433_spi_port_config,
1432 },
1433 { },
1434};
1435MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1436
1437static struct platform_driver s3c64xx_spi_driver = {
1438 .driver = {
1439 .name = "s3c64xx-spi",
1440 .pm = &s3c64xx_spi_pm,
1441 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1442 },
1443 .probe = s3c64xx_spi_probe,
1444 .remove = s3c64xx_spi_remove,
1445 .id_table = s3c64xx_spi_driver_ids,
1446};
1447MODULE_ALIAS("platform:s3c64xx-spi");
1448
1449module_platform_driver(s3c64xx_spi_driver);
1450
1451MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1452MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1453MODULE_LICENSE("GPL");