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v6.2
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * OpenRISC setup.c
  4 *
  5 * Linux architectural port borrowing liberally from similar works of
  6 * others.  All original copyrights apply as per the original source
  7 * declaration.
  8 *
  9 * Modifications for the OpenRISC architecture:
 10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
 11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
 12 *
 13 * This file handles the architecture-dependent parts of initialization
 14 */
 15
 16#include <linux/errno.h>
 17#include <linux/sched.h>
 18#include <linux/kernel.h>
 19#include <linux/mm.h>
 20#include <linux/stddef.h>
 21#include <linux/unistd.h>
 22#include <linux/ptrace.h>
 23#include <linux/slab.h>
 24#include <linux/tty.h>
 25#include <linux/ioport.h>
 26#include <linux/delay.h>
 27#include <linux/console.h>
 28#include <linux/init.h>
 29#include <linux/memblock.h>
 30#include <linux/seq_file.h>
 31#include <linux/serial.h>
 32#include <linux/initrd.h>
 33#include <linux/of_fdt.h>
 34#include <linux/of.h>
 35#include <linux/device.h>
 36
 37#include <asm/sections.h>
 38#include <asm/types.h>
 39#include <asm/setup.h>
 40#include <asm/io.h>
 41#include <asm/cpuinfo.h>
 42#include <asm/delay.h>
 43
 44#include "vmlinux.h"
 45
 46static void __init setup_memory(void)
 47{
 48	unsigned long ram_start_pfn;
 49	unsigned long ram_end_pfn;
 50	phys_addr_t memory_start, memory_end;
 
 51
 52	memory_end = memory_start = 0;
 53
 54	/* Find main memory where is the kernel, we assume its the only one */
 55	memory_start = memblock_start_of_DRAM();
 56	memory_end = memblock_end_of_DRAM();
 
 
 
 
 57
 58	if (!memory_end) {
 59		panic("No memory!");
 60	}
 61
 62	ram_start_pfn = PFN_UP(memory_start);
 63	ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM());
 64
 65	/* setup bootmem globals (we use no_bootmem, but mm still depends on this) */
 66	min_low_pfn = ram_start_pfn;
 67	max_low_pfn = ram_end_pfn;
 68	max_pfn = ram_end_pfn;
 69
 70	/*
 71	 * initialize the boot-time allocator (with low memory only).
 72	 *
 73	 * This makes the memory from the end of the kernel to the end of
 74	 * RAM usable.
 75	 */
 76	memblock_reserve(__pa(_stext), _end - _stext);
 77
 78#ifdef CONFIG_BLK_DEV_INITRD
 79	/* Then reserve the initrd, if any */
 80	if (initrd_start && (initrd_end > initrd_start)) {
 81		unsigned long aligned_start = ALIGN_DOWN(initrd_start, PAGE_SIZE);
 82		unsigned long aligned_end = ALIGN(initrd_end, PAGE_SIZE);
 83
 84		memblock_reserve(__pa(aligned_start), aligned_end - aligned_start);
 85	}
 86#endif /* CONFIG_BLK_DEV_INITRD */
 87
 88	early_init_fdt_reserve_self();
 89	early_init_fdt_scan_reserved_mem();
 90
 91	memblock_dump_all();
 92}
 93
 94struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
 95
 96static void print_cpuinfo(void)
 97{
 98	unsigned long upr = mfspr(SPR_UPR);
 99	unsigned long vr = mfspr(SPR_VR);
100	unsigned int version;
101	unsigned int revision;
102	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
103
104	version = (vr & SPR_VR_VER) >> 24;
105	revision = (vr & SPR_VR_REV);
106
107	printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n",
108	       version, revision, cpuinfo->clock_frequency / 1000000);
109
110	if (!(upr & SPR_UPR_UP)) {
111		printk(KERN_INFO
112		       "-- no UPR register... unable to detect configuration\n");
113		return;
114	}
115
116	if (upr & SPR_UPR_DCP)
117		printk(KERN_INFO
118		       "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
119		       cpuinfo->dcache_size, cpuinfo->dcache_block_size,
120		       cpuinfo->dcache_ways);
121	else
122		printk(KERN_INFO "-- dcache disabled\n");
123	if (upr & SPR_UPR_ICP)
124		printk(KERN_INFO
125		       "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
126		       cpuinfo->icache_size, cpuinfo->icache_block_size,
127		       cpuinfo->icache_ways);
128	else
129		printk(KERN_INFO "-- icache disabled\n");
130
131	if (upr & SPR_UPR_DMP)
132		printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
133		       1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
134		       1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
135	if (upr & SPR_UPR_IMP)
136		printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n",
137		       1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
138		       1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
139
140	printk(KERN_INFO "-- additional features:\n");
141	if (upr & SPR_UPR_DUP)
142		printk(KERN_INFO "-- debug unit\n");
143	if (upr & SPR_UPR_PCUP)
144		printk(KERN_INFO "-- performance counters\n");
145	if (upr & SPR_UPR_PMP)
146		printk(KERN_INFO "-- power management\n");
147	if (upr & SPR_UPR_PICP)
148		printk(KERN_INFO "-- PIC\n");
149	if (upr & SPR_UPR_TTP)
150		printk(KERN_INFO "-- timer\n");
151	if (upr & SPR_UPR_CUP)
152		printk(KERN_INFO "-- custom unit(s)\n");
153}
154
155static struct device_node *setup_find_cpu_node(int cpu)
156{
157	u32 hwid;
158	struct device_node *cpun;
159
160	for_each_of_cpu_node(cpun) {
161		if (of_property_read_u32(cpun, "reg", &hwid))
162			continue;
163		if (hwid == cpu)
164			return cpun;
165	}
166
167	return NULL;
168}
169
170void __init setup_cpuinfo(void)
171{
172	struct device_node *cpu;
173	unsigned long iccfgr, dccfgr;
174	unsigned long cache_set_size;
175	int cpu_id = smp_processor_id();
176	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
177
178	cpu = setup_find_cpu_node(cpu_id);
179	if (!cpu)
180		panic("Couldn't find CPU%d in device tree...\n", cpu_id);
181
182	iccfgr = mfspr(SPR_ICCFGR);
183	cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
184	cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
185	cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
186	cpuinfo->icache_size =
187	    cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
188
189	dccfgr = mfspr(SPR_DCCFGR);
190	cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
191	cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
192	cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
193	cpuinfo->dcache_size =
194	    cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
195
196	if (of_property_read_u32(cpu, "clock-frequency",
197				 &cpuinfo->clock_frequency)) {
198		printk(KERN_WARNING
199		       "Device tree missing CPU 'clock-frequency' parameter."
200		       "Assuming frequency 25MHZ"
201		       "This is probably not what you want.");
202	}
203
204	cpuinfo->coreid = mfspr(SPR_COREID);
205
206	of_node_put(cpu);
207
208	print_cpuinfo();
209}
210
211/**
212 * or1k_early_setup
213 * @fdt: pointer to the start of the device tree in memory or NULL
214 *
215 * Handles the pointer to the device tree that this kernel is to use
216 * for establishing the available platform devices.
217 *
218 * Falls back on built-in device tree in case null pointer is passed.
219 */
220
221void __init or1k_early_setup(void *fdt)
222{
223	if (fdt)
224		pr_info("FDT at %p\n", fdt);
225	else {
226		fdt = __dtb_start;
227		pr_info("Compiled-in FDT at %p\n", fdt);
228	}
229	early_init_devtree(fdt);
230}
231
232static inline unsigned long extract_value_bits(unsigned long reg,
233					       short bit_nr, short width)
234{
235	return (reg >> bit_nr) & (0 << width);
236}
237
238static inline unsigned long extract_value(unsigned long reg, unsigned long mask)
239{
240	while (!(mask & 0x1)) {
241		reg = reg >> 1;
242		mask = mask >> 1;
243	}
244	return mask & reg;
245}
246
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
247/*
248 * calibrate_delay
249 *
250 * Lightweight calibrate_delay implementation that calculates loops_per_jiffy
251 * from the clock frequency passed in via the device tree
252 *
253 */
254
255void calibrate_delay(void)
256{
257	const int *val;
258	struct device_node *cpu = setup_find_cpu_node(smp_processor_id());
259
260	val = of_get_property(cpu, "clock-frequency", NULL);
261	if (!val)
262		panic("no cpu 'clock-frequency' parameter in device tree");
263	loops_per_jiffy = *val / HZ;
264	pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
265		loops_per_jiffy / (500000 / HZ),
266		(loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
267
268	of_node_put(cpu);
269}
270
271void __init setup_arch(char **cmdline_p)
272{
273	unflatten_and_copy_device_tree();
274
275	setup_cpuinfo();
276
277#ifdef CONFIG_SMP
278	smp_init_cpus();
279#endif
280
281	/* process 1's initial memory region is the kernel code/data */
282	setup_initial_init_mm(_stext, _etext, _edata, _end);
 
 
 
283
284#ifdef CONFIG_BLK_DEV_INITRD
285	if (initrd_start == initrd_end) {
286		printk(KERN_INFO "Initial ramdisk not found\n");
287		initrd_start = 0;
288		initrd_end = 0;
289	} else {
290		printk(KERN_INFO "Initial ramdisk at: 0x%p (%lu bytes)\n",
291		       (void *)(initrd_start), initrd_end - initrd_start);
292		initrd_below_start_ok = 1;
293	}
294#endif
295
296	/* setup memblock allocator */
297	setup_memory();
298
299	/* paging_init() sets up the MMU and marks all pages as reserved */
300	paging_init();
301
302	*cmdline_p = boot_command_line;
303
304	printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
305}
306
307static int show_cpuinfo(struct seq_file *m, void *v)
308{
309	unsigned int vr, cpucfgr;
310	unsigned int avr;
311	unsigned int version;
312	struct cpuinfo_or1k *cpuinfo = v;
313
314	vr = mfspr(SPR_VR);
315	cpucfgr = mfspr(SPR_CPUCFGR);
316
317#ifdef CONFIG_SMP
318	seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
319#endif
320	if (vr & SPR_VR_UVRP) {
321		vr = mfspr(SPR_VR2);
322		version = vr & SPR_VR2_VER;
323		avr = mfspr(SPR_AVR);
324		seq_printf(m, "cpu architecture\t: "
325			   "OpenRISC 1000 (%d.%d-rev%d)\n",
326			   (avr >> 24) & 0xff,
327			   (avr >> 16) & 0xff,
328			   (avr >> 8) & 0xff);
329		seq_printf(m, "cpu implementation id\t: 0x%x\n",
330			   (vr & SPR_VR2_CPUID) >> 24);
331		seq_printf(m, "cpu version\t\t: 0x%x\n", version);
332	} else {
333		version = (vr & SPR_VR_VER) >> 24;
334		seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version);
335		seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
336	}
337	seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
338	seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
339	seq_printf(m, "dcache block size\t: %d bytes\n",
340		   cpuinfo->dcache_block_size);
341	seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
342	seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
343	seq_printf(m, "icache block size\t: %d bytes\n",
344		   cpuinfo->icache_block_size);
345	seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
346	seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
347		   1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
348		   1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
349	seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n",
350		   1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
351		   1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
352	seq_printf(m, "bogomips\t\t: %lu.%02lu\n",
353		   (loops_per_jiffy * HZ) / 500000,
354		   ((loops_per_jiffy * HZ) / 5000) % 100);
355
356	seq_puts(m, "features\t\t: ");
357	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : "");
358	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : "");
359	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : "");
360	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : "");
361	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : "");
362	seq_puts(m, "\n");
363
364	seq_puts(m, "\n");
365
366	return 0;
367}
368
369static void *c_start(struct seq_file *m, loff_t *pos)
370{
371	*pos = cpumask_next(*pos - 1, cpu_online_mask);
372	if ((*pos) < nr_cpu_ids)
373		return &cpuinfo_or1k[*pos];
374	return NULL;
375}
376
377static void *c_next(struct seq_file *m, void *v, loff_t *pos)
378{
379	(*pos)++;
380	return c_start(m, pos);
381}
382
383static void c_stop(struct seq_file *m, void *v)
384{
385}
386
387const struct seq_operations cpuinfo_op = {
388	.start = c_start,
389	.next = c_next,
390	.stop = c_stop,
391	.show = show_cpuinfo,
392};
v5.9
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * OpenRISC setup.c
  4 *
  5 * Linux architectural port borrowing liberally from similar works of
  6 * others.  All original copyrights apply as per the original source
  7 * declaration.
  8 *
  9 * Modifications for the OpenRISC architecture:
 10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
 11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
 12 *
 13 * This file handles the architecture-dependent parts of initialization
 14 */
 15
 16#include <linux/errno.h>
 17#include <linux/sched.h>
 18#include <linux/kernel.h>
 19#include <linux/mm.h>
 20#include <linux/stddef.h>
 21#include <linux/unistd.h>
 22#include <linux/ptrace.h>
 23#include <linux/slab.h>
 24#include <linux/tty.h>
 25#include <linux/ioport.h>
 26#include <linux/delay.h>
 27#include <linux/console.h>
 28#include <linux/init.h>
 29#include <linux/memblock.h>
 30#include <linux/seq_file.h>
 31#include <linux/serial.h>
 32#include <linux/initrd.h>
 33#include <linux/of_fdt.h>
 34#include <linux/of.h>
 35#include <linux/device.h>
 36
 37#include <asm/sections.h>
 38#include <asm/types.h>
 39#include <asm/setup.h>
 40#include <asm/io.h>
 41#include <asm/cpuinfo.h>
 42#include <asm/delay.h>
 43
 44#include "vmlinux.h"
 45
 46static void __init setup_memory(void)
 47{
 48	unsigned long ram_start_pfn;
 49	unsigned long ram_end_pfn;
 50	phys_addr_t memory_start, memory_end;
 51	struct memblock_region *region;
 52
 53	memory_end = memory_start = 0;
 54
 55	/* Find main memory where is the kernel, we assume its the only one */
 56	for_each_memblock(memory, region) {
 57		memory_start = region->base;
 58		memory_end = region->base + region->size;
 59		printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__,
 60		       memory_start, memory_end);
 61	}
 62
 63	if (!memory_end) {
 64		panic("No memory!");
 65	}
 66
 67	ram_start_pfn = PFN_UP(memory_start);
 68	ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM());
 69
 70	/* setup bootmem globals (we use no_bootmem, but mm still depends on this) */
 71	min_low_pfn = ram_start_pfn;
 72	max_low_pfn = ram_end_pfn;
 73	max_pfn = ram_end_pfn;
 74
 75	/*
 76	 * initialize the boot-time allocator (with low memory only).
 77	 *
 78	 * This makes the memory from the end of the kernel to the end of
 79	 * RAM usable.
 80	 */
 81	memblock_reserve(__pa(_stext), _end - _stext);
 82
 83#ifdef CONFIG_BLK_DEV_INITRD
 84	/* Then reserve the initrd, if any */
 85	if (initrd_start && (initrd_end > initrd_start)) {
 86		unsigned long aligned_start = ALIGN_DOWN(initrd_start, PAGE_SIZE);
 87		unsigned long aligned_end = ALIGN(initrd_end, PAGE_SIZE);
 88
 89		memblock_reserve(__pa(aligned_start), aligned_end - aligned_start);
 90	}
 91#endif /* CONFIG_BLK_DEV_INITRD */
 92
 93	early_init_fdt_reserve_self();
 94	early_init_fdt_scan_reserved_mem();
 95
 96	memblock_dump_all();
 97}
 98
 99struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
100
101static void print_cpuinfo(void)
102{
103	unsigned long upr = mfspr(SPR_UPR);
104	unsigned long vr = mfspr(SPR_VR);
105	unsigned int version;
106	unsigned int revision;
107	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
108
109	version = (vr & SPR_VR_VER) >> 24;
110	revision = (vr & SPR_VR_REV);
111
112	printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n",
113	       version, revision, cpuinfo->clock_frequency / 1000000);
114
115	if (!(upr & SPR_UPR_UP)) {
116		printk(KERN_INFO
117		       "-- no UPR register... unable to detect configuration\n");
118		return;
119	}
120
121	if (upr & SPR_UPR_DCP)
122		printk(KERN_INFO
123		       "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
124		       cpuinfo->dcache_size, cpuinfo->dcache_block_size,
125		       cpuinfo->dcache_ways);
126	else
127		printk(KERN_INFO "-- dcache disabled\n");
128	if (upr & SPR_UPR_ICP)
129		printk(KERN_INFO
130		       "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
131		       cpuinfo->icache_size, cpuinfo->icache_block_size,
132		       cpuinfo->icache_ways);
133	else
134		printk(KERN_INFO "-- icache disabled\n");
135
136	if (upr & SPR_UPR_DMP)
137		printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
138		       1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
139		       1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
140	if (upr & SPR_UPR_IMP)
141		printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n",
142		       1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
143		       1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
144
145	printk(KERN_INFO "-- additional features:\n");
146	if (upr & SPR_UPR_DUP)
147		printk(KERN_INFO "-- debug unit\n");
148	if (upr & SPR_UPR_PCUP)
149		printk(KERN_INFO "-- performance counters\n");
150	if (upr & SPR_UPR_PMP)
151		printk(KERN_INFO "-- power management\n");
152	if (upr & SPR_UPR_PICP)
153		printk(KERN_INFO "-- PIC\n");
154	if (upr & SPR_UPR_TTP)
155		printk(KERN_INFO "-- timer\n");
156	if (upr & SPR_UPR_CUP)
157		printk(KERN_INFO "-- custom unit(s)\n");
158}
159
160static struct device_node *setup_find_cpu_node(int cpu)
161{
162	u32 hwid;
163	struct device_node *cpun;
164
165	for_each_of_cpu_node(cpun) {
166		if (of_property_read_u32(cpun, "reg", &hwid))
167			continue;
168		if (hwid == cpu)
169			return cpun;
170	}
171
172	return NULL;
173}
174
175void __init setup_cpuinfo(void)
176{
177	struct device_node *cpu;
178	unsigned long iccfgr, dccfgr;
179	unsigned long cache_set_size;
180	int cpu_id = smp_processor_id();
181	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
182
183	cpu = setup_find_cpu_node(cpu_id);
184	if (!cpu)
185		panic("Couldn't find CPU%d in device tree...\n", cpu_id);
186
187	iccfgr = mfspr(SPR_ICCFGR);
188	cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
189	cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
190	cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
191	cpuinfo->icache_size =
192	    cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
193
194	dccfgr = mfspr(SPR_DCCFGR);
195	cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
196	cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
197	cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
198	cpuinfo->dcache_size =
199	    cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
200
201	if (of_property_read_u32(cpu, "clock-frequency",
202				 &cpuinfo->clock_frequency)) {
203		printk(KERN_WARNING
204		       "Device tree missing CPU 'clock-frequency' parameter."
205		       "Assuming frequency 25MHZ"
206		       "This is probably not what you want.");
207	}
208
209	cpuinfo->coreid = mfspr(SPR_COREID);
210
211	of_node_put(cpu);
212
213	print_cpuinfo();
214}
215
216/**
217 * or32_early_setup
 
218 *
219 * Handles the pointer to the device tree that this kernel is to use
220 * for establishing the available platform devices.
221 *
222 * Falls back on built-in device tree in case null pointer is passed.
223 */
224
225void __init or32_early_setup(void *fdt)
226{
227	if (fdt)
228		pr_info("FDT at %p\n", fdt);
229	else {
230		fdt = __dtb_start;
231		pr_info("Compiled-in FDT at %p\n", fdt);
232	}
233	early_init_devtree(fdt);
234}
235
236static inline unsigned long extract_value_bits(unsigned long reg,
237					       short bit_nr, short width)
238{
239	return (reg >> bit_nr) & (0 << width);
240}
241
242static inline unsigned long extract_value(unsigned long reg, unsigned long mask)
243{
244	while (!(mask & 0x1)) {
245		reg = reg >> 1;
246		mask = mask >> 1;
247	}
248	return mask & reg;
249}
250
251void __init detect_unit_config(unsigned long upr, unsigned long mask,
252			       char *text, void (*func) (void))
253{
254	if (text != NULL)
255		printk("%s", text);
256
257	if (upr & mask) {
258		if (func != NULL)
259			func();
260		else
261			printk("present\n");
262	} else
263		printk("not present\n");
264}
265
266/*
267 * calibrate_delay
268 *
269 * Lightweight calibrate_delay implementation that calculates loops_per_jiffy
270 * from the clock frequency passed in via the device tree
271 *
272 */
273
274void calibrate_delay(void)
275{
276	const int *val;
277	struct device_node *cpu = setup_find_cpu_node(smp_processor_id());
278
279	val = of_get_property(cpu, "clock-frequency", NULL);
280	if (!val)
281		panic("no cpu 'clock-frequency' parameter in device tree");
282	loops_per_jiffy = *val / HZ;
283	pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
284		loops_per_jiffy / (500000 / HZ),
285		(loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
 
 
286}
287
288void __init setup_arch(char **cmdline_p)
289{
290	unflatten_and_copy_device_tree();
291
292	setup_cpuinfo();
293
294#ifdef CONFIG_SMP
295	smp_init_cpus();
296#endif
297
298	/* process 1's initial memory region is the kernel code/data */
299	init_mm.start_code = (unsigned long)_stext;
300	init_mm.end_code = (unsigned long)_etext;
301	init_mm.end_data = (unsigned long)_edata;
302	init_mm.brk = (unsigned long)_end;
303
304#ifdef CONFIG_BLK_DEV_INITRD
305	if (initrd_start == initrd_end) {
306		printk(KERN_INFO "Initial ramdisk not found\n");
307		initrd_start = 0;
308		initrd_end = 0;
309	} else {
310		printk(KERN_INFO "Initial ramdisk at: 0x%p (%lu bytes)\n",
311		       (void *)(initrd_start), initrd_end - initrd_start);
312		initrd_below_start_ok = 1;
313	}
314#endif
315
316	/* setup memblock allocator */
317	setup_memory();
318
319	/* paging_init() sets up the MMU and marks all pages as reserved */
320	paging_init();
321
322	*cmdline_p = boot_command_line;
323
324	printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
325}
326
327static int show_cpuinfo(struct seq_file *m, void *v)
328{
329	unsigned int vr, cpucfgr;
330	unsigned int avr;
331	unsigned int version;
332	struct cpuinfo_or1k *cpuinfo = v;
333
334	vr = mfspr(SPR_VR);
335	cpucfgr = mfspr(SPR_CPUCFGR);
336
337#ifdef CONFIG_SMP
338	seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
339#endif
340	if (vr & SPR_VR_UVRP) {
341		vr = mfspr(SPR_VR2);
342		version = vr & SPR_VR2_VER;
343		avr = mfspr(SPR_AVR);
344		seq_printf(m, "cpu architecture\t: "
345			   "OpenRISC 1000 (%d.%d-rev%d)\n",
346			   (avr >> 24) & 0xff,
347			   (avr >> 16) & 0xff,
348			   (avr >> 8) & 0xff);
349		seq_printf(m, "cpu implementation id\t: 0x%x\n",
350			   (vr & SPR_VR2_CPUID) >> 24);
351		seq_printf(m, "cpu version\t\t: 0x%x\n", version);
352	} else {
353		version = (vr & SPR_VR_VER) >> 24;
354		seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version);
355		seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
356	}
357	seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
358	seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
359	seq_printf(m, "dcache block size\t: %d bytes\n",
360		   cpuinfo->dcache_block_size);
361	seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
362	seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
363	seq_printf(m, "icache block size\t: %d bytes\n",
364		   cpuinfo->icache_block_size);
365	seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
366	seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
367		   1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
368		   1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
369	seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n",
370		   1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
371		   1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
372	seq_printf(m, "bogomips\t\t: %lu.%02lu\n",
373		   (loops_per_jiffy * HZ) / 500000,
374		   ((loops_per_jiffy * HZ) / 5000) % 100);
375
376	seq_puts(m, "features\t\t: ");
377	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : "");
378	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : "");
379	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : "");
380	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : "");
381	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : "");
382	seq_puts(m, "\n");
383
384	seq_puts(m, "\n");
385
386	return 0;
387}
388
389static void *c_start(struct seq_file *m, loff_t *pos)
390{
391	*pos = cpumask_next(*pos - 1, cpu_online_mask);
392	if ((*pos) < nr_cpu_ids)
393		return &cpuinfo_or1k[*pos];
394	return NULL;
395}
396
397static void *c_next(struct seq_file *m, void *v, loff_t *pos)
398{
399	(*pos)++;
400	return c_start(m, pos);
401}
402
403static void c_stop(struct seq_file *m, void *v)
404{
405}
406
407const struct seq_operations cpuinfo_op = {
408	.start = c_start,
409	.next = c_next,
410	.stop = c_stop,
411	.show = show_cpuinfo,
412};