1/*
   2 * Copyright 2012-14 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef DC_INTERFACE_H_
  27#define DC_INTERFACE_H_
  28
  29#include "dc_types.h"
  30#include "grph_object_defs.h"
  31#include "logger_types.h"
  32#if defined(CONFIG_DRM_AMD_DC_HDCP)
  33#include "hdcp_types.h"
  34#endif
  35#include "gpio_types.h"
  36#include "link_service_types.h"
  37#include "grph_object_ctrl_defs.h"
  38#include <inc/hw/opp.h>
  39
  40#include "inc/hw_sequencer.h"
  41#include "inc/compressor.h"
  42#include "inc/hw/dmcu.h"
  43#include "dml/display_mode_lib.h"
  44
  45/* forward declaration */
  46struct aux_payload;
  47struct set_config_cmd_payload;
  48struct dmub_notification;
  49
  50#define DC_VER "3.2.215"
  51
  52#define MAX_SURFACES 3
  53#define MAX_PLANES 6
  54#define MAX_STREAMS 6
  55#define MAX_SINKS_PER_LINK 4
  56#define MIN_VIEWPORT_SIZE 12
  57#define MAX_NUM_EDP 2
  58
  59/* Display Core Interfaces */
 
 
  60struct dc_versions {
  61	const char *dc_ver;
  62	struct dmcu_version dmcu_version;
  63};
  64
  65enum dp_protocol_version {
  66	DP_VERSION_1_4,
  67};
  68
  69enum dc_plane_type {
  70	DC_PLANE_TYPE_INVALID,
  71	DC_PLANE_TYPE_DCE_RGB,
  72	DC_PLANE_TYPE_DCE_UNDERLAY,
  73	DC_PLANE_TYPE_DCN_UNIVERSAL,
  74};
  75
  76// Sizes defined as multiples of 64KB
  77enum det_size {
  78	DET_SIZE_DEFAULT = 0,
  79	DET_SIZE_192KB = 3,
  80	DET_SIZE_256KB = 4,
  81	DET_SIZE_320KB = 5,
  82	DET_SIZE_384KB = 6
  83};
  84
  85
  86struct dc_plane_cap {
  87	enum dc_plane_type type;
  88	uint32_t blends_with_above : 1;
  89	uint32_t blends_with_below : 1;
  90	uint32_t per_pixel_alpha : 1;
  91	struct {
  92		uint32_t argb8888 : 1;
  93		uint32_t nv12 : 1;
  94		uint32_t fp16 : 1;
  95		uint32_t p010 : 1;
  96		uint32_t ayuv : 1;
  97	} pixel_format_support;
  98	// max upscaling factor x1000
  99	// upscaling factors are always >= 1
 100	// for example, 1080p -> 8K is 4.0, or 4000 raw value
 101	struct {
 102		uint32_t argb8888;
 103		uint32_t nv12;
 104		uint32_t fp16;
 105	} max_upscale_factor;
 106	// max downscale factor x1000
 107	// downscale factors are always <= 1
 108	// for example, 8K -> 1080p is 0.25, or 250 raw value
 109	struct {
 110		uint32_t argb8888;
 111		uint32_t nv12;
 112		uint32_t fp16;
 113	} max_downscale_factor;
 114	// minimal width/height
 115	uint32_t min_width;
 116	uint32_t min_height;
 117};
 118
 119/**
 120 * DOC: color-management-caps
 121 *
 122 * **Color management caps (DPP and MPC)**
 123 *
 124 * Modules/color calculates various color operations which are translated to
 125 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
 126 * DCN1, every new generation comes with fairly major differences in color
 127 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
 128 * decide mapping to HW block based on logical capabilities.
 129 */
 130
 131/**
 132 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
 133 * @srgb: RGB color space transfer func
 134 * @bt2020: BT.2020 transfer func
 135 * @gamma2_2: standard gamma
 136 * @pq: perceptual quantizer transfer function
 137 * @hlg: hybrid log–gamma transfer function
 138 */
 139struct rom_curve_caps {
 140	uint16_t srgb : 1;
 141	uint16_t bt2020 : 1;
 142	uint16_t gamma2_2 : 1;
 143	uint16_t pq : 1;
 144	uint16_t hlg : 1;
 145};
 146
 147/**
 148 * struct dpp_color_caps - color pipeline capabilities for display pipe and
 149 * plane blocks
 150 *
 151 * @dcn_arch: all DCE generations treated the same
 152 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
 153 * just plain 256-entry lookup
 154 * @icsc: input color space conversion
 155 * @dgam_ram: programmable degamma LUT
 156 * @post_csc: post color space conversion, before gamut remap
 157 * @gamma_corr: degamma correction
 158 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
 159 * with MPC by setting mpc:shared_3d_lut flag
 160 * @ogam_ram: programmable out/blend gamma LUT
 161 * @ocsc: output color space conversion
 162 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
 163 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
 164 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
 165 *
 166 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
 167 */
 168struct dpp_color_caps {
 169	uint16_t dcn_arch : 1;
 170	uint16_t input_lut_shared : 1;
 
 171	uint16_t icsc : 1;
 172	uint16_t dgam_ram : 1;
 173	uint16_t post_csc : 1;
 174	uint16_t gamma_corr : 1;
 
 
 
 
 175	uint16_t hw_3d_lut : 1;
 176	uint16_t ogam_ram : 1;
 177	uint16_t ocsc : 1;
 178	uint16_t dgam_rom_for_yuv : 1;
 179	struct rom_curve_caps dgam_rom_caps;
 180	struct rom_curve_caps ogam_rom_caps;
 181};
 182
 183/**
 184 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
 185 * plane combined blocks
 186 *
 187 * @gamut_remap: color transformation matrix
 188 * @ogam_ram: programmable out gamma LUT
 189 * @ocsc: output color space conversion matrix
 190 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
 191 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
 192 * instance
 193 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
 194 */
 195struct mpc_color_caps {
 196	uint16_t gamut_remap : 1;
 197	uint16_t ogam_ram : 1;
 198	uint16_t ocsc : 1;
 199	uint16_t num_3dluts : 3;
 200	uint16_t shared_3d_lut:1;
 
 201	struct rom_curve_caps ogam_rom_caps;
 202};
 203
 204/**
 205 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
 206 * @dpp: color pipes caps for DPP
 207 * @mpc: color pipes caps for MPC
 208 */
 209struct dc_color_caps {
 210	struct dpp_color_caps dpp;
 211	struct mpc_color_caps mpc;
 212};
 213
 214struct dc_dmub_caps {
 215	bool psr;
 216	bool mclk_sw;
 217};
 218
 219struct dc_caps {
 220	uint32_t max_streams;
 221	uint32_t max_links;
 222	uint32_t max_audios;
 223	uint32_t max_slave_planes;
 224	uint32_t max_slave_yuv_planes;
 225	uint32_t max_slave_rgb_planes;
 226	uint32_t max_planes;
 227	uint32_t max_downscale_ratio;
 228	uint32_t i2c_speed_in_khz;
 229	uint32_t i2c_speed_in_khz_hdcp;
 230	uint32_t dmdata_alloc_size;
 231	unsigned int max_cursor_size;
 232	unsigned int max_video_width;
 233	unsigned int min_horizontal_blanking_period;
 234	int linear_pitch_alignment;
 235	bool dcc_const_color;
 236	bool dynamic_audio;
 237	bool is_apu;
 238	bool dual_link_dvi;
 239	bool post_blend_color_processing;
 240	bool force_dp_tps4_for_cp2520;
 241	bool disable_dp_clk_share;
 242	bool psp_setup_panel_mode;
 243	bool extended_aux_timeout_support;
 244	bool dmcub_support;
 245	bool zstate_support;
 246	uint32_t num_of_internal_disp;
 247	enum dp_protocol_version max_dp_protocol_version;
 248	unsigned int mall_size_per_mem_channel;
 249	unsigned int mall_size_total;
 250	unsigned int cursor_cache_size;
 251	struct dc_plane_cap planes[MAX_PLANES];
 252	struct dc_color_caps color;
 253	struct dc_dmub_caps dmub_caps;
 254	bool dp_hpo;
 255	bool dp_hdmi21_pcon_support;
 256	bool edp_dsc_support;
 257	bool vbios_lttpr_aware;
 258	bool vbios_lttpr_enable;
 259	uint32_t max_otg_num;
 260	uint32_t max_cab_allocation_bytes;
 261	uint32_t cache_line_size;
 262	uint32_t cache_num_ways;
 263	uint16_t subvp_fw_processing_delay_us;
 264	uint8_t subvp_drr_max_vblank_margin_us;
 265	uint16_t subvp_prefetch_end_to_mall_start_us;
 266	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
 267	uint16_t subvp_pstate_allow_width_us;
 268	uint16_t subvp_vertical_int_margin_us;
 269	bool seamless_odm;
 270	uint8_t subvp_drr_vblank_start_margin_us;
 271};
 272
 273struct dc_bug_wa {
 274	bool no_connect_phy_config;
 275	bool dedcn20_305_wa;
 276	bool skip_clock_update;
 277	bool lt_early_cr_pattern;
 278};
 279
 280struct dc_dcc_surface_param {
 281	struct dc_size surface_size;
 282	enum surface_pixel_format format;
 283	enum swizzle_mode_values swizzle_mode;
 284	enum dc_scan_direction scan;
 285};
 286
 287struct dc_dcc_setting {
 288	unsigned int max_compressed_blk_size;
 289	unsigned int max_uncompressed_blk_size;
 290	bool independent_64b_blks;
 291	//These bitfields to be used starting with DCN
 
 292	struct {
 293		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
 294		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN
 295		uint32_t dcc_256_128_128 : 1;		//available starting with DCN
 296		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN (the best compression case)
 297	} dcc_controls;
 
 298};
 299
 300struct dc_surface_dcc_cap {
 301	union {
 302		struct {
 303			struct dc_dcc_setting rgb;
 304		} grph;
 305
 306		struct {
 307			struct dc_dcc_setting luma;
 308			struct dc_dcc_setting chroma;
 309		} video;
 310	};
 311
 312	bool capable;
 313	bool const_color_support;
 314};
 315
 316struct dc_static_screen_params {
 317	struct {
 318		bool force_trigger;
 319		bool cursor_update;
 320		bool surface_update;
 321		bool overlay_update;
 322	} triggers;
 323	unsigned int num_frames;
 324};
 325
 326
 327/* Surface update type is used by dc_update_surfaces_and_stream
 328 * The update type is determined at the very beginning of the function based
 329 * on parameters passed in and decides how much programming (or updating) is
 330 * going to be done during the call.
 331 *
 332 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 333 * logical calculations or hardware register programming. This update MUST be
 334 * ISR safe on windows. Currently fast update will only be used to flip surface
 335 * address.
 336 *
 337 * UPDATE_TYPE_MED is used for slower updates which require significant hw
 338 * re-programming however do not affect bandwidth consumption or clock
 339 * requirements. At present, this is the level at which front end updates
 340 * that do not require us to run bw_calcs happen. These are in/out transfer func
 341 * updates, viewport offset changes, recout size changes and pixel depth changes.
 342 * This update can be done at ISR, but we want to minimize how often this happens.
 343 *
 344 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 345 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 346 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 347 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 348 * a full update. This cannot be done at ISR level and should be a rare event.
 349 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 350 * underscan we don't expect to see this call at all.
 351 */
 352
 353enum surface_update_type {
 354	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
 355	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
 356	UPDATE_TYPE_FULL, /* may need to shuffle resources */
 357};
 358
 359/* Forward declaration*/
 360struct dc;
 361struct dc_plane_state;
 362struct dc_state;
 363
 364
 365struct dc_cap_funcs {
 366	bool (*get_dcc_compression_cap)(const struct dc *dc,
 367			const struct dc_dcc_surface_param *input,
 368			struct dc_surface_dcc_cap *output);
 369};
 370
 371struct link_training_settings;
 372
 373union allow_lttpr_non_transparent_mode {
 374	struct {
 375		bool DP1_4A : 1;
 376		bool DP2_0 : 1;
 377	} bits;
 378	unsigned char raw;
 379};
 380
 381/* Structure to hold configuration flags set by dm at dc creation. */
 382struct dc_config {
 383	bool gpu_vm_support;
 384	bool disable_disp_pll_sharing;
 385	bool fbc_support;
 
 386	bool disable_fractional_pwm;
 387	bool allow_seamless_boot_optimization;
 388	bool seamless_boot_edp_requested;
 389	bool edp_not_connected;
 390	bool edp_no_power_sequencing;
 391	bool force_enum_edp;
 392	bool forced_clocks;
 393	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
 394	bool multi_mon_pp_mclk_switch;
 395	bool disable_dmcu;
 396	bool enable_4to1MPC;
 397	bool enable_windowed_mpo_odm;
 398	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
 399	uint32_t allow_edp_hotplug_detection;
 400	bool clamp_min_dcfclk;
 401	uint64_t vblank_alignment_dto_params;
 402	uint8_t  vblank_alignment_max_frame_time_diff;
 403	bool is_asymmetric_memory;
 404	bool is_single_rank_dimm;
 405	bool is_vmin_only_asic;
 406	bool use_pipe_ctx_sync_logic;
 407	bool ignore_dpref_ss;
 408	bool enable_mipi_converter_optimization;
 409	bool use_default_clock_table;
 410	bool force_bios_enable_lttpr;
 411	uint8_t force_bios_fixed_vs;
 412	int sdpif_request_limit_words_per_umc;
 413
 414};
 415
 416enum visual_confirm {
 417	VISUAL_CONFIRM_DISABLE = 0,
 418	VISUAL_CONFIRM_SURFACE = 1,
 419	VISUAL_CONFIRM_HDR = 2,
 420	VISUAL_CONFIRM_MPCTREE = 4,
 421	VISUAL_CONFIRM_PSR = 5,
 422	VISUAL_CONFIRM_SWAPCHAIN = 6,
 423	VISUAL_CONFIRM_FAMS = 7,
 424	VISUAL_CONFIRM_SWIZZLE = 9,
 425	VISUAL_CONFIRM_SUBVP = 14,
 426};
 427
 428enum dc_psr_power_opts {
 429	psr_power_opt_invalid = 0x0,
 430	psr_power_opt_smu_opt_static_screen = 0x1,
 431	psr_power_opt_z10_static_screen = 0x10,
 432	psr_power_opt_ds_disable_allow = 0x100,
 433};
 434
 435enum dml_hostvm_override_opts {
 436	DML_HOSTVM_NO_OVERRIDE = 0x0,
 437	DML_HOSTVM_OVERRIDE_FALSE = 0x1,
 438	DML_HOSTVM_OVERRIDE_TRUE = 0x2,
 439};
 440
 441enum dcc_option {
 442	DCC_ENABLE = 0,
 443	DCC_DISABLE = 1,
 444	DCC_HALF_REQ_DISALBE = 2,
 445};
 446
 447/**
 448 * enum pipe_split_policy - Pipe split strategy supported by DCN
 449 *
 450 * This enum is used to define the pipe split policy supported by DCN. By
 451 * default, DC favors MPC_SPLIT_DYNAMIC.
 452 */
 453enum pipe_split_policy {
 454	/**
 455	 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
 456	 * pipe in order to bring the best trade-off between performance and
 457	 * power consumption. This is the recommended option.
 458	 */
 459	MPC_SPLIT_DYNAMIC = 0,
 460
 461	/**
 462	 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
 463	 * try any sort of split optimization.
 464	 */
 465	MPC_SPLIT_AVOID = 1,
 466
 467	/**
 468	 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
 469	 * optimize the pipe utilization when using a single display; if the
 470	 * user connects to a second display, DC will avoid pipe split.
 471	 */
 472	MPC_SPLIT_AVOID_MULT_DISP = 2,
 473};
 474
 475enum wm_report_mode {
 476	WM_REPORT_DEFAULT = 0,
 477	WM_REPORT_OVERRIDE = 1,
 478};
 479enum dtm_pstate{
 480	dtm_level_p0 = 0,/*highest voltage*/
 481	dtm_level_p1,
 482	dtm_level_p2,
 483	dtm_level_p3,
 484	dtm_level_p4,/*when active_display_count = 0*/
 485};
 486
 487enum dcn_pwr_state {
 488	DCN_PWR_STATE_UNKNOWN = -1,
 489	DCN_PWR_STATE_MISSION_MODE = 0,
 490	DCN_PWR_STATE_LOW_POWER = 3,
 491};
 492
 493enum dcn_zstate_support_state {
 494	DCN_ZSTATE_SUPPORT_UNKNOWN,
 495	DCN_ZSTATE_SUPPORT_ALLOW,
 496	DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
 497	DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
 498	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
 499	DCN_ZSTATE_SUPPORT_DISALLOW,
 500};
 501
 502/**
 503 * struct dc_clocks - DC pipe clocks
 504 *
 505 * For any clocks that may differ per pipe only the max is stored in this
 506 * structure
 507 */
 508struct dc_clocks {
 509	int dispclk_khz;
 510	int actual_dispclk_khz;
 511	int dppclk_khz;
 512	int actual_dppclk_khz;
 513	int disp_dpp_voltage_level_khz;
 514	int dcfclk_khz;
 515	int socclk_khz;
 516	int dcfclk_deep_sleep_khz;
 517	int fclk_khz;
 518	int phyclk_khz;
 519	int dramclk_khz;
 520	bool p_state_change_support;
 521	enum dcn_zstate_support_state zstate_support;
 522	bool dtbclk_en;
 523	int ref_dtbclk_khz;
 524	bool fclk_p_state_change_support;
 525	enum dcn_pwr_state pwr_state;
 526	/*
 527	 * Elements below are not compared for the purposes of
 528	 * optimization required
 529	 */
 530	bool prev_p_state_change_support;
 531	bool fclk_prev_p_state_change_support;
 532	int num_ways;
 533
 534	/*
 535	 * @fw_based_mclk_switching
 536	 *
 537	 * DC has a mechanism that leverage the variable refresh rate to switch
 538	 * memory clock in cases that we have a large latency to achieve the
 539	 * memory clock change and a short vblank window. DC has some
 540	 * requirements to enable this feature, and this field describes if the
 541	 * system support or not such a feature.
 542	 */
 543	bool fw_based_mclk_switching;
 544	bool fw_based_mclk_switching_shut_down;
 545	int prev_num_ways;
 546	enum dtm_pstate dtm_level;
 547	int max_supported_dppclk_khz;
 548	int max_supported_dispclk_khz;
 549	int bw_dppclk_khz; /*a copy of dppclk_khz*/
 550	int bw_dispclk_khz;
 551};
 552
 553struct dc_bw_validation_profile {
 554	bool enable;
 555
 556	unsigned long long total_ticks;
 557	unsigned long long voltage_level_ticks;
 558	unsigned long long watermark_ticks;
 559	unsigned long long rq_dlg_ticks;
 560
 561	unsigned long long total_count;
 562	unsigned long long skip_fast_count;
 563	unsigned long long skip_pass_count;
 564	unsigned long long skip_fail_count;
 565};
 566
 567#define BW_VAL_TRACE_SETUP() \
 568		unsigned long long end_tick = 0; \
 569		unsigned long long voltage_level_tick = 0; \
 570		unsigned long long watermark_tick = 0; \
 571		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
 572				dm_get_timestamp(dc->ctx) : 0
 573
 574#define BW_VAL_TRACE_COUNT() \
 575		if (dc->debug.bw_val_profile.enable) \
 576			dc->debug.bw_val_profile.total_count++
 577
 578#define BW_VAL_TRACE_SKIP(status) \
 579		if (dc->debug.bw_val_profile.enable) { \
 580			if (!voltage_level_tick) \
 581				voltage_level_tick = dm_get_timestamp(dc->ctx); \
 582			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
 583		}
 584
 585#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
 586		if (dc->debug.bw_val_profile.enable) \
 587			voltage_level_tick = dm_get_timestamp(dc->ctx)
 588
 589#define BW_VAL_TRACE_END_WATERMARKS() \
 590		if (dc->debug.bw_val_profile.enable) \
 591			watermark_tick = dm_get_timestamp(dc->ctx)
 592
 593#define BW_VAL_TRACE_FINISH() \
 594		if (dc->debug.bw_val_profile.enable) { \
 595			end_tick = dm_get_timestamp(dc->ctx); \
 596			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
 597			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
 598			if (watermark_tick) { \
 599				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
 600				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
 601			} \
 602		}
 603
 604union mem_low_power_enable_options {
 605	struct {
 606		bool vga: 1;
 607		bool i2c: 1;
 608		bool dmcu: 1;
 609		bool dscl: 1;
 610		bool cm: 1;
 611		bool mpc: 1;
 612		bool optc: 1;
 613		bool vpg: 1;
 614		bool afmt: 1;
 615	} bits;
 616	uint32_t u32All;
 617};
 618
 619union root_clock_optimization_options {
 620	struct {
 621		bool dpp: 1;
 622		bool dsc: 1;
 623		bool hdmistream: 1;
 624		bool hdmichar: 1;
 625		bool dpstream: 1;
 626		bool symclk32_se: 1;
 627		bool symclk32_le: 1;
 628		bool symclk_fe: 1;
 629		bool physymclk: 1;
 630		bool dpiasymclk: 1;
 631		uint32_t reserved: 22;
 632	} bits;
 633	uint32_t u32All;
 634};
 635
 636union dpia_debug_options {
 637	struct {
 638		uint32_t disable_dpia:1; /* bit 0 */
 639		uint32_t force_non_lttpr:1; /* bit 1 */
 640		uint32_t extend_aux_rd_interval:1; /* bit 2 */
 641		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
 642		uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
 643		uint32_t reserved:27;
 644	} bits;
 645	uint32_t raw;
 646};
 647
 648/* AUX wake work around options
 649 * 0: enable/disable work around
 650 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
 651 * 15-2: reserved
 652 * 31-16: timeout in ms
 653 */
 654union aux_wake_wa_options {
 655	struct {
 656		uint32_t enable_wa : 1;
 657		uint32_t use_default_timeout : 1;
 658		uint32_t rsvd: 14;
 659		uint32_t timeout_ms : 16;
 660	} bits;
 661	uint32_t raw;
 662};
 663
 664struct dc_debug_data {
 665	uint32_t ltFailCount;
 666	uint32_t i2cErrorCount;
 667	uint32_t auxErrorCount;
 668};
 669
 670struct dc_phy_addr_space_config {
 671	struct {
 672		uint64_t start_addr;
 673		uint64_t end_addr;
 674		uint64_t fb_top;
 675		uint64_t fb_offset;
 676		uint64_t fb_base;
 677		uint64_t agp_top;
 678		uint64_t agp_bot;
 679		uint64_t agp_base;
 680	} system_aperture;
 681
 682	struct {
 683		uint64_t page_table_start_addr;
 684		uint64_t page_table_end_addr;
 685		uint64_t page_table_base_addr;
 686		bool base_addr_is_mc_addr;
 687	} gart_config;
 688
 689	bool valid;
 690	bool is_hvm_enabled;
 691	uint64_t page_table_default_page_addr;
 692};
 693
 694struct dc_virtual_addr_space_config {
 695	uint64_t	page_table_base_addr;
 696	uint64_t	page_table_start_addr;
 697	uint64_t	page_table_end_addr;
 698	uint32_t	page_table_block_size_in_bytes;
 699	uint8_t		page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
 700};
 701
 702struct dc_bounding_box_overrides {
 703	int sr_exit_time_ns;
 704	int sr_enter_plus_exit_time_ns;
 705	int urgent_latency_ns;
 706	int percent_of_ideal_drambw;
 707	int dram_clock_change_latency_ns;
 708	int dummy_clock_change_latency_ns;
 709	int fclk_clock_change_latency_ns;
 710	/* This forces a hard min on the DCFCLK we use
 711	 * for DML.  Unlike the debug option for forcing
 712	 * DCFCLK, this override affects watermark calculations
 713	 */
 714	int min_dcfclk_mhz;
 715};
 716
 717struct dc_state;
 718struct resource_pool;
 719struct dce_hwseq;
 720
 721/**
 722 * struct dc_debug_options - DC debug struct
 723 *
 724 * This struct provides a simple mechanism for developers to change some
 725 * configurations, enable/disable features, and activate extra debug options.
 726 * This can be very handy to narrow down whether some specific feature is
 727 * causing an issue or not.
 728 */
 729struct dc_debug_options {
 730	bool native422_support;
 731	bool disable_dsc;
 732	enum visual_confirm visual_confirm;
 733	int visual_confirm_rect_height;
 734
 735	bool sanity_checks;
 736	bool max_disp_clk;
 737	bool surface_trace;
 738	bool timing_trace;
 739	bool clock_trace;
 740	bool validation_trace;
 741	bool bandwidth_calcs_trace;
 742	int max_downscale_src_width;
 743
 744	/* stutter efficiency related */
 745	bool disable_stutter;
 746	bool use_max_lb;
 747	enum dcc_option disable_dcc;
 748
 749	/**
 750	 * @pipe_split_policy: Define which pipe split policy is used by the
 751	 * display core.
 752	 */
 753	enum pipe_split_policy pipe_split_policy;
 754	bool force_single_disp_pipe_split;
 755	bool voltage_align_fclk;
 756	bool disable_min_fclk;
 757
 758	bool disable_dfs_bypass;
 759	bool disable_dpp_power_gate;
 760	bool disable_hubp_power_gate;
 761	bool disable_dsc_power_gate;
 762	int dsc_min_slice_height_override;
 763	int dsc_bpp_increment_div;
 
 764	bool disable_pplib_wm_range;
 765	enum wm_report_mode pplib_wm_report_mode;
 766	unsigned int min_disp_clk_khz;
 767	unsigned int min_dpp_clk_khz;
 768	unsigned int min_dram_clk_khz;
 769	int sr_exit_time_dpm0_ns;
 770	int sr_enter_plus_exit_time_dpm0_ns;
 771	int sr_exit_time_ns;
 772	int sr_enter_plus_exit_time_ns;
 773	int urgent_latency_ns;
 774	uint32_t underflow_assert_delay_us;
 775	int percent_of_ideal_drambw;
 776	int dram_clock_change_latency_ns;
 777	bool optimized_watermark;
 778	int always_scale;
 779	bool disable_pplib_clock_request;
 780	bool disable_clock_gate;
 781	bool disable_mem_low_power;
 782	bool pstate_enabled;
 783	bool disable_dmcu;
 
 784	bool force_abm_enable;
 785	bool disable_stereo_support;
 786	bool vsr_support;
 787	bool performance_trace;
 788	bool az_endpoint_mute_only;
 789	bool always_use_regamma;
 
 790	bool recovery_enabled;
 791	bool avoid_vbios_exec_table;
 792	bool scl_reset_length10;
 793	bool hdmi20_disable;
 794	bool skip_detection_link_training;
 795	uint32_t edid_read_retry_times;
 
 796	unsigned int force_odm_combine; //bit vector based on otg inst
 797	unsigned int seamless_boot_odm_combine;
 798	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
 799	bool disable_z9_mpc;
 800	unsigned int force_fclk_khz;
 801	bool enable_tri_buf;
 802	bool dmub_offload_enabled;
 803	bool dmcub_emulation;
 
 804	bool disable_idle_power_optimizations;
 805	unsigned int mall_size_override;
 806	unsigned int mall_additional_timer_percent;
 807	bool mall_error_as_fatal;
 808	bool dmub_command_table; /* for testing only */
 809	struct dc_bw_validation_profile bw_val_profile;
 810	bool disable_fec;
 811	bool disable_48mhz_pwrdwn;
 812	/* This forces a hard min on the DCFCLK requested to SMU/PP
 813	 * watermarks are not affected.
 814	 */
 815	unsigned int force_min_dcfclk_mhz;
 
 816	int dwb_fi_phase;
 
 817	bool disable_timing_sync;
 818	bool cm_in_bypass;
 819	int force_clock_mode;/*every mode change.*/
 820
 821	bool disable_dram_clock_change_vactive_support;
 822	bool validate_dml_output;
 823	bool enable_dmcub_surface_flip;
 824	bool usbc_combo_phy_reset_wa;
 
 825	bool enable_dram_clock_change_one_display_vactive;
 826	/* TODO - remove once tested */
 827	bool legacy_dp2_lt;
 828	bool set_mst_en_for_sst;
 829	bool disable_uhbr;
 830	bool force_dp2_lt_fallback_method;
 831	bool ignore_cable_id;
 832	union mem_low_power_enable_options enable_mem_low_power;
 833	union root_clock_optimization_options root_clock_optimization;
 834	bool hpo_optimization;
 835	bool force_vblank_alignment;
 836
 837	/* Enable dmub aux for legacy ddc */
 838	bool enable_dmub_aux_for_legacy_ddc;
 839	bool disable_fams;
 840	/* FEC/PSR1 sequence enable delay in 100us */
 841	uint8_t fec_enable_delay_in100us;
 842	bool enable_driver_sequence_debug;
 843	enum det_size crb_alloc_policy;
 844	int crb_alloc_policy_min_disp_count;
 845	bool disable_z10;
 846	bool enable_z9_disable_interface;
 847	bool psr_skip_crtc_disable;
 848	union dpia_debug_options dpia_debug;
 849	bool disable_fixed_vs_aux_timeout_wa;
 850	bool force_disable_subvp;
 851	bool force_subvp_mclk_switch;
 852	bool allow_sw_cursor_fallback;
 853	unsigned int force_subvp_num_ways;
 854	unsigned int force_mall_ss_num_ways;
 855	bool alloc_extra_way_for_cursor;
 856	uint32_t subvp_extra_lines;
 857	bool force_usr_allow;
 858	/* uses value at boot and disables switch */
 859	bool disable_dtb_ref_clk_switch;
 860	uint32_t fixed_vs_aux_delay_config_wa;
 861	bool extended_blank_optimization;
 862	union aux_wake_wa_options aux_wake_wa;
 863	uint32_t mst_start_top_delay;
 864	uint8_t psr_power_use_phy_fsm;
 865	enum dml_hostvm_override_opts dml_hostvm_override;
 866	bool dml_disallow_alternate_prefetch_modes;
 867	bool use_legacy_soc_bb_mechanism;
 868	bool exit_idle_opt_for_cursor_updates;
 869	bool enable_single_display_2to1_odm_policy;
 870	bool enable_double_buffered_dsc_pg_support;
 871	bool enable_dp_dig_pixel_rate_div_policy;
 872	enum lttpr_mode lttpr_mode_override;
 873	unsigned int dsc_delay_factor_wa_x1000;
 874	unsigned int min_prefetch_in_strobe_ns;
 875};
 876
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 877struct gpu_info_soc_bounding_box_v1_0;
 878struct dc {
 879	struct dc_debug_options debug;
 880	struct dc_versions versions;
 881	struct dc_caps caps;
 882	struct dc_cap_funcs cap_funcs;
 883	struct dc_config config;
 
 884	struct dc_bounding_box_overrides bb_overrides;
 885	struct dc_bug_wa work_arounds;
 886	struct dc_context *ctx;
 887	struct dc_phy_addr_space_config vm_pa_config;
 888
 889	uint8_t link_count;
 890	struct dc_link *links[MAX_PIPES * 2];
 891
 892	struct dc_state *current_state;
 893	struct resource_pool *res_pool;
 894
 895	struct clk_mgr *clk_mgr;
 896
 897	/* Display Engine Clock levels */
 898	struct dm_pp_clock_levels sclk_lvls;
 899
 900	/* Inputs into BW and WM calculations. */
 901	struct bw_calcs_dceip *bw_dceip;
 902	struct bw_calcs_vbios *bw_vbios;
 
 903	struct dcn_soc_bounding_box *dcn_soc;
 904	struct dcn_ip_params *dcn_ip;
 905	struct display_mode_lib dml;
 
 906
 907	/* HW functions */
 908	struct hw_sequencer_funcs hwss;
 909	struct dce_hwseq *hwseq;
 910
 911	/* Require to optimize clocks and bandwidth for added/removed planes */
 912	bool optimized_required;
 913	bool wm_optimized_required;
 
 914	bool idle_optimizations_allowed;
 915	bool enable_c20_dtm_b0;
 916
 917	/* Require to maintain clocks and bandwidth for UEFI enabled HW */
 
 918
 919	/* FBC compressor */
 920	struct compressor *fbc_compressor;
 921
 922	struct dc_debug_data debug_data;
 923	struct dpcd_vendor_signature vendor_signature;
 924
 925	const char *build_id;
 926	struct vm_helper *vm_helper;
 927
 928	uint32_t *dcn_reg_offsets;
 929	uint32_t *nbio_reg_offsets;
 930
 931	/* Scratch memory */
 932	struct {
 933		struct {
 934			/*
 935			 * For matching clock_limits table in driver with table
 936			 * from PMFW.
 937			 */
 938			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 939		} update_bw_bounding_box;
 940	} scratch;
 941};
 942
 943enum frame_buffer_mode {
 944	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
 945	FRAME_BUFFER_MODE_ZFB_ONLY,
 946	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
 947} ;
 948
 949struct dchub_init_data {
 950	int64_t zfb_phys_addr_base;
 951	int64_t zfb_mc_base_addr;
 952	uint64_t zfb_size_in_byte;
 953	enum frame_buffer_mode fb_mode;
 954	bool dchub_initialzied;
 955	bool dchub_info_valid;
 956};
 957
 958struct dc_init_data {
 959	struct hw_asic_id asic_id;
 960	void *driver; /* ctx */
 961	struct cgs_device *cgs_device;
 962	struct dc_bounding_box_overrides bb_overrides;
 963
 964	int num_virtual_links;
 965	/*
 966	 * If 'vbios_override' not NULL, it will be called instead
 967	 * of the real VBIOS. Intended use is Diagnostics on FPGA.
 968	 */
 969	struct dc_bios *vbios_override;
 970	enum dce_environment dce_environment;
 971
 972	struct dmub_offload_funcs *dmub_if;
 973	struct dc_reg_helper_state *dmub_offload;
 974
 975	struct dc_config flags;
 976	uint64_t log_mask;
 977
 
 
 
 
 
 978	struct dpcd_vendor_signature vendor_signature;
 
 979	bool force_smu_not_present;
 980	/*
 981	 * IP offset for run time initializaion of register addresses
 982	 *
 983	 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
 984	 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
 985	 * before them.
 986	 */
 987	uint32_t *dcn_reg_offsets;
 988	uint32_t *nbio_reg_offsets;
 989};
 990
 991struct dc_callback_init {
 992#ifdef CONFIG_DRM_AMD_DC_HDCP
 993	struct cp_psp cp_psp;
 994#else
 995	uint8_t reserved;
 996#endif
 997};
 998
 999struct dc *dc_create(const struct dc_init_data *init_params);
1000void dc_hardware_init(struct dc *dc);
1001
1002int dc_get_vmid_use_vector(struct dc *dc);
1003void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1004/* Returns the number of vmids supported */
1005int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1006void dc_init_callbacks(struct dc *dc,
1007		const struct dc_callback_init *init_params);
1008void dc_deinit_callbacks(struct dc *dc);
1009void dc_destroy(struct dc **dc);
1010
1011/* Surface Interfaces */
 
 
1012
1013enum {
1014	TRANSFER_FUNC_POINTS = 1025
1015};
1016
1017struct dc_hdr_static_metadata {
1018	/* display chromaticities and white point in units of 0.00001 */
1019	unsigned int chromaticity_green_x;
1020	unsigned int chromaticity_green_y;
1021	unsigned int chromaticity_blue_x;
1022	unsigned int chromaticity_blue_y;
1023	unsigned int chromaticity_red_x;
1024	unsigned int chromaticity_red_y;
1025	unsigned int chromaticity_white_point_x;
1026	unsigned int chromaticity_white_point_y;
1027
1028	uint32_t min_luminance;
1029	uint32_t max_luminance;
1030	uint32_t maximum_content_light_level;
1031	uint32_t maximum_frame_average_light_level;
1032};
1033
1034enum dc_transfer_func_type {
1035	TF_TYPE_PREDEFINED,
1036	TF_TYPE_DISTRIBUTED_POINTS,
1037	TF_TYPE_BYPASS,
1038	TF_TYPE_HWPWL
1039};
1040
1041struct dc_transfer_func_distributed_points {
1042	struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1043	struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1044	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1045
1046	uint16_t end_exponent;
1047	uint16_t x_point_at_y1_red;
1048	uint16_t x_point_at_y1_green;
1049	uint16_t x_point_at_y1_blue;
1050};
1051
1052enum dc_transfer_func_predefined {
1053	TRANSFER_FUNCTION_SRGB,
1054	TRANSFER_FUNCTION_BT709,
1055	TRANSFER_FUNCTION_PQ,
1056	TRANSFER_FUNCTION_LINEAR,
1057	TRANSFER_FUNCTION_UNITY,
1058	TRANSFER_FUNCTION_HLG,
1059	TRANSFER_FUNCTION_HLG12,
1060	TRANSFER_FUNCTION_GAMMA22,
1061	TRANSFER_FUNCTION_GAMMA24,
1062	TRANSFER_FUNCTION_GAMMA26
1063};
1064
1065
1066struct dc_transfer_func {
1067	struct kref refcount;
1068	enum dc_transfer_func_type type;
1069	enum dc_transfer_func_predefined tf;
1070	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1071	uint32_t sdr_ref_white_level;
 
1072	union {
1073		struct pwl_params pwl;
1074		struct dc_transfer_func_distributed_points tf_pts;
1075	};
1076};
1077
1078
1079union dc_3dlut_state {
1080	struct {
1081		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */
1082		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/
1083		uint32_t rmu_mux_num:3;		/*index of mux to use*/
1084		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1085		uint32_t mpc_rmu1_mux:4;
1086		uint32_t mpc_rmu2_mux:4;
1087		uint32_t reserved:15;
1088	} bits;
1089	uint32_t raw;
1090};
1091
1092
1093struct dc_3dlut {
1094	struct kref refcount;
1095	struct tetrahedral_params lut_3d;
1096	struct fixed31_32 hdr_multiplier;
1097	union dc_3dlut_state state;
 
1098};
1099/*
1100 * This structure is filled in by dc_surface_get_status and contains
1101 * the last requested address and the currently active address so the called
1102 * can determine if there are any outstanding flips
1103 */
1104struct dc_plane_status {
1105	struct dc_plane_address requested_address;
1106	struct dc_plane_address current_address;
1107	bool is_flip_pending;
1108	bool is_right_eye;
1109};
1110
1111union surface_update_flags {
1112
1113	struct {
1114		uint32_t addr_update:1;
1115		/* Medium updates */
1116		uint32_t dcc_change:1;
1117		uint32_t color_space_change:1;
1118		uint32_t horizontal_mirror_change:1;
1119		uint32_t per_pixel_alpha_change:1;
1120		uint32_t global_alpha_change:1;
1121		uint32_t hdr_mult:1;
1122		uint32_t rotation_change:1;
1123		uint32_t swizzle_change:1;
1124		uint32_t scaling_change:1;
1125		uint32_t position_change:1;
1126		uint32_t in_transfer_func_change:1;
1127		uint32_t input_csc_change:1;
1128		uint32_t coeff_reduction_change:1;
1129		uint32_t output_tf_change:1;
1130		uint32_t pixel_format_change:1;
1131		uint32_t plane_size_change:1;
1132		uint32_t gamut_remap_change:1;
1133
1134		/* Full updates */
1135		uint32_t new_plane:1;
1136		uint32_t bpp_change:1;
1137		uint32_t gamma_change:1;
1138		uint32_t bandwidth_change:1;
1139		uint32_t clock_change:1;
1140		uint32_t stereo_format_change:1;
1141		uint32_t lut_3d:1;
1142		uint32_t tmz_changed:1;
1143		uint32_t full_update:1;
1144	} bits;
1145
1146	uint32_t raw;
1147};
1148
1149struct dc_plane_state {
1150	struct dc_plane_address address;
1151	struct dc_plane_flip_time time;
1152	bool triplebuffer_flips;
1153	struct scaling_taps scaling_quality;
1154	struct rect src_rect;
1155	struct rect dst_rect;
1156	struct rect clip_rect;
1157
1158	struct plane_size plane_size;
1159	union dc_tiling_info tiling_info;
1160
1161	struct dc_plane_dcc_param dcc;
1162
1163	struct dc_gamma *gamma_correction;
1164	struct dc_transfer_func *in_transfer_func;
1165	struct dc_bias_and_scale *bias_and_scale;
1166	struct dc_csc_transform input_csc_color_matrix;
1167	struct fixed31_32 coeff_reduction_factor;
1168	struct fixed31_32 hdr_mult;
1169	struct colorspace_transform gamut_remap_matrix;
1170
1171	// TODO: No longer used, remove
1172	struct dc_hdr_static_metadata hdr_static_ctx;
1173
1174	enum dc_color_space color_space;
1175
1176	struct dc_3dlut *lut3d_func;
1177	struct dc_transfer_func *in_shaper_func;
1178	struct dc_transfer_func *blend_tf;
1179
 
1180	struct dc_transfer_func *gamcor_tf;
 
1181	enum surface_pixel_format format;
1182	enum dc_rotation_angle rotation;
1183	enum plane_stereo_format stereo_format;
1184
1185	bool is_tiling_rotated;
1186	bool per_pixel_alpha;
1187	bool pre_multiplied_alpha;
1188	bool global_alpha;
1189	int  global_alpha_value;
1190	bool visible;
1191	bool flip_immediate;
1192	bool horizontal_mirror;
1193	int layer_index;
1194
1195	union surface_update_flags update_flags;
1196	bool flip_int_enabled;
1197	bool skip_manual_trigger;
1198
1199	/* private to DC core */
1200	struct dc_plane_status status;
1201	struct dc_context *ctx;
1202
1203	/* HACK: Workaround for forcing full reprogramming under some conditions */
1204	bool force_full_update;
1205
1206	bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1207
1208	/* private to dc_surface.c */
1209	enum dc_irq_source irq_source;
1210	struct kref refcount;
1211	struct tg_color visual_confirm_color;
1212
1213	bool is_statically_allocated;
1214};
1215
1216struct dc_plane_info {
1217	struct plane_size plane_size;
1218	union dc_tiling_info tiling_info;
1219	struct dc_plane_dcc_param dcc;
1220	enum surface_pixel_format format;
1221	enum dc_rotation_angle rotation;
1222	enum plane_stereo_format stereo_format;
1223	enum dc_color_space color_space;
1224	bool horizontal_mirror;
1225	bool visible;
1226	bool per_pixel_alpha;
1227	bool pre_multiplied_alpha;
1228	bool global_alpha;
1229	int  global_alpha_value;
1230	bool input_csc_enabled;
1231	int layer_index;
1232};
1233
1234struct dc_scaling_info {
1235	struct rect src_rect;
1236	struct rect dst_rect;
1237	struct rect clip_rect;
1238	struct scaling_taps scaling_quality;
1239};
1240
1241struct dc_surface_update {
1242	struct dc_plane_state *surface;
1243
1244	/* isr safe update parameters.  null means no updates */
1245	const struct dc_flip_addrs *flip_addr;
1246	const struct dc_plane_info *plane_info;
1247	const struct dc_scaling_info *scaling_info;
1248	struct fixed31_32 hdr_mult;
1249	/* following updates require alloc/sleep/spin that is not isr safe,
1250	 * null means no updates
1251	 */
1252	const struct dc_gamma *gamma;
1253	const struct dc_transfer_func *in_transfer_func;
1254
1255	const struct dc_csc_transform *input_csc_color_matrix;
1256	const struct fixed31_32 *coeff_reduction_factor;
1257	const struct dc_transfer_func *func_shaper;
1258	const struct dc_3dlut *lut3d_func;
1259	const struct dc_transfer_func *blend_tf;
1260	const struct colorspace_transform *gamut_remap_matrix;
1261};
1262
1263/*
1264 * Create a new surface with default parameters;
1265 */
1266struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1267const struct dc_plane_status *dc_plane_get_status(
1268		const struct dc_plane_state *plane_state);
1269
1270void dc_plane_state_retain(struct dc_plane_state *plane_state);
1271void dc_plane_state_release(struct dc_plane_state *plane_state);
1272
1273void dc_gamma_retain(struct dc_gamma *dc_gamma);
1274void dc_gamma_release(struct dc_gamma **dc_gamma);
1275struct dc_gamma *dc_create_gamma(void);
1276
1277void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1278void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1279struct dc_transfer_func *dc_create_transfer_func(void);
1280
1281struct dc_3dlut *dc_create_3dlut_func(void);
1282void dc_3dlut_func_release(struct dc_3dlut *lut);
1283void dc_3dlut_func_retain(struct dc_3dlut *lut);
 
 
 
 
 
 
 
 
 
 
 
 
1284
1285void dc_post_update_surfaces_to_stream(
1286		struct dc *dc);
1287
1288#include "dc_stream.h"
1289
1290/**
1291 * struct dc_validation_set - Struct to store surface/stream associations for validation
1292 */
1293struct dc_validation_set {
1294	/**
1295	 * @stream: Stream state properties
1296	 */
1297	struct dc_stream_state *stream;
1298
1299	/**
1300	 * @plane_state: Surface state
1301	 */
1302	struct dc_plane_state *plane_states[MAX_SURFACES];
1303
1304	/**
1305	 * @plane_count: Total of active planes
1306	 */
1307	uint8_t plane_count;
1308};
1309
1310bool dc_validate_boot_timing(const struct dc *dc,
1311				const struct dc_sink *sink,
1312				struct dc_crtc_timing *crtc_timing);
1313
1314enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1315
1316void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1317
1318enum dc_status dc_validate_with_context(struct dc *dc,
1319					const struct dc_validation_set set[],
1320					int set_count,
1321					struct dc_state *context,
1322					bool fast_validate);
1323
1324bool dc_set_generic_gpio_for_stereo(bool enable,
1325		struct gpio_service *gpio_service);
1326
1327/*
1328 * fast_validate: we return after determining if we can support the new state,
1329 * but before we populate the programming info
1330 */
1331enum dc_status dc_validate_global_state(
1332		struct dc *dc,
1333		struct dc_state *new_ctx,
1334		bool fast_validate);
1335
1336
1337void dc_resource_state_construct(
1338		const struct dc *dc,
1339		struct dc_state *dst_ctx);
1340
 
1341bool dc_acquire_release_mpc_3dlut(
1342		struct dc *dc, bool acquire,
1343		struct dc_stream_state *stream,
1344		struct dc_3dlut **lut,
1345		struct dc_transfer_func **shaper);
 
1346
1347void dc_resource_state_copy_construct(
1348		const struct dc_state *src_ctx,
1349		struct dc_state *dst_ctx);
1350
1351void dc_resource_state_copy_construct_current(
1352		const struct dc *dc,
1353		struct dc_state *dst_ctx);
1354
1355void dc_resource_state_destruct(struct dc_state *context);
1356
1357bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1358
1359enum dc_status dc_commit_streams(struct dc *dc,
1360				 struct dc_stream_state *streams[],
1361				 uint8_t stream_count);
1362
1363/* TODO: When the transition to the new commit sequence is done, remove this
1364 * function in favor of dc_commit_streams. */
 
 
 
1365bool dc_commit_state(struct dc *dc, struct dc_state *context);
1366
 
 
1367struct dc_state *dc_create_state(struct dc *dc);
1368struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1369void dc_retain_state(struct dc_state *context);
1370void dc_release_state(struct dc_state *context);
1371
1372/* Link Interfaces */
 
 
1373
1374struct dpcd_caps {
1375	union dpcd_rev dpcd_rev;
1376	union max_lane_count max_ln_count;
1377	union max_down_spread max_down_spread;
1378	union dprx_feature dprx_feature;
1379
1380	/* valid only for eDP v1.4 or higher*/
1381	uint8_t edp_supported_link_rates_count;
1382	enum dc_link_rate edp_supported_link_rates[8];
1383
1384	/* dongle type (DP converter, CV smart dongle) */
1385	enum display_dongle_type dongle_type;
1386	bool is_dongle_type_one;
1387	/* branch device or sink device */
1388	bool is_branch_dev;
1389	/* Dongle's downstream count. */
1390	union sink_count sink_count;
1391	bool is_mst_capable;
1392	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1393	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1394	struct dc_dongle_caps dongle_caps;
1395
1396	uint32_t sink_dev_id;
1397	int8_t sink_dev_id_str[6];
1398	int8_t sink_hw_revision;
1399	int8_t sink_fw_revision[2];
1400
1401	uint32_t branch_dev_id;
1402	int8_t branch_dev_name[6];
1403	int8_t branch_hw_revision;
1404	int8_t branch_fw_revision[2];
1405
1406	bool allow_invalid_MSA_timing_param;
1407	bool panel_mode_edp;
1408	bool dpcd_display_control_capable;
1409	bool ext_receiver_cap_field_present;
1410	bool set_power_state_capable_edp;
1411	bool dynamic_backlight_capable_edp;
1412	union dpcd_fec_capability fec_cap;
1413	struct dpcd_dsc_capabilities dsc_caps;
1414	struct dc_lttpr_caps lttpr_caps;
1415	struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
1416
1417	union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
1418	union dp_main_line_channel_coding_cap channel_coding_cap;
1419	union dp_sink_video_fallback_formats fallback_formats;
1420	union dp_fec_capability1 fec_cap1;
1421	union dp_cable_id cable_id;
1422	uint8_t edp_rev;
1423	union edp_alpm_caps alpm_caps;
1424	struct edp_psr_info psr_info;
1425};
1426
1427union dpcd_sink_ext_caps {
1428	struct {
1429		/* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1430		 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1431		 */
1432		uint8_t sdr_aux_backlight_control : 1;
1433		uint8_t hdr_aux_backlight_control : 1;
1434		uint8_t reserved_1 : 2;
1435		uint8_t oled : 1;
1436		uint8_t reserved : 3;
1437	} bits;
1438	uint8_t raw;
1439};
1440
1441#if defined(CONFIG_DRM_AMD_DC_HDCP)
1442union hdcp_rx_caps {
1443	struct {
1444		uint8_t version;
1445		uint8_t reserved;
1446		struct {
1447			uint8_t repeater	: 1;
1448			uint8_t hdcp_capable	: 1;
1449			uint8_t reserved	: 6;
1450		} byte0;
1451	} fields;
1452	uint8_t raw[3];
1453};
1454
1455union hdcp_bcaps {
1456	struct {
1457		uint8_t HDCP_CAPABLE:1;
1458		uint8_t REPEATER:1;
1459		uint8_t RESERVED:6;
1460	} bits;
1461	uint8_t raw;
1462};
1463
1464struct hdcp_caps {
1465	union hdcp_rx_caps rx_caps;
1466	union hdcp_bcaps bcaps;
1467};
1468#endif
1469
1470#include "dc_link.h"
1471
 
1472uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1473
1474/* Sink Interfaces - A sink corresponds to a display output device */
 
 
 
1475
1476struct dc_container_id {
1477	// 128bit GUID in binary form
1478	unsigned char  guid[16];
1479	// 8 byte port ID -> ELD.PortID
1480	unsigned int   portId[2];
1481	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1482	unsigned short manufacturerName;
1483	// 2 byte product code -> ELD.ProductCode
1484	unsigned short productCode;
1485};
1486
1487
1488struct dc_sink_dsc_caps {
1489	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1490	// 'false' if they are sink's DSC caps
1491	bool is_virtual_dpcd_dsc;
1492#if defined(CONFIG_DRM_AMD_DC_DCN)
1493	// 'true' if MST topology supports DSC passthrough for sink
1494	// 'false' if MST topology does not support DSC passthrough
1495	bool is_dsc_passthrough_supported;
1496#endif
1497	struct dsc_dec_dpcd_caps dsc_dec_caps;
1498};
1499
1500struct dc_sink_fec_caps {
1501	bool is_rx_fec_supported;
1502	bool is_topology_fec_supported;
1503};
1504
1505/*
1506 * The sink structure contains EDID and other display device properties
1507 */
1508struct dc_sink {
1509	enum signal_type sink_signal;
1510	struct dc_edid dc_edid; /* raw edid */
1511	struct dc_edid_caps edid_caps; /* parse display caps */
1512	struct dc_container_id *dc_container_id;
1513	uint32_t dongle_max_pix_clk;
1514	void *priv;
1515	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1516	bool converter_disable_audio;
1517
1518	struct dc_sink_dsc_caps dsc_caps;
1519	struct dc_sink_fec_caps fec_caps;
1520
1521	bool is_vsc_sdp_colorimetry_supported;
1522
1523	/* private to DC core */
1524	struct dc_link *link;
1525	struct dc_context *ctx;
1526
1527	uint32_t sink_id;
1528
1529	/* private to dc_sink.c */
1530	// refcount must be the last member in dc_sink, since we want the
1531	// sink structure to be logically cloneable up to (but not including)
1532	// refcount
1533	struct kref refcount;
1534};
1535
1536void dc_sink_retain(struct dc_sink *sink);
1537void dc_sink_release(struct dc_sink *sink);
1538
1539struct dc_sink_init_data {
1540	enum signal_type sink_signal;
1541	struct dc_link *link;
1542	uint32_t dongle_max_pix_clk;
1543	bool converter_disable_audio;
 
1544};
1545
1546bool dc_extended_blank_supported(struct dc *dc);
1547
1548struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1549
1550/* Newer interfaces  */
1551struct dc_cursor {
1552	struct dc_plane_address address;
1553	struct dc_cursor_attributes attributes;
1554};
1555
1556
1557/* Interrupt interfaces */
 
 
1558enum dc_irq_source dc_interrupt_to_irq_source(
1559		struct dc *dc,
1560		uint32_t src_id,
1561		uint32_t ext_id);
1562bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1563void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1564enum dc_irq_source dc_get_hpd_irq_source_at_index(
1565		struct dc *dc, uint32_t link_index);
1566
1567void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
1568
1569/* Power Interfaces */
1570
1571void dc_set_power_state(
1572		struct dc *dc,
1573		enum dc_acpi_cm_power_state power_state);
1574void dc_resume(struct dc *dc);
1575
1576void dc_power_down_on_boot(struct dc *dc);
1577
1578#if defined(CONFIG_DRM_AMD_DC_HDCP)
1579/*
1580 * HDCP Interfaces
1581 */
1582enum hdcp_message_status dc_process_hdcp_msg(
1583		enum signal_type signal,
1584		struct dc_link *link,
1585		struct hdcp_protection_message *message_info);
1586#endif
1587bool dc_is_dmcu_initialized(struct dc *dc);
1588
1589enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1590void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1591
1592bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
1593				struct dc_cursor_attributes *cursor_attr);
1594
1595void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1596
1597/* set min and max memory clock to lowest and highest DPM level, respectively */
 
 
 
1598void dc_unlock_memory_clock_frequency(struct dc *dc);
1599
1600/* set min memory clock to the min required for current mode, max to maxDPM */
 
 
 
1601void dc_lock_memory_clock_frequency(struct dc *dc);
1602
1603/* set soft max for memclk, to be used for AC/DC switching clock limitations */
1604void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
1605
1606/* cleanup on driver unload */
1607void dc_hardware_release(struct dc *dc);
1608
1609/* disables fw based mclk switch */
1610void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
1611
1612bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1613void dc_z10_restore(const struct dc *dc);
1614void dc_z10_save_init(struct dc *dc);
1615
1616bool dc_is_dmub_outbox_supported(struct dc *dc);
1617bool dc_enable_dmub_notifications(struct dc *dc);
1618
1619void dc_enable_dmub_outbox(struct dc *dc);
1620
1621bool dc_process_dmub_aux_transfer_async(struct dc *dc,
1622				uint32_t link_index,
1623				struct aux_payload *payload);
1624
1625/* Get dc link index from dpia port index */
1626uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
1627				uint8_t dpia_port_index);
1628
1629bool dc_process_dmub_set_config_async(struct dc *dc,
1630				uint32_t link_index,
1631				struct set_config_cmd_payload *payload,
1632				struct dmub_notification *notify);
1633
1634enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
1635				uint32_t link_index,
1636				uint8_t mst_alloc_slots,
1637				uint8_t *mst_slots_in_use);
1638
1639void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
1640				uint32_t hpd_int_enable);
1641
1642/* DSC Interfaces */
1643#include "dc_dsc.h"
1644
1645/* Disable acc mode Interfaces */
1646void dc_disable_accelerated_mode(struct dc *dc);
1647
1648#endif /* DC_INTERFACE_H_ */