1/*
   2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef DC_INTERFACE_H_
  27#define DC_INTERFACE_H_
  28
  29#include "dc_types.h"
  30#include "dc_state.h"
  31#include "dc_plane.h"
  32#include "grph_object_defs.h"
  33#include "logger_types.h"
  34#include "hdcp_msg_types.h"
  35#include "gpio_types.h"
  36#include "link_service_types.h"
  37#include "grph_object_ctrl_defs.h"
  38#include <inc/hw/opp.h>
  39
  40#include "hwss/hw_sequencer.h"
  41#include "inc/compressor.h"
  42#include "inc/hw/dmcu.h"
  43#include "dml/display_mode_lib.h"
  44
  45#include "dml2/dml2_wrapper.h"
  46
  47struct abm_save_restore;
  48
  49/* forward declaration */
  50struct aux_payload;
  51struct set_config_cmd_payload;
  52struct dmub_notification;
  53
  54#define DC_VER "3.2.273"
  55
  56#define MAX_SURFACES 3
  57#define MAX_PLANES 6
  58#define MAX_STREAMS 6
  59#define MIN_VIEWPORT_SIZE 12
  60#define MAX_NUM_EDP 2
  61
  62/* Display Core Interfaces */
  63struct dc_versions {
  64	const char *dc_ver;
  65	struct dmcu_version dmcu_version;
  66};
  67
  68enum dp_protocol_version {
  69	DP_VERSION_1_4 = 0,
  70	DP_VERSION_2_1,
  71	DP_VERSION_UNKNOWN,
  72};
  73
  74enum dc_plane_type {
  75	DC_PLANE_TYPE_INVALID,
  76	DC_PLANE_TYPE_DCE_RGB,
  77	DC_PLANE_TYPE_DCE_UNDERLAY,
  78	DC_PLANE_TYPE_DCN_UNIVERSAL,
  79};
  80
  81// Sizes defined as multiples of 64KB
  82enum det_size {
  83	DET_SIZE_DEFAULT = 0,
  84	DET_SIZE_192KB = 3,
  85	DET_SIZE_256KB = 4,
  86	DET_SIZE_320KB = 5,
  87	DET_SIZE_384KB = 6
  88};
  89
  90
  91struct dc_plane_cap {
  92	enum dc_plane_type type;
  93	uint32_t per_pixel_alpha : 1;
  94	struct {
  95		uint32_t argb8888 : 1;
  96		uint32_t nv12 : 1;
  97		uint32_t fp16 : 1;
  98		uint32_t p010 : 1;
  99		uint32_t ayuv : 1;
 100	} pixel_format_support;
 101	// max upscaling factor x1000
 102	// upscaling factors are always >= 1
 103	// for example, 1080p -> 8K is 4.0, or 4000 raw value
 104	struct {
 105		uint32_t argb8888;
 106		uint32_t nv12;
 107		uint32_t fp16;
 108	} max_upscale_factor;
 109	// max downscale factor x1000
 110	// downscale factors are always <= 1
 111	// for example, 8K -> 1080p is 0.25, or 250 raw value
 112	struct {
 113		uint32_t argb8888;
 114		uint32_t nv12;
 115		uint32_t fp16;
 116	} max_downscale_factor;
 117	// minimal width/height
 118	uint32_t min_width;
 119	uint32_t min_height;
 120};
 121
 122/**
 123 * DOC: color-management-caps
 124 *
 125 * **Color management caps (DPP and MPC)**
 126 *
 127 * Modules/color calculates various color operations which are translated to
 128 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
 129 * DCN1, every new generation comes with fairly major differences in color
 130 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
 131 * decide mapping to HW block based on logical capabilities.
 132 */
 133
 134/**
 135 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
 136 * @srgb: RGB color space transfer func
 137 * @bt2020: BT.2020 transfer func
 138 * @gamma2_2: standard gamma
 139 * @pq: perceptual quantizer transfer function
 140 * @hlg: hybrid log–gamma transfer function
 141 */
 142struct rom_curve_caps {
 143	uint16_t srgb : 1;
 144	uint16_t bt2020 : 1;
 145	uint16_t gamma2_2 : 1;
 146	uint16_t pq : 1;
 147	uint16_t hlg : 1;
 148};
 149
 150/**
 151 * struct dpp_color_caps - color pipeline capabilities for display pipe and
 152 * plane blocks
 153 *
 154 * @dcn_arch: all DCE generations treated the same
 155 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
 156 * just plain 256-entry lookup
 157 * @icsc: input color space conversion
 158 * @dgam_ram: programmable degamma LUT
 159 * @post_csc: post color space conversion, before gamut remap
 160 * @gamma_corr: degamma correction
 161 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
 162 * with MPC by setting mpc:shared_3d_lut flag
 163 * @ogam_ram: programmable out/blend gamma LUT
 164 * @ocsc: output color space conversion
 165 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
 166 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
 167 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
 168 *
 169 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
 170 */
 171struct dpp_color_caps {
 172	uint16_t dcn_arch : 1;
 173	uint16_t input_lut_shared : 1;
 174	uint16_t icsc : 1;
 175	uint16_t dgam_ram : 1;
 176	uint16_t post_csc : 1;
 177	uint16_t gamma_corr : 1;
 178	uint16_t hw_3d_lut : 1;
 179	uint16_t ogam_ram : 1;
 180	uint16_t ocsc : 1;
 181	uint16_t dgam_rom_for_yuv : 1;
 182	struct rom_curve_caps dgam_rom_caps;
 183	struct rom_curve_caps ogam_rom_caps;
 184};
 185
 186/**
 187 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
 188 * plane combined blocks
 189 *
 190 * @gamut_remap: color transformation matrix
 191 * @ogam_ram: programmable out gamma LUT
 192 * @ocsc: output color space conversion matrix
 193 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
 194 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
 195 * instance
 196 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
 197 */
 198struct mpc_color_caps {
 199	uint16_t gamut_remap : 1;
 200	uint16_t ogam_ram : 1;
 201	uint16_t ocsc : 1;
 202	uint16_t num_3dluts : 3;
 203	uint16_t shared_3d_lut:1;
 204	struct rom_curve_caps ogam_rom_caps;
 205};
 206
 207/**
 208 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
 209 * @dpp: color pipes caps for DPP
 210 * @mpc: color pipes caps for MPC
 211 */
 212struct dc_color_caps {
 213	struct dpp_color_caps dpp;
 214	struct mpc_color_caps mpc;
 215};
 216
 217struct dc_dmub_caps {
 218	bool psr;
 219	bool mclk_sw;
 220	bool subvp_psr;
 221	bool gecc_enable;
 222};
 223
 224struct dc_caps {
 225	uint32_t max_streams;
 226	uint32_t max_links;
 227	uint32_t max_audios;
 228	uint32_t max_slave_planes;
 229	uint32_t max_slave_yuv_planes;
 230	uint32_t max_slave_rgb_planes;
 231	uint32_t max_planes;
 232	uint32_t max_downscale_ratio;
 233	uint32_t i2c_speed_in_khz;
 234	uint32_t i2c_speed_in_khz_hdcp;
 235	uint32_t dmdata_alloc_size;
 236	unsigned int max_cursor_size;
 237	unsigned int max_video_width;
 238	/*
 239	 * max video plane width that can be safely assumed to be always
 240	 * supported by single DPP pipe.
 241	 */
 242	unsigned int max_optimizable_video_width;
 243	unsigned int min_horizontal_blanking_period;
 244	int linear_pitch_alignment;
 245	bool dcc_const_color;
 246	bool dynamic_audio;
 247	bool is_apu;
 248	bool dual_link_dvi;
 249	bool post_blend_color_processing;
 250	bool force_dp_tps4_for_cp2520;
 251	bool disable_dp_clk_share;
 252	bool psp_setup_panel_mode;
 253	bool extended_aux_timeout_support;
 254	bool dmcub_support;
 255	bool zstate_support;
 256	bool ips_support;
 257	uint32_t num_of_internal_disp;
 258	enum dp_protocol_version max_dp_protocol_version;
 259	unsigned int mall_size_per_mem_channel;
 260	unsigned int mall_size_total;
 261	unsigned int cursor_cache_size;
 262	struct dc_plane_cap planes[MAX_PLANES];
 263	struct dc_color_caps color;
 264	struct dc_dmub_caps dmub_caps;
 265	bool dp_hpo;
 266	bool dp_hdmi21_pcon_support;
 267	bool edp_dsc_support;
 268	bool vbios_lttpr_aware;
 269	bool vbios_lttpr_enable;
 270	uint32_t max_otg_num;
 271	uint32_t max_cab_allocation_bytes;
 272	uint32_t cache_line_size;
 273	uint32_t cache_num_ways;
 274	uint16_t subvp_fw_processing_delay_us;
 275	uint8_t subvp_drr_max_vblank_margin_us;
 276	uint16_t subvp_prefetch_end_to_mall_start_us;
 277	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
 278	uint16_t subvp_pstate_allow_width_us;
 279	uint16_t subvp_vertical_int_margin_us;
 280	bool seamless_odm;
 281	uint32_t max_v_total;
 282	uint32_t max_disp_clock_khz_at_vmin;
 283	uint8_t subvp_drr_vblank_start_margin_us;
 284};
 285
 286struct dc_bug_wa {
 287	bool no_connect_phy_config;
 288	bool dedcn20_305_wa;
 289	bool skip_clock_update;
 290	bool lt_early_cr_pattern;
 291	struct {
 292		uint8_t uclk : 1;
 293		uint8_t fclk : 1;
 294		uint8_t dcfclk : 1;
 295		uint8_t dcfclk_ds: 1;
 296	} clock_update_disable_mask;
 297};
 298struct dc_dcc_surface_param {
 299	struct dc_size surface_size;
 300	enum surface_pixel_format format;
 301	enum swizzle_mode_values swizzle_mode;
 302	enum dc_scan_direction scan;
 303};
 304
 305struct dc_dcc_setting {
 306	unsigned int max_compressed_blk_size;
 307	unsigned int max_uncompressed_blk_size;
 308	bool independent_64b_blks;
 309	//These bitfields to be used starting with DCN
 310	struct {
 311		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
 312		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN
 313		uint32_t dcc_256_128_128 : 1;		//available starting with DCN
 314		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN (the best compression case)
 315	} dcc_controls;
 316};
 317
 318struct dc_surface_dcc_cap {
 319	union {
 320		struct {
 321			struct dc_dcc_setting rgb;
 322		} grph;
 323
 324		struct {
 325			struct dc_dcc_setting luma;
 326			struct dc_dcc_setting chroma;
 327		} video;
 328	};
 329
 330	bool capable;
 331	bool const_color_support;
 332};
 333
 334struct dc_static_screen_params {
 335	struct {
 336		bool force_trigger;
 337		bool cursor_update;
 338		bool surface_update;
 339		bool overlay_update;
 340	} triggers;
 341	unsigned int num_frames;
 342};
 343
 344
 345/* Surface update type is used by dc_update_surfaces_and_stream
 346 * The update type is determined at the very beginning of the function based
 347 * on parameters passed in and decides how much programming (or updating) is
 348 * going to be done during the call.
 349 *
 350 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 351 * logical calculations or hardware register programming. This update MUST be
 352 * ISR safe on windows. Currently fast update will only be used to flip surface
 353 * address.
 354 *
 355 * UPDATE_TYPE_MED is used for slower updates which require significant hw
 356 * re-programming however do not affect bandwidth consumption or clock
 357 * requirements. At present, this is the level at which front end updates
 358 * that do not require us to run bw_calcs happen. These are in/out transfer func
 359 * updates, viewport offset changes, recout size changes and pixel depth changes.
 360 * This update can be done at ISR, but we want to minimize how often this happens.
 361 *
 362 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 363 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 364 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 365 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 366 * a full update. This cannot be done at ISR level and should be a rare event.
 367 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 368 * underscan we don't expect to see this call at all.
 369 */
 370
 371enum surface_update_type {
 372	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
 373	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
 374	UPDATE_TYPE_FULL, /* may need to shuffle resources */
 375};
 376
 377/* Forward declaration*/
 378struct dc;
 379struct dc_plane_state;
 380struct dc_state;
 381
 382
 383struct dc_cap_funcs {
 384	bool (*get_dcc_compression_cap)(const struct dc *dc,
 385			const struct dc_dcc_surface_param *input,
 386			struct dc_surface_dcc_cap *output);
 387	bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
 388};
 389
 390struct link_training_settings;
 391
 392union allow_lttpr_non_transparent_mode {
 393	struct {
 394		bool DP1_4A : 1;
 395		bool DP2_0 : 1;
 396	} bits;
 397	unsigned char raw;
 398};
 399
 400/* Structure to hold configuration flags set by dm at dc creation. */
 401struct dc_config {
 402	bool gpu_vm_support;
 403	bool disable_disp_pll_sharing;
 404	bool fbc_support;
 405	bool disable_fractional_pwm;
 406	bool allow_seamless_boot_optimization;
 407	bool seamless_boot_edp_requested;
 408	bool edp_not_connected;
 409	bool edp_no_power_sequencing;
 410	bool force_enum_edp;
 411	bool forced_clocks;
 412	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
 413	bool multi_mon_pp_mclk_switch;
 414	bool disable_dmcu;
 415	bool enable_4to1MPC;
 416	bool enable_windowed_mpo_odm;
 417	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
 418	uint32_t allow_edp_hotplug_detection;
 419	bool clamp_min_dcfclk;
 420	uint64_t vblank_alignment_dto_params;
 421	uint8_t  vblank_alignment_max_frame_time_diff;
 422	bool is_asymmetric_memory;
 423	bool is_single_rank_dimm;
 424	bool is_vmin_only_asic;
 425	bool use_pipe_ctx_sync_logic;
 426	bool ignore_dpref_ss;
 427	bool enable_mipi_converter_optimization;
 428	bool use_default_clock_table;
 429	bool force_bios_enable_lttpr;
 430	uint8_t force_bios_fixed_vs;
 431	int sdpif_request_limit_words_per_umc;
 432	bool dc_mode_clk_limit_support;
 433	bool EnableMinDispClkODM;
 434	bool enable_auto_dpm_test_logs;
 435	unsigned int disable_ips;
 436	unsigned int disable_ips_in_vpb;
 437	bool usb4_bw_alloc_support;
 438};
 439
 440enum visual_confirm {
 441	VISUAL_CONFIRM_DISABLE = 0,
 442	VISUAL_CONFIRM_SURFACE = 1,
 443	VISUAL_CONFIRM_HDR = 2,
 444	VISUAL_CONFIRM_MPCTREE = 4,
 445	VISUAL_CONFIRM_PSR = 5,
 446	VISUAL_CONFIRM_SWAPCHAIN = 6,
 447	VISUAL_CONFIRM_FAMS = 7,
 448	VISUAL_CONFIRM_SWIZZLE = 9,
 449	VISUAL_CONFIRM_REPLAY = 12,
 450	VISUAL_CONFIRM_SUBVP = 14,
 451	VISUAL_CONFIRM_MCLK_SWITCH = 16,
 452};
 453
 454enum dc_psr_power_opts {
 455	psr_power_opt_invalid = 0x0,
 456	psr_power_opt_smu_opt_static_screen = 0x1,
 457	psr_power_opt_z10_static_screen = 0x10,
 458	psr_power_opt_ds_disable_allow = 0x100,
 459};
 460
 461enum dml_hostvm_override_opts {
 462	DML_HOSTVM_NO_OVERRIDE = 0x0,
 463	DML_HOSTVM_OVERRIDE_FALSE = 0x1,
 464	DML_HOSTVM_OVERRIDE_TRUE = 0x2,
 465};
 466
 467enum dc_replay_power_opts {
 468	replay_power_opt_invalid		= 0x0,
 469	replay_power_opt_smu_opt_static_screen	= 0x1,
 470	replay_power_opt_z10_static_screen	= 0x10,
 471};
 472
 473enum dcc_option {
 474	DCC_ENABLE = 0,
 475	DCC_DISABLE = 1,
 476	DCC_HALF_REQ_DISALBE = 2,
 477};
 478
 479/**
 480 * enum pipe_split_policy - Pipe split strategy supported by DCN
 481 *
 482 * This enum is used to define the pipe split policy supported by DCN. By
 483 * default, DC favors MPC_SPLIT_DYNAMIC.
 484 */
 485enum pipe_split_policy {
 486	/**
 487	 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
 488	 * pipe in order to bring the best trade-off between performance and
 489	 * power consumption. This is the recommended option.
 490	 */
 491	MPC_SPLIT_DYNAMIC = 0,
 492
 493	/**
 494	 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
 495	 * try any sort of split optimization.
 496	 */
 497	MPC_SPLIT_AVOID = 1,
 498
 499	/**
 500	 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
 501	 * optimize the pipe utilization when using a single display; if the
 502	 * user connects to a second display, DC will avoid pipe split.
 503	 */
 504	MPC_SPLIT_AVOID_MULT_DISP = 2,
 505};
 506
 507enum wm_report_mode {
 508	WM_REPORT_DEFAULT = 0,
 509	WM_REPORT_OVERRIDE = 1,
 510};
 511enum dtm_pstate{
 512	dtm_level_p0 = 0,/*highest voltage*/
 513	dtm_level_p1,
 514	dtm_level_p2,
 515	dtm_level_p3,
 516	dtm_level_p4,/*when active_display_count = 0*/
 517};
 518
 519enum dcn_pwr_state {
 520	DCN_PWR_STATE_UNKNOWN = -1,
 521	DCN_PWR_STATE_MISSION_MODE = 0,
 522	DCN_PWR_STATE_LOW_POWER = 3,
 523};
 524
 525enum dcn_zstate_support_state {
 526	DCN_ZSTATE_SUPPORT_UNKNOWN,
 527	DCN_ZSTATE_SUPPORT_ALLOW,
 528	DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
 529	DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
 530	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
 531	DCN_ZSTATE_SUPPORT_DISALLOW,
 532};
 533
 534/*
 535 * struct dc_clocks - DC pipe clocks
 536 *
 537 * For any clocks that may differ per pipe only the max is stored in this
 538 * structure
 539 */
 540struct dc_clocks {
 541	int dispclk_khz;
 542	int actual_dispclk_khz;
 543	int dppclk_khz;
 544	int actual_dppclk_khz;
 545	int disp_dpp_voltage_level_khz;
 546	int dcfclk_khz;
 547	int socclk_khz;
 548	int dcfclk_deep_sleep_khz;
 549	int fclk_khz;
 550	int phyclk_khz;
 551	int dramclk_khz;
 552	bool p_state_change_support;
 553	enum dcn_zstate_support_state zstate_support;
 554	bool dtbclk_en;
 555	int ref_dtbclk_khz;
 556	bool fclk_p_state_change_support;
 557	enum dcn_pwr_state pwr_state;
 558	/*
 559	 * Elements below are not compared for the purposes of
 560	 * optimization required
 561	 */
 562	bool prev_p_state_change_support;
 563	bool fclk_prev_p_state_change_support;
 564	int num_ways;
 565
 566	/*
 567	 * @fw_based_mclk_switching
 568	 *
 569	 * DC has a mechanism that leverage the variable refresh rate to switch
 570	 * memory clock in cases that we have a large latency to achieve the
 571	 * memory clock change and a short vblank window. DC has some
 572	 * requirements to enable this feature, and this field describes if the
 573	 * system support or not such a feature.
 574	 */
 575	bool fw_based_mclk_switching;
 576	bool fw_based_mclk_switching_shut_down;
 577	int prev_num_ways;
 578	enum dtm_pstate dtm_level;
 579	int max_supported_dppclk_khz;
 580	int max_supported_dispclk_khz;
 581	int bw_dppclk_khz; /*a copy of dppclk_khz*/
 582	int bw_dispclk_khz;
 583};
 584
 585struct dc_bw_validation_profile {
 586	bool enable;
 587
 588	unsigned long long total_ticks;
 589	unsigned long long voltage_level_ticks;
 590	unsigned long long watermark_ticks;
 591	unsigned long long rq_dlg_ticks;
 592
 593	unsigned long long total_count;
 594	unsigned long long skip_fast_count;
 595	unsigned long long skip_pass_count;
 596	unsigned long long skip_fail_count;
 597};
 598
 599#define BW_VAL_TRACE_SETUP() \
 600		unsigned long long end_tick = 0; \
 601		unsigned long long voltage_level_tick = 0; \
 602		unsigned long long watermark_tick = 0; \
 603		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
 604				dm_get_timestamp(dc->ctx) : 0
 605
 606#define BW_VAL_TRACE_COUNT() \
 607		if (dc->debug.bw_val_profile.enable) \
 608			dc->debug.bw_val_profile.total_count++
 609
 610#define BW_VAL_TRACE_SKIP(status) \
 611		if (dc->debug.bw_val_profile.enable) { \
 612			if (!voltage_level_tick) \
 613				voltage_level_tick = dm_get_timestamp(dc->ctx); \
 614			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
 615		}
 616
 617#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
 618		if (dc->debug.bw_val_profile.enable) \
 619			voltage_level_tick = dm_get_timestamp(dc->ctx)
 620
 621#define BW_VAL_TRACE_END_WATERMARKS() \
 622		if (dc->debug.bw_val_profile.enable) \
 623			watermark_tick = dm_get_timestamp(dc->ctx)
 624
 625#define BW_VAL_TRACE_FINISH() \
 626		if (dc->debug.bw_val_profile.enable) { \
 627			end_tick = dm_get_timestamp(dc->ctx); \
 628			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
 629			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
 630			if (watermark_tick) { \
 631				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
 632				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
 633			} \
 634		}
 635
 636union mem_low_power_enable_options {
 637	struct {
 638		bool vga: 1;
 639		bool i2c: 1;
 640		bool dmcu: 1;
 641		bool dscl: 1;
 642		bool cm: 1;
 643		bool mpc: 1;
 644		bool optc: 1;
 645		bool vpg: 1;
 646		bool afmt: 1;
 647	} bits;
 648	uint32_t u32All;
 649};
 650
 651union root_clock_optimization_options {
 652	struct {
 653		bool dpp: 1;
 654		bool dsc: 1;
 655		bool hdmistream: 1;
 656		bool hdmichar: 1;
 657		bool dpstream: 1;
 658		bool symclk32_se: 1;
 659		bool symclk32_le: 1;
 660		bool symclk_fe: 1;
 661		bool physymclk: 1;
 662		bool dpiasymclk: 1;
 663		uint32_t reserved: 22;
 664	} bits;
 665	uint32_t u32All;
 666};
 667
 668union fine_grain_clock_gating_enable_options {
 669	struct {
 670		bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */
 671		bool dchub : 1;	   /* Display controller hub */
 672		bool dchubbub : 1;
 673		bool dpp : 1;	   /* Display pipes and planes */
 674		bool opp : 1;	   /* Output pixel processing */
 675		bool optc : 1;	   /* Output pipe timing combiner */
 676		bool dio : 1;	   /* Display output */
 677		bool dwb : 1;	   /* Display writeback */
 678		bool mmhubbub : 1; /* Multimedia hub */
 679		bool dmu : 1;	   /* Display core management unit */
 680		bool az : 1;	   /* Azalia */
 681		bool dchvm : 1;
 682		bool dsc : 1;	   /* Display stream compression */
 683
 684		uint32_t reserved : 19;
 685	} bits;
 686	uint32_t u32All;
 687};
 688
 689enum pg_hw_pipe_resources {
 690	PG_HUBP = 0,
 691	PG_DPP,
 692	PG_DSC,
 693	PG_MPCC,
 694	PG_OPP,
 695	PG_OPTC,
 696	PG_HW_PIPE_RESOURCES_NUM_ELEMENT
 697};
 698
 699enum pg_hw_resources {
 700	PG_DCCG = 0,
 701	PG_DCIO,
 702	PG_DIO,
 703	PG_DCHUBBUB,
 704	PG_DCHVM,
 705	PG_DWB,
 706	PG_HPO,
 707	PG_HW_RESOURCES_NUM_ELEMENT
 708};
 709
 710struct pg_block_update {
 711	bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
 712	bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT];
 713};
 714
 715union dpia_debug_options {
 716	struct {
 717		uint32_t disable_dpia:1; /* bit 0 */
 718		uint32_t force_non_lttpr:1; /* bit 1 */
 719		uint32_t extend_aux_rd_interval:1; /* bit 2 */
 720		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
 721		uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
 722		uint32_t reserved:27;
 723	} bits;
 724	uint32_t raw;
 725};
 726
 727/* AUX wake work around options
 728 * 0: enable/disable work around
 729 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
 730 * 15-2: reserved
 731 * 31-16: timeout in ms
 732 */
 733union aux_wake_wa_options {
 734	struct {
 735		uint32_t enable_wa : 1;
 736		uint32_t use_default_timeout : 1;
 737		uint32_t rsvd: 14;
 738		uint32_t timeout_ms : 16;
 739	} bits;
 740	uint32_t raw;
 741};
 742
 743struct dc_debug_data {
 744	uint32_t ltFailCount;
 745	uint32_t i2cErrorCount;
 746	uint32_t auxErrorCount;
 747};
 748
 749struct dc_phy_addr_space_config {
 750	struct {
 751		uint64_t start_addr;
 752		uint64_t end_addr;
 753		uint64_t fb_top;
 754		uint64_t fb_offset;
 755		uint64_t fb_base;
 756		uint64_t agp_top;
 757		uint64_t agp_bot;
 758		uint64_t agp_base;
 759	} system_aperture;
 760
 761	struct {
 762		uint64_t page_table_start_addr;
 763		uint64_t page_table_end_addr;
 764		uint64_t page_table_base_addr;
 765		bool base_addr_is_mc_addr;
 766	} gart_config;
 767
 768	bool valid;
 769	bool is_hvm_enabled;
 770	uint64_t page_table_default_page_addr;
 771};
 772
 773struct dc_virtual_addr_space_config {
 774	uint64_t	page_table_base_addr;
 775	uint64_t	page_table_start_addr;
 776	uint64_t	page_table_end_addr;
 777	uint32_t	page_table_block_size_in_bytes;
 778	uint8_t		page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
 779};
 780
 781struct dc_bounding_box_overrides {
 782	int sr_exit_time_ns;
 783	int sr_enter_plus_exit_time_ns;
 784	int sr_exit_z8_time_ns;
 785	int sr_enter_plus_exit_z8_time_ns;
 786	int urgent_latency_ns;
 787	int percent_of_ideal_drambw;
 788	int dram_clock_change_latency_ns;
 789	int dummy_clock_change_latency_ns;
 790	int fclk_clock_change_latency_ns;
 791	/* This forces a hard min on the DCFCLK we use
 792	 * for DML.  Unlike the debug option for forcing
 793	 * DCFCLK, this override affects watermark calculations
 794	 */
 795	int min_dcfclk_mhz;
 796};
 797
 798struct dc_state;
 799struct resource_pool;
 800struct dce_hwseq;
 801struct link_service;
 802
 803/*
 804 * struct dc_debug_options - DC debug struct
 805 *
 806 * This struct provides a simple mechanism for developers to change some
 807 * configurations, enable/disable features, and activate extra debug options.
 808 * This can be very handy to narrow down whether some specific feature is
 809 * causing an issue or not.
 810 */
 811struct dc_debug_options {
 812	bool native422_support;
 813	bool disable_dsc;
 814	enum visual_confirm visual_confirm;
 815	int visual_confirm_rect_height;
 816
 817	bool sanity_checks;
 818	bool max_disp_clk;
 819	bool surface_trace;
 820	bool timing_trace;
 821	bool clock_trace;
 822	bool validation_trace;
 823	bool bandwidth_calcs_trace;
 824	int max_downscale_src_width;
 825
 826	/* stutter efficiency related */
 827	bool disable_stutter;
 828	bool use_max_lb;
 829	enum dcc_option disable_dcc;
 830
 831	/*
 832	 * @pipe_split_policy: Define which pipe split policy is used by the
 833	 * display core.
 834	 */
 835	enum pipe_split_policy pipe_split_policy;
 836	bool force_single_disp_pipe_split;
 837	bool voltage_align_fclk;
 838	bool disable_min_fclk;
 839
 840	bool disable_dfs_bypass;
 841	bool disable_dpp_power_gate;
 842	bool disable_hubp_power_gate;
 843	bool disable_dsc_power_gate;
 844	bool disable_optc_power_gate;
 845	bool disable_hpo_power_gate;
 846	int dsc_min_slice_height_override;
 847	int dsc_bpp_increment_div;
 848	bool disable_pplib_wm_range;
 849	enum wm_report_mode pplib_wm_report_mode;
 850	unsigned int min_disp_clk_khz;
 851	unsigned int min_dpp_clk_khz;
 852	unsigned int min_dram_clk_khz;
 853	int sr_exit_time_dpm0_ns;
 854	int sr_enter_plus_exit_time_dpm0_ns;
 855	int sr_exit_time_ns;
 856	int sr_enter_plus_exit_time_ns;
 857	int sr_exit_z8_time_ns;
 858	int sr_enter_plus_exit_z8_time_ns;
 859	int urgent_latency_ns;
 860	uint32_t underflow_assert_delay_us;
 861	int percent_of_ideal_drambw;
 862	int dram_clock_change_latency_ns;
 863	bool optimized_watermark;
 864	int always_scale;
 865	bool disable_pplib_clock_request;
 866	bool disable_clock_gate;
 867	bool disable_mem_low_power;
 868	bool pstate_enabled;
 869	bool disable_dmcu;
 870	bool force_abm_enable;
 871	bool disable_stereo_support;
 872	bool vsr_support;
 873	bool performance_trace;
 874	bool az_endpoint_mute_only;
 875	bool always_use_regamma;
 876	bool recovery_enabled;
 877	bool avoid_vbios_exec_table;
 878	bool scl_reset_length10;
 879	bool hdmi20_disable;
 880	bool skip_detection_link_training;
 881	uint32_t edid_read_retry_times;
 882	unsigned int force_odm_combine; //bit vector based on otg inst
 883	unsigned int seamless_boot_odm_combine;
 884	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
 885	int minimum_z8_residency_time;
 886	int minimum_z10_residency_time;
 887	bool disable_z9_mpc;
 888	unsigned int force_fclk_khz;
 889	bool enable_tri_buf;
 890	bool dmub_offload_enabled;
 891	bool dmcub_emulation;
 892	bool disable_idle_power_optimizations;
 893	unsigned int mall_size_override;
 894	unsigned int mall_additional_timer_percent;
 895	bool mall_error_as_fatal;
 896	bool dmub_command_table; /* for testing only */
 897	struct dc_bw_validation_profile bw_val_profile;
 898	bool disable_fec;
 899	bool disable_48mhz_pwrdwn;
 900	/* This forces a hard min on the DCFCLK requested to SMU/PP
 901	 * watermarks are not affected.
 902	 */
 903	unsigned int force_min_dcfclk_mhz;
 904	int dwb_fi_phase;
 905	bool disable_timing_sync;
 906	bool cm_in_bypass;
 907	int force_clock_mode;/*every mode change.*/
 908
 909	bool disable_dram_clock_change_vactive_support;
 910	bool validate_dml_output;
 911	bool enable_dmcub_surface_flip;
 912	bool usbc_combo_phy_reset_wa;
 913	bool enable_dram_clock_change_one_display_vactive;
 914	/* TODO - remove once tested */
 915	bool legacy_dp2_lt;
 916	bool set_mst_en_for_sst;
 917	bool disable_uhbr;
 918	bool force_dp2_lt_fallback_method;
 919	bool ignore_cable_id;
 920	union mem_low_power_enable_options enable_mem_low_power;
 921	union root_clock_optimization_options root_clock_optimization;
 922	union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating;
 923	bool hpo_optimization;
 924	bool force_vblank_alignment;
 925
 926	/* Enable dmub aux for legacy ddc */
 927	bool enable_dmub_aux_for_legacy_ddc;
 928	bool disable_fams;
 929	bool disable_fams_gaming;
 930	/* FEC/PSR1 sequence enable delay in 100us */
 931	uint8_t fec_enable_delay_in100us;
 932	bool enable_driver_sequence_debug;
 933	enum det_size crb_alloc_policy;
 934	int crb_alloc_policy_min_disp_count;
 935	bool disable_z10;
 936	bool enable_z9_disable_interface;
 937	bool psr_skip_crtc_disable;
 938	union dpia_debug_options dpia_debug;
 939	bool disable_fixed_vs_aux_timeout_wa;
 940	uint32_t fixed_vs_aux_delay_config_wa;
 941	bool force_disable_subvp;
 942	bool force_subvp_mclk_switch;
 943	bool allow_sw_cursor_fallback;
 944	unsigned int force_subvp_num_ways;
 945	unsigned int force_mall_ss_num_ways;
 946	bool alloc_extra_way_for_cursor;
 947	uint32_t subvp_extra_lines;
 948	bool force_usr_allow;
 949	/* uses value at boot and disables switch */
 950	bool disable_dtb_ref_clk_switch;
 951	bool extended_blank_optimization;
 952	union aux_wake_wa_options aux_wake_wa;
 953	uint32_t mst_start_top_delay;
 954	uint8_t psr_power_use_phy_fsm;
 955	enum dml_hostvm_override_opts dml_hostvm_override;
 956	bool dml_disallow_alternate_prefetch_modes;
 957	bool use_legacy_soc_bb_mechanism;
 958	bool exit_idle_opt_for_cursor_updates;
 959	bool using_dml2;
 960	bool enable_single_display_2to1_odm_policy;
 961	bool enable_double_buffered_dsc_pg_support;
 962	bool enable_dp_dig_pixel_rate_div_policy;
 963	enum lttpr_mode lttpr_mode_override;
 964	unsigned int dsc_delay_factor_wa_x1000;
 965	unsigned int min_prefetch_in_strobe_ns;
 966	bool disable_unbounded_requesting;
 967	bool dig_fifo_off_in_blank;
 968	bool override_dispclk_programming;
 969	bool otg_crc_db;
 970	bool disallow_dispclk_dppclk_ds;
 971	bool disable_fpo_optimizations;
 972	bool support_eDP1_5;
 973	uint32_t fpo_vactive_margin_us;
 974	bool disable_fpo_vactive;
 975	bool disable_boot_optimizations;
 976	bool override_odm_optimization;
 977	bool minimize_dispclk_using_odm;
 978	bool disable_subvp_high_refresh;
 979	bool disable_dp_plus_plus_wa;
 980	uint32_t fpo_vactive_min_active_margin_us;
 981	uint32_t fpo_vactive_max_blank_us;
 982	bool enable_hpo_pg_support;
 983	bool enable_legacy_fast_update;
 984	bool disable_dc_mode_overwrite;
 985	bool replay_skip_crtc_disabled;
 986	bool ignore_pg;/*do nothing, let pmfw control it*/
 987	bool psp_disabled_wa;
 988	unsigned int ips2_eval_delay_us;
 989	unsigned int ips2_entry_delay_us;
 990	bool disable_dmub_reallow_idle;
 991	bool disable_timeout;
 992	bool disable_extblankadj;
 993	unsigned int static_screen_wait_frames;
 994	bool force_chroma_subsampling_1tap;
 995};
 996
 997struct gpu_info_soc_bounding_box_v1_0;
 998
 999/* Generic structure that can be used to query properties of DC. More fields
1000 * can be added as required.
1001 */
1002struct dc_current_properties {
1003	unsigned int cursor_size_limit;
1004};
1005
1006struct dc {
1007	struct dc_debug_options debug;
1008	struct dc_versions versions;
1009	struct dc_caps caps;
1010	struct dc_cap_funcs cap_funcs;
1011	struct dc_config config;
1012	struct dc_bounding_box_overrides bb_overrides;
1013	struct dc_bug_wa work_arounds;
1014	struct dc_context *ctx;
1015	struct dc_phy_addr_space_config vm_pa_config;
1016
1017	uint8_t link_count;
1018	struct dc_link *links[MAX_PIPES * 2];
1019	struct link_service *link_srv;
1020
1021	struct dc_state *current_state;
1022	struct resource_pool *res_pool;
1023
1024	struct clk_mgr *clk_mgr;
1025
1026	/* Display Engine Clock levels */
1027	struct dm_pp_clock_levels sclk_lvls;
1028
1029	/* Inputs into BW and WM calculations. */
1030	struct bw_calcs_dceip *bw_dceip;
1031	struct bw_calcs_vbios *bw_vbios;
1032	struct dcn_soc_bounding_box *dcn_soc;
1033	struct dcn_ip_params *dcn_ip;
1034	struct display_mode_lib dml;
1035
1036	/* HW functions */
1037	struct hw_sequencer_funcs hwss;
1038	struct dce_hwseq *hwseq;
1039
1040	/* Require to optimize clocks and bandwidth for added/removed planes */
1041	bool optimized_required;
1042	bool wm_optimized_required;
1043	bool idle_optimizations_allowed;
1044	bool enable_c20_dtm_b0;
1045
1046	/* Require to maintain clocks and bandwidth for UEFI enabled HW */
1047
1048	/* FBC compressor */
1049	struct compressor *fbc_compressor;
1050
1051	struct dc_debug_data debug_data;
1052	struct dpcd_vendor_signature vendor_signature;
1053
1054	const char *build_id;
1055	struct vm_helper *vm_helper;
1056
1057	uint32_t *dcn_reg_offsets;
1058	uint32_t *nbio_reg_offsets;
1059	uint32_t *clk_reg_offsets;
1060
1061	/* Scratch memory */
1062	struct {
1063		struct {
1064			/*
1065			 * For matching clock_limits table in driver with table
1066			 * from PMFW.
1067			 */
1068			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1069		} update_bw_bounding_box;
1070	} scratch;
1071
1072	struct dml2_configuration_options dml2_options;
1073	enum dc_acpi_cm_power_state power_state;
1074};
1075
1076enum frame_buffer_mode {
1077	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
1078	FRAME_BUFFER_MODE_ZFB_ONLY,
1079	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
1080} ;
1081
1082struct dchub_init_data {
1083	int64_t zfb_phys_addr_base;
1084	int64_t zfb_mc_base_addr;
1085	uint64_t zfb_size_in_byte;
1086	enum frame_buffer_mode fb_mode;
1087	bool dchub_initialzied;
1088	bool dchub_info_valid;
1089};
1090
1091struct dc_init_data {
1092	struct hw_asic_id asic_id;
1093	void *driver; /* ctx */
1094	struct cgs_device *cgs_device;
1095	struct dc_bounding_box_overrides bb_overrides;
1096
1097	int num_virtual_links;
1098	/*
1099	 * If 'vbios_override' not NULL, it will be called instead
1100	 * of the real VBIOS. Intended use is Diagnostics on FPGA.
1101	 */
1102	struct dc_bios *vbios_override;
1103	enum dce_environment dce_environment;
1104
1105	struct dmub_offload_funcs *dmub_if;
1106	struct dc_reg_helper_state *dmub_offload;
1107
1108	struct dc_config flags;
1109	uint64_t log_mask;
1110
1111	struct dpcd_vendor_signature vendor_signature;
1112	bool force_smu_not_present;
1113	/*
1114	 * IP offset for run time initializaion of register addresses
1115	 *
1116	 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
1117	 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
1118	 * before them.
1119	 */
1120	uint32_t *dcn_reg_offsets;
1121	uint32_t *nbio_reg_offsets;
1122	uint32_t *clk_reg_offsets;
1123};
1124
1125struct dc_callback_init {
1126	struct cp_psp cp_psp;
1127};
1128
1129struct dc *dc_create(const struct dc_init_data *init_params);
1130void dc_hardware_init(struct dc *dc);
1131
1132int dc_get_vmid_use_vector(struct dc *dc);
1133void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1134/* Returns the number of vmids supported */
1135int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1136void dc_init_callbacks(struct dc *dc,
1137		const struct dc_callback_init *init_params);
1138void dc_deinit_callbacks(struct dc *dc);
1139void dc_destroy(struct dc **dc);
1140
1141/* Surface Interfaces */
1142
1143enum {
1144	TRANSFER_FUNC_POINTS = 1025
1145};
1146
1147struct dc_hdr_static_metadata {
1148	/* display chromaticities and white point in units of 0.00001 */
1149	unsigned int chromaticity_green_x;
1150	unsigned int chromaticity_green_y;
1151	unsigned int chromaticity_blue_x;
1152	unsigned int chromaticity_blue_y;
1153	unsigned int chromaticity_red_x;
1154	unsigned int chromaticity_red_y;
1155	unsigned int chromaticity_white_point_x;
1156	unsigned int chromaticity_white_point_y;
1157
1158	uint32_t min_luminance;
1159	uint32_t max_luminance;
1160	uint32_t maximum_content_light_level;
1161	uint32_t maximum_frame_average_light_level;
1162};
1163
1164enum dc_transfer_func_type {
1165	TF_TYPE_PREDEFINED,
1166	TF_TYPE_DISTRIBUTED_POINTS,
1167	TF_TYPE_BYPASS,
1168	TF_TYPE_HWPWL
1169};
1170
1171struct dc_transfer_func_distributed_points {
1172	struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1173	struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1174	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1175
1176	uint16_t end_exponent;
1177	uint16_t x_point_at_y1_red;
1178	uint16_t x_point_at_y1_green;
1179	uint16_t x_point_at_y1_blue;
1180};
1181
1182enum dc_transfer_func_predefined {
1183	TRANSFER_FUNCTION_SRGB,
1184	TRANSFER_FUNCTION_BT709,
1185	TRANSFER_FUNCTION_PQ,
1186	TRANSFER_FUNCTION_LINEAR,
1187	TRANSFER_FUNCTION_UNITY,
1188	TRANSFER_FUNCTION_HLG,
1189	TRANSFER_FUNCTION_HLG12,
1190	TRANSFER_FUNCTION_GAMMA22,
1191	TRANSFER_FUNCTION_GAMMA24,
1192	TRANSFER_FUNCTION_GAMMA26
1193};
1194
1195
1196struct dc_transfer_func {
1197	struct kref refcount;
1198	enum dc_transfer_func_type type;
1199	enum dc_transfer_func_predefined tf;
1200	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1201	uint32_t sdr_ref_white_level;
1202	union {
1203		struct pwl_params pwl;
1204		struct dc_transfer_func_distributed_points tf_pts;
1205	};
1206};
1207
1208
1209union dc_3dlut_state {
1210	struct {
1211		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */
1212		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/
1213		uint32_t rmu_mux_num:3;		/*index of mux to use*/
1214		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1215		uint32_t mpc_rmu1_mux:4;
1216		uint32_t mpc_rmu2_mux:4;
1217		uint32_t reserved:15;
1218	} bits;
1219	uint32_t raw;
1220};
1221
1222
1223struct dc_3dlut {
1224	struct kref refcount;
1225	struct tetrahedral_params lut_3d;
1226	struct fixed31_32 hdr_multiplier;
1227	union dc_3dlut_state state;
1228};
1229/*
1230 * This structure is filled in by dc_surface_get_status and contains
1231 * the last requested address and the currently active address so the called
1232 * can determine if there are any outstanding flips
1233 */
1234struct dc_plane_status {
1235	struct dc_plane_address requested_address;
1236	struct dc_plane_address current_address;
1237	bool is_flip_pending;
1238	bool is_right_eye;
1239};
1240
1241union surface_update_flags {
1242
1243	struct {
1244		uint32_t addr_update:1;
1245		/* Medium updates */
1246		uint32_t dcc_change:1;
1247		uint32_t color_space_change:1;
1248		uint32_t horizontal_mirror_change:1;
1249		uint32_t per_pixel_alpha_change:1;
1250		uint32_t global_alpha_change:1;
1251		uint32_t hdr_mult:1;
1252		uint32_t rotation_change:1;
1253		uint32_t swizzle_change:1;
1254		uint32_t scaling_change:1;
1255		uint32_t clip_size_change: 1;
1256		uint32_t position_change:1;
1257		uint32_t in_transfer_func_change:1;
1258		uint32_t input_csc_change:1;
1259		uint32_t coeff_reduction_change:1;
1260		uint32_t output_tf_change:1;
1261		uint32_t pixel_format_change:1;
1262		uint32_t plane_size_change:1;
1263		uint32_t gamut_remap_change:1;
1264
1265		/* Full updates */
1266		uint32_t new_plane:1;
1267		uint32_t bpp_change:1;
1268		uint32_t gamma_change:1;
1269		uint32_t bandwidth_change:1;
1270		uint32_t clock_change:1;
1271		uint32_t stereo_format_change:1;
1272		uint32_t lut_3d:1;
1273		uint32_t tmz_changed:1;
1274		uint32_t full_update:1;
1275	} bits;
1276
1277	uint32_t raw;
1278};
1279
1280struct dc_plane_state {
1281	struct dc_plane_address address;
1282	struct dc_plane_flip_time time;
1283	bool triplebuffer_flips;
1284	struct scaling_taps scaling_quality;
1285	struct rect src_rect;
1286	struct rect dst_rect;
1287	struct rect clip_rect;
1288
1289	struct plane_size plane_size;
1290	union dc_tiling_info tiling_info;
1291
1292	struct dc_plane_dcc_param dcc;
1293
1294	struct dc_gamma *gamma_correction;
1295	struct dc_transfer_func *in_transfer_func;
1296	struct dc_bias_and_scale *bias_and_scale;
1297	struct dc_csc_transform input_csc_color_matrix;
1298	struct fixed31_32 coeff_reduction_factor;
1299	struct fixed31_32 hdr_mult;
1300	struct colorspace_transform gamut_remap_matrix;
1301
1302	// TODO: No longer used, remove
1303	struct dc_hdr_static_metadata hdr_static_ctx;
1304
1305	enum dc_color_space color_space;
1306
1307	struct dc_3dlut *lut3d_func;
1308	struct dc_transfer_func *in_shaper_func;
1309	struct dc_transfer_func *blend_tf;
1310
1311	struct dc_transfer_func *gamcor_tf;
1312	enum surface_pixel_format format;
1313	enum dc_rotation_angle rotation;
1314	enum plane_stereo_format stereo_format;
1315
1316	bool is_tiling_rotated;
1317	bool per_pixel_alpha;
1318	bool pre_multiplied_alpha;
1319	bool global_alpha;
1320	int  global_alpha_value;
1321	bool visible;
1322	bool flip_immediate;
1323	bool horizontal_mirror;
1324	int layer_index;
1325
1326	union surface_update_flags update_flags;
1327	bool flip_int_enabled;
1328	bool skip_manual_trigger;
1329
1330	/* private to DC core */
1331	struct dc_plane_status status;
1332	struct dc_context *ctx;
1333
1334	/* HACK: Workaround for forcing full reprogramming under some conditions */
1335	bool force_full_update;
1336
1337	bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1338
1339	/* private to dc_surface.c */
1340	enum dc_irq_source irq_source;
1341	struct kref refcount;
1342	struct tg_color visual_confirm_color;
1343
1344	bool is_statically_allocated;
1345};
1346
1347struct dc_plane_info {
1348	struct plane_size plane_size;
1349	union dc_tiling_info tiling_info;
1350	struct dc_plane_dcc_param dcc;
1351	enum surface_pixel_format format;
1352	enum dc_rotation_angle rotation;
1353	enum plane_stereo_format stereo_format;
1354	enum dc_color_space color_space;
1355	bool horizontal_mirror;
1356	bool visible;
1357	bool per_pixel_alpha;
1358	bool pre_multiplied_alpha;
1359	bool global_alpha;
1360	int  global_alpha_value;
1361	bool input_csc_enabled;
1362	int layer_index;
1363};
1364
1365struct dc_scaling_info {
1366	struct rect src_rect;
1367	struct rect dst_rect;
1368	struct rect clip_rect;
1369	struct scaling_taps scaling_quality;
1370};
1371
1372struct dc_fast_update {
1373	const struct dc_flip_addrs *flip_addr;
1374	const struct dc_gamma *gamma;
1375	const struct colorspace_transform *gamut_remap_matrix;
1376	const struct dc_csc_transform *input_csc_color_matrix;
1377	const struct fixed31_32 *coeff_reduction_factor;
1378	struct dc_transfer_func *out_transfer_func;
1379	struct dc_csc_transform *output_csc_transform;
1380};
1381
1382struct dc_surface_update {
1383	struct dc_plane_state *surface;
1384
1385	/* isr safe update parameters.  null means no updates */
1386	const struct dc_flip_addrs *flip_addr;
1387	const struct dc_plane_info *plane_info;
1388	const struct dc_scaling_info *scaling_info;
1389	struct fixed31_32 hdr_mult;
1390	/* following updates require alloc/sleep/spin that is not isr safe,
1391	 * null means no updates
1392	 */
1393	const struct dc_gamma *gamma;
1394	const struct dc_transfer_func *in_transfer_func;
1395
1396	const struct dc_csc_transform *input_csc_color_matrix;
1397	const struct fixed31_32 *coeff_reduction_factor;
1398	const struct dc_transfer_func *func_shaper;
1399	const struct dc_3dlut *lut3d_func;
1400	const struct dc_transfer_func *blend_tf;
1401	const struct colorspace_transform *gamut_remap_matrix;
1402};
1403
1404/*
1405 * Create a new surface with default parameters;
1406 */
1407void dc_gamma_retain(struct dc_gamma *dc_gamma);
1408void dc_gamma_release(struct dc_gamma **dc_gamma);
1409struct dc_gamma *dc_create_gamma(void);
1410
1411void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1412void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1413struct dc_transfer_func *dc_create_transfer_func(void);
1414
1415struct dc_3dlut *dc_create_3dlut_func(void);
1416void dc_3dlut_func_release(struct dc_3dlut *lut);
1417void dc_3dlut_func_retain(struct dc_3dlut *lut);
1418
1419void dc_post_update_surfaces_to_stream(
1420		struct dc *dc);
1421
1422#include "dc_stream.h"
1423
1424/**
1425 * struct dc_validation_set - Struct to store surface/stream associations for validation
1426 */
1427struct dc_validation_set {
1428	/**
1429	 * @stream: Stream state properties
1430	 */
1431	struct dc_stream_state *stream;
1432
1433	/**
1434	 * @plane_states: Surface state
1435	 */
1436	struct dc_plane_state *plane_states[MAX_SURFACES];
1437
1438	/**
1439	 * @plane_count: Total of active planes
1440	 */
1441	uint8_t plane_count;
1442};
1443
1444bool dc_validate_boot_timing(const struct dc *dc,
1445				const struct dc_sink *sink,
1446				struct dc_crtc_timing *crtc_timing);
1447
1448enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1449
1450void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1451
1452enum dc_status dc_validate_with_context(struct dc *dc,
1453					const struct dc_validation_set set[],
1454					int set_count,
1455					struct dc_state *context,
1456					bool fast_validate);
1457
1458bool dc_set_generic_gpio_for_stereo(bool enable,
1459		struct gpio_service *gpio_service);
1460
1461/*
1462 * fast_validate: we return after determining if we can support the new state,
1463 * but before we populate the programming info
1464 */
1465enum dc_status dc_validate_global_state(
1466		struct dc *dc,
1467		struct dc_state *new_ctx,
1468		bool fast_validate);
1469
1470bool dc_acquire_release_mpc_3dlut(
1471		struct dc *dc, bool acquire,
1472		struct dc_stream_state *stream,
1473		struct dc_3dlut **lut,
1474		struct dc_transfer_func **shaper);
1475
1476bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1477void get_audio_check(struct audio_info *aud_modes,
1478	struct audio_check *aud_chk);
1479
1480enum dc_status dc_commit_streams(struct dc *dc,
1481				 struct dc_stream_state *streams[],
1482				 uint8_t stream_count);
1483
1484
1485struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1486		struct dc_stream_state *stream,
1487		int mpcc_inst);
1488
1489
1490uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1491
1492void dc_set_disable_128b_132b_stream_overhead(bool disable);
1493
1494/* The function returns minimum bandwidth required to drive a given timing
1495 * return - minimum required timing bandwidth in kbps.
1496 */
1497uint32_t dc_bandwidth_in_kbps_from_timing(
1498		const struct dc_crtc_timing *timing,
1499		const enum dc_link_encoding_format link_encoding);
1500
1501/* Link Interfaces */
1502/*
1503 * A link contains one or more sinks and their connected status.
1504 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1505 */
1506struct dc_link {
1507	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1508	unsigned int sink_count;
1509	struct dc_sink *local_sink;
1510	unsigned int link_index;
1511	enum dc_connection_type type;
1512	enum signal_type connector_signal;
1513	enum dc_irq_source irq_source_hpd;
1514	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
1515
1516	bool is_hpd_filter_disabled;
1517	bool dp_ss_off;
1518
1519	/**
1520	 * @link_state_valid:
1521	 *
1522	 * If there is no link and local sink, this variable should be set to
1523	 * false. Otherwise, it should be set to true; usually, the function
1524	 * core_link_enable_stream sets this field to true.
1525	 */
1526	bool link_state_valid;
1527	bool aux_access_disabled;
1528	bool sync_lt_in_progress;
1529	bool skip_stream_reenable;
1530	bool is_internal_display;
1531	/** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1532	bool is_dig_mapping_flexible;
1533	bool hpd_status; /* HPD status of link without physical HPD pin. */
1534	bool is_hpd_pending; /* Indicates a new received hpd */
1535
1536	/* USB4 DPIA links skip verifying link cap, instead performing the fallback method
1537	 * for every link training. This is incompatible with DP LL compliance automation,
1538	 * which expects the same link settings to be used every retry on a link loss.
1539	 * This flag is used to skip the fallback when link loss occurs during automation.
1540	 */
1541	bool skip_fallback_on_link_loss;
1542
1543	bool edp_sink_present;
1544
1545	struct dp_trace dp_trace;
1546
1547	/* caps is the same as reported_link_cap. link_traing use
1548	 * reported_link_cap. Will clean up.  TODO
1549	 */
1550	struct dc_link_settings reported_link_cap;
1551	struct dc_link_settings verified_link_cap;
1552	struct dc_link_settings cur_link_settings;
1553	struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1554	struct dc_link_settings preferred_link_setting;
1555	/* preferred_training_settings are override values that
1556	 * come from DM. DM is responsible for the memory
1557	 * management of the override pointers.
1558	 */
1559	struct dc_link_training_overrides preferred_training_settings;
1560	struct dp_audio_test_data audio_test_data;
1561
1562	uint8_t ddc_hw_inst;
1563
1564	uint8_t hpd_src;
1565
1566	uint8_t link_enc_hw_inst;
1567	/* DIG link encoder ID. Used as index in link encoder resource pool.
1568	 * For links with fixed mapping to DIG, this is not changed after dc_link
1569	 * object creation.
1570	 */
1571	enum engine_id eng_id;
1572	enum engine_id dpia_preferred_eng_id;
1573
1574	bool test_pattern_enabled;
1575	/* Pending/Current test pattern are only used to perform and track
1576	 * FIXED_VS retimer test pattern/lane adjustment override state.
1577	 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1578	 * to perform specific lane adjust overrides before setting certain
1579	 * PHY test patterns. In cases when lane adjust and set test pattern
1580	 * calls are not performed atomically (i.e. performing link training),
1581	 * pending_test_pattern will be invalid or contain a non-PHY test pattern
1582	 * and current_test_pattern will contain required context for any future
1583	 * set pattern/set lane adjust to transition between override state(s).
1584	 * */
1585	enum dp_test_pattern current_test_pattern;
1586	enum dp_test_pattern pending_test_pattern;
1587
1588	union compliance_test_state compliance_test_state;
1589
1590	void *priv;
1591
1592	struct ddc_service *ddc;
1593
1594	enum dp_panel_mode panel_mode;
1595	bool aux_mode;
1596
1597	/* Private to DC core */
1598
1599	const struct dc *dc;
1600
1601	struct dc_context *ctx;
1602
1603	struct panel_cntl *panel_cntl;
1604	struct link_encoder *link_enc;
1605	struct graphics_object_id link_id;
1606	/* Endpoint type distinguishes display endpoints which do not have entries
1607	 * in the BIOS connector table from those that do. Helps when tracking link
1608	 * encoder to display endpoint assignments.
1609	 */
1610	enum display_endpoint_type ep_type;
1611	union ddi_channel_mapping ddi_channel_mapping;
1612	struct connector_device_tag_info device_tag;
1613	struct dpcd_caps dpcd_caps;
1614	uint32_t dongle_max_pix_clk;
1615	unsigned short chip_caps;
1616	unsigned int dpcd_sink_count;
1617	struct hdcp_caps hdcp_caps;
1618	enum edp_revision edp_revision;
1619	union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1620
1621	struct psr_settings psr_settings;
1622
1623	struct replay_settings replay_settings;
1624
1625	/* Drive settings read from integrated info table */
1626	struct dc_lane_settings bios_forced_drive_settings;
1627
1628	/* Vendor specific LTTPR workaround variables */
1629	uint8_t vendor_specific_lttpr_link_rate_wa;
1630	bool apply_vendor_specific_lttpr_link_rate_wa;
1631
1632	/* MST record stream using this link */
1633	struct link_flags {
1634		bool dp_keep_receiver_powered;
1635		bool dp_skip_DID2;
1636		bool dp_skip_reset_segment;
1637		bool dp_skip_fs_144hz;
1638		bool dp_mot_reset_segment;
1639		/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1640		bool dpia_mst_dsc_always_on;
1641		/* Forced DPIA into TBT3 compatibility mode. */
1642		bool dpia_forced_tbt3_mode;
1643		bool dongle_mode_timing_override;
1644		bool blank_stream_on_ocs_change;
1645		bool read_dpcd204h_on_irq_hpd;
1646	} wa_flags;
1647	struct link_mst_stream_allocation_table mst_stream_alloc_table;
1648
1649	struct dc_link_status link_status;
1650	struct dprx_states dprx_states;
1651
1652	struct gpio *hpd_gpio;
1653	enum dc_link_fec_state fec_state;
1654	bool link_powered_externally;	// Used to bypass hardware sequencing delays when panel is powered down forcibly
1655
1656	struct dc_panel_config panel_config;
1657	struct phy_state phy_state;
1658	// BW ALLOCATON USB4 ONLY
1659	struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1660	bool skip_implict_edp_power_control;
1661};
1662
1663/* Return an enumerated dc_link.
1664 * dc_link order is constant and determined at
1665 * boot time.  They cannot be created or destroyed.
1666 * Use dc_get_caps() to get number of links.
1667 */
1668struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1669
1670/* Return instance id of the edp link. Inst 0 is primary edp link. */
1671bool dc_get_edp_link_panel_inst(const struct dc *dc,
1672		const struct dc_link *link,
1673		unsigned int *inst_out);
1674
1675/* Return an array of link pointers to edp links. */
1676void dc_get_edp_links(const struct dc *dc,
1677		struct dc_link **edp_links,
1678		int *edp_num);
1679
1680void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1681				 bool powerOn);
1682
1683/* The function initiates detection handshake over the given link. It first
1684 * determines if there are display connections over the link. If so it initiates
1685 * detection protocols supported by the connected receiver device. The function
1686 * contains protocol specific handshake sequences which are sometimes mandatory
1687 * to establish a proper connection between TX and RX. So it is always
1688 * recommended to call this function as the first link operation upon HPD event
1689 * or power up event. Upon completion, the function will update link structure
1690 * in place based on latest RX capabilities. The function may also cause dpms
1691 * to be reset to off for all currently enabled streams to the link. It is DM's
1692 * responsibility to serialize detection and DPMS updates.
1693 *
1694 * @reason - Indicate which event triggers this detection. dc may customize
1695 * detection flow depending on the triggering events.
1696 * return false - if detection is not fully completed. This could happen when
1697 * there is an unrecoverable error during detection or detection is partially
1698 * completed (detection has been delegated to dm mst manager ie.
1699 * link->connection_type == dc_connection_mst_branch when returning false).
1700 * return true - detection is completed, link has been fully updated with latest
1701 * detection result.
1702 */
1703bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
1704
1705struct dc_sink_init_data;
1706
1707/* When link connection type is dc_connection_mst_branch, remote sink can be
1708 * added to the link. The interface creates a remote sink and associates it with
1709 * current link. The sink will be retained by link until remove remote sink is
1710 * called.
1711 *
1712 * @dc_link - link the remote sink will be added to.
1713 * @edid - byte array of EDID raw data.
1714 * @len - size of the edid in byte
1715 * @init_data -
1716 */
1717struct dc_sink *dc_link_add_remote_sink(
1718		struct dc_link *dc_link,
1719		const uint8_t *edid,
1720		int len,
1721		struct dc_sink_init_data *init_data);
1722
1723/* Remove remote sink from a link with dc_connection_mst_branch connection type.
1724 * @link - link the sink should be removed from
1725 * @sink - sink to be removed.
1726 */
1727void dc_link_remove_remote_sink(
1728	struct dc_link *link,
1729	struct dc_sink *sink);
1730
1731/* Enable HPD interrupt handler for a given link */
1732void dc_link_enable_hpd(const struct dc_link *link);
1733
1734/* Disable HPD interrupt handler for a given link */
1735void dc_link_disable_hpd(const struct dc_link *link);
1736
1737/* determine if there is a sink connected to the link
1738 *
1739 * @type - dc_connection_single if connected, dc_connection_none otherwise.
1740 * return - false if an unexpected error occurs, true otherwise.
1741 *
1742 * NOTE: This function doesn't detect downstream sink connections i.e
1743 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
1744 * return dc_connection_single if the branch device is connected despite of
1745 * downstream sink's connection status.
1746 */
1747bool dc_link_detect_connection_type(struct dc_link *link,
1748		enum dc_connection_type *type);
1749
1750/* query current hpd pin value
1751 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1752 *
1753 */
1754bool dc_link_get_hpd_state(struct dc_link *link);
1755
1756/* Getter for cached link status from given link */
1757const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
1758
1759/* enable/disable hardware HPD filter.
1760 *
1761 * @link - The link the HPD pin is associated with.
1762 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1763 * handler once after no HPD change has been detected within dc default HPD
1764 * filtering interval since last HPD event. i.e if display keeps toggling hpd
1765 * pulses within default HPD interval, no HPD event will be received until HPD
1766 * toggles have stopped. Then HPD event will be queued to irq handler once after
1767 * dc default HPD filtering interval since last HPD event.
1768 *
1769 * @enable = false - disable hardware HPD filter. HPD event will be queued
1770 * immediately to irq handler after no HPD change has been detected within
1771 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
1772 */
1773void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
1774
1775/* submit i2c read/write payloads through ddc channel
1776 * @link_index - index to a link with ddc in i2c mode
1777 * @cmd - i2c command structure
1778 * return - true if success, false otherwise.
1779 */
1780bool dc_submit_i2c(
1781		struct dc *dc,
1782		uint32_t link_index,
1783		struct i2c_command *cmd);
1784
1785/* submit i2c read/write payloads through oem channel
1786 * @link_index - index to a link with ddc in i2c mode
1787 * @cmd - i2c command structure
1788 * return - true if success, false otherwise.
1789 */
1790bool dc_submit_i2c_oem(
1791		struct dc *dc,
1792		struct i2c_command *cmd);
1793
1794enum aux_return_code_type;
1795/* Attempt to transfer the given aux payload. This function does not perform
1796 * retries or handle error states. The reply is returned in the payload->reply
1797 * and the result through operation_result. Returns the number of bytes
1798 * transferred,or -1 on a failure.
1799 */
1800int dc_link_aux_transfer_raw(struct ddc_service *ddc,
1801		struct aux_payload *payload,
1802		enum aux_return_code_type *operation_result);
1803
1804bool dc_is_oem_i2c_device_present(
1805	struct dc *dc,
1806	size_t slave_address
1807);
1808
1809/* return true if the connected receiver supports the hdcp version */
1810bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1811bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1812
1813/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
1814 *
1815 * TODO - When defer_handling is true the function will have a different purpose.
1816 * It no longer does complete hpd rx irq handling. We should create a separate
1817 * interface specifically for this case.
1818 *
1819 * Return:
1820 * true - Downstream port status changed. DM should call DC to do the
1821 * detection.
1822 * false - no change in Downstream port status. No further action required
1823 * from DM.
1824 */
1825bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
1826		union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
1827		bool defer_handling, bool *has_left_work);
1828/* handle DP specs define test automation sequence*/
1829void dc_link_dp_handle_automated_test(struct dc_link *link);
1830
1831/* handle DP Link loss sequence and try to recover RX link loss with best
1832 * effort
1833 */
1834void dc_link_dp_handle_link_loss(struct dc_link *link);
1835
1836/* Determine if hpd rx irq should be handled or ignored
1837 * return true - hpd rx irq should be handled.
1838 * return false - it is safe to ignore hpd rx irq event
1839 */
1840bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
1841
1842/* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
1843 * @link - link the hpd irq data associated with
1844 * @hpd_irq_dpcd_data - input hpd irq data
1845 * return - true if hpd irq data indicates a link lost
1846 */
1847bool dc_link_check_link_loss_status(struct dc_link *link,
1848		union hpd_irq_data *hpd_irq_dpcd_data);
1849
1850/* Read hpd rx irq data from a given link
1851 * @link - link where the hpd irq data should be read from
1852 * @irq_data - output hpd irq data
1853 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1854 * read has failed.
1855 */
1856enum dc_status dc_link_dp_read_hpd_rx_irq_data(
1857	struct dc_link *link,
1858	union hpd_irq_data *irq_data);
1859
1860/* The function clears recorded DP RX states in the link. DM should call this
1861 * function when it is resuming from S3 power state to previously connected links.
1862 *
1863 * TODO - in the future we should consider to expand link resume interface to
1864 * support clearing previous rx states. So we don't have to rely on dm to call
1865 * this interface explicitly.
1866 */
1867void dc_link_clear_dprx_states(struct dc_link *link);
1868
1869/* Destruct the mst topology of the link and reset the allocated payload table
1870 *
1871 * NOTE: this should only be called if DM chooses not to call dc_link_detect but
1872 * still wants to reset MST topology on an unplug event */
1873bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
1874
1875/* The function calculates effective DP link bandwidth when a given link is
1876 * using the given link settings.
1877 *
1878 * return - total effective link bandwidth in kbps.
1879 */
1880uint32_t dc_link_bandwidth_kbps(
1881	const struct dc_link *link,
1882	const struct dc_link_settings *link_setting);
1883
1884/* The function takes a snapshot of current link resource allocation state
1885 * @dc: pointer to dc of the dm calling this
1886 * @map: a dc link resource snapshot defined internally to dc.
1887 *
1888 * DM needs to capture a snapshot of current link resource allocation mapping
1889 * and store it in its persistent storage.
1890 *
1891 * Some of the link resource is using first come first serve policy.
1892 * The allocation mapping depends on original hotplug order. This information
1893 * is lost after driver is loaded next time. The snapshot is used in order to
1894 * restore link resource to its previous state so user will get consistent
1895 * link capability allocation across reboot.
1896 *
1897 */
1898void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
1899
1900/* This function restores link resource allocation state from a snapshot
1901 * @dc: pointer to dc of the dm calling this
1902 * @map: a dc link resource snapshot defined internally to dc.
1903 *
1904 * DM needs to call this function after initial link detection on boot and
1905 * before first commit streams to restore link resource allocation state
1906 * from previous boot session.
1907 *
1908 * Some of the link resource is using first come first serve policy.
1909 * The allocation mapping depends on original hotplug order. This information
1910 * is lost after driver is loaded next time. The snapshot is used in order to
1911 * restore link resource to its previous state so user will get consistent
1912 * link capability allocation across reboot.
1913 *
1914 */
1915void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
1916
1917/* TODO: this is not meant to be exposed to DM. Should switch to stream update
1918 * interface i.e stream_update->dsc_config
1919 */
1920bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
1921
1922/* translate a raw link rate data to bandwidth in kbps */
1923uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
1924
1925/* determine the optimal bandwidth given link and required bw.
1926 * @link - current detected link
1927 * @req_bw - requested bandwidth in kbps
1928 * @link_settings - returned most optimal link settings that can fit the
1929 * requested bandwidth
1930 * return - false if link can't support requested bandwidth, true if link
1931 * settings is found.
1932 */
1933bool dc_link_decide_edp_link_settings(struct dc_link *link,
1934		struct dc_link_settings *link_settings,
1935		uint32_t req_bw);
1936
1937/* return the max dp link settings can be driven by the link without considering
1938 * connected RX device and its capability
1939 */
1940bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
1941		struct dc_link_settings *max_link_enc_cap);
1942
1943/* determine when the link is driving MST mode, what DP link channel coding
1944 * format will be used. The decision will remain unchanged until next HPD event.
1945 *
1946 * @link -  a link with DP RX connection
1947 * return - if stream is committed to this link with MST signal type, type of
1948 * channel coding format dc will choose.
1949 */
1950enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
1951		const struct dc_link *link);
1952
1953/* get max dp link settings the link can enable with all things considered. (i.e
1954 * TX/RX/Cable capabilities and dp override policies.
1955 *
1956 * @link - a link with DP RX connection
1957 * return - max dp link settings the link can enable.
1958 *
1959 */
1960const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
1961
1962/* Get the highest encoding format that the link supports; highest meaning the
1963 * encoding format which supports the maximum bandwidth.
1964 *
1965 * @link - a link with DP RX connection
1966 * return - highest encoding format link supports.
1967 */
1968enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);
1969
1970/* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
1971 * to a link with dp connector signal type.
1972 * @link - a link with dp connector signal type
1973 * return - true if connected, false otherwise
1974 */
1975bool dc_link_is_dp_sink_present(struct dc_link *link);
1976
1977/* Force DP lane settings update to main-link video signal and notify the change
1978 * to DP RX via DPCD. This is a debug interface used for video signal integrity
1979 * tuning purpose. The interface assumes link has already been enabled with DP
1980 * signal.
1981 *
1982 * @lt_settings - a container structure with desired hw_lane_settings
1983 */
1984void dc_link_set_drive_settings(struct dc *dc,
1985				struct link_training_settings *lt_settings,
1986				struct dc_link *link);
1987
1988/* Enable a test pattern in Link or PHY layer in an active link for compliance
1989 * test or debugging purpose. The test pattern will remain until next un-plug.
1990 *
1991 * @link - active link with DP signal output enabled.
1992 * @test_pattern - desired test pattern to output.
1993 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
1994 * @test_pattern_color_space - for video test pattern choose a desired color
1995 * space.
1996 * @p_link_settings - For PHY pattern choose a desired link settings
1997 * @p_custom_pattern - some test pattern will require a custom input to
1998 * customize some pattern details. Otherwise keep it to NULL.
1999 * @cust_pattern_size - size of the custom pattern input.
2000 *
2001 */
2002bool dc_link_dp_set_test_pattern(
2003	struct dc_link *link,
2004	enum dp_test_pattern test_pattern,
2005	enum dp_test_pattern_color_space test_pattern_color_space,
2006	const struct link_training_settings *p_link_settings,
2007	const unsigned char *p_custom_pattern,
2008	unsigned int cust_pattern_size);
2009
2010/* Force DP link settings to always use a specific value until reboot to a
2011 * specific link. If link has already been enabled, the interface will also
2012 * switch to desired link settings immediately. This is a debug interface to
2013 * generic dp issue trouble shooting.
2014 */
2015void dc_link_set_preferred_link_settings(struct dc *dc,
2016		struct dc_link_settings *link_setting,
2017		struct dc_link *link);
2018
2019/* Force DP link to customize a specific link training behavior by overriding to
2020 * standard DP specs defined protocol. This is a debug interface to trouble shoot
2021 * display specific link training issues or apply some display specific
2022 * workaround in link training.
2023 *
2024 * @link_settings - if not NULL, force preferred link settings to the link.
2025 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2026 * will apply this particular override in future link training. If NULL is
2027 * passed in, dc resets previous overrides.
2028 * NOTE: DM must keep the memory from override pointers until DM resets preferred
2029 * training settings.
2030 */
2031void dc_link_set_preferred_training_settings(struct dc *dc,
2032		struct dc_link_settings *link_setting,
2033		struct dc_link_training_overrides *lt_overrides,
2034		struct dc_link *link,
2035		bool skip_immediate_retrain);
2036
2037/* return - true if FEC is supported with connected DP RX, false otherwise */
2038bool dc_link_is_fec_supported(const struct dc_link *link);
2039
2040/* query FEC enablement policy to determine if FEC will be enabled by dc during
2041 * link enablement.
2042 * return - true if FEC should be enabled, false otherwise.
2043 */
2044bool dc_link_should_enable_fec(const struct dc_link *link);
2045
2046/* determine lttpr mode the current link should be enabled with a specific link
2047 * settings.
2048 */
2049enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
2050		struct dc_link_settings *link_setting);
2051
2052/* Force DP RX to update its power state.
2053 * NOTE: this interface doesn't update dp main-link. Calling this function will
2054 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2055 * RX power state back upon finish DM specific execution requiring DP RX in a
2056 * specific power state.
2057 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2058 * state.
2059 */
2060void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
2061
2062/* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2063 * current value read from extended receiver cap from 02200h - 0220Fh.
2064 * Some DP RX has problems of providing accurate DP receiver caps from extended
2065 * field, this interface is a workaround to revert link back to use base caps.
2066 */
2067void dc_link_overwrite_extended_receiver_cap(
2068		struct dc_link *link);
2069
2070void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
2071		bool wait_for_hpd);
2072
2073/* Set backlight level of an embedded panel (eDP, LVDS).
2074 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
2075 * and 16 bit fractional, where 1.0 is max backlight value.
2076 */
2077bool dc_link_set_backlight_level(const struct dc_link *dc_link,
2078		uint32_t backlight_pwm_u16_16,
2079		uint32_t frame_ramp);
2080
2081/* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2082bool dc_link_set_backlight_level_nits(struct dc_link *link,
2083		bool isHDR,
2084		uint32_t backlight_millinits,
2085		uint32_t transition_time_in_ms);
2086
2087bool dc_link_get_backlight_level_nits(struct dc_link *link,
2088		uint32_t *backlight_millinits,
2089		uint32_t *backlight_millinits_peak);
2090
2091int dc_link_get_backlight_level(const struct dc_link *dc_link);
2092
2093int dc_link_get_target_backlight_pwm(const struct dc_link *link);
2094
2095bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
2096		bool wait, bool force_static, const unsigned int *power_opts);
2097
2098bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
2099
2100bool dc_link_setup_psr(struct dc_link *dc_link,
2101		const struct dc_stream_state *stream, struct psr_config *psr_config,
2102		struct psr_context *psr_context);
2103
2104/*
2105 * Communicate with DMUB to allow or disallow Panel Replay on the specified link:
2106 *
2107 * @link: pointer to the dc_link struct instance
2108 * @enable: enable(active) or disable(inactive) replay
2109 * @wait: state transition need to wait the active set completed.
2110 * @force_static: force disable(inactive) the replay
2111 * @power_opts: set power optimazation parameters to DMUB.
2112 *
2113 * return: allow Replay active will return true, else will return false.
2114 */
2115bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
2116		bool wait, bool force_static, const unsigned int *power_opts);
2117
2118bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);
2119
2120/* On eDP links this function call will stall until T12 has elapsed.
2121 * If the panel is not in power off state, this function will return
2122 * immediately.
2123 */
2124bool dc_link_wait_for_t12(struct dc_link *link);
2125
2126/* Determine if dp trace has been initialized to reflect upto date result *
2127 * return - true if trace is initialized and has valid data. False dp trace
2128 * doesn't have valid result.
2129 */
2130bool dc_dp_trace_is_initialized(struct dc_link *link);
2131
2132/* Query a dp trace flag to indicate if the current dp trace data has been
2133 * logged before
2134 */
2135bool dc_dp_trace_is_logged(struct dc_link *link,
2136		bool in_detection);
2137
2138/* Set dp trace flag to indicate whether DM has already logged the current dp
2139 * trace data. DM can set is_logged to true upon logging and check
2140 * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
2141 */
2142void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
2143		bool in_detection,
2144		bool is_logged);
2145
2146/* Obtain driver time stamp for last dp link training end. The time stamp is
2147 * formatted based on dm_get_timestamp DM function.
2148 * @in_detection - true to get link training end time stamp of last link
2149 * training in detection sequence. false to get link training end time stamp
2150 * of last link training in commit (dpms) sequence
2151 */
2152unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
2153		bool in_detection);
2154
2155/* Get how many link training attempts dc has done with latest sequence.
2156 * @in_detection - true to get link training count of last link
2157 * training in detection sequence. false to get link training count of last link
2158 * training in commit (dpms) sequence
2159 */
2160const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
2161		bool in_detection);
2162
2163/* Get how many link loss has happened since last link training attempts */
2164unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
2165
2166/*
2167 *  USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
2168 */
2169/*
2170 * Send a request from DP-Tx requesting to allocate BW remotely after
2171 * allocating it locally. This will get processed by CM and a CB function
2172 * will be called.
2173 *
2174 * @link: pointer to the dc_link struct instance
2175 * @req_bw: The requested bw in Kbyte to allocated
2176 *
2177 * return: none
2178 */
2179void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
2180
2181/*
2182 * Handle function for when the status of the Request above is complete.
2183 * We will find out the result of allocating on CM and update structs.
2184 *
2185 * @link: pointer to the dc_link struct instance
2186 * @bw: Allocated or Estimated BW depending on the result
2187 * @result: Response type
2188 *
2189 * return: none
2190 */
2191void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,
2192		uint8_t bw, uint8_t result);
2193
2194/*
2195 * Handle the USB4 BW Allocation related functionality here:
2196 * Plug => Try to allocate max bw from timing parameters supported by the sink
2197 * Unplug => de-allocate bw
2198 *
2199 * @link: pointer to the dc_link struct instance
2200 * @peak_bw: Peak bw used by the link/sink
2201 *
2202 * return: allocated bw else return 0
2203 */
2204int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
2205		struct dc_link *link, int peak_bw);
2206
2207/*
2208 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2209 * available BW for each host router
2210 *
2211 * @dc: pointer to dc struct
2212 * @stream: pointer to all possible streams
2213 * @count: number of valid DPIA streams
2214 *
2215 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
2216 */
2217bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,
2218		const unsigned int count);
2219
2220/* Sink Interfaces - A sink corresponds to a display output device */
2221
2222struct dc_container_id {
2223	// 128bit GUID in binary form
2224	unsigned char  guid[16];
2225	// 8 byte port ID -> ELD.PortID
2226	unsigned int   portId[2];
2227	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2228	unsigned short manufacturerName;
2229	// 2 byte product code -> ELD.ProductCode
2230	unsigned short productCode;
2231};
2232
2233
2234struct dc_sink_dsc_caps {
2235	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2236	// 'false' if they are sink's DSC caps
2237	bool is_virtual_dpcd_dsc;
2238	// 'true' if MST topology supports DSC passthrough for sink
2239	// 'false' if MST topology does not support DSC passthrough
2240	bool is_dsc_passthrough_supported;
2241	struct dsc_dec_dpcd_caps dsc_dec_caps;
2242};
2243
2244struct dc_sink_fec_caps {
2245	bool is_rx_fec_supported;
2246	bool is_topology_fec_supported;
2247};
2248
2249struct scdc_caps {
2250	union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
2251	union hdmi_scdc_device_id_data device_id;
2252};
2253
2254/*
2255 * The sink structure contains EDID and other display device properties
2256 */
2257struct dc_sink {
2258	enum signal_type sink_signal;
2259	struct dc_edid dc_edid; /* raw edid */
2260	struct dc_edid_caps edid_caps; /* parse display caps */
2261	struct dc_container_id *dc_container_id;
2262	uint32_t dongle_max_pix_clk;
2263	void *priv;
2264	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
2265	bool converter_disable_audio;
2266
2267	struct scdc_caps scdc_caps;
2268	struct dc_sink_dsc_caps dsc_caps;
2269	struct dc_sink_fec_caps fec_caps;
2270
2271	bool is_vsc_sdp_colorimetry_supported;
2272
2273	/* private to DC core */
2274	struct dc_link *link;
2275	struct dc_context *ctx;
2276
2277	uint32_t sink_id;
2278
2279	/* private to dc_sink.c */
2280	// refcount must be the last member in dc_sink, since we want the
2281	// sink structure to be logically cloneable up to (but not including)
2282	// refcount
2283	struct kref refcount;
2284};
2285
2286void dc_sink_retain(struct dc_sink *sink);
2287void dc_sink_release(struct dc_sink *sink);
2288
2289struct dc_sink_init_data {
2290	enum signal_type sink_signal;
2291	struct dc_link *link;
2292	uint32_t dongle_max_pix_clk;
2293	bool converter_disable_audio;
2294};
2295
2296struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
2297
2298/* Newer interfaces  */
2299struct dc_cursor {
2300	struct dc_plane_address address;
2301	struct dc_cursor_attributes attributes;
2302};
2303
2304
2305/* Interrupt interfaces */
2306enum dc_irq_source dc_interrupt_to_irq_source(
2307		struct dc *dc,
2308		uint32_t src_id,
2309		uint32_t ext_id);
2310bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2311void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2312enum dc_irq_source dc_get_hpd_irq_source_at_index(
2313		struct dc *dc, uint32_t link_index);
2314
2315void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2316
2317/* Power Interfaces */
2318
2319void dc_set_power_state(
2320		struct dc *dc,
2321		enum dc_acpi_cm_power_state power_state);
2322void dc_resume(struct dc *dc);
2323
2324void dc_power_down_on_boot(struct dc *dc);
2325
2326/*
2327 * HDCP Interfaces
2328 */
2329enum hdcp_message_status dc_process_hdcp_msg(
2330		enum signal_type signal,
2331		struct dc_link *link,
2332		struct hdcp_protection_message *message_info);
2333bool dc_is_dmcu_initialized(struct dc *dc);
2334
2335enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
2336void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2337
2338bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
2339				struct dc_cursor_attributes *cursor_attr);
2340
2341void dc_allow_idle_optimizations(struct dc *dc, bool allow);
2342void dc_exit_ips_for_hw_access(struct dc *dc);
2343bool dc_dmub_is_ips_idle_state(struct dc *dc);
2344
2345/* set min and max memory clock to lowest and highest DPM level, respectively */
2346void dc_unlock_memory_clock_frequency(struct dc *dc);
2347
2348/* set min memory clock to the min required for current mode, max to maxDPM */
2349void dc_lock_memory_clock_frequency(struct dc *dc);
2350
2351/* set soft max for memclk, to be used for AC/DC switching clock limitations */
2352void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2353
2354/* cleanup on driver unload */
2355void dc_hardware_release(struct dc *dc);
2356
2357/* disables fw based mclk switch */
2358void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2359
2360bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2361
2362bool dc_set_replay_allow_active(struct dc *dc, bool active);
2363
2364void dc_z10_restore(const struct dc *dc);
2365void dc_z10_save_init(struct dc *dc);
2366
2367bool dc_is_dmub_outbox_supported(struct dc *dc);
2368bool dc_enable_dmub_notifications(struct dc *dc);
2369
2370bool dc_abm_save_restore(
2371		struct dc *dc,
2372		struct dc_stream_state *stream,
2373		struct abm_save_restore *pData);
2374
2375void dc_enable_dmub_outbox(struct dc *dc);
2376
2377bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2378				uint32_t link_index,
2379				struct aux_payload *payload);
2380
2381/* Get dc link index from dpia port index */
2382uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2383				uint8_t dpia_port_index);
2384
2385bool dc_process_dmub_set_config_async(struct dc *dc,
2386				uint32_t link_index,
2387				struct set_config_cmd_payload *payload,
2388				struct dmub_notification *notify);
2389
2390enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2391				uint32_t link_index,
2392				uint8_t mst_alloc_slots,
2393				uint8_t *mst_slots_in_use);
2394
2395void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2396				uint32_t hpd_int_enable);
2397
2398void dc_print_dmub_diagnostic_data(const struct dc *dc);
2399
2400void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2401
2402struct dc_power_profile {
2403	int power_level; /* Lower is better */
2404};
2405
2406struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);
2407
2408/* DSC Interfaces */
2409#include "dc_dsc.h"
2410
2411/* Disable acc mode Interfaces */
2412void dc_disable_accelerated_mode(struct dc *dc);
2413
2414bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
2415		       struct dc_stream_state *new_stream);
2416
2417#endif /* DC_INTERFACE_H_ */