1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *  ahci.c - AHCI SATA support
   4 *
   5 *  Maintained by:  Tejun Heo <tj@kernel.org>
   6 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
   7 *		    on emails.
   8 *
   9 *  Copyright 2004-2005 Red Hat, Inc.
  10 *
  11 * libata documentation is available via 'make {ps|pdf}docs',
  12 * as Documentation/driver-api/libata.rst
  13 *
  14 * AHCI hardware documentation:
  15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/module.h>
  21#include <linux/pci.h>
  22#include <linux/blkdev.h>
  23#include <linux/delay.h>
  24#include <linux/interrupt.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/device.h>
  27#include <linux/dmi.h>
  28#include <linux/gfp.h>
 
  29#include <scsi/scsi_host.h>
  30#include <scsi/scsi_cmnd.h>
  31#include <linux/libata.h>
  32#include <linux/ahci-remap.h>
  33#include <linux/io-64-nonatomic-lo-hi.h>
  34#include "ahci.h"
  35
  36#define DRV_NAME	"ahci"
  37#define DRV_VERSION	"3.0"
  38
  39enum {
  40	AHCI_PCI_BAR_STA2X11	= 0,
  41	AHCI_PCI_BAR_CAVIUM	= 0,
  42	AHCI_PCI_BAR_LOONGSON	= 0,
  43	AHCI_PCI_BAR_ENMOTUS	= 2,
  44	AHCI_PCI_BAR_CAVIUM_GEN5	= 4,
  45	AHCI_PCI_BAR_STANDARD	= 5,
  46};
  47
  48enum board_ids {
  49	/* board IDs by feature in alphabetical order */
  50	board_ahci,
  51	board_ahci_ign_iferr,
  52	board_ahci_low_power,
  53	board_ahci_no_debounce_delay,
  54	board_ahci_nomsi,
  55	board_ahci_noncq,
  56	board_ahci_nosntf,
  57	board_ahci_yes_fbs,
  58
  59	/* board IDs for specific chipsets in alphabetical order */
  60	board_ahci_al,
  61	board_ahci_avn,
  62	board_ahci_mcp65,
  63	board_ahci_mcp77,
  64	board_ahci_mcp89,
  65	board_ahci_mv,
  66	board_ahci_sb600,
  67	board_ahci_sb700,	/* for SB700 and SB800 */
  68	board_ahci_vt8251,
  69
  70	/*
  71	 * board IDs for Intel chipsets that support more than 6 ports
  72	 * *and* end up needing the PCS quirk.
  73	 */
  74	board_ahci_pcs7,
  75
  76	/* aliases */
  77	board_ahci_mcp_linux	= board_ahci_mcp65,
  78	board_ahci_mcp67	= board_ahci_mcp65,
  79	board_ahci_mcp73	= board_ahci_mcp65,
  80	board_ahci_mcp79	= board_ahci_mcp77,
  81};
  82
  83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  84static void ahci_remove_one(struct pci_dev *dev);
  85static void ahci_shutdown_one(struct pci_dev *dev);
  86static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
  87static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  88				 unsigned long deadline);
  89static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
  90			      unsigned long deadline);
  91static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
  92static bool is_mcp89_apple(struct pci_dev *pdev);
  93static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  94				unsigned long deadline);
  95#ifdef CONFIG_PM
  96static int ahci_pci_device_runtime_suspend(struct device *dev);
  97static int ahci_pci_device_runtime_resume(struct device *dev);
  98#ifdef CONFIG_PM_SLEEP
  99static int ahci_pci_device_suspend(struct device *dev);
 100static int ahci_pci_device_resume(struct device *dev);
 101#endif
 102#endif /* CONFIG_PM */
 103
 104static struct scsi_host_template ahci_sht = {
 105	AHCI_SHT("ahci"),
 106};
 107
 108static struct ata_port_operations ahci_vt8251_ops = {
 109	.inherits		= &ahci_ops,
 110	.hardreset		= ahci_vt8251_hardreset,
 111};
 112
 113static struct ata_port_operations ahci_p5wdh_ops = {
 114	.inherits		= &ahci_ops,
 115	.hardreset		= ahci_p5wdh_hardreset,
 116};
 117
 118static struct ata_port_operations ahci_avn_ops = {
 119	.inherits		= &ahci_ops,
 120	.hardreset		= ahci_avn_hardreset,
 121};
 122
 123static const struct ata_port_info ahci_port_info[] = {
 124	/* by features */
 125	[board_ahci] = {
 126		.flags		= AHCI_FLAG_COMMON,
 127		.pio_mask	= ATA_PIO4,
 128		.udma_mask	= ATA_UDMA6,
 129		.port_ops	= &ahci_ops,
 130	},
 131	[board_ahci_ign_iferr] = {
 132		AHCI_HFLAGS	(AHCI_HFLAG_IGN_IRQ_IF_ERR),
 133		.flags		= AHCI_FLAG_COMMON,
 134		.pio_mask	= ATA_PIO4,
 135		.udma_mask	= ATA_UDMA6,
 136		.port_ops	= &ahci_ops,
 137	},
 138	[board_ahci_low_power] = {
 139		AHCI_HFLAGS	(AHCI_HFLAG_USE_LPM_POLICY),
 140		.flags		= AHCI_FLAG_COMMON,
 141		.pio_mask	= ATA_PIO4,
 142		.udma_mask	= ATA_UDMA6,
 143		.port_ops	= &ahci_ops,
 144	},
 145	[board_ahci_no_debounce_delay] = {
 146		.flags		= AHCI_FLAG_COMMON,
 147		.link_flags	= ATA_LFLAG_NO_DEBOUNCE_DELAY,
 148		.pio_mask	= ATA_PIO4,
 149		.udma_mask	= ATA_UDMA6,
 150		.port_ops	= &ahci_ops,
 151	},
 152	[board_ahci_nomsi] = {
 153		AHCI_HFLAGS	(AHCI_HFLAG_NO_MSI),
 154		.flags		= AHCI_FLAG_COMMON,
 155		.pio_mask	= ATA_PIO4,
 156		.udma_mask	= ATA_UDMA6,
 157		.port_ops	= &ahci_ops,
 158	},
 159	[board_ahci_noncq] = {
 160		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ),
 161		.flags		= AHCI_FLAG_COMMON,
 162		.pio_mask	= ATA_PIO4,
 163		.udma_mask	= ATA_UDMA6,
 164		.port_ops	= &ahci_ops,
 165	},
 166	[board_ahci_nosntf] = {
 167		AHCI_HFLAGS	(AHCI_HFLAG_NO_SNTF),
 168		.flags		= AHCI_FLAG_COMMON,
 169		.pio_mask	= ATA_PIO4,
 170		.udma_mask	= ATA_UDMA6,
 171		.port_ops	= &ahci_ops,
 172	},
 173	[board_ahci_yes_fbs] = {
 174		AHCI_HFLAGS	(AHCI_HFLAG_YES_FBS),
 175		.flags		= AHCI_FLAG_COMMON,
 176		.pio_mask	= ATA_PIO4,
 177		.udma_mask	= ATA_UDMA6,
 178		.port_ops	= &ahci_ops,
 179	},
 180	/* by chipsets */
 181	[board_ahci_al] = {
 182		AHCI_HFLAGS	(AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
 183		.flags		= AHCI_FLAG_COMMON,
 184		.pio_mask	= ATA_PIO4,
 185		.udma_mask	= ATA_UDMA6,
 186		.port_ops	= &ahci_ops,
 187	},
 188	[board_ahci_avn] = {
 189		.flags		= AHCI_FLAG_COMMON,
 190		.pio_mask	= ATA_PIO4,
 191		.udma_mask	= ATA_UDMA6,
 192		.port_ops	= &ahci_avn_ops,
 193	},
 194	[board_ahci_mcp65] = {
 195		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 196				 AHCI_HFLAG_YES_NCQ),
 197		.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 198		.pio_mask	= ATA_PIO4,
 199		.udma_mask	= ATA_UDMA6,
 200		.port_ops	= &ahci_ops,
 201	},
 202	[board_ahci_mcp77] = {
 203		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 204		.flags		= AHCI_FLAG_COMMON,
 205		.pio_mask	= ATA_PIO4,
 206		.udma_mask	= ATA_UDMA6,
 207		.port_ops	= &ahci_ops,
 208	},
 209	[board_ahci_mcp89] = {
 210		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA),
 211		.flags		= AHCI_FLAG_COMMON,
 212		.pio_mask	= ATA_PIO4,
 213		.udma_mask	= ATA_UDMA6,
 214		.port_ops	= &ahci_ops,
 215	},
 216	[board_ahci_mv] = {
 217		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 218				 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 219		.flags		= ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
 220		.pio_mask	= ATA_PIO4,
 221		.udma_mask	= ATA_UDMA6,
 222		.port_ops	= &ahci_ops,
 223	},
 224	[board_ahci_sb600] = {
 225		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL |
 226				 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 227				 AHCI_HFLAG_32BIT_ONLY),
 228		.flags		= AHCI_FLAG_COMMON,
 229		.pio_mask	= ATA_PIO4,
 230		.udma_mask	= ATA_UDMA6,
 231		.port_ops	= &ahci_pmp_retry_srst_ops,
 232	},
 233	[board_ahci_sb700] = {	/* for SB700 and SB800 */
 234		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL),
 235		.flags		= AHCI_FLAG_COMMON,
 236		.pio_mask	= ATA_PIO4,
 237		.udma_mask	= ATA_UDMA6,
 238		.port_ops	= &ahci_pmp_retry_srst_ops,
 239	},
 240	[board_ahci_vt8251] = {
 241		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 242		.flags		= AHCI_FLAG_COMMON,
 243		.pio_mask	= ATA_PIO4,
 244		.udma_mask	= ATA_UDMA6,
 245		.port_ops	= &ahci_vt8251_ops,
 246	},
 247	[board_ahci_pcs7] = {
 248		.flags		= AHCI_FLAG_COMMON,
 249		.pio_mask	= ATA_PIO4,
 250		.udma_mask	= ATA_UDMA6,
 251		.port_ops	= &ahci_ops,
 252	},
 253};
 254
 255static const struct pci_device_id ahci_pci_tbl[] = {
 256	/* Intel */
 257	{ PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
 258	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 259	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 260	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 261	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 262	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 263	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 264	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 265	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 266	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 267	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 268	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 269	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
 270	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 271	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 272	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 273	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 274	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 275	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 276	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 277	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 278	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
 279	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
 280	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
 281	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
 282	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
 283	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 284	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
 285	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 286	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 287	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 288	{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 289	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 290	{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 291	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 292	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 293	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 294	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
 295	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 296	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
 297	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 298	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
 299	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
 300	{ PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
 301	{ PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
 302	{ PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
 303	{ PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
 304	{ PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
 305	{ PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
 306	{ PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
 307	{ PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
 308	{ PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
 309	{ PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
 310	{ PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
 311	{ PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
 312	{ PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
 313	{ PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
 314	{ PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
 315	{ PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
 316	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
 317	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
 318	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 319	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
 320	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 321	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
 322	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 323	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 324	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
 325	{ PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
 326	{ PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 
 327	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
 328	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
 329	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
 330	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
 331	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
 332	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
 333	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
 334	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
 335	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
 336	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
 337	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
 338	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
 339	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
 340	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
 341	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
 342	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
 343	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
 344	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
 345	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
 346	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
 347	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
 348	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
 349	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
 350	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
 351	{ PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
 352	{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
 353	{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
 354	{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
 355	{ PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
 356	{ PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
 357	{ PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
 358	{ PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
 359	{ PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
 360	{ PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
 361	{ PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
 362	{ PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
 363	{ PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
 364	{ PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
 365	{ PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
 366	{ PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
 367	{ PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
 368	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
 369	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
 370	{ PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
 371	{ PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
 372	{ PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
 373	{ PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
 374	{ PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
 375	{ PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
 376	{ PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
 377	{ PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
 378	{ PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
 379	{ PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
 380	{ PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
 381	{ PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
 382	{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
 383	{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
 384	{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
 385	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
 386	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
 387	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
 388	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
 389	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
 390	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
 391	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
 392	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
 393	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
 394	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
 395	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
 396	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
 397	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
 398	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
 399	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
 400	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
 401	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
 402	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
 403	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
 404	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
 405	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
 
 
 
 
 406	{ PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
 407	{ PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
 408	{ PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
 409	{ PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
 410	{ PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
 411	{ PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
 412	{ PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
 413	{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
 414	{ PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
 415	{ PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
 416	{ PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
 417	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
 418	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
 419	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
 420	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
 421	{ PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
 422	{ PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
 423	{ PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
 424	{ PCI_VDEVICE(INTEL, 0xa0d3), board_ahci_low_power }, /* Tiger Lake UP{3,4} AHCI */
 425
 426	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
 427	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 428	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 429	/* JMicron 362B and 362C have an AHCI function with IDE class code */
 430	{ PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
 431	{ PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
 432	/* May need to update quirk_jmicron_async_suspend() for additions */
 433
 434	/* ATI */
 435	{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 436	{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 437	{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 438	{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 439	{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 440	{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 441	{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 442
 443	/* Amazon's Annapurna Labs support */
 444	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
 445		.class = PCI_CLASS_STORAGE_SATA_AHCI,
 446		.class_mask = 0xffffff,
 447		board_ahci_al },
 448	/* AMD */
 449	{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 450	{ PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
 451	{ PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
 452	{ PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
 453	/* AMD is using RAID class only for ahci controllers */
 454	{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 455	  PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 456
 457	/* Dell S140/S150 */
 458	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
 459	  PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 460
 461	/* VIA */
 462	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 463	{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 464
 465	/* NVIDIA */
 466	{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },	/* MCP65 */
 467	{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },	/* MCP65 */
 468	{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },	/* MCP65 */
 469	{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },	/* MCP65 */
 470	{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },	/* MCP65 */
 471	{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },	/* MCP65 */
 472	{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },	/* MCP65 */
 473	{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },	/* MCP65 */
 474	{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },	/* MCP67 */
 475	{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },	/* MCP67 */
 476	{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },	/* MCP67 */
 477	{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },	/* MCP67 */
 478	{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },	/* MCP67 */
 479	{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },	/* MCP67 */
 480	{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },	/* MCP67 */
 481	{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },	/* MCP67 */
 482	{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },	/* MCP67 */
 483	{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },	/* MCP67 */
 484	{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },	/* MCP67 */
 485	{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },	/* MCP67 */
 486	{ PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },	/* Linux ID */
 487	{ PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },	/* Linux ID */
 488	{ PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },	/* Linux ID */
 489	{ PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },	/* Linux ID */
 490	{ PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },	/* Linux ID */
 491	{ PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },	/* Linux ID */
 492	{ PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },	/* Linux ID */
 493	{ PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },	/* Linux ID */
 494	{ PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },	/* Linux ID */
 495	{ PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },	/* Linux ID */
 496	{ PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },	/* Linux ID */
 497	{ PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },	/* Linux ID */
 498	{ PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },	/* Linux ID */
 499	{ PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },	/* Linux ID */
 500	{ PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },	/* Linux ID */
 501	{ PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },	/* Linux ID */
 502	{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },	/* MCP73 */
 503	{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },	/* MCP73 */
 504	{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },	/* MCP73 */
 505	{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },	/* MCP73 */
 506	{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },	/* MCP73 */
 507	{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },	/* MCP73 */
 508	{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },	/* MCP73 */
 509	{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },	/* MCP73 */
 510	{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },	/* MCP73 */
 511	{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },	/* MCP73 */
 512	{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },	/* MCP73 */
 513	{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },	/* MCP73 */
 514	{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },	/* MCP77 */
 515	{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },	/* MCP77 */
 516	{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },	/* MCP77 */
 517	{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },	/* MCP77 */
 518	{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },	/* MCP77 */
 519	{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },	/* MCP77 */
 520	{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },	/* MCP77 */
 521	{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },	/* MCP77 */
 522	{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },	/* MCP77 */
 523	{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },	/* MCP77 */
 524	{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },	/* MCP77 */
 525	{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },	/* MCP77 */
 526	{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },	/* MCP79 */
 527	{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },	/* MCP79 */
 528	{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },	/* MCP79 */
 529	{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },	/* MCP79 */
 530	{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },	/* MCP79 */
 531	{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },	/* MCP79 */
 532	{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },	/* MCP79 */
 533	{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },	/* MCP79 */
 534	{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },	/* MCP79 */
 535	{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },	/* MCP79 */
 536	{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },	/* MCP79 */
 537	{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },	/* MCP79 */
 538	{ PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },	/* MCP89 */
 539	{ PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },	/* MCP89 */
 540	{ PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },	/* MCP89 */
 541	{ PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },	/* MCP89 */
 542	{ PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },	/* MCP89 */
 543	{ PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },	/* MCP89 */
 544	{ PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },	/* MCP89 */
 545	{ PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },	/* MCP89 */
 546	{ PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },	/* MCP89 */
 547	{ PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },	/* MCP89 */
 548	{ PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },	/* MCP89 */
 549	{ PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },	/* MCP89 */
 550
 551	/* SiS */
 552	{ PCI_VDEVICE(SI, 0x1184), board_ahci },		/* SiS 966 */
 553	{ PCI_VDEVICE(SI, 0x1185), board_ahci },		/* SiS 968 */
 554	{ PCI_VDEVICE(SI, 0x0186), board_ahci },		/* SiS 968 */
 555
 556	/* ST Microelectronics */
 557	{ PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },		/* ST ConneXt */
 558
 559	/* Marvell */
 560	{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },	/* 6145 */
 561	{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },	/* 6121 */
 562	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
 563	  .class = PCI_CLASS_STORAGE_SATA_AHCI,
 564	  .class_mask = 0xffffff,
 565	  .driver_data = board_ahci_yes_fbs },			/* 88se9128 */
 566	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
 567	  .driver_data = board_ahci_yes_fbs },			/* 88se9125 */
 568	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
 569			 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
 570	  .driver_data = board_ahci_yes_fbs },			/* 88se9170 */
 571	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
 572	  .driver_data = board_ahci_yes_fbs },			/* 88se9172 */
 573	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
 574	  .driver_data = board_ahci_yes_fbs },			/* 88se9182 */
 575	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
 576	  .driver_data = board_ahci_yes_fbs },			/* 88se9172 */
 577	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
 578	  .driver_data = board_ahci_yes_fbs },			/* 88se9172 on some Gigabyte */
 579	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
 580	  .driver_data = board_ahci_yes_fbs },
 581	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), 	/* 88se91a2 */
 582	  .driver_data = board_ahci_yes_fbs },
 583	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
 584	  .driver_data = board_ahci_yes_fbs },
 585	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
 586	  .driver_data = board_ahci_yes_fbs },
 587	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
 588	  .driver_data = board_ahci_no_debounce_delay },
 589	{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
 590	  .driver_data = board_ahci_yes_fbs },
 591	{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
 592	  .driver_data = board_ahci_yes_fbs },
 593
 594	/* Promise */
 595	{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },	/* PDC42819 */
 596	{ PCI_VDEVICE(PROMISE, 0x3781), board_ahci },   /* FastTrak TX8660 ahci-mode */
 597
 598	/* Asmedia */
 599	{ PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },	/* ASM1060 */
 600	{ PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },	/* ASM1060 */
 601	{ PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },	/* ASM1061 */
 602	{ PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },	/* ASM1062 */
 603	{ PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci },   /* ASM1061R */
 604	{ PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci },   /* ASM1062R */
 605	{ PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci },   /* ASM1062+JMB575 */
 606
 607	/*
 608	 * Samsung SSDs found on some macbooks.  NCQ times out if MSI is
 609	 * enabled.  https://bugzilla.kernel.org/show_bug.cgi?id=60731
 610	 */
 611	{ PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
 612	{ PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
 613
 614	/* Enmotus */
 615	{ PCI_DEVICE(0x1c44, 0x8000), board_ahci },
 616
 617	/* Loongson */
 618	{ PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
 619
 620	/* Generic, PCI class code for AHCI */
 621	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 622	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 623
 624	{ }	/* terminate list */
 625};
 626
 627static const struct dev_pm_ops ahci_pci_pm_ops = {
 628	SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
 629	SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
 630			   ahci_pci_device_runtime_resume, NULL)
 631};
 632
 633static struct pci_driver ahci_pci_driver = {
 634	.name			= DRV_NAME,
 635	.id_table		= ahci_pci_tbl,
 636	.probe			= ahci_init_one,
 637	.remove			= ahci_remove_one,
 638	.shutdown		= ahci_shutdown_one,
 639	.driver = {
 640		.pm		= &ahci_pci_pm_ops,
 641	},
 642};
 643
 644#if IS_ENABLED(CONFIG_PATA_MARVELL)
 645static int marvell_enable;
 646#else
 647static int marvell_enable = 1;
 648#endif
 649module_param(marvell_enable, int, 0644);
 650MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 651
 652static int mobile_lpm_policy = -1;
 653module_param(mobile_lpm_policy, int, 0644);
 654MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
 655
 656static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 657					 struct ahci_host_priv *hpriv)
 658{
 659	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 660		dev_info(&pdev->dev, "JMB361 has only one port\n");
 661		hpriv->saved_port_map = 1;
 662	}
 663
 664	/*
 665	 * Temporary Marvell 6145 hack: PATA port presence
 666	 * is asserted through the standard AHCI port
 667	 * presence register, as bit 4 (counting from 0)
 668	 */
 669	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 670		if (pdev->device == 0x6121)
 671			hpriv->mask_port_map = 0x3;
 672		else
 673			hpriv->mask_port_map = 0xf;
 674		dev_info(&pdev->dev,
 675			  "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 676	}
 677
 678	ahci_save_initial_config(&pdev->dev, hpriv);
 679}
 680
 681static int ahci_pci_reset_controller(struct ata_host *host)
 682{
 683	struct pci_dev *pdev = to_pci_dev(host->dev);
 684	struct ahci_host_priv *hpriv = host->private_data;
 685	int rc;
 686
 687	rc = ahci_reset_controller(host);
 688	if (rc)
 689		return rc;
 690
 691	/*
 692	 * If platform firmware failed to enable ports, try to enable
 693	 * them here.
 694	 */
 695	ahci_intel_pcs_quirk(pdev, hpriv);
 696
 697	return 0;
 698}
 699
 700static void ahci_pci_init_controller(struct ata_host *host)
 701{
 702	struct ahci_host_priv *hpriv = host->private_data;
 703	struct pci_dev *pdev = to_pci_dev(host->dev);
 704	void __iomem *port_mmio;
 705	u32 tmp;
 706	int mv;
 707
 708	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 709		if (pdev->device == 0x6121)
 710			mv = 2;
 711		else
 712			mv = 4;
 713		port_mmio = __ahci_port_base(hpriv, mv);
 714
 715		writel(0, port_mmio + PORT_IRQ_MASK);
 716
 717		/* clear port IRQ */
 718		tmp = readl(port_mmio + PORT_IRQ_STAT);
 719		dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
 720		if (tmp)
 721			writel(tmp, port_mmio + PORT_IRQ_STAT);
 722	}
 723
 724	ahci_init_controller(host);
 725}
 726
 727static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 728				 unsigned long deadline)
 729{
 730	struct ata_port *ap = link->ap;
 731	struct ahci_host_priv *hpriv = ap->host->private_data;
 732	bool online;
 733	int rc;
 734
 
 
 735	hpriv->stop_engine(ap);
 736
 737	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 738				 deadline, &online, NULL);
 739
 740	hpriv->start_engine(ap);
 741
 
 
 742	/* vt8251 doesn't clear BSY on signature FIS reception,
 743	 * request follow-up softreset.
 744	 */
 745	return online ? -EAGAIN : rc;
 746}
 747
 748static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 749				unsigned long deadline)
 750{
 751	struct ata_port *ap = link->ap;
 752	struct ahci_port_priv *pp = ap->private_data;
 753	struct ahci_host_priv *hpriv = ap->host->private_data;
 754	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 755	struct ata_taskfile tf;
 756	bool online;
 757	int rc;
 758
 759	hpriv->stop_engine(ap);
 760
 761	/* clear D2H reception area to properly wait for D2H FIS */
 762	ata_tf_init(link->device, &tf);
 763	tf.status = ATA_BUSY;
 764	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 765
 766	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 767				 deadline, &online, NULL);
 768
 769	hpriv->start_engine(ap);
 770
 771	/* The pseudo configuration device on SIMG4726 attached to
 772	 * ASUS P5W-DH Deluxe doesn't send signature FIS after
 773	 * hardreset if no device is attached to the first downstream
 774	 * port && the pseudo device locks up on SRST w/ PMP==0.  To
 775	 * work around this, wait for !BSY only briefly.  If BSY isn't
 776	 * cleared, perform CLO and proceed to IDENTIFY (achieved by
 777	 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 778	 *
 779	 * Wait for two seconds.  Devices attached to downstream port
 780	 * which can't process the following IDENTIFY after this will
 781	 * have to be reset again.  For most cases, this should
 782	 * suffice while making probing snappish enough.
 783	 */
 784	if (online) {
 785		rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 786					  ahci_check_ready);
 787		if (rc)
 788			ahci_kick_engine(ap);
 789	}
 790	return rc;
 791}
 792
 793/*
 794 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
 795 *
 796 * It has been observed with some SSDs that the timing of events in the
 797 * link synchronization phase can leave the port in a state that can not
 798 * be recovered by a SATA-hard-reset alone.  The failing signature is
 799 * SStatus.DET stuck at 1 ("Device presence detected but Phy
 800 * communication not established").  It was found that unloading and
 801 * reloading the driver when this problem occurs allows the drive
 802 * connection to be recovered (DET advanced to 0x3).  The critical
 803 * component of reloading the driver is that the port state machines are
 804 * reset by bouncing "port enable" in the AHCI PCS configuration
 805 * register.  So, reproduce that effect by bouncing a port whenever we
 806 * see DET==1 after a reset.
 807 */
 808static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 809			      unsigned long deadline)
 810{
 811	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
 812	struct ata_port *ap = link->ap;
 813	struct ahci_port_priv *pp = ap->private_data;
 814	struct ahci_host_priv *hpriv = ap->host->private_data;
 815	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 816	unsigned long tmo = deadline - jiffies;
 817	struct ata_taskfile tf;
 818	bool online;
 819	int rc, i;
 820
 
 
 821	hpriv->stop_engine(ap);
 822
 823	for (i = 0; i < 2; i++) {
 824		u16 val;
 825		u32 sstatus;
 826		int port = ap->port_no;
 827		struct ata_host *host = ap->host;
 828		struct pci_dev *pdev = to_pci_dev(host->dev);
 829
 830		/* clear D2H reception area to properly wait for D2H FIS */
 831		ata_tf_init(link->device, &tf);
 832		tf.status = ATA_BUSY;
 833		ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 834
 835		rc = sata_link_hardreset(link, timing, deadline, &online,
 836				ahci_check_ready);
 837
 838		if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
 839				(sstatus & 0xf) != 1)
 840			break;
 841
 842		ata_link_info(link,  "avn bounce port%d\n", port);
 843
 844		pci_read_config_word(pdev, 0x92, &val);
 845		val &= ~(1 << port);
 846		pci_write_config_word(pdev, 0x92, val);
 847		ata_msleep(ap, 1000);
 848		val |= 1 << port;
 849		pci_write_config_word(pdev, 0x92, val);
 850		deadline += tmo;
 851	}
 852
 853	hpriv->start_engine(ap);
 854
 855	if (online)
 856		*class = ahci_dev_classify(ap);
 857
 
 858	return rc;
 859}
 860
 861
 862#ifdef CONFIG_PM
 863static void ahci_pci_disable_interrupts(struct ata_host *host)
 864{
 865	struct ahci_host_priv *hpriv = host->private_data;
 866	void __iomem *mmio = hpriv->mmio;
 867	u32 ctl;
 868
 869	/* AHCI spec rev1.1 section 8.3.3:
 870	 * Software must disable interrupts prior to requesting a
 871	 * transition of the HBA to D3 state.
 872	 */
 873	ctl = readl(mmio + HOST_CTL);
 874	ctl &= ~HOST_IRQ_EN;
 875	writel(ctl, mmio + HOST_CTL);
 876	readl(mmio + HOST_CTL); /* flush */
 877}
 878
 879static int ahci_pci_device_runtime_suspend(struct device *dev)
 880{
 881	struct pci_dev *pdev = to_pci_dev(dev);
 882	struct ata_host *host = pci_get_drvdata(pdev);
 883
 884	ahci_pci_disable_interrupts(host);
 885	return 0;
 886}
 887
 888static int ahci_pci_device_runtime_resume(struct device *dev)
 889{
 890	struct pci_dev *pdev = to_pci_dev(dev);
 891	struct ata_host *host = pci_get_drvdata(pdev);
 892	int rc;
 893
 894	rc = ahci_pci_reset_controller(host);
 895	if (rc)
 896		return rc;
 897	ahci_pci_init_controller(host);
 898	return 0;
 899}
 900
 901#ifdef CONFIG_PM_SLEEP
 902static int ahci_pci_device_suspend(struct device *dev)
 903{
 904	struct pci_dev *pdev = to_pci_dev(dev);
 905	struct ata_host *host = pci_get_drvdata(pdev);
 906	struct ahci_host_priv *hpriv = host->private_data;
 907
 908	if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 909		dev_err(&pdev->dev,
 910			"BIOS update required for suspend/resume\n");
 911		return -EIO;
 912	}
 913
 914	ahci_pci_disable_interrupts(host);
 915	ata_host_suspend(host, PMSG_SUSPEND);
 916	return 0;
 917}
 918
 919static int ahci_pci_device_resume(struct device *dev)
 920{
 921	struct pci_dev *pdev = to_pci_dev(dev);
 922	struct ata_host *host = pci_get_drvdata(pdev);
 923	int rc;
 924
 925	/* Apple BIOS helpfully mangles the registers on resume */
 926	if (is_mcp89_apple(pdev))
 927		ahci_mcp89_apple_enable(pdev);
 928
 929	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 930		rc = ahci_pci_reset_controller(host);
 931		if (rc)
 932			return rc;
 933
 934		ahci_pci_init_controller(host);
 935	}
 936
 937	ata_host_resume(host);
 938
 939	return 0;
 940}
 941#endif
 942
 943#endif /* CONFIG_PM */
 944
 945static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 946{
 947	const int dma_bits = using_dac ? 64 : 32;
 948	int rc;
 949
 950	/*
 951	 * If the device fixup already set the dma_mask to some non-standard
 952	 * value, don't extend it here. This happens on STA2X11, for example.
 953	 *
 954	 * XXX: manipulating the DMA mask from platform code is completely
 955	 * bogus, platform code should use dev->bus_dma_limit instead..
 956	 */
 957	if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 958		return 0;
 959
 960	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
 961	if (rc)
 962		dev_err(&pdev->dev, "DMA enable failed\n");
 963	return rc;
 964}
 965
 966static void ahci_pci_print_info(struct ata_host *host)
 967{
 968	struct pci_dev *pdev = to_pci_dev(host->dev);
 969	u16 cc;
 970	const char *scc_s;
 971
 972	pci_read_config_word(pdev, 0x0a, &cc);
 973	if (cc == PCI_CLASS_STORAGE_IDE)
 974		scc_s = "IDE";
 975	else if (cc == PCI_CLASS_STORAGE_SATA)
 976		scc_s = "SATA";
 977	else if (cc == PCI_CLASS_STORAGE_RAID)
 978		scc_s = "RAID";
 979	else
 980		scc_s = "unknown";
 981
 982	ahci_print_info(host, scc_s);
 983}
 984
 985/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 986 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 987 * support PMP and the 4726 either directly exports the device
 988 * attached to the first downstream port or acts as a hardware storage
 989 * controller and emulate a single ATA device (can be RAID 0/1 or some
 990 * other configuration).
 991 *
 992 * When there's no device attached to the first downstream port of the
 993 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 994 * configure the 4726.  However, ATA emulation of the device is very
 995 * lame.  It doesn't send signature D2H Reg FIS after the initial
 996 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 997 *
 998 * The following function works around the problem by always using
 999 * hardreset on the port and not depending on receiving signature FIS
1000 * afterward.  If signature FIS isn't received soon, ATA class is
1001 * assumed without follow-up softreset.
1002 */
1003static void ahci_p5wdh_workaround(struct ata_host *host)
1004{
1005	static const struct dmi_system_id sysids[] = {
1006		{
1007			.ident = "P5W DH Deluxe",
1008			.matches = {
1009				DMI_MATCH(DMI_SYS_VENDOR,
1010					  "ASUSTEK COMPUTER INC"),
1011				DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1012			},
1013		},
1014		{ }
1015	};
1016	struct pci_dev *pdev = to_pci_dev(host->dev);
1017
1018	if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1019	    dmi_check_system(sysids)) {
1020		struct ata_port *ap = host->ports[1];
1021
1022		dev_info(&pdev->dev,
1023			 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1024
1025		ap->ops = &ahci_p5wdh_ops;
1026		ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1027	}
1028}
1029
1030/*
1031 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1032 * booting in BIOS compatibility mode.  We restore the registers but not ID.
1033 */
1034static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1035{
1036	u32 val;
1037
1038	printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1039
1040	pci_read_config_dword(pdev, 0xf8, &val);
1041	val |= 1 << 0x1b;
1042	/* the following changes the device ID, but appears not to affect function */
1043	/* val = (val & ~0xf0000000) | 0x80000000; */
1044	pci_write_config_dword(pdev, 0xf8, val);
1045
1046	pci_read_config_dword(pdev, 0x54c, &val);
1047	val |= 1 << 0xc;
1048	pci_write_config_dword(pdev, 0x54c, val);
1049
1050	pci_read_config_dword(pdev, 0x4a4, &val);
1051	val &= 0xff;
1052	val |= 0x01060100;
1053	pci_write_config_dword(pdev, 0x4a4, val);
1054
1055	pci_read_config_dword(pdev, 0x54c, &val);
1056	val &= ~(1 << 0xc);
1057	pci_write_config_dword(pdev, 0x54c, val);
1058
1059	pci_read_config_dword(pdev, 0xf8, &val);
1060	val &= ~(1 << 0x1b);
1061	pci_write_config_dword(pdev, 0xf8, val);
1062}
1063
1064static bool is_mcp89_apple(struct pci_dev *pdev)
1065{
1066	return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1067		pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1068		pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1069		pdev->subsystem_device == 0xcb89;
1070}
1071
1072/* only some SB600 ahci controllers can do 64bit DMA */
1073static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1074{
1075	static const struct dmi_system_id sysids[] = {
1076		/*
1077		 * The oldest version known to be broken is 0901 and
1078		 * working is 1501 which was released on 2007-10-26.
1079		 * Enable 64bit DMA on 1501 and anything newer.
1080		 *
1081		 * Please read bko#9412 for more info.
1082		 */
1083		{
1084			.ident = "ASUS M2A-VM",
1085			.matches = {
1086				DMI_MATCH(DMI_BOARD_VENDOR,
1087					  "ASUSTeK Computer INC."),
1088				DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1089			},
1090			.driver_data = "20071026",	/* yyyymmdd */
1091		},
1092		/*
1093		 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1094		 * support 64bit DMA.
1095		 *
1096		 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1097		 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1098		 * This spelling mistake was fixed in BIOS version 1.5, so
1099		 * 1.5 and later have the Manufacturer as
1100		 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1101		 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1102		 *
1103		 * BIOS versions earlier than 1.9 had a Board Product Name
1104		 * DMI field of "MS-7376". This was changed to be
1105		 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1106		 * match on DMI_BOARD_NAME of "MS-7376".
1107		 */
1108		{
1109			.ident = "MSI K9A2 Platinum",
1110			.matches = {
1111				DMI_MATCH(DMI_BOARD_VENDOR,
1112					  "MICRO-STAR INTER"),
1113				DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1114			},
1115		},
1116		/*
1117		 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1118		 * 64bit DMA.
1119		 *
1120		 * This board also had the typo mentioned above in the
1121		 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1122		 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1123		 */
1124		{
1125			.ident = "MSI K9AGM2",
1126			.matches = {
1127				DMI_MATCH(DMI_BOARD_VENDOR,
1128					  "MICRO-STAR INTER"),
1129				DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1130			},
1131		},
1132		/*
1133		 * All BIOS versions for the Asus M3A support 64bit DMA.
1134		 * (all release versions from 0301 to 1206 were tested)
1135		 */
1136		{
1137			.ident = "ASUS M3A",
1138			.matches = {
1139				DMI_MATCH(DMI_BOARD_VENDOR,
1140					  "ASUSTeK Computer INC."),
1141				DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1142			},
1143		},
1144		{ }
1145	};
1146	const struct dmi_system_id *match;
1147	int year, month, date;
1148	char buf[9];
1149
1150	match = dmi_first_match(sysids);
1151	if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1152	    !match)
1153		return false;
1154
1155	if (!match->driver_data)
1156		goto enable_64bit;
1157
1158	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1159	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1160
1161	if (strcmp(buf, match->driver_data) >= 0)
1162		goto enable_64bit;
1163	else {
1164		dev_warn(&pdev->dev,
1165			 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1166			 match->ident);
1167		return false;
1168	}
1169
1170enable_64bit:
1171	dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1172	return true;
1173}
1174
1175static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1176{
1177	static const struct dmi_system_id broken_systems[] = {
1178		{
1179			.ident = "HP Compaq nx6310",
1180			.matches = {
1181				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1182				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1183			},
1184			/* PCI slot number of the controller */
1185			.driver_data = (void *)0x1FUL,
1186		},
1187		{
1188			.ident = "HP Compaq 6720s",
1189			.matches = {
1190				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1191				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1192			},
1193			/* PCI slot number of the controller */
1194			.driver_data = (void *)0x1FUL,
1195		},
1196
1197		{ }	/* terminate list */
1198	};
1199	const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1200
1201	if (dmi) {
1202		unsigned long slot = (unsigned long)dmi->driver_data;
1203		/* apply the quirk only to on-board controllers */
1204		return slot == PCI_SLOT(pdev->devfn);
1205	}
1206
1207	return false;
1208}
1209
1210static bool ahci_broken_suspend(struct pci_dev *pdev)
1211{
1212	static const struct dmi_system_id sysids[] = {
1213		/*
1214		 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1215		 * to the harddisk doesn't become online after
1216		 * resuming from STR.  Warn and fail suspend.
1217		 *
1218		 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1219		 *
1220		 * Use dates instead of versions to match as HP is
1221		 * apparently recycling both product and version
1222		 * strings.
1223		 *
1224		 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1225		 */
1226		{
1227			.ident = "dv4",
1228			.matches = {
1229				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1230				DMI_MATCH(DMI_PRODUCT_NAME,
1231					  "HP Pavilion dv4 Notebook PC"),
1232			},
1233			.driver_data = "20090105",	/* F.30 */
1234		},
1235		{
1236			.ident = "dv5",
1237			.matches = {
1238				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1239				DMI_MATCH(DMI_PRODUCT_NAME,
1240					  "HP Pavilion dv5 Notebook PC"),
1241			},
1242			.driver_data = "20090506",	/* F.16 */
1243		},
1244		{
1245			.ident = "dv6",
1246			.matches = {
1247				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1248				DMI_MATCH(DMI_PRODUCT_NAME,
1249					  "HP Pavilion dv6 Notebook PC"),
1250			},
1251			.driver_data = "20090423",	/* F.21 */
1252		},
1253		{
1254			.ident = "HDX18",
1255			.matches = {
1256				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1257				DMI_MATCH(DMI_PRODUCT_NAME,
1258					  "HP HDX18 Notebook PC"),
1259			},
1260			.driver_data = "20090430",	/* F.23 */
1261		},
1262		/*
1263		 * Acer eMachines G725 has the same problem.  BIOS
1264		 * V1.03 is known to be broken.  V3.04 is known to
1265		 * work.  Between, there are V1.06, V2.06 and V3.03
1266		 * that we don't have much idea about.  For now,
1267		 * blacklist anything older than V3.04.
1268		 *
1269		 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1270		 */
1271		{
1272			.ident = "G725",
1273			.matches = {
1274				DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1275				DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1276			},
1277			.driver_data = "20091216",	/* V3.04 */
1278		},
1279		{ }	/* terminate list */
1280	};
1281	const struct dmi_system_id *dmi = dmi_first_match(sysids);
1282	int year, month, date;
1283	char buf[9];
1284
1285	if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1286		return false;
1287
1288	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1289	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1290
1291	return strcmp(buf, dmi->driver_data) < 0;
1292}
1293
1294static bool ahci_broken_lpm(struct pci_dev *pdev)
1295{
1296	static const struct dmi_system_id sysids[] = {
1297		/* Various Lenovo 50 series have LPM issues with older BIOSen */
1298		{
1299			.matches = {
1300				DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1301				DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1302			},
1303			.driver_data = "20180406", /* 1.31 */
1304		},
1305		{
1306			.matches = {
1307				DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1308				DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1309			},
1310			.driver_data = "20180420", /* 1.28 */
1311		},
1312		{
1313			.matches = {
1314				DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1315				DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1316			},
1317			.driver_data = "20180315", /* 1.33 */
1318		},
1319		{
1320			.matches = {
1321				DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1322				DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1323			},
1324			/*
1325			 * Note date based on release notes, 2.35 has been
1326			 * reported to be good, but I've been unable to get
1327			 * a hold of the reporter to get the DMI BIOS date.
1328			 * TODO: fix this.
1329			 */
1330			.driver_data = "20180310", /* 2.35 */
1331		},
1332		{ }	/* terminate list */
1333	};
1334	const struct dmi_system_id *dmi = dmi_first_match(sysids);
1335	int year, month, date;
1336	char buf[9];
1337
1338	if (!dmi)
1339		return false;
1340
1341	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1342	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1343
1344	return strcmp(buf, dmi->driver_data) < 0;
1345}
1346
1347static bool ahci_broken_online(struct pci_dev *pdev)
1348{
1349#define ENCODE_BUSDEVFN(bus, slot, func)			\
1350	(void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1351	static const struct dmi_system_id sysids[] = {
1352		/*
1353		 * There are several gigabyte boards which use
1354		 * SIMG5723s configured as hardware RAID.  Certain
1355		 * 5723 firmware revisions shipped there keep the link
1356		 * online but fail to answer properly to SRST or
1357		 * IDENTIFY when no device is attached downstream
1358		 * causing libata to retry quite a few times leading
1359		 * to excessive detection delay.
1360		 *
1361		 * As these firmwares respond to the second reset try
1362		 * with invalid device signature, considering unknown
1363		 * sig as offline works around the problem acceptably.
1364		 */
1365		{
1366			.ident = "EP45-DQ6",
1367			.matches = {
1368				DMI_MATCH(DMI_BOARD_VENDOR,
1369					  "Gigabyte Technology Co., Ltd."),
1370				DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1371			},
1372			.driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1373		},
1374		{
1375			.ident = "EP45-DS5",
1376			.matches = {
1377				DMI_MATCH(DMI_BOARD_VENDOR,
1378					  "Gigabyte Technology Co., Ltd."),
1379				DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1380			},
1381			.driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1382		},
1383		{ }	/* terminate list */
1384	};
1385#undef ENCODE_BUSDEVFN
1386	const struct dmi_system_id *dmi = dmi_first_match(sysids);
1387	unsigned int val;
1388
1389	if (!dmi)
1390		return false;
1391
1392	val = (unsigned long)dmi->driver_data;
1393
1394	return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1395}
1396
1397static bool ahci_broken_devslp(struct pci_dev *pdev)
1398{
1399	/* device with broken DEVSLP but still showing SDS capability */
1400	static const struct pci_device_id ids[] = {
1401		{ PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1402		{}
1403	};
1404
1405	return pci_match_id(ids, pdev);
1406}
1407
1408#ifdef CONFIG_ATA_ACPI
1409static void ahci_gtf_filter_workaround(struct ata_host *host)
1410{
1411	static const struct dmi_system_id sysids[] = {
1412		/*
1413		 * Aspire 3810T issues a bunch of SATA enable commands
1414		 * via _GTF including an invalid one and one which is
1415		 * rejected by the device.  Among the successful ones
1416		 * is FPDMA non-zero offset enable which when enabled
1417		 * only on the drive side leads to NCQ command
1418		 * failures.  Filter it out.
1419		 */
1420		{
1421			.ident = "Aspire 3810T",
1422			.matches = {
1423				DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1424				DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1425			},
1426			.driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1427		},
1428		{ }
1429	};
1430	const struct dmi_system_id *dmi = dmi_first_match(sysids);
1431	unsigned int filter;
1432	int i;
1433
1434	if (!dmi)
1435		return;
1436
1437	filter = (unsigned long)dmi->driver_data;
1438	dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1439		 filter, dmi->ident);
1440
1441	for (i = 0; i < host->n_ports; i++) {
1442		struct ata_port *ap = host->ports[i];
1443		struct ata_link *link;
1444		struct ata_device *dev;
1445
1446		ata_for_each_link(link, ap, EDGE)
1447			ata_for_each_dev(dev, link, ALL)
1448				dev->gtf_filter |= filter;
1449	}
1450}
1451#else
1452static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1453{}
1454#endif
1455
1456/*
1457 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1458 * as DUMMY, or detected but eventually get a "link down" and never get up
1459 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1460 * port_map may hold a value of 0x00.
1461 *
1462 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1463 * and can significantly reduce the occurrence of the problem.
1464 *
1465 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1466 */
1467static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1468				    struct pci_dev *pdev)
1469{
1470	static const struct dmi_system_id sysids[] = {
1471		{
1472			.ident = "Acer Switch Alpha 12",
1473			.matches = {
1474				DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1475				DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1476			},
1477		},
1478		{ }
1479	};
1480
1481	if (dmi_check_system(sysids)) {
1482		dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1483		if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1484			hpriv->port_map = 0x7;
1485			hpriv->cap = 0xC734FF02;
1486		}
1487	}
1488}
1489
1490#ifdef CONFIG_ARM64
1491/*
1492 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1493 * Workaround is to make sure all pending IRQs are served before leaving
1494 * handler.
1495 */
1496static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1497{
1498	struct ata_host *host = dev_instance;
1499	struct ahci_host_priv *hpriv;
1500	unsigned int rc = 0;
1501	void __iomem *mmio;
1502	u32 irq_stat, irq_masked;
1503	unsigned int handled = 1;
1504
 
1505	hpriv = host->private_data;
1506	mmio = hpriv->mmio;
1507	irq_stat = readl(mmio + HOST_IRQ_STAT);
1508	if (!irq_stat)
1509		return IRQ_NONE;
1510
1511	do {
1512		irq_masked = irq_stat & hpriv->port_map;
1513		spin_lock(&host->lock);
1514		rc = ahci_handle_port_intr(host, irq_masked);
1515		if (!rc)
1516			handled = 0;
1517		writel(irq_stat, mmio + HOST_IRQ_STAT);
1518		irq_stat = readl(mmio + HOST_IRQ_STAT);
1519		spin_unlock(&host->lock);
1520	} while (irq_stat);
 
1521
1522	return IRQ_RETVAL(handled);
1523}
1524#endif
1525
1526static void ahci_remap_check(struct pci_dev *pdev, int bar,
1527		struct ahci_host_priv *hpriv)
1528{
1529	int i;
1530	u32 cap;
1531
1532	/*
1533	 * Check if this device might have remapped nvme devices.
1534	 */
1535	if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1536	    pci_resource_len(pdev, bar) < SZ_512K ||
1537	    bar != AHCI_PCI_BAR_STANDARD ||
1538	    !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1539		return;
1540
1541	cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1542	for (i = 0; i < AHCI_MAX_REMAP; i++) {
1543		if ((cap & (1 << i)) == 0)
1544			continue;
1545		if (readl(hpriv->mmio + ahci_remap_dcc(i))
1546				!= PCI_CLASS_STORAGE_EXPRESS)
1547			continue;
1548
1549		/* We've found a remapped device */
1550		hpriv->remapped_nvme++;
1551	}
1552
1553	if (!hpriv->remapped_nvme)
1554		return;
1555
1556	dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1557		 hpriv->remapped_nvme);
1558	dev_warn(&pdev->dev,
1559		 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1560
1561	/*
1562	 * Don't rely on the msi-x capability in the remap case,
1563	 * share the legacy interrupt across ahci and remapped devices.
1564	 */
1565	hpriv->flags |= AHCI_HFLAG_NO_MSI;
1566}
1567
1568static int ahci_get_irq_vector(struct ata_host *host, int port)
1569{
1570	return pci_irq_vector(to_pci_dev(host->dev), port);
1571}
1572
1573static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1574			struct ahci_host_priv *hpriv)
1575{
1576	int nvec;
1577
1578	if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1579		return -ENODEV;
1580
1581	/*
1582	 * If number of MSIs is less than number of ports then Sharing Last
1583	 * Message mode could be enforced. In this case assume that advantage
1584	 * of multipe MSIs is negated and use single MSI mode instead.
1585	 */
1586	if (n_ports > 1) {
1587		nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1588				PCI_IRQ_MSIX | PCI_IRQ_MSI);
1589		if (nvec > 0) {
1590			if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1591				hpriv->get_irq_vector = ahci_get_irq_vector;
1592				hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1593				return nvec;
1594			}
1595
1596			/*
1597			 * Fallback to single MSI mode if the controller
1598			 * enforced MRSM mode.
1599			 */
1600			printk(KERN_INFO
1601				"ahci: MRSM is on, fallback to single MSI\n");
1602			pci_free_irq_vectors(pdev);
1603		}
1604	}
1605
1606	/*
1607	 * If the host is not capable of supporting per-port vectors, fall
1608	 * back to single MSI before finally attempting single MSI-X.
1609	 */
1610	nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1611	if (nvec == 1)
1612		return nvec;
1613	return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1614}
1615
1616static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1617					   struct ahci_host_priv *hpriv)
1618{
1619	int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1620
1621
1622	/* Ignore processing for chipsets that don't use policy */
1623	if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1624		return;
1625
1626	/* user modified policy via module param */
1627	if (mobile_lpm_policy != -1) {
1628		policy = mobile_lpm_policy;
1629		goto update_policy;
1630	}
1631
1632	if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
 
 
1633		if (hpriv->cap & HOST_CAP_PART)
1634			policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1635		else if (hpriv->cap & HOST_CAP_SSC)
1636			policy = ATA_LPM_MIN_POWER;
1637	}
 
1638
1639update_policy:
1640	if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1641		ap->target_lpm_policy = policy;
1642}
1643
1644static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1645{
1646	const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1647	u16 tmp16;
1648
1649	/*
1650	 * Only apply the 6-port PCS quirk for known legacy platforms.
1651	 */
1652	if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1653		return;
1654
1655	/* Skip applying the quirk on Denverton and beyond */
1656	if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1657		return;
1658
1659	/*
1660	 * port_map is determined from PORTS_IMPL PCI register which is
1661	 * implemented as write or write-once register.  If the register
1662	 * isn't programmed, ahci automatically generates it from number
1663	 * of ports, which is good enough for PCS programming. It is
1664	 * otherwise expected that platform firmware enables the ports
1665	 * before the OS boots.
1666	 */
1667	pci_read_config_word(pdev, PCS_6, &tmp16);
1668	if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1669		tmp16 |= hpriv->port_map;
1670		pci_write_config_word(pdev, PCS_6, tmp16);
1671	}
1672}
1673
1674static ssize_t remapped_nvme_show(struct device *dev,
1675				  struct device_attribute *attr,
1676				  char *buf)
1677{
1678	struct ata_host *host = dev_get_drvdata(dev);
1679	struct ahci_host_priv *hpriv = host->private_data;
1680
1681	return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1682}
1683
1684static DEVICE_ATTR_RO(remapped_nvme);
1685
1686static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1687{
1688	unsigned int board_id = ent->driver_data;
1689	struct ata_port_info pi = ahci_port_info[board_id];
1690	const struct ata_port_info *ppi[] = { &pi, NULL };
1691	struct device *dev = &pdev->dev;
1692	struct ahci_host_priv *hpriv;
1693	struct ata_host *host;
1694	int n_ports, i, rc;
1695	int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1696
 
 
1697	WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1698
1699	ata_print_version_once(&pdev->dev, DRV_VERSION);
1700
1701	/* The AHCI driver can only drive the SATA ports, the PATA driver
1702	   can drive them all so if both drivers are selected make sure
1703	   AHCI stays out of the way */
1704	if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1705		return -ENODEV;
1706
1707	/* Apple BIOS on MCP89 prevents us using AHCI */
1708	if (is_mcp89_apple(pdev))
1709		ahci_mcp89_apple_enable(pdev);
1710
1711	/* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1712	 * At the moment, we can only use the AHCI mode. Let the users know
1713	 * that for SAS drives they're out of luck.
1714	 */
1715	if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1716		dev_info(&pdev->dev,
1717			 "PDC42819 can only drive SATA devices with this driver\n");
1718
1719	/* Some devices use non-standard BARs */
1720	if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1721		ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1722	else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1723		ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1724	else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1725		if (pdev->device == 0xa01c)
1726			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1727		if (pdev->device == 0xa084)
1728			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1729	} else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1730		if (pdev->device == 0x7a08)
1731			ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1732	}
1733
1734	/* acquire resources */
1735	rc = pcim_enable_device(pdev);
1736	if (rc)
1737		return rc;
1738
1739	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1740	    (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1741		u8 map;
1742
1743		/* ICH6s share the same PCI ID for both piix and ahci
1744		 * modes.  Enabling ahci mode while MAP indicates
1745		 * combined mode is a bad idea.  Yield to ata_piix.
1746		 */
1747		pci_read_config_byte(pdev, ICH_MAP, &map);
1748		if (map & 0x3) {
1749			dev_info(&pdev->dev,
1750				 "controller is in combined mode, can't enable AHCI mode\n");
1751			return -ENODEV;
1752		}
1753	}
1754
1755	/* AHCI controllers often implement SFF compatible interface.
1756	 * Grab all PCI BARs just in case.
1757	 */
1758	rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1759	if (rc == -EBUSY)
1760		pcim_pin_device(pdev);
1761	if (rc)
1762		return rc;
1763
1764	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1765	if (!hpriv)
1766		return -ENOMEM;
1767	hpriv->flags |= (unsigned long)pi.private_data;
1768
1769	/* MCP65 revision A1 and A2 can't do MSI */
1770	if (board_id == board_ahci_mcp65 &&
1771	    (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1772		hpriv->flags |= AHCI_HFLAG_NO_MSI;
1773
1774	/* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1775	if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1776		hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1777
1778	/* only some SB600s can do 64bit DMA */
1779	if (ahci_sb600_enable_64bit(pdev))
1780		hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1781
1782	hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1783
1784	/* detect remapped nvme devices */
1785	ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1786
1787	sysfs_add_file_to_group(&pdev->dev.kobj,
1788				&dev_attr_remapped_nvme.attr,
1789				NULL);
1790
1791	/* must set flag prior to save config in order to take effect */
1792	if (ahci_broken_devslp(pdev))
1793		hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1794
1795#ifdef CONFIG_ARM64
1796	if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1797	    pdev->device == 0xa235 &&
1798	    pdev->revision < 0x30)
1799		hpriv->flags |= AHCI_HFLAG_NO_SXS;
1800
1801	if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1802		hpriv->irq_handler = ahci_thunderx_irq_handler;
1803#endif
1804
1805	/* save initial config */
1806	ahci_pci_save_initial_config(pdev, hpriv);
1807
 
 
 
 
 
 
1808	/* prepare host */
1809	if (hpriv->cap & HOST_CAP_NCQ) {
1810		pi.flags |= ATA_FLAG_NCQ;
1811		/*
1812		 * Auto-activate optimization is supposed to be
1813		 * supported on all AHCI controllers indicating NCQ
1814		 * capability, but it seems to be broken on some
1815		 * chipsets including NVIDIAs.
1816		 */
1817		if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1818			pi.flags |= ATA_FLAG_FPDMA_AA;
1819
1820		/*
1821		 * All AHCI controllers should be forward-compatible
1822		 * with the new auxiliary field. This code should be
1823		 * conditionalized if any buggy AHCI controllers are
1824		 * encountered.
1825		 */
1826		pi.flags |= ATA_FLAG_FPDMA_AUX;
1827	}
1828
1829	if (hpriv->cap & HOST_CAP_PMP)
1830		pi.flags |= ATA_FLAG_PMP;
1831
1832	ahci_set_em_messages(hpriv, &pi);
1833
1834	if (ahci_broken_system_poweroff(pdev)) {
1835		pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1836		dev_info(&pdev->dev,
1837			"quirky BIOS, skipping spindown on poweroff\n");
1838	}
1839
1840	if (ahci_broken_lpm(pdev)) {
1841		pi.flags |= ATA_FLAG_NO_LPM;
1842		dev_warn(&pdev->dev,
1843			 "BIOS update required for Link Power Management support\n");
1844	}
1845
1846	if (ahci_broken_suspend(pdev)) {
1847		hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1848		dev_warn(&pdev->dev,
1849			 "BIOS update required for suspend/resume\n");
1850	}
1851
1852	if (ahci_broken_online(pdev)) {
1853		hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1854		dev_info(&pdev->dev,
1855			 "online status unreliable, applying workaround\n");
1856	}
1857
1858
1859	/* Acer SA5-271 workaround modifies private_data */
1860	acer_sa5_271_workaround(hpriv, pdev);
1861
1862	/* CAP.NP sometimes indicate the index of the last enabled
1863	 * port, at other times, that of the last possible port, so
1864	 * determining the maximum port number requires looking at
1865	 * both CAP.NP and port_map.
1866	 */
1867	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1868
1869	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1870	if (!host)
1871		return -ENOMEM;
1872	host->private_data = hpriv;
1873
1874	if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1875		/* legacy intx interrupts */
1876		pci_intx(pdev, 1);
1877	}
1878	hpriv->irq = pci_irq_vector(pdev, 0);
1879
1880	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1881		host->flags |= ATA_HOST_PARALLEL_SCAN;
1882	else
1883		dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1884
1885	if (pi.flags & ATA_FLAG_EM)
1886		ahci_reset_em(host);
1887
1888	for (i = 0; i < host->n_ports; i++) {
1889		struct ata_port *ap = host->ports[i];
1890
1891		ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1892		ata_port_pbar_desc(ap, ahci_pci_bar,
1893				   0x100 + ap->port_no * 0x80, "port");
1894
1895		/* set enclosure management message type */
1896		if (ap->flags & ATA_FLAG_EM)
1897			ap->em_message_type = hpriv->em_msg_type;
1898
1899		ahci_update_initial_lpm_policy(ap, hpriv);
1900
1901		/* disabled/not-implemented port */
1902		if (!(hpriv->port_map & (1 << i)))
1903			ap->ops = &ata_dummy_port_ops;
1904	}
1905
1906	/* apply workaround for ASUS P5W DH Deluxe mainboard */
1907	ahci_p5wdh_workaround(host);
1908
1909	/* apply gtf filter quirk */
1910	ahci_gtf_filter_workaround(host);
1911
1912	/* initialize adapter */
1913	rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1914	if (rc)
1915		return rc;
1916
1917	rc = ahci_pci_reset_controller(host);
1918	if (rc)
1919		return rc;
1920
1921	ahci_pci_init_controller(host);
1922	ahci_pci_print_info(host);
1923
1924	pci_set_master(pdev);
1925
1926	rc = ahci_host_activate(host, &ahci_sht);
1927	if (rc)
1928		return rc;
1929
1930	pm_runtime_put_noidle(&pdev->dev);
1931	return 0;
1932}
1933
1934static void ahci_shutdown_one(struct pci_dev *pdev)
1935{
1936	ata_pci_shutdown_one(pdev);
1937}
1938
1939static void ahci_remove_one(struct pci_dev *pdev)
1940{
1941	sysfs_remove_file_from_group(&pdev->dev.kobj,
1942				     &dev_attr_remapped_nvme.attr,
1943				     NULL);
1944	pm_runtime_get_noresume(&pdev->dev);
1945	ata_pci_remove_one(pdev);
1946}
1947
1948module_pci_driver(ahci_pci_driver);
1949
1950MODULE_AUTHOR("Jeff Garzik");
1951MODULE_DESCRIPTION("AHCI SATA low-level driver");
1952MODULE_LICENSE("GPL");
1953MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1954MODULE_VERSION(DRV_VERSION);