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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11/*
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
17 *
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
29 *
30 * Cycle bit rules:
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
35 *
36 * Producer rules:
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
40 * cycle state).
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
44 *
45 * Consumer rules:
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
53 */
54
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/dma-mapping.h>
58#include "xhci.h"
59#include "xhci-trace.h"
60
61static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
64
65/*
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
67 * address of the TRB.
68 */
69dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
70 union xhci_trb *trb)
71{
72 unsigned long segment_offset;
73
74 if (!seg || !trb || trb < seg->trbs)
75 return 0;
76 /* offset in TRBs */
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
79 return 0;
80 return seg->dma + (segment_offset * sizeof(*trb));
81}
82
83static bool trb_is_noop(union xhci_trb *trb)
84{
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
86}
87
88static bool trb_is_link(union xhci_trb *trb)
89{
90 return TRB_TYPE_LINK_LE32(trb->link.control);
91}
92
93static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
94{
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
96}
97
98static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
100{
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
102}
103
104static bool link_trb_toggles_cycle(union xhci_trb *trb)
105{
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
107}
108
109static bool last_td_in_urb(struct xhci_td *td)
110{
111 struct urb_priv *urb_priv = td->urb->hcpriv;
112
113 return urb_priv->num_tds_done == urb_priv->num_tds;
114}
115
116static void inc_td_cnt(struct urb *urb)
117{
118 struct urb_priv *urb_priv = urb->hcpriv;
119
120 urb_priv->num_tds_done++;
121}
122
123static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
124{
125 if (trb_is_link(trb)) {
126 /* unchain chained link TRBs */
127 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
128 } else {
129 trb->generic.field[0] = 0;
130 trb->generic.field[1] = 0;
131 trb->generic.field[2] = 0;
132 /* Preserve only the cycle bit of this TRB */
133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 }
136}
137
138/* Updates trb to point to the next TRB in the ring, and updates seg if the next
139 * TRB is in a new segment. This does not skip over link TRBs, and it does not
140 * effect the ring dequeue or enqueue pointers.
141 */
142static void next_trb(struct xhci_hcd *xhci,
143 struct xhci_ring *ring,
144 struct xhci_segment **seg,
145 union xhci_trb **trb)
146{
147 if (trb_is_link(*trb)) {
148 *seg = (*seg)->next;
149 *trb = ((*seg)->trbs);
150 } else {
151 (*trb)++;
152 }
153}
154
155/*
156 * See Cycle bit rules. SW is the consumer for the event ring only.
157 */
158void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
159{
160 unsigned int link_trb_count = 0;
161
162 /* event ring doesn't have link trbs, check for last trb */
163 if (ring->type == TYPE_EVENT) {
164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
165 ring->dequeue++;
166 goto out;
167 }
168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
169 ring->cycle_state ^= 1;
170 ring->deq_seg = ring->deq_seg->next;
171 ring->dequeue = ring->deq_seg->trbs;
172 goto out;
173 }
174
175 /* All other rings have link trbs */
176 if (!trb_is_link(ring->dequeue)) {
177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
178 xhci_warn(xhci, "Missing link TRB at end of segment\n");
179 } else {
180 ring->dequeue++;
181 ring->num_trbs_free++;
182 }
183 }
184
185 while (trb_is_link(ring->dequeue)) {
186 ring->deq_seg = ring->deq_seg->next;
187 ring->dequeue = ring->deq_seg->trbs;
188
189 if (link_trb_count++ > ring->num_segs) {
190 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
191 break;
192 }
193 }
194out:
195 trace_xhci_inc_deq(ring);
196
197 return;
198}
199
200/*
201 * See Cycle bit rules. SW is the consumer for the event ring only.
202 *
203 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
204 * chain bit is set), then set the chain bit in all the following link TRBs.
205 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
206 * have their chain bit cleared (so that each Link TRB is a separate TD).
207 *
208 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
209 * set, but other sections talk about dealing with the chain bit set. This was
210 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
211 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
212 *
213 * @more_trbs_coming: Will you enqueue more TRBs before calling
214 * prepare_transfer()?
215 */
216static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
217 bool more_trbs_coming)
218{
219 u32 chain;
220 union xhci_trb *next;
221 unsigned int link_trb_count = 0;
222
223 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
224 /* If this is not event ring, there is one less usable TRB */
225 if (!trb_is_link(ring->enqueue))
226 ring->num_trbs_free--;
227
228 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
229 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
230 return;
231 }
232
233 next = ++(ring->enqueue);
234
235 /* Update the dequeue pointer further if that was a link TRB */
236 while (trb_is_link(next)) {
237
238 /*
239 * If the caller doesn't plan on enqueueing more TDs before
240 * ringing the doorbell, then we don't want to give the link TRB
241 * to the hardware just yet. We'll give the link TRB back in
242 * prepare_ring() just before we enqueue the TD at the top of
243 * the ring.
244 */
245 if (!chain && !more_trbs_coming)
246 break;
247
248 /* If we're not dealing with 0.95 hardware or isoc rings on
249 * AMD 0.96 host, carry over the chain bit of the previous TRB
250 * (which may mean the chain bit is cleared).
251 */
252 if (!(ring->type == TYPE_ISOC &&
253 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
254 !xhci_link_trb_quirk(xhci)) {
255 next->link.control &= cpu_to_le32(~TRB_CHAIN);
256 next->link.control |= cpu_to_le32(chain);
257 }
258 /* Give this link TRB to the hardware */
259 wmb();
260 next->link.control ^= cpu_to_le32(TRB_CYCLE);
261
262 /* Toggle the cycle bit after the last ring segment. */
263 if (link_trb_toggles_cycle(next))
264 ring->cycle_state ^= 1;
265
266 ring->enq_seg = ring->enq_seg->next;
267 ring->enqueue = ring->enq_seg->trbs;
268 next = ring->enqueue;
269
270 if (link_trb_count++ > ring->num_segs) {
271 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
272 break;
273 }
274 }
275
276 trace_xhci_inc_enq(ring);
277}
278
279/*
280 * Check to see if there's room to enqueue num_trbs on the ring and make sure
281 * enqueue pointer will not advance into dequeue segment. See rules above.
282 */
283static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
284 unsigned int num_trbs)
285{
286 int num_trbs_in_deq_seg;
287
288 if (ring->num_trbs_free < num_trbs)
289 return 0;
290
291 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
292 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
293 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
294 return 0;
295 }
296
297 return 1;
298}
299
300/* Ring the host controller doorbell after placing a command on the ring */
301void xhci_ring_cmd_db(struct xhci_hcd *xhci)
302{
303 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
304 return;
305
306 xhci_dbg(xhci, "// Ding dong!\n");
307
308 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
309
310 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
311 /* Flush PCI posted writes */
312 readl(&xhci->dba->doorbell[0]);
313}
314
315static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
316{
317 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
318}
319
320static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
321{
322 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
323 cmd_list);
324}
325
326/*
327 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
328 * If there are other commands waiting then restart the ring and kick the timer.
329 * This must be called with command ring stopped and xhci->lock held.
330 */
331static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
332 struct xhci_command *cur_cmd)
333{
334 struct xhci_command *i_cmd;
335
336 /* Turn all aborted commands in list to no-ops, then restart */
337 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
338
339 if (i_cmd->status != COMP_COMMAND_ABORTED)
340 continue;
341
342 i_cmd->status = COMP_COMMAND_RING_STOPPED;
343
344 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
345 i_cmd->command_trb);
346
347 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
348
349 /*
350 * caller waiting for completion is called when command
351 * completion event is received for these no-op commands
352 */
353 }
354
355 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
356
357 /* ring command ring doorbell to restart the command ring */
358 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
359 !(xhci->xhc_state & XHCI_STATE_DYING)) {
360 xhci->current_cmd = cur_cmd;
361 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
362 xhci_ring_cmd_db(xhci);
363 }
364}
365
366/* Must be called with xhci->lock held, releases and aquires lock back */
367static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
368{
369 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
370 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
371 u64 crcr;
372 int ret;
373
374 xhci_dbg(xhci, "Abort command ring\n");
375
376 reinit_completion(&xhci->cmd_ring_stop_completion);
377
378 /*
379 * The control bits like command stop, abort are located in lower
380 * dword of the command ring control register.
381 * Some controllers require all 64 bits to be written to abort the ring.
382 * Make sure the upper dword is valid, pointing to the next command,
383 * avoiding corrupting the command ring pointer in case the command ring
384 * is stopped by the time the upper dword is written.
385 */
386 next_trb(xhci, NULL, &new_seg, &new_deq);
387 if (trb_is_link(new_deq))
388 next_trb(xhci, NULL, &new_seg, &new_deq);
389
390 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
391 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
392
393 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
394 * completion of the Command Abort operation. If CRR is not negated in 5
395 * seconds then driver handles it as if host died (-ENODEV).
396 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
397 * and try to recover a -ETIMEDOUT with a host controller reset.
398 */
399 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
400 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
401 if (ret < 0) {
402 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
403 xhci_halt(xhci);
404 xhci_hc_died(xhci);
405 return ret;
406 }
407 /*
408 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
409 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
410 * but the completion event in never sent. Wait 2 secs (arbitrary
411 * number) to handle those cases after negation of CMD_RING_RUNNING.
412 */
413 spin_unlock_irqrestore(&xhci->lock, flags);
414 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
415 msecs_to_jiffies(2000));
416 spin_lock_irqsave(&xhci->lock, flags);
417 if (!ret) {
418 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
419 xhci_cleanup_command_queue(xhci);
420 } else {
421 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
422 }
423 return 0;
424}
425
426void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
427 unsigned int slot_id,
428 unsigned int ep_index,
429 unsigned int stream_id)
430{
431 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
432 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
433 unsigned int ep_state = ep->ep_state;
434
435 /* Don't ring the doorbell for this endpoint if there are pending
436 * cancellations because we don't want to interrupt processing.
437 * We don't want to restart any stream rings if there's a set dequeue
438 * pointer command pending because the device can choose to start any
439 * stream once the endpoint is on the HW schedule.
440 */
441 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
442 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
443 return;
444
445 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
446
447 writel(DB_VALUE(ep_index, stream_id), db_addr);
448 /* flush the write */
449 readl(db_addr);
450}
451
452/* Ring the doorbell for any rings with pending URBs */
453static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
454 unsigned int slot_id,
455 unsigned int ep_index)
456{
457 unsigned int stream_id;
458 struct xhci_virt_ep *ep;
459
460 ep = &xhci->devs[slot_id]->eps[ep_index];
461
462 /* A ring has pending URBs if its TD list is not empty */
463 if (!(ep->ep_state & EP_HAS_STREAMS)) {
464 if (ep->ring && !(list_empty(&ep->ring->td_list)))
465 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
466 return;
467 }
468
469 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
470 stream_id++) {
471 struct xhci_stream_info *stream_info = ep->stream_info;
472 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
473 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
474 stream_id);
475 }
476}
477
478void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
479 unsigned int slot_id,
480 unsigned int ep_index)
481{
482 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
483}
484
485static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
486 unsigned int slot_id,
487 unsigned int ep_index)
488{
489 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
490 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
491 return NULL;
492 }
493 if (ep_index >= EP_CTX_PER_DEV) {
494 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
495 return NULL;
496 }
497 if (!xhci->devs[slot_id]) {
498 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
499 return NULL;
500 }
501
502 return &xhci->devs[slot_id]->eps[ep_index];
503}
504
505static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
506 struct xhci_virt_ep *ep,
507 unsigned int stream_id)
508{
509 /* common case, no streams */
510 if (!(ep->ep_state & EP_HAS_STREAMS))
511 return ep->ring;
512
513 if (!ep->stream_info)
514 return NULL;
515
516 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
517 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
518 stream_id, ep->vdev->slot_id, ep->ep_index);
519 return NULL;
520 }
521
522 return ep->stream_info->stream_rings[stream_id];
523}
524
525/* Get the right ring for the given slot_id, ep_index and stream_id.
526 * If the endpoint supports streams, boundary check the URB's stream ID.
527 * If the endpoint doesn't support streams, return the singular endpoint ring.
528 */
529struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
530 unsigned int slot_id, unsigned int ep_index,
531 unsigned int stream_id)
532{
533 struct xhci_virt_ep *ep;
534
535 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
536 if (!ep)
537 return NULL;
538
539 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
540}
541
542
543/*
544 * Get the hw dequeue pointer xHC stopped on, either directly from the
545 * endpoint context, or if streams are in use from the stream context.
546 * The returned hw_dequeue contains the lowest four bits with cycle state
547 * and possbile stream context type.
548 */
549static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
550 unsigned int ep_index, unsigned int stream_id)
551{
552 struct xhci_ep_ctx *ep_ctx;
553 struct xhci_stream_ctx *st_ctx;
554 struct xhci_virt_ep *ep;
555
556 ep = &vdev->eps[ep_index];
557
558 if (ep->ep_state & EP_HAS_STREAMS) {
559 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
560 return le64_to_cpu(st_ctx->stream_ring);
561 }
562 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
563 return le64_to_cpu(ep_ctx->deq);
564}
565
566static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
567 unsigned int slot_id, unsigned int ep_index,
568 unsigned int stream_id, struct xhci_td *td)
569{
570 struct xhci_virt_device *dev = xhci->devs[slot_id];
571 struct xhci_virt_ep *ep = &dev->eps[ep_index];
572 struct xhci_ring *ep_ring;
573 struct xhci_command *cmd;
574 struct xhci_segment *new_seg;
575 struct xhci_segment *halted_seg = NULL;
576 union xhci_trb *new_deq;
577 int new_cycle;
578 union xhci_trb *halted_trb;
579 int index = 0;
580 dma_addr_t addr;
581 u64 hw_dequeue;
582 bool cycle_found = false;
583 bool td_last_trb_found = false;
584 u32 trb_sct = 0;
585 int ret;
586
587 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
588 ep_index, stream_id);
589 if (!ep_ring) {
590 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
591 stream_id);
592 return -ENODEV;
593 }
594 /*
595 * A cancelled TD can complete with a stall if HW cached the trb.
596 * In this case driver can't find td, but if the ring is empty we
597 * can move the dequeue pointer to the current enqueue position.
598 * We shouldn't hit this anymore as cached cancelled TRBs are given back
599 * after clearing the cache, but be on the safe side and keep it anyway
600 */
601 if (!td) {
602 if (list_empty(&ep_ring->td_list)) {
603 new_seg = ep_ring->enq_seg;
604 new_deq = ep_ring->enqueue;
605 new_cycle = ep_ring->cycle_state;
606 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
607 goto deq_found;
608 } else {
609 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
610 return -EINVAL;
611 }
612 }
613
614 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
615 new_seg = ep_ring->deq_seg;
616 new_deq = ep_ring->dequeue;
617
618 /*
619 * Quirk: xHC write-back of the DCS field in the hardware dequeue
620 * pointer is wrong - use the cycle state of the TRB pointed to by
621 * the dequeue pointer.
622 */
623 if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS &&
624 !(ep->ep_state & EP_HAS_STREAMS))
625 halted_seg = trb_in_td(xhci, td->start_seg,
626 td->first_trb, td->last_trb,
627 hw_dequeue & ~0xf, false);
628 if (halted_seg) {
629 index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) /
630 sizeof(*halted_trb);
631 halted_trb = &halted_seg->trbs[index];
632 new_cycle = halted_trb->generic.field[3] & 0x1;
633 xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n",
634 (u8)(hw_dequeue & 0x1), index, new_cycle);
635 } else {
636 new_cycle = hw_dequeue & 0x1;
637 }
638
639 /*
640 * We want to find the pointer, segment and cycle state of the new trb
641 * (the one after current TD's last_trb). We know the cycle state at
642 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
643 * found.
644 */
645 do {
646 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
647 == (dma_addr_t)(hw_dequeue & ~0xf)) {
648 cycle_found = true;
649 if (td_last_trb_found)
650 break;
651 }
652 if (new_deq == td->last_trb)
653 td_last_trb_found = true;
654
655 if (cycle_found && trb_is_link(new_deq) &&
656 link_trb_toggles_cycle(new_deq))
657 new_cycle ^= 0x1;
658
659 next_trb(xhci, ep_ring, &new_seg, &new_deq);
660
661 /* Search wrapped around, bail out */
662 if (new_deq == ep->ring->dequeue) {
663 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
664 return -EINVAL;
665 }
666
667 } while (!cycle_found || !td_last_trb_found);
668
669deq_found:
670
671 /* Don't update the ring cycle state for the producer (us). */
672 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
673 if (addr == 0) {
674 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
675 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
676 return -EINVAL;
677 }
678
679 if ((ep->ep_state & SET_DEQ_PENDING)) {
680 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
681 &addr);
682 return -EBUSY;
683 }
684
685 /* This function gets called from contexts where it cannot sleep */
686 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
687 if (!cmd) {
688 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
689 return -ENOMEM;
690 }
691
692 if (stream_id)
693 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
694 ret = queue_command(xhci, cmd,
695 lower_32_bits(addr) | trb_sct | new_cycle,
696 upper_32_bits(addr),
697 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
698 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
699 if (ret < 0) {
700 xhci_free_command(xhci, cmd);
701 return ret;
702 }
703 ep->queued_deq_seg = new_seg;
704 ep->queued_deq_ptr = new_deq;
705
706 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
707 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
708
709 /* Stop the TD queueing code from ringing the doorbell until
710 * this command completes. The HC won't set the dequeue pointer
711 * if the ring is running, and ringing the doorbell starts the
712 * ring running.
713 */
714 ep->ep_state |= SET_DEQ_PENDING;
715 xhci_ring_cmd_db(xhci);
716 return 0;
717}
718
719/* flip_cycle means flip the cycle bit of all but the first and last TRB.
720 * (The last TRB actually points to the ring enqueue pointer, which is not part
721 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
722 */
723static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
724 struct xhci_td *td, bool flip_cycle)
725{
726 struct xhci_segment *seg = td->start_seg;
727 union xhci_trb *trb = td->first_trb;
728
729 while (1) {
730 trb_to_noop(trb, TRB_TR_NOOP);
731
732 /* flip cycle if asked to */
733 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
734 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
735
736 if (trb == td->last_trb)
737 break;
738
739 next_trb(xhci, ep_ring, &seg, &trb);
740 }
741}
742
743/*
744 * Must be called with xhci->lock held in interrupt context,
745 * releases and re-acquires xhci->lock
746 */
747static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
748 struct xhci_td *cur_td, int status)
749{
750 struct urb *urb = cur_td->urb;
751 struct urb_priv *urb_priv = urb->hcpriv;
752 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
753
754 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
755 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
756 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
757 if (xhci->quirks & XHCI_AMD_PLL_FIX)
758 usb_amd_quirk_pll_enable();
759 }
760 }
761 xhci_urb_free_priv(urb_priv);
762 usb_hcd_unlink_urb_from_ep(hcd, urb);
763 trace_xhci_urb_giveback(urb);
764 usb_hcd_giveback_urb(hcd, urb, status);
765}
766
767static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
768 struct xhci_ring *ring, struct xhci_td *td)
769{
770 struct device *dev = xhci_to_hcd(xhci)->self.controller;
771 struct xhci_segment *seg = td->bounce_seg;
772 struct urb *urb = td->urb;
773 size_t len;
774
775 if (!ring || !seg || !urb)
776 return;
777
778 if (usb_urb_dir_out(urb)) {
779 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
780 DMA_TO_DEVICE);
781 return;
782 }
783
784 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
785 DMA_FROM_DEVICE);
786 /* for in tranfers we need to copy the data from bounce to sg */
787 if (urb->num_sgs) {
788 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
789 seg->bounce_len, seg->bounce_offs);
790 if (len != seg->bounce_len)
791 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
792 len, seg->bounce_len);
793 } else {
794 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
795 seg->bounce_len);
796 }
797 seg->bounce_len = 0;
798 seg->bounce_offs = 0;
799}
800
801static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
802 struct xhci_ring *ep_ring, int status)
803{
804 struct urb *urb = NULL;
805
806 /* Clean up the endpoint's TD list */
807 urb = td->urb;
808
809 /* if a bounce buffer was used to align this td then unmap it */
810 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
811
812 /* Do one last check of the actual transfer length.
813 * If the host controller said we transferred more data than the buffer
814 * length, urb->actual_length will be a very big number (since it's
815 * unsigned). Play it safe and say we didn't transfer anything.
816 */
817 if (urb->actual_length > urb->transfer_buffer_length) {
818 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
819 urb->transfer_buffer_length, urb->actual_length);
820 urb->actual_length = 0;
821 status = 0;
822 }
823 /* TD might be removed from td_list if we are giving back a cancelled URB */
824 if (!list_empty(&td->td_list))
825 list_del_init(&td->td_list);
826 /* Giving back a cancelled URB, or if a slated TD completed anyway */
827 if (!list_empty(&td->cancelled_td_list))
828 list_del_init(&td->cancelled_td_list);
829
830 inc_td_cnt(urb);
831 /* Giveback the urb when all the tds are completed */
832 if (last_td_in_urb(td)) {
833 if ((urb->actual_length != urb->transfer_buffer_length &&
834 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
835 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
836 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
837 urb, urb->actual_length,
838 urb->transfer_buffer_length, status);
839
840 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
841 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
842 status = 0;
843 xhci_giveback_urb_in_irq(xhci, td, status);
844 }
845
846 return 0;
847}
848
849
850/* Complete the cancelled URBs we unlinked from td_list. */
851static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
852{
853 struct xhci_ring *ring;
854 struct xhci_td *td, *tmp_td;
855
856 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
857 cancelled_td_list) {
858
859 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
860
861 if (td->cancel_status == TD_CLEARED) {
862 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
863 __func__, td->urb);
864 xhci_td_cleanup(ep->xhci, td, ring, td->status);
865 } else {
866 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
867 __func__, td->urb, td->cancel_status);
868 }
869 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
870 return;
871 }
872}
873
874static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
875 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
876{
877 struct xhci_command *command;
878 int ret = 0;
879
880 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
881 if (!command) {
882 ret = -ENOMEM;
883 goto done;
884 }
885
886 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
887 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
888 ep_index, slot_id);
889
890 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
891done:
892 if (ret)
893 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
894 slot_id, ep_index, ret);
895 return ret;
896}
897
898static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
899 struct xhci_virt_ep *ep,
900 struct xhci_td *td,
901 enum xhci_ep_reset_type reset_type)
902{
903 unsigned int slot_id = ep->vdev->slot_id;
904 int err;
905
906 /*
907 * Avoid resetting endpoint if link is inactive. Can cause host hang.
908 * Device will be reset soon to recover the link so don't do anything
909 */
910 if (ep->vdev->flags & VDEV_PORT_ERROR)
911 return -ENODEV;
912
913 /* add td to cancelled list and let reset ep handler take care of it */
914 if (reset_type == EP_HARD_RESET) {
915 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
916 if (td && list_empty(&td->cancelled_td_list)) {
917 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
918 td->cancel_status = TD_HALTED;
919 }
920 }
921
922 if (ep->ep_state & EP_HALTED) {
923 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
924 ep->ep_index);
925 return 0;
926 }
927
928 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
929 if (err)
930 return err;
931
932 ep->ep_state |= EP_HALTED;
933
934 xhci_ring_cmd_db(xhci);
935
936 return 0;
937}
938
939/*
940 * Fix up the ep ring first, so HW stops executing cancelled TDs.
941 * We have the xHCI lock, so nothing can modify this list until we drop it.
942 * We're also in the event handler, so we can't get re-interrupted if another
943 * Stop Endpoint command completes.
944 *
945 * only call this when ring is not in a running state
946 */
947
948static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
949{
950 struct xhci_hcd *xhci;
951 struct xhci_td *td = NULL;
952 struct xhci_td *tmp_td = NULL;
953 struct xhci_td *cached_td = NULL;
954 struct xhci_ring *ring;
955 u64 hw_deq;
956 unsigned int slot_id = ep->vdev->slot_id;
957 int err;
958
959 xhci = ep->xhci;
960
961 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
962 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
963 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
964 (unsigned long long)xhci_trb_virt_to_dma(
965 td->start_seg, td->first_trb),
966 td->urb->stream_id, td->urb);
967 list_del_init(&td->td_list);
968 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
969 if (!ring) {
970 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
971 td->urb, td->urb->stream_id);
972 continue;
973 }
974 /*
975 * If a ring stopped on the TD we need to cancel then we have to
976 * move the xHC endpoint ring dequeue pointer past this TD.
977 * Rings halted due to STALL may show hw_deq is past the stalled
978 * TD, but still require a set TR Deq command to flush xHC cache.
979 */
980 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
981 td->urb->stream_id);
982 hw_deq &= ~0xf;
983
984 if (td->cancel_status == TD_HALTED ||
985 trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
986 switch (td->cancel_status) {
987 case TD_CLEARED: /* TD is already no-op */
988 case TD_CLEARING_CACHE: /* set TR deq command already queued */
989 break;
990 case TD_DIRTY: /* TD is cached, clear it */
991 case TD_HALTED:
992 td->cancel_status = TD_CLEARING_CACHE;
993 if (cached_td)
994 /* FIXME stream case, several stopped rings */
995 xhci_dbg(xhci,
996 "Move dq past stream %u URB %p instead of stream %u URB %p\n",
997 td->urb->stream_id, td->urb,
998 cached_td->urb->stream_id, cached_td->urb);
999 cached_td = td;
1000 break;
1001 }
1002 } else {
1003 td_to_noop(xhci, ring, td, false);
1004 td->cancel_status = TD_CLEARED;
1005 }
1006 }
1007
1008 /* If there's no need to move the dequeue pointer then we're done */
1009 if (!cached_td)
1010 return 0;
1011
1012 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1013 cached_td->urb->stream_id,
1014 cached_td);
1015 if (err) {
1016 /* Failed to move past cached td, just set cached TDs to no-op */
1017 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1018 if (td->cancel_status != TD_CLEARING_CACHE)
1019 continue;
1020 xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1021 td->urb);
1022 td_to_noop(xhci, ring, td, false);
1023 td->cancel_status = TD_CLEARED;
1024 }
1025 }
1026 return 0;
1027}
1028
1029/*
1030 * Returns the TD the endpoint ring halted on.
1031 * Only call for non-running rings without streams.
1032 */
1033static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1034{
1035 struct xhci_td *td;
1036 u64 hw_deq;
1037
1038 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1039 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1040 hw_deq &= ~0xf;
1041 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1042 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1043 td->last_trb, hw_deq, false))
1044 return td;
1045 }
1046 return NULL;
1047}
1048
1049/*
1050 * When we get a command completion for a Stop Endpoint Command, we need to
1051 * unlink any cancelled TDs from the ring. There are two ways to do that:
1052 *
1053 * 1. If the HW was in the middle of processing the TD that needs to be
1054 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1055 * in the TD with a Set Dequeue Pointer Command.
1056 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1057 * bit cleared) so that the HW will skip over them.
1058 */
1059static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1060 union xhci_trb *trb, u32 comp_code)
1061{
1062 unsigned int ep_index;
1063 struct xhci_virt_ep *ep;
1064 struct xhci_ep_ctx *ep_ctx;
1065 struct xhci_td *td = NULL;
1066 enum xhci_ep_reset_type reset_type;
1067 struct xhci_command *command;
1068 int err;
1069
1070 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1071 if (!xhci->devs[slot_id])
1072 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1073 slot_id);
1074 return;
1075 }
1076
1077 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1078 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1079 if (!ep)
1080 return;
1081
1082 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1083
1084 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1085
1086 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1087 /*
1088 * If stop endpoint command raced with a halting endpoint we need to
1089 * reset the host side endpoint first.
1090 * If the TD we halted on isn't cancelled the TD should be given back
1091 * with a proper error code, and the ring dequeue moved past the TD.
1092 * If streams case we can't find hw_deq, or the TD we halted on so do a
1093 * soft reset.
1094 *
1095 * Proper error code is unknown here, it would be -EPIPE if device side
1096 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1097 * We use -EPROTO, if device is stalled it should return a stall error on
1098 * next transfer, which then will return -EPIPE, and device side stall is
1099 * noted and cleared by class driver.
1100 */
1101 switch (GET_EP_CTX_STATE(ep_ctx)) {
1102 case EP_STATE_HALTED:
1103 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1104 if (ep->ep_state & EP_HAS_STREAMS) {
1105 reset_type = EP_SOFT_RESET;
1106 } else {
1107 reset_type = EP_HARD_RESET;
1108 td = find_halted_td(ep);
1109 if (td)
1110 td->status = -EPROTO;
1111 }
1112 /* reset ep, reset handler cleans up cancelled tds */
1113 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1114 if (err)
1115 break;
1116 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1117 return;
1118 case EP_STATE_RUNNING:
1119 /* Race, HW handled stop ep cmd before ep was running */
1120 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
1121
1122 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1123 if (!command) {
1124 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1125 return;
1126 }
1127 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1128 xhci_ring_cmd_db(xhci);
1129
1130 return;
1131 default:
1132 break;
1133 }
1134 }
1135
1136 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1137 xhci_invalidate_cancelled_tds(ep);
1138 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1139
1140 /* Otherwise ring the doorbell(s) to restart queued transfers */
1141 xhci_giveback_invalidated_tds(ep);
1142 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1143}
1144
1145static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1146{
1147 struct xhci_td *cur_td;
1148 struct xhci_td *tmp;
1149
1150 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1151 list_del_init(&cur_td->td_list);
1152
1153 if (!list_empty(&cur_td->cancelled_td_list))
1154 list_del_init(&cur_td->cancelled_td_list);
1155
1156 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1157
1158 inc_td_cnt(cur_td->urb);
1159 if (last_td_in_urb(cur_td))
1160 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1161 }
1162}
1163
1164static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1165 int slot_id, int ep_index)
1166{
1167 struct xhci_td *cur_td;
1168 struct xhci_td *tmp;
1169 struct xhci_virt_ep *ep;
1170 struct xhci_ring *ring;
1171
1172 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1173 if (!ep)
1174 return;
1175
1176 if ((ep->ep_state & EP_HAS_STREAMS) ||
1177 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1178 int stream_id;
1179
1180 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1181 stream_id++) {
1182 ring = ep->stream_info->stream_rings[stream_id];
1183 if (!ring)
1184 continue;
1185
1186 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1187 "Killing URBs for slot ID %u, ep index %u, stream %u",
1188 slot_id, ep_index, stream_id);
1189 xhci_kill_ring_urbs(xhci, ring);
1190 }
1191 } else {
1192 ring = ep->ring;
1193 if (!ring)
1194 return;
1195 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1196 "Killing URBs for slot ID %u, ep index %u",
1197 slot_id, ep_index);
1198 xhci_kill_ring_urbs(xhci, ring);
1199 }
1200
1201 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1202 cancelled_td_list) {
1203 list_del_init(&cur_td->cancelled_td_list);
1204 inc_td_cnt(cur_td->urb);
1205
1206 if (last_td_in_urb(cur_td))
1207 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1208 }
1209}
1210
1211/*
1212 * host controller died, register read returns 0xffffffff
1213 * Complete pending commands, mark them ABORTED.
1214 * URBs need to be given back as usb core might be waiting with device locks
1215 * held for the URBs to finish during device disconnect, blocking host remove.
1216 *
1217 * Call with xhci->lock held.
1218 * lock is relased and re-acquired while giving back urb.
1219 */
1220void xhci_hc_died(struct xhci_hcd *xhci)
1221{
1222 int i, j;
1223
1224 if (xhci->xhc_state & XHCI_STATE_DYING)
1225 return;
1226
1227 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1228 xhci->xhc_state |= XHCI_STATE_DYING;
1229
1230 xhci_cleanup_command_queue(xhci);
1231
1232 /* return any pending urbs, remove may be waiting for them */
1233 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1234 if (!xhci->devs[i])
1235 continue;
1236 for (j = 0; j < 31; j++)
1237 xhci_kill_endpoint_urbs(xhci, i, j);
1238 }
1239
1240 /* inform usb core hc died if PCI remove isn't already handling it */
1241 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1242 usb_hc_died(xhci_to_hcd(xhci));
1243}
1244
1245static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1246 struct xhci_virt_device *dev,
1247 struct xhci_ring *ep_ring,
1248 unsigned int ep_index)
1249{
1250 union xhci_trb *dequeue_temp;
1251 int num_trbs_free_temp;
1252 bool revert = false;
1253
1254 num_trbs_free_temp = ep_ring->num_trbs_free;
1255 dequeue_temp = ep_ring->dequeue;
1256
1257 /* If we get two back-to-back stalls, and the first stalled transfer
1258 * ends just before a link TRB, the dequeue pointer will be left on
1259 * the link TRB by the code in the while loop. So we have to update
1260 * the dequeue pointer one segment further, or we'll jump off
1261 * the segment into la-la-land.
1262 */
1263 if (trb_is_link(ep_ring->dequeue)) {
1264 ep_ring->deq_seg = ep_ring->deq_seg->next;
1265 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1266 }
1267
1268 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1269 /* We have more usable TRBs */
1270 ep_ring->num_trbs_free++;
1271 ep_ring->dequeue++;
1272 if (trb_is_link(ep_ring->dequeue)) {
1273 if (ep_ring->dequeue ==
1274 dev->eps[ep_index].queued_deq_ptr)
1275 break;
1276 ep_ring->deq_seg = ep_ring->deq_seg->next;
1277 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1278 }
1279 if (ep_ring->dequeue == dequeue_temp) {
1280 revert = true;
1281 break;
1282 }
1283 }
1284
1285 if (revert) {
1286 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1287 ep_ring->num_trbs_free = num_trbs_free_temp;
1288 }
1289}
1290
1291/*
1292 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1293 * we need to clear the set deq pending flag in the endpoint ring state, so that
1294 * the TD queueing code can ring the doorbell again. We also need to ring the
1295 * endpoint doorbell to restart the ring, but only if there aren't more
1296 * cancellations pending.
1297 */
1298static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1299 union xhci_trb *trb, u32 cmd_comp_code)
1300{
1301 unsigned int ep_index;
1302 unsigned int stream_id;
1303 struct xhci_ring *ep_ring;
1304 struct xhci_virt_ep *ep;
1305 struct xhci_ep_ctx *ep_ctx;
1306 struct xhci_slot_ctx *slot_ctx;
1307 struct xhci_td *td, *tmp_td;
1308
1309 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1310 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1311 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1312 if (!ep)
1313 return;
1314
1315 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1316 if (!ep_ring) {
1317 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1318 stream_id);
1319 /* XXX: Harmless??? */
1320 goto cleanup;
1321 }
1322
1323 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1324 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1325 trace_xhci_handle_cmd_set_deq(slot_ctx);
1326 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1327
1328 if (cmd_comp_code != COMP_SUCCESS) {
1329 unsigned int ep_state;
1330 unsigned int slot_state;
1331
1332 switch (cmd_comp_code) {
1333 case COMP_TRB_ERROR:
1334 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1335 break;
1336 case COMP_CONTEXT_STATE_ERROR:
1337 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1338 ep_state = GET_EP_CTX_STATE(ep_ctx);
1339 slot_state = le32_to_cpu(slot_ctx->dev_state);
1340 slot_state = GET_SLOT_STATE(slot_state);
1341 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1342 "Slot state = %u, EP state = %u",
1343 slot_state, ep_state);
1344 break;
1345 case COMP_SLOT_NOT_ENABLED_ERROR:
1346 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1347 slot_id);
1348 break;
1349 default:
1350 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1351 cmd_comp_code);
1352 break;
1353 }
1354 /* OK what do we do now? The endpoint state is hosed, and we
1355 * should never get to this point if the synchronization between
1356 * queueing, and endpoint state are correct. This might happen
1357 * if the device gets disconnected after we've finished
1358 * cancelling URBs, which might not be an error...
1359 */
1360 } else {
1361 u64 deq;
1362 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1363 if (ep->ep_state & EP_HAS_STREAMS) {
1364 struct xhci_stream_ctx *ctx =
1365 &ep->stream_info->stream_ctx_array[stream_id];
1366 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1367 } else {
1368 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1369 }
1370 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1371 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1372 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1373 ep->queued_deq_ptr) == deq) {
1374 /* Update the ring's dequeue segment and dequeue pointer
1375 * to reflect the new position.
1376 */
1377 update_ring_for_set_deq_completion(xhci, ep->vdev,
1378 ep_ring, ep_index);
1379 } else {
1380 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1381 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1382 ep->queued_deq_seg, ep->queued_deq_ptr);
1383 }
1384 }
1385 /* HW cached TDs cleared from cache, give them back */
1386 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1387 cancelled_td_list) {
1388 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1389 if (td->cancel_status == TD_CLEARING_CACHE) {
1390 td->cancel_status = TD_CLEARED;
1391 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1392 __func__, td->urb);
1393 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1394 } else {
1395 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1396 __func__, td->urb, td->cancel_status);
1397 }
1398 }
1399cleanup:
1400 ep->ep_state &= ~SET_DEQ_PENDING;
1401 ep->queued_deq_seg = NULL;
1402 ep->queued_deq_ptr = NULL;
1403 /* Restart any rings with pending URBs */
1404 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1405}
1406
1407static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1408 union xhci_trb *trb, u32 cmd_comp_code)
1409{
1410 struct xhci_virt_ep *ep;
1411 struct xhci_ep_ctx *ep_ctx;
1412 unsigned int ep_index;
1413
1414 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1415 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1416 if (!ep)
1417 return;
1418
1419 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1420 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1421
1422 /* This command will only fail if the endpoint wasn't halted,
1423 * but we don't care.
1424 */
1425 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1426 "Ignoring reset ep completion code of %u", cmd_comp_code);
1427
1428 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1429 xhci_invalidate_cancelled_tds(ep);
1430
1431 /* Clear our internal halted state */
1432 ep->ep_state &= ~EP_HALTED;
1433
1434 xhci_giveback_invalidated_tds(ep);
1435
1436 /* if this was a soft reset, then restart */
1437 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1438 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1439}
1440
1441static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1442 struct xhci_command *command, u32 cmd_comp_code)
1443{
1444 if (cmd_comp_code == COMP_SUCCESS)
1445 command->slot_id = slot_id;
1446 else
1447 command->slot_id = 0;
1448}
1449
1450static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1451{
1452 struct xhci_virt_device *virt_dev;
1453 struct xhci_slot_ctx *slot_ctx;
1454
1455 virt_dev = xhci->devs[slot_id];
1456 if (!virt_dev)
1457 return;
1458
1459 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1460 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1461
1462 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1463 /* Delete default control endpoint resources */
1464 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1465}
1466
1467static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1468 u32 cmd_comp_code)
1469{
1470 struct xhci_virt_device *virt_dev;
1471 struct xhci_input_control_ctx *ctrl_ctx;
1472 struct xhci_ep_ctx *ep_ctx;
1473 unsigned int ep_index;
1474 u32 add_flags;
1475
1476 /*
1477 * Configure endpoint commands can come from the USB core configuration
1478 * or alt setting changes, or when streams were being configured.
1479 */
1480
1481 virt_dev = xhci->devs[slot_id];
1482 if (!virt_dev)
1483 return;
1484 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1485 if (!ctrl_ctx) {
1486 xhci_warn(xhci, "Could not get input context, bad type.\n");
1487 return;
1488 }
1489
1490 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1491
1492 /* Input ctx add_flags are the endpoint index plus one */
1493 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1494
1495 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1496 trace_xhci_handle_cmd_config_ep(ep_ctx);
1497
1498 return;
1499}
1500
1501static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1502{
1503 struct xhci_virt_device *vdev;
1504 struct xhci_slot_ctx *slot_ctx;
1505
1506 vdev = xhci->devs[slot_id];
1507 if (!vdev)
1508 return;
1509 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1510 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1511}
1512
1513static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1514{
1515 struct xhci_virt_device *vdev;
1516 struct xhci_slot_ctx *slot_ctx;
1517
1518 vdev = xhci->devs[slot_id];
1519 if (!vdev) {
1520 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1521 slot_id);
1522 return;
1523 }
1524 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1525 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1526
1527 xhci_dbg(xhci, "Completed reset device command.\n");
1528}
1529
1530static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1531 struct xhci_event_cmd *event)
1532{
1533 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1534 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1535 return;
1536 }
1537 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1538 "NEC firmware version %2x.%02x",
1539 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1540 NEC_FW_MINOR(le32_to_cpu(event->status)));
1541}
1542
1543static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1544{
1545 list_del(&cmd->cmd_list);
1546
1547 if (cmd->completion) {
1548 cmd->status = status;
1549 complete(cmd->completion);
1550 } else {
1551 kfree(cmd);
1552 }
1553}
1554
1555void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1556{
1557 struct xhci_command *cur_cmd, *tmp_cmd;
1558 xhci->current_cmd = NULL;
1559 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1560 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1561}
1562
1563void xhci_handle_command_timeout(struct work_struct *work)
1564{
1565 struct xhci_hcd *xhci;
1566 unsigned long flags;
1567 char str[XHCI_MSG_MAX];
1568 u64 hw_ring_state;
1569 u32 cmd_field3;
1570 u32 usbsts;
1571
1572 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1573
1574 spin_lock_irqsave(&xhci->lock, flags);
1575
1576 /*
1577 * If timeout work is pending, or current_cmd is NULL, it means we
1578 * raced with command completion. Command is handled so just return.
1579 */
1580 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1581 spin_unlock_irqrestore(&xhci->lock, flags);
1582 return;
1583 }
1584
1585 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1586 usbsts = readl(&xhci->op_regs->status);
1587 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1588
1589 /* Bail out and tear down xhci if a stop endpoint command failed */
1590 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1591 struct xhci_virt_ep *ep;
1592
1593 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1594
1595 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1596 TRB_TO_EP_INDEX(cmd_field3));
1597 if (ep)
1598 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1599
1600 xhci_halt(xhci);
1601 xhci_hc_died(xhci);
1602 goto time_out_completed;
1603 }
1604
1605 /* mark this command to be cancelled */
1606 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1607
1608 /* Make sure command ring is running before aborting it */
1609 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1610 if (hw_ring_state == ~(u64)0) {
1611 xhci_hc_died(xhci);
1612 goto time_out_completed;
1613 }
1614
1615 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1616 (hw_ring_state & CMD_RING_RUNNING)) {
1617 /* Prevent new doorbell, and start command abort */
1618 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1619 xhci_dbg(xhci, "Command timeout\n");
1620 xhci_abort_cmd_ring(xhci, flags);
1621 goto time_out_completed;
1622 }
1623
1624 /* host removed. Bail out */
1625 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1626 xhci_dbg(xhci, "host removed, ring start fail?\n");
1627 xhci_cleanup_command_queue(xhci);
1628
1629 goto time_out_completed;
1630 }
1631
1632 /* command timeout on stopped ring, ring can't be aborted */
1633 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1634 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1635
1636time_out_completed:
1637 spin_unlock_irqrestore(&xhci->lock, flags);
1638 return;
1639}
1640
1641static void handle_cmd_completion(struct xhci_hcd *xhci,
1642 struct xhci_event_cmd *event)
1643{
1644 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1645 u64 cmd_dma;
1646 dma_addr_t cmd_dequeue_dma;
1647 u32 cmd_comp_code;
1648 union xhci_trb *cmd_trb;
1649 struct xhci_command *cmd;
1650 u32 cmd_type;
1651
1652 if (slot_id >= MAX_HC_SLOTS) {
1653 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1654 return;
1655 }
1656
1657 cmd_dma = le64_to_cpu(event->cmd_trb);
1658 cmd_trb = xhci->cmd_ring->dequeue;
1659
1660 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1661
1662 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1663 cmd_trb);
1664 /*
1665 * Check whether the completion event is for our internal kept
1666 * command.
1667 */
1668 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1669 xhci_warn(xhci,
1670 "ERROR mismatched command completion event\n");
1671 return;
1672 }
1673
1674 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1675
1676 cancel_delayed_work(&xhci->cmd_timer);
1677
1678 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1679
1680 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1681 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1682 complete_all(&xhci->cmd_ring_stop_completion);
1683 return;
1684 }
1685
1686 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1687 xhci_err(xhci,
1688 "Command completion event does not match command\n");
1689 return;
1690 }
1691
1692 /*
1693 * Host aborted the command ring, check if the current command was
1694 * supposed to be aborted, otherwise continue normally.
1695 * The command ring is stopped now, but the xHC will issue a Command
1696 * Ring Stopped event which will cause us to restart it.
1697 */
1698 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1699 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1700 if (cmd->status == COMP_COMMAND_ABORTED) {
1701 if (xhci->current_cmd == cmd)
1702 xhci->current_cmd = NULL;
1703 goto event_handled;
1704 }
1705 }
1706
1707 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1708 switch (cmd_type) {
1709 case TRB_ENABLE_SLOT:
1710 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1711 break;
1712 case TRB_DISABLE_SLOT:
1713 xhci_handle_cmd_disable_slot(xhci, slot_id);
1714 break;
1715 case TRB_CONFIG_EP:
1716 if (!cmd->completion)
1717 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1718 break;
1719 case TRB_EVAL_CONTEXT:
1720 break;
1721 case TRB_ADDR_DEV:
1722 xhci_handle_cmd_addr_dev(xhci, slot_id);
1723 break;
1724 case TRB_STOP_RING:
1725 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1726 le32_to_cpu(cmd_trb->generic.field[3])));
1727 if (!cmd->completion)
1728 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1729 cmd_comp_code);
1730 break;
1731 case TRB_SET_DEQ:
1732 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1733 le32_to_cpu(cmd_trb->generic.field[3])));
1734 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1735 break;
1736 case TRB_CMD_NOOP:
1737 /* Is this an aborted command turned to NO-OP? */
1738 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1739 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1740 break;
1741 case TRB_RESET_EP:
1742 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1743 le32_to_cpu(cmd_trb->generic.field[3])));
1744 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1745 break;
1746 case TRB_RESET_DEV:
1747 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1748 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1749 */
1750 slot_id = TRB_TO_SLOT_ID(
1751 le32_to_cpu(cmd_trb->generic.field[3]));
1752 xhci_handle_cmd_reset_dev(xhci, slot_id);
1753 break;
1754 case TRB_NEC_GET_FW:
1755 xhci_handle_cmd_nec_get_fw(xhci, event);
1756 break;
1757 default:
1758 /* Skip over unknown commands on the event ring */
1759 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1760 break;
1761 }
1762
1763 /* restart timer if this wasn't the last command */
1764 if (!list_is_singular(&xhci->cmd_list)) {
1765 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1766 struct xhci_command, cmd_list);
1767 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1768 } else if (xhci->current_cmd == cmd) {
1769 xhci->current_cmd = NULL;
1770 }
1771
1772event_handled:
1773 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1774
1775 inc_deq(xhci, xhci->cmd_ring);
1776}
1777
1778static void handle_vendor_event(struct xhci_hcd *xhci,
1779 union xhci_trb *event, u32 trb_type)
1780{
1781 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1782 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1783 handle_cmd_completion(xhci, &event->event_cmd);
1784}
1785
1786static void handle_device_notification(struct xhci_hcd *xhci,
1787 union xhci_trb *event)
1788{
1789 u32 slot_id;
1790 struct usb_device *udev;
1791
1792 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1793 if (!xhci->devs[slot_id]) {
1794 xhci_warn(xhci, "Device Notification event for "
1795 "unused slot %u\n", slot_id);
1796 return;
1797 }
1798
1799 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1800 slot_id);
1801 udev = xhci->devs[slot_id]->udev;
1802 if (udev && udev->parent)
1803 usb_wakeup_notification(udev->parent, udev->portnum);
1804}
1805
1806/*
1807 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1808 * Controller.
1809 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1810 * If a connection to a USB 1 device is followed by another connection
1811 * to a USB 2 device.
1812 *
1813 * Reset the PHY after the USB device is disconnected if device speed
1814 * is less than HCD_USB3.
1815 * Retry the reset sequence max of 4 times checking the PLL lock status.
1816 *
1817 */
1818static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1819{
1820 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1821 u32 pll_lock_check;
1822 u32 retry_count = 4;
1823
1824 do {
1825 /* Assert PHY reset */
1826 writel(0x6F, hcd->regs + 0x1048);
1827 udelay(10);
1828 /* De-assert the PHY reset */
1829 writel(0x7F, hcd->regs + 0x1048);
1830 udelay(200);
1831 pll_lock_check = readl(hcd->regs + 0x1070);
1832 } while (!(pll_lock_check & 0x1) && --retry_count);
1833}
1834
1835static void handle_port_status(struct xhci_hcd *xhci,
1836 union xhci_trb *event)
1837{
1838 struct usb_hcd *hcd;
1839 u32 port_id;
1840 u32 portsc, cmd_reg;
1841 int max_ports;
1842 int slot_id;
1843 unsigned int hcd_portnum;
1844 struct xhci_bus_state *bus_state;
1845 bool bogus_port_status = false;
1846 struct xhci_port *port;
1847
1848 /* Port status change events always have a successful completion code */
1849 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1850 xhci_warn(xhci,
1851 "WARN: xHC returned failed port status event\n");
1852
1853 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1854 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1855
1856 if ((port_id <= 0) || (port_id > max_ports)) {
1857 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1858 port_id);
1859 inc_deq(xhci, xhci->event_ring);
1860 return;
1861 }
1862
1863 port = &xhci->hw_ports[port_id - 1];
1864 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1865 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1866 port_id);
1867 bogus_port_status = true;
1868 goto cleanup;
1869 }
1870
1871 /* We might get interrupts after shared_hcd is removed */
1872 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1873 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1874 bogus_port_status = true;
1875 goto cleanup;
1876 }
1877
1878 hcd = port->rhub->hcd;
1879 bus_state = &port->rhub->bus_state;
1880 hcd_portnum = port->hcd_portnum;
1881 portsc = readl(port->addr);
1882
1883 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1884 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1885
1886 trace_xhci_handle_port_status(hcd_portnum, portsc);
1887
1888 if (hcd->state == HC_STATE_SUSPENDED) {
1889 xhci_dbg(xhci, "resume root hub\n");
1890 usb_hcd_resume_root_hub(hcd);
1891 }
1892
1893 if (hcd->speed >= HCD_USB3 &&
1894 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1895 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1896 if (slot_id && xhci->devs[slot_id])
1897 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1898 }
1899
1900 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1901 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1902
1903 cmd_reg = readl(&xhci->op_regs->command);
1904 if (!(cmd_reg & CMD_RUN)) {
1905 xhci_warn(xhci, "xHC is not running.\n");
1906 goto cleanup;
1907 }
1908
1909 if (DEV_SUPERSPEED_ANY(portsc)) {
1910 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1911 /* Set a flag to say the port signaled remote wakeup,
1912 * so we can tell the difference between the end of
1913 * device and host initiated resume.
1914 */
1915 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1916 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1917 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1918 xhci_set_link_state(xhci, port, XDEV_U0);
1919 /* Need to wait until the next link state change
1920 * indicates the device is actually in U0.
1921 */
1922 bogus_port_status = true;
1923 goto cleanup;
1924 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1925 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1926 bus_state->resume_done[hcd_portnum] = jiffies +
1927 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1928 set_bit(hcd_portnum, &bus_state->resuming_ports);
1929 /* Do the rest in GetPortStatus after resume time delay.
1930 * Avoid polling roothub status before that so that a
1931 * usb device auto-resume latency around ~40ms.
1932 */
1933 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1934 mod_timer(&hcd->rh_timer,
1935 bus_state->resume_done[hcd_portnum]);
1936 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1937 bogus_port_status = true;
1938 }
1939 }
1940
1941 if ((portsc & PORT_PLC) &&
1942 DEV_SUPERSPEED_ANY(portsc) &&
1943 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1944 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1945 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1946 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1947 complete(&bus_state->u3exit_done[hcd_portnum]);
1948 /* We've just brought the device into U0/1/2 through either the
1949 * Resume state after a device remote wakeup, or through the
1950 * U3Exit state after a host-initiated resume. If it's a device
1951 * initiated remote wake, don't pass up the link state change,
1952 * so the roothub behavior is consistent with external
1953 * USB 3.0 hub behavior.
1954 */
1955 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1956 if (slot_id && xhci->devs[slot_id])
1957 xhci_ring_device(xhci, slot_id);
1958 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1959 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1960 usb_wakeup_notification(hcd->self.root_hub,
1961 hcd_portnum + 1);
1962 bogus_port_status = true;
1963 goto cleanup;
1964 }
1965 }
1966
1967 /*
1968 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1969 * RExit to a disconnect state). If so, let the driver know it's
1970 * out of the RExit state.
1971 */
1972 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1973 test_and_clear_bit(hcd_portnum,
1974 &bus_state->rexit_ports)) {
1975 complete(&bus_state->rexit_done[hcd_portnum]);
1976 bogus_port_status = true;
1977 goto cleanup;
1978 }
1979
1980 if (hcd->speed < HCD_USB3) {
1981 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1982 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1983 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1984 xhci_cavium_reset_phy_quirk(xhci);
1985 }
1986
1987cleanup:
1988 /* Update event ring dequeue pointer before dropping the lock */
1989 inc_deq(xhci, xhci->event_ring);
1990
1991 /* Don't make the USB core poll the roothub if we got a bad port status
1992 * change event. Besides, at that point we can't tell which roothub
1993 * (USB 2.0 or USB 3.0) to kick.
1994 */
1995 if (bogus_port_status)
1996 return;
1997
1998 /*
1999 * xHCI port-status-change events occur when the "or" of all the
2000 * status-change bits in the portsc register changes from 0 to 1.
2001 * New status changes won't cause an event if any other change
2002 * bits are still set. When an event occurs, switch over to
2003 * polling to avoid losing status changes.
2004 */
2005 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2006 __func__, hcd->self.busnum);
2007 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2008 spin_unlock(&xhci->lock);
2009 /* Pass this up to the core */
2010 usb_hcd_poll_rh_status(hcd);
2011 spin_lock(&xhci->lock);
2012}
2013
2014/*
2015 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2016 * at end_trb, which may be in another segment. If the suspect DMA address is a
2017 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2018 * returns 0.
2019 */
2020struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2021 struct xhci_segment *start_seg,
2022 union xhci_trb *start_trb,
2023 union xhci_trb *end_trb,
2024 dma_addr_t suspect_dma,
2025 bool debug)
2026{
2027 dma_addr_t start_dma;
2028 dma_addr_t end_seg_dma;
2029 dma_addr_t end_trb_dma;
2030 struct xhci_segment *cur_seg;
2031
2032 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2033 cur_seg = start_seg;
2034
2035 do {
2036 if (start_dma == 0)
2037 return NULL;
2038 /* We may get an event for a Link TRB in the middle of a TD */
2039 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2040 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2041 /* If the end TRB isn't in this segment, this is set to 0 */
2042 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2043
2044 if (debug)
2045 xhci_warn(xhci,
2046 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2047 (unsigned long long)suspect_dma,
2048 (unsigned long long)start_dma,
2049 (unsigned long long)end_trb_dma,
2050 (unsigned long long)cur_seg->dma,
2051 (unsigned long long)end_seg_dma);
2052
2053 if (end_trb_dma > 0) {
2054 /* The end TRB is in this segment, so suspect should be here */
2055 if (start_dma <= end_trb_dma) {
2056 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2057 return cur_seg;
2058 } else {
2059 /* Case for one segment with
2060 * a TD wrapped around to the top
2061 */
2062 if ((suspect_dma >= start_dma &&
2063 suspect_dma <= end_seg_dma) ||
2064 (suspect_dma >= cur_seg->dma &&
2065 suspect_dma <= end_trb_dma))
2066 return cur_seg;
2067 }
2068 return NULL;
2069 } else {
2070 /* Might still be somewhere in this segment */
2071 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2072 return cur_seg;
2073 }
2074 cur_seg = cur_seg->next;
2075 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2076 } while (cur_seg != start_seg);
2077
2078 return NULL;
2079}
2080
2081static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2082 struct xhci_virt_ep *ep)
2083{
2084 /*
2085 * As part of low/full-speed endpoint-halt processing
2086 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2087 */
2088 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2089 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2090 !(ep->ep_state & EP_CLEARING_TT)) {
2091 ep->ep_state |= EP_CLEARING_TT;
2092 td->urb->ep->hcpriv = td->urb->dev;
2093 if (usb_hub_clear_tt_buffer(td->urb))
2094 ep->ep_state &= ~EP_CLEARING_TT;
2095 }
2096}
2097
2098/* Check if an error has halted the endpoint ring. The class driver will
2099 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2100 * However, a babble and other errors also halt the endpoint ring, and the class
2101 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2102 * Ring Dequeue Pointer command manually.
2103 */
2104static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2105 struct xhci_ep_ctx *ep_ctx,
2106 unsigned int trb_comp_code)
2107{
2108 /* TRB completion codes that may require a manual halt cleanup */
2109 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2110 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2111 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2112 /* The 0.95 spec says a babbling control endpoint
2113 * is not halted. The 0.96 spec says it is. Some HW
2114 * claims to be 0.95 compliant, but it halts the control
2115 * endpoint anyway. Check if a babble halted the
2116 * endpoint.
2117 */
2118 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2119 return 1;
2120
2121 return 0;
2122}
2123
2124int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2125{
2126 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2127 /* Vendor defined "informational" completion code,
2128 * treat as not-an-error.
2129 */
2130 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2131 trb_comp_code);
2132 xhci_dbg(xhci, "Treating code as success.\n");
2133 return 1;
2134 }
2135 return 0;
2136}
2137
2138static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2139 struct xhci_ring *ep_ring, struct xhci_td *td,
2140 u32 trb_comp_code)
2141{
2142 struct xhci_ep_ctx *ep_ctx;
2143
2144 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2145
2146 switch (trb_comp_code) {
2147 case COMP_STOPPED_LENGTH_INVALID:
2148 case COMP_STOPPED_SHORT_PACKET:
2149 case COMP_STOPPED:
2150 /*
2151 * The "Stop Endpoint" completion will take care of any
2152 * stopped TDs. A stopped TD may be restarted, so don't update
2153 * the ring dequeue pointer or take this TD off any lists yet.
2154 */
2155 return 0;
2156 case COMP_USB_TRANSACTION_ERROR:
2157 case COMP_BABBLE_DETECTED_ERROR:
2158 case COMP_SPLIT_TRANSACTION_ERROR:
2159 /*
2160 * If endpoint context state is not halted we might be
2161 * racing with a reset endpoint command issued by a unsuccessful
2162 * stop endpoint completion (context error). In that case the
2163 * td should be on the cancelled list, and EP_HALTED flag set.
2164 *
2165 * Or then it's not halted due to the 0.95 spec stating that a
2166 * babbling control endpoint should not halt. The 0.96 spec
2167 * again says it should. Some HW claims to be 0.95 compliant,
2168 * but it halts the control endpoint anyway.
2169 */
2170 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2171 /*
2172 * If EP_HALTED is set and TD is on the cancelled list
2173 * the TD and dequeue pointer will be handled by reset
2174 * ep command completion
2175 */
2176 if ((ep->ep_state & EP_HALTED) &&
2177 !list_empty(&td->cancelled_td_list)) {
2178 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2179 (unsigned long long)xhci_trb_virt_to_dma(
2180 td->start_seg, td->first_trb));
2181 return 0;
2182 }
2183 /* endpoint not halted, don't reset it */
2184 break;
2185 }
2186 /* Almost same procedure as for STALL_ERROR below */
2187 xhci_clear_hub_tt_buffer(xhci, td, ep);
2188 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2189 return 0;
2190 case COMP_STALL_ERROR:
2191 /*
2192 * xhci internal endpoint state will go to a "halt" state for
2193 * any stall, including default control pipe protocol stall.
2194 * To clear the host side halt we need to issue a reset endpoint
2195 * command, followed by a set dequeue command to move past the
2196 * TD.
2197 * Class drivers clear the device side halt from a functional
2198 * stall later. Hub TT buffer should only be cleared for FS/LS
2199 * devices behind HS hubs for functional stalls.
2200 */
2201 if (ep->ep_index != 0)
2202 xhci_clear_hub_tt_buffer(xhci, td, ep);
2203
2204 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2205
2206 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2207 default:
2208 break;
2209 }
2210
2211 /* Update ring dequeue pointer */
2212 ep_ring->dequeue = td->last_trb;
2213 ep_ring->deq_seg = td->last_trb_seg;
2214 ep_ring->num_trbs_free += td->num_trbs - 1;
2215 inc_deq(xhci, ep_ring);
2216
2217 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2218}
2219
2220/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2221static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2222 union xhci_trb *stop_trb)
2223{
2224 u32 sum;
2225 union xhci_trb *trb = ring->dequeue;
2226 struct xhci_segment *seg = ring->deq_seg;
2227
2228 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2229 if (!trb_is_noop(trb) && !trb_is_link(trb))
2230 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2231 }
2232 return sum;
2233}
2234
2235/*
2236 * Process control tds, update urb status and actual_length.
2237 */
2238static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2239 struct xhci_ring *ep_ring, struct xhci_td *td,
2240 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2241{
2242 struct xhci_ep_ctx *ep_ctx;
2243 u32 trb_comp_code;
2244 u32 remaining, requested;
2245 u32 trb_type;
2246
2247 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2248 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2249 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2250 requested = td->urb->transfer_buffer_length;
2251 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2252
2253 switch (trb_comp_code) {
2254 case COMP_SUCCESS:
2255 if (trb_type != TRB_STATUS) {
2256 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2257 (trb_type == TRB_DATA) ? "data" : "setup");
2258 td->status = -ESHUTDOWN;
2259 break;
2260 }
2261 td->status = 0;
2262 break;
2263 case COMP_SHORT_PACKET:
2264 td->status = 0;
2265 break;
2266 case COMP_STOPPED_SHORT_PACKET:
2267 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2268 td->urb->actual_length = remaining;
2269 else
2270 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2271 goto finish_td;
2272 case COMP_STOPPED:
2273 switch (trb_type) {
2274 case TRB_SETUP:
2275 td->urb->actual_length = 0;
2276 goto finish_td;
2277 case TRB_DATA:
2278 case TRB_NORMAL:
2279 td->urb->actual_length = requested - remaining;
2280 goto finish_td;
2281 case TRB_STATUS:
2282 td->urb->actual_length = requested;
2283 goto finish_td;
2284 default:
2285 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2286 trb_type);
2287 goto finish_td;
2288 }
2289 case COMP_STOPPED_LENGTH_INVALID:
2290 goto finish_td;
2291 default:
2292 if (!xhci_requires_manual_halt_cleanup(xhci,
2293 ep_ctx, trb_comp_code))
2294 break;
2295 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2296 trb_comp_code, ep->ep_index);
2297 fallthrough;
2298 case COMP_STALL_ERROR:
2299 /* Did we transfer part of the data (middle) phase? */
2300 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2301 td->urb->actual_length = requested - remaining;
2302 else if (!td->urb_length_set)
2303 td->urb->actual_length = 0;
2304 goto finish_td;
2305 }
2306
2307 /* stopped at setup stage, no data transferred */
2308 if (trb_type == TRB_SETUP)
2309 goto finish_td;
2310
2311 /*
2312 * if on data stage then update the actual_length of the URB and flag it
2313 * as set, so it won't be overwritten in the event for the last TRB.
2314 */
2315 if (trb_type == TRB_DATA ||
2316 trb_type == TRB_NORMAL) {
2317 td->urb_length_set = true;
2318 td->urb->actual_length = requested - remaining;
2319 xhci_dbg(xhci, "Waiting for status stage event\n");
2320 return 0;
2321 }
2322
2323 /* at status stage */
2324 if (!td->urb_length_set)
2325 td->urb->actual_length = requested;
2326
2327finish_td:
2328 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2329}
2330
2331/*
2332 * Process isochronous tds, update urb packet status and actual_length.
2333 */
2334static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2335 struct xhci_ring *ep_ring, struct xhci_td *td,
2336 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2337{
2338 struct urb_priv *urb_priv;
2339 int idx;
2340 struct usb_iso_packet_descriptor *frame;
2341 u32 trb_comp_code;
2342 bool sum_trbs_for_length = false;
2343 u32 remaining, requested, ep_trb_len;
2344 int short_framestatus;
2345
2346 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2347 urb_priv = td->urb->hcpriv;
2348 idx = urb_priv->num_tds_done;
2349 frame = &td->urb->iso_frame_desc[idx];
2350 requested = frame->length;
2351 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2352 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2353 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2354 -EREMOTEIO : 0;
2355
2356 /* handle completion code */
2357 switch (trb_comp_code) {
2358 case COMP_SUCCESS:
2359 if (remaining) {
2360 frame->status = short_framestatus;
2361 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2362 sum_trbs_for_length = true;
2363 break;
2364 }
2365 frame->status = 0;
2366 break;
2367 case COMP_SHORT_PACKET:
2368 frame->status = short_framestatus;
2369 sum_trbs_for_length = true;
2370 break;
2371 case COMP_BANDWIDTH_OVERRUN_ERROR:
2372 frame->status = -ECOMM;
2373 break;
2374 case COMP_ISOCH_BUFFER_OVERRUN:
2375 case COMP_BABBLE_DETECTED_ERROR:
2376 frame->status = -EOVERFLOW;
2377 break;
2378 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2379 case COMP_STALL_ERROR:
2380 frame->status = -EPROTO;
2381 break;
2382 case COMP_USB_TRANSACTION_ERROR:
2383 frame->status = -EPROTO;
2384 if (ep_trb != td->last_trb)
2385 return 0;
2386 break;
2387 case COMP_STOPPED:
2388 sum_trbs_for_length = true;
2389 break;
2390 case COMP_STOPPED_SHORT_PACKET:
2391 /* field normally containing residue now contains tranferred */
2392 frame->status = short_framestatus;
2393 requested = remaining;
2394 break;
2395 case COMP_STOPPED_LENGTH_INVALID:
2396 requested = 0;
2397 remaining = 0;
2398 break;
2399 default:
2400 sum_trbs_for_length = true;
2401 frame->status = -1;
2402 break;
2403 }
2404
2405 if (sum_trbs_for_length)
2406 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2407 ep_trb_len - remaining;
2408 else
2409 frame->actual_length = requested;
2410
2411 td->urb->actual_length += frame->actual_length;
2412
2413 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2414}
2415
2416static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2417 struct xhci_virt_ep *ep, int status)
2418{
2419 struct urb_priv *urb_priv;
2420 struct usb_iso_packet_descriptor *frame;
2421 int idx;
2422
2423 urb_priv = td->urb->hcpriv;
2424 idx = urb_priv->num_tds_done;
2425 frame = &td->urb->iso_frame_desc[idx];
2426
2427 /* The transfer is partly done. */
2428 frame->status = -EXDEV;
2429
2430 /* calc actual length */
2431 frame->actual_length = 0;
2432
2433 /* Update ring dequeue pointer */
2434 ep->ring->dequeue = td->last_trb;
2435 ep->ring->deq_seg = td->last_trb_seg;
2436 ep->ring->num_trbs_free += td->num_trbs - 1;
2437 inc_deq(xhci, ep->ring);
2438
2439 return xhci_td_cleanup(xhci, td, ep->ring, status);
2440}
2441
2442/*
2443 * Process bulk and interrupt tds, update urb status and actual_length.
2444 */
2445static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2446 struct xhci_ring *ep_ring, struct xhci_td *td,
2447 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2448{
2449 struct xhci_slot_ctx *slot_ctx;
2450 u32 trb_comp_code;
2451 u32 remaining, requested, ep_trb_len;
2452
2453 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2454 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2455 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2456 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2457 requested = td->urb->transfer_buffer_length;
2458
2459 switch (trb_comp_code) {
2460 case COMP_SUCCESS:
2461 ep->err_count = 0;
2462 /* handle success with untransferred data as short packet */
2463 if (ep_trb != td->last_trb || remaining) {
2464 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2465 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2466 td->urb->ep->desc.bEndpointAddress,
2467 requested, remaining);
2468 }
2469 td->status = 0;
2470 break;
2471 case COMP_SHORT_PACKET:
2472 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2473 td->urb->ep->desc.bEndpointAddress,
2474 requested, remaining);
2475 td->status = 0;
2476 break;
2477 case COMP_STOPPED_SHORT_PACKET:
2478 td->urb->actual_length = remaining;
2479 goto finish_td;
2480 case COMP_STOPPED_LENGTH_INVALID:
2481 /* stopped on ep trb with invalid length, exclude it */
2482 ep_trb_len = 0;
2483 remaining = 0;
2484 break;
2485 case COMP_USB_TRANSACTION_ERROR:
2486 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2487 (ep->err_count++ > MAX_SOFT_RETRY) ||
2488 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2489 break;
2490
2491 td->status = 0;
2492
2493 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2494 return 0;
2495 default:
2496 /* do nothing */
2497 break;
2498 }
2499
2500 if (ep_trb == td->last_trb)
2501 td->urb->actual_length = requested - remaining;
2502 else
2503 td->urb->actual_length =
2504 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2505 ep_trb_len - remaining;
2506finish_td:
2507 if (remaining > requested) {
2508 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2509 remaining);
2510 td->urb->actual_length = 0;
2511 }
2512
2513 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2514}
2515
2516/*
2517 * If this function returns an error condition, it means it got a Transfer
2518 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2519 * At this point, the host controller is probably hosed and should be reset.
2520 */
2521static int handle_tx_event(struct xhci_hcd *xhci,
2522 struct xhci_transfer_event *event)
2523{
2524 struct xhci_virt_ep *ep;
2525 struct xhci_ring *ep_ring;
2526 unsigned int slot_id;
2527 int ep_index;
2528 struct xhci_td *td = NULL;
2529 dma_addr_t ep_trb_dma;
2530 struct xhci_segment *ep_seg;
2531 union xhci_trb *ep_trb;
2532 int status = -EINPROGRESS;
2533 struct xhci_ep_ctx *ep_ctx;
2534 struct list_head *tmp;
2535 u32 trb_comp_code;
2536 int td_num = 0;
2537 bool handling_skipped_tds = false;
2538
2539 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2540 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2541 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2542 ep_trb_dma = le64_to_cpu(event->buffer);
2543
2544 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2545 if (!ep) {
2546 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2547 goto err_out;
2548 }
2549
2550 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2551 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2552
2553 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2554 xhci_err(xhci,
2555 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2556 slot_id, ep_index);
2557 goto err_out;
2558 }
2559
2560 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2561 if (!ep_ring) {
2562 switch (trb_comp_code) {
2563 case COMP_STALL_ERROR:
2564 case COMP_USB_TRANSACTION_ERROR:
2565 case COMP_INVALID_STREAM_TYPE_ERROR:
2566 case COMP_INVALID_STREAM_ID_ERROR:
2567 xhci_dbg(xhci, "Stream transaction error ep %u no id\n",
2568 ep_index);
2569 if (ep->err_count++ > MAX_SOFT_RETRY)
2570 xhci_handle_halted_endpoint(xhci, ep, NULL,
2571 EP_HARD_RESET);
2572 else
2573 xhci_handle_halted_endpoint(xhci, ep, NULL,
2574 EP_SOFT_RESET);
2575 goto cleanup;
2576 case COMP_RING_UNDERRUN:
2577 case COMP_RING_OVERRUN:
2578 case COMP_STOPPED_LENGTH_INVALID:
2579 goto cleanup;
2580 default:
2581 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2582 slot_id, ep_index);
2583 goto err_out;
2584 }
2585 }
2586
2587 /* Count current td numbers if ep->skip is set */
2588 if (ep->skip) {
2589 list_for_each(tmp, &ep_ring->td_list)
2590 td_num++;
2591 }
2592
2593 /* Look for common error cases */
2594 switch (trb_comp_code) {
2595 /* Skip codes that require special handling depending on
2596 * transfer type
2597 */
2598 case COMP_SUCCESS:
2599 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2600 break;
2601 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2602 ep_ring->last_td_was_short)
2603 trb_comp_code = COMP_SHORT_PACKET;
2604 else
2605 xhci_warn_ratelimited(xhci,
2606 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2607 slot_id, ep_index);
2608 break;
2609 case COMP_SHORT_PACKET:
2610 break;
2611 /* Completion codes for endpoint stopped state */
2612 case COMP_STOPPED:
2613 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2614 slot_id, ep_index);
2615 break;
2616 case COMP_STOPPED_LENGTH_INVALID:
2617 xhci_dbg(xhci,
2618 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2619 slot_id, ep_index);
2620 break;
2621 case COMP_STOPPED_SHORT_PACKET:
2622 xhci_dbg(xhci,
2623 "Stopped with short packet transfer detected for slot %u ep %u\n",
2624 slot_id, ep_index);
2625 break;
2626 /* Completion codes for endpoint halted state */
2627 case COMP_STALL_ERROR:
2628 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2629 ep_index);
2630 status = -EPIPE;
2631 break;
2632 case COMP_SPLIT_TRANSACTION_ERROR:
2633 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2634 slot_id, ep_index);
2635 status = -EPROTO;
2636 break;
2637 case COMP_USB_TRANSACTION_ERROR:
2638 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2639 slot_id, ep_index);
2640 status = -EPROTO;
2641 break;
2642 case COMP_BABBLE_DETECTED_ERROR:
2643 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2644 slot_id, ep_index);
2645 status = -EOVERFLOW;
2646 break;
2647 /* Completion codes for endpoint error state */
2648 case COMP_TRB_ERROR:
2649 xhci_warn(xhci,
2650 "WARN: TRB error for slot %u ep %u on endpoint\n",
2651 slot_id, ep_index);
2652 status = -EILSEQ;
2653 break;
2654 /* completion codes not indicating endpoint state change */
2655 case COMP_DATA_BUFFER_ERROR:
2656 xhci_warn(xhci,
2657 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2658 slot_id, ep_index);
2659 status = -ENOSR;
2660 break;
2661 case COMP_BANDWIDTH_OVERRUN_ERROR:
2662 xhci_warn(xhci,
2663 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2664 slot_id, ep_index);
2665 break;
2666 case COMP_ISOCH_BUFFER_OVERRUN:
2667 xhci_warn(xhci,
2668 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2669 slot_id, ep_index);
2670 break;
2671 case COMP_RING_UNDERRUN:
2672 /*
2673 * When the Isoch ring is empty, the xHC will generate
2674 * a Ring Overrun Event for IN Isoch endpoint or Ring
2675 * Underrun Event for OUT Isoch endpoint.
2676 */
2677 xhci_dbg(xhci, "underrun event on endpoint\n");
2678 if (!list_empty(&ep_ring->td_list))
2679 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2680 "still with TDs queued?\n",
2681 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2682 ep_index);
2683 goto cleanup;
2684 case COMP_RING_OVERRUN:
2685 xhci_dbg(xhci, "overrun event on endpoint\n");
2686 if (!list_empty(&ep_ring->td_list))
2687 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2688 "still with TDs queued?\n",
2689 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2690 ep_index);
2691 goto cleanup;
2692 case COMP_MISSED_SERVICE_ERROR:
2693 /*
2694 * When encounter missed service error, one or more isoc tds
2695 * may be missed by xHC.
2696 * Set skip flag of the ep_ring; Complete the missed tds as
2697 * short transfer when process the ep_ring next time.
2698 */
2699 ep->skip = true;
2700 xhci_dbg(xhci,
2701 "Miss service interval error for slot %u ep %u, set skip flag\n",
2702 slot_id, ep_index);
2703 goto cleanup;
2704 case COMP_NO_PING_RESPONSE_ERROR:
2705 ep->skip = true;
2706 xhci_dbg(xhci,
2707 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2708 slot_id, ep_index);
2709 goto cleanup;
2710
2711 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2712 /* needs disable slot command to recover */
2713 xhci_warn(xhci,
2714 "WARN: detect an incompatible device for slot %u ep %u",
2715 slot_id, ep_index);
2716 status = -EPROTO;
2717 break;
2718 default:
2719 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2720 status = 0;
2721 break;
2722 }
2723 xhci_warn(xhci,
2724 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2725 trb_comp_code, slot_id, ep_index);
2726 goto cleanup;
2727 }
2728
2729 do {
2730 /* This TRB should be in the TD at the head of this ring's
2731 * TD list.
2732 */
2733 if (list_empty(&ep_ring->td_list)) {
2734 /*
2735 * Don't print wanings if it's due to a stopped endpoint
2736 * generating an extra completion event if the device
2737 * was suspended. Or, a event for the last TRB of a
2738 * short TD we already got a short event for.
2739 * The short TD is already removed from the TD list.
2740 */
2741
2742 if (!(trb_comp_code == COMP_STOPPED ||
2743 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2744 ep_ring->last_td_was_short)) {
2745 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2746 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2747 ep_index);
2748 }
2749 if (ep->skip) {
2750 ep->skip = false;
2751 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2752 slot_id, ep_index);
2753 }
2754 if (trb_comp_code == COMP_STALL_ERROR ||
2755 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2756 trb_comp_code)) {
2757 xhci_handle_halted_endpoint(xhci, ep, NULL,
2758 EP_HARD_RESET);
2759 }
2760 goto cleanup;
2761 }
2762
2763 /* We've skipped all the TDs on the ep ring when ep->skip set */
2764 if (ep->skip && td_num == 0) {
2765 ep->skip = false;
2766 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2767 slot_id, ep_index);
2768 goto cleanup;
2769 }
2770
2771 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2772 td_list);
2773 if (ep->skip)
2774 td_num--;
2775
2776 /* Is this a TRB in the currently executing TD? */
2777 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2778 td->last_trb, ep_trb_dma, false);
2779
2780 /*
2781 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2782 * is not in the current TD pointed by ep_ring->dequeue because
2783 * that the hardware dequeue pointer still at the previous TRB
2784 * of the current TD. The previous TRB maybe a Link TD or the
2785 * last TRB of the previous TD. The command completion handle
2786 * will take care the rest.
2787 */
2788 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2789 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2790 goto cleanup;
2791 }
2792
2793 if (!ep_seg) {
2794 if (!ep->skip ||
2795 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2796 /* Some host controllers give a spurious
2797 * successful event after a short transfer.
2798 * Ignore it.
2799 */
2800 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2801 ep_ring->last_td_was_short) {
2802 ep_ring->last_td_was_short = false;
2803 goto cleanup;
2804 }
2805 /* HC is busted, give up! */
2806 xhci_err(xhci,
2807 "ERROR Transfer event TRB DMA ptr not "
2808 "part of current TD ep_index %d "
2809 "comp_code %u\n", ep_index,
2810 trb_comp_code);
2811 trb_in_td(xhci, ep_ring->deq_seg,
2812 ep_ring->dequeue, td->last_trb,
2813 ep_trb_dma, true);
2814 return -ESHUTDOWN;
2815 }
2816
2817 skip_isoc_td(xhci, td, ep, status);
2818 goto cleanup;
2819 }
2820 if (trb_comp_code == COMP_SHORT_PACKET)
2821 ep_ring->last_td_was_short = true;
2822 else
2823 ep_ring->last_td_was_short = false;
2824
2825 if (ep->skip) {
2826 xhci_dbg(xhci,
2827 "Found td. Clear skip flag for slot %u ep %u.\n",
2828 slot_id, ep_index);
2829 ep->skip = false;
2830 }
2831
2832 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2833 sizeof(*ep_trb)];
2834
2835 trace_xhci_handle_transfer(ep_ring,
2836 (struct xhci_generic_trb *) ep_trb);
2837
2838 /*
2839 * No-op TRB could trigger interrupts in a case where
2840 * a URB was killed and a STALL_ERROR happens right
2841 * after the endpoint ring stopped. Reset the halted
2842 * endpoint. Otherwise, the endpoint remains stalled
2843 * indefinitely.
2844 */
2845
2846 if (trb_is_noop(ep_trb)) {
2847 if (trb_comp_code == COMP_STALL_ERROR ||
2848 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2849 trb_comp_code))
2850 xhci_handle_halted_endpoint(xhci, ep, td,
2851 EP_HARD_RESET);
2852 goto cleanup;
2853 }
2854
2855 td->status = status;
2856
2857 /* update the urb's actual_length and give back to the core */
2858 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2859 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2860 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2861 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2862 else
2863 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2864cleanup:
2865 handling_skipped_tds = ep->skip &&
2866 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2867 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2868
2869 /*
2870 * Do not update event ring dequeue pointer if we're in a loop
2871 * processing missed tds.
2872 */
2873 if (!handling_skipped_tds)
2874 inc_deq(xhci, xhci->event_ring);
2875
2876 /*
2877 * If ep->skip is set, it means there are missed tds on the
2878 * endpoint ring need to take care of.
2879 * Process them as short transfer until reach the td pointed by
2880 * the event.
2881 */
2882 } while (handling_skipped_tds);
2883
2884 return 0;
2885
2886err_out:
2887 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2888 (unsigned long long) xhci_trb_virt_to_dma(
2889 xhci->event_ring->deq_seg,
2890 xhci->event_ring->dequeue),
2891 lower_32_bits(le64_to_cpu(event->buffer)),
2892 upper_32_bits(le64_to_cpu(event->buffer)),
2893 le32_to_cpu(event->transfer_len),
2894 le32_to_cpu(event->flags));
2895 return -ENODEV;
2896}
2897
2898/*
2899 * This function handles all OS-owned events on the event ring. It may drop
2900 * xhci->lock between event processing (e.g. to pass up port status changes).
2901 * Returns >0 for "possibly more events to process" (caller should call again),
2902 * otherwise 0 if done. In future, <0 returns should indicate error code.
2903 */
2904static int xhci_handle_event(struct xhci_hcd *xhci)
2905{
2906 union xhci_trb *event;
2907 int update_ptrs = 1;
2908 u32 trb_type;
2909 int ret;
2910
2911 /* Event ring hasn't been allocated yet. */
2912 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2913 xhci_err(xhci, "ERROR event ring not ready\n");
2914 return -ENOMEM;
2915 }
2916
2917 event = xhci->event_ring->dequeue;
2918 /* Does the HC or OS own the TRB? */
2919 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2920 xhci->event_ring->cycle_state)
2921 return 0;
2922
2923 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2924
2925 /*
2926 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2927 * speculative reads of the event's flags/data below.
2928 */
2929 rmb();
2930 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2931 /* FIXME: Handle more event types. */
2932
2933 switch (trb_type) {
2934 case TRB_COMPLETION:
2935 handle_cmd_completion(xhci, &event->event_cmd);
2936 break;
2937 case TRB_PORT_STATUS:
2938 handle_port_status(xhci, event);
2939 update_ptrs = 0;
2940 break;
2941 case TRB_TRANSFER:
2942 ret = handle_tx_event(xhci, &event->trans_event);
2943 if (ret >= 0)
2944 update_ptrs = 0;
2945 break;
2946 case TRB_DEV_NOTE:
2947 handle_device_notification(xhci, event);
2948 break;
2949 default:
2950 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
2951 handle_vendor_event(xhci, event, trb_type);
2952 else
2953 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
2954 }
2955 /* Any of the above functions may drop and re-acquire the lock, so check
2956 * to make sure a watchdog timer didn't mark the host as non-responsive.
2957 */
2958 if (xhci->xhc_state & XHCI_STATE_DYING) {
2959 xhci_dbg(xhci, "xHCI host dying, returning from "
2960 "event handler.\n");
2961 return 0;
2962 }
2963
2964 if (update_ptrs)
2965 /* Update SW event ring dequeue pointer */
2966 inc_deq(xhci, xhci->event_ring);
2967
2968 /* Are there more items on the event ring? Caller will call us again to
2969 * check.
2970 */
2971 return 1;
2972}
2973
2974/*
2975 * Update Event Ring Dequeue Pointer:
2976 * - When all events have finished
2977 * - To avoid "Event Ring Full Error" condition
2978 */
2979static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2980 union xhci_trb *event_ring_deq)
2981{
2982 u64 temp_64;
2983 dma_addr_t deq;
2984
2985 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2986 /* If necessary, update the HW's version of the event ring deq ptr. */
2987 if (event_ring_deq != xhci->event_ring->dequeue) {
2988 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2989 xhci->event_ring->dequeue);
2990 if (deq == 0)
2991 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2992 /*
2993 * Per 4.9.4, Software writes to the ERDP register shall
2994 * always advance the Event Ring Dequeue Pointer value.
2995 */
2996 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2997 ((u64) deq & (u64) ~ERST_PTR_MASK))
2998 return;
2999
3000 /* Update HC event ring dequeue pointer */
3001 temp_64 &= ERST_PTR_MASK;
3002 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
3003 }
3004
3005 /* Clear the event handler busy flag (RW1C) */
3006 temp_64 |= ERST_EHB;
3007 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
3008}
3009
3010/*
3011 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3012 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3013 * indicators of an event TRB error, but we check the status *first* to be safe.
3014 */
3015irqreturn_t xhci_irq(struct usb_hcd *hcd)
3016{
3017 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3018 union xhci_trb *event_ring_deq;
3019 irqreturn_t ret = IRQ_NONE;
3020 u64 temp_64;
3021 u32 status;
3022 int event_loop = 0;
3023
3024 spin_lock(&xhci->lock);
3025 /* Check if the xHC generated the interrupt, or the irq is shared */
3026 status = readl(&xhci->op_regs->status);
3027 if (status == ~(u32)0) {
3028 xhci_hc_died(xhci);
3029 ret = IRQ_HANDLED;
3030 goto out;
3031 }
3032
3033 if (!(status & STS_EINT))
3034 goto out;
3035
3036 if (status & STS_HCE) {
3037 xhci_warn(xhci, "WARNING: Host Controller Error\n");
3038 goto out;
3039 }
3040
3041 if (status & STS_FATAL) {
3042 xhci_warn(xhci, "WARNING: Host System Error\n");
3043 xhci_halt(xhci);
3044 ret = IRQ_HANDLED;
3045 goto out;
3046 }
3047
3048 /*
3049 * Clear the op reg interrupt status first,
3050 * so we can receive interrupts from other MSI-X interrupters.
3051 * Write 1 to clear the interrupt status.
3052 */
3053 status |= STS_EINT;
3054 writel(status, &xhci->op_regs->status);
3055
3056 if (!hcd->msi_enabled) {
3057 u32 irq_pending;
3058 irq_pending = readl(&xhci->ir_set->irq_pending);
3059 irq_pending |= IMAN_IP;
3060 writel(irq_pending, &xhci->ir_set->irq_pending);
3061 }
3062
3063 if (xhci->xhc_state & XHCI_STATE_DYING ||
3064 xhci->xhc_state & XHCI_STATE_HALTED) {
3065 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3066 "Shouldn't IRQs be disabled?\n");
3067 /* Clear the event handler busy flag (RW1C);
3068 * the event ring should be empty.
3069 */
3070 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
3071 xhci_write_64(xhci, temp_64 | ERST_EHB,
3072 &xhci->ir_set->erst_dequeue);
3073 ret = IRQ_HANDLED;
3074 goto out;
3075 }
3076
3077 event_ring_deq = xhci->event_ring->dequeue;
3078 /* FIXME this should be a delayed service routine
3079 * that clears the EHB.
3080 */
3081 while (xhci_handle_event(xhci) > 0) {
3082 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3083 continue;
3084 xhci_update_erst_dequeue(xhci, event_ring_deq);
3085 event_ring_deq = xhci->event_ring->dequeue;
3086
3087 /* ring is half-full, force isoc trbs to interrupt more often */
3088 if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3089 xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2;
3090
3091 event_loop = 0;
3092 }
3093
3094 xhci_update_erst_dequeue(xhci, event_ring_deq);
3095 ret = IRQ_HANDLED;
3096
3097out:
3098 spin_unlock(&xhci->lock);
3099
3100 return ret;
3101}
3102
3103irqreturn_t xhci_msi_irq(int irq, void *hcd)
3104{
3105 return xhci_irq(hcd);
3106}
3107
3108/**** Endpoint Ring Operations ****/
3109
3110/*
3111 * Generic function for queueing a TRB on a ring.
3112 * The caller must have checked to make sure there's room on the ring.
3113 *
3114 * @more_trbs_coming: Will you enqueue more TRBs before calling
3115 * prepare_transfer()?
3116 */
3117static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3118 bool more_trbs_coming,
3119 u32 field1, u32 field2, u32 field3, u32 field4)
3120{
3121 struct xhci_generic_trb *trb;
3122
3123 trb = &ring->enqueue->generic;
3124 trb->field[0] = cpu_to_le32(field1);
3125 trb->field[1] = cpu_to_le32(field2);
3126 trb->field[2] = cpu_to_le32(field3);
3127 /* make sure TRB is fully written before giving it to the controller */
3128 wmb();
3129 trb->field[3] = cpu_to_le32(field4);
3130
3131 trace_xhci_queue_trb(ring, trb);
3132
3133 inc_enq(xhci, ring, more_trbs_coming);
3134}
3135
3136/*
3137 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3138 * FIXME allocate segments if the ring is full.
3139 */
3140static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3141 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3142{
3143 unsigned int num_trbs_needed;
3144 unsigned int link_trb_count = 0;
3145
3146 /* Make sure the endpoint has been added to xHC schedule */
3147 switch (ep_state) {
3148 case EP_STATE_DISABLED:
3149 /*
3150 * USB core changed config/interfaces without notifying us,
3151 * or hardware is reporting the wrong state.
3152 */
3153 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3154 return -ENOENT;
3155 case EP_STATE_ERROR:
3156 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3157 /* FIXME event handling code for error needs to clear it */
3158 /* XXX not sure if this should be -ENOENT or not */
3159 return -EINVAL;
3160 case EP_STATE_HALTED:
3161 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3162 break;
3163 case EP_STATE_STOPPED:
3164 case EP_STATE_RUNNING:
3165 break;
3166 default:
3167 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3168 /*
3169 * FIXME issue Configure Endpoint command to try to get the HC
3170 * back into a known state.
3171 */
3172 return -EINVAL;
3173 }
3174
3175 while (1) {
3176 if (room_on_ring(xhci, ep_ring, num_trbs))
3177 break;
3178
3179 if (ep_ring == xhci->cmd_ring) {
3180 xhci_err(xhci, "Do not support expand command ring\n");
3181 return -ENOMEM;
3182 }
3183
3184 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3185 "ERROR no room on ep ring, try ring expansion");
3186 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3187 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3188 mem_flags)) {
3189 xhci_err(xhci, "Ring expansion failed\n");
3190 return -ENOMEM;
3191 }
3192 }
3193
3194 while (trb_is_link(ep_ring->enqueue)) {
3195 /* If we're not dealing with 0.95 hardware or isoc rings
3196 * on AMD 0.96 host, clear the chain bit.
3197 */
3198 if (!xhci_link_trb_quirk(xhci) &&
3199 !(ep_ring->type == TYPE_ISOC &&
3200 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3201 ep_ring->enqueue->link.control &=
3202 cpu_to_le32(~TRB_CHAIN);
3203 else
3204 ep_ring->enqueue->link.control |=
3205 cpu_to_le32(TRB_CHAIN);
3206
3207 wmb();
3208 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3209
3210 /* Toggle the cycle bit after the last ring segment. */
3211 if (link_trb_toggles_cycle(ep_ring->enqueue))
3212 ep_ring->cycle_state ^= 1;
3213
3214 ep_ring->enq_seg = ep_ring->enq_seg->next;
3215 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3216
3217 /* prevent infinite loop if all first trbs are link trbs */
3218 if (link_trb_count++ > ep_ring->num_segs) {
3219 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3220 return -EINVAL;
3221 }
3222 }
3223
3224 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3225 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3226 return -EINVAL;
3227 }
3228
3229 return 0;
3230}
3231
3232static int prepare_transfer(struct xhci_hcd *xhci,
3233 struct xhci_virt_device *xdev,
3234 unsigned int ep_index,
3235 unsigned int stream_id,
3236 unsigned int num_trbs,
3237 struct urb *urb,
3238 unsigned int td_index,
3239 gfp_t mem_flags)
3240{
3241 int ret;
3242 struct urb_priv *urb_priv;
3243 struct xhci_td *td;
3244 struct xhci_ring *ep_ring;
3245 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3246
3247 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3248 stream_id);
3249 if (!ep_ring) {
3250 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3251 stream_id);
3252 return -EINVAL;
3253 }
3254
3255 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3256 num_trbs, mem_flags);
3257 if (ret)
3258 return ret;
3259
3260 urb_priv = urb->hcpriv;
3261 td = &urb_priv->td[td_index];
3262
3263 INIT_LIST_HEAD(&td->td_list);
3264 INIT_LIST_HEAD(&td->cancelled_td_list);
3265
3266 if (td_index == 0) {
3267 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3268 if (unlikely(ret))
3269 return ret;
3270 }
3271
3272 td->urb = urb;
3273 /* Add this TD to the tail of the endpoint ring's TD list */
3274 list_add_tail(&td->td_list, &ep_ring->td_list);
3275 td->start_seg = ep_ring->enq_seg;
3276 td->first_trb = ep_ring->enqueue;
3277
3278 return 0;
3279}
3280
3281unsigned int count_trbs(u64 addr, u64 len)
3282{
3283 unsigned int num_trbs;
3284
3285 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3286 TRB_MAX_BUFF_SIZE);
3287 if (num_trbs == 0)
3288 num_trbs++;
3289
3290 return num_trbs;
3291}
3292
3293static inline unsigned int count_trbs_needed(struct urb *urb)
3294{
3295 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3296}
3297
3298static unsigned int count_sg_trbs_needed(struct urb *urb)
3299{
3300 struct scatterlist *sg;
3301 unsigned int i, len, full_len, num_trbs = 0;
3302
3303 full_len = urb->transfer_buffer_length;
3304
3305 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3306 len = sg_dma_len(sg);
3307 num_trbs += count_trbs(sg_dma_address(sg), len);
3308 len = min_t(unsigned int, len, full_len);
3309 full_len -= len;
3310 if (full_len == 0)
3311 break;
3312 }
3313
3314 return num_trbs;
3315}
3316
3317static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3318{
3319 u64 addr, len;
3320
3321 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3322 len = urb->iso_frame_desc[i].length;
3323
3324 return count_trbs(addr, len);
3325}
3326
3327static void check_trb_math(struct urb *urb, int running_total)
3328{
3329 if (unlikely(running_total != urb->transfer_buffer_length))
3330 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3331 "queued %#x (%d), asked for %#x (%d)\n",
3332 __func__,
3333 urb->ep->desc.bEndpointAddress,
3334 running_total, running_total,
3335 urb->transfer_buffer_length,
3336 urb->transfer_buffer_length);
3337}
3338
3339static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3340 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3341 struct xhci_generic_trb *start_trb)
3342{
3343 /*
3344 * Pass all the TRBs to the hardware at once and make sure this write
3345 * isn't reordered.
3346 */
3347 wmb();
3348 if (start_cycle)
3349 start_trb->field[3] |= cpu_to_le32(start_cycle);
3350 else
3351 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3352 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3353}
3354
3355static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3356 struct xhci_ep_ctx *ep_ctx)
3357{
3358 int xhci_interval;
3359 int ep_interval;
3360
3361 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3362 ep_interval = urb->interval;
3363
3364 /* Convert to microframes */
3365 if (urb->dev->speed == USB_SPEED_LOW ||
3366 urb->dev->speed == USB_SPEED_FULL)
3367 ep_interval *= 8;
3368
3369 /* FIXME change this to a warning and a suggestion to use the new API
3370 * to set the polling interval (once the API is added).
3371 */
3372 if (xhci_interval != ep_interval) {
3373 dev_dbg_ratelimited(&urb->dev->dev,
3374 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3375 ep_interval, ep_interval == 1 ? "" : "s",
3376 xhci_interval, xhci_interval == 1 ? "" : "s");
3377 urb->interval = xhci_interval;
3378 /* Convert back to frames for LS/FS devices */
3379 if (urb->dev->speed == USB_SPEED_LOW ||
3380 urb->dev->speed == USB_SPEED_FULL)
3381 urb->interval /= 8;
3382 }
3383}
3384
3385/*
3386 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3387 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3388 * (comprised of sg list entries) can take several service intervals to
3389 * transmit.
3390 */
3391int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3392 struct urb *urb, int slot_id, unsigned int ep_index)
3393{
3394 struct xhci_ep_ctx *ep_ctx;
3395
3396 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3397 check_interval(xhci, urb, ep_ctx);
3398
3399 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3400}
3401
3402/*
3403 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3404 * packets remaining in the TD (*not* including this TRB).
3405 *
3406 * Total TD packet count = total_packet_count =
3407 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3408 *
3409 * Packets transferred up to and including this TRB = packets_transferred =
3410 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3411 *
3412 * TD size = total_packet_count - packets_transferred
3413 *
3414 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3415 * including this TRB, right shifted by 10
3416 *
3417 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3418 * This is taken care of in the TRB_TD_SIZE() macro
3419 *
3420 * The last TRB in a TD must have the TD size set to zero.
3421 */
3422static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3423 int trb_buff_len, unsigned int td_total_len,
3424 struct urb *urb, bool more_trbs_coming)
3425{
3426 u32 maxp, total_packet_count;
3427
3428 /* MTK xHCI 0.96 contains some features from 1.0 */
3429 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3430 return ((td_total_len - transferred) >> 10);
3431
3432 /* One TRB with a zero-length data packet. */
3433 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3434 trb_buff_len == td_total_len)
3435 return 0;
3436
3437 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3438 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3439 trb_buff_len = 0;
3440
3441 maxp = usb_endpoint_maxp(&urb->ep->desc);
3442 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3443
3444 /* Queueing functions don't count the current TRB into transferred */
3445 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3446}
3447
3448
3449static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3450 u32 *trb_buff_len, struct xhci_segment *seg)
3451{
3452 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3453 unsigned int unalign;
3454 unsigned int max_pkt;
3455 u32 new_buff_len;
3456 size_t len;
3457
3458 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3459 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3460
3461 /* we got lucky, last normal TRB data on segment is packet aligned */
3462 if (unalign == 0)
3463 return 0;
3464
3465 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3466 unalign, *trb_buff_len);
3467
3468 /* is the last nornal TRB alignable by splitting it */
3469 if (*trb_buff_len > unalign) {
3470 *trb_buff_len -= unalign;
3471 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3472 return 0;
3473 }
3474
3475 /*
3476 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3477 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3478 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3479 */
3480 new_buff_len = max_pkt - (enqd_len % max_pkt);
3481
3482 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3483 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3484
3485 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3486 if (usb_urb_dir_out(urb)) {
3487 if (urb->num_sgs) {
3488 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3489 seg->bounce_buf, new_buff_len, enqd_len);
3490 if (len != new_buff_len)
3491 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3492 len, new_buff_len);
3493 } else {
3494 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3495 }
3496
3497 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3498 max_pkt, DMA_TO_DEVICE);
3499 } else {
3500 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3501 max_pkt, DMA_FROM_DEVICE);
3502 }
3503
3504 if (dma_mapping_error(dev, seg->bounce_dma)) {
3505 /* try without aligning. Some host controllers survive */
3506 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3507 return 0;
3508 }
3509 *trb_buff_len = new_buff_len;
3510 seg->bounce_len = new_buff_len;
3511 seg->bounce_offs = enqd_len;
3512
3513 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3514
3515 return 1;
3516}
3517
3518/* This is very similar to what ehci-q.c qtd_fill() does */
3519int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3520 struct urb *urb, int slot_id, unsigned int ep_index)
3521{
3522 struct xhci_ring *ring;
3523 struct urb_priv *urb_priv;
3524 struct xhci_td *td;
3525 struct xhci_generic_trb *start_trb;
3526 struct scatterlist *sg = NULL;
3527 bool more_trbs_coming = true;
3528 bool need_zero_pkt = false;
3529 bool first_trb = true;
3530 unsigned int num_trbs;
3531 unsigned int start_cycle, num_sgs = 0;
3532 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3533 int sent_len, ret;
3534 u32 field, length_field, remainder;
3535 u64 addr, send_addr;
3536
3537 ring = xhci_urb_to_transfer_ring(xhci, urb);
3538 if (!ring)
3539 return -EINVAL;
3540
3541 full_len = urb->transfer_buffer_length;
3542 /* If we have scatter/gather list, we use it. */
3543 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3544 num_sgs = urb->num_mapped_sgs;
3545 sg = urb->sg;
3546 addr = (u64) sg_dma_address(sg);
3547 block_len = sg_dma_len(sg);
3548 num_trbs = count_sg_trbs_needed(urb);
3549 } else {
3550 num_trbs = count_trbs_needed(urb);
3551 addr = (u64) urb->transfer_dma;
3552 block_len = full_len;
3553 }
3554 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3555 ep_index, urb->stream_id,
3556 num_trbs, urb, 0, mem_flags);
3557 if (unlikely(ret < 0))
3558 return ret;
3559
3560 urb_priv = urb->hcpriv;
3561
3562 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3563 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3564 need_zero_pkt = true;
3565
3566 td = &urb_priv->td[0];
3567
3568 /*
3569 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3570 * until we've finished creating all the other TRBs. The ring's cycle
3571 * state may change as we enqueue the other TRBs, so save it too.
3572 */
3573 start_trb = &ring->enqueue->generic;
3574 start_cycle = ring->cycle_state;
3575 send_addr = addr;
3576
3577 /* Queue the TRBs, even if they are zero-length */
3578 for (enqd_len = 0; first_trb || enqd_len < full_len;
3579 enqd_len += trb_buff_len) {
3580 field = TRB_TYPE(TRB_NORMAL);
3581
3582 /* TRB buffer should not cross 64KB boundaries */
3583 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3584 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3585
3586 if (enqd_len + trb_buff_len > full_len)
3587 trb_buff_len = full_len - enqd_len;
3588
3589 /* Don't change the cycle bit of the first TRB until later */
3590 if (first_trb) {
3591 first_trb = false;
3592 if (start_cycle == 0)
3593 field |= TRB_CYCLE;
3594 } else
3595 field |= ring->cycle_state;
3596
3597 /* Chain all the TRBs together; clear the chain bit in the last
3598 * TRB to indicate it's the last TRB in the chain.
3599 */
3600 if (enqd_len + trb_buff_len < full_len) {
3601 field |= TRB_CHAIN;
3602 if (trb_is_link(ring->enqueue + 1)) {
3603 if (xhci_align_td(xhci, urb, enqd_len,
3604 &trb_buff_len,
3605 ring->enq_seg)) {
3606 send_addr = ring->enq_seg->bounce_dma;
3607 /* assuming TD won't span 2 segs */
3608 td->bounce_seg = ring->enq_seg;
3609 }
3610 }
3611 }
3612 if (enqd_len + trb_buff_len >= full_len) {
3613 field &= ~TRB_CHAIN;
3614 field |= TRB_IOC;
3615 more_trbs_coming = false;
3616 td->last_trb = ring->enqueue;
3617 td->last_trb_seg = ring->enq_seg;
3618 if (xhci_urb_suitable_for_idt(urb)) {
3619 memcpy(&send_addr, urb->transfer_buffer,
3620 trb_buff_len);
3621 le64_to_cpus(&send_addr);
3622 field |= TRB_IDT;
3623 }
3624 }
3625
3626 /* Only set interrupt on short packet for IN endpoints */
3627 if (usb_urb_dir_in(urb))
3628 field |= TRB_ISP;
3629
3630 /* Set the TRB length, TD size, and interrupter fields. */
3631 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3632 full_len, urb, more_trbs_coming);
3633
3634 length_field = TRB_LEN(trb_buff_len) |
3635 TRB_TD_SIZE(remainder) |
3636 TRB_INTR_TARGET(0);
3637
3638 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3639 lower_32_bits(send_addr),
3640 upper_32_bits(send_addr),
3641 length_field,
3642 field);
3643 td->num_trbs++;
3644 addr += trb_buff_len;
3645 sent_len = trb_buff_len;
3646
3647 while (sg && sent_len >= block_len) {
3648 /* New sg entry */
3649 --num_sgs;
3650 sent_len -= block_len;
3651 sg = sg_next(sg);
3652 if (num_sgs != 0 && sg) {
3653 block_len = sg_dma_len(sg);
3654 addr = (u64) sg_dma_address(sg);
3655 addr += sent_len;
3656 }
3657 }
3658 block_len -= sent_len;
3659 send_addr = addr;
3660 }
3661
3662 if (need_zero_pkt) {
3663 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3664 ep_index, urb->stream_id,
3665 1, urb, 1, mem_flags);
3666 urb_priv->td[1].last_trb = ring->enqueue;
3667 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3668 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3669 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3670 urb_priv->td[1].num_trbs++;
3671 }
3672
3673 check_trb_math(urb, enqd_len);
3674 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3675 start_cycle, start_trb);
3676 return 0;
3677}
3678
3679/* Caller must have locked xhci->lock */
3680int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3681 struct urb *urb, int slot_id, unsigned int ep_index)
3682{
3683 struct xhci_ring *ep_ring;
3684 int num_trbs;
3685 int ret;
3686 struct usb_ctrlrequest *setup;
3687 struct xhci_generic_trb *start_trb;
3688 int start_cycle;
3689 u32 field;
3690 struct urb_priv *urb_priv;
3691 struct xhci_td *td;
3692
3693 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3694 if (!ep_ring)
3695 return -EINVAL;
3696
3697 /*
3698 * Need to copy setup packet into setup TRB, so we can't use the setup
3699 * DMA address.
3700 */
3701 if (!urb->setup_packet)
3702 return -EINVAL;
3703
3704 /* 1 TRB for setup, 1 for status */
3705 num_trbs = 2;
3706 /*
3707 * Don't need to check if we need additional event data and normal TRBs,
3708 * since data in control transfers will never get bigger than 16MB
3709 * XXX: can we get a buffer that crosses 64KB boundaries?
3710 */
3711 if (urb->transfer_buffer_length > 0)
3712 num_trbs++;
3713 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3714 ep_index, urb->stream_id,
3715 num_trbs, urb, 0, mem_flags);
3716 if (ret < 0)
3717 return ret;
3718
3719 urb_priv = urb->hcpriv;
3720 td = &urb_priv->td[0];
3721 td->num_trbs = num_trbs;
3722
3723 /*
3724 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3725 * until we've finished creating all the other TRBs. The ring's cycle
3726 * state may change as we enqueue the other TRBs, so save it too.
3727 */
3728 start_trb = &ep_ring->enqueue->generic;
3729 start_cycle = ep_ring->cycle_state;
3730
3731 /* Queue setup TRB - see section 6.4.1.2.1 */
3732 /* FIXME better way to translate setup_packet into two u32 fields? */
3733 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3734 field = 0;
3735 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3736 if (start_cycle == 0)
3737 field |= 0x1;
3738
3739 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3740 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3741 if (urb->transfer_buffer_length > 0) {
3742 if (setup->bRequestType & USB_DIR_IN)
3743 field |= TRB_TX_TYPE(TRB_DATA_IN);
3744 else
3745 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3746 }
3747 }
3748
3749 queue_trb(xhci, ep_ring, true,
3750 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3751 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3752 TRB_LEN(8) | TRB_INTR_TARGET(0),
3753 /* Immediate data in pointer */
3754 field);
3755
3756 /* If there's data, queue data TRBs */
3757 /* Only set interrupt on short packet for IN endpoints */
3758 if (usb_urb_dir_in(urb))
3759 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3760 else
3761 field = TRB_TYPE(TRB_DATA);
3762
3763 if (urb->transfer_buffer_length > 0) {
3764 u32 length_field, remainder;
3765 u64 addr;
3766
3767 if (xhci_urb_suitable_for_idt(urb)) {
3768 memcpy(&addr, urb->transfer_buffer,
3769 urb->transfer_buffer_length);
3770 le64_to_cpus(&addr);
3771 field |= TRB_IDT;
3772 } else {
3773 addr = (u64) urb->transfer_dma;
3774 }
3775
3776 remainder = xhci_td_remainder(xhci, 0,
3777 urb->transfer_buffer_length,
3778 urb->transfer_buffer_length,
3779 urb, 1);
3780 length_field = TRB_LEN(urb->transfer_buffer_length) |
3781 TRB_TD_SIZE(remainder) |
3782 TRB_INTR_TARGET(0);
3783 if (setup->bRequestType & USB_DIR_IN)
3784 field |= TRB_DIR_IN;
3785 queue_trb(xhci, ep_ring, true,
3786 lower_32_bits(addr),
3787 upper_32_bits(addr),
3788 length_field,
3789 field | ep_ring->cycle_state);
3790 }
3791
3792 /* Save the DMA address of the last TRB in the TD */
3793 td->last_trb = ep_ring->enqueue;
3794 td->last_trb_seg = ep_ring->enq_seg;
3795
3796 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3797 /* If the device sent data, the status stage is an OUT transfer */
3798 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3799 field = 0;
3800 else
3801 field = TRB_DIR_IN;
3802 queue_trb(xhci, ep_ring, false,
3803 0,
3804 0,
3805 TRB_INTR_TARGET(0),
3806 /* Event on completion */
3807 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3808
3809 giveback_first_trb(xhci, slot_id, ep_index, 0,
3810 start_cycle, start_trb);
3811 return 0;
3812}
3813
3814/*
3815 * The transfer burst count field of the isochronous TRB defines the number of
3816 * bursts that are required to move all packets in this TD. Only SuperSpeed
3817 * devices can burst up to bMaxBurst number of packets per service interval.
3818 * This field is zero based, meaning a value of zero in the field means one
3819 * burst. Basically, for everything but SuperSpeed devices, this field will be
3820 * zero. Only xHCI 1.0 host controllers support this field.
3821 */
3822static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3823 struct urb *urb, unsigned int total_packet_count)
3824{
3825 unsigned int max_burst;
3826
3827 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3828 return 0;
3829
3830 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3831 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3832}
3833
3834/*
3835 * Returns the number of packets in the last "burst" of packets. This field is
3836 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3837 * the last burst packet count is equal to the total number of packets in the
3838 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3839 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3840 * contain 1 to (bMaxBurst + 1) packets.
3841 */
3842static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3843 struct urb *urb, unsigned int total_packet_count)
3844{
3845 unsigned int max_burst;
3846 unsigned int residue;
3847
3848 if (xhci->hci_version < 0x100)
3849 return 0;
3850
3851 if (urb->dev->speed >= USB_SPEED_SUPER) {
3852 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3853 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3854 residue = total_packet_count % (max_burst + 1);
3855 /* If residue is zero, the last burst contains (max_burst + 1)
3856 * number of packets, but the TLBPC field is zero-based.
3857 */
3858 if (residue == 0)
3859 return max_burst;
3860 return residue - 1;
3861 }
3862 if (total_packet_count == 0)
3863 return 0;
3864 return total_packet_count - 1;
3865}
3866
3867/*
3868 * Calculates Frame ID field of the isochronous TRB identifies the
3869 * target frame that the Interval associated with this Isochronous
3870 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3871 *
3872 * Returns actual frame id on success, negative value on error.
3873 */
3874static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3875 struct urb *urb, int index)
3876{
3877 int start_frame, ist, ret = 0;
3878 int start_frame_id, end_frame_id, current_frame_id;
3879
3880 if (urb->dev->speed == USB_SPEED_LOW ||
3881 urb->dev->speed == USB_SPEED_FULL)
3882 start_frame = urb->start_frame + index * urb->interval;
3883 else
3884 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3885
3886 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3887 *
3888 * If bit [3] of IST is cleared to '0', software can add a TRB no
3889 * later than IST[2:0] Microframes before that TRB is scheduled to
3890 * be executed.
3891 * If bit [3] of IST is set to '1', software can add a TRB no later
3892 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3893 */
3894 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3895 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3896 ist <<= 3;
3897
3898 /* Software shall not schedule an Isoch TD with a Frame ID value that
3899 * is less than the Start Frame ID or greater than the End Frame ID,
3900 * where:
3901 *
3902 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3903 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3904 *
3905 * Both the End Frame ID and Start Frame ID values are calculated
3906 * in microframes. When software determines the valid Frame ID value;
3907 * The End Frame ID value should be rounded down to the nearest Frame
3908 * boundary, and the Start Frame ID value should be rounded up to the
3909 * nearest Frame boundary.
3910 */
3911 current_frame_id = readl(&xhci->run_regs->microframe_index);
3912 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3913 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3914
3915 start_frame &= 0x7ff;
3916 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3917 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3918
3919 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3920 __func__, index, readl(&xhci->run_regs->microframe_index),
3921 start_frame_id, end_frame_id, start_frame);
3922
3923 if (start_frame_id < end_frame_id) {
3924 if (start_frame > end_frame_id ||
3925 start_frame < start_frame_id)
3926 ret = -EINVAL;
3927 } else if (start_frame_id > end_frame_id) {
3928 if ((start_frame > end_frame_id &&
3929 start_frame < start_frame_id))
3930 ret = -EINVAL;
3931 } else {
3932 ret = -EINVAL;
3933 }
3934
3935 if (index == 0) {
3936 if (ret == -EINVAL || start_frame == start_frame_id) {
3937 start_frame = start_frame_id + 1;
3938 if (urb->dev->speed == USB_SPEED_LOW ||
3939 urb->dev->speed == USB_SPEED_FULL)
3940 urb->start_frame = start_frame;
3941 else
3942 urb->start_frame = start_frame << 3;
3943 ret = 0;
3944 }
3945 }
3946
3947 if (ret) {
3948 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3949 start_frame, current_frame_id, index,
3950 start_frame_id, end_frame_id);
3951 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3952 return ret;
3953 }
3954
3955 return start_frame;
3956}
3957
3958/* Check if we should generate event interrupt for a TD in an isoc URB */
3959static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3960{
3961 if (xhci->hci_version < 0x100)
3962 return false;
3963 /* always generate an event interrupt for the last TD */
3964 if (i == num_tds - 1)
3965 return false;
3966 /*
3967 * If AVOID_BEI is set the host handles full event rings poorly,
3968 * generate an event at least every 8th TD to clear the event ring
3969 */
3970 if (i && xhci->quirks & XHCI_AVOID_BEI)
3971 return !!(i % xhci->isoc_bei_interval);
3972
3973 return true;
3974}
3975
3976/* This is for isoc transfer */
3977static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3978 struct urb *urb, int slot_id, unsigned int ep_index)
3979{
3980 struct xhci_ring *ep_ring;
3981 struct urb_priv *urb_priv;
3982 struct xhci_td *td;
3983 int num_tds, trbs_per_td;
3984 struct xhci_generic_trb *start_trb;
3985 bool first_trb;
3986 int start_cycle;
3987 u32 field, length_field;
3988 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3989 u64 start_addr, addr;
3990 int i, j;
3991 bool more_trbs_coming;
3992 struct xhci_virt_ep *xep;
3993 int frame_id;
3994
3995 xep = &xhci->devs[slot_id]->eps[ep_index];
3996 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3997
3998 num_tds = urb->number_of_packets;
3999 if (num_tds < 1) {
4000 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4001 return -EINVAL;
4002 }
4003 start_addr = (u64) urb->transfer_dma;
4004 start_trb = &ep_ring->enqueue->generic;
4005 start_cycle = ep_ring->cycle_state;
4006
4007 urb_priv = urb->hcpriv;
4008 /* Queue the TRBs for each TD, even if they are zero-length */
4009 for (i = 0; i < num_tds; i++) {
4010 unsigned int total_pkt_count, max_pkt;
4011 unsigned int burst_count, last_burst_pkt_count;
4012 u32 sia_frame_id;
4013
4014 first_trb = true;
4015 running_total = 0;
4016 addr = start_addr + urb->iso_frame_desc[i].offset;
4017 td_len = urb->iso_frame_desc[i].length;
4018 td_remain_len = td_len;
4019 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4020 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4021
4022 /* A zero-length transfer still involves at least one packet. */
4023 if (total_pkt_count == 0)
4024 total_pkt_count++;
4025 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4026 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4027 urb, total_pkt_count);
4028
4029 trbs_per_td = count_isoc_trbs_needed(urb, i);
4030
4031 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4032 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4033 if (ret < 0) {
4034 if (i == 0)
4035 return ret;
4036 goto cleanup;
4037 }
4038 td = &urb_priv->td[i];
4039 td->num_trbs = trbs_per_td;
4040 /* use SIA as default, if frame id is used overwrite it */
4041 sia_frame_id = TRB_SIA;
4042 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4043 HCC_CFC(xhci->hcc_params)) {
4044 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4045 if (frame_id >= 0)
4046 sia_frame_id = TRB_FRAME_ID(frame_id);
4047 }
4048 /*
4049 * Set isoc specific data for the first TRB in a TD.
4050 * Prevent HW from getting the TRBs by keeping the cycle state
4051 * inverted in the first TDs isoc TRB.
4052 */
4053 field = TRB_TYPE(TRB_ISOC) |
4054 TRB_TLBPC(last_burst_pkt_count) |
4055 sia_frame_id |
4056 (i ? ep_ring->cycle_state : !start_cycle);
4057
4058 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4059 if (!xep->use_extended_tbc)
4060 field |= TRB_TBC(burst_count);
4061
4062 /* fill the rest of the TRB fields, and remaining normal TRBs */
4063 for (j = 0; j < trbs_per_td; j++) {
4064 u32 remainder = 0;
4065
4066 /* only first TRB is isoc, overwrite otherwise */
4067 if (!first_trb)
4068 field = TRB_TYPE(TRB_NORMAL) |
4069 ep_ring->cycle_state;
4070
4071 /* Only set interrupt on short packet for IN EPs */
4072 if (usb_urb_dir_in(urb))
4073 field |= TRB_ISP;
4074
4075 /* Set the chain bit for all except the last TRB */
4076 if (j < trbs_per_td - 1) {
4077 more_trbs_coming = true;
4078 field |= TRB_CHAIN;
4079 } else {
4080 more_trbs_coming = false;
4081 td->last_trb = ep_ring->enqueue;
4082 td->last_trb_seg = ep_ring->enq_seg;
4083 field |= TRB_IOC;
4084 if (trb_block_event_intr(xhci, num_tds, i))
4085 field |= TRB_BEI;
4086 }
4087 /* Calculate TRB length */
4088 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4089 if (trb_buff_len > td_remain_len)
4090 trb_buff_len = td_remain_len;
4091
4092 /* Set the TRB length, TD size, & interrupter fields. */
4093 remainder = xhci_td_remainder(xhci, running_total,
4094 trb_buff_len, td_len,
4095 urb, more_trbs_coming);
4096
4097 length_field = TRB_LEN(trb_buff_len) |
4098 TRB_INTR_TARGET(0);
4099
4100 /* xhci 1.1 with ETE uses TD Size field for TBC */
4101 if (first_trb && xep->use_extended_tbc)
4102 length_field |= TRB_TD_SIZE_TBC(burst_count);
4103 else
4104 length_field |= TRB_TD_SIZE(remainder);
4105 first_trb = false;
4106
4107 queue_trb(xhci, ep_ring, more_trbs_coming,
4108 lower_32_bits(addr),
4109 upper_32_bits(addr),
4110 length_field,
4111 field);
4112 running_total += trb_buff_len;
4113
4114 addr += trb_buff_len;
4115 td_remain_len -= trb_buff_len;
4116 }
4117
4118 /* Check TD length */
4119 if (running_total != td_len) {
4120 xhci_err(xhci, "ISOC TD length unmatch\n");
4121 ret = -EINVAL;
4122 goto cleanup;
4123 }
4124 }
4125
4126 /* store the next frame id */
4127 if (HCC_CFC(xhci->hcc_params))
4128 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4129
4130 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4131 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4132 usb_amd_quirk_pll_disable();
4133 }
4134 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4135
4136 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4137 start_cycle, start_trb);
4138 return 0;
4139cleanup:
4140 /* Clean up a partially enqueued isoc transfer. */
4141
4142 for (i--; i >= 0; i--)
4143 list_del_init(&urb_priv->td[i].td_list);
4144
4145 /* Use the first TD as a temporary variable to turn the TDs we've queued
4146 * into No-ops with a software-owned cycle bit. That way the hardware
4147 * won't accidentally start executing bogus TDs when we partially
4148 * overwrite them. td->first_trb and td->start_seg are already set.
4149 */
4150 urb_priv->td[0].last_trb = ep_ring->enqueue;
4151 /* Every TRB except the first & last will have its cycle bit flipped. */
4152 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4153
4154 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4155 ep_ring->enqueue = urb_priv->td[0].first_trb;
4156 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4157 ep_ring->cycle_state = start_cycle;
4158 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4159 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4160 return ret;
4161}
4162
4163/*
4164 * Check transfer ring to guarantee there is enough room for the urb.
4165 * Update ISO URB start_frame and interval.
4166 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4167 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4168 * Contiguous Frame ID is not supported by HC.
4169 */
4170int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4171 struct urb *urb, int slot_id, unsigned int ep_index)
4172{
4173 struct xhci_virt_device *xdev;
4174 struct xhci_ring *ep_ring;
4175 struct xhci_ep_ctx *ep_ctx;
4176 int start_frame;
4177 int num_tds, num_trbs, i;
4178 int ret;
4179 struct xhci_virt_ep *xep;
4180 int ist;
4181
4182 xdev = xhci->devs[slot_id];
4183 xep = &xhci->devs[slot_id]->eps[ep_index];
4184 ep_ring = xdev->eps[ep_index].ring;
4185 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4186
4187 num_trbs = 0;
4188 num_tds = urb->number_of_packets;
4189 for (i = 0; i < num_tds; i++)
4190 num_trbs += count_isoc_trbs_needed(urb, i);
4191
4192 /* Check the ring to guarantee there is enough room for the whole urb.
4193 * Do not insert any td of the urb to the ring if the check failed.
4194 */
4195 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4196 num_trbs, mem_flags);
4197 if (ret)
4198 return ret;
4199
4200 /*
4201 * Check interval value. This should be done before we start to
4202 * calculate the start frame value.
4203 */
4204 check_interval(xhci, urb, ep_ctx);
4205
4206 /* Calculate the start frame and put it in urb->start_frame. */
4207 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4208 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4209 urb->start_frame = xep->next_frame_id;
4210 goto skip_start_over;
4211 }
4212 }
4213
4214 start_frame = readl(&xhci->run_regs->microframe_index);
4215 start_frame &= 0x3fff;
4216 /*
4217 * Round up to the next frame and consider the time before trb really
4218 * gets scheduled by hardare.
4219 */
4220 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4221 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4222 ist <<= 3;
4223 start_frame += ist + XHCI_CFC_DELAY;
4224 start_frame = roundup(start_frame, 8);
4225
4226 /*
4227 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4228 * is greate than 8 microframes.
4229 */
4230 if (urb->dev->speed == USB_SPEED_LOW ||
4231 urb->dev->speed == USB_SPEED_FULL) {
4232 start_frame = roundup(start_frame, urb->interval << 3);
4233 urb->start_frame = start_frame >> 3;
4234 } else {
4235 start_frame = roundup(start_frame, urb->interval);
4236 urb->start_frame = start_frame;
4237 }
4238
4239skip_start_over:
4240 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4241
4242 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4243}
4244
4245/**** Command Ring Operations ****/
4246
4247/* Generic function for queueing a command TRB on the command ring.
4248 * Check to make sure there's room on the command ring for one command TRB.
4249 * Also check that there's room reserved for commands that must not fail.
4250 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4251 * then only check for the number of reserved spots.
4252 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4253 * because the command event handler may want to resubmit a failed command.
4254 */
4255static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4256 u32 field1, u32 field2,
4257 u32 field3, u32 field4, bool command_must_succeed)
4258{
4259 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4260 int ret;
4261
4262 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4263 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4264 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4265 return -ESHUTDOWN;
4266 }
4267
4268 if (!command_must_succeed)
4269 reserved_trbs++;
4270
4271 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4272 reserved_trbs, GFP_ATOMIC);
4273 if (ret < 0) {
4274 xhci_err(xhci, "ERR: No room for command on command ring\n");
4275 if (command_must_succeed)
4276 xhci_err(xhci, "ERR: Reserved TRB counting for "
4277 "unfailable commands failed.\n");
4278 return ret;
4279 }
4280
4281 cmd->command_trb = xhci->cmd_ring->enqueue;
4282
4283 /* if there are no other commands queued we start the timeout timer */
4284 if (list_empty(&xhci->cmd_list)) {
4285 xhci->current_cmd = cmd;
4286 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4287 }
4288
4289 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4290
4291 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4292 field4 | xhci->cmd_ring->cycle_state);
4293 return 0;
4294}
4295
4296/* Queue a slot enable or disable request on the command ring */
4297int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4298 u32 trb_type, u32 slot_id)
4299{
4300 return queue_command(xhci, cmd, 0, 0, 0,
4301 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4302}
4303
4304/* Queue an address device command TRB */
4305int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4306 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4307{
4308 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4309 upper_32_bits(in_ctx_ptr), 0,
4310 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4311 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4312}
4313
4314int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4315 u32 field1, u32 field2, u32 field3, u32 field4)
4316{
4317 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4318}
4319
4320/* Queue a reset device command TRB */
4321int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4322 u32 slot_id)
4323{
4324 return queue_command(xhci, cmd, 0, 0, 0,
4325 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4326 false);
4327}
4328
4329/* Queue a configure endpoint command TRB */
4330int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4331 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4332 u32 slot_id, bool command_must_succeed)
4333{
4334 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4335 upper_32_bits(in_ctx_ptr), 0,
4336 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4337 command_must_succeed);
4338}
4339
4340/* Queue an evaluate context command TRB */
4341int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4342 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4343{
4344 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4345 upper_32_bits(in_ctx_ptr), 0,
4346 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4347 command_must_succeed);
4348}
4349
4350/*
4351 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4352 * activity on an endpoint that is about to be suspended.
4353 */
4354int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4355 int slot_id, unsigned int ep_index, int suspend)
4356{
4357 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4358 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4359 u32 type = TRB_TYPE(TRB_STOP_RING);
4360 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4361
4362 return queue_command(xhci, cmd, 0, 0, 0,
4363 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4364}
4365
4366int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4367 int slot_id, unsigned int ep_index,
4368 enum xhci_ep_reset_type reset_type)
4369{
4370 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4371 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4372 u32 type = TRB_TYPE(TRB_RESET_EP);
4373
4374 if (reset_type == EP_SOFT_RESET)
4375 type |= TRB_TSP;
4376
4377 return queue_command(xhci, cmd, 0, 0, 0,
4378 trb_slot_id | trb_ep_index | type, false);
4379}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11/*
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
17 *
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
29 *
30 * Cycle bit rules:
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
35 *
36 * Producer rules:
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
40 * cycle state).
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
44 *
45 * Consumer rules:
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
53 */
54
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/dma-mapping.h>
58#include "xhci.h"
59#include "xhci-trace.h"
60#include "xhci-mtk.h"
61
62/*
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
64 * address of the TRB.
65 */
66dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
67 union xhci_trb *trb)
68{
69 unsigned long segment_offset;
70
71 if (!seg || !trb || trb < seg->trbs)
72 return 0;
73 /* offset in TRBs */
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
76 return 0;
77 return seg->dma + (segment_offset * sizeof(*trb));
78}
79
80static bool trb_is_noop(union xhci_trb *trb)
81{
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
83}
84
85static bool trb_is_link(union xhci_trb *trb)
86{
87 return TRB_TYPE_LINK_LE32(trb->link.control);
88}
89
90static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
91{
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
93}
94
95static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
97{
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
99}
100
101static bool link_trb_toggles_cycle(union xhci_trb *trb)
102{
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104}
105
106static bool last_td_in_urb(struct xhci_td *td)
107{
108 struct urb_priv *urb_priv = td->urb->hcpriv;
109
110 return urb_priv->num_tds_done == urb_priv->num_tds;
111}
112
113static void inc_td_cnt(struct urb *urb)
114{
115 struct urb_priv *urb_priv = urb->hcpriv;
116
117 urb_priv->num_tds_done++;
118}
119
120static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
121{
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
125 } else {
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
132 }
133}
134
135/* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
138 */
139static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
143{
144 if (trb_is_link(*trb)) {
145 *seg = (*seg)->next;
146 *trb = ((*seg)->trbs);
147 } else {
148 (*trb)++;
149 }
150}
151
152/*
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
155 */
156void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
157{
158 /* event ring doesn't have link trbs, check for last trb */
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
161 ring->dequeue++;
162 goto out;
163 }
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
168 goto out;
169 }
170
171 /* All other rings have link trbs */
172 if (!trb_is_link(ring->dequeue)) {
173 ring->dequeue++;
174 ring->num_trbs_free++;
175 }
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
179 }
180
181out:
182 trace_xhci_inc_deq(ring);
183
184 return;
185}
186
187/*
188 * See Cycle bit rules. SW is the consumer for the event ring only.
189 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
190 *
191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
192 * chain bit is set), then set the chain bit in all the following link TRBs.
193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
194 * have their chain bit cleared (so that each Link TRB is a separate TD).
195 *
196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
197 * set, but other sections talk about dealing with the chain bit set. This was
198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
200 *
201 * @more_trbs_coming: Will you enqueue more TRBs before calling
202 * prepare_transfer()?
203 */
204static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
206{
207 u32 chain;
208 union xhci_trb *next;
209
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211 /* If this is not event ring, there is one less usable TRB */
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
215
216 /* Update the dequeue pointer further if that was a link TRB */
217 while (trb_is_link(next)) {
218
219 /*
220 * If the caller doesn't plan on enqueueing more TDs before
221 * ringing the doorbell, then we don't want to give the link TRB
222 * to the hardware just yet. We'll give the link TRB back in
223 * prepare_ring() just before we enqueue the TD at the top of
224 * the ring.
225 */
226 if (!chain && !more_trbs_coming)
227 break;
228
229 /* If we're not dealing with 0.95 hardware or isoc rings on
230 * AMD 0.96 host, carry over the chain bit of the previous TRB
231 * (which may mean the chain bit is cleared).
232 */
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
238 }
239 /* Give this link TRB to the hardware */
240 wmb();
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
242
243 /* Toggle the cycle bit after the last ring segment. */
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
246
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
250 }
251
252 trace_xhci_inc_enq(ring);
253}
254
255/*
256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
257 * enqueue pointer will not advance into dequeue segment. See rules above.
258 */
259static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
261{
262 int num_trbs_in_deq_seg;
263
264 if (ring->num_trbs_free < num_trbs)
265 return 0;
266
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
270 return 0;
271 }
272
273 return 1;
274}
275
276/* Ring the host controller doorbell after placing a command on the ring */
277void xhci_ring_cmd_db(struct xhci_hcd *xhci)
278{
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
280 return;
281
282 xhci_dbg(xhci, "// Ding dong!\n");
283 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
284 /* Flush PCI posted writes */
285 readl(&xhci->dba->doorbell[0]);
286}
287
288static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
289{
290 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
291}
292
293static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
294{
295 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
296 cmd_list);
297}
298
299/*
300 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
301 * If there are other commands waiting then restart the ring and kick the timer.
302 * This must be called with command ring stopped and xhci->lock held.
303 */
304static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
305 struct xhci_command *cur_cmd)
306{
307 struct xhci_command *i_cmd;
308
309 /* Turn all aborted commands in list to no-ops, then restart */
310 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
311
312 if (i_cmd->status != COMP_COMMAND_ABORTED)
313 continue;
314
315 i_cmd->status = COMP_COMMAND_RING_STOPPED;
316
317 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
318 i_cmd->command_trb);
319
320 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
321
322 /*
323 * caller waiting for completion is called when command
324 * completion event is received for these no-op commands
325 */
326 }
327
328 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
329
330 /* ring command ring doorbell to restart the command ring */
331 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
332 !(xhci->xhc_state & XHCI_STATE_DYING)) {
333 xhci->current_cmd = cur_cmd;
334 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
335 xhci_ring_cmd_db(xhci);
336 }
337}
338
339/* Must be called with xhci->lock held, releases and aquires lock back */
340static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
341{
342 u64 temp_64;
343 int ret;
344
345 xhci_dbg(xhci, "Abort command ring\n");
346
347 reinit_completion(&xhci->cmd_ring_stop_completion);
348
349 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
350 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
351 &xhci->op_regs->cmd_ring);
352
353 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
354 * completion of the Command Abort operation. If CRR is not negated in 5
355 * seconds then driver handles it as if host died (-ENODEV).
356 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
357 * and try to recover a -ETIMEDOUT with a host controller reset.
358 */
359 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
360 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
361 if (ret < 0) {
362 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
363 xhci_halt(xhci);
364 xhci_hc_died(xhci);
365 return ret;
366 }
367 /*
368 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
369 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
370 * but the completion event in never sent. Wait 2 secs (arbitrary
371 * number) to handle those cases after negation of CMD_RING_RUNNING.
372 */
373 spin_unlock_irqrestore(&xhci->lock, flags);
374 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
375 msecs_to_jiffies(2000));
376 spin_lock_irqsave(&xhci->lock, flags);
377 if (!ret) {
378 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
379 xhci_cleanup_command_queue(xhci);
380 } else {
381 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
382 }
383 return 0;
384}
385
386void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
387 unsigned int slot_id,
388 unsigned int ep_index,
389 unsigned int stream_id)
390{
391 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
392 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
393 unsigned int ep_state = ep->ep_state;
394
395 /* Don't ring the doorbell for this endpoint if there are pending
396 * cancellations because we don't want to interrupt processing.
397 * We don't want to restart any stream rings if there's a set dequeue
398 * pointer command pending because the device can choose to start any
399 * stream once the endpoint is on the HW schedule.
400 */
401 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
402 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
403 return;
404 writel(DB_VALUE(ep_index, stream_id), db_addr);
405 /* The CPU has better things to do at this point than wait for a
406 * write-posting flush. It'll get there soon enough.
407 */
408}
409
410/* Ring the doorbell for any rings with pending URBs */
411static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
412 unsigned int slot_id,
413 unsigned int ep_index)
414{
415 unsigned int stream_id;
416 struct xhci_virt_ep *ep;
417
418 ep = &xhci->devs[slot_id]->eps[ep_index];
419
420 /* A ring has pending URBs if its TD list is not empty */
421 if (!(ep->ep_state & EP_HAS_STREAMS)) {
422 if (ep->ring && !(list_empty(&ep->ring->td_list)))
423 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
424 return;
425 }
426
427 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
428 stream_id++) {
429 struct xhci_stream_info *stream_info = ep->stream_info;
430 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
431 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
432 stream_id);
433 }
434}
435
436void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
437 unsigned int slot_id,
438 unsigned int ep_index)
439{
440 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
441}
442
443/* Get the right ring for the given slot_id, ep_index and stream_id.
444 * If the endpoint supports streams, boundary check the URB's stream ID.
445 * If the endpoint doesn't support streams, return the singular endpoint ring.
446 */
447struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
448 unsigned int slot_id, unsigned int ep_index,
449 unsigned int stream_id)
450{
451 struct xhci_virt_ep *ep;
452
453 ep = &xhci->devs[slot_id]->eps[ep_index];
454 /* Common case: no streams */
455 if (!(ep->ep_state & EP_HAS_STREAMS))
456 return ep->ring;
457
458 if (stream_id == 0) {
459 xhci_warn(xhci,
460 "WARN: Slot ID %u, ep index %u has streams, "
461 "but URB has no stream ID.\n",
462 slot_id, ep_index);
463 return NULL;
464 }
465
466 if (stream_id < ep->stream_info->num_streams)
467 return ep->stream_info->stream_rings[stream_id];
468
469 xhci_warn(xhci,
470 "WARN: Slot ID %u, ep index %u has "
471 "stream IDs 1 to %u allocated, "
472 "but stream ID %u is requested.\n",
473 slot_id, ep_index,
474 ep->stream_info->num_streams - 1,
475 stream_id);
476 return NULL;
477}
478
479
480/*
481 * Get the hw dequeue pointer xHC stopped on, either directly from the
482 * endpoint context, or if streams are in use from the stream context.
483 * The returned hw_dequeue contains the lowest four bits with cycle state
484 * and possbile stream context type.
485 */
486static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
487 unsigned int ep_index, unsigned int stream_id)
488{
489 struct xhci_ep_ctx *ep_ctx;
490 struct xhci_stream_ctx *st_ctx;
491 struct xhci_virt_ep *ep;
492
493 ep = &vdev->eps[ep_index];
494
495 if (ep->ep_state & EP_HAS_STREAMS) {
496 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
497 return le64_to_cpu(st_ctx->stream_ring);
498 }
499 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
500 return le64_to_cpu(ep_ctx->deq);
501}
502
503/*
504 * Move the xHC's endpoint ring dequeue pointer past cur_td.
505 * Record the new state of the xHC's endpoint ring dequeue segment,
506 * dequeue pointer, stream id, and new consumer cycle state in state.
507 * Update our internal representation of the ring's dequeue pointer.
508 *
509 * We do this in three jumps:
510 * - First we update our new ring state to be the same as when the xHC stopped.
511 * - Then we traverse the ring to find the segment that contains
512 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
513 * any link TRBs with the toggle cycle bit set.
514 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
515 * if we've moved it past a link TRB with the toggle cycle bit set.
516 *
517 * Some of the uses of xhci_generic_trb are grotty, but if they're done
518 * with correct __le32 accesses they should work fine. Only users of this are
519 * in here.
520 */
521void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
522 unsigned int slot_id, unsigned int ep_index,
523 unsigned int stream_id, struct xhci_td *cur_td,
524 struct xhci_dequeue_state *state)
525{
526 struct xhci_virt_device *dev = xhci->devs[slot_id];
527 struct xhci_virt_ep *ep = &dev->eps[ep_index];
528 struct xhci_ring *ep_ring;
529 struct xhci_segment *new_seg;
530 union xhci_trb *new_deq;
531 dma_addr_t addr;
532 u64 hw_dequeue;
533 bool cycle_found = false;
534 bool td_last_trb_found = false;
535
536 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
537 ep_index, stream_id);
538 if (!ep_ring) {
539 xhci_warn(xhci, "WARN can't find new dequeue state "
540 "for invalid stream ID %u.\n",
541 stream_id);
542 return;
543 }
544 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
545 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
546 "Finding endpoint context");
547
548 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
549 new_seg = ep_ring->deq_seg;
550 new_deq = ep_ring->dequeue;
551 state->new_cycle_state = hw_dequeue & 0x1;
552 state->stream_id = stream_id;
553
554 /*
555 * We want to find the pointer, segment and cycle state of the new trb
556 * (the one after current TD's last_trb). We know the cycle state at
557 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
558 * found.
559 */
560 do {
561 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
562 == (dma_addr_t)(hw_dequeue & ~0xf)) {
563 cycle_found = true;
564 if (td_last_trb_found)
565 break;
566 }
567 if (new_deq == cur_td->last_trb)
568 td_last_trb_found = true;
569
570 if (cycle_found && trb_is_link(new_deq) &&
571 link_trb_toggles_cycle(new_deq))
572 state->new_cycle_state ^= 0x1;
573
574 next_trb(xhci, ep_ring, &new_seg, &new_deq);
575
576 /* Search wrapped around, bail out */
577 if (new_deq == ep->ring->dequeue) {
578 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
579 state->new_deq_seg = NULL;
580 state->new_deq_ptr = NULL;
581 return;
582 }
583
584 } while (!cycle_found || !td_last_trb_found);
585
586 state->new_deq_seg = new_seg;
587 state->new_deq_ptr = new_deq;
588
589 /* Don't update the ring cycle state for the producer (us). */
590 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
591 "Cycle state = 0x%x", state->new_cycle_state);
592
593 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
594 "New dequeue segment = %p (virtual)",
595 state->new_deq_seg);
596 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
597 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
598 "New dequeue pointer = 0x%llx (DMA)",
599 (unsigned long long) addr);
600}
601
602/* flip_cycle means flip the cycle bit of all but the first and last TRB.
603 * (The last TRB actually points to the ring enqueue pointer, which is not part
604 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
605 */
606static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
607 struct xhci_td *td, bool flip_cycle)
608{
609 struct xhci_segment *seg = td->start_seg;
610 union xhci_trb *trb = td->first_trb;
611
612 while (1) {
613 trb_to_noop(trb, TRB_TR_NOOP);
614
615 /* flip cycle if asked to */
616 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
617 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
618
619 if (trb == td->last_trb)
620 break;
621
622 next_trb(xhci, ep_ring, &seg, &trb);
623 }
624}
625
626static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
627 struct xhci_virt_ep *ep)
628{
629 ep->ep_state &= ~EP_STOP_CMD_PENDING;
630 /* Can't del_timer_sync in interrupt */
631 del_timer(&ep->stop_cmd_timer);
632}
633
634/*
635 * Must be called with xhci->lock held in interrupt context,
636 * releases and re-acquires xhci->lock
637 */
638static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
639 struct xhci_td *cur_td, int status)
640{
641 struct urb *urb = cur_td->urb;
642 struct urb_priv *urb_priv = urb->hcpriv;
643 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
644
645 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
646 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
647 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
648 if (xhci->quirks & XHCI_AMD_PLL_FIX)
649 usb_amd_quirk_pll_enable();
650 }
651 }
652 xhci_urb_free_priv(urb_priv);
653 usb_hcd_unlink_urb_from_ep(hcd, urb);
654 spin_unlock(&xhci->lock);
655 trace_xhci_urb_giveback(urb);
656 usb_hcd_giveback_urb(hcd, urb, status);
657 spin_lock(&xhci->lock);
658}
659
660static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
661 struct xhci_ring *ring, struct xhci_td *td)
662{
663 struct device *dev = xhci_to_hcd(xhci)->self.controller;
664 struct xhci_segment *seg = td->bounce_seg;
665 struct urb *urb = td->urb;
666 size_t len;
667
668 if (!ring || !seg || !urb)
669 return;
670
671 if (usb_urb_dir_out(urb)) {
672 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
673 DMA_TO_DEVICE);
674 return;
675 }
676
677 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
678 DMA_FROM_DEVICE);
679 /* for in tranfers we need to copy the data from bounce to sg */
680 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
681 seg->bounce_len, seg->bounce_offs);
682 if (len != seg->bounce_len)
683 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
684 len, seg->bounce_len);
685 seg->bounce_len = 0;
686 seg->bounce_offs = 0;
687}
688
689/*
690 * When we get a command completion for a Stop Endpoint Command, we need to
691 * unlink any cancelled TDs from the ring. There are two ways to do that:
692 *
693 * 1. If the HW was in the middle of processing the TD that needs to be
694 * cancelled, then we must move the ring's dequeue pointer past the last TRB
695 * in the TD with a Set Dequeue Pointer Command.
696 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
697 * bit cleared) so that the HW will skip over them.
698 */
699static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
700 union xhci_trb *trb, struct xhci_event_cmd *event)
701{
702 unsigned int ep_index;
703 struct xhci_ring *ep_ring;
704 struct xhci_virt_ep *ep;
705 struct xhci_td *cur_td = NULL;
706 struct xhci_td *last_unlinked_td;
707 struct xhci_ep_ctx *ep_ctx;
708 struct xhci_virt_device *vdev;
709 u64 hw_deq;
710 struct xhci_dequeue_state deq_state;
711
712 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
713 if (!xhci->devs[slot_id])
714 xhci_warn(xhci, "Stop endpoint command "
715 "completion for disabled slot %u\n",
716 slot_id);
717 return;
718 }
719
720 memset(&deq_state, 0, sizeof(deq_state));
721 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
722
723 vdev = xhci->devs[slot_id];
724 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
725 trace_xhci_handle_cmd_stop_ep(ep_ctx);
726
727 ep = &xhci->devs[slot_id]->eps[ep_index];
728 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
729 struct xhci_td, cancelled_td_list);
730
731 if (list_empty(&ep->cancelled_td_list)) {
732 xhci_stop_watchdog_timer_in_irq(xhci, ep);
733 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
734 return;
735 }
736
737 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
738 * We have the xHCI lock, so nothing can modify this list until we drop
739 * it. We're also in the event handler, so we can't get re-interrupted
740 * if another Stop Endpoint command completes
741 */
742 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
743 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
744 "Removing canceled TD starting at 0x%llx (dma).",
745 (unsigned long long)xhci_trb_virt_to_dma(
746 cur_td->start_seg, cur_td->first_trb));
747 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
748 if (!ep_ring) {
749 /* This shouldn't happen unless a driver is mucking
750 * with the stream ID after submission. This will
751 * leave the TD on the hardware ring, and the hardware
752 * will try to execute it, and may access a buffer
753 * that has already been freed. In the best case, the
754 * hardware will execute it, and the event handler will
755 * ignore the completion event for that TD, since it was
756 * removed from the td_list for that endpoint. In
757 * short, don't muck with the stream ID after
758 * submission.
759 */
760 xhci_warn(xhci, "WARN Cancelled URB %p "
761 "has invalid stream ID %u.\n",
762 cur_td->urb,
763 cur_td->urb->stream_id);
764 goto remove_finished_td;
765 }
766 /*
767 * If we stopped on the TD we need to cancel, then we have to
768 * move the xHC endpoint ring dequeue pointer past this TD.
769 */
770 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
771 cur_td->urb->stream_id);
772 hw_deq &= ~0xf;
773
774 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
775 cur_td->last_trb, hw_deq, false)) {
776 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
777 cur_td->urb->stream_id,
778 cur_td, &deq_state);
779 } else {
780 td_to_noop(xhci, ep_ring, cur_td, false);
781 }
782
783remove_finished_td:
784 /*
785 * The event handler won't see a completion for this TD anymore,
786 * so remove it from the endpoint ring's TD list. Keep it in
787 * the cancelled TD list for URB completion later.
788 */
789 list_del_init(&cur_td->td_list);
790 }
791
792 xhci_stop_watchdog_timer_in_irq(xhci, ep);
793
794 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
795 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
796 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
797 &deq_state);
798 xhci_ring_cmd_db(xhci);
799 } else {
800 /* Otherwise ring the doorbell(s) to restart queued transfers */
801 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
802 }
803
804 /*
805 * Drop the lock and complete the URBs in the cancelled TD list.
806 * New TDs to be cancelled might be added to the end of the list before
807 * we can complete all the URBs for the TDs we already unlinked.
808 * So stop when we've completed the URB for the last TD we unlinked.
809 */
810 do {
811 cur_td = list_first_entry(&ep->cancelled_td_list,
812 struct xhci_td, cancelled_td_list);
813 list_del_init(&cur_td->cancelled_td_list);
814
815 /* Clean up the cancelled URB */
816 /* Doesn't matter what we pass for status, since the core will
817 * just overwrite it (because the URB has been unlinked).
818 */
819 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
820 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
821 inc_td_cnt(cur_td->urb);
822 if (last_td_in_urb(cur_td))
823 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
824
825 /* Stop processing the cancelled list if the watchdog timer is
826 * running.
827 */
828 if (xhci->xhc_state & XHCI_STATE_DYING)
829 return;
830 } while (cur_td != last_unlinked_td);
831
832 /* Return to the event handler with xhci->lock re-acquired */
833}
834
835static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
836{
837 struct xhci_td *cur_td;
838 struct xhci_td *tmp;
839
840 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
841 list_del_init(&cur_td->td_list);
842
843 if (!list_empty(&cur_td->cancelled_td_list))
844 list_del_init(&cur_td->cancelled_td_list);
845
846 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
847
848 inc_td_cnt(cur_td->urb);
849 if (last_td_in_urb(cur_td))
850 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
851 }
852}
853
854static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
855 int slot_id, int ep_index)
856{
857 struct xhci_td *cur_td;
858 struct xhci_td *tmp;
859 struct xhci_virt_ep *ep;
860 struct xhci_ring *ring;
861
862 ep = &xhci->devs[slot_id]->eps[ep_index];
863 if ((ep->ep_state & EP_HAS_STREAMS) ||
864 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
865 int stream_id;
866
867 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
868 stream_id++) {
869 ring = ep->stream_info->stream_rings[stream_id];
870 if (!ring)
871 continue;
872
873 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
874 "Killing URBs for slot ID %u, ep index %u, stream %u",
875 slot_id, ep_index, stream_id);
876 xhci_kill_ring_urbs(xhci, ring);
877 }
878 } else {
879 ring = ep->ring;
880 if (!ring)
881 return;
882 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
883 "Killing URBs for slot ID %u, ep index %u",
884 slot_id, ep_index);
885 xhci_kill_ring_urbs(xhci, ring);
886 }
887
888 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
889 cancelled_td_list) {
890 list_del_init(&cur_td->cancelled_td_list);
891 inc_td_cnt(cur_td->urb);
892
893 if (last_td_in_urb(cur_td))
894 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
895 }
896}
897
898/*
899 * host controller died, register read returns 0xffffffff
900 * Complete pending commands, mark them ABORTED.
901 * URBs need to be given back as usb core might be waiting with device locks
902 * held for the URBs to finish during device disconnect, blocking host remove.
903 *
904 * Call with xhci->lock held.
905 * lock is relased and re-acquired while giving back urb.
906 */
907void xhci_hc_died(struct xhci_hcd *xhci)
908{
909 int i, j;
910
911 if (xhci->xhc_state & XHCI_STATE_DYING)
912 return;
913
914 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
915 xhci->xhc_state |= XHCI_STATE_DYING;
916
917 xhci_cleanup_command_queue(xhci);
918
919 /* return any pending urbs, remove may be waiting for them */
920 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
921 if (!xhci->devs[i])
922 continue;
923 for (j = 0; j < 31; j++)
924 xhci_kill_endpoint_urbs(xhci, i, j);
925 }
926
927 /* inform usb core hc died if PCI remove isn't already handling it */
928 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
929 usb_hc_died(xhci_to_hcd(xhci));
930}
931
932/* Watchdog timer function for when a stop endpoint command fails to complete.
933 * In this case, we assume the host controller is broken or dying or dead. The
934 * host may still be completing some other events, so we have to be careful to
935 * let the event ring handler and the URB dequeueing/enqueueing functions know
936 * through xhci->state.
937 *
938 * The timer may also fire if the host takes a very long time to respond to the
939 * command, and the stop endpoint command completion handler cannot delete the
940 * timer before the timer function is called. Another endpoint cancellation may
941 * sneak in before the timer function can grab the lock, and that may queue
942 * another stop endpoint command and add the timer back. So we cannot use a
943 * simple flag to say whether there is a pending stop endpoint command for a
944 * particular endpoint.
945 *
946 * Instead we use a combination of that flag and checking if a new timer is
947 * pending.
948 */
949void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
950{
951 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
952 struct xhci_hcd *xhci = ep->xhci;
953 unsigned long flags;
954
955 spin_lock_irqsave(&xhci->lock, flags);
956
957 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
958 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
959 timer_pending(&ep->stop_cmd_timer)) {
960 spin_unlock_irqrestore(&xhci->lock, flags);
961 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
962 return;
963 }
964
965 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
966 ep->ep_state &= ~EP_STOP_CMD_PENDING;
967
968 xhci_halt(xhci);
969
970 /*
971 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
972 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
973 * and try to recover a -ETIMEDOUT with a host controller reset
974 */
975 xhci_hc_died(xhci);
976
977 spin_unlock_irqrestore(&xhci->lock, flags);
978 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
979 "xHCI host controller is dead.");
980}
981
982static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
983 struct xhci_virt_device *dev,
984 struct xhci_ring *ep_ring,
985 unsigned int ep_index)
986{
987 union xhci_trb *dequeue_temp;
988 int num_trbs_free_temp;
989 bool revert = false;
990
991 num_trbs_free_temp = ep_ring->num_trbs_free;
992 dequeue_temp = ep_ring->dequeue;
993
994 /* If we get two back-to-back stalls, and the first stalled transfer
995 * ends just before a link TRB, the dequeue pointer will be left on
996 * the link TRB by the code in the while loop. So we have to update
997 * the dequeue pointer one segment further, or we'll jump off
998 * the segment into la-la-land.
999 */
1000 if (trb_is_link(ep_ring->dequeue)) {
1001 ep_ring->deq_seg = ep_ring->deq_seg->next;
1002 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1003 }
1004
1005 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1006 /* We have more usable TRBs */
1007 ep_ring->num_trbs_free++;
1008 ep_ring->dequeue++;
1009 if (trb_is_link(ep_ring->dequeue)) {
1010 if (ep_ring->dequeue ==
1011 dev->eps[ep_index].queued_deq_ptr)
1012 break;
1013 ep_ring->deq_seg = ep_ring->deq_seg->next;
1014 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1015 }
1016 if (ep_ring->dequeue == dequeue_temp) {
1017 revert = true;
1018 break;
1019 }
1020 }
1021
1022 if (revert) {
1023 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1024 ep_ring->num_trbs_free = num_trbs_free_temp;
1025 }
1026}
1027
1028/*
1029 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1030 * we need to clear the set deq pending flag in the endpoint ring state, so that
1031 * the TD queueing code can ring the doorbell again. We also need to ring the
1032 * endpoint doorbell to restart the ring, but only if there aren't more
1033 * cancellations pending.
1034 */
1035static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1036 union xhci_trb *trb, u32 cmd_comp_code)
1037{
1038 unsigned int ep_index;
1039 unsigned int stream_id;
1040 struct xhci_ring *ep_ring;
1041 struct xhci_virt_device *dev;
1042 struct xhci_virt_ep *ep;
1043 struct xhci_ep_ctx *ep_ctx;
1044 struct xhci_slot_ctx *slot_ctx;
1045
1046 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1047 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1048 dev = xhci->devs[slot_id];
1049 ep = &dev->eps[ep_index];
1050
1051 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1052 if (!ep_ring) {
1053 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1054 stream_id);
1055 /* XXX: Harmless??? */
1056 goto cleanup;
1057 }
1058
1059 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1060 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1061 trace_xhci_handle_cmd_set_deq(slot_ctx);
1062 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1063
1064 if (cmd_comp_code != COMP_SUCCESS) {
1065 unsigned int ep_state;
1066 unsigned int slot_state;
1067
1068 switch (cmd_comp_code) {
1069 case COMP_TRB_ERROR:
1070 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1071 break;
1072 case COMP_CONTEXT_STATE_ERROR:
1073 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1074 ep_state = GET_EP_CTX_STATE(ep_ctx);
1075 slot_state = le32_to_cpu(slot_ctx->dev_state);
1076 slot_state = GET_SLOT_STATE(slot_state);
1077 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1078 "Slot state = %u, EP state = %u",
1079 slot_state, ep_state);
1080 break;
1081 case COMP_SLOT_NOT_ENABLED_ERROR:
1082 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1083 slot_id);
1084 break;
1085 default:
1086 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1087 cmd_comp_code);
1088 break;
1089 }
1090 /* OK what do we do now? The endpoint state is hosed, and we
1091 * should never get to this point if the synchronization between
1092 * queueing, and endpoint state are correct. This might happen
1093 * if the device gets disconnected after we've finished
1094 * cancelling URBs, which might not be an error...
1095 */
1096 } else {
1097 u64 deq;
1098 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1099 if (ep->ep_state & EP_HAS_STREAMS) {
1100 struct xhci_stream_ctx *ctx =
1101 &ep->stream_info->stream_ctx_array[stream_id];
1102 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1103 } else {
1104 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1105 }
1106 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1107 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1108 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1109 ep->queued_deq_ptr) == deq) {
1110 /* Update the ring's dequeue segment and dequeue pointer
1111 * to reflect the new position.
1112 */
1113 update_ring_for_set_deq_completion(xhci, dev,
1114 ep_ring, ep_index);
1115 } else {
1116 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1117 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1118 ep->queued_deq_seg, ep->queued_deq_ptr);
1119 }
1120 }
1121
1122cleanup:
1123 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1124 dev->eps[ep_index].queued_deq_seg = NULL;
1125 dev->eps[ep_index].queued_deq_ptr = NULL;
1126 /* Restart any rings with pending URBs */
1127 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1128}
1129
1130static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1131 union xhci_trb *trb, u32 cmd_comp_code)
1132{
1133 struct xhci_virt_device *vdev;
1134 struct xhci_ep_ctx *ep_ctx;
1135 unsigned int ep_index;
1136
1137 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1138 vdev = xhci->devs[slot_id];
1139 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1140 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1141
1142 /* This command will only fail if the endpoint wasn't halted,
1143 * but we don't care.
1144 */
1145 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1146 "Ignoring reset ep completion code of %u", cmd_comp_code);
1147
1148 /* HW with the reset endpoint quirk needs to have a configure endpoint
1149 * command complete before the endpoint can be used. Queue that here
1150 * because the HW can't handle two commands being queued in a row.
1151 */
1152 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1153 struct xhci_command *command;
1154
1155 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1156 if (!command)
1157 return;
1158
1159 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1160 "Queueing configure endpoint command");
1161 xhci_queue_configure_endpoint(xhci, command,
1162 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1163 false);
1164 xhci_ring_cmd_db(xhci);
1165 } else {
1166 /* Clear our internal halted state */
1167 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1168 }
1169
1170 /* if this was a soft reset, then restart */
1171 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1172 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1173}
1174
1175static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1176 struct xhci_command *command, u32 cmd_comp_code)
1177{
1178 if (cmd_comp_code == COMP_SUCCESS)
1179 command->slot_id = slot_id;
1180 else
1181 command->slot_id = 0;
1182}
1183
1184static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1185{
1186 struct xhci_virt_device *virt_dev;
1187 struct xhci_slot_ctx *slot_ctx;
1188
1189 virt_dev = xhci->devs[slot_id];
1190 if (!virt_dev)
1191 return;
1192
1193 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1194 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1195
1196 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1197 /* Delete default control endpoint resources */
1198 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1199 xhci_free_virt_device(xhci, slot_id);
1200}
1201
1202static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1203 struct xhci_event_cmd *event, u32 cmd_comp_code)
1204{
1205 struct xhci_virt_device *virt_dev;
1206 struct xhci_input_control_ctx *ctrl_ctx;
1207 struct xhci_ep_ctx *ep_ctx;
1208 unsigned int ep_index;
1209 unsigned int ep_state;
1210 u32 add_flags, drop_flags;
1211
1212 /*
1213 * Configure endpoint commands can come from the USB core
1214 * configuration or alt setting changes, or because the HW
1215 * needed an extra configure endpoint command after a reset
1216 * endpoint command or streams were being configured.
1217 * If the command was for a halted endpoint, the xHCI driver
1218 * is not waiting on the configure endpoint command.
1219 */
1220 virt_dev = xhci->devs[slot_id];
1221 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1222 if (!ctrl_ctx) {
1223 xhci_warn(xhci, "Could not get input context, bad type.\n");
1224 return;
1225 }
1226
1227 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1228 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1229 /* Input ctx add_flags are the endpoint index plus one */
1230 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1231
1232 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1233 trace_xhci_handle_cmd_config_ep(ep_ctx);
1234
1235 /* A usb_set_interface() call directly after clearing a halted
1236 * condition may race on this quirky hardware. Not worth
1237 * worrying about, since this is prototype hardware. Not sure
1238 * if this will work for streams, but streams support was
1239 * untested on this prototype.
1240 */
1241 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1242 ep_index != (unsigned int) -1 &&
1243 add_flags - SLOT_FLAG == drop_flags) {
1244 ep_state = virt_dev->eps[ep_index].ep_state;
1245 if (!(ep_state & EP_HALTED))
1246 return;
1247 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1248 "Completed config ep cmd - "
1249 "last ep index = %d, state = %d",
1250 ep_index, ep_state);
1251 /* Clear internal halted state and restart ring(s) */
1252 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1253 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1254 return;
1255 }
1256 return;
1257}
1258
1259static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1260{
1261 struct xhci_virt_device *vdev;
1262 struct xhci_slot_ctx *slot_ctx;
1263
1264 vdev = xhci->devs[slot_id];
1265 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1266 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1267}
1268
1269static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1270 struct xhci_event_cmd *event)
1271{
1272 struct xhci_virt_device *vdev;
1273 struct xhci_slot_ctx *slot_ctx;
1274
1275 vdev = xhci->devs[slot_id];
1276 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1277 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1278
1279 xhci_dbg(xhci, "Completed reset device command.\n");
1280 if (!xhci->devs[slot_id])
1281 xhci_warn(xhci, "Reset device command completion "
1282 "for disabled slot %u\n", slot_id);
1283}
1284
1285static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1286 struct xhci_event_cmd *event)
1287{
1288 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1289 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1290 return;
1291 }
1292 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1293 "NEC firmware version %2x.%02x",
1294 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1295 NEC_FW_MINOR(le32_to_cpu(event->status)));
1296}
1297
1298static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1299{
1300 list_del(&cmd->cmd_list);
1301
1302 if (cmd->completion) {
1303 cmd->status = status;
1304 complete(cmd->completion);
1305 } else {
1306 kfree(cmd);
1307 }
1308}
1309
1310void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1311{
1312 struct xhci_command *cur_cmd, *tmp_cmd;
1313 xhci->current_cmd = NULL;
1314 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1315 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1316}
1317
1318void xhci_handle_command_timeout(struct work_struct *work)
1319{
1320 struct xhci_hcd *xhci;
1321 unsigned long flags;
1322 u64 hw_ring_state;
1323
1324 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1325
1326 spin_lock_irqsave(&xhci->lock, flags);
1327
1328 /*
1329 * If timeout work is pending, or current_cmd is NULL, it means we
1330 * raced with command completion. Command is handled so just return.
1331 */
1332 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1333 spin_unlock_irqrestore(&xhci->lock, flags);
1334 return;
1335 }
1336 /* mark this command to be cancelled */
1337 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1338
1339 /* Make sure command ring is running before aborting it */
1340 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1341 if (hw_ring_state == ~(u64)0) {
1342 xhci_hc_died(xhci);
1343 goto time_out_completed;
1344 }
1345
1346 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1347 (hw_ring_state & CMD_RING_RUNNING)) {
1348 /* Prevent new doorbell, and start command abort */
1349 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1350 xhci_dbg(xhci, "Command timeout\n");
1351 xhci_abort_cmd_ring(xhci, flags);
1352 goto time_out_completed;
1353 }
1354
1355 /* host removed. Bail out */
1356 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1357 xhci_dbg(xhci, "host removed, ring start fail?\n");
1358 xhci_cleanup_command_queue(xhci);
1359
1360 goto time_out_completed;
1361 }
1362
1363 /* command timeout on stopped ring, ring can't be aborted */
1364 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1365 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1366
1367time_out_completed:
1368 spin_unlock_irqrestore(&xhci->lock, flags);
1369 return;
1370}
1371
1372static void handle_cmd_completion(struct xhci_hcd *xhci,
1373 struct xhci_event_cmd *event)
1374{
1375 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1376 u64 cmd_dma;
1377 dma_addr_t cmd_dequeue_dma;
1378 u32 cmd_comp_code;
1379 union xhci_trb *cmd_trb;
1380 struct xhci_command *cmd;
1381 u32 cmd_type;
1382
1383 cmd_dma = le64_to_cpu(event->cmd_trb);
1384 cmd_trb = xhci->cmd_ring->dequeue;
1385
1386 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1387
1388 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1389 cmd_trb);
1390 /*
1391 * Check whether the completion event is for our internal kept
1392 * command.
1393 */
1394 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1395 xhci_warn(xhci,
1396 "ERROR mismatched command completion event\n");
1397 return;
1398 }
1399
1400 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1401
1402 cancel_delayed_work(&xhci->cmd_timer);
1403
1404 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1405
1406 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1407 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1408 complete_all(&xhci->cmd_ring_stop_completion);
1409 return;
1410 }
1411
1412 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1413 xhci_err(xhci,
1414 "Command completion event does not match command\n");
1415 return;
1416 }
1417
1418 /*
1419 * Host aborted the command ring, check if the current command was
1420 * supposed to be aborted, otherwise continue normally.
1421 * The command ring is stopped now, but the xHC will issue a Command
1422 * Ring Stopped event which will cause us to restart it.
1423 */
1424 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1425 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1426 if (cmd->status == COMP_COMMAND_ABORTED) {
1427 if (xhci->current_cmd == cmd)
1428 xhci->current_cmd = NULL;
1429 goto event_handled;
1430 }
1431 }
1432
1433 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1434 switch (cmd_type) {
1435 case TRB_ENABLE_SLOT:
1436 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1437 break;
1438 case TRB_DISABLE_SLOT:
1439 xhci_handle_cmd_disable_slot(xhci, slot_id);
1440 break;
1441 case TRB_CONFIG_EP:
1442 if (!cmd->completion)
1443 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1444 cmd_comp_code);
1445 break;
1446 case TRB_EVAL_CONTEXT:
1447 break;
1448 case TRB_ADDR_DEV:
1449 xhci_handle_cmd_addr_dev(xhci, slot_id);
1450 break;
1451 case TRB_STOP_RING:
1452 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1453 le32_to_cpu(cmd_trb->generic.field[3])));
1454 if (!cmd->completion)
1455 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1456 break;
1457 case TRB_SET_DEQ:
1458 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1459 le32_to_cpu(cmd_trb->generic.field[3])));
1460 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1461 break;
1462 case TRB_CMD_NOOP:
1463 /* Is this an aborted command turned to NO-OP? */
1464 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1465 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1466 break;
1467 case TRB_RESET_EP:
1468 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1469 le32_to_cpu(cmd_trb->generic.field[3])));
1470 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1471 break;
1472 case TRB_RESET_DEV:
1473 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1474 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1475 */
1476 slot_id = TRB_TO_SLOT_ID(
1477 le32_to_cpu(cmd_trb->generic.field[3]));
1478 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1479 break;
1480 case TRB_NEC_GET_FW:
1481 xhci_handle_cmd_nec_get_fw(xhci, event);
1482 break;
1483 default:
1484 /* Skip over unknown commands on the event ring */
1485 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1486 break;
1487 }
1488
1489 /* restart timer if this wasn't the last command */
1490 if (!list_is_singular(&xhci->cmd_list)) {
1491 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1492 struct xhci_command, cmd_list);
1493 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1494 } else if (xhci->current_cmd == cmd) {
1495 xhci->current_cmd = NULL;
1496 }
1497
1498event_handled:
1499 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1500
1501 inc_deq(xhci, xhci->cmd_ring);
1502}
1503
1504static void handle_vendor_event(struct xhci_hcd *xhci,
1505 union xhci_trb *event)
1506{
1507 u32 trb_type;
1508
1509 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1510 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1511 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1512 handle_cmd_completion(xhci, &event->event_cmd);
1513}
1514
1515static void handle_device_notification(struct xhci_hcd *xhci,
1516 union xhci_trb *event)
1517{
1518 u32 slot_id;
1519 struct usb_device *udev;
1520
1521 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1522 if (!xhci->devs[slot_id]) {
1523 xhci_warn(xhci, "Device Notification event for "
1524 "unused slot %u\n", slot_id);
1525 return;
1526 }
1527
1528 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1529 slot_id);
1530 udev = xhci->devs[slot_id]->udev;
1531 if (udev && udev->parent)
1532 usb_wakeup_notification(udev->parent, udev->portnum);
1533}
1534
1535/*
1536 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1537 * Controller.
1538 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1539 * If a connection to a USB 1 device is followed by another connection
1540 * to a USB 2 device.
1541 *
1542 * Reset the PHY after the USB device is disconnected if device speed
1543 * is less than HCD_USB3.
1544 * Retry the reset sequence max of 4 times checking the PLL lock status.
1545 *
1546 */
1547static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1548{
1549 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1550 u32 pll_lock_check;
1551 u32 retry_count = 4;
1552
1553 do {
1554 /* Assert PHY reset */
1555 writel(0x6F, hcd->regs + 0x1048);
1556 udelay(10);
1557 /* De-assert the PHY reset */
1558 writel(0x7F, hcd->regs + 0x1048);
1559 udelay(200);
1560 pll_lock_check = readl(hcd->regs + 0x1070);
1561 } while (!(pll_lock_check & 0x1) && --retry_count);
1562}
1563
1564static void handle_port_status(struct xhci_hcd *xhci,
1565 union xhci_trb *event)
1566{
1567 struct usb_hcd *hcd;
1568 u32 port_id;
1569 u32 portsc, cmd_reg;
1570 int max_ports;
1571 int slot_id;
1572 unsigned int hcd_portnum;
1573 struct xhci_bus_state *bus_state;
1574 bool bogus_port_status = false;
1575 struct xhci_port *port;
1576
1577 /* Port status change events always have a successful completion code */
1578 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1579 xhci_warn(xhci,
1580 "WARN: xHC returned failed port status event\n");
1581
1582 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1583 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1584
1585 if ((port_id <= 0) || (port_id > max_ports)) {
1586 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1587 port_id);
1588 inc_deq(xhci, xhci->event_ring);
1589 return;
1590 }
1591
1592 port = &xhci->hw_ports[port_id - 1];
1593 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1594 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1595 port_id);
1596 bogus_port_status = true;
1597 goto cleanup;
1598 }
1599
1600 /* We might get interrupts after shared_hcd is removed */
1601 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1602 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1603 bogus_port_status = true;
1604 goto cleanup;
1605 }
1606
1607 hcd = port->rhub->hcd;
1608 bus_state = &port->rhub->bus_state;
1609 hcd_portnum = port->hcd_portnum;
1610 portsc = readl(port->addr);
1611
1612 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1613 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1614
1615 trace_xhci_handle_port_status(hcd_portnum, portsc);
1616
1617 if (hcd->state == HC_STATE_SUSPENDED) {
1618 xhci_dbg(xhci, "resume root hub\n");
1619 usb_hcd_resume_root_hub(hcd);
1620 }
1621
1622 if (hcd->speed >= HCD_USB3 &&
1623 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1624 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1625 if (slot_id && xhci->devs[slot_id])
1626 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1627 bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
1628 }
1629
1630 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1631 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1632
1633 cmd_reg = readl(&xhci->op_regs->command);
1634 if (!(cmd_reg & CMD_RUN)) {
1635 xhci_warn(xhci, "xHC is not running.\n");
1636 goto cleanup;
1637 }
1638
1639 if (DEV_SUPERSPEED_ANY(portsc)) {
1640 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1641 /* Set a flag to say the port signaled remote wakeup,
1642 * so we can tell the difference between the end of
1643 * device and host initiated resume.
1644 */
1645 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1646 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1647 xhci_set_link_state(xhci, port, XDEV_U0);
1648 /* Need to wait until the next link state change
1649 * indicates the device is actually in U0.
1650 */
1651 bogus_port_status = true;
1652 goto cleanup;
1653 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1654 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1655 bus_state->resume_done[hcd_portnum] = jiffies +
1656 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1657 set_bit(hcd_portnum, &bus_state->resuming_ports);
1658 /* Do the rest in GetPortStatus after resume time delay.
1659 * Avoid polling roothub status before that so that a
1660 * usb device auto-resume latency around ~40ms.
1661 */
1662 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1663 mod_timer(&hcd->rh_timer,
1664 bus_state->resume_done[hcd_portnum]);
1665 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1666 bogus_port_status = true;
1667 }
1668 }
1669
1670 if ((portsc & PORT_PLC) &&
1671 DEV_SUPERSPEED_ANY(portsc) &&
1672 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1673 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1674 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1675 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1676 /* We've just brought the device into U0/1/2 through either the
1677 * Resume state after a device remote wakeup, or through the
1678 * U3Exit state after a host-initiated resume. If it's a device
1679 * initiated remote wake, don't pass up the link state change,
1680 * so the roothub behavior is consistent with external
1681 * USB 3.0 hub behavior.
1682 */
1683 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1684 if (slot_id && xhci->devs[slot_id])
1685 xhci_ring_device(xhci, slot_id);
1686 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1687 bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
1688 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1689 usb_wakeup_notification(hcd->self.root_hub,
1690 hcd_portnum + 1);
1691 bogus_port_status = true;
1692 goto cleanup;
1693 }
1694 }
1695
1696 /*
1697 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1698 * RExit to a disconnect state). If so, let the the driver know it's
1699 * out of the RExit state.
1700 */
1701 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1702 test_and_clear_bit(hcd_portnum,
1703 &bus_state->rexit_ports)) {
1704 complete(&bus_state->rexit_done[hcd_portnum]);
1705 bogus_port_status = true;
1706 goto cleanup;
1707 }
1708
1709 if (hcd->speed < HCD_USB3) {
1710 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1711 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1712 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1713 xhci_cavium_reset_phy_quirk(xhci);
1714 }
1715
1716cleanup:
1717 /* Update event ring dequeue pointer before dropping the lock */
1718 inc_deq(xhci, xhci->event_ring);
1719
1720 /* Don't make the USB core poll the roothub if we got a bad port status
1721 * change event. Besides, at that point we can't tell which roothub
1722 * (USB 2.0 or USB 3.0) to kick.
1723 */
1724 if (bogus_port_status)
1725 return;
1726
1727 /*
1728 * xHCI port-status-change events occur when the "or" of all the
1729 * status-change bits in the portsc register changes from 0 to 1.
1730 * New status changes won't cause an event if any other change
1731 * bits are still set. When an event occurs, switch over to
1732 * polling to avoid losing status changes.
1733 */
1734 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1735 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1736 spin_unlock(&xhci->lock);
1737 /* Pass this up to the core */
1738 usb_hcd_poll_rh_status(hcd);
1739 spin_lock(&xhci->lock);
1740}
1741
1742/*
1743 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1744 * at end_trb, which may be in another segment. If the suspect DMA address is a
1745 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1746 * returns 0.
1747 */
1748struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1749 struct xhci_segment *start_seg,
1750 union xhci_trb *start_trb,
1751 union xhci_trb *end_trb,
1752 dma_addr_t suspect_dma,
1753 bool debug)
1754{
1755 dma_addr_t start_dma;
1756 dma_addr_t end_seg_dma;
1757 dma_addr_t end_trb_dma;
1758 struct xhci_segment *cur_seg;
1759
1760 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1761 cur_seg = start_seg;
1762
1763 do {
1764 if (start_dma == 0)
1765 return NULL;
1766 /* We may get an event for a Link TRB in the middle of a TD */
1767 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1768 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1769 /* If the end TRB isn't in this segment, this is set to 0 */
1770 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1771
1772 if (debug)
1773 xhci_warn(xhci,
1774 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1775 (unsigned long long)suspect_dma,
1776 (unsigned long long)start_dma,
1777 (unsigned long long)end_trb_dma,
1778 (unsigned long long)cur_seg->dma,
1779 (unsigned long long)end_seg_dma);
1780
1781 if (end_trb_dma > 0) {
1782 /* The end TRB is in this segment, so suspect should be here */
1783 if (start_dma <= end_trb_dma) {
1784 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1785 return cur_seg;
1786 } else {
1787 /* Case for one segment with
1788 * a TD wrapped around to the top
1789 */
1790 if ((suspect_dma >= start_dma &&
1791 suspect_dma <= end_seg_dma) ||
1792 (suspect_dma >= cur_seg->dma &&
1793 suspect_dma <= end_trb_dma))
1794 return cur_seg;
1795 }
1796 return NULL;
1797 } else {
1798 /* Might still be somewhere in this segment */
1799 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1800 return cur_seg;
1801 }
1802 cur_seg = cur_seg->next;
1803 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1804 } while (cur_seg != start_seg);
1805
1806 return NULL;
1807}
1808
1809static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
1810 struct xhci_virt_ep *ep)
1811{
1812 /*
1813 * As part of low/full-speed endpoint-halt processing
1814 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
1815 */
1816 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
1817 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
1818 !(ep->ep_state & EP_CLEARING_TT)) {
1819 ep->ep_state |= EP_CLEARING_TT;
1820 td->urb->ep->hcpriv = td->urb->dev;
1821 if (usb_hub_clear_tt_buffer(td->urb))
1822 ep->ep_state &= ~EP_CLEARING_TT;
1823 }
1824}
1825
1826static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1827 unsigned int slot_id, unsigned int ep_index,
1828 unsigned int stream_id, struct xhci_td *td,
1829 enum xhci_ep_reset_type reset_type)
1830{
1831 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1832 struct xhci_command *command;
1833
1834 /*
1835 * Avoid resetting endpoint if link is inactive. Can cause host hang.
1836 * Device will be reset soon to recover the link so don't do anything
1837 */
1838 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1839 return;
1840
1841 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1842 if (!command)
1843 return;
1844
1845 ep->ep_state |= EP_HALTED;
1846
1847 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1848
1849 if (reset_type == EP_HARD_RESET) {
1850 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1851 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1852 xhci_clear_hub_tt_buffer(xhci, td, ep);
1853 }
1854 xhci_ring_cmd_db(xhci);
1855}
1856
1857/* Check if an error has halted the endpoint ring. The class driver will
1858 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1859 * However, a babble and other errors also halt the endpoint ring, and the class
1860 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1861 * Ring Dequeue Pointer command manually.
1862 */
1863static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1864 struct xhci_ep_ctx *ep_ctx,
1865 unsigned int trb_comp_code)
1866{
1867 /* TRB completion codes that may require a manual halt cleanup */
1868 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1869 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1870 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1871 /* The 0.95 spec says a babbling control endpoint
1872 * is not halted. The 0.96 spec says it is. Some HW
1873 * claims to be 0.95 compliant, but it halts the control
1874 * endpoint anyway. Check if a babble halted the
1875 * endpoint.
1876 */
1877 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1878 return 1;
1879
1880 return 0;
1881}
1882
1883int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1884{
1885 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1886 /* Vendor defined "informational" completion code,
1887 * treat as not-an-error.
1888 */
1889 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1890 trb_comp_code);
1891 xhci_dbg(xhci, "Treating code as success.\n");
1892 return 1;
1893 }
1894 return 0;
1895}
1896
1897static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1898 struct xhci_ring *ep_ring, int *status)
1899{
1900 struct urb *urb = NULL;
1901
1902 /* Clean up the endpoint's TD list */
1903 urb = td->urb;
1904
1905 /* if a bounce buffer was used to align this td then unmap it */
1906 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1907
1908 /* Do one last check of the actual transfer length.
1909 * If the host controller said we transferred more data than the buffer
1910 * length, urb->actual_length will be a very big number (since it's
1911 * unsigned). Play it safe and say we didn't transfer anything.
1912 */
1913 if (urb->actual_length > urb->transfer_buffer_length) {
1914 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1915 urb->transfer_buffer_length, urb->actual_length);
1916 urb->actual_length = 0;
1917 *status = 0;
1918 }
1919 list_del_init(&td->td_list);
1920 /* Was this TD slated to be cancelled but completed anyway? */
1921 if (!list_empty(&td->cancelled_td_list))
1922 list_del_init(&td->cancelled_td_list);
1923
1924 inc_td_cnt(urb);
1925 /* Giveback the urb when all the tds are completed */
1926 if (last_td_in_urb(td)) {
1927 if ((urb->actual_length != urb->transfer_buffer_length &&
1928 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1929 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1930 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1931 urb, urb->actual_length,
1932 urb->transfer_buffer_length, *status);
1933
1934 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1935 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1936 *status = 0;
1937 xhci_giveback_urb_in_irq(xhci, td, *status);
1938 }
1939
1940 return 0;
1941}
1942
1943static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1944 struct xhci_transfer_event *event,
1945 struct xhci_virt_ep *ep, int *status)
1946{
1947 struct xhci_virt_device *xdev;
1948 struct xhci_ep_ctx *ep_ctx;
1949 struct xhci_ring *ep_ring;
1950 unsigned int slot_id;
1951 u32 trb_comp_code;
1952 int ep_index;
1953
1954 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1955 xdev = xhci->devs[slot_id];
1956 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1957 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1958 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1959 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1960
1961 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1962 trb_comp_code == COMP_STOPPED ||
1963 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1964 /* The Endpoint Stop Command completion will take care of any
1965 * stopped TDs. A stopped TD may be restarted, so don't update
1966 * the ring dequeue pointer or take this TD off any lists yet.
1967 */
1968 return 0;
1969 }
1970 if (trb_comp_code == COMP_STALL_ERROR ||
1971 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1972 trb_comp_code)) {
1973 /* Issue a reset endpoint command to clear the host side
1974 * halt, followed by a set dequeue command to move the
1975 * dequeue pointer past the TD.
1976 * The class driver clears the device side halt later.
1977 */
1978 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1979 ep_ring->stream_id, td, EP_HARD_RESET);
1980 } else {
1981 /* Update ring dequeue pointer */
1982 while (ep_ring->dequeue != td->last_trb)
1983 inc_deq(xhci, ep_ring);
1984 inc_deq(xhci, ep_ring);
1985 }
1986
1987 return xhci_td_cleanup(xhci, td, ep_ring, status);
1988}
1989
1990/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
1991static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1992 union xhci_trb *stop_trb)
1993{
1994 u32 sum;
1995 union xhci_trb *trb = ring->dequeue;
1996 struct xhci_segment *seg = ring->deq_seg;
1997
1998 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
1999 if (!trb_is_noop(trb) && !trb_is_link(trb))
2000 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2001 }
2002 return sum;
2003}
2004
2005/*
2006 * Process control tds, update urb status and actual_length.
2007 */
2008static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2009 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2010 struct xhci_virt_ep *ep, int *status)
2011{
2012 struct xhci_virt_device *xdev;
2013 unsigned int slot_id;
2014 int ep_index;
2015 struct xhci_ep_ctx *ep_ctx;
2016 u32 trb_comp_code;
2017 u32 remaining, requested;
2018 u32 trb_type;
2019
2020 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2021 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2022 xdev = xhci->devs[slot_id];
2023 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2024 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2025 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2026 requested = td->urb->transfer_buffer_length;
2027 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2028
2029 switch (trb_comp_code) {
2030 case COMP_SUCCESS:
2031 if (trb_type != TRB_STATUS) {
2032 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2033 (trb_type == TRB_DATA) ? "data" : "setup");
2034 *status = -ESHUTDOWN;
2035 break;
2036 }
2037 *status = 0;
2038 break;
2039 case COMP_SHORT_PACKET:
2040 *status = 0;
2041 break;
2042 case COMP_STOPPED_SHORT_PACKET:
2043 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2044 td->urb->actual_length = remaining;
2045 else
2046 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2047 goto finish_td;
2048 case COMP_STOPPED:
2049 switch (trb_type) {
2050 case TRB_SETUP:
2051 td->urb->actual_length = 0;
2052 goto finish_td;
2053 case TRB_DATA:
2054 case TRB_NORMAL:
2055 td->urb->actual_length = requested - remaining;
2056 goto finish_td;
2057 case TRB_STATUS:
2058 td->urb->actual_length = requested;
2059 goto finish_td;
2060 default:
2061 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2062 trb_type);
2063 goto finish_td;
2064 }
2065 case COMP_STOPPED_LENGTH_INVALID:
2066 goto finish_td;
2067 default:
2068 if (!xhci_requires_manual_halt_cleanup(xhci,
2069 ep_ctx, trb_comp_code))
2070 break;
2071 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2072 trb_comp_code, ep_index);
2073 /* else fall through */
2074 case COMP_STALL_ERROR:
2075 /* Did we transfer part of the data (middle) phase? */
2076 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2077 td->urb->actual_length = requested - remaining;
2078 else if (!td->urb_length_set)
2079 td->urb->actual_length = 0;
2080 goto finish_td;
2081 }
2082
2083 /* stopped at setup stage, no data transferred */
2084 if (trb_type == TRB_SETUP)
2085 goto finish_td;
2086
2087 /*
2088 * if on data stage then update the actual_length of the URB and flag it
2089 * as set, so it won't be overwritten in the event for the last TRB.
2090 */
2091 if (trb_type == TRB_DATA ||
2092 trb_type == TRB_NORMAL) {
2093 td->urb_length_set = true;
2094 td->urb->actual_length = requested - remaining;
2095 xhci_dbg(xhci, "Waiting for status stage event\n");
2096 return 0;
2097 }
2098
2099 /* at status stage */
2100 if (!td->urb_length_set)
2101 td->urb->actual_length = requested;
2102
2103finish_td:
2104 return finish_td(xhci, td, event, ep, status);
2105}
2106
2107/*
2108 * Process isochronous tds, update urb packet status and actual_length.
2109 */
2110static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2111 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2112 struct xhci_virt_ep *ep, int *status)
2113{
2114 struct xhci_ring *ep_ring;
2115 struct urb_priv *urb_priv;
2116 int idx;
2117 struct usb_iso_packet_descriptor *frame;
2118 u32 trb_comp_code;
2119 bool sum_trbs_for_length = false;
2120 u32 remaining, requested, ep_trb_len;
2121 int short_framestatus;
2122
2123 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2124 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2125 urb_priv = td->urb->hcpriv;
2126 idx = urb_priv->num_tds_done;
2127 frame = &td->urb->iso_frame_desc[idx];
2128 requested = frame->length;
2129 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2130 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2131 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2132 -EREMOTEIO : 0;
2133
2134 /* handle completion code */
2135 switch (trb_comp_code) {
2136 case COMP_SUCCESS:
2137 if (remaining) {
2138 frame->status = short_framestatus;
2139 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2140 sum_trbs_for_length = true;
2141 break;
2142 }
2143 frame->status = 0;
2144 break;
2145 case COMP_SHORT_PACKET:
2146 frame->status = short_framestatus;
2147 sum_trbs_for_length = true;
2148 break;
2149 case COMP_BANDWIDTH_OVERRUN_ERROR:
2150 frame->status = -ECOMM;
2151 break;
2152 case COMP_ISOCH_BUFFER_OVERRUN:
2153 case COMP_BABBLE_DETECTED_ERROR:
2154 frame->status = -EOVERFLOW;
2155 break;
2156 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2157 case COMP_STALL_ERROR:
2158 frame->status = -EPROTO;
2159 break;
2160 case COMP_USB_TRANSACTION_ERROR:
2161 frame->status = -EPROTO;
2162 if (ep_trb != td->last_trb)
2163 return 0;
2164 break;
2165 case COMP_STOPPED:
2166 sum_trbs_for_length = true;
2167 break;
2168 case COMP_STOPPED_SHORT_PACKET:
2169 /* field normally containing residue now contains tranferred */
2170 frame->status = short_framestatus;
2171 requested = remaining;
2172 break;
2173 case COMP_STOPPED_LENGTH_INVALID:
2174 requested = 0;
2175 remaining = 0;
2176 break;
2177 default:
2178 sum_trbs_for_length = true;
2179 frame->status = -1;
2180 break;
2181 }
2182
2183 if (sum_trbs_for_length)
2184 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2185 ep_trb_len - remaining;
2186 else
2187 frame->actual_length = requested;
2188
2189 td->urb->actual_length += frame->actual_length;
2190
2191 return finish_td(xhci, td, event, ep, status);
2192}
2193
2194static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2195 struct xhci_transfer_event *event,
2196 struct xhci_virt_ep *ep, int *status)
2197{
2198 struct xhci_ring *ep_ring;
2199 struct urb_priv *urb_priv;
2200 struct usb_iso_packet_descriptor *frame;
2201 int idx;
2202
2203 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2204 urb_priv = td->urb->hcpriv;
2205 idx = urb_priv->num_tds_done;
2206 frame = &td->urb->iso_frame_desc[idx];
2207
2208 /* The transfer is partly done. */
2209 frame->status = -EXDEV;
2210
2211 /* calc actual length */
2212 frame->actual_length = 0;
2213
2214 /* Update ring dequeue pointer */
2215 while (ep_ring->dequeue != td->last_trb)
2216 inc_deq(xhci, ep_ring);
2217 inc_deq(xhci, ep_ring);
2218
2219 return xhci_td_cleanup(xhci, td, ep_ring, status);
2220}
2221
2222/*
2223 * Process bulk and interrupt tds, update urb status and actual_length.
2224 */
2225static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2226 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2227 struct xhci_virt_ep *ep, int *status)
2228{
2229 struct xhci_slot_ctx *slot_ctx;
2230 struct xhci_ring *ep_ring;
2231 u32 trb_comp_code;
2232 u32 remaining, requested, ep_trb_len;
2233 unsigned int slot_id;
2234 int ep_index;
2235
2236 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2237 slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[slot_id]->out_ctx);
2238 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2239 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2240 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2241 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2242 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2243 requested = td->urb->transfer_buffer_length;
2244
2245 switch (trb_comp_code) {
2246 case COMP_SUCCESS:
2247 ep_ring->err_count = 0;
2248 /* handle success with untransferred data as short packet */
2249 if (ep_trb != td->last_trb || remaining) {
2250 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2251 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2252 td->urb->ep->desc.bEndpointAddress,
2253 requested, remaining);
2254 }
2255 *status = 0;
2256 break;
2257 case COMP_SHORT_PACKET:
2258 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2259 td->urb->ep->desc.bEndpointAddress,
2260 requested, remaining);
2261 *status = 0;
2262 break;
2263 case COMP_STOPPED_SHORT_PACKET:
2264 td->urb->actual_length = remaining;
2265 goto finish_td;
2266 case COMP_STOPPED_LENGTH_INVALID:
2267 /* stopped on ep trb with invalid length, exclude it */
2268 ep_trb_len = 0;
2269 remaining = 0;
2270 break;
2271 case COMP_USB_TRANSACTION_ERROR:
2272 if ((ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2273 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2274 break;
2275 *status = 0;
2276 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2277 ep_ring->stream_id, td, EP_SOFT_RESET);
2278 return 0;
2279 default:
2280 /* do nothing */
2281 break;
2282 }
2283
2284 if (ep_trb == td->last_trb)
2285 td->urb->actual_length = requested - remaining;
2286 else
2287 td->urb->actual_length =
2288 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2289 ep_trb_len - remaining;
2290finish_td:
2291 if (remaining > requested) {
2292 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2293 remaining);
2294 td->urb->actual_length = 0;
2295 }
2296 return finish_td(xhci, td, event, ep, status);
2297}
2298
2299/*
2300 * If this function returns an error condition, it means it got a Transfer
2301 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2302 * At this point, the host controller is probably hosed and should be reset.
2303 */
2304static int handle_tx_event(struct xhci_hcd *xhci,
2305 struct xhci_transfer_event *event)
2306{
2307 struct xhci_virt_device *xdev;
2308 struct xhci_virt_ep *ep;
2309 struct xhci_ring *ep_ring;
2310 unsigned int slot_id;
2311 int ep_index;
2312 struct xhci_td *td = NULL;
2313 dma_addr_t ep_trb_dma;
2314 struct xhci_segment *ep_seg;
2315 union xhci_trb *ep_trb;
2316 int status = -EINPROGRESS;
2317 struct xhci_ep_ctx *ep_ctx;
2318 struct list_head *tmp;
2319 u32 trb_comp_code;
2320 int td_num = 0;
2321 bool handling_skipped_tds = false;
2322
2323 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2324 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2325 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2326 ep_trb_dma = le64_to_cpu(event->buffer);
2327
2328 xdev = xhci->devs[slot_id];
2329 if (!xdev) {
2330 xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2331 slot_id);
2332 goto err_out;
2333 }
2334
2335 ep = &xdev->eps[ep_index];
2336 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2337 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2338
2339 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2340 xhci_err(xhci,
2341 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2342 slot_id, ep_index);
2343 goto err_out;
2344 }
2345
2346 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2347 if (!ep_ring) {
2348 switch (trb_comp_code) {
2349 case COMP_STALL_ERROR:
2350 case COMP_USB_TRANSACTION_ERROR:
2351 case COMP_INVALID_STREAM_TYPE_ERROR:
2352 case COMP_INVALID_STREAM_ID_ERROR:
2353 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2354 NULL, EP_SOFT_RESET);
2355 goto cleanup;
2356 case COMP_RING_UNDERRUN:
2357 case COMP_RING_OVERRUN:
2358 case COMP_STOPPED_LENGTH_INVALID:
2359 goto cleanup;
2360 default:
2361 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2362 slot_id, ep_index);
2363 goto err_out;
2364 }
2365 }
2366
2367 /* Count current td numbers if ep->skip is set */
2368 if (ep->skip) {
2369 list_for_each(tmp, &ep_ring->td_list)
2370 td_num++;
2371 }
2372
2373 /* Look for common error cases */
2374 switch (trb_comp_code) {
2375 /* Skip codes that require special handling depending on
2376 * transfer type
2377 */
2378 case COMP_SUCCESS:
2379 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2380 break;
2381 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2382 trb_comp_code = COMP_SHORT_PACKET;
2383 else
2384 xhci_warn_ratelimited(xhci,
2385 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2386 slot_id, ep_index);
2387 case COMP_SHORT_PACKET:
2388 break;
2389 /* Completion codes for endpoint stopped state */
2390 case COMP_STOPPED:
2391 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2392 slot_id, ep_index);
2393 break;
2394 case COMP_STOPPED_LENGTH_INVALID:
2395 xhci_dbg(xhci,
2396 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2397 slot_id, ep_index);
2398 break;
2399 case COMP_STOPPED_SHORT_PACKET:
2400 xhci_dbg(xhci,
2401 "Stopped with short packet transfer detected for slot %u ep %u\n",
2402 slot_id, ep_index);
2403 break;
2404 /* Completion codes for endpoint halted state */
2405 case COMP_STALL_ERROR:
2406 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2407 ep_index);
2408 ep->ep_state |= EP_HALTED;
2409 status = -EPIPE;
2410 break;
2411 case COMP_SPLIT_TRANSACTION_ERROR:
2412 case COMP_USB_TRANSACTION_ERROR:
2413 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2414 slot_id, ep_index);
2415 status = -EPROTO;
2416 break;
2417 case COMP_BABBLE_DETECTED_ERROR:
2418 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2419 slot_id, ep_index);
2420 status = -EOVERFLOW;
2421 break;
2422 /* Completion codes for endpoint error state */
2423 case COMP_TRB_ERROR:
2424 xhci_warn(xhci,
2425 "WARN: TRB error for slot %u ep %u on endpoint\n",
2426 slot_id, ep_index);
2427 status = -EILSEQ;
2428 break;
2429 /* completion codes not indicating endpoint state change */
2430 case COMP_DATA_BUFFER_ERROR:
2431 xhci_warn(xhci,
2432 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2433 slot_id, ep_index);
2434 status = -ENOSR;
2435 break;
2436 case COMP_BANDWIDTH_OVERRUN_ERROR:
2437 xhci_warn(xhci,
2438 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2439 slot_id, ep_index);
2440 break;
2441 case COMP_ISOCH_BUFFER_OVERRUN:
2442 xhci_warn(xhci,
2443 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2444 slot_id, ep_index);
2445 break;
2446 case COMP_RING_UNDERRUN:
2447 /*
2448 * When the Isoch ring is empty, the xHC will generate
2449 * a Ring Overrun Event for IN Isoch endpoint or Ring
2450 * Underrun Event for OUT Isoch endpoint.
2451 */
2452 xhci_dbg(xhci, "underrun event on endpoint\n");
2453 if (!list_empty(&ep_ring->td_list))
2454 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2455 "still with TDs queued?\n",
2456 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2457 ep_index);
2458 goto cleanup;
2459 case COMP_RING_OVERRUN:
2460 xhci_dbg(xhci, "overrun event on endpoint\n");
2461 if (!list_empty(&ep_ring->td_list))
2462 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2463 "still with TDs queued?\n",
2464 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2465 ep_index);
2466 goto cleanup;
2467 case COMP_MISSED_SERVICE_ERROR:
2468 /*
2469 * When encounter missed service error, one or more isoc tds
2470 * may be missed by xHC.
2471 * Set skip flag of the ep_ring; Complete the missed tds as
2472 * short transfer when process the ep_ring next time.
2473 */
2474 ep->skip = true;
2475 xhci_dbg(xhci,
2476 "Miss service interval error for slot %u ep %u, set skip flag\n",
2477 slot_id, ep_index);
2478 goto cleanup;
2479 case COMP_NO_PING_RESPONSE_ERROR:
2480 ep->skip = true;
2481 xhci_dbg(xhci,
2482 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2483 slot_id, ep_index);
2484 goto cleanup;
2485
2486 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2487 /* needs disable slot command to recover */
2488 xhci_warn(xhci,
2489 "WARN: detect an incompatible device for slot %u ep %u",
2490 slot_id, ep_index);
2491 status = -EPROTO;
2492 break;
2493 default:
2494 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2495 status = 0;
2496 break;
2497 }
2498 xhci_warn(xhci,
2499 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2500 trb_comp_code, slot_id, ep_index);
2501 goto cleanup;
2502 }
2503
2504 do {
2505 /* This TRB should be in the TD at the head of this ring's
2506 * TD list.
2507 */
2508 if (list_empty(&ep_ring->td_list)) {
2509 /*
2510 * Don't print wanings if it's due to a stopped endpoint
2511 * generating an extra completion event if the device
2512 * was suspended. Or, a event for the last TRB of a
2513 * short TD we already got a short event for.
2514 * The short TD is already removed from the TD list.
2515 */
2516
2517 if (!(trb_comp_code == COMP_STOPPED ||
2518 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2519 ep_ring->last_td_was_short)) {
2520 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2521 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2522 ep_index);
2523 }
2524 if (ep->skip) {
2525 ep->skip = false;
2526 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2527 slot_id, ep_index);
2528 }
2529 goto cleanup;
2530 }
2531
2532 /* We've skipped all the TDs on the ep ring when ep->skip set */
2533 if (ep->skip && td_num == 0) {
2534 ep->skip = false;
2535 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2536 slot_id, ep_index);
2537 goto cleanup;
2538 }
2539
2540 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2541 td_list);
2542 if (ep->skip)
2543 td_num--;
2544
2545 /* Is this a TRB in the currently executing TD? */
2546 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2547 td->last_trb, ep_trb_dma, false);
2548
2549 /*
2550 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2551 * is not in the current TD pointed by ep_ring->dequeue because
2552 * that the hardware dequeue pointer still at the previous TRB
2553 * of the current TD. The previous TRB maybe a Link TD or the
2554 * last TRB of the previous TD. The command completion handle
2555 * will take care the rest.
2556 */
2557 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2558 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2559 goto cleanup;
2560 }
2561
2562 if (!ep_seg) {
2563 if (!ep->skip ||
2564 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2565 /* Some host controllers give a spurious
2566 * successful event after a short transfer.
2567 * Ignore it.
2568 */
2569 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2570 ep_ring->last_td_was_short) {
2571 ep_ring->last_td_was_short = false;
2572 goto cleanup;
2573 }
2574 /* HC is busted, give up! */
2575 xhci_err(xhci,
2576 "ERROR Transfer event TRB DMA ptr not "
2577 "part of current TD ep_index %d "
2578 "comp_code %u\n", ep_index,
2579 trb_comp_code);
2580 trb_in_td(xhci, ep_ring->deq_seg,
2581 ep_ring->dequeue, td->last_trb,
2582 ep_trb_dma, true);
2583 return -ESHUTDOWN;
2584 }
2585
2586 skip_isoc_td(xhci, td, event, ep, &status);
2587 goto cleanup;
2588 }
2589 if (trb_comp_code == COMP_SHORT_PACKET)
2590 ep_ring->last_td_was_short = true;
2591 else
2592 ep_ring->last_td_was_short = false;
2593
2594 if (ep->skip) {
2595 xhci_dbg(xhci,
2596 "Found td. Clear skip flag for slot %u ep %u.\n",
2597 slot_id, ep_index);
2598 ep->skip = false;
2599 }
2600
2601 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2602 sizeof(*ep_trb)];
2603
2604 trace_xhci_handle_transfer(ep_ring,
2605 (struct xhci_generic_trb *) ep_trb);
2606
2607 /*
2608 * No-op TRB could trigger interrupts in a case where
2609 * a URB was killed and a STALL_ERROR happens right
2610 * after the endpoint ring stopped. Reset the halted
2611 * endpoint. Otherwise, the endpoint remains stalled
2612 * indefinitely.
2613 */
2614 if (trb_is_noop(ep_trb)) {
2615 if (trb_comp_code == COMP_STALL_ERROR ||
2616 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2617 trb_comp_code))
2618 xhci_cleanup_halted_endpoint(xhci, slot_id,
2619 ep_index,
2620 ep_ring->stream_id,
2621 td, EP_HARD_RESET);
2622 goto cleanup;
2623 }
2624
2625 /* update the urb's actual_length and give back to the core */
2626 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2627 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2628 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2629 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2630 else
2631 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2632 &status);
2633cleanup:
2634 handling_skipped_tds = ep->skip &&
2635 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2636 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2637
2638 /*
2639 * Do not update event ring dequeue pointer if we're in a loop
2640 * processing missed tds.
2641 */
2642 if (!handling_skipped_tds)
2643 inc_deq(xhci, xhci->event_ring);
2644
2645 /*
2646 * If ep->skip is set, it means there are missed tds on the
2647 * endpoint ring need to take care of.
2648 * Process them as short transfer until reach the td pointed by
2649 * the event.
2650 */
2651 } while (handling_skipped_tds);
2652
2653 return 0;
2654
2655err_out:
2656 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2657 (unsigned long long) xhci_trb_virt_to_dma(
2658 xhci->event_ring->deq_seg,
2659 xhci->event_ring->dequeue),
2660 lower_32_bits(le64_to_cpu(event->buffer)),
2661 upper_32_bits(le64_to_cpu(event->buffer)),
2662 le32_to_cpu(event->transfer_len),
2663 le32_to_cpu(event->flags));
2664 return -ENODEV;
2665}
2666
2667/*
2668 * This function handles all OS-owned events on the event ring. It may drop
2669 * xhci->lock between event processing (e.g. to pass up port status changes).
2670 * Returns >0 for "possibly more events to process" (caller should call again),
2671 * otherwise 0 if done. In future, <0 returns should indicate error code.
2672 */
2673static int xhci_handle_event(struct xhci_hcd *xhci)
2674{
2675 union xhci_trb *event;
2676 int update_ptrs = 1;
2677 int ret;
2678
2679 /* Event ring hasn't been allocated yet. */
2680 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2681 xhci_err(xhci, "ERROR event ring not ready\n");
2682 return -ENOMEM;
2683 }
2684
2685 event = xhci->event_ring->dequeue;
2686 /* Does the HC or OS own the TRB? */
2687 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2688 xhci->event_ring->cycle_state)
2689 return 0;
2690
2691 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2692
2693 /*
2694 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2695 * speculative reads of the event's flags/data below.
2696 */
2697 rmb();
2698 /* FIXME: Handle more event types. */
2699 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2700 case TRB_TYPE(TRB_COMPLETION):
2701 handle_cmd_completion(xhci, &event->event_cmd);
2702 break;
2703 case TRB_TYPE(TRB_PORT_STATUS):
2704 handle_port_status(xhci, event);
2705 update_ptrs = 0;
2706 break;
2707 case TRB_TYPE(TRB_TRANSFER):
2708 ret = handle_tx_event(xhci, &event->trans_event);
2709 if (ret >= 0)
2710 update_ptrs = 0;
2711 break;
2712 case TRB_TYPE(TRB_DEV_NOTE):
2713 handle_device_notification(xhci, event);
2714 break;
2715 default:
2716 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2717 TRB_TYPE(48))
2718 handle_vendor_event(xhci, event);
2719 else
2720 xhci_warn(xhci, "ERROR unknown event type %d\n",
2721 TRB_FIELD_TO_TYPE(
2722 le32_to_cpu(event->event_cmd.flags)));
2723 }
2724 /* Any of the above functions may drop and re-acquire the lock, so check
2725 * to make sure a watchdog timer didn't mark the host as non-responsive.
2726 */
2727 if (xhci->xhc_state & XHCI_STATE_DYING) {
2728 xhci_dbg(xhci, "xHCI host dying, returning from "
2729 "event handler.\n");
2730 return 0;
2731 }
2732
2733 if (update_ptrs)
2734 /* Update SW event ring dequeue pointer */
2735 inc_deq(xhci, xhci->event_ring);
2736
2737 /* Are there more items on the event ring? Caller will call us again to
2738 * check.
2739 */
2740 return 1;
2741}
2742
2743/*
2744 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2745 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2746 * indicators of an event TRB error, but we check the status *first* to be safe.
2747 */
2748irqreturn_t xhci_irq(struct usb_hcd *hcd)
2749{
2750 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2751 union xhci_trb *event_ring_deq;
2752 irqreturn_t ret = IRQ_NONE;
2753 unsigned long flags;
2754 dma_addr_t deq;
2755 u64 temp_64;
2756 u32 status;
2757
2758 spin_lock_irqsave(&xhci->lock, flags);
2759 /* Check if the xHC generated the interrupt, or the irq is shared */
2760 status = readl(&xhci->op_regs->status);
2761 if (status == ~(u32)0) {
2762 xhci_hc_died(xhci);
2763 ret = IRQ_HANDLED;
2764 goto out;
2765 }
2766
2767 if (!(status & STS_EINT))
2768 goto out;
2769
2770 if (status & STS_FATAL) {
2771 xhci_warn(xhci, "WARNING: Host System Error\n");
2772 xhci_halt(xhci);
2773 ret = IRQ_HANDLED;
2774 goto out;
2775 }
2776
2777 /*
2778 * Clear the op reg interrupt status first,
2779 * so we can receive interrupts from other MSI-X interrupters.
2780 * Write 1 to clear the interrupt status.
2781 */
2782 status |= STS_EINT;
2783 writel(status, &xhci->op_regs->status);
2784
2785 if (!hcd->msi_enabled) {
2786 u32 irq_pending;
2787 irq_pending = readl(&xhci->ir_set->irq_pending);
2788 irq_pending |= IMAN_IP;
2789 writel(irq_pending, &xhci->ir_set->irq_pending);
2790 }
2791
2792 if (xhci->xhc_state & XHCI_STATE_DYING ||
2793 xhci->xhc_state & XHCI_STATE_HALTED) {
2794 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2795 "Shouldn't IRQs be disabled?\n");
2796 /* Clear the event handler busy flag (RW1C);
2797 * the event ring should be empty.
2798 */
2799 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2800 xhci_write_64(xhci, temp_64 | ERST_EHB,
2801 &xhci->ir_set->erst_dequeue);
2802 ret = IRQ_HANDLED;
2803 goto out;
2804 }
2805
2806 event_ring_deq = xhci->event_ring->dequeue;
2807 /* FIXME this should be a delayed service routine
2808 * that clears the EHB.
2809 */
2810 while (xhci_handle_event(xhci) > 0) {}
2811
2812 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2813 /* If necessary, update the HW's version of the event ring deq ptr. */
2814 if (event_ring_deq != xhci->event_ring->dequeue) {
2815 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2816 xhci->event_ring->dequeue);
2817 if (deq == 0)
2818 xhci_warn(xhci, "WARN something wrong with SW event "
2819 "ring dequeue ptr.\n");
2820 /* Update HC event ring dequeue pointer */
2821 temp_64 &= ERST_PTR_MASK;
2822 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2823 }
2824
2825 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2826 temp_64 |= ERST_EHB;
2827 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2828 ret = IRQ_HANDLED;
2829
2830out:
2831 spin_unlock_irqrestore(&xhci->lock, flags);
2832
2833 return ret;
2834}
2835
2836irqreturn_t xhci_msi_irq(int irq, void *hcd)
2837{
2838 return xhci_irq(hcd);
2839}
2840
2841/**** Endpoint Ring Operations ****/
2842
2843/*
2844 * Generic function for queueing a TRB on a ring.
2845 * The caller must have checked to make sure there's room on the ring.
2846 *
2847 * @more_trbs_coming: Will you enqueue more TRBs before calling
2848 * prepare_transfer()?
2849 */
2850static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2851 bool more_trbs_coming,
2852 u32 field1, u32 field2, u32 field3, u32 field4)
2853{
2854 struct xhci_generic_trb *trb;
2855
2856 trb = &ring->enqueue->generic;
2857 trb->field[0] = cpu_to_le32(field1);
2858 trb->field[1] = cpu_to_le32(field2);
2859 trb->field[2] = cpu_to_le32(field3);
2860 trb->field[3] = cpu_to_le32(field4);
2861
2862 trace_xhci_queue_trb(ring, trb);
2863
2864 inc_enq(xhci, ring, more_trbs_coming);
2865}
2866
2867/*
2868 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2869 * FIXME allocate segments if the ring is full.
2870 */
2871static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2872 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2873{
2874 unsigned int num_trbs_needed;
2875
2876 /* Make sure the endpoint has been added to xHC schedule */
2877 switch (ep_state) {
2878 case EP_STATE_DISABLED:
2879 /*
2880 * USB core changed config/interfaces without notifying us,
2881 * or hardware is reporting the wrong state.
2882 */
2883 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2884 return -ENOENT;
2885 case EP_STATE_ERROR:
2886 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2887 /* FIXME event handling code for error needs to clear it */
2888 /* XXX not sure if this should be -ENOENT or not */
2889 return -EINVAL;
2890 case EP_STATE_HALTED:
2891 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2892 case EP_STATE_STOPPED:
2893 case EP_STATE_RUNNING:
2894 break;
2895 default:
2896 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2897 /*
2898 * FIXME issue Configure Endpoint command to try to get the HC
2899 * back into a known state.
2900 */
2901 return -EINVAL;
2902 }
2903
2904 while (1) {
2905 if (room_on_ring(xhci, ep_ring, num_trbs))
2906 break;
2907
2908 if (ep_ring == xhci->cmd_ring) {
2909 xhci_err(xhci, "Do not support expand command ring\n");
2910 return -ENOMEM;
2911 }
2912
2913 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2914 "ERROR no room on ep ring, try ring expansion");
2915 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2916 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2917 mem_flags)) {
2918 xhci_err(xhci, "Ring expansion failed\n");
2919 return -ENOMEM;
2920 }
2921 }
2922
2923 while (trb_is_link(ep_ring->enqueue)) {
2924 /* If we're not dealing with 0.95 hardware or isoc rings
2925 * on AMD 0.96 host, clear the chain bit.
2926 */
2927 if (!xhci_link_trb_quirk(xhci) &&
2928 !(ep_ring->type == TYPE_ISOC &&
2929 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2930 ep_ring->enqueue->link.control &=
2931 cpu_to_le32(~TRB_CHAIN);
2932 else
2933 ep_ring->enqueue->link.control |=
2934 cpu_to_le32(TRB_CHAIN);
2935
2936 wmb();
2937 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2938
2939 /* Toggle the cycle bit after the last ring segment. */
2940 if (link_trb_toggles_cycle(ep_ring->enqueue))
2941 ep_ring->cycle_state ^= 1;
2942
2943 ep_ring->enq_seg = ep_ring->enq_seg->next;
2944 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2945 }
2946 return 0;
2947}
2948
2949static int prepare_transfer(struct xhci_hcd *xhci,
2950 struct xhci_virt_device *xdev,
2951 unsigned int ep_index,
2952 unsigned int stream_id,
2953 unsigned int num_trbs,
2954 struct urb *urb,
2955 unsigned int td_index,
2956 gfp_t mem_flags)
2957{
2958 int ret;
2959 struct urb_priv *urb_priv;
2960 struct xhci_td *td;
2961 struct xhci_ring *ep_ring;
2962 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2963
2964 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2965 if (!ep_ring) {
2966 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2967 stream_id);
2968 return -EINVAL;
2969 }
2970
2971 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2972 num_trbs, mem_flags);
2973 if (ret)
2974 return ret;
2975
2976 urb_priv = urb->hcpriv;
2977 td = &urb_priv->td[td_index];
2978
2979 INIT_LIST_HEAD(&td->td_list);
2980 INIT_LIST_HEAD(&td->cancelled_td_list);
2981
2982 if (td_index == 0) {
2983 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2984 if (unlikely(ret))
2985 return ret;
2986 }
2987
2988 td->urb = urb;
2989 /* Add this TD to the tail of the endpoint ring's TD list */
2990 list_add_tail(&td->td_list, &ep_ring->td_list);
2991 td->start_seg = ep_ring->enq_seg;
2992 td->first_trb = ep_ring->enqueue;
2993
2994 return 0;
2995}
2996
2997unsigned int count_trbs(u64 addr, u64 len)
2998{
2999 unsigned int num_trbs;
3000
3001 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3002 TRB_MAX_BUFF_SIZE);
3003 if (num_trbs == 0)
3004 num_trbs++;
3005
3006 return num_trbs;
3007}
3008
3009static inline unsigned int count_trbs_needed(struct urb *urb)
3010{
3011 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3012}
3013
3014static unsigned int count_sg_trbs_needed(struct urb *urb)
3015{
3016 struct scatterlist *sg;
3017 unsigned int i, len, full_len, num_trbs = 0;
3018
3019 full_len = urb->transfer_buffer_length;
3020
3021 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3022 len = sg_dma_len(sg);
3023 num_trbs += count_trbs(sg_dma_address(sg), len);
3024 len = min_t(unsigned int, len, full_len);
3025 full_len -= len;
3026 if (full_len == 0)
3027 break;
3028 }
3029
3030 return num_trbs;
3031}
3032
3033static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3034{
3035 u64 addr, len;
3036
3037 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3038 len = urb->iso_frame_desc[i].length;
3039
3040 return count_trbs(addr, len);
3041}
3042
3043static void check_trb_math(struct urb *urb, int running_total)
3044{
3045 if (unlikely(running_total != urb->transfer_buffer_length))
3046 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3047 "queued %#x (%d), asked for %#x (%d)\n",
3048 __func__,
3049 urb->ep->desc.bEndpointAddress,
3050 running_total, running_total,
3051 urb->transfer_buffer_length,
3052 urb->transfer_buffer_length);
3053}
3054
3055static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3056 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3057 struct xhci_generic_trb *start_trb)
3058{
3059 /*
3060 * Pass all the TRBs to the hardware at once and make sure this write
3061 * isn't reordered.
3062 */
3063 wmb();
3064 if (start_cycle)
3065 start_trb->field[3] |= cpu_to_le32(start_cycle);
3066 else
3067 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3068 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3069}
3070
3071static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3072 struct xhci_ep_ctx *ep_ctx)
3073{
3074 int xhci_interval;
3075 int ep_interval;
3076
3077 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3078 ep_interval = urb->interval;
3079
3080 /* Convert to microframes */
3081 if (urb->dev->speed == USB_SPEED_LOW ||
3082 urb->dev->speed == USB_SPEED_FULL)
3083 ep_interval *= 8;
3084
3085 /* FIXME change this to a warning and a suggestion to use the new API
3086 * to set the polling interval (once the API is added).
3087 */
3088 if (xhci_interval != ep_interval) {
3089 dev_dbg_ratelimited(&urb->dev->dev,
3090 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3091 ep_interval, ep_interval == 1 ? "" : "s",
3092 xhci_interval, xhci_interval == 1 ? "" : "s");
3093 urb->interval = xhci_interval;
3094 /* Convert back to frames for LS/FS devices */
3095 if (urb->dev->speed == USB_SPEED_LOW ||
3096 urb->dev->speed == USB_SPEED_FULL)
3097 urb->interval /= 8;
3098 }
3099}
3100
3101/*
3102 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3103 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3104 * (comprised of sg list entries) can take several service intervals to
3105 * transmit.
3106 */
3107int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3108 struct urb *urb, int slot_id, unsigned int ep_index)
3109{
3110 struct xhci_ep_ctx *ep_ctx;
3111
3112 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3113 check_interval(xhci, urb, ep_ctx);
3114
3115 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3116}
3117
3118/*
3119 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3120 * packets remaining in the TD (*not* including this TRB).
3121 *
3122 * Total TD packet count = total_packet_count =
3123 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3124 *
3125 * Packets transferred up to and including this TRB = packets_transferred =
3126 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3127 *
3128 * TD size = total_packet_count - packets_transferred
3129 *
3130 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3131 * including this TRB, right shifted by 10
3132 *
3133 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3134 * This is taken care of in the TRB_TD_SIZE() macro
3135 *
3136 * The last TRB in a TD must have the TD size set to zero.
3137 */
3138static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3139 int trb_buff_len, unsigned int td_total_len,
3140 struct urb *urb, bool more_trbs_coming)
3141{
3142 u32 maxp, total_packet_count;
3143
3144 /* MTK xHCI 0.96 contains some features from 1.0 */
3145 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3146 return ((td_total_len - transferred) >> 10);
3147
3148 /* One TRB with a zero-length data packet. */
3149 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3150 trb_buff_len == td_total_len)
3151 return 0;
3152
3153 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3154 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3155 trb_buff_len = 0;
3156
3157 maxp = usb_endpoint_maxp(&urb->ep->desc);
3158 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3159
3160 /* Queueing functions don't count the current TRB into transferred */
3161 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3162}
3163
3164
3165static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3166 u32 *trb_buff_len, struct xhci_segment *seg)
3167{
3168 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3169 unsigned int unalign;
3170 unsigned int max_pkt;
3171 u32 new_buff_len;
3172 size_t len;
3173
3174 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3175 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3176
3177 /* we got lucky, last normal TRB data on segment is packet aligned */
3178 if (unalign == 0)
3179 return 0;
3180
3181 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3182 unalign, *trb_buff_len);
3183
3184 /* is the last nornal TRB alignable by splitting it */
3185 if (*trb_buff_len > unalign) {
3186 *trb_buff_len -= unalign;
3187 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3188 return 0;
3189 }
3190
3191 /*
3192 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3193 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3194 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3195 */
3196 new_buff_len = max_pkt - (enqd_len % max_pkt);
3197
3198 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3199 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3200
3201 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3202 if (usb_urb_dir_out(urb)) {
3203 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3204 seg->bounce_buf, new_buff_len, enqd_len);
3205 if (len != new_buff_len)
3206 xhci_warn(xhci,
3207 "WARN Wrong bounce buffer write length: %zu != %d\n",
3208 len, new_buff_len);
3209 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3210 max_pkt, DMA_TO_DEVICE);
3211 } else {
3212 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3213 max_pkt, DMA_FROM_DEVICE);
3214 }
3215
3216 if (dma_mapping_error(dev, seg->bounce_dma)) {
3217 /* try without aligning. Some host controllers survive */
3218 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3219 return 0;
3220 }
3221 *trb_buff_len = new_buff_len;
3222 seg->bounce_len = new_buff_len;
3223 seg->bounce_offs = enqd_len;
3224
3225 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3226
3227 return 1;
3228}
3229
3230/* This is very similar to what ehci-q.c qtd_fill() does */
3231int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3232 struct urb *urb, int slot_id, unsigned int ep_index)
3233{
3234 struct xhci_ring *ring;
3235 struct urb_priv *urb_priv;
3236 struct xhci_td *td;
3237 struct xhci_generic_trb *start_trb;
3238 struct scatterlist *sg = NULL;
3239 bool more_trbs_coming = true;
3240 bool need_zero_pkt = false;
3241 bool first_trb = true;
3242 unsigned int num_trbs;
3243 unsigned int start_cycle, num_sgs = 0;
3244 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3245 int sent_len, ret;
3246 u32 field, length_field, remainder;
3247 u64 addr, send_addr;
3248
3249 ring = xhci_urb_to_transfer_ring(xhci, urb);
3250 if (!ring)
3251 return -EINVAL;
3252
3253 full_len = urb->transfer_buffer_length;
3254 /* If we have scatter/gather list, we use it. */
3255 if (urb->num_sgs) {
3256 num_sgs = urb->num_mapped_sgs;
3257 sg = urb->sg;
3258 addr = (u64) sg_dma_address(sg);
3259 block_len = sg_dma_len(sg);
3260 num_trbs = count_sg_trbs_needed(urb);
3261 } else {
3262 num_trbs = count_trbs_needed(urb);
3263 addr = (u64) urb->transfer_dma;
3264 block_len = full_len;
3265 }
3266 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3267 ep_index, urb->stream_id,
3268 num_trbs, urb, 0, mem_flags);
3269 if (unlikely(ret < 0))
3270 return ret;
3271
3272 urb_priv = urb->hcpriv;
3273
3274 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3275 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3276 need_zero_pkt = true;
3277
3278 td = &urb_priv->td[0];
3279
3280 /*
3281 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3282 * until we've finished creating all the other TRBs. The ring's cycle
3283 * state may change as we enqueue the other TRBs, so save it too.
3284 */
3285 start_trb = &ring->enqueue->generic;
3286 start_cycle = ring->cycle_state;
3287 send_addr = addr;
3288
3289 /* Queue the TRBs, even if they are zero-length */
3290 for (enqd_len = 0; first_trb || enqd_len < full_len;
3291 enqd_len += trb_buff_len) {
3292 field = TRB_TYPE(TRB_NORMAL);
3293
3294 /* TRB buffer should not cross 64KB boundaries */
3295 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3296 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3297
3298 if (enqd_len + trb_buff_len > full_len)
3299 trb_buff_len = full_len - enqd_len;
3300
3301 /* Don't change the cycle bit of the first TRB until later */
3302 if (first_trb) {
3303 first_trb = false;
3304 if (start_cycle == 0)
3305 field |= TRB_CYCLE;
3306 } else
3307 field |= ring->cycle_state;
3308
3309 /* Chain all the TRBs together; clear the chain bit in the last
3310 * TRB to indicate it's the last TRB in the chain.
3311 */
3312 if (enqd_len + trb_buff_len < full_len) {
3313 field |= TRB_CHAIN;
3314 if (trb_is_link(ring->enqueue + 1)) {
3315 if (xhci_align_td(xhci, urb, enqd_len,
3316 &trb_buff_len,
3317 ring->enq_seg)) {
3318 send_addr = ring->enq_seg->bounce_dma;
3319 /* assuming TD won't span 2 segs */
3320 td->bounce_seg = ring->enq_seg;
3321 }
3322 }
3323 }
3324 if (enqd_len + trb_buff_len >= full_len) {
3325 field &= ~TRB_CHAIN;
3326 field |= TRB_IOC;
3327 more_trbs_coming = false;
3328 td->last_trb = ring->enqueue;
3329
3330 if (xhci_urb_suitable_for_idt(urb)) {
3331 memcpy(&send_addr, urb->transfer_buffer,
3332 trb_buff_len);
3333 le64_to_cpus(&send_addr);
3334 field |= TRB_IDT;
3335 }
3336 }
3337
3338 /* Only set interrupt on short packet for IN endpoints */
3339 if (usb_urb_dir_in(urb))
3340 field |= TRB_ISP;
3341
3342 /* Set the TRB length, TD size, and interrupter fields. */
3343 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3344 full_len, urb, more_trbs_coming);
3345
3346 length_field = TRB_LEN(trb_buff_len) |
3347 TRB_TD_SIZE(remainder) |
3348 TRB_INTR_TARGET(0);
3349
3350 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3351 lower_32_bits(send_addr),
3352 upper_32_bits(send_addr),
3353 length_field,
3354 field);
3355
3356 addr += trb_buff_len;
3357 sent_len = trb_buff_len;
3358
3359 while (sg && sent_len >= block_len) {
3360 /* New sg entry */
3361 --num_sgs;
3362 sent_len -= block_len;
3363 if (num_sgs != 0) {
3364 sg = sg_next(sg);
3365 block_len = sg_dma_len(sg);
3366 addr = (u64) sg_dma_address(sg);
3367 addr += sent_len;
3368 }
3369 }
3370 block_len -= sent_len;
3371 send_addr = addr;
3372 }
3373
3374 if (need_zero_pkt) {
3375 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3376 ep_index, urb->stream_id,
3377 1, urb, 1, mem_flags);
3378 urb_priv->td[1].last_trb = ring->enqueue;
3379 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3380 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3381 }
3382
3383 check_trb_math(urb, enqd_len);
3384 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3385 start_cycle, start_trb);
3386 return 0;
3387}
3388
3389/* Caller must have locked xhci->lock */
3390int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3391 struct urb *urb, int slot_id, unsigned int ep_index)
3392{
3393 struct xhci_ring *ep_ring;
3394 int num_trbs;
3395 int ret;
3396 struct usb_ctrlrequest *setup;
3397 struct xhci_generic_trb *start_trb;
3398 int start_cycle;
3399 u32 field;
3400 struct urb_priv *urb_priv;
3401 struct xhci_td *td;
3402
3403 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3404 if (!ep_ring)
3405 return -EINVAL;
3406
3407 /*
3408 * Need to copy setup packet into setup TRB, so we can't use the setup
3409 * DMA address.
3410 */
3411 if (!urb->setup_packet)
3412 return -EINVAL;
3413
3414 /* 1 TRB for setup, 1 for status */
3415 num_trbs = 2;
3416 /*
3417 * Don't need to check if we need additional event data and normal TRBs,
3418 * since data in control transfers will never get bigger than 16MB
3419 * XXX: can we get a buffer that crosses 64KB boundaries?
3420 */
3421 if (urb->transfer_buffer_length > 0)
3422 num_trbs++;
3423 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3424 ep_index, urb->stream_id,
3425 num_trbs, urb, 0, mem_flags);
3426 if (ret < 0)
3427 return ret;
3428
3429 urb_priv = urb->hcpriv;
3430 td = &urb_priv->td[0];
3431
3432 /*
3433 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3434 * until we've finished creating all the other TRBs. The ring's cycle
3435 * state may change as we enqueue the other TRBs, so save it too.
3436 */
3437 start_trb = &ep_ring->enqueue->generic;
3438 start_cycle = ep_ring->cycle_state;
3439
3440 /* Queue setup TRB - see section 6.4.1.2.1 */
3441 /* FIXME better way to translate setup_packet into two u32 fields? */
3442 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3443 field = 0;
3444 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3445 if (start_cycle == 0)
3446 field |= 0x1;
3447
3448 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3449 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3450 if (urb->transfer_buffer_length > 0) {
3451 if (setup->bRequestType & USB_DIR_IN)
3452 field |= TRB_TX_TYPE(TRB_DATA_IN);
3453 else
3454 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3455 }
3456 }
3457
3458 queue_trb(xhci, ep_ring, true,
3459 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3460 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3461 TRB_LEN(8) | TRB_INTR_TARGET(0),
3462 /* Immediate data in pointer */
3463 field);
3464
3465 /* If there's data, queue data TRBs */
3466 /* Only set interrupt on short packet for IN endpoints */
3467 if (usb_urb_dir_in(urb))
3468 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3469 else
3470 field = TRB_TYPE(TRB_DATA);
3471
3472 if (urb->transfer_buffer_length > 0) {
3473 u32 length_field, remainder;
3474 u64 addr;
3475
3476 if (xhci_urb_suitable_for_idt(urb)) {
3477 memcpy(&addr, urb->transfer_buffer,
3478 urb->transfer_buffer_length);
3479 le64_to_cpus(&addr);
3480 field |= TRB_IDT;
3481 } else {
3482 addr = (u64) urb->transfer_dma;
3483 }
3484
3485 remainder = xhci_td_remainder(xhci, 0,
3486 urb->transfer_buffer_length,
3487 urb->transfer_buffer_length,
3488 urb, 1);
3489 length_field = TRB_LEN(urb->transfer_buffer_length) |
3490 TRB_TD_SIZE(remainder) |
3491 TRB_INTR_TARGET(0);
3492 if (setup->bRequestType & USB_DIR_IN)
3493 field |= TRB_DIR_IN;
3494 queue_trb(xhci, ep_ring, true,
3495 lower_32_bits(addr),
3496 upper_32_bits(addr),
3497 length_field,
3498 field | ep_ring->cycle_state);
3499 }
3500
3501 /* Save the DMA address of the last TRB in the TD */
3502 td->last_trb = ep_ring->enqueue;
3503
3504 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3505 /* If the device sent data, the status stage is an OUT transfer */
3506 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3507 field = 0;
3508 else
3509 field = TRB_DIR_IN;
3510 queue_trb(xhci, ep_ring, false,
3511 0,
3512 0,
3513 TRB_INTR_TARGET(0),
3514 /* Event on completion */
3515 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3516
3517 giveback_first_trb(xhci, slot_id, ep_index, 0,
3518 start_cycle, start_trb);
3519 return 0;
3520}
3521
3522/*
3523 * The transfer burst count field of the isochronous TRB defines the number of
3524 * bursts that are required to move all packets in this TD. Only SuperSpeed
3525 * devices can burst up to bMaxBurst number of packets per service interval.
3526 * This field is zero based, meaning a value of zero in the field means one
3527 * burst. Basically, for everything but SuperSpeed devices, this field will be
3528 * zero. Only xHCI 1.0 host controllers support this field.
3529 */
3530static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3531 struct urb *urb, unsigned int total_packet_count)
3532{
3533 unsigned int max_burst;
3534
3535 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3536 return 0;
3537
3538 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3539 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3540}
3541
3542/*
3543 * Returns the number of packets in the last "burst" of packets. This field is
3544 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3545 * the last burst packet count is equal to the total number of packets in the
3546 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3547 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3548 * contain 1 to (bMaxBurst + 1) packets.
3549 */
3550static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3551 struct urb *urb, unsigned int total_packet_count)
3552{
3553 unsigned int max_burst;
3554 unsigned int residue;
3555
3556 if (xhci->hci_version < 0x100)
3557 return 0;
3558
3559 if (urb->dev->speed >= USB_SPEED_SUPER) {
3560 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3561 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3562 residue = total_packet_count % (max_burst + 1);
3563 /* If residue is zero, the last burst contains (max_burst + 1)
3564 * number of packets, but the TLBPC field is zero-based.
3565 */
3566 if (residue == 0)
3567 return max_burst;
3568 return residue - 1;
3569 }
3570 if (total_packet_count == 0)
3571 return 0;
3572 return total_packet_count - 1;
3573}
3574
3575/*
3576 * Calculates Frame ID field of the isochronous TRB identifies the
3577 * target frame that the Interval associated with this Isochronous
3578 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3579 *
3580 * Returns actual frame id on success, negative value on error.
3581 */
3582static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3583 struct urb *urb, int index)
3584{
3585 int start_frame, ist, ret = 0;
3586 int start_frame_id, end_frame_id, current_frame_id;
3587
3588 if (urb->dev->speed == USB_SPEED_LOW ||
3589 urb->dev->speed == USB_SPEED_FULL)
3590 start_frame = urb->start_frame + index * urb->interval;
3591 else
3592 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3593
3594 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3595 *
3596 * If bit [3] of IST is cleared to '0', software can add a TRB no
3597 * later than IST[2:0] Microframes before that TRB is scheduled to
3598 * be executed.
3599 * If bit [3] of IST is set to '1', software can add a TRB no later
3600 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3601 */
3602 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3603 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3604 ist <<= 3;
3605
3606 /* Software shall not schedule an Isoch TD with a Frame ID value that
3607 * is less than the Start Frame ID or greater than the End Frame ID,
3608 * where:
3609 *
3610 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3611 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3612 *
3613 * Both the End Frame ID and Start Frame ID values are calculated
3614 * in microframes. When software determines the valid Frame ID value;
3615 * The End Frame ID value should be rounded down to the nearest Frame
3616 * boundary, and the Start Frame ID value should be rounded up to the
3617 * nearest Frame boundary.
3618 */
3619 current_frame_id = readl(&xhci->run_regs->microframe_index);
3620 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3621 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3622
3623 start_frame &= 0x7ff;
3624 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3625 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3626
3627 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3628 __func__, index, readl(&xhci->run_regs->microframe_index),
3629 start_frame_id, end_frame_id, start_frame);
3630
3631 if (start_frame_id < end_frame_id) {
3632 if (start_frame > end_frame_id ||
3633 start_frame < start_frame_id)
3634 ret = -EINVAL;
3635 } else if (start_frame_id > end_frame_id) {
3636 if ((start_frame > end_frame_id &&
3637 start_frame < start_frame_id))
3638 ret = -EINVAL;
3639 } else {
3640 ret = -EINVAL;
3641 }
3642
3643 if (index == 0) {
3644 if (ret == -EINVAL || start_frame == start_frame_id) {
3645 start_frame = start_frame_id + 1;
3646 if (urb->dev->speed == USB_SPEED_LOW ||
3647 urb->dev->speed == USB_SPEED_FULL)
3648 urb->start_frame = start_frame;
3649 else
3650 urb->start_frame = start_frame << 3;
3651 ret = 0;
3652 }
3653 }
3654
3655 if (ret) {
3656 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3657 start_frame, current_frame_id, index,
3658 start_frame_id, end_frame_id);
3659 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3660 return ret;
3661 }
3662
3663 return start_frame;
3664}
3665
3666/* This is for isoc transfer */
3667static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3668 struct urb *urb, int slot_id, unsigned int ep_index)
3669{
3670 struct xhci_ring *ep_ring;
3671 struct urb_priv *urb_priv;
3672 struct xhci_td *td;
3673 int num_tds, trbs_per_td;
3674 struct xhci_generic_trb *start_trb;
3675 bool first_trb;
3676 int start_cycle;
3677 u32 field, length_field;
3678 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3679 u64 start_addr, addr;
3680 int i, j;
3681 bool more_trbs_coming;
3682 struct xhci_virt_ep *xep;
3683 int frame_id;
3684
3685 xep = &xhci->devs[slot_id]->eps[ep_index];
3686 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3687
3688 num_tds = urb->number_of_packets;
3689 if (num_tds < 1) {
3690 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3691 return -EINVAL;
3692 }
3693 start_addr = (u64) urb->transfer_dma;
3694 start_trb = &ep_ring->enqueue->generic;
3695 start_cycle = ep_ring->cycle_state;
3696
3697 urb_priv = urb->hcpriv;
3698 /* Queue the TRBs for each TD, even if they are zero-length */
3699 for (i = 0; i < num_tds; i++) {
3700 unsigned int total_pkt_count, max_pkt;
3701 unsigned int burst_count, last_burst_pkt_count;
3702 u32 sia_frame_id;
3703
3704 first_trb = true;
3705 running_total = 0;
3706 addr = start_addr + urb->iso_frame_desc[i].offset;
3707 td_len = urb->iso_frame_desc[i].length;
3708 td_remain_len = td_len;
3709 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3710 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3711
3712 /* A zero-length transfer still involves at least one packet. */
3713 if (total_pkt_count == 0)
3714 total_pkt_count++;
3715 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3716 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3717 urb, total_pkt_count);
3718
3719 trbs_per_td = count_isoc_trbs_needed(urb, i);
3720
3721 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3722 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3723 if (ret < 0) {
3724 if (i == 0)
3725 return ret;
3726 goto cleanup;
3727 }
3728 td = &urb_priv->td[i];
3729
3730 /* use SIA as default, if frame id is used overwrite it */
3731 sia_frame_id = TRB_SIA;
3732 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3733 HCC_CFC(xhci->hcc_params)) {
3734 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3735 if (frame_id >= 0)
3736 sia_frame_id = TRB_FRAME_ID(frame_id);
3737 }
3738 /*
3739 * Set isoc specific data for the first TRB in a TD.
3740 * Prevent HW from getting the TRBs by keeping the cycle state
3741 * inverted in the first TDs isoc TRB.
3742 */
3743 field = TRB_TYPE(TRB_ISOC) |
3744 TRB_TLBPC(last_burst_pkt_count) |
3745 sia_frame_id |
3746 (i ? ep_ring->cycle_state : !start_cycle);
3747
3748 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3749 if (!xep->use_extended_tbc)
3750 field |= TRB_TBC(burst_count);
3751
3752 /* fill the rest of the TRB fields, and remaining normal TRBs */
3753 for (j = 0; j < trbs_per_td; j++) {
3754 u32 remainder = 0;
3755
3756 /* only first TRB is isoc, overwrite otherwise */
3757 if (!first_trb)
3758 field = TRB_TYPE(TRB_NORMAL) |
3759 ep_ring->cycle_state;
3760
3761 /* Only set interrupt on short packet for IN EPs */
3762 if (usb_urb_dir_in(urb))
3763 field |= TRB_ISP;
3764
3765 /* Set the chain bit for all except the last TRB */
3766 if (j < trbs_per_td - 1) {
3767 more_trbs_coming = true;
3768 field |= TRB_CHAIN;
3769 } else {
3770 more_trbs_coming = false;
3771 td->last_trb = ep_ring->enqueue;
3772 field |= TRB_IOC;
3773 /* set BEI, except for the last TD */
3774 if (xhci->hci_version >= 0x100 &&
3775 !(xhci->quirks & XHCI_AVOID_BEI) &&
3776 i < num_tds - 1)
3777 field |= TRB_BEI;
3778 }
3779 /* Calculate TRB length */
3780 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3781 if (trb_buff_len > td_remain_len)
3782 trb_buff_len = td_remain_len;
3783
3784 /* Set the TRB length, TD size, & interrupter fields. */
3785 remainder = xhci_td_remainder(xhci, running_total,
3786 trb_buff_len, td_len,
3787 urb, more_trbs_coming);
3788
3789 length_field = TRB_LEN(trb_buff_len) |
3790 TRB_INTR_TARGET(0);
3791
3792 /* xhci 1.1 with ETE uses TD Size field for TBC */
3793 if (first_trb && xep->use_extended_tbc)
3794 length_field |= TRB_TD_SIZE_TBC(burst_count);
3795 else
3796 length_field |= TRB_TD_SIZE(remainder);
3797 first_trb = false;
3798
3799 queue_trb(xhci, ep_ring, more_trbs_coming,
3800 lower_32_bits(addr),
3801 upper_32_bits(addr),
3802 length_field,
3803 field);
3804 running_total += trb_buff_len;
3805
3806 addr += trb_buff_len;
3807 td_remain_len -= trb_buff_len;
3808 }
3809
3810 /* Check TD length */
3811 if (running_total != td_len) {
3812 xhci_err(xhci, "ISOC TD length unmatch\n");
3813 ret = -EINVAL;
3814 goto cleanup;
3815 }
3816 }
3817
3818 /* store the next frame id */
3819 if (HCC_CFC(xhci->hcc_params))
3820 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3821
3822 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3823 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3824 usb_amd_quirk_pll_disable();
3825 }
3826 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3827
3828 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3829 start_cycle, start_trb);
3830 return 0;
3831cleanup:
3832 /* Clean up a partially enqueued isoc transfer. */
3833
3834 for (i--; i >= 0; i--)
3835 list_del_init(&urb_priv->td[i].td_list);
3836
3837 /* Use the first TD as a temporary variable to turn the TDs we've queued
3838 * into No-ops with a software-owned cycle bit. That way the hardware
3839 * won't accidentally start executing bogus TDs when we partially
3840 * overwrite them. td->first_trb and td->start_seg are already set.
3841 */
3842 urb_priv->td[0].last_trb = ep_ring->enqueue;
3843 /* Every TRB except the first & last will have its cycle bit flipped. */
3844 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3845
3846 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3847 ep_ring->enqueue = urb_priv->td[0].first_trb;
3848 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3849 ep_ring->cycle_state = start_cycle;
3850 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3851 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3852 return ret;
3853}
3854
3855/*
3856 * Check transfer ring to guarantee there is enough room for the urb.
3857 * Update ISO URB start_frame and interval.
3858 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3859 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3860 * Contiguous Frame ID is not supported by HC.
3861 */
3862int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3863 struct urb *urb, int slot_id, unsigned int ep_index)
3864{
3865 struct xhci_virt_device *xdev;
3866 struct xhci_ring *ep_ring;
3867 struct xhci_ep_ctx *ep_ctx;
3868 int start_frame;
3869 int num_tds, num_trbs, i;
3870 int ret;
3871 struct xhci_virt_ep *xep;
3872 int ist;
3873
3874 xdev = xhci->devs[slot_id];
3875 xep = &xhci->devs[slot_id]->eps[ep_index];
3876 ep_ring = xdev->eps[ep_index].ring;
3877 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3878
3879 num_trbs = 0;
3880 num_tds = urb->number_of_packets;
3881 for (i = 0; i < num_tds; i++)
3882 num_trbs += count_isoc_trbs_needed(urb, i);
3883
3884 /* Check the ring to guarantee there is enough room for the whole urb.
3885 * Do not insert any td of the urb to the ring if the check failed.
3886 */
3887 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3888 num_trbs, mem_flags);
3889 if (ret)
3890 return ret;
3891
3892 /*
3893 * Check interval value. This should be done before we start to
3894 * calculate the start frame value.
3895 */
3896 check_interval(xhci, urb, ep_ctx);
3897
3898 /* Calculate the start frame and put it in urb->start_frame. */
3899 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3900 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3901 urb->start_frame = xep->next_frame_id;
3902 goto skip_start_over;
3903 }
3904 }
3905
3906 start_frame = readl(&xhci->run_regs->microframe_index);
3907 start_frame &= 0x3fff;
3908 /*
3909 * Round up to the next frame and consider the time before trb really
3910 * gets scheduled by hardare.
3911 */
3912 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3913 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3914 ist <<= 3;
3915 start_frame += ist + XHCI_CFC_DELAY;
3916 start_frame = roundup(start_frame, 8);
3917
3918 /*
3919 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3920 * is greate than 8 microframes.
3921 */
3922 if (urb->dev->speed == USB_SPEED_LOW ||
3923 urb->dev->speed == USB_SPEED_FULL) {
3924 start_frame = roundup(start_frame, urb->interval << 3);
3925 urb->start_frame = start_frame >> 3;
3926 } else {
3927 start_frame = roundup(start_frame, urb->interval);
3928 urb->start_frame = start_frame;
3929 }
3930
3931skip_start_over:
3932 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3933
3934 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3935}
3936
3937/**** Command Ring Operations ****/
3938
3939/* Generic function for queueing a command TRB on the command ring.
3940 * Check to make sure there's room on the command ring for one command TRB.
3941 * Also check that there's room reserved for commands that must not fail.
3942 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3943 * then only check for the number of reserved spots.
3944 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3945 * because the command event handler may want to resubmit a failed command.
3946 */
3947static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3948 u32 field1, u32 field2,
3949 u32 field3, u32 field4, bool command_must_succeed)
3950{
3951 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3952 int ret;
3953
3954 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3955 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3956 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3957 return -ESHUTDOWN;
3958 }
3959
3960 if (!command_must_succeed)
3961 reserved_trbs++;
3962
3963 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3964 reserved_trbs, GFP_ATOMIC);
3965 if (ret < 0) {
3966 xhci_err(xhci, "ERR: No room for command on command ring\n");
3967 if (command_must_succeed)
3968 xhci_err(xhci, "ERR: Reserved TRB counting for "
3969 "unfailable commands failed.\n");
3970 return ret;
3971 }
3972
3973 cmd->command_trb = xhci->cmd_ring->enqueue;
3974
3975 /* if there are no other commands queued we start the timeout timer */
3976 if (list_empty(&xhci->cmd_list)) {
3977 xhci->current_cmd = cmd;
3978 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3979 }
3980
3981 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3982
3983 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3984 field4 | xhci->cmd_ring->cycle_state);
3985 return 0;
3986}
3987
3988/* Queue a slot enable or disable request on the command ring */
3989int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3990 u32 trb_type, u32 slot_id)
3991{
3992 return queue_command(xhci, cmd, 0, 0, 0,
3993 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3994}
3995
3996/* Queue an address device command TRB */
3997int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3998 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3999{
4000 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4001 upper_32_bits(in_ctx_ptr), 0,
4002 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4003 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4004}
4005
4006int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4007 u32 field1, u32 field2, u32 field3, u32 field4)
4008{
4009 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4010}
4011
4012/* Queue a reset device command TRB */
4013int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4014 u32 slot_id)
4015{
4016 return queue_command(xhci, cmd, 0, 0, 0,
4017 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4018 false);
4019}
4020
4021/* Queue a configure endpoint command TRB */
4022int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4023 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4024 u32 slot_id, bool command_must_succeed)
4025{
4026 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4027 upper_32_bits(in_ctx_ptr), 0,
4028 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4029 command_must_succeed);
4030}
4031
4032/* Queue an evaluate context command TRB */
4033int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4034 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4035{
4036 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4037 upper_32_bits(in_ctx_ptr), 0,
4038 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4039 command_must_succeed);
4040}
4041
4042/*
4043 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4044 * activity on an endpoint that is about to be suspended.
4045 */
4046int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4047 int slot_id, unsigned int ep_index, int suspend)
4048{
4049 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4050 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4051 u32 type = TRB_TYPE(TRB_STOP_RING);
4052 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4053
4054 return queue_command(xhci, cmd, 0, 0, 0,
4055 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4056}
4057
4058/* Set Transfer Ring Dequeue Pointer command */
4059void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4060 unsigned int slot_id, unsigned int ep_index,
4061 struct xhci_dequeue_state *deq_state)
4062{
4063 dma_addr_t addr;
4064 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4065 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4066 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4067 u32 trb_sct = 0;
4068 u32 type = TRB_TYPE(TRB_SET_DEQ);
4069 struct xhci_virt_ep *ep;
4070 struct xhci_command *cmd;
4071 int ret;
4072
4073 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4074 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4075 deq_state->new_deq_seg,
4076 (unsigned long long)deq_state->new_deq_seg->dma,
4077 deq_state->new_deq_ptr,
4078 (unsigned long long)xhci_trb_virt_to_dma(
4079 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4080 deq_state->new_cycle_state);
4081
4082 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4083 deq_state->new_deq_ptr);
4084 if (addr == 0) {
4085 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4086 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4087 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4088 return;
4089 }
4090 ep = &xhci->devs[slot_id]->eps[ep_index];
4091 if ((ep->ep_state & SET_DEQ_PENDING)) {
4092 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4093 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4094 return;
4095 }
4096
4097 /* This function gets called from contexts where it cannot sleep */
4098 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4099 if (!cmd)
4100 return;
4101
4102 ep->queued_deq_seg = deq_state->new_deq_seg;
4103 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4104 if (deq_state->stream_id)
4105 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4106 ret = queue_command(xhci, cmd,
4107 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4108 upper_32_bits(addr), trb_stream_id,
4109 trb_slot_id | trb_ep_index | type, false);
4110 if (ret < 0) {
4111 xhci_free_command(xhci, cmd);
4112 return;
4113 }
4114
4115 /* Stop the TD queueing code from ringing the doorbell until
4116 * this command completes. The HC won't set the dequeue pointer
4117 * if the ring is running, and ringing the doorbell starts the
4118 * ring running.
4119 */
4120 ep->ep_state |= SET_DEQ_PENDING;
4121}
4122
4123int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4124 int slot_id, unsigned int ep_index,
4125 enum xhci_ep_reset_type reset_type)
4126{
4127 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4128 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4129 u32 type = TRB_TYPE(TRB_RESET_EP);
4130
4131 if (reset_type == EP_SOFT_RESET)
4132 type |= TRB_TSP;
4133
4134 return queue_command(xhci, cmd, 0, 0, 0,
4135 trb_slot_id | trb_ep_index | type, false);
4136}