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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright 2006-2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6*/
7
8#include <linux/spinlock.h>
9#include <linux/interrupt.h>
10#include <linux/delay.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17
18#include <linux/spi/spi.h>
19#include <linux/spi/spi_bitbang.h>
20#include <linux/spi/s3c24xx.h>
21#include <linux/spi/s3c24xx-fiq.h>
22#include <linux/module.h>
23
24#include <asm/fiq.h>
25
26#include "spi-s3c24xx-regs.h"
27
28/**
29 * struct s3c24xx_spi_devstate - per device data
30 * @hz: Last frequency calculated for @sppre field.
31 * @mode: Last mode setting for the @spcon field.
32 * @spcon: Value to write to the SPCON register.
33 * @sppre: Value to write to the SPPRE register.
34 */
35struct s3c24xx_spi_devstate {
36 unsigned int hz;
37 unsigned int mode;
38 u8 spcon;
39 u8 sppre;
40};
41
42enum spi_fiq_mode {
43 FIQ_MODE_NONE = 0,
44 FIQ_MODE_TX = 1,
45 FIQ_MODE_RX = 2,
46 FIQ_MODE_TXRX = 3,
47};
48
49struct s3c24xx_spi {
50 /* bitbang has to be first */
51 struct spi_bitbang bitbang;
52 struct completion done;
53
54 void __iomem *regs;
55 int irq;
56 int len;
57 int count;
58
59 struct fiq_handler fiq_handler;
60 enum spi_fiq_mode fiq_mode;
61 unsigned char fiq_inuse;
62 unsigned char fiq_claimed;
63
64 /* data buffers */
65 const unsigned char *tx;
66 unsigned char *rx;
67
68 struct clk *clk;
69 struct spi_master *master;
70 struct spi_device *curdev;
71 struct device *dev;
72 struct s3c2410_spi_info *pdata;
73};
74
75#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
76#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
77
78static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
79{
80 return spi_master_get_devdata(sdev->master);
81}
82
83static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
84{
85 struct s3c24xx_spi_devstate *cs = spi->controller_state;
86 struct s3c24xx_spi *hw = to_hw(spi);
87
88 /* change the chipselect state and the state of the spi engine clock */
89
90 switch (value) {
91 case BITBANG_CS_INACTIVE:
92 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
93 break;
94
95 case BITBANG_CS_ACTIVE:
96 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
97 hw->regs + S3C2410_SPCON);
98 break;
99 }
100}
101
102static int s3c24xx_spi_update_state(struct spi_device *spi,
103 struct spi_transfer *t)
104{
105 struct s3c24xx_spi *hw = to_hw(spi);
106 struct s3c24xx_spi_devstate *cs = spi->controller_state;
107 unsigned int hz;
108 unsigned int div;
109 unsigned long clk;
110
111 hz = t ? t->speed_hz : spi->max_speed_hz;
112
113 if (!hz)
114 hz = spi->max_speed_hz;
115
116 if (spi->mode != cs->mode) {
117 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
118
119 if (spi->mode & SPI_CPHA)
120 spcon |= S3C2410_SPCON_CPHA_FMTB;
121
122 if (spi->mode & SPI_CPOL)
123 spcon |= S3C2410_SPCON_CPOL_HIGH;
124
125 cs->mode = spi->mode;
126 cs->spcon = spcon;
127 }
128
129 if (cs->hz != hz) {
130 clk = clk_get_rate(hw->clk);
131 div = DIV_ROUND_UP(clk, hz * 2) - 1;
132
133 if (div > 255)
134 div = 255;
135
136 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
137 div, hz, clk / (2 * (div + 1)));
138
139 cs->hz = hz;
140 cs->sppre = div;
141 }
142
143 return 0;
144}
145
146static int s3c24xx_spi_setupxfer(struct spi_device *spi,
147 struct spi_transfer *t)
148{
149 struct s3c24xx_spi_devstate *cs = spi->controller_state;
150 struct s3c24xx_spi *hw = to_hw(spi);
151 int ret;
152
153 ret = s3c24xx_spi_update_state(spi, t);
154 if (!ret)
155 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
156
157 return ret;
158}
159
160static int s3c24xx_spi_setup(struct spi_device *spi)
161{
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166 /* allocate settings on the first call */
167 if (!cs) {
168 cs = devm_kzalloc(&spi->dev,
169 sizeof(struct s3c24xx_spi_devstate),
170 GFP_KERNEL);
171 if (!cs)
172 return -ENOMEM;
173
174 cs->spcon = SPCON_DEFAULT;
175 cs->hz = -1;
176 spi->controller_state = cs;
177 }
178
179 /* initialise the state from the device */
180 ret = s3c24xx_spi_update_state(spi, NULL);
181 if (ret)
182 return ret;
183
184 mutex_lock(&hw->bitbang.lock);
185 if (!hw->bitbang.busy) {
186 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
187 /* need to ndelay for 0.5 clocktick ? */
188 }
189 mutex_unlock(&hw->bitbang.lock);
190
191 return 0;
192}
193
194static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
195{
196 return hw->tx ? hw->tx[count] : 0;
197}
198
199#ifdef CONFIG_SPI_S3C24XX_FIQ
200/* Support for FIQ based pseudo-DMA to improve the transfer speed.
201 *
202 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
203 * used by the FIQ core to move data between main memory and the peripheral
204 * block. Since this is code running on the processor, there is no problem
205 * with cache coherency of the buffers, so we can use any buffer we like.
206 */
207
208/**
209 * struct spi_fiq_code - FIQ code and header
210 * @length: The length of the code fragment, excluding this header.
211 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
212 * @data: The code itself to install as a FIQ handler.
213 */
214struct spi_fiq_code {
215 u32 length;
216 u32 ack_offset;
217 u8 data[];
218};
219
220/**
221 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
222 * @hw: The hardware state.
223 *
224 * Claim the FIQ handler (only one can be active at any one time) and
225 * then setup the correct transfer code for this transfer.
226 *
227 * This call updates all the necessary state information if successful,
228 * so the caller does not need to do anything more than start the transfer
229 * as normal, since the IRQ will have been re-routed to the FIQ handler.
230*/
231static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
232{
233 struct pt_regs regs;
234 enum spi_fiq_mode mode;
235 struct spi_fiq_code *code;
236 u32 *ack_ptr = NULL;
237 int ret;
238
239 if (!hw->fiq_claimed) {
240 /* try and claim fiq if we haven't got it, and if not
241 * then return and simply use another transfer method */
242
243 ret = claim_fiq(&hw->fiq_handler);
244 if (ret)
245 return;
246 }
247
248 if (hw->tx && !hw->rx)
249 mode = FIQ_MODE_TX;
250 else if (hw->rx && !hw->tx)
251 mode = FIQ_MODE_RX;
252 else
253 mode = FIQ_MODE_TXRX;
254
255 regs.uregs[fiq_rspi] = (long)hw->regs;
256 regs.uregs[fiq_rrx] = (long)hw->rx;
257 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
258 regs.uregs[fiq_rcount] = hw->len - 1;
259
260 set_fiq_regs(®s);
261
262 if (hw->fiq_mode != mode) {
263 hw->fiq_mode = mode;
264
265 switch (mode) {
266 case FIQ_MODE_TX:
267 code = &s3c24xx_spi_fiq_tx;
268 break;
269 case FIQ_MODE_RX:
270 code = &s3c24xx_spi_fiq_rx;
271 break;
272 case FIQ_MODE_TXRX:
273 code = &s3c24xx_spi_fiq_txrx;
274 break;
275 default:
276 code = NULL;
277 }
278
279 BUG_ON(!code);
280
281 ack_ptr = (u32 *)&code->data[code->ack_offset];
282 set_fiq_handler(&code->data, code->length);
283 }
284
285 s3c24xx_set_fiq(hw->irq, ack_ptr, true);
286
287 hw->fiq_mode = mode;
288 hw->fiq_inuse = 1;
289}
290
291/**
292 * s3c24xx_spi_fiqop - FIQ core code callback
293 * @pw: Data registered with the handler
294 * @release: Whether this is a release or a return.
295 *
296 * Called by the FIQ code when another module wants to use the FIQ, so
297 * return whether we are currently using this or not and then update our
298 * internal state.
299 */
300static int s3c24xx_spi_fiqop(void *pw, int release)
301{
302 struct s3c24xx_spi *hw = pw;
303 int ret = 0;
304
305 if (release) {
306 if (hw->fiq_inuse)
307 ret = -EBUSY;
308
309 /* note, we do not need to unroute the FIQ, as the FIQ
310 * vector code de-routes it to signal the end of transfer */
311
312 hw->fiq_mode = FIQ_MODE_NONE;
313 hw->fiq_claimed = 0;
314 } else {
315 hw->fiq_claimed = 1;
316 }
317
318 return ret;
319}
320
321/**
322 * s3c24xx_spi_initfiq - setup the information for the FIQ core
323 * @hw: The hardware state.
324 *
325 * Setup the fiq_handler block to pass to the FIQ core.
326 */
327static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
328{
329 hw->fiq_handler.dev_id = hw;
330 hw->fiq_handler.name = dev_name(hw->dev);
331 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
332}
333
334/**
335 * s3c24xx_spi_usefiq - return if we should be using FIQ.
336 * @hw: The hardware state.
337 *
338 * Return true if the platform data specifies whether this channel is
339 * allowed to use the FIQ.
340 */
341static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
342{
343 return hw->pdata->use_fiq;
344}
345
346/**
347 * s3c24xx_spi_usingfiq - return if channel is using FIQ
348 * @spi: The hardware state.
349 *
350 * Return whether the channel is currently using the FIQ (separate from
351 * whether the FIQ is claimed).
352 */
353static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
354{
355 return spi->fiq_inuse;
356}
357#else
358
359static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
360static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
361static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
362static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
363
364#endif /* CONFIG_SPI_S3C24XX_FIQ */
365
366static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
367{
368 struct s3c24xx_spi *hw = to_hw(spi);
369
370 hw->tx = t->tx_buf;
371 hw->rx = t->rx_buf;
372 hw->len = t->len;
373 hw->count = 0;
374
375 init_completion(&hw->done);
376
377 hw->fiq_inuse = 0;
378 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
379 s3c24xx_spi_tryfiq(hw);
380
381 /* send the first byte */
382 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
383
384 wait_for_completion(&hw->done);
385 return hw->count;
386}
387
388static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
389{
390 struct s3c24xx_spi *hw = dev;
391 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
392 unsigned int count = hw->count;
393
394 if (spsta & S3C2410_SPSTA_DCOL) {
395 dev_dbg(hw->dev, "data-collision\n");
396 complete(&hw->done);
397 goto irq_done;
398 }
399
400 if (!(spsta & S3C2410_SPSTA_READY)) {
401 dev_dbg(hw->dev, "spi not ready for tx?\n");
402 complete(&hw->done);
403 goto irq_done;
404 }
405
406 if (!s3c24xx_spi_usingfiq(hw)) {
407 hw->count++;
408
409 if (hw->rx)
410 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
411
412 count++;
413
414 if (count < hw->len)
415 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
416 else
417 complete(&hw->done);
418 } else {
419 hw->count = hw->len;
420 hw->fiq_inuse = 0;
421
422 if (hw->rx)
423 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
424
425 complete(&hw->done);
426 }
427
428 irq_done:
429 return IRQ_HANDLED;
430}
431
432static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
433{
434 /* for the moment, permanently enable the clock */
435
436 clk_enable(hw->clk);
437
438 /* program defaults into the registers */
439
440 writeb(0xff, hw->regs + S3C2410_SPPRE);
441 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
442 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
443}
444
445static int s3c24xx_spi_probe(struct platform_device *pdev)
446{
447 struct s3c2410_spi_info *pdata;
448 struct s3c24xx_spi *hw;
449 struct spi_master *master;
450 int err = 0;
451
452 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
453 if (master == NULL) {
454 dev_err(&pdev->dev, "No memory for spi_master\n");
455 return -ENOMEM;
456 }
457
458 hw = spi_master_get_devdata(master);
459
460 hw->master = master;
461 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
462 hw->dev = &pdev->dev;
463
464 if (pdata == NULL) {
465 dev_err(&pdev->dev, "No platform data supplied\n");
466 return -ENOENT;
467 }
468
469 platform_set_drvdata(pdev, hw);
470 init_completion(&hw->done);
471
472 /* initialise fiq handler */
473
474 s3c24xx_spi_initfiq(hw);
475
476 /* setup the master state. */
477
478 /* the spi->mode bits understood by this driver: */
479 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
480
481 master->num_chipselect = hw->pdata->num_cs;
482 master->bus_num = pdata->bus_num;
483 master->bits_per_word_mask = SPI_BPW_MASK(8);
484 /* we need to call the local chipselect callback */
485 master->flags = SPI_MASTER_GPIO_SS;
486 master->use_gpio_descriptors = true;
487
488 /* setup the state for the bitbang driver */
489
490 hw->bitbang.master = hw->master;
491 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
492 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
493 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
494
495 hw->master->setup = s3c24xx_spi_setup;
496
497 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
498
499 /* find and map our resources */
500 hw->regs = devm_platform_ioremap_resource(pdev, 0);
501 if (IS_ERR(hw->regs))
502 return PTR_ERR(hw->regs);
503
504 hw->irq = platform_get_irq(pdev, 0);
505 if (hw->irq < 0)
506 return -ENOENT;
507
508 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
509 pdev->name, hw);
510 if (err) {
511 dev_err(&pdev->dev, "Cannot claim IRQ\n");
512 return err;
513 }
514
515 hw->clk = devm_clk_get(&pdev->dev, "spi");
516 if (IS_ERR(hw->clk)) {
517 dev_err(&pdev->dev, "No clock for device\n");
518 return PTR_ERR(hw->clk);
519 }
520
521 s3c24xx_spi_initialsetup(hw);
522
523 /* register our spi controller */
524
525 err = spi_bitbang_start(&hw->bitbang);
526 if (err) {
527 dev_err(&pdev->dev, "Failed to register SPI master\n");
528 goto err_register;
529 }
530
531 return 0;
532
533 err_register:
534 clk_disable(hw->clk);
535
536 return err;
537}
538
539static int s3c24xx_spi_remove(struct platform_device *dev)
540{
541 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
542
543 spi_bitbang_stop(&hw->bitbang);
544 clk_disable(hw->clk);
545 spi_master_put(hw->master);
546 return 0;
547}
548
549
550#ifdef CONFIG_PM
551
552static int s3c24xx_spi_suspend(struct device *dev)
553{
554 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
555 int ret;
556
557 ret = spi_master_suspend(hw->master);
558 if (ret)
559 return ret;
560
561 clk_disable(hw->clk);
562 return 0;
563}
564
565static int s3c24xx_spi_resume(struct device *dev)
566{
567 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
568
569 s3c24xx_spi_initialsetup(hw);
570 return spi_master_resume(hw->master);
571}
572
573static const struct dev_pm_ops s3c24xx_spi_pmops = {
574 .suspend = s3c24xx_spi_suspend,
575 .resume = s3c24xx_spi_resume,
576};
577
578#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
579#else
580#define S3C24XX_SPI_PMOPS NULL
581#endif /* CONFIG_PM */
582
583MODULE_ALIAS("platform:s3c2410-spi");
584static struct platform_driver s3c24xx_spi_driver = {
585 .probe = s3c24xx_spi_probe,
586 .remove = s3c24xx_spi_remove,
587 .driver = {
588 .name = "s3c2410-spi",
589 .pm = S3C24XX_SPI_PMOPS,
590 },
591};
592module_platform_driver(s3c24xx_spi_driver);
593
594MODULE_DESCRIPTION("S3C24XX SPI Driver");
595MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
596MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright 2006-2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6*/
7
8#include <linux/spinlock.h>
9#include <linux/interrupt.h>
10#include <linux/delay.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15#include <linux/gpio.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18
19#include <linux/spi/spi.h>
20#include <linux/spi/spi_bitbang.h>
21#include <linux/spi/s3c24xx.h>
22#include <linux/module.h>
23
24#include <plat/regs-spi.h>
25
26#include <asm/fiq.h>
27
28#include "spi-s3c24xx-fiq.h"
29
30/**
31 * s3c24xx_spi_devstate - per device data
32 * @hz: Last frequency calculated for @sppre field.
33 * @mode: Last mode setting for the @spcon field.
34 * @spcon: Value to write to the SPCON register.
35 * @sppre: Value to write to the SPPRE register.
36 */
37struct s3c24xx_spi_devstate {
38 unsigned int hz;
39 unsigned int mode;
40 u8 spcon;
41 u8 sppre;
42};
43
44enum spi_fiq_mode {
45 FIQ_MODE_NONE = 0,
46 FIQ_MODE_TX = 1,
47 FIQ_MODE_RX = 2,
48 FIQ_MODE_TXRX = 3,
49};
50
51struct s3c24xx_spi {
52 /* bitbang has to be first */
53 struct spi_bitbang bitbang;
54 struct completion done;
55
56 void __iomem *regs;
57 int irq;
58 int len;
59 int count;
60
61 struct fiq_handler fiq_handler;
62 enum spi_fiq_mode fiq_mode;
63 unsigned char fiq_inuse;
64 unsigned char fiq_claimed;
65
66 void (*set_cs)(struct s3c2410_spi_info *spi,
67 int cs, int pol);
68
69 /* data buffers */
70 const unsigned char *tx;
71 unsigned char *rx;
72
73 struct clk *clk;
74 struct spi_master *master;
75 struct spi_device *curdev;
76 struct device *dev;
77 struct s3c2410_spi_info *pdata;
78};
79
80#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
81#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
82
83static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
84{
85 return spi_master_get_devdata(sdev->master);
86}
87
88static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
89{
90 gpio_set_value(spi->pin_cs, pol);
91}
92
93static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
94{
95 struct s3c24xx_spi_devstate *cs = spi->controller_state;
96 struct s3c24xx_spi *hw = to_hw(spi);
97 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
98
99 /* change the chipselect state and the state of the spi engine clock */
100
101 switch (value) {
102 case BITBANG_CS_INACTIVE:
103 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
104 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
105 break;
106
107 case BITBANG_CS_ACTIVE:
108 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
109 hw->regs + S3C2410_SPCON);
110 hw->set_cs(hw->pdata, spi->chip_select, cspol);
111 break;
112 }
113}
114
115static int s3c24xx_spi_update_state(struct spi_device *spi,
116 struct spi_transfer *t)
117{
118 struct s3c24xx_spi *hw = to_hw(spi);
119 struct s3c24xx_spi_devstate *cs = spi->controller_state;
120 unsigned int hz;
121 unsigned int div;
122 unsigned long clk;
123
124 hz = t ? t->speed_hz : spi->max_speed_hz;
125
126 if (!hz)
127 hz = spi->max_speed_hz;
128
129 if (spi->mode != cs->mode) {
130 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
131
132 if (spi->mode & SPI_CPHA)
133 spcon |= S3C2410_SPCON_CPHA_FMTB;
134
135 if (spi->mode & SPI_CPOL)
136 spcon |= S3C2410_SPCON_CPOL_HIGH;
137
138 cs->mode = spi->mode;
139 cs->spcon = spcon;
140 }
141
142 if (cs->hz != hz) {
143 clk = clk_get_rate(hw->clk);
144 div = DIV_ROUND_UP(clk, hz * 2) - 1;
145
146 if (div > 255)
147 div = 255;
148
149 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
150 div, hz, clk / (2 * (div + 1)));
151
152 cs->hz = hz;
153 cs->sppre = div;
154 }
155
156 return 0;
157}
158
159static int s3c24xx_spi_setupxfer(struct spi_device *spi,
160 struct spi_transfer *t)
161{
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166 ret = s3c24xx_spi_update_state(spi, t);
167 if (!ret)
168 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
169
170 return ret;
171}
172
173static int s3c24xx_spi_setup(struct spi_device *spi)
174{
175 struct s3c24xx_spi_devstate *cs = spi->controller_state;
176 struct s3c24xx_spi *hw = to_hw(spi);
177 int ret;
178
179 /* allocate settings on the first call */
180 if (!cs) {
181 cs = devm_kzalloc(&spi->dev,
182 sizeof(struct s3c24xx_spi_devstate),
183 GFP_KERNEL);
184 if (!cs)
185 return -ENOMEM;
186
187 cs->spcon = SPCON_DEFAULT;
188 cs->hz = -1;
189 spi->controller_state = cs;
190 }
191
192 /* initialise the state from the device */
193 ret = s3c24xx_spi_update_state(spi, NULL);
194 if (ret)
195 return ret;
196
197 mutex_lock(&hw->bitbang.lock);
198 if (!hw->bitbang.busy) {
199 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
200 /* need to ndelay for 0.5 clocktick ? */
201 }
202 mutex_unlock(&hw->bitbang.lock);
203
204 return 0;
205}
206
207static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
208{
209 return hw->tx ? hw->tx[count] : 0;
210}
211
212#ifdef CONFIG_SPI_S3C24XX_FIQ
213/* Support for FIQ based pseudo-DMA to improve the transfer speed.
214 *
215 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
216 * used by the FIQ core to move data between main memory and the peripheral
217 * block. Since this is code running on the processor, there is no problem
218 * with cache coherency of the buffers, so we can use any buffer we like.
219 */
220
221/**
222 * struct spi_fiq_code - FIQ code and header
223 * @length: The length of the code fragment, excluding this header.
224 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
225 * @data: The code itself to install as a FIQ handler.
226 */
227struct spi_fiq_code {
228 u32 length;
229 u32 ack_offset;
230 u8 data[0];
231};
232
233extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
234extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
235extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
236
237/**
238 * ack_bit - turn IRQ into IRQ acknowledgement bit
239 * @irq: The interrupt number
240 *
241 * Returns the bit to write to the interrupt acknowledge register.
242 */
243static inline u32 ack_bit(unsigned int irq)
244{
245 return 1 << (irq - IRQ_EINT0);
246}
247
248/**
249 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
250 * @hw: The hardware state.
251 *
252 * Claim the FIQ handler (only one can be active at any one time) and
253 * then setup the correct transfer code for this transfer.
254 *
255 * This call updates all the necessary state information if successful,
256 * so the caller does not need to do anything more than start the transfer
257 * as normal, since the IRQ will have been re-routed to the FIQ handler.
258*/
259static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
260{
261 struct pt_regs regs;
262 enum spi_fiq_mode mode;
263 struct spi_fiq_code *code;
264 int ret;
265
266 if (!hw->fiq_claimed) {
267 /* try and claim fiq if we haven't got it, and if not
268 * then return and simply use another transfer method */
269
270 ret = claim_fiq(&hw->fiq_handler);
271 if (ret)
272 return;
273 }
274
275 if (hw->tx && !hw->rx)
276 mode = FIQ_MODE_TX;
277 else if (hw->rx && !hw->tx)
278 mode = FIQ_MODE_RX;
279 else
280 mode = FIQ_MODE_TXRX;
281
282 regs.uregs[fiq_rspi] = (long)hw->regs;
283 regs.uregs[fiq_rrx] = (long)hw->rx;
284 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
285 regs.uregs[fiq_rcount] = hw->len - 1;
286 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
287
288 set_fiq_regs(®s);
289
290 if (hw->fiq_mode != mode) {
291 u32 *ack_ptr;
292
293 hw->fiq_mode = mode;
294
295 switch (mode) {
296 case FIQ_MODE_TX:
297 code = &s3c24xx_spi_fiq_tx;
298 break;
299 case FIQ_MODE_RX:
300 code = &s3c24xx_spi_fiq_rx;
301 break;
302 case FIQ_MODE_TXRX:
303 code = &s3c24xx_spi_fiq_txrx;
304 break;
305 default:
306 code = NULL;
307 }
308
309 BUG_ON(!code);
310
311 ack_ptr = (u32 *)&code->data[code->ack_offset];
312 *ack_ptr = ack_bit(hw->irq);
313
314 set_fiq_handler(&code->data, code->length);
315 }
316
317 s3c24xx_set_fiq(hw->irq, true);
318
319 hw->fiq_mode = mode;
320 hw->fiq_inuse = 1;
321}
322
323/**
324 * s3c24xx_spi_fiqop - FIQ core code callback
325 * @pw: Data registered with the handler
326 * @release: Whether this is a release or a return.
327 *
328 * Called by the FIQ code when another module wants to use the FIQ, so
329 * return whether we are currently using this or not and then update our
330 * internal state.
331 */
332static int s3c24xx_spi_fiqop(void *pw, int release)
333{
334 struct s3c24xx_spi *hw = pw;
335 int ret = 0;
336
337 if (release) {
338 if (hw->fiq_inuse)
339 ret = -EBUSY;
340
341 /* note, we do not need to unroute the FIQ, as the FIQ
342 * vector code de-routes it to signal the end of transfer */
343
344 hw->fiq_mode = FIQ_MODE_NONE;
345 hw->fiq_claimed = 0;
346 } else {
347 hw->fiq_claimed = 1;
348 }
349
350 return ret;
351}
352
353/**
354 * s3c24xx_spi_initfiq - setup the information for the FIQ core
355 * @hw: The hardware state.
356 *
357 * Setup the fiq_handler block to pass to the FIQ core.
358 */
359static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
360{
361 hw->fiq_handler.dev_id = hw;
362 hw->fiq_handler.name = dev_name(hw->dev);
363 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
364}
365
366/**
367 * s3c24xx_spi_usefiq - return if we should be using FIQ.
368 * @hw: The hardware state.
369 *
370 * Return true if the platform data specifies whether this channel is
371 * allowed to use the FIQ.
372 */
373static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
374{
375 return hw->pdata->use_fiq;
376}
377
378/**
379 * s3c24xx_spi_usingfiq - return if channel is using FIQ
380 * @spi: The hardware state.
381 *
382 * Return whether the channel is currently using the FIQ (separate from
383 * whether the FIQ is claimed).
384 */
385static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
386{
387 return spi->fiq_inuse;
388}
389#else
390
391static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
392static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
393static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
394static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
395
396#endif /* CONFIG_SPI_S3C24XX_FIQ */
397
398static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
399{
400 struct s3c24xx_spi *hw = to_hw(spi);
401
402 hw->tx = t->tx_buf;
403 hw->rx = t->rx_buf;
404 hw->len = t->len;
405 hw->count = 0;
406
407 init_completion(&hw->done);
408
409 hw->fiq_inuse = 0;
410 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
411 s3c24xx_spi_tryfiq(hw);
412
413 /* send the first byte */
414 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
415
416 wait_for_completion(&hw->done);
417 return hw->count;
418}
419
420static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
421{
422 struct s3c24xx_spi *hw = dev;
423 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
424 unsigned int count = hw->count;
425
426 if (spsta & S3C2410_SPSTA_DCOL) {
427 dev_dbg(hw->dev, "data-collision\n");
428 complete(&hw->done);
429 goto irq_done;
430 }
431
432 if (!(spsta & S3C2410_SPSTA_READY)) {
433 dev_dbg(hw->dev, "spi not ready for tx?\n");
434 complete(&hw->done);
435 goto irq_done;
436 }
437
438 if (!s3c24xx_spi_usingfiq(hw)) {
439 hw->count++;
440
441 if (hw->rx)
442 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
443
444 count++;
445
446 if (count < hw->len)
447 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
448 else
449 complete(&hw->done);
450 } else {
451 hw->count = hw->len;
452 hw->fiq_inuse = 0;
453
454 if (hw->rx)
455 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
456
457 complete(&hw->done);
458 }
459
460 irq_done:
461 return IRQ_HANDLED;
462}
463
464static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
465{
466 /* for the moment, permanently enable the clock */
467
468 clk_enable(hw->clk);
469
470 /* program defaults into the registers */
471
472 writeb(0xff, hw->regs + S3C2410_SPPRE);
473 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
474 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
475
476 if (hw->pdata) {
477 if (hw->set_cs == s3c24xx_spi_gpiocs)
478 gpio_direction_output(hw->pdata->pin_cs, 1);
479
480 if (hw->pdata->gpio_setup)
481 hw->pdata->gpio_setup(hw->pdata, 1);
482 }
483}
484
485static int s3c24xx_spi_probe(struct platform_device *pdev)
486{
487 struct s3c2410_spi_info *pdata;
488 struct s3c24xx_spi *hw;
489 struct spi_master *master;
490 int err = 0;
491
492 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
493 if (master == NULL) {
494 dev_err(&pdev->dev, "No memory for spi_master\n");
495 return -ENOMEM;
496 }
497
498 hw = spi_master_get_devdata(master);
499
500 hw->master = master;
501 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
502 hw->dev = &pdev->dev;
503
504 if (pdata == NULL) {
505 dev_err(&pdev->dev, "No platform data supplied\n");
506 err = -ENOENT;
507 goto err_no_pdata;
508 }
509
510 platform_set_drvdata(pdev, hw);
511 init_completion(&hw->done);
512
513 /* initialise fiq handler */
514
515 s3c24xx_spi_initfiq(hw);
516
517 /* setup the master state. */
518
519 /* the spi->mode bits understood by this driver: */
520 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
521
522 master->num_chipselect = hw->pdata->num_cs;
523 master->bus_num = pdata->bus_num;
524 master->bits_per_word_mask = SPI_BPW_MASK(8);
525
526 /* setup the state for the bitbang driver */
527
528 hw->bitbang.master = hw->master;
529 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
530 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
531 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
532
533 hw->master->setup = s3c24xx_spi_setup;
534
535 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
536
537 /* find and map our resources */
538 hw->regs = devm_platform_ioremap_resource(pdev, 0);
539 if (IS_ERR(hw->regs)) {
540 err = PTR_ERR(hw->regs);
541 goto err_no_pdata;
542 }
543
544 hw->irq = platform_get_irq(pdev, 0);
545 if (hw->irq < 0) {
546 err = -ENOENT;
547 goto err_no_pdata;
548 }
549
550 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
551 pdev->name, hw);
552 if (err) {
553 dev_err(&pdev->dev, "Cannot claim IRQ\n");
554 goto err_no_pdata;
555 }
556
557 hw->clk = devm_clk_get(&pdev->dev, "spi");
558 if (IS_ERR(hw->clk)) {
559 dev_err(&pdev->dev, "No clock for device\n");
560 err = PTR_ERR(hw->clk);
561 goto err_no_pdata;
562 }
563
564 /* setup any gpio we can */
565
566 if (!pdata->set_cs) {
567 if (pdata->pin_cs < 0) {
568 dev_err(&pdev->dev, "No chipselect pin\n");
569 err = -EINVAL;
570 goto err_register;
571 }
572
573 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
574 dev_name(&pdev->dev));
575 if (err) {
576 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
577 goto err_register;
578 }
579
580 hw->set_cs = s3c24xx_spi_gpiocs;
581 gpio_direction_output(pdata->pin_cs, 1);
582 } else
583 hw->set_cs = pdata->set_cs;
584
585 s3c24xx_spi_initialsetup(hw);
586
587 /* register our spi controller */
588
589 err = spi_bitbang_start(&hw->bitbang);
590 if (err) {
591 dev_err(&pdev->dev, "Failed to register SPI master\n");
592 goto err_register;
593 }
594
595 return 0;
596
597 err_register:
598 clk_disable(hw->clk);
599
600 err_no_pdata:
601 spi_master_put(hw->master);
602 return err;
603}
604
605static int s3c24xx_spi_remove(struct platform_device *dev)
606{
607 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
608
609 spi_bitbang_stop(&hw->bitbang);
610 clk_disable(hw->clk);
611 spi_master_put(hw->master);
612 return 0;
613}
614
615
616#ifdef CONFIG_PM
617
618static int s3c24xx_spi_suspend(struct device *dev)
619{
620 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
621 int ret;
622
623 ret = spi_master_suspend(hw->master);
624 if (ret)
625 return ret;
626
627 if (hw->pdata && hw->pdata->gpio_setup)
628 hw->pdata->gpio_setup(hw->pdata, 0);
629
630 clk_disable(hw->clk);
631 return 0;
632}
633
634static int s3c24xx_spi_resume(struct device *dev)
635{
636 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
637
638 s3c24xx_spi_initialsetup(hw);
639 return spi_master_resume(hw->master);
640}
641
642static const struct dev_pm_ops s3c24xx_spi_pmops = {
643 .suspend = s3c24xx_spi_suspend,
644 .resume = s3c24xx_spi_resume,
645};
646
647#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
648#else
649#define S3C24XX_SPI_PMOPS NULL
650#endif /* CONFIG_PM */
651
652MODULE_ALIAS("platform:s3c2410-spi");
653static struct platform_driver s3c24xx_spi_driver = {
654 .probe = s3c24xx_spi_probe,
655 .remove = s3c24xx_spi_remove,
656 .driver = {
657 .name = "s3c2410-spi",
658 .pm = S3C24XX_SPI_PMOPS,
659 },
660};
661module_platform_driver(s3c24xx_spi_driver);
662
663MODULE_DESCRIPTION("S3C24XX SPI Driver");
664MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
665MODULE_LICENSE("GPL");