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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright 2006-2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6*/
7
8#include <linux/spinlock.h>
9#include <linux/interrupt.h>
10#include <linux/delay.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17
18#include <linux/spi/spi.h>
19#include <linux/spi/spi_bitbang.h>
20#include <linux/spi/s3c24xx.h>
21#include <linux/spi/s3c24xx-fiq.h>
22#include <linux/module.h>
23
24#include <asm/fiq.h>
25
26#include "spi-s3c24xx-regs.h"
27
28/**
29 * struct s3c24xx_spi_devstate - per device data
30 * @hz: Last frequency calculated for @sppre field.
31 * @mode: Last mode setting for the @spcon field.
32 * @spcon: Value to write to the SPCON register.
33 * @sppre: Value to write to the SPPRE register.
34 */
35struct s3c24xx_spi_devstate {
36 unsigned int hz;
37 unsigned int mode;
38 u8 spcon;
39 u8 sppre;
40};
41
42enum spi_fiq_mode {
43 FIQ_MODE_NONE = 0,
44 FIQ_MODE_TX = 1,
45 FIQ_MODE_RX = 2,
46 FIQ_MODE_TXRX = 3,
47};
48
49struct s3c24xx_spi {
50 /* bitbang has to be first */
51 struct spi_bitbang bitbang;
52 struct completion done;
53
54 void __iomem *regs;
55 int irq;
56 int len;
57 int count;
58
59 struct fiq_handler fiq_handler;
60 enum spi_fiq_mode fiq_mode;
61 unsigned char fiq_inuse;
62 unsigned char fiq_claimed;
63
64 /* data buffers */
65 const unsigned char *tx;
66 unsigned char *rx;
67
68 struct clk *clk;
69 struct spi_master *master;
70 struct spi_device *curdev;
71 struct device *dev;
72 struct s3c2410_spi_info *pdata;
73};
74
75#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
76#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
77
78static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
79{
80 return spi_master_get_devdata(sdev->master);
81}
82
83static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
84{
85 struct s3c24xx_spi_devstate *cs = spi->controller_state;
86 struct s3c24xx_spi *hw = to_hw(spi);
87
88 /* change the chipselect state and the state of the spi engine clock */
89
90 switch (value) {
91 case BITBANG_CS_INACTIVE:
92 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
93 break;
94
95 case BITBANG_CS_ACTIVE:
96 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
97 hw->regs + S3C2410_SPCON);
98 break;
99 }
100}
101
102static int s3c24xx_spi_update_state(struct spi_device *spi,
103 struct spi_transfer *t)
104{
105 struct s3c24xx_spi *hw = to_hw(spi);
106 struct s3c24xx_spi_devstate *cs = spi->controller_state;
107 unsigned int hz;
108 unsigned int div;
109 unsigned long clk;
110
111 hz = t ? t->speed_hz : spi->max_speed_hz;
112
113 if (!hz)
114 hz = spi->max_speed_hz;
115
116 if (spi->mode != cs->mode) {
117 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
118
119 if (spi->mode & SPI_CPHA)
120 spcon |= S3C2410_SPCON_CPHA_FMTB;
121
122 if (spi->mode & SPI_CPOL)
123 spcon |= S3C2410_SPCON_CPOL_HIGH;
124
125 cs->mode = spi->mode;
126 cs->spcon = spcon;
127 }
128
129 if (cs->hz != hz) {
130 clk = clk_get_rate(hw->clk);
131 div = DIV_ROUND_UP(clk, hz * 2) - 1;
132
133 if (div > 255)
134 div = 255;
135
136 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
137 div, hz, clk / (2 * (div + 1)));
138
139 cs->hz = hz;
140 cs->sppre = div;
141 }
142
143 return 0;
144}
145
146static int s3c24xx_spi_setupxfer(struct spi_device *spi,
147 struct spi_transfer *t)
148{
149 struct s3c24xx_spi_devstate *cs = spi->controller_state;
150 struct s3c24xx_spi *hw = to_hw(spi);
151 int ret;
152
153 ret = s3c24xx_spi_update_state(spi, t);
154 if (!ret)
155 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
156
157 return ret;
158}
159
160static int s3c24xx_spi_setup(struct spi_device *spi)
161{
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166 /* allocate settings on the first call */
167 if (!cs) {
168 cs = devm_kzalloc(&spi->dev,
169 sizeof(struct s3c24xx_spi_devstate),
170 GFP_KERNEL);
171 if (!cs)
172 return -ENOMEM;
173
174 cs->spcon = SPCON_DEFAULT;
175 cs->hz = -1;
176 spi->controller_state = cs;
177 }
178
179 /* initialise the state from the device */
180 ret = s3c24xx_spi_update_state(spi, NULL);
181 if (ret)
182 return ret;
183
184 mutex_lock(&hw->bitbang.lock);
185 if (!hw->bitbang.busy) {
186 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
187 /* need to ndelay for 0.5 clocktick ? */
188 }
189 mutex_unlock(&hw->bitbang.lock);
190
191 return 0;
192}
193
194static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
195{
196 return hw->tx ? hw->tx[count] : 0;
197}
198
199#ifdef CONFIG_SPI_S3C24XX_FIQ
200/* Support for FIQ based pseudo-DMA to improve the transfer speed.
201 *
202 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
203 * used by the FIQ core to move data between main memory and the peripheral
204 * block. Since this is code running on the processor, there is no problem
205 * with cache coherency of the buffers, so we can use any buffer we like.
206 */
207
208/**
209 * struct spi_fiq_code - FIQ code and header
210 * @length: The length of the code fragment, excluding this header.
211 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
212 * @data: The code itself to install as a FIQ handler.
213 */
214struct spi_fiq_code {
215 u32 length;
216 u32 ack_offset;
217 u8 data[];
218};
219
220/**
221 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
222 * @hw: The hardware state.
223 *
224 * Claim the FIQ handler (only one can be active at any one time) and
225 * then setup the correct transfer code for this transfer.
226 *
227 * This call updates all the necessary state information if successful,
228 * so the caller does not need to do anything more than start the transfer
229 * as normal, since the IRQ will have been re-routed to the FIQ handler.
230*/
231static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
232{
233 struct pt_regs regs;
234 enum spi_fiq_mode mode;
235 struct spi_fiq_code *code;
236 u32 *ack_ptr = NULL;
237 int ret;
238
239 if (!hw->fiq_claimed) {
240 /* try and claim fiq if we haven't got it, and if not
241 * then return and simply use another transfer method */
242
243 ret = claim_fiq(&hw->fiq_handler);
244 if (ret)
245 return;
246 }
247
248 if (hw->tx && !hw->rx)
249 mode = FIQ_MODE_TX;
250 else if (hw->rx && !hw->tx)
251 mode = FIQ_MODE_RX;
252 else
253 mode = FIQ_MODE_TXRX;
254
255 regs.uregs[fiq_rspi] = (long)hw->regs;
256 regs.uregs[fiq_rrx] = (long)hw->rx;
257 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
258 regs.uregs[fiq_rcount] = hw->len - 1;
259
260 set_fiq_regs(®s);
261
262 if (hw->fiq_mode != mode) {
263 hw->fiq_mode = mode;
264
265 switch (mode) {
266 case FIQ_MODE_TX:
267 code = &s3c24xx_spi_fiq_tx;
268 break;
269 case FIQ_MODE_RX:
270 code = &s3c24xx_spi_fiq_rx;
271 break;
272 case FIQ_MODE_TXRX:
273 code = &s3c24xx_spi_fiq_txrx;
274 break;
275 default:
276 code = NULL;
277 }
278
279 BUG_ON(!code);
280
281 ack_ptr = (u32 *)&code->data[code->ack_offset];
282 set_fiq_handler(&code->data, code->length);
283 }
284
285 s3c24xx_set_fiq(hw->irq, ack_ptr, true);
286
287 hw->fiq_mode = mode;
288 hw->fiq_inuse = 1;
289}
290
291/**
292 * s3c24xx_spi_fiqop - FIQ core code callback
293 * @pw: Data registered with the handler
294 * @release: Whether this is a release or a return.
295 *
296 * Called by the FIQ code when another module wants to use the FIQ, so
297 * return whether we are currently using this or not and then update our
298 * internal state.
299 */
300static int s3c24xx_spi_fiqop(void *pw, int release)
301{
302 struct s3c24xx_spi *hw = pw;
303 int ret = 0;
304
305 if (release) {
306 if (hw->fiq_inuse)
307 ret = -EBUSY;
308
309 /* note, we do not need to unroute the FIQ, as the FIQ
310 * vector code de-routes it to signal the end of transfer */
311
312 hw->fiq_mode = FIQ_MODE_NONE;
313 hw->fiq_claimed = 0;
314 } else {
315 hw->fiq_claimed = 1;
316 }
317
318 return ret;
319}
320
321/**
322 * s3c24xx_spi_initfiq - setup the information for the FIQ core
323 * @hw: The hardware state.
324 *
325 * Setup the fiq_handler block to pass to the FIQ core.
326 */
327static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
328{
329 hw->fiq_handler.dev_id = hw;
330 hw->fiq_handler.name = dev_name(hw->dev);
331 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
332}
333
334/**
335 * s3c24xx_spi_usefiq - return if we should be using FIQ.
336 * @hw: The hardware state.
337 *
338 * Return true if the platform data specifies whether this channel is
339 * allowed to use the FIQ.
340 */
341static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
342{
343 return hw->pdata->use_fiq;
344}
345
346/**
347 * s3c24xx_spi_usingfiq - return if channel is using FIQ
348 * @spi: The hardware state.
349 *
350 * Return whether the channel is currently using the FIQ (separate from
351 * whether the FIQ is claimed).
352 */
353static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
354{
355 return spi->fiq_inuse;
356}
357#else
358
359static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
360static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
361static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
362static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
363
364#endif /* CONFIG_SPI_S3C24XX_FIQ */
365
366static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
367{
368 struct s3c24xx_spi *hw = to_hw(spi);
369
370 hw->tx = t->tx_buf;
371 hw->rx = t->rx_buf;
372 hw->len = t->len;
373 hw->count = 0;
374
375 init_completion(&hw->done);
376
377 hw->fiq_inuse = 0;
378 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
379 s3c24xx_spi_tryfiq(hw);
380
381 /* send the first byte */
382 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
383
384 wait_for_completion(&hw->done);
385 return hw->count;
386}
387
388static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
389{
390 struct s3c24xx_spi *hw = dev;
391 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
392 unsigned int count = hw->count;
393
394 if (spsta & S3C2410_SPSTA_DCOL) {
395 dev_dbg(hw->dev, "data-collision\n");
396 complete(&hw->done);
397 goto irq_done;
398 }
399
400 if (!(spsta & S3C2410_SPSTA_READY)) {
401 dev_dbg(hw->dev, "spi not ready for tx?\n");
402 complete(&hw->done);
403 goto irq_done;
404 }
405
406 if (!s3c24xx_spi_usingfiq(hw)) {
407 hw->count++;
408
409 if (hw->rx)
410 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
411
412 count++;
413
414 if (count < hw->len)
415 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
416 else
417 complete(&hw->done);
418 } else {
419 hw->count = hw->len;
420 hw->fiq_inuse = 0;
421
422 if (hw->rx)
423 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
424
425 complete(&hw->done);
426 }
427
428 irq_done:
429 return IRQ_HANDLED;
430}
431
432static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
433{
434 /* for the moment, permanently enable the clock */
435
436 clk_enable(hw->clk);
437
438 /* program defaults into the registers */
439
440 writeb(0xff, hw->regs + S3C2410_SPPRE);
441 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
442 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
443}
444
445static int s3c24xx_spi_probe(struct platform_device *pdev)
446{
447 struct s3c2410_spi_info *pdata;
448 struct s3c24xx_spi *hw;
449 struct spi_master *master;
450 int err = 0;
451
452 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
453 if (master == NULL) {
454 dev_err(&pdev->dev, "No memory for spi_master\n");
455 return -ENOMEM;
456 }
457
458 hw = spi_master_get_devdata(master);
459
460 hw->master = master;
461 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
462 hw->dev = &pdev->dev;
463
464 if (pdata == NULL) {
465 dev_err(&pdev->dev, "No platform data supplied\n");
466 return -ENOENT;
467 }
468
469 platform_set_drvdata(pdev, hw);
470 init_completion(&hw->done);
471
472 /* initialise fiq handler */
473
474 s3c24xx_spi_initfiq(hw);
475
476 /* setup the master state. */
477
478 /* the spi->mode bits understood by this driver: */
479 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
480
481 master->num_chipselect = hw->pdata->num_cs;
482 master->bus_num = pdata->bus_num;
483 master->bits_per_word_mask = SPI_BPW_MASK(8);
484 /* we need to call the local chipselect callback */
485 master->flags = SPI_MASTER_GPIO_SS;
486 master->use_gpio_descriptors = true;
487
488 /* setup the state for the bitbang driver */
489
490 hw->bitbang.master = hw->master;
491 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
492 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
493 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
494
495 hw->master->setup = s3c24xx_spi_setup;
496
497 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
498
499 /* find and map our resources */
500 hw->regs = devm_platform_ioremap_resource(pdev, 0);
501 if (IS_ERR(hw->regs))
502 return PTR_ERR(hw->regs);
503
504 hw->irq = platform_get_irq(pdev, 0);
505 if (hw->irq < 0)
506 return -ENOENT;
507
508 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
509 pdev->name, hw);
510 if (err) {
511 dev_err(&pdev->dev, "Cannot claim IRQ\n");
512 return err;
513 }
514
515 hw->clk = devm_clk_get(&pdev->dev, "spi");
516 if (IS_ERR(hw->clk)) {
517 dev_err(&pdev->dev, "No clock for device\n");
518 return PTR_ERR(hw->clk);
519 }
520
521 s3c24xx_spi_initialsetup(hw);
522
523 /* register our spi controller */
524
525 err = spi_bitbang_start(&hw->bitbang);
526 if (err) {
527 dev_err(&pdev->dev, "Failed to register SPI master\n");
528 goto err_register;
529 }
530
531 return 0;
532
533 err_register:
534 clk_disable(hw->clk);
535
536 return err;
537}
538
539static int s3c24xx_spi_remove(struct platform_device *dev)
540{
541 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
542
543 spi_bitbang_stop(&hw->bitbang);
544 clk_disable(hw->clk);
545 spi_master_put(hw->master);
546 return 0;
547}
548
549
550#ifdef CONFIG_PM
551
552static int s3c24xx_spi_suspend(struct device *dev)
553{
554 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
555 int ret;
556
557 ret = spi_master_suspend(hw->master);
558 if (ret)
559 return ret;
560
561 clk_disable(hw->clk);
562 return 0;
563}
564
565static int s3c24xx_spi_resume(struct device *dev)
566{
567 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
568
569 s3c24xx_spi_initialsetup(hw);
570 return spi_master_resume(hw->master);
571}
572
573static const struct dev_pm_ops s3c24xx_spi_pmops = {
574 .suspend = s3c24xx_spi_suspend,
575 .resume = s3c24xx_spi_resume,
576};
577
578#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
579#else
580#define S3C24XX_SPI_PMOPS NULL
581#endif /* CONFIG_PM */
582
583MODULE_ALIAS("platform:s3c2410-spi");
584static struct platform_driver s3c24xx_spi_driver = {
585 .probe = s3c24xx_spi_probe,
586 .remove = s3c24xx_spi_remove,
587 .driver = {
588 .name = "s3c2410-spi",
589 .pm = S3C24XX_SPI_PMOPS,
590 },
591};
592module_platform_driver(s3c24xx_spi_driver);
593
594MODULE_DESCRIPTION("S3C24XX SPI Driver");
595MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
596MODULE_LICENSE("GPL");
1/*
2 * Copyright (c) 2006 Ben Dooks
3 * Copyright 2006-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10*/
11
12#include <linux/spinlock.h>
13#include <linux/interrupt.h>
14#include <linux/delay.h>
15#include <linux/errno.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
19#include <linux/gpio.h>
20#include <linux/io.h>
21#include <linux/slab.h>
22
23#include <linux/spi/spi.h>
24#include <linux/spi/spi_bitbang.h>
25#include <linux/spi/s3c24xx.h>
26#include <linux/module.h>
27
28#include <plat/regs-spi.h>
29
30#include <asm/fiq.h>
31
32#include "spi-s3c24xx-fiq.h"
33
34/**
35 * s3c24xx_spi_devstate - per device data
36 * @hz: Last frequency calculated for @sppre field.
37 * @mode: Last mode setting for the @spcon field.
38 * @spcon: Value to write to the SPCON register.
39 * @sppre: Value to write to the SPPRE register.
40 */
41struct s3c24xx_spi_devstate {
42 unsigned int hz;
43 unsigned int mode;
44 u8 spcon;
45 u8 sppre;
46};
47
48enum spi_fiq_mode {
49 FIQ_MODE_NONE = 0,
50 FIQ_MODE_TX = 1,
51 FIQ_MODE_RX = 2,
52 FIQ_MODE_TXRX = 3,
53};
54
55struct s3c24xx_spi {
56 /* bitbang has to be first */
57 struct spi_bitbang bitbang;
58 struct completion done;
59
60 void __iomem *regs;
61 int irq;
62 int len;
63 int count;
64
65 struct fiq_handler fiq_handler;
66 enum spi_fiq_mode fiq_mode;
67 unsigned char fiq_inuse;
68 unsigned char fiq_claimed;
69
70 void (*set_cs)(struct s3c2410_spi_info *spi,
71 int cs, int pol);
72
73 /* data buffers */
74 const unsigned char *tx;
75 unsigned char *rx;
76
77 struct clk *clk;
78 struct spi_master *master;
79 struct spi_device *curdev;
80 struct device *dev;
81 struct s3c2410_spi_info *pdata;
82};
83
84#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
85#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
86
87static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
88{
89 return spi_master_get_devdata(sdev->master);
90}
91
92static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
93{
94 gpio_set_value(spi->pin_cs, pol);
95}
96
97static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
98{
99 struct s3c24xx_spi_devstate *cs = spi->controller_state;
100 struct s3c24xx_spi *hw = to_hw(spi);
101 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
102
103 /* change the chipselect state and the state of the spi engine clock */
104
105 switch (value) {
106 case BITBANG_CS_INACTIVE:
107 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
108 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
109 break;
110
111 case BITBANG_CS_ACTIVE:
112 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
113 hw->regs + S3C2410_SPCON);
114 hw->set_cs(hw->pdata, spi->chip_select, cspol);
115 break;
116 }
117}
118
119static int s3c24xx_spi_update_state(struct spi_device *spi,
120 struct spi_transfer *t)
121{
122 struct s3c24xx_spi *hw = to_hw(spi);
123 struct s3c24xx_spi_devstate *cs = spi->controller_state;
124 unsigned int hz;
125 unsigned int div;
126 unsigned long clk;
127
128 hz = t ? t->speed_hz : spi->max_speed_hz;
129
130 if (!hz)
131 hz = spi->max_speed_hz;
132
133 if (spi->mode != cs->mode) {
134 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
135
136 if (spi->mode & SPI_CPHA)
137 spcon |= S3C2410_SPCON_CPHA_FMTB;
138
139 if (spi->mode & SPI_CPOL)
140 spcon |= S3C2410_SPCON_CPOL_HIGH;
141
142 cs->mode = spi->mode;
143 cs->spcon = spcon;
144 }
145
146 if (cs->hz != hz) {
147 clk = clk_get_rate(hw->clk);
148 div = DIV_ROUND_UP(clk, hz * 2) - 1;
149
150 if (div > 255)
151 div = 255;
152
153 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
154 div, hz, clk / (2 * (div + 1)));
155
156 cs->hz = hz;
157 cs->sppre = div;
158 }
159
160 return 0;
161}
162
163static int s3c24xx_spi_setupxfer(struct spi_device *spi,
164 struct spi_transfer *t)
165{
166 struct s3c24xx_spi_devstate *cs = spi->controller_state;
167 struct s3c24xx_spi *hw = to_hw(spi);
168 int ret;
169
170 ret = s3c24xx_spi_update_state(spi, t);
171 if (!ret)
172 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
173
174 return ret;
175}
176
177static int s3c24xx_spi_setup(struct spi_device *spi)
178{
179 struct s3c24xx_spi_devstate *cs = spi->controller_state;
180 struct s3c24xx_spi *hw = to_hw(spi);
181 int ret;
182
183 /* allocate settings on the first call */
184 if (!cs) {
185 cs = devm_kzalloc(&spi->dev,
186 sizeof(struct s3c24xx_spi_devstate),
187 GFP_KERNEL);
188 if (!cs)
189 return -ENOMEM;
190
191 cs->spcon = SPCON_DEFAULT;
192 cs->hz = -1;
193 spi->controller_state = cs;
194 }
195
196 /* initialise the state from the device */
197 ret = s3c24xx_spi_update_state(spi, NULL);
198 if (ret)
199 return ret;
200
201 mutex_lock(&hw->bitbang.lock);
202 if (!hw->bitbang.busy) {
203 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
204 /* need to ndelay for 0.5 clocktick ? */
205 }
206 mutex_unlock(&hw->bitbang.lock);
207
208 return 0;
209}
210
211static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
212{
213 return hw->tx ? hw->tx[count] : 0;
214}
215
216#ifdef CONFIG_SPI_S3C24XX_FIQ
217/* Support for FIQ based pseudo-DMA to improve the transfer speed.
218 *
219 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
220 * used by the FIQ core to move data between main memory and the peripheral
221 * block. Since this is code running on the processor, there is no problem
222 * with cache coherency of the buffers, so we can use any buffer we like.
223 */
224
225/**
226 * struct spi_fiq_code - FIQ code and header
227 * @length: The length of the code fragment, excluding this header.
228 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
229 * @data: The code itself to install as a FIQ handler.
230 */
231struct spi_fiq_code {
232 u32 length;
233 u32 ack_offset;
234 u8 data[0];
235};
236
237extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
238extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
239extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
240
241/**
242 * ack_bit - turn IRQ into IRQ acknowledgement bit
243 * @irq: The interrupt number
244 *
245 * Returns the bit to write to the interrupt acknowledge register.
246 */
247static inline u32 ack_bit(unsigned int irq)
248{
249 return 1 << (irq - IRQ_EINT0);
250}
251
252/**
253 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
254 * @hw: The hardware state.
255 *
256 * Claim the FIQ handler (only one can be active at any one time) and
257 * then setup the correct transfer code for this transfer.
258 *
259 * This call updates all the necessary state information if successful,
260 * so the caller does not need to do anything more than start the transfer
261 * as normal, since the IRQ will have been re-routed to the FIQ handler.
262*/
263static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
264{
265 struct pt_regs regs;
266 enum spi_fiq_mode mode;
267 struct spi_fiq_code *code;
268 int ret;
269
270 if (!hw->fiq_claimed) {
271 /* try and claim fiq if we haven't got it, and if not
272 * then return and simply use another transfer method */
273
274 ret = claim_fiq(&hw->fiq_handler);
275 if (ret)
276 return;
277 }
278
279 if (hw->tx && !hw->rx)
280 mode = FIQ_MODE_TX;
281 else if (hw->rx && !hw->tx)
282 mode = FIQ_MODE_RX;
283 else
284 mode = FIQ_MODE_TXRX;
285
286 regs.uregs[fiq_rspi] = (long)hw->regs;
287 regs.uregs[fiq_rrx] = (long)hw->rx;
288 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
289 regs.uregs[fiq_rcount] = hw->len - 1;
290 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
291
292 set_fiq_regs(®s);
293
294 if (hw->fiq_mode != mode) {
295 u32 *ack_ptr;
296
297 hw->fiq_mode = mode;
298
299 switch (mode) {
300 case FIQ_MODE_TX:
301 code = &s3c24xx_spi_fiq_tx;
302 break;
303 case FIQ_MODE_RX:
304 code = &s3c24xx_spi_fiq_rx;
305 break;
306 case FIQ_MODE_TXRX:
307 code = &s3c24xx_spi_fiq_txrx;
308 break;
309 default:
310 code = NULL;
311 }
312
313 BUG_ON(!code);
314
315 ack_ptr = (u32 *)&code->data[code->ack_offset];
316 *ack_ptr = ack_bit(hw->irq);
317
318 set_fiq_handler(&code->data, code->length);
319 }
320
321 s3c24xx_set_fiq(hw->irq, true);
322
323 hw->fiq_mode = mode;
324 hw->fiq_inuse = 1;
325}
326
327/**
328 * s3c24xx_spi_fiqop - FIQ core code callback
329 * @pw: Data registered with the handler
330 * @release: Whether this is a release or a return.
331 *
332 * Called by the FIQ code when another module wants to use the FIQ, so
333 * return whether we are currently using this or not and then update our
334 * internal state.
335 */
336static int s3c24xx_spi_fiqop(void *pw, int release)
337{
338 struct s3c24xx_spi *hw = pw;
339 int ret = 0;
340
341 if (release) {
342 if (hw->fiq_inuse)
343 ret = -EBUSY;
344
345 /* note, we do not need to unroute the FIQ, as the FIQ
346 * vector code de-routes it to signal the end of transfer */
347
348 hw->fiq_mode = FIQ_MODE_NONE;
349 hw->fiq_claimed = 0;
350 } else {
351 hw->fiq_claimed = 1;
352 }
353
354 return ret;
355}
356
357/**
358 * s3c24xx_spi_initfiq - setup the information for the FIQ core
359 * @hw: The hardware state.
360 *
361 * Setup the fiq_handler block to pass to the FIQ core.
362 */
363static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
364{
365 hw->fiq_handler.dev_id = hw;
366 hw->fiq_handler.name = dev_name(hw->dev);
367 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
368}
369
370/**
371 * s3c24xx_spi_usefiq - return if we should be using FIQ.
372 * @hw: The hardware state.
373 *
374 * Return true if the platform data specifies whether this channel is
375 * allowed to use the FIQ.
376 */
377static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
378{
379 return hw->pdata->use_fiq;
380}
381
382/**
383 * s3c24xx_spi_usingfiq - return if channel is using FIQ
384 * @spi: The hardware state.
385 *
386 * Return whether the channel is currently using the FIQ (separate from
387 * whether the FIQ is claimed).
388 */
389static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
390{
391 return spi->fiq_inuse;
392}
393#else
394
395static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
396static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
397static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
398static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
399
400#endif /* CONFIG_SPI_S3C24XX_FIQ */
401
402static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
403{
404 struct s3c24xx_spi *hw = to_hw(spi);
405
406 hw->tx = t->tx_buf;
407 hw->rx = t->rx_buf;
408 hw->len = t->len;
409 hw->count = 0;
410
411 init_completion(&hw->done);
412
413 hw->fiq_inuse = 0;
414 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
415 s3c24xx_spi_tryfiq(hw);
416
417 /* send the first byte */
418 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
419
420 wait_for_completion(&hw->done);
421 return hw->count;
422}
423
424static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
425{
426 struct s3c24xx_spi *hw = dev;
427 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
428 unsigned int count = hw->count;
429
430 if (spsta & S3C2410_SPSTA_DCOL) {
431 dev_dbg(hw->dev, "data-collision\n");
432 complete(&hw->done);
433 goto irq_done;
434 }
435
436 if (!(spsta & S3C2410_SPSTA_READY)) {
437 dev_dbg(hw->dev, "spi not ready for tx?\n");
438 complete(&hw->done);
439 goto irq_done;
440 }
441
442 if (!s3c24xx_spi_usingfiq(hw)) {
443 hw->count++;
444
445 if (hw->rx)
446 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
447
448 count++;
449
450 if (count < hw->len)
451 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
452 else
453 complete(&hw->done);
454 } else {
455 hw->count = hw->len;
456 hw->fiq_inuse = 0;
457
458 if (hw->rx)
459 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
460
461 complete(&hw->done);
462 }
463
464 irq_done:
465 return IRQ_HANDLED;
466}
467
468static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
469{
470 /* for the moment, permanently enable the clock */
471
472 clk_enable(hw->clk);
473
474 /* program defaults into the registers */
475
476 writeb(0xff, hw->regs + S3C2410_SPPRE);
477 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
478 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
479
480 if (hw->pdata) {
481 if (hw->set_cs == s3c24xx_spi_gpiocs)
482 gpio_direction_output(hw->pdata->pin_cs, 1);
483
484 if (hw->pdata->gpio_setup)
485 hw->pdata->gpio_setup(hw->pdata, 1);
486 }
487}
488
489static int s3c24xx_spi_probe(struct platform_device *pdev)
490{
491 struct s3c2410_spi_info *pdata;
492 struct s3c24xx_spi *hw;
493 struct spi_master *master;
494 struct resource *res;
495 int err = 0;
496
497 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
498 if (master == NULL) {
499 dev_err(&pdev->dev, "No memory for spi_master\n");
500 return -ENOMEM;
501 }
502
503 hw = spi_master_get_devdata(master);
504
505 hw->master = master;
506 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
507 hw->dev = &pdev->dev;
508
509 if (pdata == NULL) {
510 dev_err(&pdev->dev, "No platform data supplied\n");
511 err = -ENOENT;
512 goto err_no_pdata;
513 }
514
515 platform_set_drvdata(pdev, hw);
516 init_completion(&hw->done);
517
518 /* initialise fiq handler */
519
520 s3c24xx_spi_initfiq(hw);
521
522 /* setup the master state. */
523
524 /* the spi->mode bits understood by this driver: */
525 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
526
527 master->num_chipselect = hw->pdata->num_cs;
528 master->bus_num = pdata->bus_num;
529 master->bits_per_word_mask = SPI_BPW_MASK(8);
530
531 /* setup the state for the bitbang driver */
532
533 hw->bitbang.master = hw->master;
534 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
535 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
536 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
537
538 hw->master->setup = s3c24xx_spi_setup;
539
540 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
541
542 /* find and map our resources */
543 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
544 hw->regs = devm_ioremap_resource(&pdev->dev, res);
545 if (IS_ERR(hw->regs)) {
546 err = PTR_ERR(hw->regs);
547 goto err_no_pdata;
548 }
549
550 hw->irq = platform_get_irq(pdev, 0);
551 if (hw->irq < 0) {
552 dev_err(&pdev->dev, "No IRQ specified\n");
553 err = -ENOENT;
554 goto err_no_pdata;
555 }
556
557 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
558 pdev->name, hw);
559 if (err) {
560 dev_err(&pdev->dev, "Cannot claim IRQ\n");
561 goto err_no_pdata;
562 }
563
564 hw->clk = devm_clk_get(&pdev->dev, "spi");
565 if (IS_ERR(hw->clk)) {
566 dev_err(&pdev->dev, "No clock for device\n");
567 err = PTR_ERR(hw->clk);
568 goto err_no_pdata;
569 }
570
571 /* setup any gpio we can */
572
573 if (!pdata->set_cs) {
574 if (pdata->pin_cs < 0) {
575 dev_err(&pdev->dev, "No chipselect pin\n");
576 err = -EINVAL;
577 goto err_register;
578 }
579
580 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
581 dev_name(&pdev->dev));
582 if (err) {
583 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
584 goto err_register;
585 }
586
587 hw->set_cs = s3c24xx_spi_gpiocs;
588 gpio_direction_output(pdata->pin_cs, 1);
589 } else
590 hw->set_cs = pdata->set_cs;
591
592 s3c24xx_spi_initialsetup(hw);
593
594 /* register our spi controller */
595
596 err = spi_bitbang_start(&hw->bitbang);
597 if (err) {
598 dev_err(&pdev->dev, "Failed to register SPI master\n");
599 goto err_register;
600 }
601
602 return 0;
603
604 err_register:
605 clk_disable(hw->clk);
606
607 err_no_pdata:
608 spi_master_put(hw->master);
609 return err;
610}
611
612static int s3c24xx_spi_remove(struct platform_device *dev)
613{
614 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
615
616 spi_bitbang_stop(&hw->bitbang);
617 clk_disable(hw->clk);
618 spi_master_put(hw->master);
619 return 0;
620}
621
622
623#ifdef CONFIG_PM
624
625static int s3c24xx_spi_suspend(struct device *dev)
626{
627 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
628 int ret;
629
630 ret = spi_master_suspend(hw->master);
631 if (ret)
632 return ret;
633
634 if (hw->pdata && hw->pdata->gpio_setup)
635 hw->pdata->gpio_setup(hw->pdata, 0);
636
637 clk_disable(hw->clk);
638 return 0;
639}
640
641static int s3c24xx_spi_resume(struct device *dev)
642{
643 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
644
645 s3c24xx_spi_initialsetup(hw);
646 return spi_master_resume(hw->master);
647}
648
649static const struct dev_pm_ops s3c24xx_spi_pmops = {
650 .suspend = s3c24xx_spi_suspend,
651 .resume = s3c24xx_spi_resume,
652};
653
654#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
655#else
656#define S3C24XX_SPI_PMOPS NULL
657#endif /* CONFIG_PM */
658
659MODULE_ALIAS("platform:s3c2410-spi");
660static struct platform_driver s3c24xx_spi_driver = {
661 .probe = s3c24xx_spi_probe,
662 .remove = s3c24xx_spi_remove,
663 .driver = {
664 .name = "s3c2410-spi",
665 .pm = S3C24XX_SPI_PMOPS,
666 },
667};
668module_platform_driver(s3c24xx_spi_driver);
669
670MODULE_DESCRIPTION("S3C24XX SPI Driver");
671MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
672MODULE_LICENSE("GPL");