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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 BayHub Technology Ltd.
4 *
5 * Authors: Peter Guo <peter.guo@bayhubtech.com>
6 * Adam Lee <adam.lee@canonical.com>
7 * Ernest Zhang <ernest.zhang@bayhubtech.com>
8 */
9
10#include <linux/pci.h>
11#include <linux/mmc/host.h>
12#include <linux/mmc/mmc.h>
13#include <linux/delay.h>
14#include <linux/iopoll.h>
15#include <linux/bitfield.h>
16
17#include "sdhci.h"
18#include "sdhci-pci.h"
19
20/*
21 * O2Micro device registers
22 */
23
24#define O2_SD_MISC_REG5 0x64
25#define O2_SD_LD0_CTRL 0x68
26#define O2_SD_DEV_CTRL 0x88
27#define O2_SD_LOCK_WP 0xD3
28#define O2_SD_TEST_REG 0xD4
29#define O2_SD_FUNC_REG0 0xDC
30#define O2_SD_MULTI_VCC3V 0xEE
31#define O2_SD_CLKREQ 0xEC
32#define O2_SD_CAPS 0xE0
33#define O2_SD_ADMA1 0xE2
34#define O2_SD_ADMA2 0xE7
35#define O2_SD_MISC_CTRL2 0xF0
36#define O2_SD_INF_MOD 0xF1
37#define O2_SD_MISC_CTRL4 0xFC
38#define O2_SD_MISC_CTRL 0x1C0
39#define O2_SD_PWR_FORCE_L0 0x0002
40#define O2_SD_TUNING_CTRL 0x300
41#define O2_SD_PLL_SETTING 0x304
42#define O2_SD_MISC_SETTING 0x308
43#define O2_SD_CLK_SETTING 0x328
44#define O2_SD_CAP_REG2 0x330
45#define O2_SD_CAP_REG0 0x334
46#define O2_SD_UHS1_CAP_SETTING 0x33C
47#define O2_SD_DELAY_CTRL 0x350
48#define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354
49#define O2_SD_UHS2_L1_CTRL 0x35C
50#define O2_SD_FUNC_REG3 0x3E0
51#define O2_SD_FUNC_REG4 0x3E4
52#define O2_SD_LED_ENABLE BIT(6)
53#define O2_SD_FREG0_LEDOFF BIT(13)
54#define O2_SD_SEL_DLL BIT(16)
55#define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
56#define O2_SD_PHASE_MASK GENMASK(23, 20)
57#define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9)
58
59#define O2_SD_VENDOR_SETTING 0x110
60#define O2_SD_VENDOR_SETTING2 0x1C8
61#define O2_SD_HW_TUNING_DISABLE BIT(4)
62
63#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
64#define O2_PLL_FORCE_ACTIVE BIT(18)
65#define O2_PLL_LOCK_STATUS BIT(14)
66#define O2_PLL_SOFT_RESET BIT(12)
67#define O2_DLL_LOCK_STATUS BIT(11)
68
69#define O2_SD_DETECT_SETTING 0x324
70
71static const u32 dmdn_table[] = {0x2B1C0000,
72 0x2C1A0000, 0x371B0000, 0x35100000};
73#define DMDN_SZ ARRAY_SIZE(dmdn_table)
74
75struct o2_host {
76 u8 dll_adjust_count;
77};
78
79static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
80{
81 ktime_t timeout;
82 u32 scratch32;
83
84 /* Wait max 50 ms */
85 timeout = ktime_add_ms(ktime_get(), 50);
86 while (1) {
87 bool timedout = ktime_after(ktime_get(), timeout);
88
89 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
90 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
91 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
92 break;
93
94 if (timedout) {
95 pr_err("%s: Card Detect debounce never finished.\n",
96 mmc_hostname(host->mmc));
97 sdhci_dumpregs(host);
98 return;
99 }
100 udelay(10);
101 }
102}
103
104static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
105{
106 ktime_t timeout;
107 u16 scratch;
108 u32 scratch32;
109
110 /* PLL software reset */
111 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
112 scratch32 |= O2_PLL_SOFT_RESET;
113 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
114 udelay(1);
115 scratch32 &= ~(O2_PLL_SOFT_RESET);
116 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
117
118 /* PLL force active */
119 scratch32 |= O2_PLL_FORCE_ACTIVE;
120 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
121
122 /* Wait max 20 ms */
123 timeout = ktime_add_ms(ktime_get(), 20);
124 while (1) {
125 bool timedout = ktime_after(ktime_get(), timeout);
126
127 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
128 if (scratch & O2_PLL_LOCK_STATUS)
129 break;
130 if (timedout) {
131 pr_err("%s: Internal clock never stabilised.\n",
132 mmc_hostname(host->mmc));
133 sdhci_dumpregs(host);
134 goto out;
135 }
136 udelay(10);
137 }
138
139 /* Wait for card detect finish */
140 udelay(1);
141 sdhci_o2_wait_card_detect_stable(host);
142
143out:
144 /* Cancel PLL force active */
145 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
146 scratch32 &= ~O2_PLL_FORCE_ACTIVE;
147 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
148}
149
150static int sdhci_o2_get_cd(struct mmc_host *mmc)
151{
152 struct sdhci_host *host = mmc_priv(mmc);
153
154 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
155 sdhci_o2_enable_internal_clock(host);
156 else
157 sdhci_o2_wait_card_detect_stable(host);
158
159 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
160}
161
162static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
163{
164 u32 scratch_32;
165
166 pci_read_config_dword(chip->pdev,
167 O2_SD_PLL_SETTING, &scratch_32);
168
169 scratch_32 &= 0x0000FFFF;
170 scratch_32 |= value;
171
172 pci_write_config_dword(chip->pdev,
173 O2_SD_PLL_SETTING, scratch_32);
174}
175
176static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
177{
178 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
179}
180
181/*
182 * This function is used to detect dll lock status.
183 * Since the dll lock status bit will toggle randomly
184 * with very short interval which needs to be polled
185 * as fast as possible. Set sleep_us as 1 microsecond.
186 */
187static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
188{
189 u32 scratch32 = 0;
190
191 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
192 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
193}
194
195static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
196{
197 u16 reg;
198
199 /* enable hardware tuning */
200 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
201 reg &= ~O2_SD_HW_TUNING_DISABLE;
202 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
203}
204
205static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
206{
207 int i;
208
209 sdhci_send_tuning(host, opcode);
210
211 for (i = 0; i < 150; i++) {
212 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
213
214 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
215 if (ctrl & SDHCI_CTRL_TUNED_CLK) {
216 host->tuning_done = true;
217 return;
218 }
219 pr_warn("%s: HW tuning failed !\n",
220 mmc_hostname(host->mmc));
221 break;
222 }
223
224 mdelay(1);
225 }
226
227 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
228 mmc_hostname(host->mmc));
229 sdhci_reset_tuning(host);
230}
231
232/*
233 * This function is used to fix o2 dll shift issue.
234 * It isn't necessary to detect card present before recovery.
235 * Firstly, it is used by bht emmc card, which is embedded.
236 * Second, before call recovery card present will be detected
237 * outside of the execute tuning function.
238 */
239static int sdhci_o2_dll_recovery(struct sdhci_host *host)
240{
241 int ret = 0;
242 u8 scratch_8 = 0;
243 u32 scratch_32 = 0;
244 struct sdhci_pci_slot *slot = sdhci_priv(host);
245 struct sdhci_pci_chip *chip = slot->chip;
246 struct o2_host *o2_host = sdhci_pci_priv(slot);
247
248 /* UnLock WP */
249 pci_read_config_byte(chip->pdev,
250 O2_SD_LOCK_WP, &scratch_8);
251 scratch_8 &= 0x7f;
252 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
253 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
254 /* Disable clock */
255 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
256
257 /* PLL software reset */
258 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
259 scratch_32 |= O2_PLL_SOFT_RESET;
260 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
261
262 pci_read_config_dword(chip->pdev,
263 O2_SD_FUNC_REG4,
264 &scratch_32);
265 /* Enable Base Clk setting change */
266 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
267 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
268 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
269
270 /* Enable internal clock */
271 scratch_8 = SDHCI_CLOCK_INT_EN;
272 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
273
274 if (sdhci_o2_get_cd(host->mmc)) {
275 /*
276 * need wait at least 5ms for dll status stable,
277 * after enable internal clock
278 */
279 usleep_range(5000, 6000);
280 if (sdhci_o2_wait_dll_detect_lock(host)) {
281 scratch_8 |= SDHCI_CLOCK_CARD_EN;
282 sdhci_writeb(host, scratch_8,
283 SDHCI_CLOCK_CONTROL);
284 ret = 1;
285 } else {
286 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
287 mmc_hostname(host->mmc),
288 o2_host->dll_adjust_count);
289 }
290 } else {
291 pr_err("%s: card present detect failed.\n",
292 mmc_hostname(host->mmc));
293 break;
294 }
295
296 o2_host->dll_adjust_count++;
297 }
298 if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
299 pr_err("%s: DLL adjust over max times\n",
300 mmc_hostname(host->mmc));
301 /* Lock WP */
302 pci_read_config_byte(chip->pdev,
303 O2_SD_LOCK_WP, &scratch_8);
304 scratch_8 |= 0x80;
305 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
306 return ret;
307}
308
309static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
310{
311 struct sdhci_host *host = mmc_priv(mmc);
312 struct sdhci_pci_slot *slot = sdhci_priv(host);
313 struct sdhci_pci_chip *chip = slot->chip;
314 int current_bus_width = 0;
315 u32 scratch32 = 0;
316 u16 scratch = 0;
317 u8 scratch_8 = 0;
318 u32 reg_val;
319
320 /*
321 * This handler implements the hardware tuning that is specific to
322 * this controller. Fall back to the standard method for other TIMING.
323 */
324 if ((host->timing != MMC_TIMING_MMC_HS200) &&
325 (host->timing != MMC_TIMING_UHS_SDR104) &&
326 (host->timing != MMC_TIMING_UHS_SDR50))
327 return sdhci_execute_tuning(mmc, opcode);
328
329 if (WARN_ON(!mmc_op_tuning(opcode)))
330 return -EINVAL;
331
332 /* Force power mode enter L0 */
333 scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
334 scratch |= O2_SD_PWR_FORCE_L0;
335 sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
336
337 /* Stop clk */
338 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
339 reg_val &= ~SDHCI_CLOCK_CARD_EN;
340 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
341
342 /* UnLock WP */
343 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
344 scratch_8 &= 0x7f;
345 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
346
347 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
348 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val);
349 reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
350 reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
351 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
352
353 /* Lock WP */
354 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
355 scratch_8 |= 0x80;
356 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
357
358 /* Start clk */
359 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
360 reg_val |= SDHCI_CLOCK_CARD_EN;
361 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
362
363 /* wait DLL lock, timeout value 5ms */
364 if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
365 scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
366 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
367 mmc_hostname(host->mmc));
368 /*
369 * Judge the tuning reason, whether caused by dll shift
370 * If cause by dll shift, should call sdhci_o2_dll_recovery
371 */
372 if (!sdhci_o2_wait_dll_detect_lock(host))
373 if (!sdhci_o2_dll_recovery(host)) {
374 pr_err("%s: o2 dll recovery failed\n",
375 mmc_hostname(host->mmc));
376 return -EINVAL;
377 }
378 /*
379 * o2 sdhci host didn't support 8bit emmc tuning
380 */
381 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
382 current_bus_width = mmc->ios.bus_width;
383 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
384 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
385 }
386
387 sdhci_o2_set_tuning_mode(host);
388
389 sdhci_start_tuning(host);
390
391 __sdhci_o2_execute_tuning(host, opcode);
392
393 sdhci_end_tuning(host);
394
395 if (current_bus_width == MMC_BUS_WIDTH_8) {
396 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
397 sdhci_set_bus_width(host, current_bus_width);
398 }
399
400 /* Cancel force power mode enter L0 */
401 scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
402 scratch &= ~(O2_SD_PWR_FORCE_L0);
403 sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
404
405 sdhci_reset(host, SDHCI_RESET_CMD);
406 sdhci_reset(host, SDHCI_RESET_DATA);
407
408 host->flags &= ~SDHCI_HS400_TUNING;
409 return 0;
410}
411
412static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
413{
414 int ret;
415 u32 scratch_32;
416
417 /* Set led of SD host function enable */
418 ret = pci_read_config_dword(chip->pdev,
419 O2_SD_FUNC_REG0, &scratch_32);
420 if (ret)
421 return;
422
423 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
424 pci_write_config_dword(chip->pdev,
425 O2_SD_FUNC_REG0, scratch_32);
426
427 ret = pci_read_config_dword(chip->pdev,
428 O2_SD_TEST_REG, &scratch_32);
429 if (ret)
430 return;
431
432 scratch_32 |= O2_SD_LED_ENABLE;
433 pci_write_config_dword(chip->pdev,
434 O2_SD_TEST_REG, scratch_32);
435}
436
437static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
438{
439 u32 scratch_32;
440 int ret;
441 /* Improve write performance for SD3.0 */
442 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
443 if (ret)
444 return;
445 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
446 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
447
448 /* Enable Link abnormal reset generating Reset */
449 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
450 if (ret)
451 return;
452 scratch_32 &= ~((1 << 19) | (1 << 11));
453 scratch_32 |= (1 << 10);
454 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
455
456 /* set card power over current protection */
457 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
458 if (ret)
459 return;
460 scratch_32 |= (1 << 4);
461 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
462
463 /* adjust the output delay for SD mode */
464 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
465
466 /* Set the output voltage setting of Aux 1.2v LDO */
467 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
468 if (ret)
469 return;
470 scratch_32 &= ~(3 << 12);
471 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
472
473 /* Set Max power supply capability of SD host */
474 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
475 if (ret)
476 return;
477 scratch_32 &= ~(0x01FE);
478 scratch_32 |= 0x00CC;
479 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
480 /* Set DLL Tuning Window */
481 ret = pci_read_config_dword(chip->pdev,
482 O2_SD_TUNING_CTRL, &scratch_32);
483 if (ret)
484 return;
485 scratch_32 &= ~(0x000000FF);
486 scratch_32 |= 0x00000066;
487 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
488
489 /* Set UHS2 T_EIDLE */
490 ret = pci_read_config_dword(chip->pdev,
491 O2_SD_UHS2_L1_CTRL, &scratch_32);
492 if (ret)
493 return;
494 scratch_32 &= ~(0x000000FC);
495 scratch_32 |= 0x00000084;
496 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
497
498 /* Set UHS2 Termination */
499 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
500 if (ret)
501 return;
502 scratch_32 &= ~((1 << 21) | (1 << 30));
503
504 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
505
506 /* Set L1 Entrance Timer */
507 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
508 if (ret)
509 return;
510 scratch_32 &= ~(0xf0000000);
511 scratch_32 |= 0x30000000;
512 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
513
514 ret = pci_read_config_dword(chip->pdev,
515 O2_SD_MISC_CTRL4, &scratch_32);
516 if (ret)
517 return;
518 scratch_32 &= ~(0x000f0000);
519 scratch_32 |= 0x00080000;
520 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
521}
522
523static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
524 struct sdhci_host *host)
525{
526 int ret;
527
528 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
529 if (!ret) {
530 pr_info("%s: unsupported MSI, use INTx irq\n",
531 mmc_hostname(host->mmc));
532 return;
533 }
534
535 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
536 PCI_IRQ_MSI | PCI_IRQ_MSIX);
537 if (ret < 0) {
538 pr_err("%s: enable PCI MSI failed, err=%d\n",
539 mmc_hostname(host->mmc), ret);
540 return;
541 }
542
543 host->irq = pci_irq_vector(chip->pdev, 0);
544}
545
546static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
547{
548 /* Enable internal clock */
549 clk |= SDHCI_CLOCK_INT_EN;
550 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
551
552 sdhci_o2_enable_internal_clock(host);
553 if (sdhci_o2_get_cd(host->mmc)) {
554 clk |= SDHCI_CLOCK_CARD_EN;
555 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
556 }
557}
558
559static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
560{
561 u16 clk;
562 u8 scratch;
563 u32 scratch_32;
564 struct sdhci_pci_slot *slot = sdhci_priv(host);
565 struct sdhci_pci_chip *chip = slot->chip;
566
567 host->mmc->actual_clock = 0;
568
569 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
570
571 if (clock == 0)
572 return;
573
574 /* UnLock WP */
575 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
576 scratch &= 0x7f;
577 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
578
579 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
580 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
581
582 if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
583 o2_pci_set_baseclk(chip, 0x2c280000);
584 } else {
585 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
586
587 if ((scratch_32 & 0xFFFF0000) != 0x25100000)
588 o2_pci_set_baseclk(chip, 0x25100000);
589 }
590
591 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);
592 scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
593 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);
594
595 /* Lock WP */
596 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
597 scratch |= 0x80;
598 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
599
600 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
601 sdhci_o2_enable_clk(host, clk);
602}
603
604static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
605{
606 struct sdhci_pci_chip *chip;
607 struct sdhci_host *host;
608 struct o2_host *o2_host = sdhci_pci_priv(slot);
609 u32 reg, caps;
610 int ret;
611
612 chip = slot->chip;
613 host = slot->host;
614
615 o2_host->dll_adjust_count = 0;
616 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
617
618 /*
619 * mmc_select_bus_width() will test the bus to determine the actual bus
620 * width.
621 */
622 if (caps & SDHCI_CAN_DO_8BIT)
623 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
624
625 switch (chip->pdev->device) {
626 case PCI_DEVICE_ID_O2_SDS0:
627 case PCI_DEVICE_ID_O2_SEABIRD0:
628 case PCI_DEVICE_ID_O2_SEABIRD1:
629 case PCI_DEVICE_ID_O2_SDS1:
630 case PCI_DEVICE_ID_O2_FUJIN2:
631 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
632 if (reg & 0x1)
633 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
634
635 host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
636
637 sdhci_pci_o2_enable_msi(chip, host);
638
639 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
640 ret = pci_read_config_dword(chip->pdev,
641 O2_SD_MISC_SETTING, ®);
642 if (ret)
643 return -EIO;
644 if (reg & (1 << 4)) {
645 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
646 mmc_hostname(host->mmc));
647 host->flags &= ~SDHCI_SIGNALING_330;
648 host->flags |= SDHCI_SIGNALING_180;
649 host->mmc->caps2 |= MMC_CAP2_NO_SD;
650 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
651 pci_write_config_dword(chip->pdev,
652 O2_SD_DETECT_SETTING, 3);
653 }
654
655 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
656 }
657
658 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
659 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
660 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
661 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
662 }
663
664 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
665
666 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
667 break;
668 /* set dll watch dog timer */
669 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
670 reg |= (1 << 12);
671 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
672
673 break;
674 default:
675 break;
676 }
677
678 return 0;
679}
680
681static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
682{
683 int ret;
684 u8 scratch;
685 u32 scratch_32;
686
687 switch (chip->pdev->device) {
688 case PCI_DEVICE_ID_O2_8220:
689 case PCI_DEVICE_ID_O2_8221:
690 case PCI_DEVICE_ID_O2_8320:
691 case PCI_DEVICE_ID_O2_8321:
692 /* This extra setup is required due to broken ADMA. */
693 ret = pci_read_config_byte(chip->pdev,
694 O2_SD_LOCK_WP, &scratch);
695 if (ret)
696 return ret;
697 scratch &= 0x7f;
698 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
699
700 /* Set Multi 3 to VCC3V# */
701 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
702
703 /* Disable CLK_REQ# support after media DET */
704 ret = pci_read_config_byte(chip->pdev,
705 O2_SD_CLKREQ, &scratch);
706 if (ret)
707 return ret;
708 scratch |= 0x20;
709 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
710
711 /* Choose capabilities, enable SDMA. We have to write 0x01
712 * to the capabilities register first to unlock it.
713 */
714 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
715 if (ret)
716 return ret;
717 scratch |= 0x01;
718 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
719 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
720
721 /* Disable ADMA1/2 */
722 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
723 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
724
725 /* Disable the infinite transfer mode */
726 ret = pci_read_config_byte(chip->pdev,
727 O2_SD_INF_MOD, &scratch);
728 if (ret)
729 return ret;
730 scratch |= 0x08;
731 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
732
733 /* Lock WP */
734 ret = pci_read_config_byte(chip->pdev,
735 O2_SD_LOCK_WP, &scratch);
736 if (ret)
737 return ret;
738 scratch |= 0x80;
739 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
740 break;
741 case PCI_DEVICE_ID_O2_SDS0:
742 case PCI_DEVICE_ID_O2_SDS1:
743 case PCI_DEVICE_ID_O2_FUJIN2:
744 /* UnLock WP */
745 ret = pci_read_config_byte(chip->pdev,
746 O2_SD_LOCK_WP, &scratch);
747 if (ret)
748 return ret;
749
750 scratch &= 0x7f;
751 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
752
753 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
754 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
755 ret = pci_read_config_dword(chip->pdev,
756 O2_SD_FUNC_REG0,
757 &scratch_32);
758 if (ret)
759 return ret;
760 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
761
762 /* Check Whether subId is 0x11 or 0x12 */
763 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
764 scratch_32 = 0x25100000;
765
766 o2_pci_set_baseclk(chip, scratch_32);
767 ret = pci_read_config_dword(chip->pdev,
768 O2_SD_FUNC_REG4,
769 &scratch_32);
770 if (ret)
771 return ret;
772
773 /* Enable Base Clk setting change */
774 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
775 pci_write_config_dword(chip->pdev,
776 O2_SD_FUNC_REG4,
777 scratch_32);
778
779 /* Set Tuning Window to 4 */
780 pci_write_config_byte(chip->pdev,
781 O2_SD_TUNING_CTRL, 0x44);
782
783 break;
784 }
785 }
786
787 /* Enable 8520 led function */
788 o2_pci_led_enable(chip);
789
790 /* Set timeout CLK */
791 ret = pci_read_config_dword(chip->pdev,
792 O2_SD_CLK_SETTING, &scratch_32);
793 if (ret)
794 return ret;
795
796 scratch_32 &= ~(0xFF00);
797 scratch_32 |= 0x07E0C800;
798 pci_write_config_dword(chip->pdev,
799 O2_SD_CLK_SETTING, scratch_32);
800
801 ret = pci_read_config_dword(chip->pdev,
802 O2_SD_CLKREQ, &scratch_32);
803 if (ret)
804 return ret;
805 scratch_32 |= 0x3;
806 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
807
808 ret = pci_read_config_dword(chip->pdev,
809 O2_SD_PLL_SETTING, &scratch_32);
810 if (ret)
811 return ret;
812
813 scratch_32 &= ~(0x1F3F070E);
814 scratch_32 |= 0x18270106;
815 pci_write_config_dword(chip->pdev,
816 O2_SD_PLL_SETTING, scratch_32);
817
818 /* Disable UHS1 funciton */
819 ret = pci_read_config_dword(chip->pdev,
820 O2_SD_CAP_REG2, &scratch_32);
821 if (ret)
822 return ret;
823 scratch_32 &= ~(0xE0);
824 pci_write_config_dword(chip->pdev,
825 O2_SD_CAP_REG2, scratch_32);
826
827 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
828 sdhci_pci_o2_fujin2_pci_init(chip);
829
830 /* Lock WP */
831 ret = pci_read_config_byte(chip->pdev,
832 O2_SD_LOCK_WP, &scratch);
833 if (ret)
834 return ret;
835 scratch |= 0x80;
836 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
837 break;
838 case PCI_DEVICE_ID_O2_SEABIRD0:
839 case PCI_DEVICE_ID_O2_SEABIRD1:
840 /* UnLock WP */
841 ret = pci_read_config_byte(chip->pdev,
842 O2_SD_LOCK_WP, &scratch);
843 if (ret)
844 return ret;
845
846 scratch &= 0x7f;
847 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
848
849 ret = pci_read_config_dword(chip->pdev,
850 O2_SD_PLL_SETTING, &scratch_32);
851 if (ret)
852 return ret;
853
854 if ((scratch_32 & 0xff000000) == 0x01000000) {
855 scratch_32 &= 0x0000FFFF;
856 scratch_32 |= 0x1F340000;
857
858 pci_write_config_dword(chip->pdev,
859 O2_SD_PLL_SETTING, scratch_32);
860 } else {
861 scratch_32 &= 0x0000FFFF;
862 scratch_32 |= 0x25100000;
863
864 pci_write_config_dword(chip->pdev,
865 O2_SD_PLL_SETTING, scratch_32);
866
867 ret = pci_read_config_dword(chip->pdev,
868 O2_SD_FUNC_REG4,
869 &scratch_32);
870 if (ret)
871 return ret;
872 scratch_32 |= (1 << 22);
873 pci_write_config_dword(chip->pdev,
874 O2_SD_FUNC_REG4, scratch_32);
875 }
876
877 /* Set Tuning Windows to 5 */
878 pci_write_config_byte(chip->pdev,
879 O2_SD_TUNING_CTRL, 0x55);
880 //Adjust 1st and 2nd CD debounce time
881 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
882 scratch_32 &= 0xFFE7FFFF;
883 scratch_32 |= 0x00180000;
884 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);
885 pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1);
886 /* Lock WP */
887 ret = pci_read_config_byte(chip->pdev,
888 O2_SD_LOCK_WP, &scratch);
889 if (ret)
890 return ret;
891 scratch |= 0x80;
892 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
893 break;
894 }
895
896 return 0;
897}
898
899#ifdef CONFIG_PM_SLEEP
900static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
901{
902 sdhci_pci_o2_probe(chip);
903 return sdhci_pci_resume_host(chip);
904}
905#endif
906
907static const struct sdhci_ops sdhci_pci_o2_ops = {
908 .set_clock = sdhci_pci_o2_set_clock,
909 .enable_dma = sdhci_pci_enable_dma,
910 .set_bus_width = sdhci_set_bus_width,
911 .reset = sdhci_reset,
912 .set_uhs_signaling = sdhci_set_uhs_signaling,
913};
914
915const struct sdhci_pci_fixes sdhci_o2 = {
916 .probe = sdhci_pci_o2_probe,
917 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
918 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
919 .probe_slot = sdhci_pci_o2_probe_slot,
920#ifdef CONFIG_PM_SLEEP
921 .resume = sdhci_pci_o2_resume,
922#endif
923 .ops = &sdhci_pci_o2_ops,
924 .priv_size = sizeof(struct o2_host),
925};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 BayHub Technology Ltd.
4 *
5 * Authors: Peter Guo <peter.guo@bayhubtech.com>
6 * Adam Lee <adam.lee@canonical.com>
7 * Ernest Zhang <ernest.zhang@bayhubtech.com>
8 */
9
10#include <linux/pci.h>
11#include <linux/mmc/host.h>
12#include <linux/mmc/mmc.h>
13#include <linux/delay.h>
14#include <linux/iopoll.h>
15
16#include "sdhci.h"
17#include "sdhci-pci.h"
18
19/*
20 * O2Micro device registers
21 */
22
23#define O2_SD_MISC_REG5 0x64
24#define O2_SD_LD0_CTRL 0x68
25#define O2_SD_DEV_CTRL 0x88
26#define O2_SD_LOCK_WP 0xD3
27#define O2_SD_TEST_REG 0xD4
28#define O2_SD_FUNC_REG0 0xDC
29#define O2_SD_MULTI_VCC3V 0xEE
30#define O2_SD_CLKREQ 0xEC
31#define O2_SD_CAPS 0xE0
32#define O2_SD_ADMA1 0xE2
33#define O2_SD_ADMA2 0xE7
34#define O2_SD_INF_MOD 0xF1
35#define O2_SD_MISC_CTRL4 0xFC
36#define O2_SD_TUNING_CTRL 0x300
37#define O2_SD_PLL_SETTING 0x304
38#define O2_SD_MISC_SETTING 0x308
39#define O2_SD_CLK_SETTING 0x328
40#define O2_SD_CAP_REG2 0x330
41#define O2_SD_CAP_REG0 0x334
42#define O2_SD_UHS1_CAP_SETTING 0x33C
43#define O2_SD_DELAY_CTRL 0x350
44#define O2_SD_UHS2_L1_CTRL 0x35C
45#define O2_SD_FUNC_REG3 0x3E0
46#define O2_SD_FUNC_REG4 0x3E4
47#define O2_SD_LED_ENABLE BIT(6)
48#define O2_SD_FREG0_LEDOFF BIT(13)
49#define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
50
51#define O2_SD_VENDOR_SETTING 0x110
52#define O2_SD_VENDOR_SETTING2 0x1C8
53#define O2_SD_HW_TUNING_DISABLE BIT(4)
54
55#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
56#define O2_PLL_FORCE_ACTIVE BIT(18)
57#define O2_PLL_LOCK_STATUS BIT(14)
58#define O2_PLL_SOFT_RESET BIT(12)
59#define O2_DLL_LOCK_STATUS BIT(11)
60
61#define O2_SD_DETECT_SETTING 0x324
62
63static const u32 dmdn_table[] = {0x2B1C0000,
64 0x2C1A0000, 0x371B0000, 0x35100000};
65#define DMDN_SZ ARRAY_SIZE(dmdn_table)
66
67struct o2_host {
68 u8 dll_adjust_count;
69};
70
71static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
72{
73 ktime_t timeout;
74 u32 scratch32;
75
76 /* Wait max 50 ms */
77 timeout = ktime_add_ms(ktime_get(), 50);
78 while (1) {
79 bool timedout = ktime_after(ktime_get(), timeout);
80
81 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
82 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
83 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
84 break;
85
86 if (timedout) {
87 pr_err("%s: Card Detect debounce never finished.\n",
88 mmc_hostname(host->mmc));
89 sdhci_dumpregs(host);
90 return;
91 }
92 udelay(10);
93 }
94}
95
96static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
97{
98 ktime_t timeout;
99 u16 scratch;
100 u32 scratch32;
101
102 /* PLL software reset */
103 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
104 scratch32 |= O2_PLL_SOFT_RESET;
105 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
106 udelay(1);
107 scratch32 &= ~(O2_PLL_SOFT_RESET);
108 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
109
110 /* PLL force active */
111 scratch32 |= O2_PLL_FORCE_ACTIVE;
112 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
113
114 /* Wait max 20 ms */
115 timeout = ktime_add_ms(ktime_get(), 20);
116 while (1) {
117 bool timedout = ktime_after(ktime_get(), timeout);
118
119 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
120 if (scratch & O2_PLL_LOCK_STATUS)
121 break;
122 if (timedout) {
123 pr_err("%s: Internal clock never stabilised.\n",
124 mmc_hostname(host->mmc));
125 sdhci_dumpregs(host);
126 goto out;
127 }
128 udelay(10);
129 }
130
131 /* Wait for card detect finish */
132 udelay(1);
133 sdhci_o2_wait_card_detect_stable(host);
134
135out:
136 /* Cancel PLL force active */
137 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
138 scratch32 &= ~O2_PLL_FORCE_ACTIVE;
139 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
140}
141
142static int sdhci_o2_get_cd(struct mmc_host *mmc)
143{
144 struct sdhci_host *host = mmc_priv(mmc);
145
146 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
147 sdhci_o2_enable_internal_clock(host);
148
149 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
150}
151
152static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
153{
154 u32 scratch_32;
155
156 pci_read_config_dword(chip->pdev,
157 O2_SD_PLL_SETTING, &scratch_32);
158
159 scratch_32 &= 0x0000FFFF;
160 scratch_32 |= value;
161
162 pci_write_config_dword(chip->pdev,
163 O2_SD_PLL_SETTING, scratch_32);
164}
165
166static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
167{
168 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
169}
170
171/*
172 * This function is used to detect dll lock status.
173 * Since the dll lock status bit will toggle randomly
174 * with very short interval which needs to be polled
175 * as fast as possible. Set sleep_us as 1 microsecond.
176 */
177static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
178{
179 u32 scratch32 = 0;
180
181 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
182 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
183}
184
185static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
186{
187 u16 reg;
188
189 /* enable hardware tuning */
190 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
191 reg &= ~O2_SD_HW_TUNING_DISABLE;
192 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
193}
194
195static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
196{
197 int i;
198
199 sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
200
201 for (i = 0; i < 150; i++) {
202 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
203
204 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
205 if (ctrl & SDHCI_CTRL_TUNED_CLK) {
206 host->tuning_done = true;
207 return;
208 }
209 pr_warn("%s: HW tuning failed !\n",
210 mmc_hostname(host->mmc));
211 break;
212 }
213
214 mdelay(1);
215 }
216
217 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
218 mmc_hostname(host->mmc));
219 sdhci_reset_tuning(host);
220}
221
222/*
223 * This function is used to fix o2 dll shift issue.
224 * It isn't necessary to detect card present before recovery.
225 * Firstly, it is used by bht emmc card, which is embedded.
226 * Second, before call recovery card present will be detected
227 * outside of the execute tuning function.
228 */
229static int sdhci_o2_dll_recovery(struct sdhci_host *host)
230{
231 int ret = 0;
232 u8 scratch_8 = 0;
233 u32 scratch_32 = 0;
234 struct sdhci_pci_slot *slot = sdhci_priv(host);
235 struct sdhci_pci_chip *chip = slot->chip;
236 struct o2_host *o2_host = sdhci_pci_priv(slot);
237
238 /* UnLock WP */
239 pci_read_config_byte(chip->pdev,
240 O2_SD_LOCK_WP, &scratch_8);
241 scratch_8 &= 0x7f;
242 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
243 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
244 /* Disable clock */
245 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
246
247 /* PLL software reset */
248 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
249 scratch_32 |= O2_PLL_SOFT_RESET;
250 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
251
252 pci_read_config_dword(chip->pdev,
253 O2_SD_FUNC_REG4,
254 &scratch_32);
255 /* Enable Base Clk setting change */
256 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
257 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
258 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
259
260 /* Enable internal clock */
261 scratch_8 = SDHCI_CLOCK_INT_EN;
262 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
263
264 if (sdhci_o2_get_cd(host->mmc)) {
265 /*
266 * need wait at least 5ms for dll status stable,
267 * after enable internal clock
268 */
269 usleep_range(5000, 6000);
270 if (sdhci_o2_wait_dll_detect_lock(host)) {
271 scratch_8 |= SDHCI_CLOCK_CARD_EN;
272 sdhci_writeb(host, scratch_8,
273 SDHCI_CLOCK_CONTROL);
274 ret = 1;
275 } else {
276 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
277 mmc_hostname(host->mmc),
278 o2_host->dll_adjust_count);
279 }
280 } else {
281 pr_err("%s: card present detect failed.\n",
282 mmc_hostname(host->mmc));
283 break;
284 }
285
286 o2_host->dll_adjust_count++;
287 }
288 if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
289 pr_err("%s: DLL adjust over max times\n",
290 mmc_hostname(host->mmc));
291 /* Lock WP */
292 pci_read_config_byte(chip->pdev,
293 O2_SD_LOCK_WP, &scratch_8);
294 scratch_8 |= 0x80;
295 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
296 return ret;
297}
298
299static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
300{
301 struct sdhci_host *host = mmc_priv(mmc);
302 int current_bus_width = 0;
303
304 /*
305 * This handler only implements the eMMC tuning that is specific to
306 * this controller. Fall back to the standard method for other TIMING.
307 */
308 if (host->timing != MMC_TIMING_MMC_HS200)
309 return sdhci_execute_tuning(mmc, opcode);
310
311 if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
312 return -EINVAL;
313 /*
314 * Judge the tuning reason, whether caused by dll shift
315 * If cause by dll shift, should call sdhci_o2_dll_recovery
316 */
317 if (!sdhci_o2_wait_dll_detect_lock(host))
318 if (!sdhci_o2_dll_recovery(host)) {
319 pr_err("%s: o2 dll recovery failed\n",
320 mmc_hostname(host->mmc));
321 return -EINVAL;
322 }
323 /*
324 * o2 sdhci host didn't support 8bit emmc tuning
325 */
326 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
327 current_bus_width = mmc->ios.bus_width;
328 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
329 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
330 }
331
332 sdhci_o2_set_tuning_mode(host);
333
334 sdhci_start_tuning(host);
335
336 __sdhci_o2_execute_tuning(host, opcode);
337
338 sdhci_end_tuning(host);
339
340 if (current_bus_width == MMC_BUS_WIDTH_8) {
341 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
342 sdhci_set_bus_width(host, current_bus_width);
343 }
344
345 host->flags &= ~SDHCI_HS400_TUNING;
346 return 0;
347}
348
349static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
350{
351 int ret;
352 u32 scratch_32;
353
354 /* Set led of SD host function enable */
355 ret = pci_read_config_dword(chip->pdev,
356 O2_SD_FUNC_REG0, &scratch_32);
357 if (ret)
358 return;
359
360 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
361 pci_write_config_dword(chip->pdev,
362 O2_SD_FUNC_REG0, scratch_32);
363
364 ret = pci_read_config_dword(chip->pdev,
365 O2_SD_TEST_REG, &scratch_32);
366 if (ret)
367 return;
368
369 scratch_32 |= O2_SD_LED_ENABLE;
370 pci_write_config_dword(chip->pdev,
371 O2_SD_TEST_REG, scratch_32);
372
373}
374
375static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
376{
377 u32 scratch_32;
378 int ret;
379 /* Improve write performance for SD3.0 */
380 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
381 if (ret)
382 return;
383 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
384 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
385
386 /* Enable Link abnormal reset generating Reset */
387 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
388 if (ret)
389 return;
390 scratch_32 &= ~((1 << 19) | (1 << 11));
391 scratch_32 |= (1 << 10);
392 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
393
394 /* set card power over current protection */
395 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
396 if (ret)
397 return;
398 scratch_32 |= (1 << 4);
399 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
400
401 /* adjust the output delay for SD mode */
402 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
403
404 /* Set the output voltage setting of Aux 1.2v LDO */
405 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
406 if (ret)
407 return;
408 scratch_32 &= ~(3 << 12);
409 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
410
411 /* Set Max power supply capability of SD host */
412 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
413 if (ret)
414 return;
415 scratch_32 &= ~(0x01FE);
416 scratch_32 |= 0x00CC;
417 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
418 /* Set DLL Tuning Window */
419 ret = pci_read_config_dword(chip->pdev,
420 O2_SD_TUNING_CTRL, &scratch_32);
421 if (ret)
422 return;
423 scratch_32 &= ~(0x000000FF);
424 scratch_32 |= 0x00000066;
425 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
426
427 /* Set UHS2 T_EIDLE */
428 ret = pci_read_config_dword(chip->pdev,
429 O2_SD_UHS2_L1_CTRL, &scratch_32);
430 if (ret)
431 return;
432 scratch_32 &= ~(0x000000FC);
433 scratch_32 |= 0x00000084;
434 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
435
436 /* Set UHS2 Termination */
437 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
438 if (ret)
439 return;
440 scratch_32 &= ~((1 << 21) | (1 << 30));
441
442 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
443
444 /* Set L1 Entrance Timer */
445 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
446 if (ret)
447 return;
448 scratch_32 &= ~(0xf0000000);
449 scratch_32 |= 0x30000000;
450 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
451
452 ret = pci_read_config_dword(chip->pdev,
453 O2_SD_MISC_CTRL4, &scratch_32);
454 if (ret)
455 return;
456 scratch_32 &= ~(0x000f0000);
457 scratch_32 |= 0x00080000;
458 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
459}
460
461static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
462 struct sdhci_host *host)
463{
464 int ret;
465
466 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
467 if (!ret) {
468 pr_info("%s: unsupport msi, use INTx irq\n",
469 mmc_hostname(host->mmc));
470 return;
471 }
472
473 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
474 PCI_IRQ_MSI | PCI_IRQ_MSIX);
475 if (ret < 0) {
476 pr_err("%s: enable PCI MSI failed, err=%d\n",
477 mmc_hostname(host->mmc), ret);
478 return;
479 }
480
481 host->irq = pci_irq_vector(chip->pdev, 0);
482}
483
484static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
485{
486 /* Enable internal clock */
487 clk |= SDHCI_CLOCK_INT_EN;
488 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
489
490 sdhci_o2_enable_internal_clock(host);
491 if (sdhci_o2_get_cd(host->mmc)) {
492 clk |= SDHCI_CLOCK_CARD_EN;
493 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
494 }
495}
496
497void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
498{
499 u16 clk;
500
501 host->mmc->actual_clock = 0;
502
503 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
504
505 if (clock == 0)
506 return;
507
508 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
509 sdhci_o2_enable_clk(host, clk);
510}
511
512int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
513{
514 struct sdhci_pci_chip *chip;
515 struct sdhci_host *host;
516 struct o2_host *o2_host = sdhci_pci_priv(slot);
517 u32 reg, caps;
518 int ret;
519
520 chip = slot->chip;
521 host = slot->host;
522
523 o2_host->dll_adjust_count = 0;
524 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
525
526 /*
527 * mmc_select_bus_width() will test the bus to determine the actual bus
528 * width.
529 */
530 if (caps & SDHCI_CAN_DO_8BIT)
531 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
532
533 switch (chip->pdev->device) {
534 case PCI_DEVICE_ID_O2_SDS0:
535 case PCI_DEVICE_ID_O2_SEABIRD0:
536 case PCI_DEVICE_ID_O2_SEABIRD1:
537 case PCI_DEVICE_ID_O2_SDS1:
538 case PCI_DEVICE_ID_O2_FUJIN2:
539 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
540 if (reg & 0x1)
541 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
542
543 sdhci_pci_o2_enable_msi(chip, host);
544
545 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
546 ret = pci_read_config_dword(chip->pdev,
547 O2_SD_MISC_SETTING, ®);
548 if (ret)
549 return -EIO;
550 if (reg & (1 << 4)) {
551 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
552 mmc_hostname(host->mmc));
553 host->flags &= ~SDHCI_SIGNALING_330;
554 host->flags |= SDHCI_SIGNALING_180;
555 host->mmc->caps2 |= MMC_CAP2_NO_SD;
556 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
557 pci_write_config_dword(chip->pdev,
558 O2_SD_DETECT_SETTING, 3);
559 }
560
561 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
562 }
563
564 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
565
566 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
567 break;
568 /* set dll watch dog timer */
569 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
570 reg |= (1 << 12);
571 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
572
573 break;
574 default:
575 break;
576 }
577
578 return 0;
579}
580
581int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
582{
583 int ret;
584 u8 scratch;
585 u32 scratch_32;
586
587 switch (chip->pdev->device) {
588 case PCI_DEVICE_ID_O2_8220:
589 case PCI_DEVICE_ID_O2_8221:
590 case PCI_DEVICE_ID_O2_8320:
591 case PCI_DEVICE_ID_O2_8321:
592 /* This extra setup is required due to broken ADMA. */
593 ret = pci_read_config_byte(chip->pdev,
594 O2_SD_LOCK_WP, &scratch);
595 if (ret)
596 return ret;
597 scratch &= 0x7f;
598 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
599
600 /* Set Multi 3 to VCC3V# */
601 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
602
603 /* Disable CLK_REQ# support after media DET */
604 ret = pci_read_config_byte(chip->pdev,
605 O2_SD_CLKREQ, &scratch);
606 if (ret)
607 return ret;
608 scratch |= 0x20;
609 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
610
611 /* Choose capabilities, enable SDMA. We have to write 0x01
612 * to the capabilities register first to unlock it.
613 */
614 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
615 if (ret)
616 return ret;
617 scratch |= 0x01;
618 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
619 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
620
621 /* Disable ADMA1/2 */
622 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
623 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
624
625 /* Disable the infinite transfer mode */
626 ret = pci_read_config_byte(chip->pdev,
627 O2_SD_INF_MOD, &scratch);
628 if (ret)
629 return ret;
630 scratch |= 0x08;
631 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
632
633 /* Lock WP */
634 ret = pci_read_config_byte(chip->pdev,
635 O2_SD_LOCK_WP, &scratch);
636 if (ret)
637 return ret;
638 scratch |= 0x80;
639 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
640 break;
641 case PCI_DEVICE_ID_O2_SDS0:
642 case PCI_DEVICE_ID_O2_SDS1:
643 case PCI_DEVICE_ID_O2_FUJIN2:
644 /* UnLock WP */
645 ret = pci_read_config_byte(chip->pdev,
646 O2_SD_LOCK_WP, &scratch);
647 if (ret)
648 return ret;
649
650 scratch &= 0x7f;
651 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
652
653 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
654 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
655 ret = pci_read_config_dword(chip->pdev,
656 O2_SD_FUNC_REG0,
657 &scratch_32);
658 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
659
660 /* Check Whether subId is 0x11 or 0x12 */
661 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
662 scratch_32 = 0x25100000;
663
664 o2_pci_set_baseclk(chip, scratch_32);
665 ret = pci_read_config_dword(chip->pdev,
666 O2_SD_FUNC_REG4,
667 &scratch_32);
668
669 /* Enable Base Clk setting change */
670 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
671 pci_write_config_dword(chip->pdev,
672 O2_SD_FUNC_REG4,
673 scratch_32);
674
675 /* Set Tuning Window to 4 */
676 pci_write_config_byte(chip->pdev,
677 O2_SD_TUNING_CTRL, 0x44);
678
679 break;
680 }
681 }
682
683 /* Enable 8520 led function */
684 o2_pci_led_enable(chip);
685
686 /* Set timeout CLK */
687 ret = pci_read_config_dword(chip->pdev,
688 O2_SD_CLK_SETTING, &scratch_32);
689 if (ret)
690 return ret;
691
692 scratch_32 &= ~(0xFF00);
693 scratch_32 |= 0x07E0C800;
694 pci_write_config_dword(chip->pdev,
695 O2_SD_CLK_SETTING, scratch_32);
696
697 ret = pci_read_config_dword(chip->pdev,
698 O2_SD_CLKREQ, &scratch_32);
699 if (ret)
700 return ret;
701 scratch_32 |= 0x3;
702 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
703
704 ret = pci_read_config_dword(chip->pdev,
705 O2_SD_PLL_SETTING, &scratch_32);
706 if (ret)
707 return ret;
708
709 scratch_32 &= ~(0x1F3F070E);
710 scratch_32 |= 0x18270106;
711 pci_write_config_dword(chip->pdev,
712 O2_SD_PLL_SETTING, scratch_32);
713
714 /* Disable UHS1 funciton */
715 ret = pci_read_config_dword(chip->pdev,
716 O2_SD_CAP_REG2, &scratch_32);
717 if (ret)
718 return ret;
719 scratch_32 &= ~(0xE0);
720 pci_write_config_dword(chip->pdev,
721 O2_SD_CAP_REG2, scratch_32);
722
723 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
724 sdhci_pci_o2_fujin2_pci_init(chip);
725
726 /* Lock WP */
727 ret = pci_read_config_byte(chip->pdev,
728 O2_SD_LOCK_WP, &scratch);
729 if (ret)
730 return ret;
731 scratch |= 0x80;
732 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
733 break;
734 case PCI_DEVICE_ID_O2_SEABIRD0:
735 case PCI_DEVICE_ID_O2_SEABIRD1:
736 /* UnLock WP */
737 ret = pci_read_config_byte(chip->pdev,
738 O2_SD_LOCK_WP, &scratch);
739 if (ret)
740 return ret;
741
742 scratch &= 0x7f;
743 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
744
745 ret = pci_read_config_dword(chip->pdev,
746 O2_SD_PLL_SETTING, &scratch_32);
747
748 if ((scratch_32 & 0xff000000) == 0x01000000) {
749 scratch_32 &= 0x0000FFFF;
750 scratch_32 |= 0x1F340000;
751
752 pci_write_config_dword(chip->pdev,
753 O2_SD_PLL_SETTING, scratch_32);
754 } else {
755 scratch_32 &= 0x0000FFFF;
756 scratch_32 |= 0x25100000;
757
758 pci_write_config_dword(chip->pdev,
759 O2_SD_PLL_SETTING, scratch_32);
760
761 ret = pci_read_config_dword(chip->pdev,
762 O2_SD_FUNC_REG4,
763 &scratch_32);
764 scratch_32 |= (1 << 22);
765 pci_write_config_dword(chip->pdev,
766 O2_SD_FUNC_REG4, scratch_32);
767 }
768
769 /* Set Tuning Windows to 5 */
770 pci_write_config_byte(chip->pdev,
771 O2_SD_TUNING_CTRL, 0x55);
772 /* Lock WP */
773 ret = pci_read_config_byte(chip->pdev,
774 O2_SD_LOCK_WP, &scratch);
775 if (ret)
776 return ret;
777 scratch |= 0x80;
778 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
779 break;
780 }
781
782 return 0;
783}
784
785#ifdef CONFIG_PM_SLEEP
786int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
787{
788 sdhci_pci_o2_probe(chip);
789 return sdhci_pci_resume_host(chip);
790}
791#endif
792
793static const struct sdhci_ops sdhci_pci_o2_ops = {
794 .set_clock = sdhci_pci_o2_set_clock,
795 .enable_dma = sdhci_pci_enable_dma,
796 .set_bus_width = sdhci_set_bus_width,
797 .reset = sdhci_reset,
798 .set_uhs_signaling = sdhci_set_uhs_signaling,
799};
800
801const struct sdhci_pci_fixes sdhci_o2 = {
802 .probe = sdhci_pci_o2_probe,
803 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
804 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
805 .probe_slot = sdhci_pci_o2_probe_slot,
806#ifdef CONFIG_PM_SLEEP
807 .resume = sdhci_pci_o2_resume,
808#endif
809 .ops = &sdhci_pci_o2_ops,
810 .priv_size = sizeof(struct o2_host),
811};