Loading...
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/isa-rev.h>
20
21/*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25#ifndef __STR
26#define __STR(x) #x
27#endif
28#ifndef STR
29#define STR(x) __STR(x)
30#endif
31
32/*
33 * Configure language
34 */
35#ifdef __ASSEMBLY__
36#define _ULCAST_
37#define _U64CAST_
38#else
39#define _ULCAST_ (unsigned long)
40#define _U64CAST_ (u64)
41#endif
42
43/*
44 * Coprocessor 0 register names
45 */
46#define CP0_INDEX $0
47#define CP0_RANDOM $1
48#define CP0_ENTRYLO0 $2
49#define CP0_ENTRYLO1 $3
50#define CP0_CONF $3
51#define CP0_GLOBALNUMBER $3, 1
52#define CP0_CONTEXT $4
53#define CP0_PAGEMASK $5
54#define CP0_PAGEGRAIN $5, 1
55#define CP0_SEGCTL0 $5, 2
56#define CP0_SEGCTL1 $5, 3
57#define CP0_SEGCTL2 $5, 4
58#define CP0_WIRED $6
59#define CP0_INFO $7
60#define CP0_HWRENA $7
61#define CP0_BADVADDR $8
62#define CP0_BADINSTR $8, 1
63#define CP0_COUNT $9
64#define CP0_ENTRYHI $10
65#define CP0_GUESTCTL1 $10, 4
66#define CP0_GUESTCTL2 $10, 5
67#define CP0_GUESTCTL3 $10, 6
68#define CP0_COMPARE $11
69#define CP0_GUESTCTL0EXT $11, 4
70#define CP0_STATUS $12
71#define CP0_GUESTCTL0 $12, 6
72#define CP0_GTOFFSET $12, 7
73#define CP0_CAUSE $13
74#define CP0_EPC $14
75#define CP0_PRID $15
76#define CP0_EBASE $15, 1
77#define CP0_CMGCRBASE $15, 3
78#define CP0_CONFIG $16
79#define CP0_CONFIG3 $16, 3
80#define CP0_CONFIG5 $16, 5
81#define CP0_CONFIG6 $16, 6
82#define CP0_LLADDR $17
83#define CP0_WATCHLO $18
84#define CP0_WATCHHI $19
85#define CP0_XCONTEXT $20
86#define CP0_FRAMEMASK $21
87#define CP0_DIAGNOSTIC $22
88#define CP0_DIAGNOSTIC1 $22, 1
89#define CP0_DEBUG $23
90#define CP0_DEPC $24
91#define CP0_PERFORMANCE $25
92#define CP0_ECC $26
93#define CP0_CACHEERR $27
94#define CP0_TAGLO $28
95#define CP0_TAGHI $29
96#define CP0_ERROREPC $30
97#define CP0_DESAVE $31
98
99/*
100 * R4640/R4650 cp0 register names. These registers are listed
101 * here only for completeness; without MMU these CPUs are not useable
102 * by Linux. A future ELKS port might take make Linux run on them
103 * though ...
104 */
105#define CP0_IBASE $0
106#define CP0_IBOUND $1
107#define CP0_DBASE $2
108#define CP0_DBOUND $3
109#define CP0_CALG $17
110#define CP0_IWATCH $18
111#define CP0_DWATCH $19
112
113/*
114 * Coprocessor 0 Set 1 register names
115 */
116#define CP0_S1_DERRADDR0 $26
117#define CP0_S1_DERRADDR1 $27
118#define CP0_S1_INTCONTROL $20
119
120/*
121 * Coprocessor 0 Set 2 register names
122 */
123#define CP0_S2_SRSCTL $12 /* MIPSR2 */
124
125/*
126 * Coprocessor 0 Set 3 register names
127 */
128#define CP0_S3_SRSMAP $12 /* MIPSR2 */
129
130/*
131 * TX39 Series
132 */
133#define CP0_TX39_CACHE $7
134
135
136/* Generic EntryLo bit definitions */
137#define ENTRYLO_G (_ULCAST_(1) << 0)
138#define ENTRYLO_V (_ULCAST_(1) << 1)
139#define ENTRYLO_D (_ULCAST_(1) << 2)
140#define ENTRYLO_C_SHIFT 3
141#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
142
143/* R3000 EntryLo bit definitions */
144#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
145#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
146#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
147#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
148
149/* MIPS32/64 EntryLo bit definitions */
150#define MIPS_ENTRYLO_PFN_SHIFT 6
151#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
152#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
153
154/*
155 * MIPSr6+ GlobalNumber register definitions
156 */
157#define MIPS_GLOBALNUMBER_VP_SHF 0
158#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
159#define MIPS_GLOBALNUMBER_CORE_SHF 8
160#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
161#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
162#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
163
164/*
165 * Values for PageMask register
166 */
167#define PM_4K 0x00000000
168#define PM_8K 0x00002000
169#define PM_16K 0x00006000
170#define PM_32K 0x0000e000
171#define PM_64K 0x0001e000
172#define PM_128K 0x0003e000
173#define PM_256K 0x0007e000
174#define PM_512K 0x000fe000
175#define PM_1M 0x001fe000
176#define PM_2M 0x003fe000
177#define PM_4M 0x007fe000
178#define PM_8M 0x00ffe000
179#define PM_16M 0x01ffe000
180#define PM_32M 0x03ffe000
181#define PM_64M 0x07ffe000
182#define PM_256M 0x1fffe000
183#define PM_1G 0x7fffe000
184
185/*
186 * Default page size for a given kernel configuration
187 */
188#ifdef CONFIG_PAGE_SIZE_4KB
189#define PM_DEFAULT_MASK PM_4K
190#elif defined(CONFIG_PAGE_SIZE_8KB)
191#define PM_DEFAULT_MASK PM_8K
192#elif defined(CONFIG_PAGE_SIZE_16KB)
193#define PM_DEFAULT_MASK PM_16K
194#elif defined(CONFIG_PAGE_SIZE_32KB)
195#define PM_DEFAULT_MASK PM_32K
196#elif defined(CONFIG_PAGE_SIZE_64KB)
197#define PM_DEFAULT_MASK PM_64K
198#else
199#error Bad page size configuration!
200#endif
201
202/*
203 * Default huge tlb size for a given kernel configuration
204 */
205#ifdef CONFIG_PAGE_SIZE_4KB
206#define PM_HUGE_MASK PM_1M
207#elif defined(CONFIG_PAGE_SIZE_8KB)
208#define PM_HUGE_MASK PM_4M
209#elif defined(CONFIG_PAGE_SIZE_16KB)
210#define PM_HUGE_MASK PM_16M
211#elif defined(CONFIG_PAGE_SIZE_32KB)
212#define PM_HUGE_MASK PM_64M
213#elif defined(CONFIG_PAGE_SIZE_64KB)
214#define PM_HUGE_MASK PM_256M
215#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
216#error Bad page size configuration for hugetlbfs!
217#endif
218
219/*
220 * Wired register bits
221 */
222#define MIPSR6_WIRED_LIMIT_SHIFT 16
223#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
224#define MIPSR6_WIRED_WIRED_SHIFT 0
225#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
226
227/*
228 * Values used for computation of new tlb entries
229 */
230#define PL_4K 12
231#define PL_16K 14
232#define PL_64K 16
233#define PL_256K 18
234#define PL_1M 20
235#define PL_4M 22
236#define PL_16M 24
237#define PL_64M 26
238#define PL_256M 28
239
240/*
241 * PageGrain bits
242 */
243#define PG_RIE (_ULCAST_(1) << 31)
244#define PG_XIE (_ULCAST_(1) << 30)
245#define PG_ELPA (_ULCAST_(1) << 29)
246#define PG_ESP (_ULCAST_(1) << 28)
247#define PG_IEC (_ULCAST_(1) << 27)
248
249/* MIPS32/64 EntryHI bit definitions */
250#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
251#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
252#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
253
254/*
255 * R4x00 interrupt enable / cause bits
256 */
257#define IE_SW0 (_ULCAST_(1) << 8)
258#define IE_SW1 (_ULCAST_(1) << 9)
259#define IE_IRQ0 (_ULCAST_(1) << 10)
260#define IE_IRQ1 (_ULCAST_(1) << 11)
261#define IE_IRQ2 (_ULCAST_(1) << 12)
262#define IE_IRQ3 (_ULCAST_(1) << 13)
263#define IE_IRQ4 (_ULCAST_(1) << 14)
264#define IE_IRQ5 (_ULCAST_(1) << 15)
265
266/*
267 * R4x00 interrupt cause bits
268 */
269#define C_SW0 (_ULCAST_(1) << 8)
270#define C_SW1 (_ULCAST_(1) << 9)
271#define C_IRQ0 (_ULCAST_(1) << 10)
272#define C_IRQ1 (_ULCAST_(1) << 11)
273#define C_IRQ2 (_ULCAST_(1) << 12)
274#define C_IRQ3 (_ULCAST_(1) << 13)
275#define C_IRQ4 (_ULCAST_(1) << 14)
276#define C_IRQ5 (_ULCAST_(1) << 15)
277
278/*
279 * Bitfields in the R4xx0 cp0 status register
280 */
281#define ST0_IE 0x00000001
282#define ST0_EXL 0x00000002
283#define ST0_ERL 0x00000004
284#define ST0_KSU 0x00000018
285# define KSU_USER 0x00000010
286# define KSU_SUPERVISOR 0x00000008
287# define KSU_KERNEL 0x00000000
288#define ST0_UX 0x00000020
289#define ST0_SX 0x00000040
290#define ST0_KX 0x00000080
291#define ST0_DE 0x00010000
292#define ST0_CE 0x00020000
293
294/*
295 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
296 * cacheops in userspace. This bit exists only on RM7000 and RM9000
297 * processors.
298 */
299#define ST0_CO 0x08000000
300
301/*
302 * Bitfields in the R[23]000 cp0 status register.
303 */
304#define ST0_IEC 0x00000001
305#define ST0_KUC 0x00000002
306#define ST0_IEP 0x00000004
307#define ST0_KUP 0x00000008
308#define ST0_IEO 0x00000010
309#define ST0_KUO 0x00000020
310/* bits 6 & 7 are reserved on R[23]000 */
311#define ST0_ISC 0x00010000
312#define ST0_SWC 0x00020000
313#define ST0_CM 0x00080000
314
315/*
316 * Bits specific to the R4640/R4650
317 */
318#define ST0_UM (_ULCAST_(1) << 4)
319#define ST0_IL (_ULCAST_(1) << 23)
320#define ST0_DL (_ULCAST_(1) << 24)
321
322/*
323 * Enable the MIPS MDMX and DSP ASEs
324 */
325#define ST0_MX 0x01000000
326
327/*
328 * Status register bits available in all MIPS CPUs.
329 */
330#define ST0_IM 0x0000ff00
331#define STATUSB_IP0 8
332#define STATUSF_IP0 (_ULCAST_(1) << 8)
333#define STATUSB_IP1 9
334#define STATUSF_IP1 (_ULCAST_(1) << 9)
335#define STATUSB_IP2 10
336#define STATUSF_IP2 (_ULCAST_(1) << 10)
337#define STATUSB_IP3 11
338#define STATUSF_IP3 (_ULCAST_(1) << 11)
339#define STATUSB_IP4 12
340#define STATUSF_IP4 (_ULCAST_(1) << 12)
341#define STATUSB_IP5 13
342#define STATUSF_IP5 (_ULCAST_(1) << 13)
343#define STATUSB_IP6 14
344#define STATUSF_IP6 (_ULCAST_(1) << 14)
345#define STATUSB_IP7 15
346#define STATUSF_IP7 (_ULCAST_(1) << 15)
347#define STATUSB_IP8 0
348#define STATUSF_IP8 (_ULCAST_(1) << 0)
349#define STATUSB_IP9 1
350#define STATUSF_IP9 (_ULCAST_(1) << 1)
351#define STATUSB_IP10 2
352#define STATUSF_IP10 (_ULCAST_(1) << 2)
353#define STATUSB_IP11 3
354#define STATUSF_IP11 (_ULCAST_(1) << 3)
355#define STATUSB_IP12 4
356#define STATUSF_IP12 (_ULCAST_(1) << 4)
357#define STATUSB_IP13 5
358#define STATUSF_IP13 (_ULCAST_(1) << 5)
359#define STATUSB_IP14 6
360#define STATUSF_IP14 (_ULCAST_(1) << 6)
361#define STATUSB_IP15 7
362#define STATUSF_IP15 (_ULCAST_(1) << 7)
363#define ST0_CH 0x00040000
364#define ST0_NMI 0x00080000
365#define ST0_SR 0x00100000
366#define ST0_TS 0x00200000
367#define ST0_BEV 0x00400000
368#define ST0_RE 0x02000000
369#define ST0_FR 0x04000000
370#define ST0_CU 0xf0000000
371#define ST0_CU0 0x10000000
372#define ST0_CU1 0x20000000
373#define ST0_CU2 0x40000000
374#define ST0_CU3 0x80000000
375#define ST0_XX 0x80000000 /* MIPS IV naming */
376
377/* in-kernel enabled CUs */
378#ifdef CONFIG_CPU_LOONGSON64
379#define ST0_KERNEL_CUMASK (ST0_CU0 | ST0_CU2)
380#else
381#define ST0_KERNEL_CUMASK ST0_CU0
382#endif
383
384/*
385 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
386 */
387#define INTCTLB_IPFDC 23
388#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
389#define INTCTLB_IPPCI 26
390#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
391#define INTCTLB_IPTI 29
392#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
393
394/*
395 * Bitfields and bit numbers in the coprocessor 0 cause register.
396 *
397 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
398 */
399#define CAUSEB_EXCCODE 2
400#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
401#define CAUSEB_IP 8
402#define CAUSEF_IP (_ULCAST_(255) << 8)
403#define CAUSEB_IP0 8
404#define CAUSEF_IP0 (_ULCAST_(1) << 8)
405#define CAUSEB_IP1 9
406#define CAUSEF_IP1 (_ULCAST_(1) << 9)
407#define CAUSEB_IP2 10
408#define CAUSEF_IP2 (_ULCAST_(1) << 10)
409#define CAUSEB_IP3 11
410#define CAUSEF_IP3 (_ULCAST_(1) << 11)
411#define CAUSEB_IP4 12
412#define CAUSEF_IP4 (_ULCAST_(1) << 12)
413#define CAUSEB_IP5 13
414#define CAUSEF_IP5 (_ULCAST_(1) << 13)
415#define CAUSEB_IP6 14
416#define CAUSEF_IP6 (_ULCAST_(1) << 14)
417#define CAUSEB_IP7 15
418#define CAUSEF_IP7 (_ULCAST_(1) << 15)
419#define CAUSEB_FDCI 21
420#define CAUSEF_FDCI (_ULCAST_(1) << 21)
421#define CAUSEB_WP 22
422#define CAUSEF_WP (_ULCAST_(1) << 22)
423#define CAUSEB_IV 23
424#define CAUSEF_IV (_ULCAST_(1) << 23)
425#define CAUSEB_PCI 26
426#define CAUSEF_PCI (_ULCAST_(1) << 26)
427#define CAUSEB_DC 27
428#define CAUSEF_DC (_ULCAST_(1) << 27)
429#define CAUSEB_CE 28
430#define CAUSEF_CE (_ULCAST_(3) << 28)
431#define CAUSEB_TI 30
432#define CAUSEF_TI (_ULCAST_(1) << 30)
433#define CAUSEB_BD 31
434#define CAUSEF_BD (_ULCAST_(1) << 31)
435
436/*
437 * Cause.ExcCode trap codes.
438 */
439#define EXCCODE_INT 0 /* Interrupt pending */
440#define EXCCODE_MOD 1 /* TLB modified fault */
441#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
442#define EXCCODE_TLBS 3 /* TLB miss on a store */
443#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
444#define EXCCODE_ADES 5 /* Address error on a store */
445#define EXCCODE_IBE 6 /* Bus error on an ifetch */
446#define EXCCODE_DBE 7 /* Bus error on a load or store */
447#define EXCCODE_SYS 8 /* System call */
448#define EXCCODE_BP 9 /* Breakpoint */
449#define EXCCODE_RI 10 /* Reserved instruction exception */
450#define EXCCODE_CPU 11 /* Coprocessor unusable */
451#define EXCCODE_OV 12 /* Arithmetic overflow */
452#define EXCCODE_TR 13 /* Trap instruction */
453#define EXCCODE_MSAFPE 14 /* MSA floating point exception */
454#define EXCCODE_FPE 15 /* Floating point exception */
455#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
456#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
457#define EXCCODE_MSADIS 21 /* MSA disabled exception */
458#define EXCCODE_MDMX 22 /* MDMX unusable exception */
459#define EXCCODE_WATCH 23 /* Watch address reference */
460#define EXCCODE_MCHECK 24 /* Machine check */
461#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
462#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
463#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
464#define EXCCODE_CACHEERR 30 /* Parity/ECC occured on a core */
465
466/* Implementation specific trap codes used by MIPS cores */
467#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
468
469/* Implementation specific trap codes used by Loongson cores */
470#define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */
471
472/*
473 * Bits in the coprocessor 0 config register.
474 */
475/* Generic bits. */
476#define CONF_CM_CACHABLE_NO_WA 0
477#define CONF_CM_CACHABLE_WA 1
478#define CONF_CM_UNCACHED 2
479#define CONF_CM_CACHABLE_NONCOHERENT 3
480#define CONF_CM_CACHABLE_CE 4
481#define CONF_CM_CACHABLE_COW 5
482#define CONF_CM_CACHABLE_CUW 6
483#define CONF_CM_CACHABLE_ACCELERATED 7
484#define CONF_CM_CMASK 7
485#define CONF_BE (_ULCAST_(1) << 15)
486
487/* Bits common to various processors. */
488#define CONF_CU (_ULCAST_(1) << 3)
489#define CONF_DB (_ULCAST_(1) << 4)
490#define CONF_IB (_ULCAST_(1) << 5)
491#define CONF_DC (_ULCAST_(7) << 6)
492#define CONF_IC (_ULCAST_(7) << 9)
493#define CONF_EB (_ULCAST_(1) << 13)
494#define CONF_EM (_ULCAST_(1) << 14)
495#define CONF_SM (_ULCAST_(1) << 16)
496#define CONF_SC (_ULCAST_(1) << 17)
497#define CONF_EW (_ULCAST_(3) << 18)
498#define CONF_EP (_ULCAST_(15)<< 24)
499#define CONF_EC (_ULCAST_(7) << 28)
500#define CONF_CM (_ULCAST_(1) << 31)
501
502/* Bits specific to the R4xx0. */
503#define R4K_CONF_SW (_ULCAST_(1) << 20)
504#define R4K_CONF_SS (_ULCAST_(1) << 21)
505#define R4K_CONF_SB (_ULCAST_(3) << 22)
506
507/* Bits specific to the R5000. */
508#define R5K_CONF_SE (_ULCAST_(1) << 12)
509#define R5K_CONF_SS (_ULCAST_(3) << 20)
510
511/* Bits specific to the RM7000. */
512#define RM7K_CONF_SE (_ULCAST_(1) << 3)
513#define RM7K_CONF_TE (_ULCAST_(1) << 12)
514#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
515#define RM7K_CONF_TC (_ULCAST_(1) << 17)
516#define RM7K_CONF_SI (_ULCAST_(3) << 20)
517#define RM7K_CONF_SC (_ULCAST_(1) << 31)
518
519/* Bits specific to the R10000. */
520#define R10K_CONF_DN (_ULCAST_(3) << 3)
521#define R10K_CONF_CT (_ULCAST_(1) << 5)
522#define R10K_CONF_PE (_ULCAST_(1) << 6)
523#define R10K_CONF_PM (_ULCAST_(3) << 7)
524#define R10K_CONF_EC (_ULCAST_(15)<< 9)
525#define R10K_CONF_SB (_ULCAST_(1) << 13)
526#define R10K_CONF_SK (_ULCAST_(1) << 14)
527#define R10K_CONF_SS (_ULCAST_(7) << 16)
528#define R10K_CONF_SC (_ULCAST_(7) << 19)
529#define R10K_CONF_DC (_ULCAST_(7) << 26)
530#define R10K_CONF_IC (_ULCAST_(7) << 29)
531
532/* Bits specific to the VR41xx. */
533#define VR41_CONF_CS (_ULCAST_(1) << 12)
534#define VR41_CONF_P4K (_ULCAST_(1) << 13)
535#define VR41_CONF_BP (_ULCAST_(1) << 16)
536#define VR41_CONF_M16 (_ULCAST_(1) << 20)
537#define VR41_CONF_AD (_ULCAST_(1) << 23)
538
539/* Bits specific to the R30xx. */
540#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
541#define R30XX_CONF_REV (_ULCAST_(1) << 22)
542#define R30XX_CONF_AC (_ULCAST_(1) << 23)
543#define R30XX_CONF_RF (_ULCAST_(1) << 24)
544#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
545#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
546#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
547#define R30XX_CONF_SB (_ULCAST_(1) << 30)
548#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
549
550/* Bits specific to the TX49. */
551#define TX49_CONF_DC (_ULCAST_(1) << 16)
552#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
553#define TX49_CONF_HALT (_ULCAST_(1) << 18)
554#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
555
556/* Bits specific to the MIPS32/64 PRA. */
557#define MIPS_CONF_VI (_ULCAST_(1) << 3)
558#define MIPS_CONF_MT (_ULCAST_(7) << 7)
559#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
560#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
561#define MIPS_CONF_AR (_ULCAST_(7) << 10)
562#define MIPS_CONF_AT (_ULCAST_(3) << 13)
563#define MIPS_CONF_BE (_ULCAST_(1) << 15)
564#define MIPS_CONF_BM (_ULCAST_(1) << 16)
565#define MIPS_CONF_MM (_ULCAST_(3) << 17)
566#define MIPS_CONF_MM_SYSAD (_ULCAST_(1) << 17)
567#define MIPS_CONF_MM_FULL (_ULCAST_(2) << 17)
568#define MIPS_CONF_SB (_ULCAST_(1) << 21)
569#define MIPS_CONF_UDI (_ULCAST_(1) << 22)
570#define MIPS_CONF_DSP (_ULCAST_(1) << 23)
571#define MIPS_CONF_ISP (_ULCAST_(1) << 24)
572#define MIPS_CONF_KU (_ULCAST_(3) << 25)
573#define MIPS_CONF_K23 (_ULCAST_(3) << 28)
574#define MIPS_CONF_M (_ULCAST_(1) << 31)
575
576/*
577 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
578 */
579#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
580#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
581#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
582#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
583#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
584#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
585#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
586#define MIPS_CONF1_DA_SHF 7
587#define MIPS_CONF1_DA_SZ 3
588#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
589#define MIPS_CONF1_DL_SHF 10
590#define MIPS_CONF1_DL_SZ 3
591#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
592#define MIPS_CONF1_DS_SHF 13
593#define MIPS_CONF1_DS_SZ 3
594#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
595#define MIPS_CONF1_IA_SHF 16
596#define MIPS_CONF1_IA_SZ 3
597#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
598#define MIPS_CONF1_IL_SHF 19
599#define MIPS_CONF1_IL_SZ 3
600#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
601#define MIPS_CONF1_IS_SHF 22
602#define MIPS_CONF1_IS_SZ 3
603#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
604#define MIPS_CONF1_TLBS_SHIFT (25)
605#define MIPS_CONF1_TLBS_SIZE (6)
606#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
607
608#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
609#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
610#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
611#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
612#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
613#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
614#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
615#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
616
617#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
618#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
619#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
620#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
621#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
622#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
623#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
624#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
625#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
626#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
627#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
628#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
629#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
630#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
631#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
632#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
633#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
634#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
635#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
636#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
637#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
638#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
639#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
640#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
641#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
642#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
643#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
644
645#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
646#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
647#define MIPS_CONF4_FTLBSETS_SHIFT (0)
648#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
649#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
650#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
651#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
652/* bits 10:8 in FTLB-only configurations */
653#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
654/* bits 12:8 in VTLB-FTLB only configurations */
655#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
656#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
657#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
658#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
659#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
660#define MIPS_CONF4_KSCREXIST_SHIFT (16)
661#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
662#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
663#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
664#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
665#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
666#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
667
668#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
669#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
670#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
671#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
672#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
673#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
674#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
675#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
676#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
677#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
678#define MIPS_CONF5_MI (_ULCAST_(1) << 17)
679#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
680#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
681#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
682#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
683#define MIPS_CONF5_K (_ULCAST_(1) << 30)
684
685/* Config6 feature bits for proAptiv/P5600 */
686
687/* Jump register cache prediction disable */
688#define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
689/* MIPSr6 extensions enable */
690#define MTI_CONF6_R6 (_ULCAST_(1) << 2)
691/* IFU Performance Control */
692#define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10)
693#define MTI_CONF6_SYND (_ULCAST_(1) << 13)
694/* Sleep state performance counter disable */
695#define MTI_CONF6_SPCD (_ULCAST_(1) << 14)
696/* proAptiv FTLB on/off bit */
697#define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15)
698/* Disable load/store bonding */
699#define MTI_CONF6_DLSB (_ULCAST_(1) << 21)
700/* FTLB probability bits */
701#define MTI_CONF6_FTLBP_SHIFT (16)
702
703/* Config6 feature bits for Loongson-3 */
704
705/* Loongson-3 internal timer bit */
706#define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
707/* Loongson-3 external timer bit */
708#define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
709/* Loongson-3 SFB on/off bit, STFill in manual */
710#define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8)
711/* Loongson-3's LL on exclusive cacheline */
712#define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16)
713/* Loongson-3's SC has a random delay */
714#define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17)
715/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
716#define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
717
718#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
719
720#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
721
722#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
723#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
724
725/* Ingenic HPTLB off bits */
726#define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
727
728/* Ingenic Config7 bits */
729#define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
730
731/* Config7 Bits specific to MIPS Technologies. */
732
733/* Performance counters implemented Per TC */
734#define MTI_CONF7_PTC (_ULCAST_(1) << 19)
735
736/* WatchLo* register definitions */
737#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
738
739/* WatchHi* register definitions */
740#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
741#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
742#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
743#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
744#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
745#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
746#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
747#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
748#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
749#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
750#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
751#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
752#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
753
754/* PerfCnt control register definitions */
755#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
756#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
757#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
758#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
759#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
760#define MIPS_PERFCTRL_EVENT_S 5
761#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
762#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
763#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
764#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
765#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
766#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
767#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
768#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
769#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
770
771/* PerfCnt control register MT extensions used by MIPS cores */
772#define MIPS_PERFCTRL_VPEID_S 16
773#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
774#define MIPS_PERFCTRL_TCID_S 22
775#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
776#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
777#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
778#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
779#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
780
781/* PerfCnt control register MT extensions used by BMIPS5000 */
782#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
783
784/* PerfCnt control register MT extensions used by Netlogic XLR */
785#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
786
787/* MAAR bit definitions */
788#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
789#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)
790#define MIPS_MAAR_ADDR_SHIFT 12
791#define MIPS_MAAR_S (_ULCAST_(1) << 1)
792#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
793#ifdef CONFIG_XPA
794#define MIPS_MAAR_V (MIPS_MAAR_VH | MIPS_MAAR_VL)
795#else
796#define MIPS_MAAR_V MIPS_MAAR_VL
797#endif
798#define MIPS_MAARX_VH (_ULCAST_(1) << 31)
799#define MIPS_MAARX_ADDR 0xF
800#define MIPS_MAARX_ADDR_SHIFT 32
801
802/* MAARI bit definitions */
803#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
804
805/* EBase bit definitions */
806#define MIPS_EBASE_CPUNUM_SHIFT 0
807#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
808#define MIPS_EBASE_WG_SHIFT 11
809#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
810#define MIPS_EBASE_BASE_SHIFT 12
811#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
812
813/* CMGCRBase bit definitions */
814#define MIPS_CMGCRB_BASE 11
815#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
816
817/* LLAddr bit definitions */
818#define MIPS_LLADDR_LLB_SHIFT 0
819#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
820
821/*
822 * Bits in the MIPS32 Memory Segmentation registers.
823 */
824#define MIPS_SEGCFG_PA_SHIFT 9
825#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
826#define MIPS_SEGCFG_AM_SHIFT 4
827#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
828#define MIPS_SEGCFG_EU_SHIFT 3
829#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
830#define MIPS_SEGCFG_C_SHIFT 0
831#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
832
833#define MIPS_SEGCFG_UUSK _ULCAST_(7)
834#define MIPS_SEGCFG_USK _ULCAST_(5)
835#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
836#define MIPS_SEGCFG_MUSK _ULCAST_(3)
837#define MIPS_SEGCFG_MSK _ULCAST_(2)
838#define MIPS_SEGCFG_MK _ULCAST_(1)
839#define MIPS_SEGCFG_UK _ULCAST_(0)
840
841#define MIPS_PWFIELD_GDI_SHIFT 24
842#define MIPS_PWFIELD_GDI_MASK 0x3f000000
843#define MIPS_PWFIELD_UDI_SHIFT 18
844#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
845#define MIPS_PWFIELD_MDI_SHIFT 12
846#define MIPS_PWFIELD_MDI_MASK 0x0003f000
847#define MIPS_PWFIELD_PTI_SHIFT 6
848#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
849#define MIPS_PWFIELD_PTEI_SHIFT 0
850#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
851
852#define MIPS_PWSIZE_PS_SHIFT 30
853#define MIPS_PWSIZE_PS_MASK 0x40000000
854#define MIPS_PWSIZE_GDW_SHIFT 24
855#define MIPS_PWSIZE_GDW_MASK 0x3f000000
856#define MIPS_PWSIZE_UDW_SHIFT 18
857#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
858#define MIPS_PWSIZE_MDW_SHIFT 12
859#define MIPS_PWSIZE_MDW_MASK 0x0003f000
860#define MIPS_PWSIZE_PTW_SHIFT 6
861#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
862#define MIPS_PWSIZE_PTEW_SHIFT 0
863#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
864
865#define MIPS_PWCTL_PWEN_SHIFT 31
866#define MIPS_PWCTL_PWEN_MASK 0x80000000
867#define MIPS_PWCTL_XK_SHIFT 28
868#define MIPS_PWCTL_XK_MASK 0x10000000
869#define MIPS_PWCTL_XS_SHIFT 27
870#define MIPS_PWCTL_XS_MASK 0x08000000
871#define MIPS_PWCTL_XU_SHIFT 26
872#define MIPS_PWCTL_XU_MASK 0x04000000
873#define MIPS_PWCTL_DPH_SHIFT 7
874#define MIPS_PWCTL_DPH_MASK 0x00000080
875#define MIPS_PWCTL_HUGEPG_SHIFT 6
876#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
877#define MIPS_PWCTL_PSN_SHIFT 0
878#define MIPS_PWCTL_PSN_MASK 0x0000003f
879
880/* GuestCtl0 fields */
881#define MIPS_GCTL0_GM_SHIFT 31
882#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
883#define MIPS_GCTL0_RI_SHIFT 30
884#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
885#define MIPS_GCTL0_MC_SHIFT 29
886#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
887#define MIPS_GCTL0_CP0_SHIFT 28
888#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
889#define MIPS_GCTL0_AT_SHIFT 26
890#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
891#define MIPS_GCTL0_GT_SHIFT 25
892#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
893#define MIPS_GCTL0_CG_SHIFT 24
894#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
895#define MIPS_GCTL0_CF_SHIFT 23
896#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
897#define MIPS_GCTL0_G1_SHIFT 22
898#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
899#define MIPS_GCTL0_G0E_SHIFT 19
900#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
901#define MIPS_GCTL0_PT_SHIFT 18
902#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
903#define MIPS_GCTL0_RAD_SHIFT 9
904#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
905#define MIPS_GCTL0_DRG_SHIFT 8
906#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
907#define MIPS_GCTL0_G2_SHIFT 7
908#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
909#define MIPS_GCTL0_GEXC_SHIFT 2
910#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
911#define MIPS_GCTL0_SFC2_SHIFT 1
912#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
913#define MIPS_GCTL0_SFC1_SHIFT 0
914#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
915
916/* GuestCtl0.AT Guest address translation control */
917#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
918#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
919
920/* GuestCtl0.GExcCode Hypervisor exception cause codes */
921#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
922#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
923#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
924#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
925#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
926#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
927#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
928
929/* GuestCtl0Ext fields */
930#define MIPS_GCTL0EXT_RPW_SHIFT 8
931#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
932#define MIPS_GCTL0EXT_NCC_SHIFT 6
933#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
934#define MIPS_GCTL0EXT_CGI_SHIFT 4
935#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
936#define MIPS_GCTL0EXT_FCD_SHIFT 3
937#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
938#define MIPS_GCTL0EXT_OG_SHIFT 2
939#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
940#define MIPS_GCTL0EXT_BG_SHIFT 1
941#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
942#define MIPS_GCTL0EXT_MG_SHIFT 0
943#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
944
945/* GuestCtl0Ext.RPW Root page walk configuration */
946#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
947#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
948#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
949
950/* GuestCtl0Ext.NCC Nested cache coherency attributes */
951#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
952#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
953
954/* GuestCtl1 fields */
955#define MIPS_GCTL1_ID_SHIFT 0
956#define MIPS_GCTL1_ID_WIDTH 8
957#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
958#define MIPS_GCTL1_RID_SHIFT 16
959#define MIPS_GCTL1_RID_WIDTH 8
960#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
961#define MIPS_GCTL1_EID_SHIFT 24
962#define MIPS_GCTL1_EID_WIDTH 8
963#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
964
965/* GuestID reserved for root context */
966#define MIPS_GCTL1_ROOT_GUESTID 0
967
968/* CDMMBase register bit definitions */
969#define MIPS_CDMMBASE_SIZE_SHIFT 0
970#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
971#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
972#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
973#define MIPS_CDMMBASE_ADDR_SHIFT 11
974#define MIPS_CDMMBASE_ADDR_START 15
975
976/* RDHWR register numbers */
977#define MIPS_HWR_CPUNUM 0 /* CPU number */
978#define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
979#define MIPS_HWR_CC 2 /* Cycle counter */
980#define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
981#define MIPS_HWR_ULR 29 /* UserLocal */
982#define MIPS_HWR_IMPL1 30 /* Implementation dependent */
983#define MIPS_HWR_IMPL2 31 /* Implementation dependent */
984
985/* Bits in HWREna register */
986#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
987#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
988#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
989#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
990#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
991#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
992#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
993
994/*
995 * Bitfields in the TX39 family CP0 Configuration Register 3
996 */
997#define TX39_CONF_ICS_SHIFT 19
998#define TX39_CONF_ICS_MASK 0x00380000
999#define TX39_CONF_ICS_1KB 0x00000000
1000#define TX39_CONF_ICS_2KB 0x00080000
1001#define TX39_CONF_ICS_4KB 0x00100000
1002#define TX39_CONF_ICS_8KB 0x00180000
1003#define TX39_CONF_ICS_16KB 0x00200000
1004
1005#define TX39_CONF_DCS_SHIFT 16
1006#define TX39_CONF_DCS_MASK 0x00070000
1007#define TX39_CONF_DCS_1KB 0x00000000
1008#define TX39_CONF_DCS_2KB 0x00010000
1009#define TX39_CONF_DCS_4KB 0x00020000
1010#define TX39_CONF_DCS_8KB 0x00030000
1011#define TX39_CONF_DCS_16KB 0x00040000
1012
1013#define TX39_CONF_CWFON 0x00004000
1014#define TX39_CONF_WBON 0x00002000
1015#define TX39_CONF_RF_SHIFT 10
1016#define TX39_CONF_RF_MASK 0x00000c00
1017#define TX39_CONF_DOZE 0x00000200
1018#define TX39_CONF_HALT 0x00000100
1019#define TX39_CONF_LOCK 0x00000080
1020#define TX39_CONF_ICE 0x00000020
1021#define TX39_CONF_DCE 0x00000010
1022#define TX39_CONF_IRSIZE_SHIFT 2
1023#define TX39_CONF_IRSIZE_MASK 0x0000000c
1024#define TX39_CONF_DRSIZE_SHIFT 0
1025#define TX39_CONF_DRSIZE_MASK 0x00000003
1026
1027/*
1028 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
1029 */
1030/* Disable Branch Target Address Cache */
1031#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
1032/* Enable Branch Prediction Global History */
1033#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
1034/* Disable Branch Return Cache */
1035#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
1036
1037/* Flush BTB */
1038#define LOONGSON_DIAG_BTB (_ULCAST_(1) << 1)
1039/* Flush ITLB */
1040#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
1041/* Flush DTLB */
1042#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
1043/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
1044#define LOONGSON_DIAG_UCAC (_ULCAST_(1) << 8)
1045/* Flush VTLB */
1046#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
1047/* Flush FTLB */
1048#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
1049
1050/*
1051 * Diag1 (GSCause in Loongson-speak) fields
1052 */
1053/* Loongson-specific exception code (GSExcCode) */
1054#define LOONGSON_DIAG1_EXCCODE_SHIFT 2
1055#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)
1056
1057/* CvmCtl register field definitions */
1058#define CVMCTL_IPPCI_SHIFT 7
1059#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1060#define CVMCTL_IPTI_SHIFT 4
1061#define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1062
1063/* CvmMemCtl2 register field definitions */
1064#define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1065
1066/* CvmVMConfig register field definitions */
1067#define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1068#define CVMVMCONF_MMUSIZEM1_S 12
1069#define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1070#define CVMVMCONF_RMMUSIZEM1_S 0
1071#define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1072
1073/* Debug register field definitions */
1074#define MIPS_DEBUG_DBP_SHIFT 1
1075#define MIPS_DEBUG_DBP (_ULCAST_(1) << MIPS_DEBUG_DBP_SHIFT)
1076
1077/*
1078 * Coprocessor 1 (FPU) register names
1079 */
1080#define CP1_REVISION $0
1081#define CP1_UFR $1
1082#define CP1_UNFR $4
1083#define CP1_FCCR $25
1084#define CP1_FEXR $26
1085#define CP1_FENR $28
1086#define CP1_STATUS $31
1087
1088
1089/*
1090 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1091 */
1092#define MIPS_FPIR_S (_ULCAST_(1) << 16)
1093#define MIPS_FPIR_D (_ULCAST_(1) << 17)
1094#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1095#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1096#define MIPS_FPIR_W (_ULCAST_(1) << 20)
1097#define MIPS_FPIR_L (_ULCAST_(1) << 21)
1098#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1099#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1100#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1101#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1102
1103/*
1104 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1105 */
1106#define MIPS_FCCR_CONDX_S 0
1107#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1108#define MIPS_FCCR_COND0_S 0
1109#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1110#define MIPS_FCCR_COND1_S 1
1111#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1112#define MIPS_FCCR_COND2_S 2
1113#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1114#define MIPS_FCCR_COND3_S 3
1115#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1116#define MIPS_FCCR_COND4_S 4
1117#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1118#define MIPS_FCCR_COND5_S 5
1119#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1120#define MIPS_FCCR_COND6_S 6
1121#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1122#define MIPS_FCCR_COND7_S 7
1123#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1124
1125/*
1126 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1127 */
1128#define MIPS_FENR_FS_S 2
1129#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1130
1131/*
1132 * FPU Status Register Values
1133 */
1134#define FPU_CSR_COND_S 23 /* $fcc0 */
1135#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1136
1137#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1138#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1139
1140#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1141#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1142#define FPU_CSR_COND1_S 25 /* $fcc1 */
1143#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1144#define FPU_CSR_COND2_S 26 /* $fcc2 */
1145#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1146#define FPU_CSR_COND3_S 27 /* $fcc3 */
1147#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1148#define FPU_CSR_COND4_S 28 /* $fcc4 */
1149#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1150#define FPU_CSR_COND5_S 29 /* $fcc5 */
1151#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1152#define FPU_CSR_COND6_S 30 /* $fcc6 */
1153#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1154#define FPU_CSR_COND7_S 31 /* $fcc7 */
1155#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1156
1157/*
1158 * Bits 22:20 of the FPU Status Register will be read as 0,
1159 * and should be written as zero.
1160 * MAC2008 was removed in Release 5 so we still treat it as
1161 * reserved.
1162 */
1163#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1164
1165#define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1166#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1167#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1168
1169/*
1170 * X the exception cause indicator
1171 * E the exception enable
1172 * S the sticky/flag bit
1173*/
1174#define FPU_CSR_ALL_X 0x0003f000
1175#define FPU_CSR_UNI_X 0x00020000
1176#define FPU_CSR_INV_X 0x00010000
1177#define FPU_CSR_DIV_X 0x00008000
1178#define FPU_CSR_OVF_X 0x00004000
1179#define FPU_CSR_UDF_X 0x00002000
1180#define FPU_CSR_INE_X 0x00001000
1181
1182#define FPU_CSR_ALL_E 0x00000f80
1183#define FPU_CSR_INV_E 0x00000800
1184#define FPU_CSR_DIV_E 0x00000400
1185#define FPU_CSR_OVF_E 0x00000200
1186#define FPU_CSR_UDF_E 0x00000100
1187#define FPU_CSR_INE_E 0x00000080
1188
1189#define FPU_CSR_ALL_S 0x0000007c
1190#define FPU_CSR_INV_S 0x00000040
1191#define FPU_CSR_DIV_S 0x00000020
1192#define FPU_CSR_OVF_S 0x00000010
1193#define FPU_CSR_UDF_S 0x00000008
1194#define FPU_CSR_INE_S 0x00000004
1195
1196/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1197#define FPU_CSR_RM 0x00000003
1198#define FPU_CSR_RN 0x0 /* nearest */
1199#define FPU_CSR_RZ 0x1 /* towards zero */
1200#define FPU_CSR_RU 0x2 /* towards +Infinity */
1201#define FPU_CSR_RD 0x3 /* towards -Infinity */
1202
1203
1204#ifndef __ASSEMBLY__
1205
1206/*
1207 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1208 */
1209#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1210 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1211#define get_isa16_mode(x) ((x) & 0x1)
1212#define msk_isa16_mode(x) ((x) & ~0x1)
1213#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1214#else
1215#define get_isa16_mode(x) 0
1216#define msk_isa16_mode(x) (x)
1217#define set_isa16_mode(x) do { } while(0)
1218#endif
1219
1220/*
1221 * microMIPS instructions can be 16-bit or 32-bit in length. This
1222 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1223 */
1224static inline int mm_insn_16bit(u16 insn)
1225{
1226 u16 opcode = (insn >> 10) & 0x7;
1227
1228 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1229}
1230
1231/*
1232 * Helper macros for generating raw instruction encodings in inline asm.
1233 */
1234#ifdef CONFIG_CPU_MICROMIPS
1235#define _ASM_INSN16_IF_MM(_enc) \
1236 ".insn\n\t" \
1237 ".hword (" #_enc ")\n\t"
1238#define _ASM_INSN32_IF_MM(_enc) \
1239 ".insn\n\t" \
1240 ".hword ((" #_enc ") >> 16)\n\t" \
1241 ".hword ((" #_enc ") & 0xffff)\n\t"
1242#else
1243#define _ASM_INSN_IF_MIPS(_enc) \
1244 ".insn\n\t" \
1245 ".word (" #_enc ")\n\t"
1246#endif
1247
1248#ifndef _ASM_INSN16_IF_MM
1249#define _ASM_INSN16_IF_MM(_enc)
1250#endif
1251#ifndef _ASM_INSN32_IF_MM
1252#define _ASM_INSN32_IF_MM(_enc)
1253#endif
1254#ifndef _ASM_INSN_IF_MIPS
1255#define _ASM_INSN_IF_MIPS(_enc)
1256#endif
1257
1258/*
1259 * parse_r var, r - Helper assembler macro for parsing register names.
1260 *
1261 * This converts the register name in $n form provided in \r to the
1262 * corresponding register number, which is assigned to the variable \var. It is
1263 * needed to allow explicit encoding of instructions in inline assembly where
1264 * registers are chosen by the compiler in $n form, allowing us to avoid using
1265 * fixed register numbers.
1266 *
1267 * It also allows newer instructions (not implemented by the assembler) to be
1268 * transparently implemented using assembler macros, instead of needing separate
1269 * cases depending on toolchain support.
1270 *
1271 * Simple usage example:
1272 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1273 * ".insn\n\t"
1274 * "# di %0\n\t"
1275 * ".word (0x41606000 | (__rt << 16))"
1276 * : "=r" (status);
1277 */
1278
1279/* Match an individual register number and assign to \var */
1280#define _IFC_REG(n) \
1281 ".ifc \\r, $" #n "\n\t" \
1282 "\\var = " #n "\n\t" \
1283 ".endif\n\t"
1284
1285#define _ASM_SET_PARSE_R \
1286 ".macro parse_r var r\n\t" \
1287 "\\var = -1\n\t" \
1288 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) \
1289 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) \
1290 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) \
1291 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) \
1292 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) \
1293 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) \
1294 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) \
1295 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) \
1296 ".iflt \\var\n\t" \
1297 ".error \"Unable to parse register name \\r\"\n\t" \
1298 ".endif\n\t" \
1299 ".endm\n\t"
1300#define _ASM_UNSET_PARSE_R ".purgem parse_r\n\t"
1301
1302/*
1303 * C macros for generating assembler macros for common instruction formats.
1304 *
1305 * The names of the operands can be chosen by the caller, and the encoding of
1306 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1307 * the ENC encodings.
1308 */
1309
1310/* Instructions with 1 register operand & 1 immediate operand */
1311#define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
1312 ".macro " #OP " " #R1 ", " #I2 "\n\t" \
1313 _ASM_SET_PARSE_R \
1314 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1315 ENC \
1316 _ASM_UNSET_PARSE_R \
1317 ".endm\n\t"
1318
1319/* Instructions with 2 register operands */
1320#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1321 ".macro " #OP " " #R1 ", " #R2 "\n\t" \
1322 _ASM_SET_PARSE_R \
1323 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1324 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1325 ENC \
1326 _ASM_UNSET_PARSE_R \
1327 ".endm\n\t"
1328
1329/* Instructions with 3 register operands */
1330#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1331 ".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1332 _ASM_SET_PARSE_R \
1333 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1334 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1335 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1336 ENC \
1337 _ASM_UNSET_PARSE_R \
1338 ".endm\n\t"
1339
1340/* Instructions with 2 register operands and 1 optional select operand */
1341#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1342 ".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1343 _ASM_SET_PARSE_R \
1344 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1345 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1346 ENC \
1347 _ASM_UNSET_PARSE_R \
1348 ".endm\n\t"
1349
1350/*
1351 * TLB Invalidate Flush
1352 */
1353static inline void tlbinvf(void)
1354{
1355 __asm__ __volatile__(
1356 ".set push\n\t"
1357 ".set noreorder\n\t"
1358 "# tlbinvf\n\t"
1359 _ASM_INSN_IF_MIPS(0x42000004)
1360 _ASM_INSN32_IF_MM(0x0000537c)
1361 ".set pop");
1362}
1363
1364
1365/*
1366 * Functions to access the R10000 performance counters. These are basically
1367 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1368 * performance counter number encoded into bits 1 ... 5 of the instruction.
1369 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1370 * disassembler these will look like an access to sel 0 or 1.
1371 */
1372#define read_r10k_perf_cntr(counter) \
1373({ \
1374 unsigned int __res; \
1375 __asm__ __volatile__( \
1376 "mfpc\t%0, %1" \
1377 : "=r" (__res) \
1378 : "i" (counter)); \
1379 \
1380 __res; \
1381})
1382
1383#define write_r10k_perf_cntr(counter,val) \
1384do { \
1385 __asm__ __volatile__( \
1386 "mtpc\t%0, %1" \
1387 : \
1388 : "r" (val), "i" (counter)); \
1389} while (0)
1390
1391#define read_r10k_perf_event(counter) \
1392({ \
1393 unsigned int __res; \
1394 __asm__ __volatile__( \
1395 "mfps\t%0, %1" \
1396 : "=r" (__res) \
1397 : "i" (counter)); \
1398 \
1399 __res; \
1400})
1401
1402#define write_r10k_perf_cntl(counter,val) \
1403do { \
1404 __asm__ __volatile__( \
1405 "mtps\t%0, %1" \
1406 : \
1407 : "r" (val), "i" (counter)); \
1408} while (0)
1409
1410
1411/*
1412 * Macros to access the system control coprocessor
1413 */
1414
1415#define ___read_32bit_c0_register(source, sel, vol) \
1416({ unsigned int __res; \
1417 if (sel == 0) \
1418 __asm__ vol( \
1419 "mfc0\t%0, " #source "\n\t" \
1420 : "=r" (__res)); \
1421 else \
1422 __asm__ vol( \
1423 ".set\tpush\n\t" \
1424 ".set\tmips32\n\t" \
1425 "mfc0\t%0, " #source ", " #sel "\n\t" \
1426 ".set\tpop\n\t" \
1427 : "=r" (__res)); \
1428 __res; \
1429})
1430
1431#define ___read_64bit_c0_register(source, sel, vol) \
1432({ unsigned long long __res; \
1433 if (sizeof(unsigned long) == 4) \
1434 __res = __read_64bit_c0_split(source, sel, vol); \
1435 else if (sel == 0) \
1436 __asm__ vol( \
1437 ".set\tpush\n\t" \
1438 ".set\tmips3\n\t" \
1439 "dmfc0\t%0, " #source "\n\t" \
1440 ".set\tpop" \
1441 : "=r" (__res)); \
1442 else \
1443 __asm__ vol( \
1444 ".set\tpush\n\t" \
1445 ".set\tmips64\n\t" \
1446 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1447 ".set\tpop" \
1448 : "=r" (__res)); \
1449 __res; \
1450})
1451
1452#define __read_32bit_c0_register(source, sel) \
1453 ___read_32bit_c0_register(source, sel, __volatile__)
1454
1455#define __read_const_32bit_c0_register(source, sel) \
1456 ___read_32bit_c0_register(source, sel,)
1457
1458#define __read_64bit_c0_register(source, sel) \
1459 ___read_64bit_c0_register(source, sel, __volatile__)
1460
1461#define __read_const_64bit_c0_register(source, sel) \
1462 ___read_64bit_c0_register(source, sel,)
1463
1464#define __write_32bit_c0_register(register, sel, value) \
1465do { \
1466 if (sel == 0) \
1467 __asm__ __volatile__( \
1468 "mtc0\t%z0, " #register "\n\t" \
1469 : : "Jr" ((unsigned int)(value))); \
1470 else \
1471 __asm__ __volatile__( \
1472 ".set\tpush\n\t" \
1473 ".set\tmips32\n\t" \
1474 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1475 ".set\tpop" \
1476 : : "Jr" ((unsigned int)(value))); \
1477} while (0)
1478
1479#define __write_64bit_c0_register(register, sel, value) \
1480do { \
1481 if (sizeof(unsigned long) == 4) \
1482 __write_64bit_c0_split(register, sel, value); \
1483 else if (sel == 0) \
1484 __asm__ __volatile__( \
1485 ".set\tpush\n\t" \
1486 ".set\tmips3\n\t" \
1487 "dmtc0\t%z0, " #register "\n\t" \
1488 ".set\tpop" \
1489 : : "Jr" (value)); \
1490 else \
1491 __asm__ __volatile__( \
1492 ".set\tpush\n\t" \
1493 ".set\tmips64\n\t" \
1494 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1495 ".set\tpop" \
1496 : : "Jr" (value)); \
1497} while (0)
1498
1499#define __read_ulong_c0_register(reg, sel) \
1500 ((sizeof(unsigned long) == 4) ? \
1501 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1502 (unsigned long) __read_64bit_c0_register(reg, sel))
1503
1504#define __read_const_ulong_c0_register(reg, sel) \
1505 ((sizeof(unsigned long) == 4) ? \
1506 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1507 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1508
1509#define __write_ulong_c0_register(reg, sel, val) \
1510do { \
1511 if (sizeof(unsigned long) == 4) \
1512 __write_32bit_c0_register(reg, sel, val); \
1513 else \
1514 __write_64bit_c0_register(reg, sel, val); \
1515} while (0)
1516
1517/*
1518 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1519 */
1520#define __read_32bit_c0_ctrl_register(source) \
1521({ unsigned int __res; \
1522 __asm__ __volatile__( \
1523 "cfc0\t%0, " #source "\n\t" \
1524 : "=r" (__res)); \
1525 __res; \
1526})
1527
1528#define __write_32bit_c0_ctrl_register(register, value) \
1529do { \
1530 __asm__ __volatile__( \
1531 "ctc0\t%z0, " #register "\n\t" \
1532 : : "Jr" ((unsigned int)(value))); \
1533} while (0)
1534
1535/*
1536 * These versions are only needed for systems with more than 38 bits of
1537 * physical address space running the 32-bit kernel. That's none atm :-)
1538 */
1539#define __read_64bit_c0_split(source, sel, vol) \
1540({ \
1541 unsigned long long __val; \
1542 unsigned long __flags; \
1543 \
1544 local_irq_save(__flags); \
1545 if (sel == 0) \
1546 __asm__ vol( \
1547 ".set\tpush\n\t" \
1548 ".set\tmips64\n\t" \
1549 "dmfc0\t%L0, " #source "\n\t" \
1550 "dsra\t%M0, %L0, 32\n\t" \
1551 "sll\t%L0, %L0, 0\n\t" \
1552 ".set\tpop" \
1553 : "=r" (__val)); \
1554 else \
1555 __asm__ vol( \
1556 ".set\tpush\n\t" \
1557 ".set\tmips64\n\t" \
1558 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1559 "dsra\t%M0, %L0, 32\n\t" \
1560 "sll\t%L0, %L0, 0\n\t" \
1561 ".set\tpop" \
1562 : "=r" (__val)); \
1563 local_irq_restore(__flags); \
1564 \
1565 __val; \
1566})
1567
1568#define __write_64bit_c0_split(source, sel, val) \
1569do { \
1570 unsigned long long __tmp = (val); \
1571 unsigned long __flags; \
1572 \
1573 local_irq_save(__flags); \
1574 if (MIPS_ISA_REV >= 2) \
1575 __asm__ __volatile__( \
1576 ".set\tpush\n\t" \
1577 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1578 "dins\t%L0, %M0, 32, 32\n\t" \
1579 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1580 ".set\tpop" \
1581 : "+r" (__tmp)); \
1582 else if (sel == 0) \
1583 __asm__ __volatile__( \
1584 ".set\tpush\n\t" \
1585 ".set\tmips64\n\t" \
1586 "dsll\t%L0, %L0, 32\n\t" \
1587 "dsrl\t%L0, %L0, 32\n\t" \
1588 "dsll\t%M0, %M0, 32\n\t" \
1589 "or\t%L0, %L0, %M0\n\t" \
1590 "dmtc0\t%L0, " #source "\n\t" \
1591 ".set\tpop" \
1592 : "+r" (__tmp)); \
1593 else \
1594 __asm__ __volatile__( \
1595 ".set\tpush\n\t" \
1596 ".set\tmips64\n\t" \
1597 "dsll\t%L0, %L0, 32\n\t" \
1598 "dsrl\t%L0, %L0, 32\n\t" \
1599 "dsll\t%M0, %M0, 32\n\t" \
1600 "or\t%L0, %L0, %M0\n\t" \
1601 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1602 ".set\tpop" \
1603 : "+r" (__tmp)); \
1604 local_irq_restore(__flags); \
1605} while (0)
1606
1607#ifndef TOOLCHAIN_SUPPORTS_XPA
1608#define _ASM_SET_MFHC0 \
1609 _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel, \
1610 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) \
1611 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11))
1612#define _ASM_UNSET_MFHC0 ".purgem mfhc0\n\t"
1613#define _ASM_SET_MTHC0 \
1614 _ASM_MACRO_2R_1S(mthc0, rt, rd, sel, \
1615 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) \
1616 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11))
1617#define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t"
1618#else /* !TOOLCHAIN_SUPPORTS_XPA */
1619#define _ASM_SET_MFHC0 ".set\txpa\n\t"
1620#define _ASM_SET_MTHC0 ".set\txpa\n\t"
1621#define _ASM_UNSET_MFHC0
1622#define _ASM_UNSET_MTHC0
1623#endif
1624
1625#define __readx_32bit_c0_register(source, sel) \
1626({ \
1627 unsigned int __res; \
1628 \
1629 __asm__ __volatile__( \
1630 " .set push \n" \
1631 " .set mips32r2 \n" \
1632 _ASM_SET_MFHC0 \
1633 " mfhc0 %0, " #source ", %1 \n" \
1634 _ASM_UNSET_MFHC0 \
1635 " .set pop \n" \
1636 : "=r" (__res) \
1637 : "i" (sel)); \
1638 __res; \
1639})
1640
1641#define __writex_32bit_c0_register(register, sel, value) \
1642do { \
1643 __asm__ __volatile__( \
1644 " .set push \n" \
1645 " .set mips32r2 \n" \
1646 _ASM_SET_MTHC0 \
1647 " mthc0 %z0, " #register ", %1 \n" \
1648 _ASM_UNSET_MTHC0 \
1649 " .set pop \n" \
1650 : \
1651 : "Jr" (value), "i" (sel)); \
1652} while (0)
1653
1654#define read_c0_index() __read_32bit_c0_register($0, 0)
1655#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1656
1657#define read_c0_random() __read_32bit_c0_register($1, 0)
1658#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1659
1660#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1661#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1662
1663#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1664#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1665
1666#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1667#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1668
1669#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1670#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1671
1672#define read_c0_conf() __read_32bit_c0_register($3, 0)
1673#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1674
1675#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1676
1677#define read_c0_context() __read_ulong_c0_register($4, 0)
1678#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1679
1680#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1681#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1682
1683#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1684#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1685
1686#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1687#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1688
1689#define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
1690#define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
1691
1692#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1693#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1694
1695#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1696#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1697
1698#define read_c0_wired() __read_32bit_c0_register($6, 0)
1699#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1700
1701#define read_c0_info() __read_32bit_c0_register($7, 0)
1702
1703#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1704#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1705
1706#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1707#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1708
1709#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1710#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1711
1712#define read_c0_count() __read_32bit_c0_register($9, 0)
1713#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1714
1715#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1716#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1717
1718#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1719#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1720
1721#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1722#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1723
1724#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1725#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1726
1727#define read_c0_compare() __read_32bit_c0_register($11, 0)
1728#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1729
1730#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1731#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1732
1733#define read_c0_status() __read_32bit_c0_register($12, 0)
1734
1735#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1736
1737#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1738#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1739
1740#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1741#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1742
1743#define read_c0_cause() __read_32bit_c0_register($13, 0)
1744#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1745
1746#define read_c0_epc() __read_ulong_c0_register($14, 0)
1747#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1748
1749#define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1750
1751#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1752
1753#define read_c0_config() __read_32bit_c0_register($16, 0)
1754#define read_c0_config1() __read_32bit_c0_register($16, 1)
1755#define read_c0_config2() __read_32bit_c0_register($16, 2)
1756#define read_c0_config3() __read_32bit_c0_register($16, 3)
1757#define read_c0_config4() __read_32bit_c0_register($16, 4)
1758#define read_c0_config5() __read_32bit_c0_register($16, 5)
1759#define read_c0_config6() __read_32bit_c0_register($16, 6)
1760#define read_c0_config7() __read_32bit_c0_register($16, 7)
1761#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1762#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1763#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1764#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1765#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1766#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1767#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1768#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1769
1770#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1771#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1772#define read_c0_maar() __read_ulong_c0_register($17, 1)
1773#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1774#define readx_c0_maar() __readx_32bit_c0_register($17, 1)
1775#define writex_c0_maar(val) __writex_32bit_c0_register($17, 1, val)
1776#define read_c0_maari() __read_32bit_c0_register($17, 2)
1777#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1778
1779/*
1780 * The WatchLo register. There may be up to 8 of them.
1781 */
1782#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1783#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1784#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1785#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1786#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1787#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1788#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1789#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1790#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1791#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1792#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1793#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1794#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1795#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1796#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1797#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1798
1799/*
1800 * The WatchHi register. There may be up to 8 of them.
1801 */
1802#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1803#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1804#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1805#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1806#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1807#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1808#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1809#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1810
1811#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1812#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1813#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1814#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1815#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1816#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1817#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1818#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1819
1820#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1821#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1822
1823#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1824#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1825
1826#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1827#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1828
1829#define read_c0_diag() __read_32bit_c0_register($22, 0)
1830#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1831
1832/* R10K CP0 Branch Diagnostic register is 64bits wide */
1833#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1834#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1835
1836#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1837#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1838
1839#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1840#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1841
1842#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1843#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1844
1845#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1846#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1847
1848#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1849#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1850
1851#define read_c0_debug() __read_32bit_c0_register($23, 0)
1852#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1853
1854#define read_c0_depc() __read_ulong_c0_register($24, 0)
1855#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1856
1857/*
1858 * MIPS32 / MIPS64 performance counters
1859 */
1860#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1861#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1862#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1863#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1864#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1865#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1866#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1867#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1868#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1869#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1870#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1871#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1872#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1873#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1874#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1875#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1876#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1877#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1878#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1879#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1880#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1881#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1882#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1883#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1884
1885#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1886#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1887
1888#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1889#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1890
1891#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1892
1893#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1894#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1895
1896#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1897#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1898
1899#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1900#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1901
1902#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1903#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1904
1905#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1906#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1907
1908#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1909#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1910
1911#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1912#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1913
1914/* MIPSR2 */
1915#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1916#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1917
1918#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1919#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1920
1921#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1922#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1923
1924#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1925#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1926
1927#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1928#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1929
1930#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1931#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1932
1933#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1934#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1935
1936/* MIPSR3 */
1937#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1938#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1939
1940#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1941#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1942
1943#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1944#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1945
1946/* Hardware Page Table Walker */
1947#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1948#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1949
1950#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1951#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1952
1953#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1954#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1955
1956#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1957#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1958
1959#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1960#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1961
1962#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1963#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1964
1965/* Cavium OCTEON (cnMIPS) */
1966#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1967#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1968
1969#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1970#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1971
1972#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1973#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1974
1975#define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1976#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1977
1978#define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1979#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1980
1981/*
1982 * The cacheerr registers are not standardized. On OCTEON, they are
1983 * 64 bits wide.
1984 */
1985#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1986#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1987
1988#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1989#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1990
1991/* BMIPS3300 */
1992#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1993#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1994
1995#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1996#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1997
1998#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1999#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
2000
2001/* BMIPS43xx */
2002#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
2003#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
2004
2005#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
2006#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
2007
2008#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
2009#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
2010
2011#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
2012#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
2013
2014#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
2015#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
2016
2017/* BMIPS5000 */
2018#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
2019#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
2020
2021#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
2022#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
2023
2024#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
2025#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
2026
2027#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
2028#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
2029
2030#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
2031#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
2032
2033#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
2034#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
2035
2036/* Ingenic page ctrl register */
2037#define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
2038
2039/*
2040 * Macros to access the guest system control coprocessor
2041 */
2042
2043#ifndef TOOLCHAIN_SUPPORTS_VIRT
2044#define _ASM_SET_MFGC0 \
2045 _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel, \
2046 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) \
2047 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2048#define _ASM_UNSET_MFGC0 ".purgem mfgc0\n\t"
2049#define _ASM_SET_DMFGC0 \
2050 _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel, \
2051 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel) \
2052 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2053#define _ASM_UNSET_DMFGC0 ".purgem dmfgc0\n\t"
2054#define _ASM_SET_MTGC0 \
2055 _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel, \
2056 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel) \
2057 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2058#define _ASM_UNSET_MTGC0 ".purgem mtgc0\n\t"
2059#define _ASM_SET_DMTGC0 \
2060 _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel, \
2061 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel) \
2062 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2063#define _ASM_UNSET_DMTGC0 ".purgem dmtgc0\n\t"
2064
2065#define __tlbgp() \
2066 _ASM_INSN_IF_MIPS(0x42000010) \
2067 _ASM_INSN32_IF_MM(0x0000017c)
2068#define __tlbgr() \
2069 _ASM_INSN_IF_MIPS(0x42000009) \
2070 _ASM_INSN32_IF_MM(0x0000117c)
2071#define __tlbgwi() \
2072 _ASM_INSN_IF_MIPS(0x4200000a) \
2073 _ASM_INSN32_IF_MM(0x0000217c)
2074#define __tlbgwr() \
2075 _ASM_INSN_IF_MIPS(0x4200000e) \
2076 _ASM_INSN32_IF_MM(0x0000317c)
2077#define __tlbginvf() \
2078 _ASM_INSN_IF_MIPS(0x4200000c) \
2079 _ASM_INSN32_IF_MM(0x0000517c)
2080#else /* !TOOLCHAIN_SUPPORTS_VIRT */
2081#define _ASM_SET_VIRT ".set\tvirt\n\t"
2082#define _ASM_SET_MFGC0 _ASM_SET_VIRT
2083#define _ASM_SET_DMFGC0 _ASM_SET_VIRT
2084#define _ASM_SET_MTGC0 _ASM_SET_VIRT
2085#define _ASM_SET_DMTGC0 _ASM_SET_VIRT
2086#define _ASM_UNSET_MFGC0
2087#define _ASM_UNSET_DMFGC0
2088#define _ASM_UNSET_MTGC0
2089#define _ASM_UNSET_DMTGC0
2090
2091#define __tlbgp() _ASM_SET_VIRT "tlbgp\n\t"
2092#define __tlbgr() _ASM_SET_VIRT "tlbgr\n\t"
2093#define __tlbgwi() _ASM_SET_VIRT "tlbgwi\n\t"
2094#define __tlbgwr() _ASM_SET_VIRT "tlbgwr\n\t"
2095#define __tlbginvf() _ASM_SET_VIRT "tlbginvf\n\t"
2096#endif
2097
2098#define __read_32bit_gc0_register(source, sel) \
2099({ int __res; \
2100 __asm__ __volatile__( \
2101 ".set\tpush\n\t" \
2102 ".set\tmips32r5\n\t" \
2103 _ASM_SET_MFGC0 \
2104 "mfgc0\t%0, " #source ", %1\n\t" \
2105 _ASM_UNSET_MFGC0 \
2106 ".set\tpop" \
2107 : "=r" (__res) \
2108 : "i" (sel)); \
2109 __res; \
2110})
2111
2112#define __read_64bit_gc0_register(source, sel) \
2113({ unsigned long long __res; \
2114 __asm__ __volatile__( \
2115 ".set\tpush\n\t" \
2116 ".set\tmips64r5\n\t" \
2117 _ASM_SET_DMFGC0 \
2118 "dmfgc0\t%0, " #source ", %1\n\t" \
2119 _ASM_UNSET_DMFGC0 \
2120 ".set\tpop" \
2121 : "=r" (__res) \
2122 : "i" (sel)); \
2123 __res; \
2124})
2125
2126#define __write_32bit_gc0_register(register, sel, value) \
2127do { \
2128 __asm__ __volatile__( \
2129 ".set\tpush\n\t" \
2130 ".set\tmips32r5\n\t" \
2131 _ASM_SET_MTGC0 \
2132 "mtgc0\t%z0, " #register ", %1\n\t" \
2133 _ASM_UNSET_MTGC0 \
2134 ".set\tpop" \
2135 : : "Jr" ((unsigned int)(value)), \
2136 "i" (sel)); \
2137} while (0)
2138
2139#define __write_64bit_gc0_register(register, sel, value) \
2140do { \
2141 __asm__ __volatile__( \
2142 ".set\tpush\n\t" \
2143 ".set\tmips64r5\n\t" \
2144 _ASM_SET_DMTGC0 \
2145 "dmtgc0\t%z0, " #register ", %1\n\t" \
2146 _ASM_UNSET_DMTGC0 \
2147 ".set\tpop" \
2148 : : "Jr" (value), \
2149 "i" (sel)); \
2150} while (0)
2151
2152#define __read_ulong_gc0_register(reg, sel) \
2153 ((sizeof(unsigned long) == 4) ? \
2154 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2155 (unsigned long) __read_64bit_gc0_register(reg, sel))
2156
2157#define __write_ulong_gc0_register(reg, sel, val) \
2158do { \
2159 if (sizeof(unsigned long) == 4) \
2160 __write_32bit_gc0_register(reg, sel, val); \
2161 else \
2162 __write_64bit_gc0_register(reg, sel, val); \
2163} while (0)
2164
2165#define read_gc0_index() __read_32bit_gc0_register($0, 0)
2166#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2167
2168#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2169#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2170
2171#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2172#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2173
2174#define read_gc0_context() __read_ulong_gc0_register($4, 0)
2175#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2176
2177#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2178#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2179
2180#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2181#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2182
2183#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2184#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2185
2186#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2187#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2188
2189#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2190#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2191
2192#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2193#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2194
2195#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2196#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2197
2198#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2199#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2200
2201#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2202#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2203
2204#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2205#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2206
2207#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2208#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2209
2210#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2211#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2212
2213#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2214#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2215
2216#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2217#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2218
2219#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2220#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2221
2222#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2223#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2224
2225#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2226#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2227
2228#define read_gc0_count() __read_32bit_gc0_register($9, 0)
2229
2230#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2231#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2232
2233#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2234#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2235
2236#define read_gc0_status() __read_32bit_gc0_register($12, 0)
2237#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2238
2239#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2240#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2241
2242#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2243#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2244
2245#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2246#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2247
2248#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2249
2250#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2251#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2252
2253#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2254#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2255
2256#define read_gc0_config() __read_32bit_gc0_register($16, 0)
2257#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2258#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2259#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2260#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2261#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2262#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2263#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2264#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2265#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2266#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2267#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2268#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2269#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2270#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2271#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2272
2273#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2274#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2275
2276#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2277#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2278#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2279#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2280#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2281#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2282#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2283#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2284#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2285#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2286#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2287#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2288#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2289#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2290#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2291#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2292
2293#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2294#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2295#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2296#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2297#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2298#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2299#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2300#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2301#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2302#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2303#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2304#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2305#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2306#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2307#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2308#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2309
2310#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2311#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2312
2313#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2314#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2315#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2316#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2317#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2318#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2319#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2320#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2321#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2322#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2323#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2324#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2325#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2326#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2327#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2328#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2329#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2330#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2331#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2332#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2333#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2334#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2335#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2336#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2337
2338#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2339#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2340
2341#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2342#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2343#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2344#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2345#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2346#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2347#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2348#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2349#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2350#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2351#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2352#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2353
2354/* Cavium OCTEON (cnMIPS) */
2355#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2356#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2357
2358#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2359#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2360
2361#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2362#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2363
2364#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2365#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2366
2367/*
2368 * Macros to access the floating point coprocessor control registers
2369 */
2370#define _read_32bit_cp1_register(source, gas_hardfloat) \
2371({ \
2372 unsigned int __res; \
2373 \
2374 __asm__ __volatile__( \
2375 " .set push \n" \
2376 " .set reorder \n" \
2377 " # gas fails to assemble cfc1 for some archs, \n" \
2378 " # like Octeon. \n" \
2379 " .set mips1 \n" \
2380 " "STR(gas_hardfloat)" \n" \
2381 " cfc1 %0,"STR(source)" \n" \
2382 " .set pop \n" \
2383 : "=r" (__res)); \
2384 __res; \
2385})
2386
2387#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2388do { \
2389 __asm__ __volatile__( \
2390 " .set push \n" \
2391 " .set reorder \n" \
2392 " "STR(gas_hardfloat)" \n" \
2393 " ctc1 %0,"STR(dest)" \n" \
2394 " .set pop \n" \
2395 : : "r" (val)); \
2396} while (0)
2397
2398#ifdef GAS_HAS_SET_HARDFLOAT
2399#define read_32bit_cp1_register(source) \
2400 _read_32bit_cp1_register(source, .set hardfloat)
2401#define write_32bit_cp1_register(dest, val) \
2402 _write_32bit_cp1_register(dest, val, .set hardfloat)
2403#else
2404#define read_32bit_cp1_register(source) \
2405 _read_32bit_cp1_register(source, )
2406#define write_32bit_cp1_register(dest, val) \
2407 _write_32bit_cp1_register(dest, val, )
2408#endif
2409
2410#ifdef TOOLCHAIN_SUPPORTS_DSP
2411#define rddsp(mask) \
2412({ \
2413 unsigned int __dspctl; \
2414 \
2415 __asm__ __volatile__( \
2416 " .set push \n" \
2417 " .set " MIPS_ISA_LEVEL " \n" \
2418 " .set dsp \n" \
2419 " rddsp %0, %x1 \n" \
2420 " .set pop \n" \
2421 : "=r" (__dspctl) \
2422 : "i" (mask)); \
2423 __dspctl; \
2424})
2425
2426#define wrdsp(val, mask) \
2427do { \
2428 __asm__ __volatile__( \
2429 " .set push \n" \
2430 " .set " MIPS_ISA_LEVEL " \n" \
2431 " .set dsp \n" \
2432 " wrdsp %0, %x1 \n" \
2433 " .set pop \n" \
2434 : \
2435 : "r" (val), "i" (mask)); \
2436} while (0)
2437
2438#define mflo0() \
2439({ \
2440 long mflo0; \
2441 __asm__( \
2442 " .set push \n" \
2443 " .set " MIPS_ISA_LEVEL " \n" \
2444 " .set dsp \n" \
2445 " mflo %0, $ac0 \n" \
2446 " .set pop \n" \
2447 : "=r" (mflo0)); \
2448 mflo0; \
2449})
2450
2451#define mflo1() \
2452({ \
2453 long mflo1; \
2454 __asm__( \
2455 " .set push \n" \
2456 " .set " MIPS_ISA_LEVEL " \n" \
2457 " .set dsp \n" \
2458 " mflo %0, $ac1 \n" \
2459 " .set pop \n" \
2460 : "=r" (mflo1)); \
2461 mflo1; \
2462})
2463
2464#define mflo2() \
2465({ \
2466 long mflo2; \
2467 __asm__( \
2468 " .set push \n" \
2469 " .set " MIPS_ISA_LEVEL " \n" \
2470 " .set dsp \n" \
2471 " mflo %0, $ac2 \n" \
2472 " .set pop \n" \
2473 : "=r" (mflo2)); \
2474 mflo2; \
2475})
2476
2477#define mflo3() \
2478({ \
2479 long mflo3; \
2480 __asm__( \
2481 " .set push \n" \
2482 " .set " MIPS_ISA_LEVEL " \n" \
2483 " .set dsp \n" \
2484 " mflo %0, $ac3 \n" \
2485 " .set pop \n" \
2486 : "=r" (mflo3)); \
2487 mflo3; \
2488})
2489
2490#define mfhi0() \
2491({ \
2492 long mfhi0; \
2493 __asm__( \
2494 " .set push \n" \
2495 " .set " MIPS_ISA_LEVEL " \n" \
2496 " .set dsp \n" \
2497 " mfhi %0, $ac0 \n" \
2498 " .set pop \n" \
2499 : "=r" (mfhi0)); \
2500 mfhi0; \
2501})
2502
2503#define mfhi1() \
2504({ \
2505 long mfhi1; \
2506 __asm__( \
2507 " .set push \n" \
2508 " .set " MIPS_ISA_LEVEL " \n" \
2509 " .set dsp \n" \
2510 " mfhi %0, $ac1 \n" \
2511 " .set pop \n" \
2512 : "=r" (mfhi1)); \
2513 mfhi1; \
2514})
2515
2516#define mfhi2() \
2517({ \
2518 long mfhi2; \
2519 __asm__( \
2520 " .set push \n" \
2521 " .set " MIPS_ISA_LEVEL " \n" \
2522 " .set dsp \n" \
2523 " mfhi %0, $ac2 \n" \
2524 " .set pop \n" \
2525 : "=r" (mfhi2)); \
2526 mfhi2; \
2527})
2528
2529#define mfhi3() \
2530({ \
2531 long mfhi3; \
2532 __asm__( \
2533 " .set push \n" \
2534 " .set " MIPS_ISA_LEVEL " \n" \
2535 " .set dsp \n" \
2536 " mfhi %0, $ac3 \n" \
2537 " .set pop \n" \
2538 : "=r" (mfhi3)); \
2539 mfhi3; \
2540})
2541
2542
2543#define mtlo0(x) \
2544({ \
2545 __asm__( \
2546 " .set push \n" \
2547 " .set " MIPS_ISA_LEVEL " \n" \
2548 " .set dsp \n" \
2549 " mtlo %0, $ac0 \n" \
2550 " .set pop \n" \
2551 : \
2552 : "r" (x)); \
2553})
2554
2555#define mtlo1(x) \
2556({ \
2557 __asm__( \
2558 " .set push \n" \
2559 " .set " MIPS_ISA_LEVEL " \n" \
2560 " .set dsp \n" \
2561 " mtlo %0, $ac1 \n" \
2562 " .set pop \n" \
2563 : \
2564 : "r" (x)); \
2565})
2566
2567#define mtlo2(x) \
2568({ \
2569 __asm__( \
2570 " .set push \n" \
2571 " .set " MIPS_ISA_LEVEL " \n" \
2572 " .set dsp \n" \
2573 " mtlo %0, $ac2 \n" \
2574 " .set pop \n" \
2575 : \
2576 : "r" (x)); \
2577})
2578
2579#define mtlo3(x) \
2580({ \
2581 __asm__( \
2582 " .set push \n" \
2583 " .set " MIPS_ISA_LEVEL " \n" \
2584 " .set dsp \n" \
2585 " mtlo %0, $ac3 \n" \
2586 " .set pop \n" \
2587 : \
2588 : "r" (x)); \
2589})
2590
2591#define mthi0(x) \
2592({ \
2593 __asm__( \
2594 " .set push \n" \
2595 " .set " MIPS_ISA_LEVEL " \n" \
2596 " .set dsp \n" \
2597 " mthi %0, $ac0 \n" \
2598 " .set pop \n" \
2599 : \
2600 : "r" (x)); \
2601})
2602
2603#define mthi1(x) \
2604({ \
2605 __asm__( \
2606 " .set push \n" \
2607 " .set " MIPS_ISA_LEVEL " \n" \
2608 " .set dsp \n" \
2609 " mthi %0, $ac1 \n" \
2610 " .set pop \n" \
2611 : \
2612 : "r" (x)); \
2613})
2614
2615#define mthi2(x) \
2616({ \
2617 __asm__( \
2618 " .set push \n" \
2619 " .set " MIPS_ISA_LEVEL " \n" \
2620 " .set dsp \n" \
2621 " mthi %0, $ac2 \n" \
2622 " .set pop \n" \
2623 : \
2624 : "r" (x)); \
2625})
2626
2627#define mthi3(x) \
2628({ \
2629 __asm__( \
2630 " .set push \n" \
2631 " .set " MIPS_ISA_LEVEL " \n" \
2632 " .set dsp \n" \
2633 " mthi %0, $ac3 \n" \
2634 " .set pop \n" \
2635 : \
2636 : "r" (x)); \
2637})
2638
2639#else
2640
2641#define rddsp(mask) \
2642({ \
2643 unsigned int __res; \
2644 \
2645 __asm__ __volatile__( \
2646 " .set push \n" \
2647 " .set noat \n" \
2648 " # rddsp $1, %x1 \n" \
2649 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2650 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2651 " move %0, $1 \n" \
2652 " .set pop \n" \
2653 : "=r" (__res) \
2654 : "i" (mask)); \
2655 __res; \
2656})
2657
2658#define wrdsp(val, mask) \
2659do { \
2660 __asm__ __volatile__( \
2661 " .set push \n" \
2662 " .set noat \n" \
2663 " move $1, %0 \n" \
2664 " # wrdsp $1, %x1 \n" \
2665 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2666 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2667 " .set pop \n" \
2668 : \
2669 : "r" (val), "i" (mask)); \
2670} while (0)
2671
2672#define _dsp_mfxxx(ins) \
2673({ \
2674 unsigned long __treg; \
2675 \
2676 __asm__ __volatile__( \
2677 " .set push \n" \
2678 " .set noat \n" \
2679 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2680 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2681 " move %0, $1 \n" \
2682 " .set pop \n" \
2683 : "=r" (__treg) \
2684 : "i" (ins)); \
2685 __treg; \
2686})
2687
2688#define _dsp_mtxxx(val, ins) \
2689do { \
2690 __asm__ __volatile__( \
2691 " .set push \n" \
2692 " .set noat \n" \
2693 " move $1, %0 \n" \
2694 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2695 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2696 " .set pop \n" \
2697 : \
2698 : "r" (val), "i" (ins)); \
2699} while (0)
2700
2701#ifdef CONFIG_CPU_MICROMIPS
2702
2703#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2704#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2705
2706#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2707#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2708
2709#else /* !CONFIG_CPU_MICROMIPS */
2710
2711#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2712#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2713
2714#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2715#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2716
2717#endif /* CONFIG_CPU_MICROMIPS */
2718
2719#define mflo0() _dsp_mflo(0)
2720#define mflo1() _dsp_mflo(1)
2721#define mflo2() _dsp_mflo(2)
2722#define mflo3() _dsp_mflo(3)
2723
2724#define mfhi0() _dsp_mfhi(0)
2725#define mfhi1() _dsp_mfhi(1)
2726#define mfhi2() _dsp_mfhi(2)
2727#define mfhi3() _dsp_mfhi(3)
2728
2729#define mtlo0(x) _dsp_mtlo(x, 0)
2730#define mtlo1(x) _dsp_mtlo(x, 1)
2731#define mtlo2(x) _dsp_mtlo(x, 2)
2732#define mtlo3(x) _dsp_mtlo(x, 3)
2733
2734#define mthi0(x) _dsp_mthi(x, 0)
2735#define mthi1(x) _dsp_mthi(x, 1)
2736#define mthi2(x) _dsp_mthi(x, 2)
2737#define mthi3(x) _dsp_mthi(x, 3)
2738
2739#endif
2740
2741/*
2742 * TLB operations.
2743 *
2744 * It is responsibility of the caller to take care of any TLB hazards.
2745 */
2746static inline void tlb_probe(void)
2747{
2748 __asm__ __volatile__(
2749 ".set noreorder\n\t"
2750 "tlbp\n\t"
2751 ".set reorder");
2752}
2753
2754static inline void tlb_read(void)
2755{
2756#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2757 int res = 0;
2758
2759 __asm__ __volatile__(
2760 " .set push \n"
2761 " .set noreorder \n"
2762 " .set noat \n"
2763 " .set mips32r2 \n"
2764 " .word 0x41610001 # dvpe $1 \n"
2765 " move %0, $1 \n"
2766 " ehb \n"
2767 " .set pop \n"
2768 : "=r" (res));
2769
2770 instruction_hazard();
2771#endif
2772
2773 __asm__ __volatile__(
2774 ".set noreorder\n\t"
2775 "tlbr\n\t"
2776 ".set reorder");
2777
2778#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2779 if ((res & _ULCAST_(1)))
2780 __asm__ __volatile__(
2781 " .set push \n"
2782 " .set noreorder \n"
2783 " .set noat \n"
2784 " .set mips32r2 \n"
2785 " .word 0x41600021 # evpe \n"
2786 " ehb \n"
2787 " .set pop \n");
2788#endif
2789}
2790
2791static inline void tlb_write_indexed(void)
2792{
2793 __asm__ __volatile__(
2794 ".set noreorder\n\t"
2795 "tlbwi\n\t"
2796 ".set reorder");
2797}
2798
2799static inline void tlb_write_random(void)
2800{
2801 __asm__ __volatile__(
2802 ".set noreorder\n\t"
2803 "tlbwr\n\t"
2804 ".set reorder");
2805}
2806
2807/*
2808 * Guest TLB operations.
2809 *
2810 * It is responsibility of the caller to take care of any TLB hazards.
2811 */
2812static inline void guest_tlb_probe(void)
2813{
2814 __asm__ __volatile__(
2815 ".set push\n\t"
2816 ".set noreorder\n\t"
2817 __tlbgp()
2818 ".set pop");
2819}
2820
2821static inline void guest_tlb_read(void)
2822{
2823 __asm__ __volatile__(
2824 ".set push\n\t"
2825 ".set noreorder\n\t"
2826 __tlbgr()
2827 ".set pop");
2828}
2829
2830static inline void guest_tlb_write_indexed(void)
2831{
2832 __asm__ __volatile__(
2833 ".set push\n\t"
2834 ".set noreorder\n\t"
2835 __tlbgwi()
2836 ".set pop");
2837}
2838
2839static inline void guest_tlb_write_random(void)
2840{
2841 __asm__ __volatile__(
2842 ".set push\n\t"
2843 ".set noreorder\n\t"
2844 __tlbgwr()
2845 ".set pop");
2846}
2847
2848/*
2849 * Guest TLB Invalidate Flush
2850 */
2851static inline void guest_tlbinvf(void)
2852{
2853 __asm__ __volatile__(
2854 ".set push\n\t"
2855 ".set noreorder\n\t"
2856 __tlbginvf()
2857 ".set pop");
2858}
2859
2860/*
2861 * Manipulate bits in a register.
2862 */
2863#define __BUILD_SET_COMMON(name) \
2864static inline unsigned int \
2865set_##name(unsigned int set) \
2866{ \
2867 unsigned int res, new; \
2868 \
2869 res = read_##name(); \
2870 new = res | set; \
2871 write_##name(new); \
2872 \
2873 return res; \
2874} \
2875 \
2876static inline unsigned int \
2877clear_##name(unsigned int clear) \
2878{ \
2879 unsigned int res, new; \
2880 \
2881 res = read_##name(); \
2882 new = res & ~clear; \
2883 write_##name(new); \
2884 \
2885 return res; \
2886} \
2887 \
2888static inline unsigned int \
2889change_##name(unsigned int change, unsigned int val) \
2890{ \
2891 unsigned int res, new; \
2892 \
2893 res = read_##name(); \
2894 new = res & ~change; \
2895 new |= (val & change); \
2896 write_##name(new); \
2897 \
2898 return res; \
2899}
2900
2901/*
2902 * Manipulate bits in a c0 register.
2903 */
2904#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2905
2906__BUILD_SET_C0(status)
2907__BUILD_SET_C0(cause)
2908__BUILD_SET_C0(config)
2909__BUILD_SET_C0(config5)
2910__BUILD_SET_C0(config6)
2911__BUILD_SET_C0(config7)
2912__BUILD_SET_C0(diag)
2913__BUILD_SET_C0(intcontrol)
2914__BUILD_SET_C0(intctl)
2915__BUILD_SET_C0(srsmap)
2916__BUILD_SET_C0(pagegrain)
2917__BUILD_SET_C0(guestctl0)
2918__BUILD_SET_C0(guestctl0ext)
2919__BUILD_SET_C0(guestctl1)
2920__BUILD_SET_C0(guestctl2)
2921__BUILD_SET_C0(guestctl3)
2922__BUILD_SET_C0(brcm_config_0)
2923__BUILD_SET_C0(brcm_bus_pll)
2924__BUILD_SET_C0(brcm_reset)
2925__BUILD_SET_C0(brcm_cmt_intr)
2926__BUILD_SET_C0(brcm_cmt_ctrl)
2927__BUILD_SET_C0(brcm_config)
2928__BUILD_SET_C0(brcm_mode)
2929
2930/*
2931 * Manipulate bits in a guest c0 register.
2932 */
2933#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2934
2935__BUILD_SET_GC0(wired)
2936__BUILD_SET_GC0(status)
2937__BUILD_SET_GC0(cause)
2938__BUILD_SET_GC0(ebase)
2939__BUILD_SET_GC0(config1)
2940
2941/*
2942 * Return low 10 bits of ebase.
2943 * Note that under KVM (MIPSVZ) this returns vcpu id.
2944 */
2945static inline unsigned int get_ebase_cpunum(void)
2946{
2947 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2948}
2949
2950#endif /* !__ASSEMBLY__ */
2951
2952#endif /* _ASM_MIPSREGS_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/isa-rev.h>
20#include <asm/war.h>
21
22/*
23 * The following macros are especially useful for __asm__
24 * inline assembler.
25 */
26#ifndef __STR
27#define __STR(x) #x
28#endif
29#ifndef STR
30#define STR(x) __STR(x)
31#endif
32
33/*
34 * Configure language
35 */
36#ifdef __ASSEMBLY__
37#define _ULCAST_
38#define _U64CAST_
39#else
40#define _ULCAST_ (unsigned long)
41#define _U64CAST_ (u64)
42#endif
43
44/*
45 * Coprocessor 0 register names
46 */
47#define CP0_INDEX $0
48#define CP0_RANDOM $1
49#define CP0_ENTRYLO0 $2
50#define CP0_ENTRYLO1 $3
51#define CP0_CONF $3
52#define CP0_GLOBALNUMBER $3, 1
53#define CP0_CONTEXT $4
54#define CP0_PAGEMASK $5
55#define CP0_PAGEGRAIN $5, 1
56#define CP0_SEGCTL0 $5, 2
57#define CP0_SEGCTL1 $5, 3
58#define CP0_SEGCTL2 $5, 4
59#define CP0_WIRED $6
60#define CP0_INFO $7
61#define CP0_HWRENA $7
62#define CP0_BADVADDR $8
63#define CP0_BADINSTR $8, 1
64#define CP0_COUNT $9
65#define CP0_ENTRYHI $10
66#define CP0_GUESTCTL1 $10, 4
67#define CP0_GUESTCTL2 $10, 5
68#define CP0_GUESTCTL3 $10, 6
69#define CP0_COMPARE $11
70#define CP0_GUESTCTL0EXT $11, 4
71#define CP0_STATUS $12
72#define CP0_GUESTCTL0 $12, 6
73#define CP0_GTOFFSET $12, 7
74#define CP0_CAUSE $13
75#define CP0_EPC $14
76#define CP0_PRID $15
77#define CP0_EBASE $15, 1
78#define CP0_CMGCRBASE $15, 3
79#define CP0_CONFIG $16
80#define CP0_CONFIG3 $16, 3
81#define CP0_CONFIG5 $16, 5
82#define CP0_CONFIG6 $16, 6
83#define CP0_LLADDR $17
84#define CP0_WATCHLO $18
85#define CP0_WATCHHI $19
86#define CP0_XCONTEXT $20
87#define CP0_FRAMEMASK $21
88#define CP0_DIAGNOSTIC $22
89#define CP0_DEBUG $23
90#define CP0_DEPC $24
91#define CP0_PERFORMANCE $25
92#define CP0_ECC $26
93#define CP0_CACHEERR $27
94#define CP0_TAGLO $28
95#define CP0_TAGHI $29
96#define CP0_ERROREPC $30
97#define CP0_DESAVE $31
98
99/*
100 * R4640/R4650 cp0 register names. These registers are listed
101 * here only for completeness; without MMU these CPUs are not useable
102 * by Linux. A future ELKS port might take make Linux run on them
103 * though ...
104 */
105#define CP0_IBASE $0
106#define CP0_IBOUND $1
107#define CP0_DBASE $2
108#define CP0_DBOUND $3
109#define CP0_CALG $17
110#define CP0_IWATCH $18
111#define CP0_DWATCH $19
112
113/*
114 * Coprocessor 0 Set 1 register names
115 */
116#define CP0_S1_DERRADDR0 $26
117#define CP0_S1_DERRADDR1 $27
118#define CP0_S1_INTCONTROL $20
119
120/*
121 * Coprocessor 0 Set 2 register names
122 */
123#define CP0_S2_SRSCTL $12 /* MIPSR2 */
124
125/*
126 * Coprocessor 0 Set 3 register names
127 */
128#define CP0_S3_SRSMAP $12 /* MIPSR2 */
129
130/*
131 * TX39 Series
132 */
133#define CP0_TX39_CACHE $7
134
135
136/* Generic EntryLo bit definitions */
137#define ENTRYLO_G (_ULCAST_(1) << 0)
138#define ENTRYLO_V (_ULCAST_(1) << 1)
139#define ENTRYLO_D (_ULCAST_(1) << 2)
140#define ENTRYLO_C_SHIFT 3
141#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
142
143/* R3000 EntryLo bit definitions */
144#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
145#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
146#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
147#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
148
149/* MIPS32/64 EntryLo bit definitions */
150#define MIPS_ENTRYLO_PFN_SHIFT 6
151#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
152#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
153
154/*
155 * MIPSr6+ GlobalNumber register definitions
156 */
157#define MIPS_GLOBALNUMBER_VP_SHF 0
158#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
159#define MIPS_GLOBALNUMBER_CORE_SHF 8
160#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
161#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
162#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
163
164/*
165 * Values for PageMask register
166 */
167#ifdef CONFIG_CPU_VR41XX
168
169/* Why doesn't stupidity hurt ... */
170
171#define PM_1K 0x00000000
172#define PM_4K 0x00001800
173#define PM_16K 0x00007800
174#define PM_64K 0x0001f800
175#define PM_256K 0x0007f800
176
177#else
178
179#define PM_4K 0x00000000
180#define PM_8K 0x00002000
181#define PM_16K 0x00006000
182#define PM_32K 0x0000e000
183#define PM_64K 0x0001e000
184#define PM_128K 0x0003e000
185#define PM_256K 0x0007e000
186#define PM_512K 0x000fe000
187#define PM_1M 0x001fe000
188#define PM_2M 0x003fe000
189#define PM_4M 0x007fe000
190#define PM_8M 0x00ffe000
191#define PM_16M 0x01ffe000
192#define PM_32M 0x03ffe000
193#define PM_64M 0x07ffe000
194#define PM_256M 0x1fffe000
195#define PM_1G 0x7fffe000
196
197#endif
198
199/*
200 * Default page size for a given kernel configuration
201 */
202#ifdef CONFIG_PAGE_SIZE_4KB
203#define PM_DEFAULT_MASK PM_4K
204#elif defined(CONFIG_PAGE_SIZE_8KB)
205#define PM_DEFAULT_MASK PM_8K
206#elif defined(CONFIG_PAGE_SIZE_16KB)
207#define PM_DEFAULT_MASK PM_16K
208#elif defined(CONFIG_PAGE_SIZE_32KB)
209#define PM_DEFAULT_MASK PM_32K
210#elif defined(CONFIG_PAGE_SIZE_64KB)
211#define PM_DEFAULT_MASK PM_64K
212#else
213#error Bad page size configuration!
214#endif
215
216/*
217 * Default huge tlb size for a given kernel configuration
218 */
219#ifdef CONFIG_PAGE_SIZE_4KB
220#define PM_HUGE_MASK PM_1M
221#elif defined(CONFIG_PAGE_SIZE_8KB)
222#define PM_HUGE_MASK PM_4M
223#elif defined(CONFIG_PAGE_SIZE_16KB)
224#define PM_HUGE_MASK PM_16M
225#elif defined(CONFIG_PAGE_SIZE_32KB)
226#define PM_HUGE_MASK PM_64M
227#elif defined(CONFIG_PAGE_SIZE_64KB)
228#define PM_HUGE_MASK PM_256M
229#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
230#error Bad page size configuration for hugetlbfs!
231#endif
232
233/*
234 * Wired register bits
235 */
236#define MIPSR6_WIRED_LIMIT_SHIFT 16
237#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
238#define MIPSR6_WIRED_WIRED_SHIFT 0
239#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
240
241/*
242 * Values used for computation of new tlb entries
243 */
244#define PL_4K 12
245#define PL_16K 14
246#define PL_64K 16
247#define PL_256K 18
248#define PL_1M 20
249#define PL_4M 22
250#define PL_16M 24
251#define PL_64M 26
252#define PL_256M 28
253
254/*
255 * PageGrain bits
256 */
257#define PG_RIE (_ULCAST_(1) << 31)
258#define PG_XIE (_ULCAST_(1) << 30)
259#define PG_ELPA (_ULCAST_(1) << 29)
260#define PG_ESP (_ULCAST_(1) << 28)
261#define PG_IEC (_ULCAST_(1) << 27)
262
263/* MIPS32/64 EntryHI bit definitions */
264#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
265#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
266#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
267
268/*
269 * R4x00 interrupt enable / cause bits
270 */
271#define IE_SW0 (_ULCAST_(1) << 8)
272#define IE_SW1 (_ULCAST_(1) << 9)
273#define IE_IRQ0 (_ULCAST_(1) << 10)
274#define IE_IRQ1 (_ULCAST_(1) << 11)
275#define IE_IRQ2 (_ULCAST_(1) << 12)
276#define IE_IRQ3 (_ULCAST_(1) << 13)
277#define IE_IRQ4 (_ULCAST_(1) << 14)
278#define IE_IRQ5 (_ULCAST_(1) << 15)
279
280/*
281 * R4x00 interrupt cause bits
282 */
283#define C_SW0 (_ULCAST_(1) << 8)
284#define C_SW1 (_ULCAST_(1) << 9)
285#define C_IRQ0 (_ULCAST_(1) << 10)
286#define C_IRQ1 (_ULCAST_(1) << 11)
287#define C_IRQ2 (_ULCAST_(1) << 12)
288#define C_IRQ3 (_ULCAST_(1) << 13)
289#define C_IRQ4 (_ULCAST_(1) << 14)
290#define C_IRQ5 (_ULCAST_(1) << 15)
291
292/*
293 * Bitfields in the R4xx0 cp0 status register
294 */
295#define ST0_IE 0x00000001
296#define ST0_EXL 0x00000002
297#define ST0_ERL 0x00000004
298#define ST0_KSU 0x00000018
299# define KSU_USER 0x00000010
300# define KSU_SUPERVISOR 0x00000008
301# define KSU_KERNEL 0x00000000
302#define ST0_UX 0x00000020
303#define ST0_SX 0x00000040
304#define ST0_KX 0x00000080
305#define ST0_DE 0x00010000
306#define ST0_CE 0x00020000
307
308/*
309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
310 * cacheops in userspace. This bit exists only on RM7000 and RM9000
311 * processors.
312 */
313#define ST0_CO 0x08000000
314
315/*
316 * Bitfields in the R[23]000 cp0 status register.
317 */
318#define ST0_IEC 0x00000001
319#define ST0_KUC 0x00000002
320#define ST0_IEP 0x00000004
321#define ST0_KUP 0x00000008
322#define ST0_IEO 0x00000010
323#define ST0_KUO 0x00000020
324/* bits 6 & 7 are reserved on R[23]000 */
325#define ST0_ISC 0x00010000
326#define ST0_SWC 0x00020000
327#define ST0_CM 0x00080000
328
329/*
330 * Bits specific to the R4640/R4650
331 */
332#define ST0_UM (_ULCAST_(1) << 4)
333#define ST0_IL (_ULCAST_(1) << 23)
334#define ST0_DL (_ULCAST_(1) << 24)
335
336/*
337 * Enable the MIPS MDMX and DSP ASEs
338 */
339#define ST0_MX 0x01000000
340
341/*
342 * Status register bits available in all MIPS CPUs.
343 */
344#define ST0_IM 0x0000ff00
345#define STATUSB_IP0 8
346#define STATUSF_IP0 (_ULCAST_(1) << 8)
347#define STATUSB_IP1 9
348#define STATUSF_IP1 (_ULCAST_(1) << 9)
349#define STATUSB_IP2 10
350#define STATUSF_IP2 (_ULCAST_(1) << 10)
351#define STATUSB_IP3 11
352#define STATUSF_IP3 (_ULCAST_(1) << 11)
353#define STATUSB_IP4 12
354#define STATUSF_IP4 (_ULCAST_(1) << 12)
355#define STATUSB_IP5 13
356#define STATUSF_IP5 (_ULCAST_(1) << 13)
357#define STATUSB_IP6 14
358#define STATUSF_IP6 (_ULCAST_(1) << 14)
359#define STATUSB_IP7 15
360#define STATUSF_IP7 (_ULCAST_(1) << 15)
361#define STATUSB_IP8 0
362#define STATUSF_IP8 (_ULCAST_(1) << 0)
363#define STATUSB_IP9 1
364#define STATUSF_IP9 (_ULCAST_(1) << 1)
365#define STATUSB_IP10 2
366#define STATUSF_IP10 (_ULCAST_(1) << 2)
367#define STATUSB_IP11 3
368#define STATUSF_IP11 (_ULCAST_(1) << 3)
369#define STATUSB_IP12 4
370#define STATUSF_IP12 (_ULCAST_(1) << 4)
371#define STATUSB_IP13 5
372#define STATUSF_IP13 (_ULCAST_(1) << 5)
373#define STATUSB_IP14 6
374#define STATUSF_IP14 (_ULCAST_(1) << 6)
375#define STATUSB_IP15 7
376#define STATUSF_IP15 (_ULCAST_(1) << 7)
377#define ST0_CH 0x00040000
378#define ST0_NMI 0x00080000
379#define ST0_SR 0x00100000
380#define ST0_TS 0x00200000
381#define ST0_BEV 0x00400000
382#define ST0_RE 0x02000000
383#define ST0_FR 0x04000000
384#define ST0_CU 0xf0000000
385#define ST0_CU0 0x10000000
386#define ST0_CU1 0x20000000
387#define ST0_CU2 0x40000000
388#define ST0_CU3 0x80000000
389#define ST0_XX 0x80000000 /* MIPS IV naming */
390
391/*
392 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
393 */
394#define INTCTLB_IPFDC 23
395#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
396#define INTCTLB_IPPCI 26
397#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
398#define INTCTLB_IPTI 29
399#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
400
401/*
402 * Bitfields and bit numbers in the coprocessor 0 cause register.
403 *
404 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
405 */
406#define CAUSEB_EXCCODE 2
407#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
408#define CAUSEB_IP 8
409#define CAUSEF_IP (_ULCAST_(255) << 8)
410#define CAUSEB_IP0 8
411#define CAUSEF_IP0 (_ULCAST_(1) << 8)
412#define CAUSEB_IP1 9
413#define CAUSEF_IP1 (_ULCAST_(1) << 9)
414#define CAUSEB_IP2 10
415#define CAUSEF_IP2 (_ULCAST_(1) << 10)
416#define CAUSEB_IP3 11
417#define CAUSEF_IP3 (_ULCAST_(1) << 11)
418#define CAUSEB_IP4 12
419#define CAUSEF_IP4 (_ULCAST_(1) << 12)
420#define CAUSEB_IP5 13
421#define CAUSEF_IP5 (_ULCAST_(1) << 13)
422#define CAUSEB_IP6 14
423#define CAUSEF_IP6 (_ULCAST_(1) << 14)
424#define CAUSEB_IP7 15
425#define CAUSEF_IP7 (_ULCAST_(1) << 15)
426#define CAUSEB_FDCI 21
427#define CAUSEF_FDCI (_ULCAST_(1) << 21)
428#define CAUSEB_WP 22
429#define CAUSEF_WP (_ULCAST_(1) << 22)
430#define CAUSEB_IV 23
431#define CAUSEF_IV (_ULCAST_(1) << 23)
432#define CAUSEB_PCI 26
433#define CAUSEF_PCI (_ULCAST_(1) << 26)
434#define CAUSEB_DC 27
435#define CAUSEF_DC (_ULCAST_(1) << 27)
436#define CAUSEB_CE 28
437#define CAUSEF_CE (_ULCAST_(3) << 28)
438#define CAUSEB_TI 30
439#define CAUSEF_TI (_ULCAST_(1) << 30)
440#define CAUSEB_BD 31
441#define CAUSEF_BD (_ULCAST_(1) << 31)
442
443/*
444 * Cause.ExcCode trap codes.
445 */
446#define EXCCODE_INT 0 /* Interrupt pending */
447#define EXCCODE_MOD 1 /* TLB modified fault */
448#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
449#define EXCCODE_TLBS 3 /* TLB miss on a store */
450#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
451#define EXCCODE_ADES 5 /* Address error on a store */
452#define EXCCODE_IBE 6 /* Bus error on an ifetch */
453#define EXCCODE_DBE 7 /* Bus error on a load or store */
454#define EXCCODE_SYS 8 /* System call */
455#define EXCCODE_BP 9 /* Breakpoint */
456#define EXCCODE_RI 10 /* Reserved instruction exception */
457#define EXCCODE_CPU 11 /* Coprocessor unusable */
458#define EXCCODE_OV 12 /* Arithmetic overflow */
459#define EXCCODE_TR 13 /* Trap instruction */
460#define EXCCODE_MSAFPE 14 /* MSA floating point exception */
461#define EXCCODE_FPE 15 /* Floating point exception */
462#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
463#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
464#define EXCCODE_MSADIS 21 /* MSA disabled exception */
465#define EXCCODE_MDMX 22 /* MDMX unusable exception */
466#define EXCCODE_WATCH 23 /* Watch address reference */
467#define EXCCODE_MCHECK 24 /* Machine check */
468#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
469#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
470#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
471
472/* Implementation specific trap codes used by MIPS cores */
473#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
474
475/*
476 * Bits in the coprocessor 0 config register.
477 */
478/* Generic bits. */
479#define CONF_CM_CACHABLE_NO_WA 0
480#define CONF_CM_CACHABLE_WA 1
481#define CONF_CM_UNCACHED 2
482#define CONF_CM_CACHABLE_NONCOHERENT 3
483#define CONF_CM_CACHABLE_CE 4
484#define CONF_CM_CACHABLE_COW 5
485#define CONF_CM_CACHABLE_CUW 6
486#define CONF_CM_CACHABLE_ACCELERATED 7
487#define CONF_CM_CMASK 7
488#define CONF_BE (_ULCAST_(1) << 15)
489
490/* Bits common to various processors. */
491#define CONF_CU (_ULCAST_(1) << 3)
492#define CONF_DB (_ULCAST_(1) << 4)
493#define CONF_IB (_ULCAST_(1) << 5)
494#define CONF_DC (_ULCAST_(7) << 6)
495#define CONF_IC (_ULCAST_(7) << 9)
496#define CONF_EB (_ULCAST_(1) << 13)
497#define CONF_EM (_ULCAST_(1) << 14)
498#define CONF_SM (_ULCAST_(1) << 16)
499#define CONF_SC (_ULCAST_(1) << 17)
500#define CONF_EW (_ULCAST_(3) << 18)
501#define CONF_EP (_ULCAST_(15)<< 24)
502#define CONF_EC (_ULCAST_(7) << 28)
503#define CONF_CM (_ULCAST_(1) << 31)
504
505/* Bits specific to the R4xx0. */
506#define R4K_CONF_SW (_ULCAST_(1) << 20)
507#define R4K_CONF_SS (_ULCAST_(1) << 21)
508#define R4K_CONF_SB (_ULCAST_(3) << 22)
509
510/* Bits specific to the R5000. */
511#define R5K_CONF_SE (_ULCAST_(1) << 12)
512#define R5K_CONF_SS (_ULCAST_(3) << 20)
513
514/* Bits specific to the RM7000. */
515#define RM7K_CONF_SE (_ULCAST_(1) << 3)
516#define RM7K_CONF_TE (_ULCAST_(1) << 12)
517#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
518#define RM7K_CONF_TC (_ULCAST_(1) << 17)
519#define RM7K_CONF_SI (_ULCAST_(3) << 20)
520#define RM7K_CONF_SC (_ULCAST_(1) << 31)
521
522/* Bits specific to the R10000. */
523#define R10K_CONF_DN (_ULCAST_(3) << 3)
524#define R10K_CONF_CT (_ULCAST_(1) << 5)
525#define R10K_CONF_PE (_ULCAST_(1) << 6)
526#define R10K_CONF_PM (_ULCAST_(3) << 7)
527#define R10K_CONF_EC (_ULCAST_(15)<< 9)
528#define R10K_CONF_SB (_ULCAST_(1) << 13)
529#define R10K_CONF_SK (_ULCAST_(1) << 14)
530#define R10K_CONF_SS (_ULCAST_(7) << 16)
531#define R10K_CONF_SC (_ULCAST_(7) << 19)
532#define R10K_CONF_DC (_ULCAST_(7) << 26)
533#define R10K_CONF_IC (_ULCAST_(7) << 29)
534
535/* Bits specific to the VR41xx. */
536#define VR41_CONF_CS (_ULCAST_(1) << 12)
537#define VR41_CONF_P4K (_ULCAST_(1) << 13)
538#define VR41_CONF_BP (_ULCAST_(1) << 16)
539#define VR41_CONF_M16 (_ULCAST_(1) << 20)
540#define VR41_CONF_AD (_ULCAST_(1) << 23)
541
542/* Bits specific to the R30xx. */
543#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
544#define R30XX_CONF_REV (_ULCAST_(1) << 22)
545#define R30XX_CONF_AC (_ULCAST_(1) << 23)
546#define R30XX_CONF_RF (_ULCAST_(1) << 24)
547#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
548#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
549#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
550#define R30XX_CONF_SB (_ULCAST_(1) << 30)
551#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
552
553/* Bits specific to the TX49. */
554#define TX49_CONF_DC (_ULCAST_(1) << 16)
555#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
556#define TX49_CONF_HALT (_ULCAST_(1) << 18)
557#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
558
559/* Bits specific to the MIPS32/64 PRA. */
560#define MIPS_CONF_VI (_ULCAST_(1) << 3)
561#define MIPS_CONF_MT (_ULCAST_(7) << 7)
562#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
563#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
564#define MIPS_CONF_AR (_ULCAST_(7) << 10)
565#define MIPS_CONF_AT (_ULCAST_(3) << 13)
566#define MIPS_CONF_M (_ULCAST_(1) << 31)
567
568/*
569 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
570 */
571#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
572#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
573#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
574#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
575#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
576#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
577#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
578#define MIPS_CONF1_DA_SHF 7
579#define MIPS_CONF1_DA_SZ 3
580#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
581#define MIPS_CONF1_DL_SHF 10
582#define MIPS_CONF1_DL_SZ 3
583#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
584#define MIPS_CONF1_DS_SHF 13
585#define MIPS_CONF1_DS_SZ 3
586#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
587#define MIPS_CONF1_IA_SHF 16
588#define MIPS_CONF1_IA_SZ 3
589#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
590#define MIPS_CONF1_IL_SHF 19
591#define MIPS_CONF1_IL_SZ 3
592#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
593#define MIPS_CONF1_IS_SHF 22
594#define MIPS_CONF1_IS_SZ 3
595#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
596#define MIPS_CONF1_TLBS_SHIFT (25)
597#define MIPS_CONF1_TLBS_SIZE (6)
598#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
599
600#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
601#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
602#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
603#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
604#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
605#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
606#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
607#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
608
609#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
610#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
611#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
612#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
613#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
614#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
615#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
616#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
617#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
618#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
619#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
620#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
621#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
622#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
623#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
624#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
625#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
626#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
627#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
628#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
629#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
630#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
631#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
632#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
633#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
634#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
635#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
636
637#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
638#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
639#define MIPS_CONF4_FTLBSETS_SHIFT (0)
640#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
641#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
642#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
643#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
644/* bits 10:8 in FTLB-only configurations */
645#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
646/* bits 12:8 in VTLB-FTLB only configurations */
647#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
648#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
649#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
650#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
651#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
652#define MIPS_CONF4_KSCREXIST_SHIFT (16)
653#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
654#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
655#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
656#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
657#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
658#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
659
660#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
661#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
662#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
663#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
664#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
665#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
666#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
667#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
668#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
669#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
670#define MIPS_CONF5_MI (_ULCAST_(1) << 17)
671#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
672#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
673#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
674#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
675#define MIPS_CONF5_K (_ULCAST_(1) << 30)
676
677#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
678/* proAptiv FTLB on/off bit */
679#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
680/* Loongson-3 FTLB on/off bit */
681#define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
682/* FTLB probability bits */
683#define MIPS_CONF6_FTLBP_SHIFT (16)
684
685#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
686
687#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
688
689#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
690#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
691
692/* Ingenic Config7 bits */
693#define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
694
695/* Config7 Bits specific to MIPS Technologies. */
696
697/* Performance counters implemented Per TC */
698#define MTI_CONF7_PTC (_ULCAST_(1) << 19)
699
700/* WatchLo* register definitions */
701#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
702
703/* WatchHi* register definitions */
704#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
705#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
706#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
707#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
708#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
709#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
710#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
711#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
712#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
713#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
714#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
715#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
716#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
717
718/* PerfCnt control register definitions */
719#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
720#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
721#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
722#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
723#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
724#define MIPS_PERFCTRL_EVENT_S 5
725#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
726#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
727#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
728#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
729#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
730#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
731#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
732#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
733#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
734
735/* PerfCnt control register MT extensions used by MIPS cores */
736#define MIPS_PERFCTRL_VPEID_S 16
737#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
738#define MIPS_PERFCTRL_TCID_S 22
739#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
740#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
741#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
742#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
743#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
744
745/* PerfCnt control register MT extensions used by BMIPS5000 */
746#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
747
748/* PerfCnt control register MT extensions used by Netlogic XLR */
749#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
750
751/* MAAR bit definitions */
752#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
753#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
754#define MIPS_MAAR_ADDR_SHIFT 12
755#define MIPS_MAAR_S (_ULCAST_(1) << 1)
756#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
757
758/* MAARI bit definitions */
759#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
760
761/* EBase bit definitions */
762#define MIPS_EBASE_CPUNUM_SHIFT 0
763#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
764#define MIPS_EBASE_WG_SHIFT 11
765#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
766#define MIPS_EBASE_BASE_SHIFT 12
767#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
768
769/* CMGCRBase bit definitions */
770#define MIPS_CMGCRB_BASE 11
771#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
772
773/* LLAddr bit definitions */
774#define MIPS_LLADDR_LLB_SHIFT 0
775#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
776
777/*
778 * Bits in the MIPS32 Memory Segmentation registers.
779 */
780#define MIPS_SEGCFG_PA_SHIFT 9
781#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
782#define MIPS_SEGCFG_AM_SHIFT 4
783#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
784#define MIPS_SEGCFG_EU_SHIFT 3
785#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
786#define MIPS_SEGCFG_C_SHIFT 0
787#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
788
789#define MIPS_SEGCFG_UUSK _ULCAST_(7)
790#define MIPS_SEGCFG_USK _ULCAST_(5)
791#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
792#define MIPS_SEGCFG_MUSK _ULCAST_(3)
793#define MIPS_SEGCFG_MSK _ULCAST_(2)
794#define MIPS_SEGCFG_MK _ULCAST_(1)
795#define MIPS_SEGCFG_UK _ULCAST_(0)
796
797#define MIPS_PWFIELD_GDI_SHIFT 24
798#define MIPS_PWFIELD_GDI_MASK 0x3f000000
799#define MIPS_PWFIELD_UDI_SHIFT 18
800#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
801#define MIPS_PWFIELD_MDI_SHIFT 12
802#define MIPS_PWFIELD_MDI_MASK 0x0003f000
803#define MIPS_PWFIELD_PTI_SHIFT 6
804#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
805#define MIPS_PWFIELD_PTEI_SHIFT 0
806#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
807
808#define MIPS_PWSIZE_PS_SHIFT 30
809#define MIPS_PWSIZE_PS_MASK 0x40000000
810#define MIPS_PWSIZE_GDW_SHIFT 24
811#define MIPS_PWSIZE_GDW_MASK 0x3f000000
812#define MIPS_PWSIZE_UDW_SHIFT 18
813#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
814#define MIPS_PWSIZE_MDW_SHIFT 12
815#define MIPS_PWSIZE_MDW_MASK 0x0003f000
816#define MIPS_PWSIZE_PTW_SHIFT 6
817#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
818#define MIPS_PWSIZE_PTEW_SHIFT 0
819#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
820
821#define MIPS_PWCTL_PWEN_SHIFT 31
822#define MIPS_PWCTL_PWEN_MASK 0x80000000
823#define MIPS_PWCTL_XK_SHIFT 28
824#define MIPS_PWCTL_XK_MASK 0x10000000
825#define MIPS_PWCTL_XS_SHIFT 27
826#define MIPS_PWCTL_XS_MASK 0x08000000
827#define MIPS_PWCTL_XU_SHIFT 26
828#define MIPS_PWCTL_XU_MASK 0x04000000
829#define MIPS_PWCTL_DPH_SHIFT 7
830#define MIPS_PWCTL_DPH_MASK 0x00000080
831#define MIPS_PWCTL_HUGEPG_SHIFT 6
832#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
833#define MIPS_PWCTL_PSN_SHIFT 0
834#define MIPS_PWCTL_PSN_MASK 0x0000003f
835
836/* GuestCtl0 fields */
837#define MIPS_GCTL0_GM_SHIFT 31
838#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
839#define MIPS_GCTL0_RI_SHIFT 30
840#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
841#define MIPS_GCTL0_MC_SHIFT 29
842#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
843#define MIPS_GCTL0_CP0_SHIFT 28
844#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
845#define MIPS_GCTL0_AT_SHIFT 26
846#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
847#define MIPS_GCTL0_GT_SHIFT 25
848#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
849#define MIPS_GCTL0_CG_SHIFT 24
850#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
851#define MIPS_GCTL0_CF_SHIFT 23
852#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
853#define MIPS_GCTL0_G1_SHIFT 22
854#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
855#define MIPS_GCTL0_G0E_SHIFT 19
856#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
857#define MIPS_GCTL0_PT_SHIFT 18
858#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
859#define MIPS_GCTL0_RAD_SHIFT 9
860#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
861#define MIPS_GCTL0_DRG_SHIFT 8
862#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
863#define MIPS_GCTL0_G2_SHIFT 7
864#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
865#define MIPS_GCTL0_GEXC_SHIFT 2
866#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
867#define MIPS_GCTL0_SFC2_SHIFT 1
868#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
869#define MIPS_GCTL0_SFC1_SHIFT 0
870#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
871
872/* GuestCtl0.AT Guest address translation control */
873#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
874#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
875
876/* GuestCtl0.GExcCode Hypervisor exception cause codes */
877#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
878#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
879#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
880#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
881#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
882#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
883#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
884
885/* GuestCtl0Ext fields */
886#define MIPS_GCTL0EXT_RPW_SHIFT 8
887#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
888#define MIPS_GCTL0EXT_NCC_SHIFT 6
889#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
890#define MIPS_GCTL0EXT_CGI_SHIFT 4
891#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
892#define MIPS_GCTL0EXT_FCD_SHIFT 3
893#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
894#define MIPS_GCTL0EXT_OG_SHIFT 2
895#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
896#define MIPS_GCTL0EXT_BG_SHIFT 1
897#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
898#define MIPS_GCTL0EXT_MG_SHIFT 0
899#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
900
901/* GuestCtl0Ext.RPW Root page walk configuration */
902#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
903#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
904#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
905
906/* GuestCtl0Ext.NCC Nested cache coherency attributes */
907#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
908#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
909
910/* GuestCtl1 fields */
911#define MIPS_GCTL1_ID_SHIFT 0
912#define MIPS_GCTL1_ID_WIDTH 8
913#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
914#define MIPS_GCTL1_RID_SHIFT 16
915#define MIPS_GCTL1_RID_WIDTH 8
916#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
917#define MIPS_GCTL1_EID_SHIFT 24
918#define MIPS_GCTL1_EID_WIDTH 8
919#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
920
921/* GuestID reserved for root context */
922#define MIPS_GCTL1_ROOT_GUESTID 0
923
924/* CDMMBase register bit definitions */
925#define MIPS_CDMMBASE_SIZE_SHIFT 0
926#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
927#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
928#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
929#define MIPS_CDMMBASE_ADDR_SHIFT 11
930#define MIPS_CDMMBASE_ADDR_START 15
931
932/* RDHWR register numbers */
933#define MIPS_HWR_CPUNUM 0 /* CPU number */
934#define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
935#define MIPS_HWR_CC 2 /* Cycle counter */
936#define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
937#define MIPS_HWR_ULR 29 /* UserLocal */
938#define MIPS_HWR_IMPL1 30 /* Implementation dependent */
939#define MIPS_HWR_IMPL2 31 /* Implementation dependent */
940
941/* Bits in HWREna register */
942#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
943#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
944#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
945#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
946#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
947#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
948#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
949
950/*
951 * Bitfields in the TX39 family CP0 Configuration Register 3
952 */
953#define TX39_CONF_ICS_SHIFT 19
954#define TX39_CONF_ICS_MASK 0x00380000
955#define TX39_CONF_ICS_1KB 0x00000000
956#define TX39_CONF_ICS_2KB 0x00080000
957#define TX39_CONF_ICS_4KB 0x00100000
958#define TX39_CONF_ICS_8KB 0x00180000
959#define TX39_CONF_ICS_16KB 0x00200000
960
961#define TX39_CONF_DCS_SHIFT 16
962#define TX39_CONF_DCS_MASK 0x00070000
963#define TX39_CONF_DCS_1KB 0x00000000
964#define TX39_CONF_DCS_2KB 0x00010000
965#define TX39_CONF_DCS_4KB 0x00020000
966#define TX39_CONF_DCS_8KB 0x00030000
967#define TX39_CONF_DCS_16KB 0x00040000
968
969#define TX39_CONF_CWFON 0x00004000
970#define TX39_CONF_WBON 0x00002000
971#define TX39_CONF_RF_SHIFT 10
972#define TX39_CONF_RF_MASK 0x00000c00
973#define TX39_CONF_DOZE 0x00000200
974#define TX39_CONF_HALT 0x00000100
975#define TX39_CONF_LOCK 0x00000080
976#define TX39_CONF_ICE 0x00000020
977#define TX39_CONF_DCE 0x00000010
978#define TX39_CONF_IRSIZE_SHIFT 2
979#define TX39_CONF_IRSIZE_MASK 0x0000000c
980#define TX39_CONF_DRSIZE_SHIFT 0
981#define TX39_CONF_DRSIZE_MASK 0x00000003
982
983/*
984 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
985 */
986/* Disable Branch Target Address Cache */
987#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
988/* Enable Branch Prediction Global History */
989#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
990/* Disable Branch Return Cache */
991#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
992
993/* Flush ITLB */
994#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
995/* Flush DTLB */
996#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
997/* Flush VTLB */
998#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
999/* Flush FTLB */
1000#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
1001
1002/* CvmCtl register field definitions */
1003#define CVMCTL_IPPCI_SHIFT 7
1004#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1005#define CVMCTL_IPTI_SHIFT 4
1006#define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1007
1008/* CvmMemCtl2 register field definitions */
1009#define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1010
1011/* CvmVMConfig register field definitions */
1012#define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1013#define CVMVMCONF_MMUSIZEM1_S 12
1014#define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1015#define CVMVMCONF_RMMUSIZEM1_S 0
1016#define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1017
1018/*
1019 * Coprocessor 1 (FPU) register names
1020 */
1021#define CP1_REVISION $0
1022#define CP1_UFR $1
1023#define CP1_UNFR $4
1024#define CP1_FCCR $25
1025#define CP1_FEXR $26
1026#define CP1_FENR $28
1027#define CP1_STATUS $31
1028
1029
1030/*
1031 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1032 */
1033#define MIPS_FPIR_S (_ULCAST_(1) << 16)
1034#define MIPS_FPIR_D (_ULCAST_(1) << 17)
1035#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1036#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1037#define MIPS_FPIR_W (_ULCAST_(1) << 20)
1038#define MIPS_FPIR_L (_ULCAST_(1) << 21)
1039#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1040#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1041#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1042#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1043
1044/*
1045 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1046 */
1047#define MIPS_FCCR_CONDX_S 0
1048#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1049#define MIPS_FCCR_COND0_S 0
1050#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1051#define MIPS_FCCR_COND1_S 1
1052#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1053#define MIPS_FCCR_COND2_S 2
1054#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1055#define MIPS_FCCR_COND3_S 3
1056#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1057#define MIPS_FCCR_COND4_S 4
1058#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1059#define MIPS_FCCR_COND5_S 5
1060#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1061#define MIPS_FCCR_COND6_S 6
1062#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1063#define MIPS_FCCR_COND7_S 7
1064#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1065
1066/*
1067 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1068 */
1069#define MIPS_FENR_FS_S 2
1070#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1071
1072/*
1073 * FPU Status Register Values
1074 */
1075#define FPU_CSR_COND_S 23 /* $fcc0 */
1076#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1077
1078#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1079#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1080
1081#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1082#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1083#define FPU_CSR_COND1_S 25 /* $fcc1 */
1084#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1085#define FPU_CSR_COND2_S 26 /* $fcc2 */
1086#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1087#define FPU_CSR_COND3_S 27 /* $fcc3 */
1088#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1089#define FPU_CSR_COND4_S 28 /* $fcc4 */
1090#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1091#define FPU_CSR_COND5_S 29 /* $fcc5 */
1092#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1093#define FPU_CSR_COND6_S 30 /* $fcc6 */
1094#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1095#define FPU_CSR_COND7_S 31 /* $fcc7 */
1096#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1097
1098/*
1099 * Bits 22:20 of the FPU Status Register will be read as 0,
1100 * and should be written as zero.
1101 */
1102#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1103
1104#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1105#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1106
1107/*
1108 * X the exception cause indicator
1109 * E the exception enable
1110 * S the sticky/flag bit
1111*/
1112#define FPU_CSR_ALL_X 0x0003f000
1113#define FPU_CSR_UNI_X 0x00020000
1114#define FPU_CSR_INV_X 0x00010000
1115#define FPU_CSR_DIV_X 0x00008000
1116#define FPU_CSR_OVF_X 0x00004000
1117#define FPU_CSR_UDF_X 0x00002000
1118#define FPU_CSR_INE_X 0x00001000
1119
1120#define FPU_CSR_ALL_E 0x00000f80
1121#define FPU_CSR_INV_E 0x00000800
1122#define FPU_CSR_DIV_E 0x00000400
1123#define FPU_CSR_OVF_E 0x00000200
1124#define FPU_CSR_UDF_E 0x00000100
1125#define FPU_CSR_INE_E 0x00000080
1126
1127#define FPU_CSR_ALL_S 0x0000007c
1128#define FPU_CSR_INV_S 0x00000040
1129#define FPU_CSR_DIV_S 0x00000020
1130#define FPU_CSR_OVF_S 0x00000010
1131#define FPU_CSR_UDF_S 0x00000008
1132#define FPU_CSR_INE_S 0x00000004
1133
1134/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1135#define FPU_CSR_RM 0x00000003
1136#define FPU_CSR_RN 0x0 /* nearest */
1137#define FPU_CSR_RZ 0x1 /* towards zero */
1138#define FPU_CSR_RU 0x2 /* towards +Infinity */
1139#define FPU_CSR_RD 0x3 /* towards -Infinity */
1140
1141
1142#ifndef __ASSEMBLY__
1143
1144/*
1145 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1146 */
1147#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1148 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1149#define get_isa16_mode(x) ((x) & 0x1)
1150#define msk_isa16_mode(x) ((x) & ~0x1)
1151#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1152#else
1153#define get_isa16_mode(x) 0
1154#define msk_isa16_mode(x) (x)
1155#define set_isa16_mode(x) do { } while(0)
1156#endif
1157
1158/*
1159 * microMIPS instructions can be 16-bit or 32-bit in length. This
1160 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1161 */
1162static inline int mm_insn_16bit(u16 insn)
1163{
1164 u16 opcode = (insn >> 10) & 0x7;
1165
1166 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1167}
1168
1169/*
1170 * Helper macros for generating raw instruction encodings in inline asm.
1171 */
1172#ifdef CONFIG_CPU_MICROMIPS
1173#define _ASM_INSN16_IF_MM(_enc) \
1174 ".insn\n\t" \
1175 ".hword (" #_enc ")\n\t"
1176#define _ASM_INSN32_IF_MM(_enc) \
1177 ".insn\n\t" \
1178 ".hword ((" #_enc ") >> 16)\n\t" \
1179 ".hword ((" #_enc ") & 0xffff)\n\t"
1180#else
1181#define _ASM_INSN_IF_MIPS(_enc) \
1182 ".insn\n\t" \
1183 ".word (" #_enc ")\n\t"
1184#endif
1185
1186#ifndef _ASM_INSN16_IF_MM
1187#define _ASM_INSN16_IF_MM(_enc)
1188#endif
1189#ifndef _ASM_INSN32_IF_MM
1190#define _ASM_INSN32_IF_MM(_enc)
1191#endif
1192#ifndef _ASM_INSN_IF_MIPS
1193#define _ASM_INSN_IF_MIPS(_enc)
1194#endif
1195
1196/*
1197 * parse_r var, r - Helper assembler macro for parsing register names.
1198 *
1199 * This converts the register name in $n form provided in \r to the
1200 * corresponding register number, which is assigned to the variable \var. It is
1201 * needed to allow explicit encoding of instructions in inline assembly where
1202 * registers are chosen by the compiler in $n form, allowing us to avoid using
1203 * fixed register numbers.
1204 *
1205 * It also allows newer instructions (not implemented by the assembler) to be
1206 * transparently implemented using assembler macros, instead of needing separate
1207 * cases depending on toolchain support.
1208 *
1209 * Simple usage example:
1210 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1211 * ".insn\n\t"
1212 * "# di %0\n\t"
1213 * ".word (0x41606000 | (__rt << 16))"
1214 * : "=r" (status);
1215 */
1216
1217/* Match an individual register number and assign to \var */
1218#define _IFC_REG(n) \
1219 ".ifc \\r, $" #n "\n\t" \
1220 "\\var = " #n "\n\t" \
1221 ".endif\n\t"
1222
1223__asm__(".macro parse_r var r\n\t"
1224 "\\var = -1\n\t"
1225 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1226 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
1227 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
1228 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1229 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1230 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1231 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1232 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1233 ".iflt \\var\n\t"
1234 ".error \"Unable to parse register name \\r\"\n\t"
1235 ".endif\n\t"
1236 ".endm");
1237
1238#undef _IFC_REG
1239
1240/*
1241 * C macros for generating assembler macros for common instruction formats.
1242 *
1243 * The names of the operands can be chosen by the caller, and the encoding of
1244 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1245 * the ENC encodings.
1246 */
1247
1248/* Instructions with no operands */
1249#define _ASM_MACRO_0(OP, ENC) \
1250 __asm__(".macro " #OP "\n\t" \
1251 ENC \
1252 ".endm")
1253
1254/* Instructions with 1 register operand & 1 immediate operand */
1255#define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
1256 __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
1257 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1258 ENC \
1259 ".endm")
1260
1261/* Instructions with 2 register operands */
1262#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1263 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1264 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1265 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1266 ENC \
1267 ".endm")
1268
1269/* Instructions with 3 register operands */
1270#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1271 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1272 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1273 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1274 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1275 ENC \
1276 ".endm")
1277
1278/* Instructions with 2 register operands and 1 optional select operand */
1279#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1280 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1281 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1282 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1283 ENC \
1284 ".endm")
1285
1286/*
1287 * TLB Invalidate Flush
1288 */
1289static inline void tlbinvf(void)
1290{
1291 __asm__ __volatile__(
1292 ".set push\n\t"
1293 ".set noreorder\n\t"
1294 "# tlbinvf\n\t"
1295 _ASM_INSN_IF_MIPS(0x42000004)
1296 _ASM_INSN32_IF_MM(0x0000537c)
1297 ".set pop");
1298}
1299
1300
1301/*
1302 * Functions to access the R10000 performance counters. These are basically
1303 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1304 * performance counter number encoded into bits 1 ... 5 of the instruction.
1305 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1306 * disassembler these will look like an access to sel 0 or 1.
1307 */
1308#define read_r10k_perf_cntr(counter) \
1309({ \
1310 unsigned int __res; \
1311 __asm__ __volatile__( \
1312 "mfpc\t%0, %1" \
1313 : "=r" (__res) \
1314 : "i" (counter)); \
1315 \
1316 __res; \
1317})
1318
1319#define write_r10k_perf_cntr(counter,val) \
1320do { \
1321 __asm__ __volatile__( \
1322 "mtpc\t%0, %1" \
1323 : \
1324 : "r" (val), "i" (counter)); \
1325} while (0)
1326
1327#define read_r10k_perf_event(counter) \
1328({ \
1329 unsigned int __res; \
1330 __asm__ __volatile__( \
1331 "mfps\t%0, %1" \
1332 : "=r" (__res) \
1333 : "i" (counter)); \
1334 \
1335 __res; \
1336})
1337
1338#define write_r10k_perf_cntl(counter,val) \
1339do { \
1340 __asm__ __volatile__( \
1341 "mtps\t%0, %1" \
1342 : \
1343 : "r" (val), "i" (counter)); \
1344} while (0)
1345
1346
1347/*
1348 * Macros to access the system control coprocessor
1349 */
1350
1351#define ___read_32bit_c0_register(source, sel, vol) \
1352({ unsigned int __res; \
1353 if (sel == 0) \
1354 __asm__ vol( \
1355 "mfc0\t%0, " #source "\n\t" \
1356 : "=r" (__res)); \
1357 else \
1358 __asm__ vol( \
1359 ".set\tpush\n\t" \
1360 ".set\tmips32\n\t" \
1361 "mfc0\t%0, " #source ", " #sel "\n\t" \
1362 ".set\tpop\n\t" \
1363 : "=r" (__res)); \
1364 __res; \
1365})
1366
1367#define ___read_64bit_c0_register(source, sel, vol) \
1368({ unsigned long long __res; \
1369 if (sizeof(unsigned long) == 4) \
1370 __res = __read_64bit_c0_split(source, sel, vol); \
1371 else if (sel == 0) \
1372 __asm__ vol( \
1373 ".set\tpush\n\t" \
1374 ".set\tmips3\n\t" \
1375 "dmfc0\t%0, " #source "\n\t" \
1376 ".set\tpop" \
1377 : "=r" (__res)); \
1378 else \
1379 __asm__ vol( \
1380 ".set\tpush\n\t" \
1381 ".set\tmips64\n\t" \
1382 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1383 ".set\tpop" \
1384 : "=r" (__res)); \
1385 __res; \
1386})
1387
1388#define __read_32bit_c0_register(source, sel) \
1389 ___read_32bit_c0_register(source, sel, __volatile__)
1390
1391#define __read_const_32bit_c0_register(source, sel) \
1392 ___read_32bit_c0_register(source, sel,)
1393
1394#define __read_64bit_c0_register(source, sel) \
1395 ___read_64bit_c0_register(source, sel, __volatile__)
1396
1397#define __read_const_64bit_c0_register(source, sel) \
1398 ___read_64bit_c0_register(source, sel,)
1399
1400#define __write_32bit_c0_register(register, sel, value) \
1401do { \
1402 if (sel == 0) \
1403 __asm__ __volatile__( \
1404 "mtc0\t%z0, " #register "\n\t" \
1405 : : "Jr" ((unsigned int)(value))); \
1406 else \
1407 __asm__ __volatile__( \
1408 ".set\tpush\n\t" \
1409 ".set\tmips32\n\t" \
1410 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1411 ".set\tpop" \
1412 : : "Jr" ((unsigned int)(value))); \
1413} while (0)
1414
1415#define __write_64bit_c0_register(register, sel, value) \
1416do { \
1417 if (sizeof(unsigned long) == 4) \
1418 __write_64bit_c0_split(register, sel, value); \
1419 else if (sel == 0) \
1420 __asm__ __volatile__( \
1421 ".set\tpush\n\t" \
1422 ".set\tmips3\n\t" \
1423 "dmtc0\t%z0, " #register "\n\t" \
1424 ".set\tpop" \
1425 : : "Jr" (value)); \
1426 else \
1427 __asm__ __volatile__( \
1428 ".set\tpush\n\t" \
1429 ".set\tmips64\n\t" \
1430 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1431 ".set\tpop" \
1432 : : "Jr" (value)); \
1433} while (0)
1434
1435#define __read_ulong_c0_register(reg, sel) \
1436 ((sizeof(unsigned long) == 4) ? \
1437 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1438 (unsigned long) __read_64bit_c0_register(reg, sel))
1439
1440#define __read_const_ulong_c0_register(reg, sel) \
1441 ((sizeof(unsigned long) == 4) ? \
1442 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1443 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1444
1445#define __write_ulong_c0_register(reg, sel, val) \
1446do { \
1447 if (sizeof(unsigned long) == 4) \
1448 __write_32bit_c0_register(reg, sel, val); \
1449 else \
1450 __write_64bit_c0_register(reg, sel, val); \
1451} while (0)
1452
1453/*
1454 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1455 */
1456#define __read_32bit_c0_ctrl_register(source) \
1457({ unsigned int __res; \
1458 __asm__ __volatile__( \
1459 "cfc0\t%0, " #source "\n\t" \
1460 : "=r" (__res)); \
1461 __res; \
1462})
1463
1464#define __write_32bit_c0_ctrl_register(register, value) \
1465do { \
1466 __asm__ __volatile__( \
1467 "ctc0\t%z0, " #register "\n\t" \
1468 : : "Jr" ((unsigned int)(value))); \
1469} while (0)
1470
1471/*
1472 * These versions are only needed for systems with more than 38 bits of
1473 * physical address space running the 32-bit kernel. That's none atm :-)
1474 */
1475#define __read_64bit_c0_split(source, sel, vol) \
1476({ \
1477 unsigned long long __val; \
1478 unsigned long __flags; \
1479 \
1480 local_irq_save(__flags); \
1481 if (sel == 0) \
1482 __asm__ vol( \
1483 ".set\tpush\n\t" \
1484 ".set\tmips64\n\t" \
1485 "dmfc0\t%L0, " #source "\n\t" \
1486 "dsra\t%M0, %L0, 32\n\t" \
1487 "sll\t%L0, %L0, 0\n\t" \
1488 ".set\tpop" \
1489 : "=r" (__val)); \
1490 else \
1491 __asm__ vol( \
1492 ".set\tpush\n\t" \
1493 ".set\tmips64\n\t" \
1494 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1495 "dsra\t%M0, %L0, 32\n\t" \
1496 "sll\t%L0, %L0, 0\n\t" \
1497 ".set\tpop" \
1498 : "=r" (__val)); \
1499 local_irq_restore(__flags); \
1500 \
1501 __val; \
1502})
1503
1504#define __write_64bit_c0_split(source, sel, val) \
1505do { \
1506 unsigned long long __tmp = (val); \
1507 unsigned long __flags; \
1508 \
1509 local_irq_save(__flags); \
1510 if (MIPS_ISA_REV >= 2) \
1511 __asm__ __volatile__( \
1512 ".set\tpush\n\t" \
1513 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1514 "dins\t%L0, %M0, 32, 32\n\t" \
1515 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1516 ".set\tpop" \
1517 : "+r" (__tmp)); \
1518 else if (sel == 0) \
1519 __asm__ __volatile__( \
1520 ".set\tpush\n\t" \
1521 ".set\tmips64\n\t" \
1522 "dsll\t%L0, %L0, 32\n\t" \
1523 "dsrl\t%L0, %L0, 32\n\t" \
1524 "dsll\t%M0, %M0, 32\n\t" \
1525 "or\t%L0, %L0, %M0\n\t" \
1526 "dmtc0\t%L0, " #source "\n\t" \
1527 ".set\tpop" \
1528 : "+r" (__tmp)); \
1529 else \
1530 __asm__ __volatile__( \
1531 ".set\tpush\n\t" \
1532 ".set\tmips64\n\t" \
1533 "dsll\t%L0, %L0, 32\n\t" \
1534 "dsrl\t%L0, %L0, 32\n\t" \
1535 "dsll\t%M0, %M0, 32\n\t" \
1536 "or\t%L0, %L0, %M0\n\t" \
1537 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1538 ".set\tpop" \
1539 : "+r" (__tmp)); \
1540 local_irq_restore(__flags); \
1541} while (0)
1542
1543#ifndef TOOLCHAIN_SUPPORTS_XPA
1544_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1545 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1546 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1547_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1548 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1549 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1550#define _ASM_SET_XPA ""
1551#else /* !TOOLCHAIN_SUPPORTS_XPA */
1552#define _ASM_SET_XPA ".set\txpa\n\t"
1553#endif
1554
1555#define __readx_32bit_c0_register(source, sel) \
1556({ \
1557 unsigned int __res; \
1558 \
1559 __asm__ __volatile__( \
1560 " .set push \n" \
1561 " .set mips32r2 \n" \
1562 _ASM_SET_XPA \
1563 " mfhc0 %0, " #source ", %1 \n" \
1564 " .set pop \n" \
1565 : "=r" (__res) \
1566 : "i" (sel)); \
1567 __res; \
1568})
1569
1570#define __writex_32bit_c0_register(register, sel, value) \
1571do { \
1572 __asm__ __volatile__( \
1573 " .set push \n" \
1574 " .set mips32r2 \n" \
1575 _ASM_SET_XPA \
1576 " mthc0 %z0, " #register ", %1 \n" \
1577 " .set pop \n" \
1578 : \
1579 : "Jr" (value), "i" (sel)); \
1580} while (0)
1581
1582#define read_c0_index() __read_32bit_c0_register($0, 0)
1583#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1584
1585#define read_c0_random() __read_32bit_c0_register($1, 0)
1586#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1587
1588#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1589#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1590
1591#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1592#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1593
1594#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1595#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1596
1597#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1598#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1599
1600#define read_c0_conf() __read_32bit_c0_register($3, 0)
1601#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1602
1603#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1604
1605#define read_c0_context() __read_ulong_c0_register($4, 0)
1606#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1607
1608#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1609#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1610
1611#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1612#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1613
1614#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1615#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1616
1617#define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
1618#define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
1619
1620#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1621#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1622
1623#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1624#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1625
1626#define read_c0_wired() __read_32bit_c0_register($6, 0)
1627#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1628
1629#define read_c0_info() __read_32bit_c0_register($7, 0)
1630
1631#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1632#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1633
1634#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1635#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1636
1637#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1638#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1639
1640#define read_c0_count() __read_32bit_c0_register($9, 0)
1641#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1642
1643#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1644#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1645
1646#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1647#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1648
1649#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1650#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1651
1652#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1653#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1654
1655#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1656#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1657
1658#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1659#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1660
1661#define read_c0_compare() __read_32bit_c0_register($11, 0)
1662#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1663
1664#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1665#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1666
1667#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1668#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1669
1670#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1671#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1672
1673#define read_c0_status() __read_32bit_c0_register($12, 0)
1674
1675#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1676
1677#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1678#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1679
1680#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1681#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1682
1683#define read_c0_cause() __read_32bit_c0_register($13, 0)
1684#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1685
1686#define read_c0_epc() __read_ulong_c0_register($14, 0)
1687#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1688
1689#define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1690
1691#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1692
1693#define read_c0_config() __read_32bit_c0_register($16, 0)
1694#define read_c0_config1() __read_32bit_c0_register($16, 1)
1695#define read_c0_config2() __read_32bit_c0_register($16, 2)
1696#define read_c0_config3() __read_32bit_c0_register($16, 3)
1697#define read_c0_config4() __read_32bit_c0_register($16, 4)
1698#define read_c0_config5() __read_32bit_c0_register($16, 5)
1699#define read_c0_config6() __read_32bit_c0_register($16, 6)
1700#define read_c0_config7() __read_32bit_c0_register($16, 7)
1701#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1702#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1703#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1704#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1705#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1706#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1707#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1708#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1709
1710#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1711#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1712#define read_c0_maar() __read_ulong_c0_register($17, 1)
1713#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1714#define read_c0_maari() __read_32bit_c0_register($17, 2)
1715#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1716
1717/*
1718 * The WatchLo register. There may be up to 8 of them.
1719 */
1720#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1721#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1722#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1723#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1724#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1725#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1726#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1727#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1728#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1729#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1730#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1731#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1732#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1733#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1734#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1735#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1736
1737/*
1738 * The WatchHi register. There may be up to 8 of them.
1739 */
1740#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1741#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1742#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1743#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1744#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1745#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1746#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1747#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1748
1749#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1750#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1751#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1752#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1753#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1754#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1755#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1756#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1757
1758#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1759#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1760
1761#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1762#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1763
1764#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1765#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1766
1767#define read_c0_diag() __read_32bit_c0_register($22, 0)
1768#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1769
1770/* R10K CP0 Branch Diagnostic register is 64bits wide */
1771#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1772#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1773
1774#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1775#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1776
1777#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1778#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1779
1780#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1781#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1782
1783#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1784#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1785
1786#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1787#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1788
1789#define read_c0_debug() __read_32bit_c0_register($23, 0)
1790#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1791
1792#define read_c0_depc() __read_ulong_c0_register($24, 0)
1793#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1794
1795/*
1796 * MIPS32 / MIPS64 performance counters
1797 */
1798#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1799#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1800#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1801#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1802#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1803#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1804#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1805#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1806#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1807#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1808#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1809#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1810#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1811#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1812#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1813#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1814#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1815#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1816#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1817#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1818#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1819#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1820#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1821#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1822
1823#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1824#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1825
1826#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1827#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1828
1829#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1830
1831#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1832#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1833
1834#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1835#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1836
1837#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1838#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1839
1840#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1841#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1842
1843#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1844#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1845
1846#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1847#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1848
1849#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1850#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1851
1852/* MIPSR2 */
1853#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1854#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1855
1856#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1857#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1858
1859#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1860#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1861
1862#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1863#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1864
1865#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1866#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1867
1868#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1869#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1870
1871#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1872#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1873
1874/* MIPSR3 */
1875#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1876#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1877
1878#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1879#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1880
1881#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1882#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1883
1884/* Hardware Page Table Walker */
1885#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1886#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1887
1888#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1889#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1890
1891#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1892#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1893
1894#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1895#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1896
1897#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1898#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1899
1900#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1901#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1902
1903/* Cavium OCTEON (cnMIPS) */
1904#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1905#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1906
1907#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1908#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1909
1910#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1911#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1912
1913#define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1914#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1915
1916#define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1917#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1918
1919/*
1920 * The cacheerr registers are not standardized. On OCTEON, they are
1921 * 64 bits wide.
1922 */
1923#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1924#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1925
1926#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1927#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1928
1929/* BMIPS3300 */
1930#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1931#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1932
1933#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1934#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1935
1936#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1937#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1938
1939/* BMIPS43xx */
1940#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1941#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1942
1943#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1944#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1945
1946#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1947#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1948
1949#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1950#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1951
1952#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1953#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1954
1955/* BMIPS5000 */
1956#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1957#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1958
1959#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1960#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1961
1962#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1963#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1964
1965#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1966#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1967
1968#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1969#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1970
1971#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1972#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1973
1974/*
1975 * Macros to access the guest system control coprocessor
1976 */
1977
1978#ifndef TOOLCHAIN_SUPPORTS_VIRT
1979_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1980 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1981 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1982_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1983 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1984 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1985_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1986 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1987 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1988_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1989 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1990 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1991_ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
1992 _ASM_INSN32_IF_MM(0x0000017c));
1993_ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
1994 _ASM_INSN32_IF_MM(0x0000117c));
1995_ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
1996 _ASM_INSN32_IF_MM(0x0000217c));
1997_ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
1998 _ASM_INSN32_IF_MM(0x0000317c));
1999_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
2000 _ASM_INSN32_IF_MM(0x0000517c));
2001#define _ASM_SET_VIRT ""
2002#else /* !TOOLCHAIN_SUPPORTS_VIRT */
2003#define _ASM_SET_VIRT ".set\tvirt\n\t"
2004#endif
2005
2006#define __read_32bit_gc0_register(source, sel) \
2007({ int __res; \
2008 __asm__ __volatile__( \
2009 ".set\tpush\n\t" \
2010 ".set\tmips32r2\n\t" \
2011 _ASM_SET_VIRT \
2012 "mfgc0\t%0, " #source ", %1\n\t" \
2013 ".set\tpop" \
2014 : "=r" (__res) \
2015 : "i" (sel)); \
2016 __res; \
2017})
2018
2019#define __read_64bit_gc0_register(source, sel) \
2020({ unsigned long long __res; \
2021 __asm__ __volatile__( \
2022 ".set\tpush\n\t" \
2023 ".set\tmips64r2\n\t" \
2024 _ASM_SET_VIRT \
2025 "dmfgc0\t%0, " #source ", %1\n\t" \
2026 ".set\tpop" \
2027 : "=r" (__res) \
2028 : "i" (sel)); \
2029 __res; \
2030})
2031
2032#define __write_32bit_gc0_register(register, sel, value) \
2033do { \
2034 __asm__ __volatile__( \
2035 ".set\tpush\n\t" \
2036 ".set\tmips32r2\n\t" \
2037 _ASM_SET_VIRT \
2038 "mtgc0\t%z0, " #register ", %1\n\t" \
2039 ".set\tpop" \
2040 : : "Jr" ((unsigned int)(value)), \
2041 "i" (sel)); \
2042} while (0)
2043
2044#define __write_64bit_gc0_register(register, sel, value) \
2045do { \
2046 __asm__ __volatile__( \
2047 ".set\tpush\n\t" \
2048 ".set\tmips64r2\n\t" \
2049 _ASM_SET_VIRT \
2050 "dmtgc0\t%z0, " #register ", %1\n\t" \
2051 ".set\tpop" \
2052 : : "Jr" (value), \
2053 "i" (sel)); \
2054} while (0)
2055
2056#define __read_ulong_gc0_register(reg, sel) \
2057 ((sizeof(unsigned long) == 4) ? \
2058 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2059 (unsigned long) __read_64bit_gc0_register(reg, sel))
2060
2061#define __write_ulong_gc0_register(reg, sel, val) \
2062do { \
2063 if (sizeof(unsigned long) == 4) \
2064 __write_32bit_gc0_register(reg, sel, val); \
2065 else \
2066 __write_64bit_gc0_register(reg, sel, val); \
2067} while (0)
2068
2069#define read_gc0_index() __read_32bit_gc0_register($0, 0)
2070#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2071
2072#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2073#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2074
2075#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2076#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2077
2078#define read_gc0_context() __read_ulong_gc0_register($4, 0)
2079#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2080
2081#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2082#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2083
2084#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2085#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2086
2087#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2088#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2089
2090#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2091#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2092
2093#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2094#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2095
2096#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2097#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2098
2099#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2100#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2101
2102#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2103#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2104
2105#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2106#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2107
2108#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2109#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2110
2111#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2112#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2113
2114#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2115#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2116
2117#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2118#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2119
2120#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2121#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2122
2123#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2124#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2125
2126#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2127#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2128
2129#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2130#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2131
2132#define read_gc0_count() __read_32bit_gc0_register($9, 0)
2133
2134#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2135#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2136
2137#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2138#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2139
2140#define read_gc0_status() __read_32bit_gc0_register($12, 0)
2141#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2142
2143#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2144#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2145
2146#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2147#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2148
2149#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2150#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2151
2152#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2153
2154#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2155#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2156
2157#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2158#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2159
2160#define read_gc0_config() __read_32bit_gc0_register($16, 0)
2161#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2162#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2163#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2164#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2165#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2166#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2167#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2168#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2169#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2170#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2171#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2172#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2173#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2174#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2175#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2176
2177#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2178#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2179
2180#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2181#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2182#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2183#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2184#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2185#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2186#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2187#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2188#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2189#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2190#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2191#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2192#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2193#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2194#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2195#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2196
2197#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2198#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2199#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2200#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2201#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2202#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2203#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2204#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2205#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2206#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2207#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2208#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2209#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2210#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2211#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2212#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2213
2214#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2215#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2216
2217#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2218#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2219#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2220#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2221#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2222#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2223#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2224#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2225#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2226#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2227#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2228#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2229#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2230#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2231#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2232#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2233#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2234#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2235#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2236#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2237#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2238#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2239#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2240#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2241
2242#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2243#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2244
2245#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2246#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2247#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2248#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2249#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2250#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2251#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2252#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2253#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2254#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2255#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2256#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2257
2258/* Cavium OCTEON (cnMIPS) */
2259#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2260#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2261
2262#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2263#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2264
2265#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2266#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2267
2268#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2269#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2270
2271/*
2272 * Macros to access the floating point coprocessor control registers
2273 */
2274#define _read_32bit_cp1_register(source, gas_hardfloat) \
2275({ \
2276 unsigned int __res; \
2277 \
2278 __asm__ __volatile__( \
2279 " .set push \n" \
2280 " .set reorder \n" \
2281 " # gas fails to assemble cfc1 for some archs, \n" \
2282 " # like Octeon. \n" \
2283 " .set mips1 \n" \
2284 " "STR(gas_hardfloat)" \n" \
2285 " cfc1 %0,"STR(source)" \n" \
2286 " .set pop \n" \
2287 : "=r" (__res)); \
2288 __res; \
2289})
2290
2291#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2292do { \
2293 __asm__ __volatile__( \
2294 " .set push \n" \
2295 " .set reorder \n" \
2296 " "STR(gas_hardfloat)" \n" \
2297 " ctc1 %0,"STR(dest)" \n" \
2298 " .set pop \n" \
2299 : : "r" (val)); \
2300} while (0)
2301
2302#ifdef GAS_HAS_SET_HARDFLOAT
2303#define read_32bit_cp1_register(source) \
2304 _read_32bit_cp1_register(source, .set hardfloat)
2305#define write_32bit_cp1_register(dest, val) \
2306 _write_32bit_cp1_register(dest, val, .set hardfloat)
2307#else
2308#define read_32bit_cp1_register(source) \
2309 _read_32bit_cp1_register(source, )
2310#define write_32bit_cp1_register(dest, val) \
2311 _write_32bit_cp1_register(dest, val, )
2312#endif
2313
2314#ifdef TOOLCHAIN_SUPPORTS_DSP
2315#define rddsp(mask) \
2316({ \
2317 unsigned int __dspctl; \
2318 \
2319 __asm__ __volatile__( \
2320 " .set push \n" \
2321 " .set " MIPS_ISA_LEVEL " \n" \
2322 " .set dsp \n" \
2323 " rddsp %0, %x1 \n" \
2324 " .set pop \n" \
2325 : "=r" (__dspctl) \
2326 : "i" (mask)); \
2327 __dspctl; \
2328})
2329
2330#define wrdsp(val, mask) \
2331do { \
2332 __asm__ __volatile__( \
2333 " .set push \n" \
2334 " .set " MIPS_ISA_LEVEL " \n" \
2335 " .set dsp \n" \
2336 " wrdsp %0, %x1 \n" \
2337 " .set pop \n" \
2338 : \
2339 : "r" (val), "i" (mask)); \
2340} while (0)
2341
2342#define mflo0() \
2343({ \
2344 long mflo0; \
2345 __asm__( \
2346 " .set push \n" \
2347 " .set " MIPS_ISA_LEVEL " \n" \
2348 " .set dsp \n" \
2349 " mflo %0, $ac0 \n" \
2350 " .set pop \n" \
2351 : "=r" (mflo0)); \
2352 mflo0; \
2353})
2354
2355#define mflo1() \
2356({ \
2357 long mflo1; \
2358 __asm__( \
2359 " .set push \n" \
2360 " .set " MIPS_ISA_LEVEL " \n" \
2361 " .set dsp \n" \
2362 " mflo %0, $ac1 \n" \
2363 " .set pop \n" \
2364 : "=r" (mflo1)); \
2365 mflo1; \
2366})
2367
2368#define mflo2() \
2369({ \
2370 long mflo2; \
2371 __asm__( \
2372 " .set push \n" \
2373 " .set " MIPS_ISA_LEVEL " \n" \
2374 " .set dsp \n" \
2375 " mflo %0, $ac2 \n" \
2376 " .set pop \n" \
2377 : "=r" (mflo2)); \
2378 mflo2; \
2379})
2380
2381#define mflo3() \
2382({ \
2383 long mflo3; \
2384 __asm__( \
2385 " .set push \n" \
2386 " .set " MIPS_ISA_LEVEL " \n" \
2387 " .set dsp \n" \
2388 " mflo %0, $ac3 \n" \
2389 " .set pop \n" \
2390 : "=r" (mflo3)); \
2391 mflo3; \
2392})
2393
2394#define mfhi0() \
2395({ \
2396 long mfhi0; \
2397 __asm__( \
2398 " .set push \n" \
2399 " .set " MIPS_ISA_LEVEL " \n" \
2400 " .set dsp \n" \
2401 " mfhi %0, $ac0 \n" \
2402 " .set pop \n" \
2403 : "=r" (mfhi0)); \
2404 mfhi0; \
2405})
2406
2407#define mfhi1() \
2408({ \
2409 long mfhi1; \
2410 __asm__( \
2411 " .set push \n" \
2412 " .set " MIPS_ISA_LEVEL " \n" \
2413 " .set dsp \n" \
2414 " mfhi %0, $ac1 \n" \
2415 " .set pop \n" \
2416 : "=r" (mfhi1)); \
2417 mfhi1; \
2418})
2419
2420#define mfhi2() \
2421({ \
2422 long mfhi2; \
2423 __asm__( \
2424 " .set push \n" \
2425 " .set " MIPS_ISA_LEVEL " \n" \
2426 " .set dsp \n" \
2427 " mfhi %0, $ac2 \n" \
2428 " .set pop \n" \
2429 : "=r" (mfhi2)); \
2430 mfhi2; \
2431})
2432
2433#define mfhi3() \
2434({ \
2435 long mfhi3; \
2436 __asm__( \
2437 " .set push \n" \
2438 " .set " MIPS_ISA_LEVEL " \n" \
2439 " .set dsp \n" \
2440 " mfhi %0, $ac3 \n" \
2441 " .set pop \n" \
2442 : "=r" (mfhi3)); \
2443 mfhi3; \
2444})
2445
2446
2447#define mtlo0(x) \
2448({ \
2449 __asm__( \
2450 " .set push \n" \
2451 " .set " MIPS_ISA_LEVEL " \n" \
2452 " .set dsp \n" \
2453 " mtlo %0, $ac0 \n" \
2454 " .set pop \n" \
2455 : \
2456 : "r" (x)); \
2457})
2458
2459#define mtlo1(x) \
2460({ \
2461 __asm__( \
2462 " .set push \n" \
2463 " .set " MIPS_ISA_LEVEL " \n" \
2464 " .set dsp \n" \
2465 " mtlo %0, $ac1 \n" \
2466 " .set pop \n" \
2467 : \
2468 : "r" (x)); \
2469})
2470
2471#define mtlo2(x) \
2472({ \
2473 __asm__( \
2474 " .set push \n" \
2475 " .set " MIPS_ISA_LEVEL " \n" \
2476 " .set dsp \n" \
2477 " mtlo %0, $ac2 \n" \
2478 " .set pop \n" \
2479 : \
2480 : "r" (x)); \
2481})
2482
2483#define mtlo3(x) \
2484({ \
2485 __asm__( \
2486 " .set push \n" \
2487 " .set " MIPS_ISA_LEVEL " \n" \
2488 " .set dsp \n" \
2489 " mtlo %0, $ac3 \n" \
2490 " .set pop \n" \
2491 : \
2492 : "r" (x)); \
2493})
2494
2495#define mthi0(x) \
2496({ \
2497 __asm__( \
2498 " .set push \n" \
2499 " .set " MIPS_ISA_LEVEL " \n" \
2500 " .set dsp \n" \
2501 " mthi %0, $ac0 \n" \
2502 " .set pop \n" \
2503 : \
2504 : "r" (x)); \
2505})
2506
2507#define mthi1(x) \
2508({ \
2509 __asm__( \
2510 " .set push \n" \
2511 " .set " MIPS_ISA_LEVEL " \n" \
2512 " .set dsp \n" \
2513 " mthi %0, $ac1 \n" \
2514 " .set pop \n" \
2515 : \
2516 : "r" (x)); \
2517})
2518
2519#define mthi2(x) \
2520({ \
2521 __asm__( \
2522 " .set push \n" \
2523 " .set " MIPS_ISA_LEVEL " \n" \
2524 " .set dsp \n" \
2525 " mthi %0, $ac2 \n" \
2526 " .set pop \n" \
2527 : \
2528 : "r" (x)); \
2529})
2530
2531#define mthi3(x) \
2532({ \
2533 __asm__( \
2534 " .set push \n" \
2535 " .set " MIPS_ISA_LEVEL " \n" \
2536 " .set dsp \n" \
2537 " mthi %0, $ac3 \n" \
2538 " .set pop \n" \
2539 : \
2540 : "r" (x)); \
2541})
2542
2543#else
2544
2545#define rddsp(mask) \
2546({ \
2547 unsigned int __res; \
2548 \
2549 __asm__ __volatile__( \
2550 " .set push \n" \
2551 " .set noat \n" \
2552 " # rddsp $1, %x1 \n" \
2553 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2554 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2555 " move %0, $1 \n" \
2556 " .set pop \n" \
2557 : "=r" (__res) \
2558 : "i" (mask)); \
2559 __res; \
2560})
2561
2562#define wrdsp(val, mask) \
2563do { \
2564 __asm__ __volatile__( \
2565 " .set push \n" \
2566 " .set noat \n" \
2567 " move $1, %0 \n" \
2568 " # wrdsp $1, %x1 \n" \
2569 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2570 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2571 " .set pop \n" \
2572 : \
2573 : "r" (val), "i" (mask)); \
2574} while (0)
2575
2576#define _dsp_mfxxx(ins) \
2577({ \
2578 unsigned long __treg; \
2579 \
2580 __asm__ __volatile__( \
2581 " .set push \n" \
2582 " .set noat \n" \
2583 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2584 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2585 " move %0, $1 \n" \
2586 " .set pop \n" \
2587 : "=r" (__treg) \
2588 : "i" (ins)); \
2589 __treg; \
2590})
2591
2592#define _dsp_mtxxx(val, ins) \
2593do { \
2594 __asm__ __volatile__( \
2595 " .set push \n" \
2596 " .set noat \n" \
2597 " move $1, %0 \n" \
2598 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2599 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2600 " .set pop \n" \
2601 : \
2602 : "r" (val), "i" (ins)); \
2603} while (0)
2604
2605#ifdef CONFIG_CPU_MICROMIPS
2606
2607#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2608#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2609
2610#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2611#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2612
2613#else /* !CONFIG_CPU_MICROMIPS */
2614
2615#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2616#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2617
2618#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2619#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2620
2621#endif /* CONFIG_CPU_MICROMIPS */
2622
2623#define mflo0() _dsp_mflo(0)
2624#define mflo1() _dsp_mflo(1)
2625#define mflo2() _dsp_mflo(2)
2626#define mflo3() _dsp_mflo(3)
2627
2628#define mfhi0() _dsp_mfhi(0)
2629#define mfhi1() _dsp_mfhi(1)
2630#define mfhi2() _dsp_mfhi(2)
2631#define mfhi3() _dsp_mfhi(3)
2632
2633#define mtlo0(x) _dsp_mtlo(x, 0)
2634#define mtlo1(x) _dsp_mtlo(x, 1)
2635#define mtlo2(x) _dsp_mtlo(x, 2)
2636#define mtlo3(x) _dsp_mtlo(x, 3)
2637
2638#define mthi0(x) _dsp_mthi(x, 0)
2639#define mthi1(x) _dsp_mthi(x, 1)
2640#define mthi2(x) _dsp_mthi(x, 2)
2641#define mthi3(x) _dsp_mthi(x, 3)
2642
2643#endif
2644
2645/*
2646 * TLB operations.
2647 *
2648 * It is responsibility of the caller to take care of any TLB hazards.
2649 */
2650static inline void tlb_probe(void)
2651{
2652 __asm__ __volatile__(
2653 ".set noreorder\n\t"
2654 "tlbp\n\t"
2655 ".set reorder");
2656}
2657
2658static inline void tlb_read(void)
2659{
2660#if MIPS34K_MISSED_ITLB_WAR
2661 int res = 0;
2662
2663 __asm__ __volatile__(
2664 " .set push \n"
2665 " .set noreorder \n"
2666 " .set noat \n"
2667 " .set mips32r2 \n"
2668 " .word 0x41610001 # dvpe $1 \n"
2669 " move %0, $1 \n"
2670 " ehb \n"
2671 " .set pop \n"
2672 : "=r" (res));
2673
2674 instruction_hazard();
2675#endif
2676
2677 __asm__ __volatile__(
2678 ".set noreorder\n\t"
2679 "tlbr\n\t"
2680 ".set reorder");
2681
2682#if MIPS34K_MISSED_ITLB_WAR
2683 if ((res & _ULCAST_(1)))
2684 __asm__ __volatile__(
2685 " .set push \n"
2686 " .set noreorder \n"
2687 " .set noat \n"
2688 " .set mips32r2 \n"
2689 " .word 0x41600021 # evpe \n"
2690 " ehb \n"
2691 " .set pop \n");
2692#endif
2693}
2694
2695static inline void tlb_write_indexed(void)
2696{
2697 __asm__ __volatile__(
2698 ".set noreorder\n\t"
2699 "tlbwi\n\t"
2700 ".set reorder");
2701}
2702
2703static inline void tlb_write_random(void)
2704{
2705 __asm__ __volatile__(
2706 ".set noreorder\n\t"
2707 "tlbwr\n\t"
2708 ".set reorder");
2709}
2710
2711/*
2712 * Guest TLB operations.
2713 *
2714 * It is responsibility of the caller to take care of any TLB hazards.
2715 */
2716static inline void guest_tlb_probe(void)
2717{
2718 __asm__ __volatile__(
2719 ".set push\n\t"
2720 ".set noreorder\n\t"
2721 _ASM_SET_VIRT
2722 "tlbgp\n\t"
2723 ".set pop");
2724}
2725
2726static inline void guest_tlb_read(void)
2727{
2728 __asm__ __volatile__(
2729 ".set push\n\t"
2730 ".set noreorder\n\t"
2731 _ASM_SET_VIRT
2732 "tlbgr\n\t"
2733 ".set pop");
2734}
2735
2736static inline void guest_tlb_write_indexed(void)
2737{
2738 __asm__ __volatile__(
2739 ".set push\n\t"
2740 ".set noreorder\n\t"
2741 _ASM_SET_VIRT
2742 "tlbgwi\n\t"
2743 ".set pop");
2744}
2745
2746static inline void guest_tlb_write_random(void)
2747{
2748 __asm__ __volatile__(
2749 ".set push\n\t"
2750 ".set noreorder\n\t"
2751 _ASM_SET_VIRT
2752 "tlbgwr\n\t"
2753 ".set pop");
2754}
2755
2756/*
2757 * Guest TLB Invalidate Flush
2758 */
2759static inline void guest_tlbinvf(void)
2760{
2761 __asm__ __volatile__(
2762 ".set push\n\t"
2763 ".set noreorder\n\t"
2764 _ASM_SET_VIRT
2765 "tlbginvf\n\t"
2766 ".set pop");
2767}
2768
2769/*
2770 * Manipulate bits in a register.
2771 */
2772#define __BUILD_SET_COMMON(name) \
2773static inline unsigned int \
2774set_##name(unsigned int set) \
2775{ \
2776 unsigned int res, new; \
2777 \
2778 res = read_##name(); \
2779 new = res | set; \
2780 write_##name(new); \
2781 \
2782 return res; \
2783} \
2784 \
2785static inline unsigned int \
2786clear_##name(unsigned int clear) \
2787{ \
2788 unsigned int res, new; \
2789 \
2790 res = read_##name(); \
2791 new = res & ~clear; \
2792 write_##name(new); \
2793 \
2794 return res; \
2795} \
2796 \
2797static inline unsigned int \
2798change_##name(unsigned int change, unsigned int val) \
2799{ \
2800 unsigned int res, new; \
2801 \
2802 res = read_##name(); \
2803 new = res & ~change; \
2804 new |= (val & change); \
2805 write_##name(new); \
2806 \
2807 return res; \
2808}
2809
2810/*
2811 * Manipulate bits in a c0 register.
2812 */
2813#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2814
2815__BUILD_SET_C0(status)
2816__BUILD_SET_C0(cause)
2817__BUILD_SET_C0(config)
2818__BUILD_SET_C0(config5)
2819__BUILD_SET_C0(config7)
2820__BUILD_SET_C0(intcontrol)
2821__BUILD_SET_C0(intctl)
2822__BUILD_SET_C0(srsmap)
2823__BUILD_SET_C0(pagegrain)
2824__BUILD_SET_C0(guestctl0)
2825__BUILD_SET_C0(guestctl0ext)
2826__BUILD_SET_C0(guestctl1)
2827__BUILD_SET_C0(guestctl2)
2828__BUILD_SET_C0(guestctl3)
2829__BUILD_SET_C0(brcm_config_0)
2830__BUILD_SET_C0(brcm_bus_pll)
2831__BUILD_SET_C0(brcm_reset)
2832__BUILD_SET_C0(brcm_cmt_intr)
2833__BUILD_SET_C0(brcm_cmt_ctrl)
2834__BUILD_SET_C0(brcm_config)
2835__BUILD_SET_C0(brcm_mode)
2836
2837/*
2838 * Manipulate bits in a guest c0 register.
2839 */
2840#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2841
2842__BUILD_SET_GC0(wired)
2843__BUILD_SET_GC0(status)
2844__BUILD_SET_GC0(cause)
2845__BUILD_SET_GC0(ebase)
2846__BUILD_SET_GC0(config1)
2847
2848/*
2849 * Return low 10 bits of ebase.
2850 * Note that under KVM (MIPSVZ) this returns vcpu id.
2851 */
2852static inline unsigned int get_ebase_cpunum(void)
2853{
2854 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2855}
2856
2857#endif /* !__ASSEMBLY__ */
2858
2859#endif /* _ASM_MIPSREGS_H */